From 3116a412a3c36481ed8ca32992e1637726e71233 Mon Sep 17 00:00:00 2001 From: Ludwig Maier Date: Thu, 13 Feb 2014 20:38:17 +0100 Subject: [PATCH] nxyter update, not working --- nxyter/cores/adc_ddr_generic.ipx | 8 +- nxyter/cores/adc_ddr_generic.lpc | 6 +- nxyter/cores/adc_ddr_generic.vhd | 8 +- nxyter/source/nx_event_buffer.vhd | 18 +-- nxyter/source/nx_histograms.vhd | 138 +++++++++--------- nxyter/source/nx_i2c_readbyte.vhd | 20 +-- nxyter/source/nx_setup.vhd | 196 ++++++++++++++++++++++---- nxyter/source/nx_trigger_handler.vhd | 89 +++++++++--- nxyter/source/nx_trigger_validate.vhd | 37 +++-- nxyter/source/nxyter_components.vhd | 41 +++++- nxyter/source/nxyter_fee_board.vhd | 73 ++++++++-- nxyter/source/registers.txt | 3 +- nxyter/trb3_periph.prj | 1 + 13 files changed, 461 insertions(+), 177 deletions(-) diff --git a/nxyter/cores/adc_ddr_generic.ipx b/nxyter/cores/adc_ddr_generic.ipx index ab6da25..5a96ed7 100644 --- a/nxyter/cores/adc_ddr_generic.ipx +++ b/nxyter/cores/adc_ddr_generic.ipx @@ -1,8 +1,8 @@ - + - - - + + + diff --git a/nxyter/cores/adc_ddr_generic.lpc b/nxyter/cores/adc_ddr_generic.lpc index ee4d7ad..e908583 100644 --- a/nxyter/cores/adc_ddr_generic.lpc +++ b/nxyter/cores/adc_ddr_generic.lpc @@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation CoreType=LPM CoreStatus=Demo CoreName=DDR_GENERIC -CoreRevision=5.3 +CoreRevision=5.4 ModuleName=adc_ddr_generic SourceFormat=VHDL ParameterFileVersion=1.0 -Date=11/23/2013 -Time=14:55:41 +Date=02/04/2014 +Time=14:33:08 [Parameters] Verilog=0 diff --git a/nxyter/cores/adc_ddr_generic.vhd b/nxyter/cores/adc_ddr_generic.vhd index 95a90c2..804a4ba 100644 --- a/nxyter/cores/adc_ddr_generic.vhd +++ b/nxyter/cores/adc_ddr_generic.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) --- Module Version: 5.3 ---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -n adc_ddr_generic -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 187.5 -gear 2 -clk dqs -dqs 1 5 -dqs 2 5 -e +-- VHDL netlist generated by SCUBA Diamond_3.0_Production (94) +-- Module Version: 5.4 +--/usr/local/opt/lattice_diamond/diamond/3.0/ispfpga/bin/lin64/scuba -w -n adc_ddr_generic -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 187.5 -gear 2 -clk dqs -dqs 1 5 -dqs 2 5 -e --- Sat Nov 23 14:55:41 2013 +-- Tue Feb 4 14:33:08 2014 library IEEE; use IEEE.std_logic_1164.all; diff --git a/nxyter/source/nx_event_buffer.vhd b/nxyter/source/nx_event_buffer.vhd index b61f679..0bd2321 100644 --- a/nxyter/source/nx_event_buffer.vhd +++ b/nxyter/source/nx_event_buffer.vhd @@ -21,8 +21,8 @@ entity nx_event_buffer is DATA_CLK_IN : in std_logic; EVT_NOMORE_DATA_IN : in std_logic; - -- LVL2 Trigger - LVL2_TRIGGER_IN : in std_logic; + -- Trigger + TRIGGER_IN : in std_logic; FAST_CLEAR_IN : in std_logic; TRIGGER_BUSY_OUT : out std_logic; EVT_BUFFER_FULL_OUT : out std_logic; @@ -30,7 +30,6 @@ entity nx_event_buffer is --Response from FEE FEE_DATA_OUT : out std_logic_vector(31 downto 0); FEE_DATA_WRITE_OUT : out std_logic; - FEE_DATA_FINISHED_OUT : out std_logic; FEE_DATA_ALMOST_FULL_IN : in std_logic; -- Slave bus @@ -53,7 +52,6 @@ architecture Behavioral of nx_event_buffer is --Data channel signal fee_data_o : std_logic_vector(31 downto 0); signal fee_data_write_o : std_logic; - signal fee_data_finished_o : std_logic; signal trigger_busy_o : std_logic; signal evt_data_flush : std_logic; @@ -134,13 +132,13 @@ begin DEBUG_OUT(3) <= fifo_almost_full; DEBUG_OUT(4) <= RESET_DATA_BUFFER_IN; DEBUG_OUT(5) <= trigger_busy_o; - DEBUG_OUT(6) <= LVL2_TRIGGER_IN; + DEBUG_OUT(6) <= TRIGGER_IN; DEBUG_OUT(7) <= evt_data_flush; DEBUG_OUT(8) <= flush_end_enable; DEBUG_OUT(9) <= evt_data_clk; DEBUG_OUT(10) <= fee_data_write_o; DEBUG_OUT(11) <= evt_data_flushed; - DEBUG_OUT(12) <= fee_data_finished_o; + DEBUG_OUT(12) <= '0'; DEBUG_OUT(13) <= EVT_NOMORE_DATA_IN; DEBUG_OUT(14) <= FAST_CLEAR_IN; DEBUG_OUT(15) <= FEE_DATA_ALMOST_FULL_IN; @@ -154,25 +152,21 @@ begin if( rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then evt_data_flush <= '0'; - fee_data_finished_o <= '0'; trigger_busy_o <= '0'; STATE <= S_IDLE; else evt_data_flush <= '0'; - fee_data_finished_o <= '0'; trigger_busy_o <= '1'; if (FAST_CLEAR_IN = '1') then - fee_data_finished_o <= '1'; STATE <= S_IDLE; else case STATE is when S_IDLE => if (NXYTER_OFFLINE_IN = '1') then - fee_data_finished_o <= '1'; trigger_busy_o <= '0'; STATE <= S_IDLE; - elsif (LVL2_TRIGGER_IN = '1') then + elsif (TRIGGER_IN = '1') then evt_data_flush <= '1'; STATE <= S_FLUSH_BUFFER_WAIT; else @@ -184,7 +178,6 @@ begin if (evt_data_flushed = '0') then STATE <= S_FLUSH_BUFFER_WAIT; else - fee_data_finished_o <= '1'; STATE <= S_IDLE; end if; @@ -473,7 +466,6 @@ begin FEE_DATA_OUT <= fee_data_o; FEE_DATA_WRITE_OUT <= fee_data_write_o; - FEE_DATA_FINISHED_OUT <= fee_data_finished_o; SLV_DATA_OUT <= slv_data_out_o; SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; diff --git a/nxyter/source/nx_histograms.vhd b/nxyter/source/nx_histograms.vhd index 5fdabfc..6d471f5 100644 --- a/nxyter/source/nx_histograms.vhd +++ b/nxyter/source/nx_histograms.vhd @@ -110,7 +110,20 @@ begin --------------------------------------------------------------------------- - -- DEBUG_OUT(0) <= SLV_READ_IN; + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(1) <= CHANNEL_FILL_IN; + DEBUG_OUT(2) <= hit_write_busy; + DEBUG_OUT(3) <= pileup_write_busy; + DEBUG_OUT(4) <= ovfl_write_busy; + DEBUG_OUT(5) <= adc_write_busy; + + DEBUG_OUT(6) <= hit_read_busy; + DEBUG_OUT(7) <= pileup_read_busy; + DEBUG_OUT(8) <= ovfl_read_busy; + DEBUG_OUT(9) <= adc_read_busy; + DEBUG_OUT(15 downto 10) <= (others => '0'); + + -- DEBUG_OUT(15 downto 1) <= SLV_ADDR_IN(14 downto 0); ----------------------------------------------------------------------------- @@ -178,7 +191,7 @@ begin CHANNEL_DATA_VALID_OUT => pileup_read_data_valid, CHANNEL_READ_BUSY_OUT => pileup_read_busy, - DEBUG_OUT => DEBUG_OUT --open + DEBUG_OUT => open ); nx_histogram_ovfl: nx_histogram @@ -207,79 +220,74 @@ begin -- Fill Histograms ----------------------------------------------------------------------------- - PROC_FILL_HISTOGRAMS: process(CLK_IN) + + PROC_FILL_HISTOGRAMS: process(CHANNEL_FILL_IN, + CHANNEL_PILEUP_IN, + CHANNEL_OVERFLOW_IN + ) begin - if (rising_edge(CLK_IN)) then - if (RESET_IN = '1') then - hit_write_id <= (others => '0'); - hit_write_data <= (others => '0'); - hit_write <= '0'; - hit_add <= '0'; - - adc_write_id <= (others => '0'); - adc_write_data <= (others => '0'); - adc_write <= '0'; - adc_add <= '0'; - - pileup_write_id <= (others => '0'); - pileup_write_data <= (others => '0'); - pileup_write <= '0'; - pileup_add <= '0'; - - ovfl_write_id <= (others => '0'); - ovfl_write_data <= (others => '0'); - ovfl_write <= '0'; - ovfl_add <= '0'; - else - hit_write_id <= (others => '0'); - hit_write_data <= (others => '0'); + if (CHANNEL_FILL_IN = '1') then + if (hit_write_busy = '0') then + hit_write_id <= "0000000"; --CHANNEL_ID_IN; + hit_write_data <= x"0000_0001"; hit_write <= '0'; - hit_add <= '0'; - - adc_write_id <= (others => '0'); - adc_write_data <= (others => '0'); + hit_add <= '1'; + + adc_write_id <= CHANNEL_ID_IN; + adc_write_data(11 downto 0) <= CHANNEL_ADC_IN; + adc_write_data(31 downto 12) <= (others => '0'); adc_write <= '0'; - adc_add <= '0'; - - pileup_write_id <= (others => '0'); - pileup_write_data <= (others => '0'); - pileup_write <= '0'; - pileup_add <= '0'; - - ovfl_write_id <= (others => '0'); - ovfl_write_data <= (others => '0'); - ovfl_write <= '0'; - ovfl_add <= '0'; + adc_add <= '1'; - if (CHANNEL_FILL_IN = '1' and hit_write_busy = '0') then - hit_write_id <= CHANNEL_ID_IN; - hit_write_data <= x"0000_0001"; - hit_add <= '1'; - - adc_write_id <= CHANNEL_ID_IN; - adc_write_data(11 downto 0) <= CHANNEL_ADC_IN; - adc_write_data(31 downto 12) <= (others => '0'); - adc_add <= '1'; - - if (CHANNEL_PILEUP_IN = '1') then - pileup_write_id <= CHANNEL_ID_IN; - pileup_write_data <= x"0000_0001"; - pileup_add <= '1'; - end if; - - if (CHANNEL_OVERFLOW_IN = '1') then - ovfl_write_id <= CHANNEL_ID_IN; - ovfl_write_data <= x"0000_0001"; - ovfl_add <= '1'; - end if; - + if (CHANNEL_PILEUP_IN = '1') then + pileup_write_id <= CHANNEL_ID_IN; + pileup_write_data <= x"0000_0001"; + pileup_write <= '0'; + pileup_add <= '1'; + else + pileup_write_id <= (others => '0'); + pileup_write_data <= (others => '0'); + pileup_write <= '0'; + pileup_add <= '0'; + end if; + + if (CHANNEL_OVERFLOW_IN = '1') then + ovfl_write_id <= CHANNEL_ID_IN; + ovfl_write_data <= x"0000_0001"; + ovfl_write <= '0'; + ovfl_add <= '1'; + else + ovfl_write_id <= (others => '0'); + ovfl_write_data <= (others => '0'); + ovfl_write <= '0'; + ovfl_add <= '0'; end if; end if; + else + hit_write_id <= (others => '0'); + hit_write_data <= (others => '0'); + hit_write <= '0'; + hit_add <= '0'; + + adc_write_id <= (others => '0'); + adc_write_data <= (others => '0'); + adc_write <= '0'; + adc_add <= '0'; + + pileup_write_id <= (others => '0'); + pileup_write_data <= (others => '0'); + pileup_write <= '0'; + pileup_add <= '0'; + + ovfl_write_id <= (others => '0'); + ovfl_write_data <= (others => '0'); + ovfl_write <= '0'; + ovfl_add <= '0'; end if; end process PROC_FILL_HISTOGRAMS; --------------------------------------------------------------------------- - -- TRBNet Slave Bus + -- Trbnet Slave Bus --------------------------------------------------------------------------- -- Give status info to the TRB Slow Control Channel diff --git a/nxyter/source/nx_i2c_readbyte.vhd b/nxyter/source/nx_i2c_readbyte.vhd index 08ed571..fe833d6 100644 --- a/nxyter/source/nx_i2c_readbyte.vhd +++ b/nxyter/source/nx_i2c_readbyte.vhd @@ -34,14 +34,14 @@ architecture Behavioral of nx_i2c_readbyte is signal i2c_start : std_logic; signal sequence_done_o : std_logic; - signal i2c_byte : unsigned(31 downto 0); + signal i2c_data : unsigned(31 downto 0); signal bit_ctr : unsigned(3 downto 0); signal i2c_ack_o : std_logic; signal byte_ctr : unsigned(2 downto 0); signal wait_timer_init : unsigned(11 downto 0); signal sequence_done_o_x : std_logic; - signal i2c_byte_x : unsigned(31 downto 0); + signal i2c_data_x : unsigned(31 downto 0); signal bit_ctr_x : unsigned(3 downto 0); signal i2c_ack_o_x : std_logic; signal byte_ctr_x : unsigned(2 downto 0); @@ -92,7 +92,7 @@ begin if( rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then sequence_done_o <= '0'; - i2c_byte <= (others => '0'); + i2c_data <= (others => '0'); bit_ctr <= (others => '0'); i2c_ack_o <= '0'; byte_ctr <= (others => '0'); @@ -100,7 +100,7 @@ begin STATE <= S_IDLE; else sequence_done_o <= sequence_done_o_x; - i2c_byte <= i2c_byte_x; + i2c_data <= i2c_data_x; bit_ctr <= bit_ctr_x; i2c_ack_o <= i2c_ack_o_x; byte_ctr <= byte_ctr_x; @@ -119,7 +119,7 @@ begin sda_o <= '1'; scl_o <= '1'; sequence_done_o_x <= '0'; - i2c_byte_x <= i2c_byte; + i2c_data_x <= i2c_data; bit_ctr_x <= bit_ctr; i2c_ack_o_x <= i2c_ack_o; byte_ctr_x <= byte_ctr; @@ -130,7 +130,7 @@ begin if (START_IN = '1') then sda_o <= '0'; scl_o <= '0'; - i2c_byte_x <= (others => '0'); + i2c_data_x <= (others => '0'); byte_ctr_x <= (others => '0'); NEXT_STATE <= S_INIT; else @@ -179,8 +179,9 @@ begin end if; when S_GET_BIT => - i2c_byte_x(0) <= SDA_IN; - NEXT_STATE <= S_SET_SCL2; + i2c_data_x(0) <= SDA_IN; + i2c_data_x(31 downto 1) <= i2c_data(30 downto 0); + NEXT_STATE <= S_SET_SCL2; when S_SET_SCL2 => if (wait_timer_done = '0') then @@ -202,7 +203,6 @@ begin scl_o <= '0'; if (bit_ctr > 0) then bit_ctr_x <= bit_ctr - 1; - i2c_byte_x <= i2c_byte sll 1; wait_timer_init_x <= I2C_SPEED srl 2; NEXT_STATE <= S_UNSET_SCL1; else @@ -279,7 +279,7 @@ begin ----------------------------------------------------------------------------- SEQUENCE_DONE_OUT <= sequence_done_o; - BYTE_OUT <= i2c_byte; + BYTE_OUT <= i2c_data; -- I2c Outputs SDA_OUT <= sda_o; diff --git a/nxyter/source/nx_setup.vhd b/nxyter/source/nx_setup.vhd index 422159d..665448c 100644 --- a/nxyter/source/nx_setup.vhd +++ b/nxyter/source/nx_setup.vhd @@ -24,6 +24,12 @@ entity nx_setup is SPI_COMMAND_BUSY_IN : in std_logic; SPI_DATA_IN : in std_logic_vector(31 downto 0); SPI_LOCK_OUT : out std_logic; + + -- Internal Register Read + INT_READ_IN : in std_logic; + INT_ADDR_IN : in std_logic_vector(15 downto 0); + INT_ACK_OUT : out std_logic; + INT_DATA_OUT : out std_logic_vector(31 downto 0); -- Slave bus SLV_READ_IN : in std_logic; @@ -100,7 +106,7 @@ architecture Behavioral of nx_setup is signal do_dac_write : std_logic; -- ADC RAM Handler - type adc_ram_t is array(0 to 3) of std_logic_vector(15 downto 0); + type adc_ram_t is array(0 to 3) of std_logic_vector(12 downto 0); signal adc_ram : adc_ram_t; -- Token Handler @@ -203,7 +209,11 @@ architecture Behavioral of nx_setup is signal i2c_disable_memory : std_logic; signal i2c_reg_reset_in_s : std_logic; signal i2c_reg_reset_clear : std_logic; - + + -- Internal Register Read + signal int_data_o : std_logic_vector(31 downto 0); + signal int_ack_o : std_logic; + -- TRBNet Slave Bus signal slv_data_out_o : std_logic_vector(31 downto 0); signal slv_no_more_data_o : std_logic; @@ -224,6 +234,7 @@ architecture Behavioral of nx_setup is signal nxyter_clock : std_logic_vector(1 downto 0); signal nxyter_testchannels : std_logic_vector(2 downto 0); signal i2c_update_memory_r : std_logic; + begin ----------------------------------------------------------------------------- @@ -247,7 +258,7 @@ begin DEBUG_OUT(13) <= i2c_lock_1; DEBUG_OUT(14) <= i2c_lock_2; DEBUG_OUT(15) <= i2c_lock_4; - + ----------------------------------------------------------------------------- PROC_I2C_RAM: process(CLK_IN) @@ -819,10 +830,10 @@ begin adc_i2c_command(31 downto 16) <= x"c229"; adc_i2c_command(15 downto 14) <= (others => '0'); case adc_token_ctr is - when "00" => adc_i2c_command(15 downto 12) <= "0000"; - when "01" => adc_i2c_command(15 downto 12) <= "0001"; - when "10" => adc_i2c_command(15 downto 12) <= "0010"; - when "11" => adc_i2c_command(15 downto 12) <= "0100"; + when "00" => adc_i2c_command(15 downto 12) <= "0001"; + when "01" => adc_i2c_command(15 downto 12) <= "0010"; + when "10" => adc_i2c_command(15 downto 12) <= "0100"; + when "11" => adc_i2c_command(15 downto 12) <= "1000"; end case; adc_i2c_command(11 downto 8) <= "0000"; adc_i2c_command( 7 downto 0) <= (others => '0'); @@ -841,7 +852,13 @@ begin end if; when ADC_READ_I2C_STORE_MEM => - adc_ram(index) <= i2c_data_bytes(15 downto 0); + if (i2c_data_bytes(13 downto 12) = + std_logic_vector(adc_token_ctr)) then + adc_ram(index)(11 downto 0) <= i2c_data_bytes(11 downto 0); + adc_ram(index)(12) <= '0'; + else + adc_ram(index) <= (others => '1'); + end if; i2c_lock_4_clear <= '1'; ADC_STATE <= ADC_NEXT_TOKEN; @@ -1002,10 +1019,137 @@ begin end if; end process PROC_REG_RESET; + ----------------------------------------------------------------------------- + + PROC_INTERNAL_REG_READ: process(CLK_IN) + variable index : integer := 0; + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + int_data_o <= (others => '0'); + int_ack_o <= '0'; + else + int_data_o <= (others => '0'); + int_ack_o <= '0'; + + if (INT_READ_IN = '1') then + if (INT_ADDR_IN >= x"0000" and INT_ADDR_IN <= x"002d") then + index := to_integer(unsigned(INT_ADDR_IN(5 downto 0))); + if (i2c_disable_memory = '0') then + int_data_o(7 downto 0) <= i2c_ram(index); + int_data_o(28 downto 8) <= (others => '0'); + int_data_o(29) <= + not register_access_type(index); + int_data_o(30) <= i2c_read_token(index); + int_data_o(31) <= i2c_write_token(index); + else + int_data_o(31 downto 0) <= (others => '1'); + end if; + int_ack_o <= '1'; + + elsif (INT_ADDR_IN >= x"0100" and INT_ADDR_IN <= x"0180") then + index := to_integer(unsigned(INT_ADDR_IN(7 downto 0))); + if (i2c_disable_memory = '0') then + int_data_o(5 downto 0) <= dac_ram(index); + int_data_o(29 downto 6) <= (others => '0'); + int_data_o(30) <= dac_read_token(index); + int_data_o(31) <= dac_write_token(index); + else + int_data_o(31 downto 0) <= (others => '1'); + end if; + int_ack_o <= '1'; + + elsif (INT_ADDR_IN >= x"0080" and INT_ADDR_IN <= x"0083") then + index := to_integer(unsigned(INT_ADDR_IN(1 downto 0))); + if (i2c_disable_memory = '0') then + int_data_o(12 downto 0) <= adc_ram(index); + int_data_o(31 downto 13) <= (others => '0'); + else + int_data_o(31 downto 0) <= (others => '1'); + end if; + int_ack_o <= '1'; + else + case INT_ADDR_IN is + when x"0050" => + -- Nxyter Clock + if (i2c_disable_memory = '0') then + int_data_o(0) <= i2c_ram(33)(3); + int_data_o(31 downto 1) <= (others => '0'); + else + int_data_o(31 downto 0) <= (others => '1'); + end if; + int_ack_o <= '1'; + + when x"0051" => + -- Nxyter Polarity + if (i2c_disable_memory = '0') then + int_data_o(0) <= i2c_ram(33)(2); + int_data_o(31 downto 1) <= (others => '0'); + else + int_data_o(31 downto 0) <= (others => '1'); + end if; + int_ack_o <= '1'; + + when x"0052" => + -- Nxyter Testpulse Polarity + if (i2c_disable_memory = '0') then + int_data_o(0) <= i2c_ram(32)(2); + int_data_o(31 downto 1) <= (others => '0'); + else + int_data_o(31 downto 0) <= (others => '1'); + end if; + int_ack_o <= '1'; + + when x"0053" => + -- Nxyter Testpulse + if (i2c_disable_memory = '0') then + int_data_o(0) <= i2c_ram(32)(0); + int_data_o(31 downto 1) <= (others => '0'); + else + int_data_o(31 downto 0) <= (others => '1'); + end if; + int_ack_o <= '1'; + + when x"0054" => + -- Nxyter Testtrigger + if (i2c_disable_memory = '0') then + int_data_o(0) <= i2c_ram(32)(3); + int_data_o(31 downto 1) <= (others => '0'); + else + int_data_o(31 downto 0) <= (others => '1'); + end if; + int_ack_o <= '1'; + + when x"0055" => + -- Nxyter Testpulse Channels + if (i2c_disable_memory = '0') then + int_data_o(1 downto 0) <= i2c_ram(33)(1 downto 0); + int_data_o(31 downto 2) <= (others => '0'); + else + int_data_o(31 downto 0) <= (others => '1'); + end if; + int_ack_o <= '1'; + + when x"0056" => + -- I2C Online + int_data_o(0) <= i2c_online_o; + int_data_o(31 downto 2) <= (others => '0'); + int_ack_o <= '1'; + + when others => + int_data_o(31 downto 0) <= (others => '1'); + int_ack_o <= '1'; + end case; + end if; + end if; + end if; + end if; + end process PROC_INTERNAL_REG_READ; + ----------------------------------------------------------------------------- PROC_SLAVE_BUS: process(CLK_IN) - variable index : integer := 0; + variable index : integer := 0; begin if( rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then @@ -1171,9 +1315,8 @@ begin elsif (SLV_ADDR_IN >= x"0080" and SLV_ADDR_IN <= x"0083") then index := to_integer(unsigned(SLV_ADDR_IN(1 downto 0))); if (i2c_disable_memory = '0') then - slv_data_out_o(15 downto 0) <= adc_ram(index); - slv_data_out_o(30 downto 16) <= (others => '0'); - slv_data_out_o(31) <= adc_read_token(index); + slv_data_out_o(12 downto 0) <= adc_ram(index); + slv_data_out_o(31 downto 13) <= (others => '0'); adc_read_token_r(index) <= '1'; else slv_data_out_o(31 downto 0) <= (others => '1'); @@ -1266,18 +1409,21 @@ begin -- Output Signals ----------------------------------------------------------------------------- - I2C_COMMAND_OUT <= i2c_command_o; - I2C_LOCK_OUT <= i2c_command_busy_o; - I2C_ONLINE_OUT <= i2c_online_o; - - - SPI_COMMAND_OUT <= (others => '0'); - SPI_LOCK_OUT <= '0'; - - -- Slave Bus - SLV_DATA_OUT <= slv_data_out_o; - SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; - SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; - SLV_ACK_OUT <= slv_ack_o; + I2C_COMMAND_OUT <= i2c_command_o; + I2C_LOCK_OUT <= i2c_command_busy_o; + I2C_ONLINE_OUT <= i2c_online_o; + + SPI_COMMAND_OUT <= (others => '0'); + SPI_LOCK_OUT <= '0'; + + -- Internal Read + INT_ACK_OUT <= int_ack_o; + INT_DATA_OUT <= int_data_o; + + -- Slave Bus + SLV_DATA_OUT <= slv_data_out_o; + SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; + SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; + SLV_ACK_OUT <= slv_ack_o; end Behavioral; diff --git a/nxyter/source/nx_trigger_handler.vhd b/nxyter/source/nx_trigger_handler.vhd index cd6eb45..d2fd595 100644 --- a/nxyter/source/nx_trigger_handler.vhd +++ b/nxyter/source/nx_trigger_handler.vhd @@ -27,21 +27,31 @@ entity nx_trigger_handler is LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + --Response from FEE + FEE_DATA_OUT : out std_logic_vector(31 downto 0); + FEE_DATA_WRITE_OUT : out std_logic; FEE_DATA_FINISHED_OUT : out std_logic; FEE_TRG_RELEASE_OUT : out std_logic; FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0); + FEE_DATA_0_IN : in std_logic_vector(31 downto 0); + FEE_DATA_WRITE_0_IN : in std_logic; + FEE_DATA_1_IN : in std_logic_vector(31 downto 0); + FEE_DATA_WRITE_1_IN : in std_logic; + -- Internal FPGA Trigger INTERNAL_TRIGGER_IN : in std_logic; -- Trigger FeedBack TRIGGER_VALIDATE_BUSY_IN : in std_logic; - LVL2_TRIGGER_BUSY_IN : in std_logic; + TRIGGER_BUSY_0_IN : in std_logic; + TRIGGER_BUSY_1_IN : in std_logic; -- OUT VALID_TRIGGER_OUT : out std_logic; TIMESTAMP_TRIGGER_OUT : out std_logic; - LVL2_TRIGGER_OUT : out std_logic; + TRIGGER_TIMING_OUT : out std_logic; + TRIGGER_SETUP_OUT : out std_logic; FAST_CLEAR_OUT : out std_logic; TRIGGER_BUSY_OUT : out std_logic; @@ -96,9 +106,12 @@ architecture Behavioral of nx_trigger_handler is -- Trigger Handler signal valid_trigger_o : std_logic; - signal lvl2_trigger_o : std_logic; + signal timing_trigger_o : std_logic; + signal setup_trigger_o : std_logic; signal fast_clear_o : std_logic; signal trigger_busy_o : std_logic; + signal fee_data_o : std_logic_vector(31 downto 0); + signal fee_data_write_o : std_logic; signal fee_data_finished_o : std_logic; signal fee_trg_release_o : std_logic; signal fee_trg_statusbits_o : std_logic_vector(31 downto 0); @@ -108,7 +121,7 @@ architecture Behavioral of nx_trigger_handler is type STATES is (S_IDLE, S_CTS_TRIGGER, S_WAIT_TRG_DATA_VALID, - S_WAIT_LVL2_TRIGGER_DONE, + S_WAIT_TIMING_TRIGGER_DONE, S_FEE_TRIGGER_RELEASE, S_WAIT_FEE_TRIGGER_RELEASE_ACK, S_INTERNAL_TRIGGER, @@ -117,6 +130,15 @@ architecture Behavioral of nx_trigger_handler is ); signal STATE : STATES; + type TRIGGER_TYPES is (T_UNDEF, + T_IGNORE, + T_INTERNAL, + T_TIMING, + T_SETUP + ); + signal TRIGGER_TYPE : TRIGGER_TYPES; + + -- Testpulse Handler type T_STATES is (T_IDLE, T_WAIT_TIMER, @@ -153,11 +175,11 @@ begin DEBUG_OUT(2) <= invalid_timing_trigger; --timing_trigger_l; DEBUG_OUT(3) <= LVL1_VALID_TIMING_TRG_IN; DEBUG_OUT(4) <= LVL1_TRG_DATA_VALID_IN; - DEBUG_OUT(5) <= INTERNAL_TRIGGER_IN; + DEBUG_OUT(5) <= fee_data_write_o; DEBUG_OUT(6) <= TRIGGER_VALIDATE_BUSY_IN; - DEBUG_OUT(7) <= LVL2_TRIGGER_BUSY_IN; + DEBUG_OUT(7) <= TRIGGER_BUSY_0_IN; DEBUG_OUT(8) <= valid_trigger_o; - DEBUG_OUT(9) <= lvl2_trigger_o; + DEBUG_OUT(9) <= timing_trigger_o; DEBUG_OUT(10) <= fee_data_finished_o; DEBUG_OUT(11) <= fee_trg_release_o; DEBUG_OUT(12) <= trigger_busy_o; @@ -335,24 +357,27 @@ begin if( rising_edge(CLK_IN) ) then if (RESET_IN = '1') then valid_trigger_o <= '0'; - lvl2_trigger_o <= '0'; + timing_trigger_o <= '0'; + setup_trigger_o <= '0'; fee_data_finished_o <= '0'; fee_trg_release_o <= '0'; fee_trg_statusbits_o <= (others => '0'); fast_clear_o <= '0'; trigger_busy_o <= '0'; send_testpulse_l <= '0'; + TRIGGER_TYPE <= T_UNDEF; STATE <= S_IDLE; else valid_trigger_o <= '0'; - lvl2_trigger_o <= '0'; + timing_trigger_o <= '0'; + setup_trigger_o <= '0'; fee_data_finished_o <= '0'; fee_trg_release_o <= '0'; fee_trg_statusbits_o <= (others => '0'); fast_clear_o <= '0'; trigger_busy_o <= '1'; send_testpulse_l <= '0'; - + if (LVL1_INVALID_TRG_IN = '1') then -- There was no valid Timing Trigger at CTS, do a fast clear fast_clear_o <= '1'; @@ -363,27 +388,32 @@ begin when S_IDLE => if (LVL1_VALID_NOTIMING_TRG_IN = '1') then -- Calibration Trigger .. ignore + TRIGGER_TYPE <= T_IGNORE; --T_SETUP; STATE <= S_WAIT_TRG_DATA_VALID; elsif (LVL1_VALID_TIMING_TRG_IN = '1') then if (NXYTER_OFFLINE_IN = '0') then -- Normal Trigger + TRIGGER_TYPE <= T_TIMING; STATE <= S_CTS_TRIGGER; else -- Ignore Trigger for nxyter is offline - STATE <= S_WAIT_TRG_DATA_VALID; + TRIGGER_TYPE <= T_IGNORE; + STATE <= S_WAIT_TRG_DATA_VALID; end if; elsif (INTERNAL_TRIGGER_IN = '1') then -- Internal Trigger, not defined yet + TRIGGER_TYPE <= T_INTERNAL; STATE <= S_INTERNAL_TRIGGER; else trigger_busy_o <= '0'; + TRIGGER_TYPE <= T_UNDEF; STATE <= S_IDLE; end if; when S_CTS_TRIGGER => valid_trigger_o <= '1'; - lvl2_trigger_o <= '1'; + timing_trigger_o <= '1'; if (reg_testpulse_enable = '1') then send_testpulse_l <= '1'; end if; @@ -393,12 +423,12 @@ begin if (LVL1_TRG_DATA_VALID_IN = '0') then STATE <= S_WAIT_TRG_DATA_VALID; else - STATE <= S_WAIT_LVL2_TRIGGER_DONE; + STATE <= S_WAIT_TIMING_TRIGGER_DONE; end if; - when S_WAIT_LVL2_TRIGGER_DONE => - if (LVL2_TRIGGER_BUSY_IN = '1') then - STATE <= S_WAIT_LVL2_TRIGGER_DONE; + when S_WAIT_TIMING_TRIGGER_DONE => + if (TRIGGER_BUSY_0_IN = '1') then + STATE <= S_WAIT_TIMING_TRIGGER_DONE; else fee_data_finished_o <= '1'; STATE <= S_FEE_TRIGGER_RELEASE; @@ -440,6 +470,25 @@ begin end if; end process PROC_TRIGGER_HANDLER; + PROC_EVENT_DATA_MULTIPLEXER: process(TRIGGER_TYPE) + begin + case TRIGGER_TYPE is + when T_UNDEF | T_IGNORE | T_INTERNAL => + fee_data_o <= (others => '0'); + fee_data_write_o <= '0'; + + when T_TIMING => + fee_data_o <= FEE_DATA_0_IN; + fee_data_write_o <= FEE_DATA_WRITE_0_IN; + + when T_SETUP => + fee_data_o <= FEE_DATA_1_IN; + fee_data_write_o <= FEE_DATA_WRITE_1_IN; + + end case; + end process PROC_EVENT_DATA_MULTIPLEXER; + + -- pulse_dtrans_4: pulse_dtrans -- generic map ( -- CLK_RATIO => 2 @@ -515,7 +564,7 @@ begin rate_timer <= (others => '0'); else if (rate_timer < x"5f5e100") then - if (lvl2_trigger_o = '1') then + if (timing_trigger_o = '1') then accepted_trigger_rate_t <= accepted_trigger_rate_t + 1; end if; rate_timer <= rate_timer + 1; @@ -614,9 +663,13 @@ begin -- Trigger Output VALID_TRIGGER_OUT <= valid_trigger_o; TIMESTAMP_TRIGGER_OUT <= timestamp_trigger_o; - LVL2_TRIGGER_OUT <= lvl2_trigger_o; + TRIGGER_TIMING_OUT <= timing_trigger_o; + TRIGGER_SETUP_OUT <= setup_trigger_o; FAST_CLEAR_OUT <= fast_clear_o; TRIGGER_BUSY_OUT <= trigger_busy_o; + + FEE_DATA_OUT <= fee_data_o; + FEE_DATA_WRITE_OUT <= fee_data_write_o; FEE_DATA_FINISHED_OUT <= fee_data_finished_o; FEE_TRG_RELEASE_OUT <= fee_trg_release_o; FEE_TRG_STATUSBITS_OUT <= fee_trg_statusbits_o; diff --git a/nxyter/source/nx_trigger_validate.vhd b/nxyter/source/nx_trigger_validate.vhd index 073c588..246d4c2 100644 --- a/nxyter/source/nx_trigger_validate.vhd +++ b/nxyter/source/nx_trigger_validate.vhd @@ -360,36 +360,43 @@ begin case readout_mode(1 downto 0) is - when "00" | "11" => + when "00" => -- Default Mode - -- RefValue + Parity Valid + Error Bits if (TIMESTAMP_STATUS_IN(S_PARITY) = '0') then d_data_o(10 downto 0) <= deltaTStore(10 downto 0); - d_data_o(11) <= TIMESTAMP_STATUS_IN(S_PILEUP); - d_data_o(12) <= TIMESTAMP_STATUS_IN(S_OVFL); - d_data_o(24 downto 13) <= ADC_DATA_IN; + d_data_o(22 downto 11) <= ADC_DATA_IN; + d_data_o(23) <= TIMESTAMP_STATUS_IN(S_OVFL); + d_data_o(24) <= TIMESTAMP_STATUS_IN(S_PILEUP); d_data_o(31 downto 25) <= CHANNEL_IN; d_data_clk_o <= '1'; end if; when "01" => - -- Extended Timestamp Mode - -- RefValue + Parity Valid, Error Bits = extended Timestamp + -- Extended Timestamp Mode 12Bit if (TIMESTAMP_STATUS_IN(S_PARITY) = '0') then - d_data_o(12 downto 0) <= deltaTStore(12 downto 0); - d_data_o(24 downto 13) <= ADC_DATA_IN; + d_data_o(11 downto 0) <= deltaTStore(11 downto 0); + d_data_o(22 downto 12) <= ADC_DATA_IN(11 downto 1); + d_data_o(23) <= TIMESTAMP_STATUS_IN(S_OVFL); + d_data_o(24) <= TIMESTAMP_STATUS_IN(S_PILEUP); d_data_o(31 downto 25) <= CHANNEL_IN; d_data_clk_o <= '1'; end if; when "10" => - -- Super Extended Timestamp Mode - -- ..... + -- Extended Timestamp Mode 14Bit if (TIMESTAMP_STATUS_IN(S_PARITY) = '0') then d_data_o(13 downto 0) <= deltaTStore; - d_data_o(14) <= TIMESTAMP_STATUS_IN(S_PILEUP); - d_data_o(15) <= TIMESTAMP_STATUS_IN(S_OVFL); - d_data_o(24 downto 16) <= (others => '0'); + d_data_o(22 downto 14) <= ADC_DATA_IN(11 downto 3); + d_data_o(23) <= TIMESTAMP_STATUS_IN(S_OVFL); + d_data_o(24) <= TIMESTAMP_STATUS_IN(S_PILEUP); + d_data_o(31 downto 25) <= CHANNEL_IN; + d_data_clk_o <= '1'; + end if; + + when "11" => + if (TIMESTAMP_STATUS_IN(S_PARITY) = '0') then + d_data_o(13 downto 0) <= deltaTStore; + d_data_o(24 downto 14) <= ADC_DATA_IN(11 downto 1); d_data_o(31 downto 25) <= CHANNEL_IN; d_data_clk_o <= '1'; end if; @@ -642,7 +649,7 @@ begin end if; when S_WRITE_HEADER => - state_d <= "10"; + state_d <= "10"; t_data_o(11 downto 0) <= timestamp_ref; t_data_o(21 downto 12) <= event_counter; diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index 5326de9..9f726a1 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -322,6 +322,10 @@ component nx_setup SPI_COMMAND_BUSY_IN : in std_logic; SPI_DATA_IN : in std_logic_vector(31 downto 0); SPI_LOCK_OUT : out std_logic; + INT_READ_IN : in std_logic; + INT_ADDR_IN : in std_logic_vector(15 downto 0); + INT_ACK_OUT : out std_logic; + INT_DATA_OUT : out std_logic_vector(31 downto 0); SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; SLV_DATA_OUT : out std_logic_vector(31 downto 0); @@ -580,13 +584,12 @@ component nx_event_buffer DATA_IN : in std_logic_vector(31 downto 0); DATA_CLK_IN : in std_logic; EVT_NOMORE_DATA_IN : in std_logic; - LVL2_TRIGGER_IN : in std_logic; + TRIGGER_IN : in std_logic; FAST_CLEAR_IN : in std_logic; TRIGGER_BUSY_OUT : out std_logic; EVT_BUFFER_FULL_OUT : out std_logic; FEE_DATA_OUT : out std_logic_vector(31 downto 0); FEE_DATA_WRITE_OUT : out std_logic; - FEE_DATA_FINISHED_OUT : out std_logic; FEE_DATA_ALMOST_FULL_IN : in std_logic; SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; @@ -600,6 +603,28 @@ component nx_event_buffer ); end component; +component nx_calib_event + generic ( + BOARD_ID : std_logic_vector(1 downto 0)); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + NXYTER_OFFLINE_IN : in std_logic; + TRIGGER_IN : in std_logic; + FAST_CLEAR_IN : in std_logic; + TRIGGER_BUSY_OUT : out std_logic; + FEE_DATA_OUT : out std_logic_vector(31 downto 0); + FEE_DATA_WRITE_OUT : out std_logic; + FEE_DATA_FINISHED_OUT : out std_logic; + FEE_DATA_ALMOST_FULL_IN : in std_logic; + INT_READ_OUT : out std_logic; + INT_ADDR_OUT : out std_logic_vector(15 downto 0); + INT_ACK_IN : in std_logic; + INT_DATA_IN : in std_logic_vector(31 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end component; + ------------------------------------------------------------------------------- component nx_histogram @@ -850,15 +875,23 @@ component nx_trigger_handler LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + FEE_DATA_OUT : out std_logic_vector(31 downto 0); + FEE_DATA_WRITE_OUT : out std_logic; FEE_DATA_FINISHED_OUT : out std_logic; FEE_TRG_RELEASE_OUT : out std_logic; FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0); + FEE_DATA_0_IN : in std_logic_vector(31 downto 0); + FEE_DATA_WRITE_0_IN : in std_logic; + FEE_DATA_1_IN : in std_logic_vector(31 downto 0); + FEE_DATA_WRITE_1_IN : in std_logic; INTERNAL_TRIGGER_IN : in std_logic; TRIGGER_VALIDATE_BUSY_IN : in std_logic; - LVL2_TRIGGER_BUSY_IN : in std_logic; + TRIGGER_BUSY_0_IN : in std_logic; + TRIGGER_BUSY_1_IN : in std_logic; VALID_TRIGGER_OUT : out std_logic; TIMESTAMP_TRIGGER_OUT : out std_logic; - LVL2_TRIGGER_OUT : out std_logic; + TRIGGER_TIMING_OUT : out std_logic; + TRIGGER_SETUP_OUT : out std_logic; FAST_CLEAR_OUT : out std_logic; TRIGGER_BUSY_OUT : out std_logic; TRIGGER_TESTPULSE_OUT : out std_logic; diff --git a/nxyter/source/nxyter_fee_board.vhd b/nxyter/source/nxyter_fee_board.vhd index 56c6ef9..ac66b29 100644 --- a/nxyter/source/nxyter_fee_board.vhd +++ b/nxyter/source/nxyter_fee_board.vhd @@ -173,20 +173,33 @@ architecture Behavioral of nXyter_FEE_board is signal trigger_validate_adc : std_logic_vector(11 downto 0); signal trigger_validate_pileup : std_logic; signal trigger_validate_ovfl : std_logic; - + -- Event Buffer - signal trigger_evt_busy : std_logic; + signal fee_data_o_0 : std_logic_vector(31 downto 0); + signal fee_data_write_o_0 : std_logic; + + signal trigger_evt_busy_0 : std_logic; signal evt_buffer_full : std_logic; signal fee_trg_statusbits_o : std_logic_vector(31 downto 0); signal fee_data_o : std_logic_vector(31 downto 0); signal fee_data_write_o : std_logic; signal fee_data_finished_o : std_logic; signal fee_almost_full_i : std_logic; - + + -- Calib Event + signal fee_data_o_1 : std_logic_vector(31 downto 0); + signal fee_data_write_o_1 : std_logic; + signal trigger_evt_busy_1 : std_logic; + + signal int_read : std_logic; + signal int_addr : std_logic_vector(15 downto 0); + signal int_ack : std_logic; + signal int_data : std_logic_vector(31 downto 0); + -- Trigger Handler signal trigger : std_logic; signal timestamp_trigger : std_logic; - signal lvl2_trigger : std_logic; + signal trigger_timing : std_logic; signal trigger_busy : std_logic; signal fast_clear : std_logic; signal fee_trg_release_o : std_logic; @@ -207,7 +220,7 @@ architecture Behavioral of nXyter_FEE_board is signal error_data_receiver : std_logic; -- Debug Handler - constant DEBUG_NUM_PORTS : integer := 13; + constant DEBUG_NUM_PORTS : integer := 14; signal debug_line : debug_array_t(0 to DEBUG_NUM_PORTS-1); begin @@ -346,6 +359,10 @@ begin SPI_COMMAND_BUSY_IN => spi_command_busy, SPI_DATA_IN => spi_data, SPI_LOCK_OUT => spi_lock, + INT_READ_IN => int_read, + INT_ADDR_IN => int_addr, + INT_ACK_OUT => int_ack, + INT_DATA_OUT => int_data, SLV_READ_IN => slv_read(9), SLV_WRITE_IN => slv_write(9), SLV_DATA_OUT => slv_data_rd(9*32+31 downto 9*32), @@ -466,18 +483,24 @@ begin LVL1_TRG_INFORMATION_IN => LVL1_TRG_INFORMATION_IN, LVL1_INT_TRG_NUMBER_IN => LVL1_INT_TRG_NUMBER_IN, + FEE_DATA_OUT => FEE_DATA_OUT, + FEE_DATA_WRITE_OUT => FEE_DATA_WRITE_OUT, FEE_DATA_FINISHED_OUT => FEE_DATA_FINISHED_OUT, FEE_TRG_RELEASE_OUT => FEE_TRG_RELEASE_OUT, FEE_TRG_STATUSBITS_OUT => FEE_TRG_STATUSBITS_OUT, - + FEE_DATA_0_IN => fee_data_o_0, + FEE_DATA_WRITE_0_IN => fee_data_write_o_0, + FEE_DATA_1_IN => fee_data_o_1, + FEE_DATA_WRITE_1_IN => fee_data_write_o_1, INTERNAL_TRIGGER_IN => trigger_intern, TRIGGER_VALIDATE_BUSY_IN => trigger_validate_busy, - LVL2_TRIGGER_BUSY_IN => trigger_evt_busy, + TRIGGER_BUSY_0_IN => trigger_evt_busy_0, + TRIGGER_BUSY_1_IN => trigger_evt_busy_1, VALID_TRIGGER_OUT => trigger, TIMESTAMP_TRIGGER_OUT => timestamp_trigger, - LVL2_TRIGGER_OUT => lvl2_trigger, + TRIGGER_TIMING_OUT => trigger_timing, FAST_CLEAR_OUT => fast_clear, TRIGGER_BUSY_OUT => trigger_busy, @@ -530,7 +553,7 @@ begin CLK_IN => CLK_IN, RESET_IN => RESET_IN, NX_DATA_CLK_TEST_IN => NX_DATA_CLK_TEST_IN, - TRIGGER_IN => lvl2_trigger, + TRIGGER_IN => trigger_timing, NX_TIMESTAMP_CLK_IN => NX_DATA_CLK_IN, NX_TIMESTAMP_IN => NX_TIMESTAMP_IN, @@ -679,7 +702,7 @@ begin ------------------------------------------------------------------------------- -- Data Buffer FIFO ------------------------------------------------------------------------------- - + nx_event_buffer_1: nx_event_buffer generic map ( BOARD_ID => BOARD_ID @@ -694,14 +717,13 @@ begin DATA_CLK_IN => trigger_data_clk, EVT_NOMORE_DATA_IN => validate_nomore_data, - LVL2_TRIGGER_IN => lvl2_trigger, + TRIGGER_IN => trigger_timing, FAST_CLEAR_IN => fast_clear, - TRIGGER_BUSY_OUT => trigger_evt_busy, + TRIGGER_BUSY_OUT => trigger_evt_busy_0, EVT_BUFFER_FULL_OUT => evt_buffer_full, - FEE_DATA_OUT => FEE_DATA_OUT, - FEE_DATA_WRITE_OUT => FEE_DATA_WRITE_OUT, - FEE_DATA_FINISHED_OUT => open, --FEE_DATA_FINISHED_OUT, + FEE_DATA_OUT => fee_data_o_0, + FEE_DATA_WRITE_OUT => fee_data_write_o_0, FEE_DATA_ALMOST_FULL_IN => FEE_DATA_ALMOST_FULL_IN, SLV_READ_IN => slv_read(3), @@ -716,6 +738,27 @@ begin DEBUG_OUT => debug_line(11) ); + nx_calib_event_1: nx_calib_event + generic map ( + BOARD_ID => BOARD_ID + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + NXYTER_OFFLINE_IN => nxyter_offline, + TRIGGER_IN => trigger_timing, + FAST_CLEAR_IN => fast_clear, + TRIGGER_BUSY_OUT => trigger_evt_busy_1, + FEE_DATA_OUT => fee_data_o_1, + FEE_DATA_WRITE_OUT => fee_data_write_o_1, + FEE_DATA_ALMOST_FULL_IN => FEE_DATA_ALMOST_FULL_IN, + INT_READ_OUT => int_read, + INT_ADDR_OUT => int_addr, + INT_ACK_IN => int_ack, + INT_DATA_IN => int_data, + DEBUG_OUT => debug_line(13) + ); + nx_histograms_1: nx_histograms port map ( CLK_IN => CLK_IN, diff --git a/nxyter/source/registers.txt b/nxyter/source/registers.txt index b72180a..efc964e 100644 --- a/nxyter/source/registers.txt +++ b/nxyter/source/registers.txt @@ -200,7 +200,8 @@ 10: nx_trigger_validate 11: nx_event_buffer 12: nx_histograms - 13: Checkerboard + 13: nx_calib_event + 14: Checkerboard --- Trigger Selction Window Setup diff --git a/nxyter/trb3_periph.prj b/nxyter/trb3_periph.prj index ab66620..aacd4f8 100644 --- a/nxyter/trb3_periph.prj +++ b/nxyter/trb3_periph.prj @@ -176,6 +176,7 @@ add_file -vhdl -lib "work" "source/nx_data_delay.vhd" add_file -vhdl -lib "work" "source/nx_data_validate.vhd" add_file -vhdl -lib "work" "source/nx_trigger_validate.vhd" add_file -vhdl -lib "work" "source/nx_event_buffer.vhd" +add_file -vhdl -lib "work" "source/nx_calib_event.vhd" add_file -vhdl -lib "work" "source/nx_control.vhd" add_file -vhdl -lib "work" "source/nx_setup.vhd" -- 2.43.0