From 3138162861a03554f3af2758c099c42decdc1244 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Tue, 26 Jul 2022 10:46:28 +0200 Subject: [PATCH] only D0CH0 on Tomcat ist inverted... --- gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d0ch1.lpc | 4 ++-- gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d0ch1.vhd | 2 +- gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d1ch1.lpc | 4 ++-- gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d1ch1.vhd | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d0ch1.lpc b/gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d0ch1.lpc index a958ddd..b96e477 100644 --- a/gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d0ch1.lpc +++ b/gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d0ch1.lpc @@ -15,7 +15,7 @@ Date=07/26/2022 ModuleName=serdes_d0ch1 ParameterFileVersion=1.0 SourceFormat=vhdl -Time=10:09:05 +Time=10:44:26 VendorName=Lattice Semiconductor Corporation [Parameters] ;ACHARA=0 00H @@ -77,7 +77,7 @@ TXDEPOST=Disabled TXDEPRE=Disabled TXDIFFTERM=50 ohms TXFIFO_ENABLE=Enabled -TXINVPOL=Invert +TXINVPOL=Non-invert TXLDR=Off TXPLLLOLTHRESHOLD=1 TXPLLMULT=10X diff --git a/gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d0ch1.vhd b/gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d0ch1.vhd index 0746605..567160f 100644 --- a/gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d0ch1.vhd +++ b/gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d0ch1.vhd @@ -103,7 +103,7 @@ begin D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b0",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0", - CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b1",CH1_PRBS_SELECTION=>"0b0", + CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0", CH1_GE_AN_ENABLE=>"0b1",CH1_PRBS_LOCK=>"0b0",CH1_PRBS_ENABLE=>"0b0", CH1_ENABLE_CG_ALIGN=>"0b1",CH1_TX_GEAR_MODE=>"0b0",CH1_RX_GEAR_MODE=>"0b0", CH1_PCS_DET_TIME_SEL=>"0b00",CH1_PCIE_EI_EN=>"0b0",CH1_TX_GEAR_BYPASS=>"0b0", diff --git a/gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d1ch1.lpc b/gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d1ch1.lpc index 06626ce..40b4076 100644 --- a/gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d1ch1.lpc +++ b/gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d1ch1.lpc @@ -15,7 +15,7 @@ Date=07/26/2022 ModuleName=serdes_d1ch1 ParameterFileVersion=1.0 SourceFormat=vhdl -Time=10:11:42 +Time=10:43:42 VendorName=Lattice Semiconductor Corporation [Parameters] ;ACHARA=0 00H @@ -77,7 +77,7 @@ TXDEPOST=Disabled TXDEPRE=Disabled TXDIFFTERM=50 ohms TXFIFO_ENABLE=Enabled -TXINVPOL=Invert +TXINVPOL=Non-invert TXLDR=Off TXPLLLOLTHRESHOLD=1 TXPLLMULT=10X diff --git a/gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d1ch1.vhd b/gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d1ch1.vhd index e5ae638..abab1b7 100644 --- a/gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d1ch1.vhd +++ b/gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d1ch1.vhd @@ -103,7 +103,7 @@ begin D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b0",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0", - CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b1",CH1_PRBS_SELECTION=>"0b0", + CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0", CH1_GE_AN_ENABLE=>"0b1",CH1_PRBS_LOCK=>"0b0",CH1_PRBS_ENABLE=>"0b0", CH1_ENABLE_CG_ALIGN=>"0b1",CH1_TX_GEAR_MODE=>"0b0",CH1_RX_GEAR_MODE=>"0b0", CH1_PCS_DET_TIME_SEL=>"0b00",CH1_PCIE_EI_EN=>"0b0",CH1_TX_GEAR_BYPASS=>"0b0", -- 2.43.0