From 31584b5f5b61de2c60965957c4e41d5f009a5e43 Mon Sep 17 00:00:00 2001 From: Cahit Date: Tue, 27 Aug 2013 15:37:58 +0200 Subject: [PATCH] cbmtof corrections --- base/cbmtof.lpf | 46 +++++++++++++++++++++++++++++++++++++++++++++- cbmtof/cbmtof.vhd | 17 +++++++++-------- 2 files changed, 54 insertions(+), 9 deletions(-) diff --git a/base/cbmtof.lpf b/base/cbmtof.lpf index a3c2790..6f1137d 100644 --- a/base/cbmtof.lpf +++ b/base/cbmtof.lpf @@ -3,6 +3,50 @@ BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; BLOCK RD_DURING_WR_PATHS ; +################################################################# +# Basic Settings +################################################################# + +SYSCONFIG MCCLK_FREQ = 20; + +FREQUENCY PORT CLK_OSC 200 MHz; +FREQUENCY PORT CLK_EXT 200 MHz; +FREQUENCY PORT CLK_CM_* 125 MHz; + +################################################################# +# Reset Nets +################################################################# +GSR_NET NET "GSR_N"; + +################################################################# +# Locate Serdes and media interfaces +################################################################# +LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_0_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ; + +REGION "MEDIA_UPLINK" "R105C109D" 10 22; +REGION "REGION_SPI" "R2C109D" 15 22 DEVSIZE; + +LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; +LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; + +LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; + +MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; +MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; +MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset*" 30 ns; + +#REGION "MEDIA_UPLINK" "R90C95D" 13 25; +#REGION "REGION_SPI" "R13C150D" 12 16 DEVSIZE; +#REGION "REGION_IOBUF" "R10C43D" 88 86 DEVSIZE; + +#LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; +#LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; +#LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; + +#MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; +#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; + + ################################################################# # Clock I/O ################################################################# @@ -18,7 +62,7 @@ LOCATE COMP "CLK_CM_7" SITE "V17"; #CM8 LOCATE COMP "CLK_CM_8" SITE "V20"; #CM9 LOCATE COMP "CLK_EXT" SITE "C14"; #external DEFINE PORT GROUP "CLK_group" -"CLK_CM[*]" +"CLK_CM_*" "CLK_EXT" "CLK_OSC"; IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; diff --git a/cbmtof/cbmtof.vhd b/cbmtof/cbmtof.vhd index 417d152..a12b03b 100644 --- a/cbmtof/cbmtof.vhd +++ b/cbmtof/cbmtof.vhd @@ -13,9 +13,9 @@ use work.version.all; entity cbmtof is port( --Clocks - CLK_OSC : in std_logic; --for tdc measurements - CLK_CM : in std_logic_vector(8 downto 0); --from clock manager - CLK_EXT : in std_logic; + CLK_OSC : in std_logic; --for tdc measurements --200MHz + CLK_CM : in std_logic_vector(8 downto 0); --from clock manager --125MHz + CLK_EXT : in std_logic; --from CK_IN1 connection --Serdes --CLK_SERDES_INT_RIGHT : in std_logic; @@ -107,7 +107,7 @@ architecture cbmtof_arch of cbmtof is --Clock / Reset signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL - signal clk_20_i : std_logic; -- clock for calibrating the tdc, 20 MHz, via Clock Manager and internal PLL + signal clk_20_i : std_logic; --clock for calibrating the tdc, 20 MHz, via Clock Manager and internal PLL signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. signal clear_i : std_logic; signal reset_i : std_logic; @@ -297,16 +297,17 @@ begin THE_MAIN_PLL : pll_in200_out100 port map( - CLK => CLK_CM(4), + CLK => CLK_OSC, --CLK_CM(4), CLKOP => clk_100_i, CLKOK => clk_200_i, + CLKOS => open, LOCK => pll_lock ); -- generates hits for calibration uncorrelated with tdc clk THE_CALIBRATION_PLL : pll_in125_out20 port map ( - CLK => CLK_OSC, + CLK => CLK_CM(4), CLKOP => clk_20_i, CLKOK => open, --clk_125_i, LOCK => open); @@ -727,7 +728,7 @@ begin LVDS(1) <= or_all(INPUT); LVDS(2) <= SPARE_LINE(0); - CLK_MNGR_USER(3 downto 0) <= (others => '0'); +-- CLK_MNGR_USER(3 downto 0) <= (others => '0'); --------------------------------------------------------------------------- -- Test Circuits @@ -745,7 +746,7 @@ begin generic map ( CHANNEL_NUMBER => 5, -- Number of TDC channels CONTROL_REG_NR => 5, -- Number of control regs - TDC_VERSION => "001" & x"51") -- TDC version numberTDC_VERSION => "001" & x"51") -- TDC version number + TDC_VERSION => "001" & x"51") -- TDC version numberTDC_VERSION => "001" & x"51") -- TDC version number port map ( RESET => reset_i, CLK_TDC => CLK_OSC, -- Clock used for the time measurement -- 2.43.0