From 31affb7915485fa3683d95998e9eeb3f71e9cb86 Mon Sep 17 00:00:00 2001 From: Ludwig Maier Date: Thu, 19 Dec 2013 13:39:18 +0100 Subject: [PATCH] rearrangement of files --- 0x4c168bfe/adcmv3.lpf | 0 adcmv3.lpf | 472 ++++++++++++++++++ adcmv3.prj | 137 ++--- design/adcmv3.vhd => adcmv3.vhd | 0 cleanup_workdir.sh | 18 + compile.pl | 4 +- compile_ORIG.pl => compile_munich21.pl | 83 +-- compile_munich21.sh | 6 + constraints_adcmv3.lpf | 0 constraints_adcmv3_BACK.lpf | 0 {design => cores}/adc_apv_map_mem.lpc | 0 {design => cores}/adc_apv_map_mem.vhd | 0 {design => cores}/adc_ch_in.lpc | 0 {design => cores}/adc_ch_in.vhd | 0 {design => cores}/adc_onewire_map_mem.lpc | 0 {design => cores}/adc_onewire_map_mem.vhd | 0 {design => cores}/adc_pll.lpc | 0 {design => cores}/adc_pll.vhd | 0 {design => cores}/adc_snoop_mem.lpc | 0 {design => cores}/adc_snoop_mem.vhd | 0 {design => cores}/apv_adc_map_mem.lpc | 0 {design => cores}/apv_adc_map_mem.vhd | 0 {design => cores}/apv_map_mem.lpc | 0 {design => cores}/apv_map_mem.vhd | 0 {design => cores}/crossover.lpc | 0 {design => cores}/crossover.vhd | 0 {design => cores}/decoder_8bit.lpc | 0 {design => cores}/decoder_8bit.mem | 0 {design => cores}/decoder_8bit.vhd | 0 {design => cores}/dll_100m.lpc | 0 {design => cores}/dll_100m.vhd | 0 {design => cores}/dpram_8x19.lpc | 0 {design => cores}/dpram_8x19.vhd | 0 {design => cores}/eds_buffer_dpram.lpc | 0 {design => cores}/eds_buffer_dpram.vhd | 0 {design => cores}/fifo_16x11.lpc | 0 {design => cores}/fifo_16x11.vhd | 0 {design => cores}/fifo_1kx18.lpc | 0 {design => cores}/fifo_1kx18.vhd | 0 {design => cores}/fifo_2kx27.lpc | 0 {design => cores}/fifo_2kx27.vhd | 0 {design => cores}/frame_status_mem.lpc | 0 {design => cores}/frame_status_mem.vhd | 0 {design => cores}/input_bram.lpc | 0 {design => cores}/input_bram.vhd | 0 {design => cores}/mult_3x8.lpc | 0 {design => cores}/mult_3x8.vhd | 0 {design => cores}/onewire_spare_one.lpc | 0 {design => cores}/onewire_spare_one.vhd | 0 {design => cores}/ped_thr_true.lpc | 0 {design => cores}/ped_thr_true.vhd | 0 {design => cores}/pll_40m.lpc | 0 {design => cores}/pll_40m.vhd | 0 {design => cores}/slv_onewire_dpram.lpc | 0 {design => cores}/slv_onewire_dpram.vhd | 0 {design => cores}/sync_pll_40m.lpc | 0 {design => cores}/sync_pll_40m.vhd | 0 {design => cores}/test_fifo.lpc | 0 {design => cores}/test_fifo.vhd | 0 {design => cores}/test_fifo2.lpc | 0 {design => cores}/test_fifo2.vhd | 0 {design => cores}/testfifo.lpc | 0 {design => cores}/testfifo.vhd | 0 debug_pin.txt | 0 featurelist.txt | 0 howto_adcm_i2c.txt | 0 lever/.recordref | 0 lever/adcmv3.ini | 0 lever/adcmv3.jid | 0 lever/adcmv3.lci | 0 lever/adcmv3.lct | 0 lever/adcmv3.lpf | 0 lever/adcmv3.mt | 0 lever/adcmv3.pt | 0 lever/adcmv3.rev | 0 lever/adcmv3.rvp | 0 lever/adcmv3.sty | 0 lever/adcmv3.syn | 0 lever/adcmv3.syn.bak | 0 lever/adcmv3.tcl | 0 lever/adcmv3_tcl.ini | 0 lever/chipsim.err | 0 lever/fifo_18x16_media_interface.vht | 0 lever/fifo_18x16_media_interface_mb.vht | 0 lever/pre.clr | 0 lever/run_options.txt | 0 lever/sbuf.cmd | 0 lever/sbuf.edi | 0 lever/sbuf.fse | 0 lever/sbuf.srd | Bin lever/sbuf.srf | 0 lever/sbuf.szr | Bin lever/syntmp/hdlorder.tcl | 0 lever/syntmp/sbuf.plg | 0 lever/tb_apv_trgctrl.rsp | 0 lever/tb_apv_trgctrl_activehdl.do | 0 lever/tb_apv_trgctrl_activehdl2.do | 0 lever/tb_apv_trgctrl_vhdf.udo | 0 lever/tb_media_fifo.rsp | 0 lever/tb_media_fifo_activehdl.do | 0 lever/tb_media_fifo_activehdl2.do | 0 lever/tb_media_fifo_mb.rsp | 0 lever/tb_media_fifo_mb_activehdl.do | 0 lever/tb_media_fifo_mb_activehdl2.do | 0 lever/tb_media_fifo_mb_vhdf.udo | 0 lever/tb_media_fifo_vhdf.udo | 0 lever/tb_ped_corr_ctrl.rsp | 0 lever/tb_ped_corr_ctrl_activehdl.do | 0 lever/tb_ped_corr_ctrl_activehdl2.do | 0 lever/tb_ped_corr_ctrl_vhdf.udo | 0 lever/tb_sfp_rx_handler.rsp | 0 lever/tb_sfp_rx_handler_activehdl.do | 0 lever/tb_sfp_rx_handler_activehdl2.do | 0 lever/tb_sfp_rx_handler_vhdf.udo | 0 lever/tb_spi_master.fado | 0 lever/tb_spi_master.rsp | 0 lever/tb_spi_master_activehdl.do | 0 lever/tb_spi_master_activehdl2.do | 0 lever/tb_spi_master_vhdf.udo | 0 lever/tb_test_media.rsp | 0 lever/tb_test_media_activehdl.do | 0 lever/tb_test_media_activehdl2.do | 0 lever/tb_test_media_vhdf.udo | 0 lever/test_media.vht | 0 lever/udo.rsp | 0 lever/work.sbuf.prj | 0 lever/work/0work.mgf | Bin lever/work/1work.mgf | 0 lever/work/3work.mgf | Bin lever/work/Edfmap.ini | 0 lever/work/compilation.order | 0 lever/work/compile.cfg | 0 lever/work/compile/contents.lib~work | 7 - lever/work/compile/sources.sth | 0 lever/work/compile/work.cmd | 0 lever/work/compile/work.epr | 0 lever/work/compile/work.erf | 0 lever/work/library.cfg | 0 lever/work/projlib.cfg | 0 lever/work/work.LIB | 0 lever/work/work.adf | 0 lever/work/work.aws | 0 lever/work/work.wsp | 0 lever/work/work.wsw | 0 sim/tb_adc_cross.vhd | 0 sim/tb_adc_crossover.vhd | 0 sim/tb_adc_handler.vhd | 0 sim/tb_adc_handler.vhd.bak | 0 sim/tb_apv_locker.vhd | 0 sim/tb_apv_pc_nc_alu.vhd | 0 sim/tb_apv_trgctrl.vhd | 0 sim/tb_apv_trgctrl.vhd.bak | 0 sim/tb_apv_trgctrl_000.vhd | 0 sim/tb_crossfifo.vhd | 0 sim/tb_crossover.vhd | 0 sim/tb_ipu_fifo_stage.vhd | 0 sim/tb_ipu_fifo_stage.vhd.bak | 0 sim/tb_ipu_fifo_stage_COPY.vhd | 0 sim/tb_ipu_fifo_stage_OLD.vhd | 0 sim/tb_logic_analyzer.vhd | 0 sim/tb_max_data.vhd | 0 sim/tb_media_fifo.vhd | 0 sim/tb_media_fifo.vhd.bak | 0 sim/tb_media_fifo_mb.vhd | 0 sim/tb_media_fifo_mb.vhd.bak | 0 sim/tb_mult_3x8.vhd | 0 sim/tb_my_sbuf.vhd | 0 sim/tb_onewire_master.vhd | 0 sim/tb_ped_corr_ctrl.vhd | 0 sim/tb_ped_corr_ctrl.vhd.bak | 0 sim/tb_ped_corr_ctrl_OLD.vhd | 0 sim/tb_pulse_stretch.vhd | 0 sim/tb_pulse_sync.vhd | 0 sim/tb_raw_buf_stage.vhd | 0 sim/tb_raw_buf_stage_new.vhd | 0 sim/tb_real_trg_handler.vhd | 0 sim/tb_reboot_handler.vhd | 0 sim/tb_reset_handler.vhd | 0 sim/tb_sfp_rx_handler.vhd | 0 sim/tb_sfp_rx_handler.vhd.bak | 0 sim/tb_slv_adc_la.vhd | 0 sim/tb_slv_adc_snoop.vhd | 0 sim/tb_slv_onewire_memory.vhd | 0 sim/tb_slv_ped_thr_mem.vhd | 0 sim/tb_slv_register_bank.vhd | 0 sim/tb_spi_master.vhd | 0 sim/tb_spi_master.vhd.bak | 0 sim/tb_spi_master_0.vhd | 0 sim/tb_spi_real_slim.vhd | 0 sim/tb_test_media.vhd | 0 sim/tb_test_media.vhd.bak | 0 sim/tb_trb_net16_ibuf2.vhd | 0 sim/tb_trb_net_sbuf2.vhd | 0 sim/tb_trb_net_sbuf3.vhd | 0 {design => source}/adc_apv_mapping.mem | 0 {design => source}/adc_channel_select.vhd | 0 {design => source}/adc_crossover.vhd | 0 {design => source}/adc_data_handler.vhd | 0 {design => source}/adc_onewire_mapping.mem | 0 {design => source}/adc_twochannels.vhd | 0 {design => source}/adcmv3_components.vhd | 0 {design => source}/adcmv3_testfifo.vhd | 0 {design => source}/apv_adc_mapping.mem | 0 {design => source}/apv_digital.vhd | 0 {design => source}/apv_lock_sm.vhd | 0 {design => source}/apv_locker.vhd | 0 {design => source}/apv_mapping.mem | 0 {design => source}/apv_pc_nc_alu.vhd | 0 {design => source}/apv_raw_buffer.vhd | 0 {design => source}/apv_sync_handler.vhd | 0 {design => source}/apv_trg_handler.vhd | 0 {design => source}/apv_trgctrl.vhd | 0 {design => source}/buf_toc.vhd | 0 {design => source}/dbg_reg.vhd | 0 {design => source}/eds_buf.vhd | 0 {design => source}/frmctr_check.vhd | 0 {design => source}/i2c_gstart.vhd | 0 {design => source}/i2c_master.vhd | 0 {design => source}/i2c_sendb.vhd | 0 {design => source}/i2c_slim.vhd | 0 {design => source}/ipu_fifo_stage.vhd | 0 {design => source}/ipu_fifo_stage_BACK.vhd | 0 {design => source}/logic_analyzer.vhd | 0 {design => source}/max_data.vhd | 0 {design => source}/my_sbuf.vhd | 0 {design => source}/onewire_master.vhd | 0 {design => source}/ped_corr_ctrl.vhd | 0 {design => source}/ped_thr_mem.mem | 0 {design => source}/pulse_stretch.vhd | 0 {design => source}/pulse_sync.vhd | 0 {design => source}/raw_buf_stage.vhd | 0 {design => source}/real_trg_handler.vhd | 0 .../real_trg_handler_BACKUP.vhd | 0 {design => source}/reboot_handler.vhd | 0 {design => source}/ref_row_sel.vhd | 0 {design => source}/replacement.vhd | 0 {design => source}/reset_handler.vhd | 0 {design => source}/rich_trb.vhd | 4 +- {design => source}/sbuf.vhd | 0 {design => source}/sfp_rx_handler.vhd | 0 {design => source}/sfp_rx_handler_BACK2.vhd | 0 {design => source}/sfp_rx_handler_BACK_0.vhd | 0 {design => source}/slave_bus.vhd | 0 {design => source}/slv_adc_la.vhd | 0 {design => source}/slv_adc_snoop.vhd | 0 {design => source}/slv_half_register.vhd | 0 {design => source}/slv_memory_true.vhd | 0 {design => source}/slv_onewire_memory.vhd | 0 {design => source}/slv_ped_thr_mem.vhd | 0 {design => source}/slv_register.vhd | 0 {design => source}/slv_register_bank.vhd | 0 {design => source}/slv_status.vhd | 0 {design => source}/slv_status_bank.vhd | 0 {design => source}/spare_onewire_mapping.mem | 0 {design => source}/spi_adc_master.vhd | 0 {design => source}/spi_real_slim.vhd | 0 {design => source}/state_sync.vhd | 0 {design => source}/tb_count_unit.vhd | 0 {design => source}/tb_count_unit.vhd.bak | 0 {design => source}/test_media.vhd | 0 test.txt | 0 tunnel.sh | 0 262 files changed, 616 insertions(+), 115 deletions(-) mode change 100755 => 100644 0x4c168bfe/adcmv3.lpf create mode 100755 adcmv3.lpf mode change 100755 => 100644 adcmv3.prj rename design/adcmv3.vhd => adcmv3.vhd (100%) mode change 100755 => 100644 create mode 100755 cleanup_workdir.sh rename compile_ORIG.pl => compile_munich21.pl (52%) create mode 100755 compile_munich21.sh mode change 100755 => 100644 constraints_adcmv3.lpf mode change 100755 => 100644 constraints_adcmv3_BACK.lpf rename {design => cores}/adc_apv_map_mem.lpc (100%) rename {design => cores}/adc_apv_map_mem.vhd (100%) rename {design => cores}/adc_ch_in.lpc (100%) rename {design => cores}/adc_ch_in.vhd (100%) rename {design => cores}/adc_onewire_map_mem.lpc (100%) rename {design => cores}/adc_onewire_map_mem.vhd (100%) rename {design => cores}/adc_pll.lpc (100%) rename {design => cores}/adc_pll.vhd (100%) rename {design => cores}/adc_snoop_mem.lpc (100%) rename {design => cores}/adc_snoop_mem.vhd (100%) rename {design => cores}/apv_adc_map_mem.lpc (100%) rename {design => cores}/apv_adc_map_mem.vhd (100%) rename {design => cores}/apv_map_mem.lpc (100%) rename {design => cores}/apv_map_mem.vhd (100%) rename {design => cores}/crossover.lpc (100%) rename {design => cores}/crossover.vhd (100%) rename {design => cores}/decoder_8bit.lpc (100%) rename {design => cores}/decoder_8bit.mem (100%) rename {design => cores}/decoder_8bit.vhd (100%) rename {design => cores}/dll_100m.lpc (100%) rename {design => cores}/dll_100m.vhd (100%) rename {design => cores}/dpram_8x19.lpc (100%) rename {design => cores}/dpram_8x19.vhd (100%) rename {design => cores}/eds_buffer_dpram.lpc (100%) rename {design => cores}/eds_buffer_dpram.vhd (100%) rename {design => cores}/fifo_16x11.lpc (100%) rename {design => cores}/fifo_16x11.vhd (100%) rename {design => cores}/fifo_1kx18.lpc (100%) rename {design => cores}/fifo_1kx18.vhd (100%) rename {design => cores}/fifo_2kx27.lpc (100%) rename {design => cores}/fifo_2kx27.vhd (100%) rename {design => cores}/frame_status_mem.lpc (100%) rename {design => cores}/frame_status_mem.vhd (100%) rename {design => cores}/input_bram.lpc (100%) rename {design => cores}/input_bram.vhd (100%) rename {design => cores}/mult_3x8.lpc (100%) rename {design => cores}/mult_3x8.vhd (100%) rename {design => cores}/onewire_spare_one.lpc (100%) rename {design => cores}/onewire_spare_one.vhd (100%) rename {design => cores}/ped_thr_true.lpc (100%) rename {design => cores}/ped_thr_true.vhd (100%) rename {design => cores}/pll_40m.lpc (100%) rename {design => cores}/pll_40m.vhd (100%) rename {design => cores}/slv_onewire_dpram.lpc (100%) rename {design => cores}/slv_onewire_dpram.vhd (100%) rename {design => cores}/sync_pll_40m.lpc (100%) rename {design => cores}/sync_pll_40m.vhd (100%) rename {design => cores}/test_fifo.lpc (100%) rename {design => cores}/test_fifo.vhd (100%) rename {design => cores}/test_fifo2.lpc (100%) rename {design => cores}/test_fifo2.vhd (100%) rename {design => cores}/testfifo.lpc (100%) rename {design => cores}/testfifo.vhd (100%) mode change 100755 => 100644 debug_pin.txt mode change 100755 => 100644 featurelist.txt mode change 100755 => 100644 howto_adcm_i2c.txt mode change 100755 => 100644 lever/.recordref mode change 100755 => 100644 lever/adcmv3.ini mode change 100755 => 100644 lever/adcmv3.jid mode change 100755 => 100644 lever/adcmv3.lci mode change 100755 => 100644 lever/adcmv3.lct mode change 100755 => 100644 lever/adcmv3.lpf mode change 100755 => 100644 lever/adcmv3.mt mode change 100755 => 100644 lever/adcmv3.pt mode change 100755 => 100644 lever/adcmv3.rev mode change 100755 => 100644 lever/adcmv3.rvp mode change 100755 => 100644 lever/adcmv3.sty mode change 100755 => 100644 lever/adcmv3.syn mode change 100755 => 100644 lever/adcmv3.syn.bak mode change 100755 => 100644 lever/adcmv3.tcl mode change 100755 => 100644 lever/adcmv3_tcl.ini mode change 100755 => 100644 lever/chipsim.err mode change 100755 => 100644 lever/fifo_18x16_media_interface.vht mode change 100755 => 100644 lever/fifo_18x16_media_interface_mb.vht mode change 100755 => 100644 lever/pre.clr mode change 100755 => 100644 lever/run_options.txt mode change 100755 => 100644 lever/sbuf.cmd mode change 100755 => 100644 lever/sbuf.edi mode change 100755 => 100644 lever/sbuf.fse mode change 100755 => 100644 lever/sbuf.srd mode change 100755 => 100644 lever/sbuf.srf mode change 100755 => 100644 lever/sbuf.szr mode change 100755 => 100644 lever/syntmp/hdlorder.tcl mode change 100755 => 100644 lever/syntmp/sbuf.plg mode change 100755 => 100644 lever/tb_apv_trgctrl.rsp mode change 100755 => 100644 lever/tb_apv_trgctrl_activehdl.do mode change 100755 => 100644 lever/tb_apv_trgctrl_activehdl2.do mode change 100755 => 100644 lever/tb_apv_trgctrl_vhdf.udo mode change 100755 => 100644 lever/tb_media_fifo.rsp mode change 100755 => 100644 lever/tb_media_fifo_activehdl.do mode change 100755 => 100644 lever/tb_media_fifo_activehdl2.do mode change 100755 => 100644 lever/tb_media_fifo_mb.rsp mode change 100755 => 100644 lever/tb_media_fifo_mb_activehdl.do mode change 100755 => 100644 lever/tb_media_fifo_mb_activehdl2.do mode change 100755 => 100644 lever/tb_media_fifo_mb_vhdf.udo mode change 100755 => 100644 lever/tb_media_fifo_vhdf.udo mode change 100755 => 100644 lever/tb_ped_corr_ctrl.rsp mode change 100755 => 100644 lever/tb_ped_corr_ctrl_activehdl.do mode change 100755 => 100644 lever/tb_ped_corr_ctrl_activehdl2.do mode change 100755 => 100644 lever/tb_ped_corr_ctrl_vhdf.udo mode change 100755 => 100644 lever/tb_sfp_rx_handler.rsp mode change 100755 => 100644 lever/tb_sfp_rx_handler_activehdl.do mode change 100755 => 100644 lever/tb_sfp_rx_handler_activehdl2.do mode change 100755 => 100644 lever/tb_sfp_rx_handler_vhdf.udo mode change 100755 => 100644 lever/tb_spi_master.fado mode change 100755 => 100644 lever/tb_spi_master.rsp mode change 100755 => 100644 lever/tb_spi_master_activehdl.do mode change 100755 => 100644 lever/tb_spi_master_activehdl2.do mode change 100755 => 100644 lever/tb_spi_master_vhdf.udo mode change 100755 => 100644 lever/tb_test_media.rsp mode change 100755 => 100644 lever/tb_test_media_activehdl.do mode change 100755 => 100644 lever/tb_test_media_activehdl2.do mode change 100755 => 100644 lever/tb_test_media_vhdf.udo mode change 100755 => 100644 lever/test_media.vht mode change 100755 => 100644 lever/udo.rsp mode change 100755 => 100644 lever/work.sbuf.prj mode change 100755 => 100644 lever/work/0work.mgf mode change 100755 => 100644 lever/work/1work.mgf mode change 100755 => 100644 lever/work/3work.mgf mode change 100755 => 100644 lever/work/Edfmap.ini mode change 100755 => 100644 lever/work/compilation.order mode change 100755 => 100644 lever/work/compile.cfg delete mode 100755 lever/work/compile/contents.lib~work mode change 100755 => 100644 lever/work/compile/sources.sth mode change 100755 => 100644 lever/work/compile/work.cmd mode change 100755 => 100644 lever/work/compile/work.epr mode change 100755 => 100644 lever/work/compile/work.erf mode change 100755 => 100644 lever/work/library.cfg mode change 100755 => 100644 lever/work/projlib.cfg mode change 100755 => 100644 lever/work/work.LIB mode change 100755 => 100644 lever/work/work.adf mode change 100755 => 100644 lever/work/work.aws mode change 100755 => 100644 lever/work/work.wsp mode change 100755 => 100644 lever/work/work.wsw mode change 100755 => 100644 sim/tb_adc_cross.vhd mode change 100755 => 100644 sim/tb_adc_crossover.vhd mode change 100755 => 100644 sim/tb_adc_handler.vhd mode change 100755 => 100644 sim/tb_adc_handler.vhd.bak mode change 100755 => 100644 sim/tb_apv_locker.vhd mode change 100755 => 100644 sim/tb_apv_pc_nc_alu.vhd mode change 100755 => 100644 sim/tb_apv_trgctrl.vhd mode change 100755 => 100644 sim/tb_apv_trgctrl.vhd.bak mode change 100755 => 100644 sim/tb_apv_trgctrl_000.vhd mode change 100755 => 100644 sim/tb_crossfifo.vhd mode change 100755 => 100644 sim/tb_crossover.vhd mode change 100755 => 100644 sim/tb_ipu_fifo_stage.vhd mode change 100755 => 100644 sim/tb_ipu_fifo_stage.vhd.bak mode change 100755 => 100644 sim/tb_ipu_fifo_stage_COPY.vhd mode change 100755 => 100644 sim/tb_ipu_fifo_stage_OLD.vhd mode change 100755 => 100644 sim/tb_logic_analyzer.vhd mode change 100755 => 100644 sim/tb_max_data.vhd mode change 100755 => 100644 sim/tb_media_fifo.vhd mode change 100755 => 100644 sim/tb_media_fifo.vhd.bak mode change 100755 => 100644 sim/tb_media_fifo_mb.vhd mode change 100755 => 100644 sim/tb_media_fifo_mb.vhd.bak mode change 100755 => 100644 sim/tb_mult_3x8.vhd mode change 100755 => 100644 sim/tb_my_sbuf.vhd mode change 100755 => 100644 sim/tb_onewire_master.vhd mode change 100755 => 100644 sim/tb_ped_corr_ctrl.vhd mode change 100755 => 100644 sim/tb_ped_corr_ctrl.vhd.bak mode change 100755 => 100644 sim/tb_ped_corr_ctrl_OLD.vhd mode change 100755 => 100644 sim/tb_pulse_stretch.vhd mode change 100755 => 100644 sim/tb_pulse_sync.vhd mode change 100755 => 100644 sim/tb_raw_buf_stage.vhd mode change 100755 => 100644 sim/tb_raw_buf_stage_new.vhd mode change 100755 => 100644 sim/tb_real_trg_handler.vhd mode change 100755 => 100644 sim/tb_reboot_handler.vhd mode change 100755 => 100644 sim/tb_reset_handler.vhd mode change 100755 => 100644 sim/tb_sfp_rx_handler.vhd mode change 100755 => 100644 sim/tb_sfp_rx_handler.vhd.bak mode change 100755 => 100644 sim/tb_slv_adc_la.vhd mode change 100755 => 100644 sim/tb_slv_adc_snoop.vhd mode change 100755 => 100644 sim/tb_slv_onewire_memory.vhd mode change 100755 => 100644 sim/tb_slv_ped_thr_mem.vhd mode change 100755 => 100644 sim/tb_slv_register_bank.vhd mode change 100755 => 100644 sim/tb_spi_master.vhd mode change 100755 => 100644 sim/tb_spi_master.vhd.bak mode change 100755 => 100644 sim/tb_spi_master_0.vhd mode change 100755 => 100644 sim/tb_spi_real_slim.vhd mode change 100755 => 100644 sim/tb_test_media.vhd mode change 100755 => 100644 sim/tb_test_media.vhd.bak mode change 100755 => 100644 sim/tb_trb_net16_ibuf2.vhd mode change 100755 => 100644 sim/tb_trb_net_sbuf2.vhd mode change 100755 => 100644 sim/tb_trb_net_sbuf3.vhd rename {design => source}/adc_apv_mapping.mem (100%) rename {design => source}/adc_channel_select.vhd (100%) rename {design => source}/adc_crossover.vhd (100%) mode change 100755 => 100644 rename {design => source}/adc_data_handler.vhd (100%) mode change 100755 => 100644 rename {design => source}/adc_onewire_mapping.mem (100%) rename {design => source}/adc_twochannels.vhd (100%) rename {design => source}/adcmv3_components.vhd (100%) mode change 100755 => 100644 rename {design => source}/adcmv3_testfifo.vhd (100%) rename {design => source}/apv_adc_mapping.mem (100%) rename {design => source}/apv_digital.vhd (100%) rename {design => source}/apv_lock_sm.vhd (100%) rename {design => source}/apv_locker.vhd (100%) rename {design => source}/apv_mapping.mem (100%) rename {design => source}/apv_pc_nc_alu.vhd (100%) mode change 100755 => 100644 rename {design => source}/apv_raw_buffer.vhd (100%) mode change 100755 => 100644 rename {design => source}/apv_sync_handler.vhd (100%) rename {design => source}/apv_trg_handler.vhd (100%) rename {design => source}/apv_trgctrl.vhd (100%) mode change 100755 => 100644 rename {design => source}/buf_toc.vhd (100%) rename {design => source}/dbg_reg.vhd (100%) mode change 100755 => 100644 rename {design => source}/eds_buf.vhd (100%) rename {design => source}/frmctr_check.vhd (100%) rename {design => source}/i2c_gstart.vhd (100%) rename {design => source}/i2c_master.vhd (100%) rename {design => source}/i2c_sendb.vhd (100%) rename {design => source}/i2c_slim.vhd (100%) rename {design => source}/ipu_fifo_stage.vhd (100%) mode change 100755 => 100644 rename {design => source}/ipu_fifo_stage_BACK.vhd (100%) rename {design => source}/logic_analyzer.vhd (100%) rename {design => source}/max_data.vhd (100%) rename {design => source}/my_sbuf.vhd (100%) rename {design => source}/onewire_master.vhd (100%) rename {design => source}/ped_corr_ctrl.vhd (100%) mode change 100755 => 100644 rename {design => source}/ped_thr_mem.mem (100%) rename {design => source}/pulse_stretch.vhd (100%) mode change 100755 => 100644 rename {design => source}/pulse_sync.vhd (100%) mode change 100755 => 100644 rename {design => source}/raw_buf_stage.vhd (100%) mode change 100755 => 100644 rename {design => source}/real_trg_handler.vhd (100%) mode change 100755 => 100644 rename {design => source}/real_trg_handler_BACKUP.vhd (100%) mode change 100755 => 100644 rename {design => source}/reboot_handler.vhd (100%) mode change 100755 => 100644 rename {design => source}/ref_row_sel.vhd (100%) rename {design => source}/replacement.vhd (100%) rename {design => source}/reset_handler.vhd (100%) mode change 100755 => 100644 rename {design => source}/rich_trb.vhd (98%) mode change 100755 => 100644 rename {design => source}/sbuf.vhd (100%) mode change 100755 => 100644 rename {design => source}/sfp_rx_handler.vhd (100%) mode change 100755 => 100644 rename {design => source}/sfp_rx_handler_BACK2.vhd (100%) mode change 100755 => 100644 rename {design => source}/sfp_rx_handler_BACK_0.vhd (100%) mode change 100755 => 100644 rename {design => source}/slave_bus.vhd (100%) mode change 100755 => 100644 rename {design => source}/slv_adc_la.vhd (100%) rename {design => source}/slv_adc_snoop.vhd (100%) rename {design => source}/slv_half_register.vhd (100%) rename {design => source}/slv_memory_true.vhd (100%) rename {design => source}/slv_onewire_memory.vhd (100%) mode change 100755 => 100644 rename {design => source}/slv_ped_thr_mem.vhd (100%) rename {design => source}/slv_register.vhd (100%) rename {design => source}/slv_register_bank.vhd (100%) rename {design => source}/slv_status.vhd (100%) rename {design => source}/slv_status_bank.vhd (100%) rename {design => source}/spare_onewire_mapping.mem (100%) rename {design => source}/spi_adc_master.vhd (100%) rename {design => source}/spi_real_slim.vhd (100%) rename {design => source}/state_sync.vhd (100%) mode change 100755 => 100644 rename {design => source}/tb_count_unit.vhd (100%) mode change 100755 => 100644 rename {design => source}/tb_count_unit.vhd.bak (100%) mode change 100755 => 100644 rename {design => source}/test_media.vhd (100%) mode change 100755 => 100644 mode change 100755 => 100644 test.txt mode change 100644 => 100755 tunnel.sh diff --git a/0x4c168bfe/adcmv3.lpf b/0x4c168bfe/adcmv3.lpf old mode 100755 new mode 100644 diff --git a/adcmv3.lpf b/adcmv3.lpf new file mode 100755 index 0000000..c701a7c --- /dev/null +++ b/adcmv3.lpf @@ -0,0 +1,472 @@ +###################################################################### +# ADCMv3 pinouts +###################################################################### + +COMMERCIAL; +BLOCK RESETPATHS; +BLOCK ASYNCPATHS; + +###################################################################### +# I/O bank 8 - 3.30V +# JTAG and SPI boot interface +###################################################################### +# +# These signals are not user definable! Hands off! + +###################################################################### +# I/O bank 7 - 2.50V +# APV1 control signals, ADC1 inputs +###################################################################### +LOCATE COMP "APV1A_CLK" SITE "J8" ; +IOBUF PORT "APV1A_CLK" IO_TYPE=LVDS25 ; +LOCATE COMP "APV1B_CLK" SITE "G5" ; +IOBUF PORT "APV1B_CLK" IO_TYPE=LVDS25 ; +LOCATE COMP "APV1A_TRG" SITE "L5" ; +IOBUF PORT "APV1A_TRG" IO_TYPE=LVDS25 ; +LOCATE COMP "APV1B_TRG" SITE "G6" ; +IOBUF PORT "APV1B_TRG" IO_TYPE=LVDS25 ; +LOCATE COMP "APV1_SDA" SITE "K7" ; +IOBUF PORT "APV1_SDA" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 ; +LOCATE COMP "APV1_SCL" SITE "K6" ; +IOBUF PORT "APV1_SCL" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 ; +LOCATE COMP "APV1_RST" SITE "K5" ; +IOBUF PORT "APV1_RST" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 ; +LOCATE COMP "ADC1_LCLK" SITE "L3" ; +IOBUF PORT "ADC1_LCLK" IO_TYPE=LVDS25 ; +LOCATE COMP "ADC1_ADCLK" SITE "D2" ; +IOBUF PORT "ADC1_ADCLK" IO_TYPE=LVDS25 ; +LOCATE COMP "ADC1_OUT_7" SITE "E2" ; +IOBUF PORT "ADC1_OUT_7" IO_TYPE=LVDS25 ; +LOCATE COMP "ADC1_OUT_6" SITE "G2" ; +IOBUF PORT "ADC1_OUT_6" IO_TYPE=LVDS25 ; +LOCATE COMP "ADC1_OUT_5" SITE "J5" ; +IOBUF PORT "ADC1_OUT_5" IO_TYPE=LVDS25 ; +LOCATE COMP "ADC1_OUT_4" SITE "J3" ; +IOBUF PORT "ADC1_OUT_4" IO_TYPE=LVDS25 ; +LOCATE COMP "ADC1_OUT_3" SITE "K2" ; +IOBUF PORT "ADC1_OUT_3" IO_TYPE=LVDS25 ; +LOCATE COMP "ADC1_OUT_2" SITE "N5" ; +IOBUF PORT "ADC1_OUT_2" IO_TYPE=LVDS25 ; +LOCATE COMP "ADC1_OUT_1" SITE "M4" ; +IOBUF PORT "ADC1_OUT_1" IO_TYPE=LVDS25 ; +LOCATE COMP "ADC1_OUT_0" SITE "P3" ; +IOBUF PORT "ADC1_OUT_0" IO_TYPE=LVDS25 ; + +LOCATE COMP "ADC1_CLK" SITE "H2" ; +IOBUF PORT "ADC1_CLK" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ; +LOCATE COMP "ADC1_RST" SITE "G3" ; +IOBUF PORT "ADC1_RST" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8 ; +LOCATE COMP "ADC1_CS" SITE "E1" ; +IOBUF PORT "ADC1_CS" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8 ; +LOCATE COMP "ADC1_PD" SITE "H1" ; +IOBUF PORT "ADC1_PD" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8 ; +LOCATE COMP "ADC1_SDI" SITE "F2" ; +IOBUF PORT "ADC1_SDI" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ; +LOCATE COMP "ADC1_SCK" SITE "F1" ; +IOBUF PORT "ADC1_SCK" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ; +LOCATE COMP "FPGA_LED_ADC_1" SITE "H3" ; +IOBUF PORT "FPGA_LED_ADC_1" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ; + +# LOCATE COMP "ADC1_DEBUG" SITE "H4" ; +# IOBUF PORT "ADC1_DEBUG" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ; + +# short cut pins for FPGA placement control by JTAG +# LOCATE COMP "PIN_CHECK_7_IN" SITE "E3" ; +# LOCATE COMP "PIN_CHECK_7_OUT" SITE "E4" ; + + +###################################################################### +# I/O bank 6 - 2.50V +# APV0 control signals, ADC0 inputs, 12 test outputs to pads +###################################################################### +LOCATE COMP "APV0A_CLK" SITE "AC7" ; +IOBUF PORT "APV0A_CLK" IO_TYPE=LVDS25 ; +LOCATE COMP "APV0B_CLK" SITE "W3" ; +IOBUF PORT "APV0B_CLK" IO_TYPE=LVDS25 ; +LOCATE COMP "APV0A_TRG" SITE "Y9" ; +IOBUF PORT "APV0A_TRG" IO_TYPE=LVDS25 ; +LOCATE COMP "APV0B_TRG" SITE "AB4" ; +IOBUF PORT "APV0B_TRG" IO_TYPE=LVDS25 ; +LOCATE COMP "APV0_SDA" SITE "Y6" ; +IOBUF PORT "APV0_SDA" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 ; +LOCATE COMP "APV0_SCL" SITE "AA6" ; +IOBUF PORT "APV0_SCL" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 ; +LOCATE COMP "APV0_RST" SITE "AA5" ; +IOBUF PORT "APV0_RST" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 ; +LOCATE COMP "ADC0_LCLK" SITE "T3" ; +IOBUF PORT "ADC0_LCLK" IO_TYPE=LVDS25 ; +LOCATE COMP "ADC0_ADCLK" SITE "R3" ; +IOBUF PORT "ADC0_ADCLK" IO_TYPE=LVDS25 ; +LOCATE COMP "ADC0_OUT_7" SITE "T5" ; +IOBUF PORT "ADC0_OUT_7" IO_TYPE=LVDS25 ; +LOCATE COMP "ADC0_OUT_6" SITE "U3" ; +IOBUF PORT "ADC0_OUT_6" IO_TYPE=LVDS25 ; +LOCATE COMP "ADC0_OUT_5" SITE "U5" ; +IOBUF PORT "ADC0_OUT_5" IO_TYPE=LVDS25 ; +LOCATE COMP "ADC0_OUT_4" SITE "Y1" ; +IOBUF PORT "ADC0_OUT_4" IO_TYPE=LVDS25 ; +LOCATE COMP "ADC0_OUT_3" SITE "AA1" ; +IOBUF PORT "ADC0_OUT_3" IO_TYPE=LVDS25 ; +LOCATE COMP "ADC0_OUT_2" SITE "AB2" ; +IOBUF PORT "ADC0_OUT_2" IO_TYPE=LVDS25 ; +LOCATE COMP "ADC0_OUT_1" SITE "AC1" ; +IOBUF PORT "ADC0_OUT_1" IO_TYPE=LVDS25 ; +LOCATE COMP "ADC0_OUT_0" SITE "AD2" ; +IOBUF PORT "ADC0_OUT_0" IO_TYPE=LVDS25 ; + +LOCATE COMP "ADC0_CLK" SITE "W1" ; +IOBUF PORT "ADC0_CLK" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4; +LOCATE COMP "ADC0_RST" SITE "AD3" ; +IOBUF PORT "ADC0_RST" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8 ; +LOCATE COMP "ADC0_CS" SITE "AC3" ; +IOBUF PORT "ADC0_CS" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8 ; +LOCATE COMP "ADC0_PD" SITE "V1" ; +IOBUF PORT "ADC0_PD" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8 ; +LOCATE COMP "ADC0_SDI" SITE "AB1" ; +IOBUF PORT "ADC0_SDI" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ; +LOCATE COMP "ADC0_SCK" SITE "W2" ; +IOBUF PORT "ADC0_SCK" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ; +LOCATE COMP "FPGA_LED_ADC_0" SITE "V2" ; +IOBUF PORT "FPGA_LED_ADC_0" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ; + +# LOCATE COMP "ADC0_DEBUG" SITE "AC5" ; +# IOBUF PORT "ADC0_DEBUG" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ; + + +###################################################################### +# I/O bank 5 - 3.30V +# LVDS driver control, backplane sense pins +###################################################################### +LOCATE COMP "ENA_LVDS_7" SITE "AG2" ; +LOCATE COMP "ENA_LVDS_6" SITE "AG3" ; +LOCATE COMP "ENA_LVDS_5" SITE "AG4" ; +LOCATE COMP "ENA_LVDS_4" SITE "AG5" ; +LOCATE COMP "ENA_LVDS_3" SITE "AG11" ; +LOCATE COMP "ENA_LVDS_2" SITE "AG12" ; +LOCATE COMP "ENA_LVDS_1" SITE "AG13" ; +LOCATE COMP "ENA_LVDS_0" SITE "AG15" ; +# LOCATE COMP "FPGA_SECTOR_5" SITE "AF16" ; +# IOBUF PORT "FPGA_SECTOR_5" IO_TYPE=LVTTL33 ; +# LOCATE COMP "FPGA_SECTOR_4" SITE "AE16" ; +# IOBUF PORT "FPGA_SECTOR_4" IO_TYPE=LVTTL33 ; +# Backplane sense wires: sector number +# small assembly bug: switch is 180degree rotated, so number are mirrored +LOCATE COMP "BP_SECTOR_3" SITE "AF11" ; # was "AF15" +IOBUF PORT "BP_SECTOR_3" IO_TYPE=LVTTL33 PULLMODE=UP ; +LOCATE COMP "BP_SECTOR_2" SITE "AF12" ; # was "AF13" +IOBUF PORT "BP_SECTOR_2" IO_TYPE=LVTTL33 PULLMODE=UP ; +LOCATE COMP "BP_SECTOR_1" SITE "AF13" ; # was "AF12" +IOBUF PORT "BP_SECTOR_1" IO_TYPE=LVTTL33 PULLMODE=UP ; +LOCATE COMP "BP_SECTOR_0" SITE "AF15" ; # was "AF11" +IOBUF PORT "BP_MODULE_0 IO_TYPE=LVTTL33 PULLMODE=UP ; + +LOCATE COMP "BP_LED" SITE "AE8" ; +IOBUF PORT "BP_LED" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 ; + +# LOCATE COMP "FPGA_SPARE_4" SITE "AF10" ; +# IOBUF PORT "FPGA_SPARE_4" IO_TYPE=LVTTL33 ; +# LOCATE COMP "FPGA_SPARE_3" SITE "AG8" ; +# IOBUF PORT "FPGA_SPARE_3" IO_TYPE=LVTTL33 ; +# LOCATE COMP "FPGA_SPARE_2" SITE "AF8" ; +# IOBUF PORT "FPGA_SPARE_2" IO_TYPE=LVTTL33 ; +# LOCATE COMP "FPGA_SPARE_1" SITE "AG10" ; +# IOBUF PORT "FPGA_SPARE_1" IO_TYPE=LVTTL33 ; +# LOCATE COMP "FPGA_SPARE_0" SITE "AG9" ; +# IOBUF PORT "FPGA_SPARE_0" IO_TYPE=LVTTL33 ; + +# short cut pins for FPGA placement control by JTAG +# LOCATE COMP "PIN_CHECK_5_IN" SITE "AF4" ; +# LOCATE COMP "PIN_CHECK_5_OUT" SITE "AF3" ; + + +###################################################################### +# I/O bank 4 - 3.30V +# 100MHZ clock in, SPI user pins, APV0 OneWire +###################################################################### +LOCATE COMP "CLK100M" SITE "AJ14" ; +IOBUF PORT "CLK100M" IO_TYPE=LVDS25 ; +LOCATE COMP "APV0_1W_7" SITE "AJ16" ; +IOBUF PORT "APV0_1W_7" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16; +LOCATE COMP "APV0_1W_6" SITE "AK16" ; +IOBUF PORT "APV0_1W_6" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16; +LOCATE COMP "APV0_1W_5" SITE "AJ17" ; +IOBUF PORT "APV0_1W_5" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16; +LOCATE COMP "APV0_1W_4" SITE "AK17" ; +IOBUF PORT "APV0_1W_4" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16; +LOCATE COMP "APV0_1W_3" SITE "AG18" ; +IOBUF PORT "APV0_1W_3" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16; +LOCATE COMP "APV0_1W_2" SITE "AG19" ; +IOBUF PORT "APV0_1W_2" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16; +LOCATE COMP "APV0_1W_1" SITE "AG20" ; +IOBUF PORT "APV0_1W_1" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16; +LOCATE COMP "APV0_1W_0" SITE "AG21" ; +IOBUF PORT "APV0_1W_0" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16; +# LOCATE COMP "EXP_2" SITE "AF21" ; +# IOBUF PORT "EXP_2" IO_TYPE=LVTTL33; +# LOCATE COMP "EXP_1" SITE "AE20" ; +# IOBUF PORT "EXP_1" IO_TYPE=LVTTL33; +# LOCATE COMP "EXP_0" SITE "AE21" ; +# IOBUF PORT "EXP_0" IO_TYPE=LVTTL33 ; +LOCATE COMP "U_SPI_SDO" SITE "AE24" ; +IOBUF PORT "U_SPI_SDO" IO_TYPE=LVTTL33 ; +LOCATE COMP "U_SPI_SDI" SITE "AE25" ; +IOBUF PORT "U_SPI_SDI" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=4 ; +LOCATE COMP "U_SPI_CS" SITE "AD24" ; +IOBUF PORT "U_SPI_CS" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=4 ; +LOCATE COMP "U_SPI_SCK" SITE "AF26" ; +IOBUF PORT "U_SPI_SCK" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=4 ; + +LOCATE COMP "FPGA_LED_PLL" SITE "AG22" ; +IOBUF PORT "FPGA_LED_PLL" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ; + +# short cut pins for FPGA placement control by JTAG +# LOCATE COMP "PIN_CHECK_4_IN" SITE "AD23" ; +# LOCATE COMP "PIN_CHECK_4_OUT" SITE "AC23" ; + + +###################################################################### +# I/O bank 3 - 3.30V +# uC connection, external inputs, debug pins (SMC50) +###################################################################### +LOCATE COMP "EXT_IN_3" SITE "AA30" ; +IOBUF PORT "EXT_IN_3" IO_TYPE=LVTTL33 ; +LOCATE COMP "EXT_IN_2" SITE "AB30" ; +IOBUF PORT "EXT_IN_2" IO_TYPE=LVTTL33 ; +LOCATE COMP "EXT_IN_1" SITE "AB29" ; +IOBUF PORT "EXT_IN_1" IO_TYPE=LVTTL33 ; +LOCATE COMP "EXT_IN_0" SITE "AB28" ; +# alternative, if needed +# LOCATE COMP "EXT_IN_0" SITE "P28" ; +IOBUF PORT "EXT_IN_0" IO_TYPE=LVTTL33 ; +# LOCATE COMP "DBG_EXP_41" SITE "T27" ; +# LOCATE COMP "DBG_EXP_39" SITE "T26" ; +# LOCATE COMP "DBG_EXP_37" SITE "U26" ; +# LOCATE COMP "DBG_EXP_35" SITE "V25" ; +# LOCATE COMP "DBG_EXP_33" SITE "W25" ; +# LOCATE COMP "DBG_EXP_31" SITE "W26" ; +# LOCATE COMP "DBG_EXP_29" SITE "Y26" ; +# LOCATE COMP "DBG_EXP_27" SITE "Y27" ; +# LOCATE COMP "DBG_EXP_25" SITE "AB26" ; +# LOCATE COMP "DBG_EXP_23" SITE "AC27" ; +# LOCATE COMP "DBG_EXP_21" SITE "U25" ; +# LOCATE COMP "DBG_EXP_19" SITE "U28" ; +# LOCATE COMP "DBG_EXP_17" SITE "U27" ; +# LOCATE COMP "DBG_EXP_5" SITE "R28" ; +# LOCATE COMP "DBG_EXP_3" SITE "R27" ; +# LOCATE COMP "DBG_EXP_1" SITE "T28" ; +LOCATE COMP "UC_REBOOT" SITE "Y28" ; # was UC_FPGA3 +IOBUF PORT "UC_REBOOT" IO_TYPE=LVTTL33 ; +# LOCATE COMP "UC_FPGA_2" SITE "W27" ; +# IOBUF PORT "UC_FPGA_2" IO_TYPE=LVTTL33 ; +# LOCATE COMP "UC_FPGA_1" SITE "W28" ; +# IOBUF PORT "UC_FPGA_1" IO_TYPE=LVTTL33 ; +# UC_FPGA_0 pin is GSR +LOCATE COMP "UC_RESET" SITE "V26" ; +IOBUF PORT "UC_RESET" IO_TYPE=LVTTL33 ; +# LOCATE COMP "UC_WR" SITE "P29" ; +# IOBUF PORT "UC_WR" IO_TYPE=LVTTL33; +# LOCATE COMP "UC_RD" SITE "P30" ; +# IOBUF PORT "UC_RD" IO_TYPE=LVTTL33 ; +# LOCATE COMP "UC_ALE" SITE "W29" ; +# IOBUF PORT "UC_ALE" IO_TYPE=LVTTL33 ; +# LOCATE COMP "UC_SCL" SITE "N30" ; +# IOBUF PORT "UC_SCL" IO_TYPE=LVTTL33 ; +# LOCATE COMP "UC_SDA" SITE "N29" ; +# IOBUF PORT "UC_SDA" IO_TYPE=LVTTL33 ; +# LOCATE COMP "UC_AD_7" SITE "W30" ; +# IOBUF PORT "UC_AD_7" IO_TYPE=LVTTL33 ; +# LOCATE COMP "UC_AD_6" SITE "Y29" ; +# IOBUF PORT "UC_AD_6" IO_TYPE=LVTTL33 ; +# LOCATE COMP "UC_AD_5" SITE "Y30" ; +# IOBUF PORT "UC_AD_5" IO_TYPE=LVTTL33 ; +# LOCATE COMP "UC_AD_4" SITE "AA29" ; +# IOBUF PORT "UC_AD_4" IO_TYPE=LVTTL33 ; +# LOCATE COMP "UC_AD_3" SITE "AB27" ; +# IOBUF PORT "UC_AD_3" IO_TYPE=LVTTL33 ; +# LOCATE COMP "UC_AD_2" SITE "AC29" ; +# IOBUF PORT "UC_AD_2" IO_TYPE=LVTTL33 ; +# LOCATE COMP "UC_AD_1" SITE "AC30" ; +# IOBUF PORT "UC_AD_1" IO_TYPE=LVTTL33 ; +# LOCATE COMP "UC_AD_0" SITE "AC28" ; +# IOBUF PORT "UC_AD_0" IO_TYPE=LVTTL33 ; +# LOCATE COMP "UC_A_15" SITE "V30" ; +# IOBUF PORT "UC_A_15" IO_TYPE=LVTTL33 ; +# LOCATE COMP "UC_A_14" SITE "V29" ; +# IOBUF PORT "UC_A_14" IO_TYPE=LVTTL33 ; +# LOCATE COMP "UC_A_13" SITE "U30" ; +# IOBUF PORT "UC_A_13" IO_TYPE=LVTTL33 ; +# LOCATE COMP "UC_A_12" SITE "U29" ; +# IOBUF PORT "UC_A_12" IO_TYPE=LVTTL33 ; +# LOCATE COMP "UC_A_11" SITE "T30" ; +# IOBUF PORT "UC_A_11" IO_TYPE=LVTTL33 ; +# LOCATE COMP "UC_A_10" SITE "T29" ; +# IOBUF PORT "UC_A_10" IO_TYPE=LVTTL33 ; +# LOCATE COMP "UC_A_9" SITE "R30" ; +# IOBUF PORT "UC_A_9" IO_TYPE=LVTTL33 ; +# LOCATE COMP "UC_A_8" SITE "R29" ; +# IOBUF PORT "UC_A_8" IO_TYPE=LVTTL33 ; + + +###################################################################### +# I/O bank 2 - 3.30V +# SFP control, LEDs, 1Wire ID, debug pins (SMC50) +###################################################################### +# LOCATE COMP "DBG_EXP_43" SITE "R26" ; +# LOCATE COMP "DBG_EXP_42" SITE "P25" ; +# LOCATE COMP "DBG_EXP_40" SITE "P26" ; +# LOCATE COMP "DBG_EXP_38" SITE "N25" ; +# LOCATE COMP "DBG_EXP_36" SITE "M25" ; +# LOCATE COMP "DBG_EXP_34" SITE "M26" ; +# LOCATE COMP "DBG_EXP_32" SITE "L25" ; +# LOCATE COMP "DBG_EXP_30" SITE "L26" ; +# LOCATE COMP "DBG_EXP_28" SITE "K25" ; +# LOCATE COMP "DBG_EXP_26" SITE "J26" ; +# LOCATE COMP "DBG_EXP_24" SITE "H25" ; +# LOCATE COMP "DBG_EXP_22" SITE "H26" ; +# LOCATE COMP "DBG_EXP_20" SITE "H24" ; +# LOCATE COMP "DBG_EXP_18" SITE "G26" ; +# LOCATE COMP "DBG_EXP_16" SITE "G25" ; +# LOCATE COMP "DBG_EXP_15" SITE "L27" ; +# LOCATE COMP "DBG_EXP_14" SITE "L28" ; +# LOCATE COMP "DBG_EXP_13" SITE "M28" ; +# LOCATE COMP "DBG_EXP_12" SITE "K24" ; +# LOCATE COMP "DBG_EXP_11" SITE "M27" ; +# LOCATE COMP "DBG_EXP_10" SITE "M30" ; +# LOCATE COMP "DBG_EXP_9" SITE "N26" ; +# LOCATE COMP "DBG_EXP_8" SITE "M29" ; +# LOCATE COMP "DBG_EXP_7" SITE "P27" ; +# LOCATE COMP "DBG_EXP_6" SITE "L30" ; +# LOCATE COMP "DBG_EXP_4" SITE "L29" ; +# LOCATE COMP "DBG_EXP_2" SITE "K30" ; +# LOCATE COMP "DBG_EXP_0" SITE "K29" ; +LOCATE COMP "FPGA_LED_6" SITE "G28" ; +IOBUF PORT "FPGA_LED_6" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ; +LOCATE COMP "FPGA_LED_5" SITE "G27" ; +IOBUF PORT "FPGA_LED_5" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ; +LOCATE COMP "FPGA_LED_4" SITE "H28" ; +IOBUF PORT "FPGA_LED_4" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ; +LOCATE COMP "FPGA_LED_3" SITE "H27" ; +IOBUF PORT "FPGA_LED_3" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ; +LOCATE COMP "FPGA_LED_RXD" SITE "J28" ; +IOBUF PORT "FPGA_LED_RXD" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ; +LOCATE COMP "FPGA_LED_TXD" SITE "J27" ; +IOBUF PORT "FPGA_LED_TXD" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ; +LOCATE COMP "FPGA_LED_LINK" SITE "K26" ; +IOBUF PORT "FPGA_LED_LINK" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ; +LOCATE COMP "SD_LOS" SITE "F30" ; +IOBUF PORT "SD_LOS" IO_TYPE=LVTTL33 ; +LOCATE COMP "SD_PRESENT" SITE "G30" ; # alias MD[0] +IOBUF PORT "SD_PRESENT" IO_TYPE=LVTTL33 ; +LOCATE COMP "SD_TXDIS" SITE "J29" ; +IOBUF PORT "SD_TXDIS" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=4 ; +# LOCATE COMP "SD_TXFAULT" SITE "J30" ; +# IOBUF PORT "SD_TXFAULT" IO_TYPE=LVTTL33 ; +# LOCATE COMP "SD_SDA" SITE "H30" ; # alias MD[2] +# IOBUF PORT "SD_SDA" IO_TYPE=LVTTL33 ; +# LOCATE COMP "SD_SCL" SITE "H29" ; # alias MD[1] +# IOBUF PORT "SD_SCL" IO_TYPE=LVTTL33 ; +# LOCATE COMP "SD_RATE" SITE "G29" ; +# IOBUF PORT "SD_RATE" IO_TYPE=LVTTL33 ; +LOCATE COMP "ADCM_ONEWIRE" SITE "F29" ; +IOBUF PORT "ADCM_ONEWIRE" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=8 ; + +# short cut pins for FPGA placement control by JTAG +# LOCATE COMP "PIN_CHECK_2_IN" SITE "D29" ; +# LOCATE COMP "PIN_CHECK_2_OUT" SITE "D30" ; + + +###################################################################### +# I/O bank 1 - 3.30V +# APV1 OneWire +###################################################################### +LOCATE COMP "APV1_1W_7" SITE "B15" ; +IOBUF PORT "APV1_1W_7" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16; +LOCATE COMP "APV1_1W_6" SITE "A16" ; +IOBUF PORT "APV1_1W_6" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16; +LOCATE COMP "APV1_1W_5" SITE "B16" ; +IOBUF PORT "APV1_1W_5" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16; +LOCATE COMP "APV1_1W_4" SITE "A17" ; +IOBUF PORT "APV1_1W_4" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16; +LOCATE COMP "APV1_1W_3" SITE "B17" ; +IOBUF PORT "APV1_1W_3" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16; +LOCATE COMP "APV1_1W_2" SITE "C16" ; +IOBUF PORT "APV1_1W_2" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16; +LOCATE COMP "APV1_1W_1" SITE "C17" ; +IOBUF PORT "APV1_1W_1" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16; +LOCATE COMP "APV1_1W_0" SITE "D16" ; +IOBUF PORT "APV1_1W_0" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16; + +#### HERE WE ARE ###################### + + +###################################################################### +# I/O bank 0 - 3.30V +# ADC1 control, LVDS driver control, backplane sense pins +###################################################################### +LOCATE COMP "ENB_LVDS_7" SITE "F6" ; +LOCATE COMP "ENB_LVDS_6" SITE "D5" ; +LOCATE COMP "ENB_LVDS_5" SITE "D4" ; +LOCATE COMP "ENB_LVDS_4" SITE "E5" ; +LOCATE COMP "ENB_LVDS_3" SITE "D15" ; +LOCATE COMP "ENB_LVDS_2" SITE "E13" ; +LOCATE COMP "ENB_LVDS_1" SITE "D13" ; +LOCATE COMP "ENB_LVDS_0" SITE "D12" ; +# LOCATE COMP "FPGA_BP_13" SITE "C15" ; +# IOBUF PORT "FPGA_BP_13" IO_TYPE=LVTTL33 ; +# LOCATE COMP "FPGA_BP_12" SITE "C14" ; +# IOBUF PORT "FPGA_BP_12" IO_TYPE=LVTTL33 ; +# Backplane sense wires: backplane number +LOCATE COMP "BP_MODULE_3" SITE "A14" ; +IOBUF PORT "BP_MODULE_3" IO_TYPE=LVTTL33 PULLMODE=UP ; +LOCATE COMP "BP_MODULE_2" SITE "F13" ; +IOBUF PORT "BP_MODULE_2" IO_TYPE=LVTTL33 PULLMODE=UP ; +LOCATE COMP "BP_MODULE_1" SITE "E12" ; +IOBUF PORT "BP_MODULE_1" IO_TYPE=LVTTL33 PULLMODE=UP ; +LOCATE COMP "BP_MODULE_0" SITE "G11" ; +IOBUF PORT "BP_MODULE_0" IO_TYPE=LVTTL33 PULLMODE=UP ; + +# LOCATE COMP "FPGA_SPARE_12" SITE "D8" ; +# IOBUF PORT "FPGA_SPARE_12" IO_TYPE=LVTTL33 ; +# LOCATE COMP "FPGA_SPARE_11" SITE "E8" ; +# IOBUF PORT "FPGA_SPARE_11" IO_TYPE=LVTTL33 ; +# LOCATE COMP "FPGA_SPARE_10" SITE "D9" ; +# IOBUF PORT "FPGA_SPARE_10" IO_TYPE=LVTTL33 ; +# LOCATE COMP "FPGA_SPARE_9" SITE "D11" ; +# IOBUF PORT "FPGA_SPARE_9" IO_TYPE=LVTTL33 ; +# LOCATE COMP "FPGA_SPARE_8" SITE "F11" ; +# IOBUF PORT "FPGA_SPARE_8" IO_TYPE=LVTTL33 ; + +LOCATE COMP "BP_ONEWIRE" SITE "F7" ; +IOBUF PORT "BP_ONEWIRE" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 ; + + +###################################################################### +# simplify IO definitions +###################################################################### +# Debug header (50pin SMC connector) +# DEFINE PORT GROUP "debug_header_group" "DBG_EXP_{0:43}" ; +# IOBUF GROUP "debug_header_group" IO_TYPE=LVCMOS33 PULLMODE=DOWN DRIVE=4 SLEWRATE=FAST ; + +# LED drivers +# DEFINE PORT GROUP "led_output_group" "FPGA_LED*" ; +# IOBUF GROUP "led_output_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ; + +# LVDS driver control +DEFINE PORT GROUP "enable_lvds_group" "EN?_LVDS_{0:7}" ; +IOBUF GROUP "enable_lvds_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW ; + +###################################################################### +# FPGA boot et. al. +###################################################################### +SYSCONFIG PERSISTENT=OFF ; +SYSCONFIG CONFIG_MODE=SPI ; +SYSCONFIG DONE_OD=OFF ; +SYSCONFIG DONE_EX=OFF ; +SYSCONFIG MCCLK_FREQ=34 ; +SYSCONFIG CONFIG_SECURE=OFF ; +SYSCONFIG WAKE_UP=21 ; +#SYSCONFIG WAKE_ON_LOCK=OFF ; +SYSCONFIG COMPRESS_CONFIG=OFF ; +SYSCONFIG INBUF=OFF ; +SYSCONFIG ENABLE_NDR=OFF ; +USERCODE HEX "DEADAFFE" ; diff --git a/adcmv3.prj b/adcmv3.prj old mode 100755 new mode 100644 index 393b5c1..8f2b6ed --- a/adcmv3.prj +++ b/adcmv3.prj @@ -7,72 +7,76 @@ add_file -vhdl -lib work "version.vhd" add_file -vhdl -lib work "../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../trbnet/trb_net_components.vhd" -add_file -vhdl -lib work "design/adcmv3_components.vhd" +add_file -vhdl -lib work "source/adcmv3_components.vhd" # ADCMv3 design files -add_file -vhdl -lib work "design/adcmv3.vhd" -add_file -vhdl -lib work "design/dbg_reg.vhd" -add_file -vhdl -lib work "design/reset_handler.vhd" -add_file -vhdl -lib work "design/reboot_handler.vhd" -add_file -vhdl -lib work "design/pulse_sync.vhd" -add_file -vhdl -lib work "design/adc_ch_in.vhd" -add_file -vhdl -lib work "design/state_sync.vhd" -add_file -vhdl -lib work "design/apv_sync_handler.vhd" -add_file -vhdl -lib work "design/apv_trg_handler.vhd" -add_file -vhdl -lib work "design/eds_buffer_dpram.vhd" -add_file -vhdl -lib work "design/eds_buf.vhd" -add_file -vhdl -lib work "design/max_data.vhd" -add_file -vhdl -lib work "design/real_trg_handler.vhd" -add_file -vhdl -lib work "design/pulse_stretch.vhd" -add_file -vhdl -lib work "design/apv_trgctrl.vhd" -add_file -vhdl -lib work "design/adc_channel_select.vhd" -add_file -vhdl -lib work "design/crossover.vhd" -add_file -vhdl -lib work "design/adc_crossover.vhd" -add_file -vhdl -lib work "design/adc_twochannels.vhd" -add_file -vhdl -lib work "design/adc_data_handler.vhd" -add_file -vhdl -lib work "design/frame_status_mem.vhd" -add_file -vhdl -lib work "design/input_bram.vhd" -add_file -vhdl -lib work "design/apv_raw_buffer.vhd" -add_file -vhdl -lib work "design/apv_lock_sm.vhd" -add_file -vhdl -lib work "design/apv_digital.vhd" -add_file -vhdl -lib work "design/apv_locker.vhd" -add_file -vhdl -lib work "design/raw_buf_stage.vhd" -add_file -vhdl -lib work "design/decoder_8bit.vhd" -add_file -vhdl -lib work "design/apv_pc_nc_alu.vhd" -add_file -vhdl -lib work "design/buf_toc.vhd" -add_file -vhdl -lib work "design/ref_row_sel.vhd" -add_file -vhdl -lib work "design/frmctr_check.vhd" -add_file -vhdl -lib work "design/ped_corr_ctrl.vhd" -add_file -vhdl -lib work "design/adc_apv_map_mem.vhd" -add_file -vhdl -lib work "design/fifo_1kx18.vhd" -add_file -vhdl -lib work "design/fifo_2kx27.vhd" -add_file -vhdl -lib work "design/ipu_fifo_stage.vhd" -add_file -vhdl -lib work "design/slv_register.vhd" -add_file -vhdl -lib work "design/adc_snoop_mem.vhd" -add_file -vhdl -lib work "design/slv_adc_snoop.vhd" -add_file -vhdl -lib work "design/slv_half_register.vhd" -add_file -vhdl -lib work "design/slv_status.vhd" -add_file -vhdl -lib work "design/slv_status_bank.vhd" -add_file -vhdl -lib work "design/apv_adc_map_mem.vhd" -add_file -vhdl -lib work "design/slv_register_bank.vhd" -add_file -vhdl -lib work "design/spi_real_slim.vhd" -add_file -vhdl -lib work "design/spi_adc_master.vhd" -add_file -vhdl -lib work "design/slv_onewire_dpram.vhd" -add_file -vhdl -lib work "design/onewire_master.vhd" -add_file -vhdl -lib work "design/onewire_spare_one.vhd" -add_file -vhdl -lib work "design/adc_onewire_map_mem.vhd" -add_file -vhdl -lib work "design/slv_onewire_memory.vhd" -add_file -vhdl -lib work "design/i2c_gstart.vhd" -add_file -vhdl -lib work "design/i2c_sendb.vhd" -add_file -vhdl -lib work "design/i2c_slim.vhd" -add_file -vhdl -lib work "design/i2c_master.vhd" -add_file -vhdl -lib work "design/ped_thr_true.vhd" -add_file -vhdl -lib work "design/slv_ped_thr_mem.vhd" -add_file -vhdl -lib work "design/slave_bus.vhd" -add_file -vhdl -lib work "design/rich_trb.vhd" -add_file -vhdl -lib work "design/sync_pll_40m.vhd" -add_file -vhdl -lib work "design/dll_100m.vhd" -add_file -vhdl -lib work "design/pll_40m.vhd" +# Top level entity +add_file -vhdl -lib work "adcmv3.vhd" + +add_file -vhdl -lib work "source/dbg_reg.vhd" +add_file -vhdl -lib work "source/reset_handler.vhd" +add_file -vhdl -lib work "source/reboot_handler.vhd" +add_file -vhdl -lib work "source/pulse_sync.vhd" +add_file -vhdl -lib work "source/state_sync.vhd" +add_file -vhdl -lib work "source/apv_sync_handler.vhd" +add_file -vhdl -lib work "source/apv_trg_handler.vhd" +add_file -vhdl -lib work "source/eds_buf.vhd" +add_file -vhdl -lib work "source/max_data.vhd" +add_file -vhdl -lib work "source/real_trg_handler.vhd" +add_file -vhdl -lib work "source/pulse_stretch.vhd" +add_file -vhdl -lib work "source/apv_trgctrl.vhd" +add_file -vhdl -lib work "source/adc_channel_select.vhd" +add_file -vhdl -lib work "source/adc_crossover.vhd" +add_file -vhdl -lib work "source/adc_twochannels.vhd" +add_file -vhdl -lib work "source/adc_data_handler.vhd" +add_file -vhdl -lib work "source/apv_raw_buffer.vhd" +add_file -vhdl -lib work "source/apv_lock_sm.vhd" +add_file -vhdl -lib work "source/apv_digital.vhd" +add_file -vhdl -lib work "source/apv_locker.vhd" +add_file -vhdl -lib work "source/raw_buf_stage.vhd" +add_file -vhdl -lib work "source/apv_pc_nc_alu.vhd" +add_file -vhdl -lib work "source/buf_toc.vhd" +add_file -vhdl -lib work "source/ref_row_sel.vhd" +add_file -vhdl -lib work "source/frmctr_check.vhd" +add_file -vhdl -lib work "source/ped_corr_ctrl.vhd" +add_file -vhdl -lib work "source/ipu_fifo_stage.vhd" +add_file -vhdl -lib work "source/slv_register.vhd" +add_file -vhdl -lib work "source/slv_adc_snoop.vhd" +add_file -vhdl -lib work "source/slv_half_register.vhd" +add_file -vhdl -lib work "source/slv_status.vhd" +add_file -vhdl -lib work "source/slv_status_bank.vhd" +add_file -vhdl -lib work "source/slv_register_bank.vhd" +add_file -vhdl -lib work "source/spi_real_slim.vhd" +add_file -vhdl -lib work "source/spi_adc_master.vhd" +add_file -vhdl -lib work "source/onewire_master.vhd" +add_file -vhdl -lib work "source/slv_onewire_memory.vhd" +add_file -vhdl -lib work "source/i2c_gstart.vhd" +add_file -vhdl -lib work "source/i2c_sendb.vhd" +add_file -vhdl -lib work "source/i2c_slim.vhd" +add_file -vhdl -lib work "source/i2c_master.vhd" +add_file -vhdl -lib work "source/slv_ped_thr_mem.vhd" +add_file -vhdl -lib work "source/slave_bus.vhd" +add_file -vhdl -lib work "source/rich_trb.vhd" + +# Core files +add_file -vhdl -lib work "cores/adc_ch_in.vhd" +add_file -vhdl -lib work "cores/eds_buffer_dpram.vhd" +add_file -vhdl -lib work "cores/crossover.vhd" +add_file -vhdl -lib work "cores/frame_status_mem.vhd" +add_file -vhdl -lib work "cores/input_bram.vhd" +add_file -vhdl -lib work "cores/decoder_8bit.vhd" +add_file -vhdl -lib work "cores/adc_apv_map_mem.vhd" +add_file -vhdl -lib work "cores/fifo_1kx18.vhd" +add_file -vhdl -lib work "cores/fifo_2kx27.vhd" +add_file -vhdl -lib work "cores/adc_snoop_mem.vhd" +add_file -vhdl -lib work "cores/apv_adc_map_mem.vhd" +add_file -vhdl -lib work "cores/onewire_spare_one.vhd" +add_file -vhdl -lib work "cores/adc_onewire_map_mem.vhd" +add_file -vhdl -lib work "cores/ped_thr_true.vhd" +add_file -vhdl -lib work "cores/sync_pll_40m.vhd" +add_file -vhdl -lib work "cores/dll_100m.vhd" +add_file -vhdl -lib work "cores/pll_40m.vhd" +add_file -vhdl -lib work "cores/slv_onewire_dpram.vhd" # TrbNet design files add_file -vhdl -lib work "../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd" @@ -113,14 +117,12 @@ add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" add_file -vhdl -lib work "../trbnet/basics/signal_sync.vhd" add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd" add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd" - # add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd" -# add_file -vhdl -lib work "design/sfp_rx_handler.vhd" +# add_file -vhdl -lib work "source/sfp_rx_handler.vhd" # implementation: "workdir" impl -add workdir -type fpga - # device options set_option -technology LATTICE-ECP2M set_option -part LFE2M100E @@ -159,3 +161,4 @@ project -result_file "workdir/adcmv3.edf" set_option -vlog_std v2001 set_option -project_relative_includes 1 impl -active "workdir" + diff --git a/design/adcmv3.vhd b/adcmv3.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/adcmv3.vhd rename to adcmv3.vhd diff --git a/cleanup_workdir.sh b/cleanup_workdir.sh new file mode 100755 index 0000000..fe88ea6 --- /dev/null +++ b/cleanup_workdir.sh @@ -0,0 +1,18 @@ +#!/bin/sh +TOPNAME=adcmv3 + +rm -f workdir/${TOPNAME}.alt +rm -f workdir/${TOPNAME}.bgn +rm -f workdir/${TOPNAME}.bit +rm -f workdir/${TOPNAME}.edf +rm -f workdir/${TOPNAME}.fse +rm -f workdir/${TOPNAME}.mrp +rm -f workdir/${TOPNAME}.ncd +rm -f workdir/${TOPNAME}.ngd +rm -f workdir/${TOPNAME}.ngo +rm -f workdir/${TOPNAME}.ngy +rm -f workdir/${TOPNAME}.pad +rm -f workdir/${TOPNAME}.par +rm -f workdir/${TOPNAME}.sr? +rm -f workdir/${TOPNAME}.tlg +rm -f workdir/${TOPNAME}.twr* diff --git a/compile.pl b/compile.pl index e8ad213..c9b4049 100755 --- a/compile.pl +++ b/compile.pl @@ -54,7 +54,9 @@ system("rm workdir/$TOPNAME.tlg"); system("rm workdir/$TOPNAME.twr*"); # Create full lpf file -system("cp ../trbnet/pinout/$TOPNAME.lpf workdir/$TOPNAME.lpf"); +#system("cp ../trbnet/pinout/$TOPNAME.lpf workdir/$TOPNAME.lpf"); +#system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf"); +system("cp ./$TOPNAME.lpf workdir/$TOPNAME.lpf"); system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf"); # Generate timestamp for slowcontrol readback diff --git a/compile_ORIG.pl b/compile_munich21.pl similarity index 52% rename from compile_ORIG.pl rename to compile_munich21.pl index 63d027c..6738163 100755 --- a/compile_ORIG.pl +++ b/compile_munich21.pl @@ -1,29 +1,28 @@ #!/usr/bin/perl -########################################### -# Script file to run the flow -########################################### - -# You need the tunnels before! - use Data::Dumper; use warnings; use strict; -# Path settings for ispLEVER tools -my $lattice_path = '/usr/local/opt/synplify/8/isptools'; -# Path settings for SynplifyPRO -# my $synplify_path = '/usr/local/opt/synplify/premier'; -my $synplify_path = '/scratch/rich/synplify/D-2009.12'; + + +################################################################################### +#Settings for this project +my $TOPNAME = "adcmv3"; #Name of top-level entity +my $lattice_path = '/usr/local/opt/lattice_diamond/diamond/2.1'; +my $synplify_path = '/usr/local/opt/synplify/F-2012.03-SP1/'; +my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; +my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; +################################################################################### + + use FileHandle; $ENV{'SYNPLIFY'}=$synplify_path; $ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; -$ENV{'LM_LICENSE_FILE'}="27000\@localhost"; +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; -# Design top level entity -my $TOPNAME="adcmv3"; # FPGA chip description my $FAMILYNAME="LATTICEECP2M"; @@ -31,11 +30,16 @@ my $DEVICENAME="LFE2M100E"; my $PACKAGE="FPBGA900"; my $SPEEDGRADE="6"; -# Create full lpf file -system("cp ../trbnet/pinout/$TOPNAME.lpf workdir/$TOPNAME.lpf"); +#create full lpf file +system("cp ./$TOPNAME.lpf workdir/$TOPNAME.lpf"); system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf"); +#system("cp ../base/$TOPNAME"."_nxyter.lpf workdir/$TOPNAME.lpf"); +#system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); + +#set -e +#set -o errexit -# Generate timestamp for slowcontrol readback +#generate timestamp my $t=time; my $fh = new FileHandle(">version.vhd"); die "could not open file" if (! defined $fh); @@ -56,68 +60,71 @@ end package version; EOF $fh->close; -# Run Synplify on the design system("env| grep LM_"); my $r = ""; -my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME".".prj"; + +my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; $r=execute($c, "do_not_exit" ); -# Check for errors + chdir "workdir"; $fh = new FileHandle("<$TOPNAME".".srr"); my @a = <$fh>; $fh -> close; + + foreach (@a) { if(/\@E:/) { - $c="cat $TOPNAME.srr"; + print "\n"; + $c="cat $TOPNAME.srr | grep \"\@E\""; system($c); - print "ERROR_ERROR_ERROR_ERROR_ERROR\n"; + print "\n\n"; exit 129; } } -# ispLEVER design flow starts here -# new license file must be given -$ENV{'LM_LICENSE_FILE'}="1710\@cronos.e12.physik.tu-muenchen.de"; -# EDIF2NGD -$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; + +$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; execute($c); $c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; execute($c); -# NGDBUILD -$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/or5s00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; +$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; execute($c); -# MAP my $tpmap = $TOPNAME . "_map" ; -$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; + +$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; execute($c); system("rm $TOPNAME.ncd"); -$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; + +$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); # IOR IO Timing Report -#$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; -#execute($c); +$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); -# TWR Timing Report (setup) +# TWR Timing Report $c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); -# TWR Timing Report (hold) $c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); -# BitGen -$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" -f "$TOPNAME.t2b" "$TOPNAME.prf"|; +$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|; +# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); chdir ".."; diff --git a/compile_munich21.sh b/compile_munich21.sh new file mode 100755 index 0000000..5b8795e --- /dev/null +++ b/compile_munich21.sh @@ -0,0 +1,6 @@ +#!/bin/sh + +. /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env + +exec ./compile_munich21.pl +#exec ./compile.pl diff --git a/constraints_adcmv3.lpf b/constraints_adcmv3.lpf old mode 100755 new mode 100644 diff --git a/constraints_adcmv3_BACK.lpf b/constraints_adcmv3_BACK.lpf old mode 100755 new mode 100644 diff --git a/design/adc_apv_map_mem.lpc b/cores/adc_apv_map_mem.lpc similarity index 100% rename from design/adc_apv_map_mem.lpc rename to cores/adc_apv_map_mem.lpc diff --git a/design/adc_apv_map_mem.vhd b/cores/adc_apv_map_mem.vhd similarity index 100% rename from design/adc_apv_map_mem.vhd rename to cores/adc_apv_map_mem.vhd diff --git a/design/adc_ch_in.lpc b/cores/adc_ch_in.lpc similarity index 100% rename from design/adc_ch_in.lpc rename to cores/adc_ch_in.lpc diff --git a/design/adc_ch_in.vhd b/cores/adc_ch_in.vhd similarity index 100% rename from design/adc_ch_in.vhd rename to cores/adc_ch_in.vhd diff --git a/design/adc_onewire_map_mem.lpc b/cores/adc_onewire_map_mem.lpc similarity index 100% rename from design/adc_onewire_map_mem.lpc rename to cores/adc_onewire_map_mem.lpc diff --git a/design/adc_onewire_map_mem.vhd b/cores/adc_onewire_map_mem.vhd similarity index 100% rename from design/adc_onewire_map_mem.vhd rename to cores/adc_onewire_map_mem.vhd diff --git a/design/adc_pll.lpc b/cores/adc_pll.lpc similarity index 100% rename from design/adc_pll.lpc rename to cores/adc_pll.lpc diff --git a/design/adc_pll.vhd b/cores/adc_pll.vhd similarity index 100% rename from design/adc_pll.vhd rename to cores/adc_pll.vhd diff --git a/design/adc_snoop_mem.lpc b/cores/adc_snoop_mem.lpc similarity index 100% rename from design/adc_snoop_mem.lpc rename to cores/adc_snoop_mem.lpc diff --git a/design/adc_snoop_mem.vhd b/cores/adc_snoop_mem.vhd similarity index 100% rename from design/adc_snoop_mem.vhd rename to cores/adc_snoop_mem.vhd diff --git a/design/apv_adc_map_mem.lpc b/cores/apv_adc_map_mem.lpc similarity index 100% rename from design/apv_adc_map_mem.lpc rename to cores/apv_adc_map_mem.lpc diff --git a/design/apv_adc_map_mem.vhd b/cores/apv_adc_map_mem.vhd similarity index 100% rename from design/apv_adc_map_mem.vhd rename to cores/apv_adc_map_mem.vhd diff --git a/design/apv_map_mem.lpc b/cores/apv_map_mem.lpc similarity index 100% rename from design/apv_map_mem.lpc rename to cores/apv_map_mem.lpc diff --git a/design/apv_map_mem.vhd b/cores/apv_map_mem.vhd similarity index 100% rename from design/apv_map_mem.vhd rename to cores/apv_map_mem.vhd diff --git a/design/crossover.lpc b/cores/crossover.lpc similarity index 100% rename from design/crossover.lpc rename to cores/crossover.lpc diff --git a/design/crossover.vhd b/cores/crossover.vhd similarity index 100% rename from design/crossover.vhd rename to cores/crossover.vhd diff --git a/design/decoder_8bit.lpc b/cores/decoder_8bit.lpc similarity index 100% rename from design/decoder_8bit.lpc rename to cores/decoder_8bit.lpc diff --git a/design/decoder_8bit.mem b/cores/decoder_8bit.mem similarity index 100% rename from design/decoder_8bit.mem rename to cores/decoder_8bit.mem diff --git a/design/decoder_8bit.vhd b/cores/decoder_8bit.vhd similarity index 100% rename from design/decoder_8bit.vhd rename to cores/decoder_8bit.vhd diff --git a/design/dll_100m.lpc b/cores/dll_100m.lpc similarity index 100% rename from design/dll_100m.lpc rename to cores/dll_100m.lpc diff --git a/design/dll_100m.vhd b/cores/dll_100m.vhd similarity index 100% rename from design/dll_100m.vhd rename to cores/dll_100m.vhd diff --git a/design/dpram_8x19.lpc b/cores/dpram_8x19.lpc similarity index 100% rename from design/dpram_8x19.lpc rename to cores/dpram_8x19.lpc diff --git a/design/dpram_8x19.vhd b/cores/dpram_8x19.vhd similarity index 100% rename from design/dpram_8x19.vhd rename to cores/dpram_8x19.vhd diff --git a/design/eds_buffer_dpram.lpc b/cores/eds_buffer_dpram.lpc similarity index 100% rename from design/eds_buffer_dpram.lpc rename to cores/eds_buffer_dpram.lpc diff --git a/design/eds_buffer_dpram.vhd b/cores/eds_buffer_dpram.vhd similarity index 100% rename from design/eds_buffer_dpram.vhd rename to cores/eds_buffer_dpram.vhd diff --git a/design/fifo_16x11.lpc b/cores/fifo_16x11.lpc similarity index 100% rename from design/fifo_16x11.lpc rename to cores/fifo_16x11.lpc diff --git a/design/fifo_16x11.vhd b/cores/fifo_16x11.vhd similarity index 100% rename from design/fifo_16x11.vhd rename to cores/fifo_16x11.vhd diff --git a/design/fifo_1kx18.lpc b/cores/fifo_1kx18.lpc similarity index 100% rename from design/fifo_1kx18.lpc rename to cores/fifo_1kx18.lpc diff --git a/design/fifo_1kx18.vhd b/cores/fifo_1kx18.vhd similarity index 100% rename from design/fifo_1kx18.vhd rename to cores/fifo_1kx18.vhd diff --git a/design/fifo_2kx27.lpc b/cores/fifo_2kx27.lpc similarity index 100% rename from design/fifo_2kx27.lpc rename to cores/fifo_2kx27.lpc diff --git a/design/fifo_2kx27.vhd b/cores/fifo_2kx27.vhd similarity index 100% rename from design/fifo_2kx27.vhd rename to cores/fifo_2kx27.vhd diff --git a/design/frame_status_mem.lpc b/cores/frame_status_mem.lpc similarity index 100% rename from design/frame_status_mem.lpc rename to cores/frame_status_mem.lpc diff --git a/design/frame_status_mem.vhd b/cores/frame_status_mem.vhd similarity index 100% rename from design/frame_status_mem.vhd rename to cores/frame_status_mem.vhd diff --git a/design/input_bram.lpc b/cores/input_bram.lpc similarity index 100% rename from design/input_bram.lpc rename to cores/input_bram.lpc diff --git a/design/input_bram.vhd b/cores/input_bram.vhd similarity index 100% rename from design/input_bram.vhd rename to cores/input_bram.vhd diff --git a/design/mult_3x8.lpc b/cores/mult_3x8.lpc similarity index 100% rename from design/mult_3x8.lpc rename to cores/mult_3x8.lpc diff --git a/design/mult_3x8.vhd b/cores/mult_3x8.vhd similarity index 100% rename from design/mult_3x8.vhd rename to cores/mult_3x8.vhd diff --git a/design/onewire_spare_one.lpc b/cores/onewire_spare_one.lpc similarity index 100% rename from design/onewire_spare_one.lpc rename to cores/onewire_spare_one.lpc diff --git a/design/onewire_spare_one.vhd b/cores/onewire_spare_one.vhd similarity index 100% rename from design/onewire_spare_one.vhd rename to cores/onewire_spare_one.vhd diff --git a/design/ped_thr_true.lpc b/cores/ped_thr_true.lpc similarity index 100% rename from design/ped_thr_true.lpc rename to cores/ped_thr_true.lpc diff --git a/design/ped_thr_true.vhd b/cores/ped_thr_true.vhd similarity index 100% rename from design/ped_thr_true.vhd rename to cores/ped_thr_true.vhd diff --git a/design/pll_40m.lpc b/cores/pll_40m.lpc similarity index 100% rename from design/pll_40m.lpc rename to cores/pll_40m.lpc diff --git a/design/pll_40m.vhd b/cores/pll_40m.vhd similarity index 100% rename from design/pll_40m.vhd rename to cores/pll_40m.vhd diff --git a/design/slv_onewire_dpram.lpc b/cores/slv_onewire_dpram.lpc similarity index 100% rename from design/slv_onewire_dpram.lpc rename to cores/slv_onewire_dpram.lpc diff --git a/design/slv_onewire_dpram.vhd b/cores/slv_onewire_dpram.vhd similarity index 100% rename from design/slv_onewire_dpram.vhd rename to cores/slv_onewire_dpram.vhd diff --git a/design/sync_pll_40m.lpc b/cores/sync_pll_40m.lpc similarity index 100% rename from design/sync_pll_40m.lpc rename to cores/sync_pll_40m.lpc diff --git a/design/sync_pll_40m.vhd b/cores/sync_pll_40m.vhd similarity index 100% rename from design/sync_pll_40m.vhd rename to cores/sync_pll_40m.vhd diff --git a/design/test_fifo.lpc b/cores/test_fifo.lpc similarity index 100% rename from design/test_fifo.lpc rename to cores/test_fifo.lpc diff --git a/design/test_fifo.vhd b/cores/test_fifo.vhd similarity index 100% rename from design/test_fifo.vhd rename to cores/test_fifo.vhd diff --git a/design/test_fifo2.lpc b/cores/test_fifo2.lpc similarity index 100% rename from design/test_fifo2.lpc rename to cores/test_fifo2.lpc diff --git a/design/test_fifo2.vhd b/cores/test_fifo2.vhd similarity index 100% rename from design/test_fifo2.vhd rename to cores/test_fifo2.vhd diff --git a/design/testfifo.lpc b/cores/testfifo.lpc similarity index 100% rename from design/testfifo.lpc rename to cores/testfifo.lpc diff --git a/design/testfifo.vhd b/cores/testfifo.vhd similarity index 100% rename from design/testfifo.vhd rename to cores/testfifo.vhd diff --git a/debug_pin.txt b/debug_pin.txt old mode 100755 new mode 100644 diff --git a/featurelist.txt b/featurelist.txt old mode 100755 new mode 100644 diff --git a/howto_adcm_i2c.txt b/howto_adcm_i2c.txt old mode 100755 new mode 100644 diff --git a/lever/.recordref b/lever/.recordref old mode 100755 new mode 100644 diff --git a/lever/adcmv3.ini b/lever/adcmv3.ini old mode 100755 new mode 100644 diff --git a/lever/adcmv3.jid b/lever/adcmv3.jid old mode 100755 new mode 100644 diff --git a/lever/adcmv3.lci b/lever/adcmv3.lci old mode 100755 new mode 100644 diff --git a/lever/adcmv3.lct b/lever/adcmv3.lct old mode 100755 new mode 100644 diff --git a/lever/adcmv3.lpf b/lever/adcmv3.lpf old mode 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a/lever/fifo_18x16_media_interface_mb.vht b/lever/fifo_18x16_media_interface_mb.vht old mode 100755 new mode 100644 diff --git a/lever/pre.clr b/lever/pre.clr old mode 100755 new mode 100644 diff --git a/lever/run_options.txt b/lever/run_options.txt old mode 100755 new mode 100644 diff --git a/lever/sbuf.cmd b/lever/sbuf.cmd old mode 100755 new mode 100644 diff --git a/lever/sbuf.edi b/lever/sbuf.edi old mode 100755 new mode 100644 diff --git a/lever/sbuf.fse b/lever/sbuf.fse old mode 100755 new mode 100644 diff --git a/lever/sbuf.srd b/lever/sbuf.srd old mode 100755 new mode 100644 diff --git a/lever/sbuf.srf b/lever/sbuf.srf old mode 100755 new mode 100644 diff --git a/lever/sbuf.szr b/lever/sbuf.szr old mode 100755 new mode 100644 diff --git a/lever/syntmp/hdlorder.tcl b/lever/syntmp/hdlorder.tcl old mode 100755 new mode 100644 diff --git a/lever/syntmp/sbuf.plg b/lever/syntmp/sbuf.plg old mode 100755 new mode 100644 diff --git a/lever/tb_apv_trgctrl.rsp b/lever/tb_apv_trgctrl.rsp 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a/lever/tb_sfp_rx_handler_activehdl2.do b/lever/tb_sfp_rx_handler_activehdl2.do old mode 100755 new mode 100644 diff --git a/lever/tb_sfp_rx_handler_vhdf.udo b/lever/tb_sfp_rx_handler_vhdf.udo old mode 100755 new mode 100644 diff --git a/lever/tb_spi_master.fado b/lever/tb_spi_master.fado old mode 100755 new mode 100644 diff --git a/lever/tb_spi_master.rsp b/lever/tb_spi_master.rsp old mode 100755 new mode 100644 diff --git a/lever/tb_spi_master_activehdl.do b/lever/tb_spi_master_activehdl.do old mode 100755 new mode 100644 diff --git a/lever/tb_spi_master_activehdl2.do b/lever/tb_spi_master_activehdl2.do old mode 100755 new mode 100644 diff --git a/lever/tb_spi_master_vhdf.udo b/lever/tb_spi_master_vhdf.udo old mode 100755 new mode 100644 diff --git a/lever/tb_test_media.rsp b/lever/tb_test_media.rsp old mode 100755 new mode 100644 diff --git a/lever/tb_test_media_activehdl.do b/lever/tb_test_media_activehdl.do old mode 100755 new mode 100644 diff --git a/lever/tb_test_media_activehdl2.do b/lever/tb_test_media_activehdl2.do old mode 100755 new mode 100644 diff --git a/lever/tb_test_media_vhdf.udo b/lever/tb_test_media_vhdf.udo old mode 100755 new mode 100644 diff --git a/lever/test_media.vht b/lever/test_media.vht old mode 100755 new mode 100644 diff --git a/lever/udo.rsp b/lever/udo.rsp old mode 100755 new mode 100644 diff --git a/lever/work.sbuf.prj b/lever/work.sbuf.prj old mode 100755 new mode 100644 diff --git a/lever/work/0work.mgf b/lever/work/0work.mgf old mode 100755 new mode 100644 diff --git a/lever/work/1work.mgf b/lever/work/1work.mgf old mode 100755 new mode 100644 diff --git a/lever/work/3work.mgf b/lever/work/3work.mgf old mode 100755 new mode 100644 diff --git a/lever/work/Edfmap.ini b/lever/work/Edfmap.ini old mode 100755 new mode 100644 diff --git a/lever/work/compilation.order b/lever/work/compilation.order old mode 100755 new mode 100644 diff --git a/lever/work/compile.cfg b/lever/work/compile.cfg old mode 100755 new mode 100644 diff --git a/lever/work/compile/contents.lib~work b/lever/work/compile/contents.lib~work deleted file mode 100755 index f49dc5d..0000000 --- a/lever/work/compile/contents.lib~work +++ /dev/null @@ -1,7 +0,0 @@ -38 -~E 1 "./../../../trbnet/special/spi_slim.vhd" 12 spi_slim -~A 1 "./../../../trbnet/special/spi_slim.vhd" 44 behavioral -~E 1 "./../../../trbnet/special/spi_master.vhd" 10 spi_master -~A 1 "./../../../trbnet/special/spi_master.vhd" 37 behavioral -~E 1 "./../../sim/tb_spi_master.vhd" 5 testbench -~A 1 "./../../sim/tb_spi_master.vhd" 8 behavior diff --git a/lever/work/compile/sources.sth b/lever/work/compile/sources.sth old mode 100755 new mode 100644 diff --git a/lever/work/compile/work.cmd b/lever/work/compile/work.cmd old mode 100755 new mode 100644 diff --git a/lever/work/compile/work.epr b/lever/work/compile/work.epr old mode 100755 new mode 100644 diff --git a/lever/work/compile/work.erf b/lever/work/compile/work.erf old mode 100755 new mode 100644 diff --git a/lever/work/library.cfg b/lever/work/library.cfg old mode 100755 new mode 100644 diff --git a/lever/work/projlib.cfg b/lever/work/projlib.cfg old mode 100755 new mode 100644 diff --git a/lever/work/work.LIB b/lever/work/work.LIB old mode 100755 new mode 100644 diff --git a/lever/work/work.adf b/lever/work/work.adf old mode 100755 new mode 100644 diff --git a/lever/work/work.aws b/lever/work/work.aws old mode 100755 new mode 100644 diff --git a/lever/work/work.wsp b/lever/work/work.wsp old mode 100755 new mode 100644 diff --git a/lever/work/work.wsw b/lever/work/work.wsw old mode 100755 new mode 100644 diff --git a/sim/tb_adc_cross.vhd b/sim/tb_adc_cross.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_adc_crossover.vhd b/sim/tb_adc_crossover.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_adc_handler.vhd b/sim/tb_adc_handler.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_adc_handler.vhd.bak b/sim/tb_adc_handler.vhd.bak old mode 100755 new mode 100644 diff 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a/sim/tb_ipu_fifo_stage_OLD.vhd b/sim/tb_ipu_fifo_stage_OLD.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_logic_analyzer.vhd b/sim/tb_logic_analyzer.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_max_data.vhd b/sim/tb_max_data.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_media_fifo.vhd b/sim/tb_media_fifo.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_media_fifo.vhd.bak b/sim/tb_media_fifo.vhd.bak old mode 100755 new mode 100644 diff --git a/sim/tb_media_fifo_mb.vhd b/sim/tb_media_fifo_mb.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_media_fifo_mb.vhd.bak b/sim/tb_media_fifo_mb.vhd.bak old mode 100755 new mode 100644 diff --git a/sim/tb_mult_3x8.vhd b/sim/tb_mult_3x8.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_my_sbuf.vhd b/sim/tb_my_sbuf.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_onewire_master.vhd b/sim/tb_onewire_master.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_ped_corr_ctrl.vhd b/sim/tb_ped_corr_ctrl.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_ped_corr_ctrl.vhd.bak b/sim/tb_ped_corr_ctrl.vhd.bak old mode 100755 new mode 100644 diff --git a/sim/tb_ped_corr_ctrl_OLD.vhd b/sim/tb_ped_corr_ctrl_OLD.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_pulse_stretch.vhd b/sim/tb_pulse_stretch.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_pulse_sync.vhd b/sim/tb_pulse_sync.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_raw_buf_stage.vhd b/sim/tb_raw_buf_stage.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_raw_buf_stage_new.vhd b/sim/tb_raw_buf_stage_new.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_real_trg_handler.vhd b/sim/tb_real_trg_handler.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_reboot_handler.vhd b/sim/tb_reboot_handler.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_reset_handler.vhd b/sim/tb_reset_handler.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_sfp_rx_handler.vhd b/sim/tb_sfp_rx_handler.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_sfp_rx_handler.vhd.bak b/sim/tb_sfp_rx_handler.vhd.bak old mode 100755 new mode 100644 diff --git a/sim/tb_slv_adc_la.vhd b/sim/tb_slv_adc_la.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_slv_adc_snoop.vhd b/sim/tb_slv_adc_snoop.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_slv_onewire_memory.vhd b/sim/tb_slv_onewire_memory.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_slv_ped_thr_mem.vhd b/sim/tb_slv_ped_thr_mem.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_slv_register_bank.vhd b/sim/tb_slv_register_bank.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_spi_master.vhd b/sim/tb_spi_master.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_spi_master.vhd.bak b/sim/tb_spi_master.vhd.bak old mode 100755 new mode 100644 diff --git a/sim/tb_spi_master_0.vhd b/sim/tb_spi_master_0.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_spi_real_slim.vhd b/sim/tb_spi_real_slim.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_test_media.vhd b/sim/tb_test_media.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_test_media.vhd.bak b/sim/tb_test_media.vhd.bak old mode 100755 new mode 100644 diff --git a/sim/tb_trb_net16_ibuf2.vhd b/sim/tb_trb_net16_ibuf2.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_trb_net_sbuf2.vhd b/sim/tb_trb_net_sbuf2.vhd old mode 100755 new mode 100644 diff --git a/sim/tb_trb_net_sbuf3.vhd b/sim/tb_trb_net_sbuf3.vhd old mode 100755 new mode 100644 diff --git a/design/adc_apv_mapping.mem b/source/adc_apv_mapping.mem similarity index 100% rename from design/adc_apv_mapping.mem rename to source/adc_apv_mapping.mem diff --git a/design/adc_channel_select.vhd b/source/adc_channel_select.vhd similarity index 100% rename from design/adc_channel_select.vhd rename to source/adc_channel_select.vhd diff --git a/design/adc_crossover.vhd b/source/adc_crossover.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/adc_crossover.vhd rename to source/adc_crossover.vhd diff --git a/design/adc_data_handler.vhd b/source/adc_data_handler.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/adc_data_handler.vhd rename to source/adc_data_handler.vhd diff --git a/design/adc_onewire_mapping.mem b/source/adc_onewire_mapping.mem similarity index 100% rename from design/adc_onewire_mapping.mem rename to source/adc_onewire_mapping.mem diff --git a/design/adc_twochannels.vhd b/source/adc_twochannels.vhd similarity index 100% rename from design/adc_twochannels.vhd rename to source/adc_twochannels.vhd diff --git a/design/adcmv3_components.vhd b/source/adcmv3_components.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/adcmv3_components.vhd rename to source/adcmv3_components.vhd diff --git a/design/adcmv3_testfifo.vhd b/source/adcmv3_testfifo.vhd similarity index 100% rename from design/adcmv3_testfifo.vhd rename to source/adcmv3_testfifo.vhd diff --git a/design/apv_adc_mapping.mem b/source/apv_adc_mapping.mem similarity index 100% rename from design/apv_adc_mapping.mem rename to source/apv_adc_mapping.mem diff --git a/design/apv_digital.vhd b/source/apv_digital.vhd similarity index 100% rename from design/apv_digital.vhd rename to source/apv_digital.vhd diff --git a/design/apv_lock_sm.vhd b/source/apv_lock_sm.vhd similarity index 100% rename from design/apv_lock_sm.vhd rename to source/apv_lock_sm.vhd diff --git a/design/apv_locker.vhd b/source/apv_locker.vhd similarity index 100% rename from design/apv_locker.vhd rename to source/apv_locker.vhd diff --git a/design/apv_mapping.mem b/source/apv_mapping.mem similarity index 100% rename from design/apv_mapping.mem rename to source/apv_mapping.mem diff --git a/design/apv_pc_nc_alu.vhd b/source/apv_pc_nc_alu.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/apv_pc_nc_alu.vhd rename to source/apv_pc_nc_alu.vhd diff --git a/design/apv_raw_buffer.vhd b/source/apv_raw_buffer.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/apv_raw_buffer.vhd rename to source/apv_raw_buffer.vhd diff --git a/design/apv_sync_handler.vhd b/source/apv_sync_handler.vhd similarity index 100% rename from design/apv_sync_handler.vhd rename to source/apv_sync_handler.vhd diff --git a/design/apv_trg_handler.vhd b/source/apv_trg_handler.vhd similarity index 100% rename from design/apv_trg_handler.vhd rename to source/apv_trg_handler.vhd diff --git a/design/apv_trgctrl.vhd b/source/apv_trgctrl.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/apv_trgctrl.vhd rename to source/apv_trgctrl.vhd diff --git a/design/buf_toc.vhd b/source/buf_toc.vhd similarity index 100% rename from design/buf_toc.vhd rename to source/buf_toc.vhd diff --git a/design/dbg_reg.vhd b/source/dbg_reg.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/dbg_reg.vhd rename to source/dbg_reg.vhd diff --git a/design/eds_buf.vhd b/source/eds_buf.vhd similarity index 100% rename from design/eds_buf.vhd rename to source/eds_buf.vhd diff --git a/design/frmctr_check.vhd b/source/frmctr_check.vhd similarity index 100% rename from design/frmctr_check.vhd rename to source/frmctr_check.vhd diff --git a/design/i2c_gstart.vhd b/source/i2c_gstart.vhd similarity index 100% rename from design/i2c_gstart.vhd rename to source/i2c_gstart.vhd diff --git a/design/i2c_master.vhd b/source/i2c_master.vhd similarity index 100% rename from design/i2c_master.vhd rename to source/i2c_master.vhd diff --git a/design/i2c_sendb.vhd b/source/i2c_sendb.vhd similarity index 100% rename from design/i2c_sendb.vhd rename to source/i2c_sendb.vhd diff --git a/design/i2c_slim.vhd b/source/i2c_slim.vhd similarity index 100% rename from design/i2c_slim.vhd rename to source/i2c_slim.vhd diff --git a/design/ipu_fifo_stage.vhd b/source/ipu_fifo_stage.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/ipu_fifo_stage.vhd rename to source/ipu_fifo_stage.vhd diff --git a/design/ipu_fifo_stage_BACK.vhd b/source/ipu_fifo_stage_BACK.vhd similarity index 100% rename from design/ipu_fifo_stage_BACK.vhd rename to source/ipu_fifo_stage_BACK.vhd diff --git a/design/logic_analyzer.vhd b/source/logic_analyzer.vhd similarity index 100% rename from design/logic_analyzer.vhd rename to source/logic_analyzer.vhd diff --git a/design/max_data.vhd b/source/max_data.vhd similarity index 100% rename from design/max_data.vhd rename to source/max_data.vhd diff --git a/design/my_sbuf.vhd b/source/my_sbuf.vhd similarity index 100% rename from design/my_sbuf.vhd rename to source/my_sbuf.vhd diff --git a/design/onewire_master.vhd b/source/onewire_master.vhd similarity index 100% rename from design/onewire_master.vhd rename to source/onewire_master.vhd diff --git a/design/ped_corr_ctrl.vhd b/source/ped_corr_ctrl.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/ped_corr_ctrl.vhd rename to source/ped_corr_ctrl.vhd diff --git a/design/ped_thr_mem.mem b/source/ped_thr_mem.mem similarity index 100% rename from design/ped_thr_mem.mem rename to source/ped_thr_mem.mem diff --git a/design/pulse_stretch.vhd b/source/pulse_stretch.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/pulse_stretch.vhd rename to source/pulse_stretch.vhd diff --git a/design/pulse_sync.vhd b/source/pulse_sync.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/pulse_sync.vhd rename to source/pulse_sync.vhd diff --git a/design/raw_buf_stage.vhd b/source/raw_buf_stage.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/raw_buf_stage.vhd rename to source/raw_buf_stage.vhd diff --git a/design/real_trg_handler.vhd b/source/real_trg_handler.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/real_trg_handler.vhd rename to source/real_trg_handler.vhd diff --git a/design/real_trg_handler_BACKUP.vhd b/source/real_trg_handler_BACKUP.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/real_trg_handler_BACKUP.vhd rename to source/real_trg_handler_BACKUP.vhd diff --git a/design/reboot_handler.vhd b/source/reboot_handler.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/reboot_handler.vhd rename to source/reboot_handler.vhd diff --git a/design/ref_row_sel.vhd b/source/ref_row_sel.vhd similarity index 100% rename from design/ref_row_sel.vhd rename to source/ref_row_sel.vhd diff --git a/design/replacement.vhd b/source/replacement.vhd similarity index 100% rename from design/replacement.vhd rename to source/replacement.vhd diff --git a/design/reset_handler.vhd b/source/reset_handler.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/reset_handler.vhd rename to source/reset_handler.vhd diff --git a/design/rich_trb.vhd b/source/rich_trb.vhd old mode 100755 new mode 100644 similarity index 98% rename from design/rich_trb.vhd rename to source/rich_trb.vhd index 960127c..a58448e --- a/design/rich_trb.vhd +++ b/source/rich_trb.vhd @@ -24,8 +24,8 @@ port( SD_LOS_IN : in std_logic; ONEWIRE_INOUT : inout std_logic; -- common regIO status / control registers - COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common status register, bit definitions like in WIKI - COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common control register, bit definitions like in WIKI + COMMON_STAT_REG_IN : in std_logic_vector(8*32-1 downto 0); -- common status register, bit definitions like in WIKI + COMMON_CTRL_REG_OUT : out std_logic_vector(3*32-1 downto 0); -- common control register, bit definitions like in WIKI -- status register input to regIO / control register output from regIO CONTROL_OUT : out std_logic_vector(63 downto 0); STATUS_IN : in std_logic_vector(127 downto 0); diff --git a/design/sbuf.vhd b/source/sbuf.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/sbuf.vhd rename to source/sbuf.vhd diff --git a/design/sfp_rx_handler.vhd b/source/sfp_rx_handler.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/sfp_rx_handler.vhd rename to source/sfp_rx_handler.vhd diff --git a/design/sfp_rx_handler_BACK2.vhd b/source/sfp_rx_handler_BACK2.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/sfp_rx_handler_BACK2.vhd rename to source/sfp_rx_handler_BACK2.vhd diff --git a/design/sfp_rx_handler_BACK_0.vhd b/source/sfp_rx_handler_BACK_0.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/sfp_rx_handler_BACK_0.vhd rename to source/sfp_rx_handler_BACK_0.vhd diff --git a/design/slave_bus.vhd b/source/slave_bus.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/slave_bus.vhd rename to source/slave_bus.vhd diff --git a/design/slv_adc_la.vhd b/source/slv_adc_la.vhd similarity index 100% rename from design/slv_adc_la.vhd rename to source/slv_adc_la.vhd diff --git a/design/slv_adc_snoop.vhd b/source/slv_adc_snoop.vhd similarity index 100% rename from design/slv_adc_snoop.vhd rename to source/slv_adc_snoop.vhd diff --git a/design/slv_half_register.vhd b/source/slv_half_register.vhd similarity index 100% rename from design/slv_half_register.vhd rename to source/slv_half_register.vhd diff --git a/design/slv_memory_true.vhd b/source/slv_memory_true.vhd similarity index 100% rename from design/slv_memory_true.vhd rename to source/slv_memory_true.vhd diff --git a/design/slv_onewire_memory.vhd b/source/slv_onewire_memory.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/slv_onewire_memory.vhd rename to source/slv_onewire_memory.vhd diff --git a/design/slv_ped_thr_mem.vhd b/source/slv_ped_thr_mem.vhd similarity index 100% rename from design/slv_ped_thr_mem.vhd rename to source/slv_ped_thr_mem.vhd diff --git a/design/slv_register.vhd b/source/slv_register.vhd similarity index 100% rename from design/slv_register.vhd rename to source/slv_register.vhd diff --git a/design/slv_register_bank.vhd b/source/slv_register_bank.vhd similarity index 100% rename from design/slv_register_bank.vhd rename to source/slv_register_bank.vhd diff --git a/design/slv_status.vhd b/source/slv_status.vhd similarity index 100% rename from design/slv_status.vhd rename to source/slv_status.vhd diff --git a/design/slv_status_bank.vhd b/source/slv_status_bank.vhd similarity index 100% rename from design/slv_status_bank.vhd rename to source/slv_status_bank.vhd diff --git a/design/spare_onewire_mapping.mem b/source/spare_onewire_mapping.mem similarity index 100% rename from design/spare_onewire_mapping.mem rename to source/spare_onewire_mapping.mem diff --git a/design/spi_adc_master.vhd b/source/spi_adc_master.vhd similarity index 100% rename from design/spi_adc_master.vhd rename to source/spi_adc_master.vhd diff --git a/design/spi_real_slim.vhd b/source/spi_real_slim.vhd similarity index 100% rename from design/spi_real_slim.vhd rename to source/spi_real_slim.vhd diff --git a/design/state_sync.vhd b/source/state_sync.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/state_sync.vhd rename to source/state_sync.vhd diff --git a/design/tb_count_unit.vhd b/source/tb_count_unit.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/tb_count_unit.vhd rename to source/tb_count_unit.vhd diff --git a/design/tb_count_unit.vhd.bak b/source/tb_count_unit.vhd.bak old mode 100755 new mode 100644 similarity index 100% rename from design/tb_count_unit.vhd.bak rename to source/tb_count_unit.vhd.bak diff --git a/design/test_media.vhd b/source/test_media.vhd old mode 100755 new mode 100644 similarity index 100% rename from design/test_media.vhd rename to source/test_media.vhd diff --git a/test.txt b/test.txt old mode 100755 new mode 100644 diff --git a/tunnel.sh b/tunnel.sh old mode 100644 new mode 100755 -- 2.43.0