From 31cc95ff66441f6d2b2d547abe7e654d009fae75 Mon Sep 17 00:00:00 2001 From: Tobias Weber Date: Fri, 26 Sep 2014 17:00:18 +0200 Subject: [PATCH] Clock generator for mupix 50 MHz clock --- mupix/cores/pll_in200_out100_50.ipx | 8 +++ mupix/cores/pll_in200_out100_50.lpc | 66 +++++++++++++++++ mupix/cores/pll_in200_out100_50.vhd | 107 ++++++++++++++++++++++++++++ 3 files changed, 181 insertions(+) create mode 100644 mupix/cores/pll_in200_out100_50.ipx create mode 100644 mupix/cores/pll_in200_out100_50.lpc create mode 100644 mupix/cores/pll_in200_out100_50.vhd diff --git a/mupix/cores/pll_in200_out100_50.ipx b/mupix/cores/pll_in200_out100_50.ipx new file mode 100644 index 0000000..0c06a01 --- /dev/null +++ b/mupix/cores/pll_in200_out100_50.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/mupix/cores/pll_in200_out100_50.lpc b/mupix/cores/pll_in200_out100_50.lpc new file mode 100644 index 0000000..5e2a6b0 --- /dev/null +++ b/mupix/cores/pll_in200_out100_50.lpc @@ -0,0 +1,66 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.4 +ModuleName=pll_in200_out100_50 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/25/2013 +Time=15:59:42 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=200 +Div=2 +ClkOPBp=0 +Post=8 +U_OFrq=100 +OP_Tol=0.0 +OFrq=100.000000 +DutyTrimP=Rising +DelayMultP=0 +fb_mode=Internal +Mult=1 +Phase=0.0 +Duty=8 +DelayMultS=0 +DPD=50% Duty +DutyTrimS=Rising +DelayMultD=0 +ClkOSDelay=0 +PhaseDuty=Static +CLKOK_INPUT=CLKOP +SecD=2 +U_KFrq=50 +OK_Tol=0.0 +KFrq=50.000000 +ClkRst=0 +PCDR=1 +FINDELA=0 +VcoRate= +Bandwidth=1.485393 +;DelayControl=No +EnCLKOS=1 +ClkOSBp=1 +EnCLKOK=1 +ClkOKBp=0 +enClkOK2=0 diff --git a/mupix/cores/pll_in200_out100_50.vhd b/mupix/cores/pll_in200_out100_50.vhd new file mode 100644 index 0000000..f189194 --- /dev/null +++ b/mupix/cores/pll_in200_out100_50.vhd @@ -0,0 +1,107 @@ +-- VHDL netlist generated by SCUBA Diamond_2.2_Production (99) +-- Module Version: 5.4 +--/d/jspc29/lattice/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n pll_in200_out100_50 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypasss -fclkop 100 -fclkop_tol 0.0 -fb_mode INTERNAL -phaseadj 0.0 -duty 8 -fclkok 50 -fclkok_tol 0.0 -clkoki 0 -use_rst -noclkok2 -bw -e + +-- Sun Aug 25 15:59:42 2013 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity pll_in200_out100_50 is + port ( + CLK: in std_logic; + RESET: in std_logic; + CLKOP: out std_logic; + CLKOS: out std_logic; + CLKOK: out std_logic; + LOCK: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of pll_in200_out100_50 : entity is true; +end pll_in200_out100_50; + +architecture Structure of pll_in200_out100_50 is + + -- internal signal declarations + signal CLKOS_t: std_logic; + signal CLKOP_t: std_logic; + signal CLKFB_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; + FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOK : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "100.000000"; + attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "200.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; + attribute FREQUENCY_PIN_CLKOK of PLLInst_0 : label is "50.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLF + generic map (FEEDBK_PATH=> "INTERNAL", CLKOK_BYPASS=> "DISABLED", + CLKOS_BYPASS=> "ENABLED", CLKOP_BYPASS=> "DISABLED", CLKOK_INPUT=> "CLKOP", + DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, CLKOS_TRIM_DELAY=> 0, + CLKOS_TRIM_POL=> "RISING", CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 2, CLKOP_DIV=> 8, CLKFB_DIV=> 1, CLKI_DIV=> 2, + FIN=> "200.000000") + port map (CLKI=>CLK, CLKFB=>CLKFB_t, RST=>RESET, RSTK=>scuba_vlo, + WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, DRPAI2=>scuba_vlo, + DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, DFPAI3=>scuba_vlo, + DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, DFPAI0=>scuba_vlo, + FDA3=>scuba_vlo, FDA2=>scuba_vlo, FDA1=>scuba_vlo, + FDA0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, + CLKOK=>CLKOK, CLKOK2=>open, LOCK=>LOCK, CLKINTFB=>CLKFB_t); + + CLKOS <= CLKOS_t; + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of pll_in200_out100_50 is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on -- 2.43.0