From 31fbf0414f16aa91941df848d6abd85458c02487 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 19 Aug 2013 23:00:00 +0200 Subject: [PATCH] deleted files which are now in mvd_vhdl --- vhdl/code/blank_ram.vhd | 80 - vhdl/code/copy_ram.vhd | 103 - vhdl/code/crc_32.vhd | 99 - vhdl/code/jtag_bypassreg_testchain_m10.vhd | 325 -- vhdl/code/jtag_check_crc_ram1a.vhd | 200 - vhdl/code/jtag_cmd_m26c.vhd | 2262 ----------- vhdl/code/jtag_constants.vhd | 103 - vhdl/code/jtag_delay_expected_values.vhd | 121 - vhdl/code/jtag_init_ram1b.vhd | 142 - vhdl/code/jtag_misc.vhd | 50 - ...ag_mux_buffer_tms_tdi_out_and_metainfo.vhd | 188 - vhdl/code/jtag_mvd.vhd | 670 ---- vhdl/code/jtag_pulses.vhd | 120 - vhdl/code/jtag_read_m26devid_m10.vhd | 288 -- vhdl/code/jtag_tck_out_component.vhd | 52 - vhdl/code/jtag_tdo_compare_count_m10.vhd | 224 -- .../jtag_tdo_compare_counttotal_noram_m10.vhd | 134 - vhdl/code/jtag_tdo_data_to_ram_m10.vhd | 209 - vhdl/code/jtag_tdo_sample.vhd | 110 - vhdl/code/jtag_update_error_counts_ram3a.vhd | 522 --- vhdl/code/jtag_write_m10.vhd | 586 --- vhdl/code/mathhelpers.vhd | 40 - vhdl/code/ram_dp.vhd | 44 - vhdl/code/ram_mux2to1_readport.vhd | 34 - vhdl/code/ram_mux2to1_writeport.vhd | 48 - vhdl/code/ram_mux4to1_readport.vhd | 47 - vhdl/code/tb/jtag_cmd_m26c_test.vhd | 3399 ----------------- ...jtag_cmd_m26c_test_regvaluesfrominput2.vhd | 1063 ------ ...cmd_m26c_test_regvaluesfrominput2_test.vhd | 77 - vhdl/code/tb/jtag_simulation_constants.vhd | 11 - vhdl/code/tb/jtag_tap_mi26_hard.vhd | 504 --- vhdl/code/tb/jtag_write_m10_test.vhd | 363 -- vhdl/compile_mvdjtag_frankfurt.pl | 158 - vhdl/sim/sim_jtag_cmd_m26c.prj.mpf | 1754 --------- vhdl/trb3_periph_mvdjtag.p2t | 20 - vhdl/trb3_periph_mvdjtag.p3t | 5 - vhdl/trb3_periph_mvdjtag.prj | 174 - vhdl/trb3_periph_mvdjtag.pt | 10 - vhdl/trb3_periph_mvdjtag.vhd | 653 ---- vhdl/trb3_periph_mvdjtag_constraints.lpf | 78 - 40 files changed, 15070 deletions(-) delete mode 100644 vhdl/code/blank_ram.vhd delete mode 100644 vhdl/code/copy_ram.vhd delete mode 100644 vhdl/code/crc_32.vhd delete mode 100755 vhdl/code/jtag_bypassreg_testchain_m10.vhd delete mode 100755 vhdl/code/jtag_check_crc_ram1a.vhd delete mode 100644 vhdl/code/jtag_cmd_m26c.vhd delete mode 100644 vhdl/code/jtag_constants.vhd delete mode 100755 vhdl/code/jtag_delay_expected_values.vhd delete mode 100755 vhdl/code/jtag_init_ram1b.vhd delete mode 100644 vhdl/code/jtag_misc.vhd delete mode 100755 vhdl/code/jtag_mux_buffer_tms_tdi_out_and_metainfo.vhd delete mode 100644 vhdl/code/jtag_mvd.vhd delete mode 100644 vhdl/code/jtag_pulses.vhd delete mode 100644 vhdl/code/jtag_read_m26devid_m10.vhd delete mode 100644 vhdl/code/jtag_tck_out_component.vhd delete mode 100644 vhdl/code/jtag_tdo_compare_count_m10.vhd delete mode 100644 vhdl/code/jtag_tdo_compare_counttotal_noram_m10.vhd delete mode 100644 vhdl/code/jtag_tdo_data_to_ram_m10.vhd delete mode 100644 vhdl/code/jtag_tdo_sample.vhd delete mode 100644 vhdl/code/jtag_update_error_counts_ram3a.vhd delete mode 100644 vhdl/code/jtag_write_m10.vhd delete mode 100644 vhdl/code/mathhelpers.vhd delete mode 100755 vhdl/code/ram_dp.vhd delete mode 100755 vhdl/code/ram_mux2to1_readport.vhd delete mode 100755 vhdl/code/ram_mux2to1_writeport.vhd delete mode 100755 vhdl/code/ram_mux4to1_readport.vhd delete mode 100644 vhdl/code/tb/jtag_cmd_m26c_test.vhd delete mode 100644 vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2.vhd delete mode 100644 vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2_test.vhd delete mode 100644 vhdl/code/tb/jtag_simulation_constants.vhd delete mode 100644 vhdl/code/tb/jtag_tap_mi26_hard.vhd delete mode 100644 vhdl/code/tb/jtag_write_m10_test.vhd delete mode 100755 vhdl/compile_mvdjtag_frankfurt.pl delete mode 100644 vhdl/sim/sim_jtag_cmd_m26c.prj.mpf delete mode 100644 vhdl/trb3_periph_mvdjtag.p2t delete mode 100644 vhdl/trb3_periph_mvdjtag.p3t delete mode 100644 vhdl/trb3_periph_mvdjtag.prj delete mode 100644 vhdl/trb3_periph_mvdjtag.pt delete mode 100644 vhdl/trb3_periph_mvdjtag.vhd delete mode 100644 vhdl/trb3_periph_mvdjtag_constraints.lpf diff --git a/vhdl/code/blank_ram.vhd b/vhdl/code/blank_ram.vhd deleted file mode 100644 index e9c132b..0000000 --- a/vhdl/code/blank_ram.vhd +++ /dev/null @@ -1,80 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; ---USE IEEE.std_logic_ARITH.ALL; ---USE IEEE.std_logic_UNSIGNED.ALL; -USE IEEE.numeric_std.ALL; - -library work; - -entity blank_ram is - generic ( - ram_depth : integer; - ram_width : integer := 32 - ); - port ( - CLK_IN : std_logic; - RESET_IN : std_logic; - TRIGGER_BLANK_IN : std_logic; - -- RAM - RAM_A_OUT : out std_logic_vector(ram_depth-1 downto 0); - RAM_D_OUT : out std_logic_vector(ram_width-1 downto 0); - RAM_WR_OUT :out std_logic; - - IDLE_OUT : out std_logic - ); -end entity; - - -architecture blank_ram_arch of blank_ram is -type state_type is (IDLE, BLANKING); -signal state, state_next : state_type; -signal ram_a, ram_a_next : std_logic_vector(ram_depth-1 downto 0); -constant ram_data : std_logic_vector(ram_width-1 downto 0) := (others => '0'); -signal ram_we, ram_we_next : std_logic; -constant addr_end : std_logic_vector(ram_depth-1 downto 0) := (others => '1'); -- this should be a constant -begin ---wordcounter_end <= (others => '1'); -- maximum RAM address -IDLE_OUT <= '1' when state = IDLE else '0'; -RAM_A_OUT <= ram_a; -RAM_WR_OUT <= ram_we; -RAM_D_OUT <= ram_data; -SYNCHRONOUS: process(CLK_IN) -begin - if (rising_edge(CLK_IN)) then - if(RESET_IN = '1') then - state <= idle; - ram_a <= (others => '0'); - ram_we <= '0'; - else - state <= state_next; - ram_a <= ram_a_next; - ram_we <= ram_we_next; - end if; - end if; -end process; - -COMB: process (state, TRIGGER_BLANK_IN, ram_a ) -begin - ram_a_next <= ram_a; - state_next <= state; - ram_we_next <= '0'; - - case state is - when IDLE => - if(TRIGGER_BLANK_IN = '1') then - ram_a_next <= (others => '0'); - ram_we_next <= '1'; - state_next <= BLANKING; - end if; - when BLANKING => - -- counting up rama_a and ramb_a individually is this ok? or how big is the probability that they get asynchronous?? - ram_a_next <= std_logic_vector(unsigned(ram_a)+1); -- word 1 - ram_we_next <= '1'; - if(ram_a = addr_end) then - state_next <= IDLE; - end if; - end case; -end process; - - -end architecture; \ No newline at end of file diff --git a/vhdl/code/copy_ram.vhd b/vhdl/code/copy_ram.vhd deleted file mode 100644 index 640f1b6..0000000 --- a/vhdl/code/copy_ram.vhd +++ /dev/null @@ -1,103 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; ---USE IEEE.std_logic_ARITH.ALL; ---USE IEEE.std_logic_UNSIGNED.ALL; -USE IEEE.numeric_std.ALL; - -library work; - -entity copy_ram is - generic ( - ram_depth : integer; - ram_width : integer := 32 - ); - port ( - CLK_IN : std_logic; - RESET_IN : std_logic; - TRIGGER_COPY_IN : std_logic; - -- RAM3a - RAMA_A_OUT : out std_logic_vector(ram_depth-1 downto 0); - RAMA_D_IN : in std_logic_vector(ram_width-1 downto 0); - -- RAM3b - RAMB_A_OUT : out std_logic_vector(ram_depth-1 downto 0); - RAMB_D_OUT : out std_logic_vector(ram_width-1 downto 0); - RAMB_WR_OUT :out std_logic; - - IDLE_OUT : out std_logic - ); -end entity; - - -architecture copy_ram_arch of copy_ram is -type state_type is (IDLE, READ0, READ1, WRITE_I); -signal state, state_next : state_type; -signal rama_a, rama_a_next : std_logic_vector(ram_depth-1 downto 0); -signal ramb_a, ramb_a_next : std_logic_vector(ram_depth-1 downto 0); -signal ramb_data, ramb_data_next : std_logic_vector(ram_width-1 downto 0); -signal ramb_we, ramb_we_next : std_logic; -constant addr_end : std_logic_vector(ram_depth-1 downto 0) := (others => '1'); -- this should be a constant -begin ---wordcounter_end <= (others => '1'); -- maximum RAM address -IDLE_OUT <= '1' when state = idle else '0'; -RAMA_A_OUT <= rama_a; -RAMB_A_OUT <= ramb_a; -RAMB_WR_OUT <= ramb_we; -RAMB_D_OUT <= ramb_data; -SYNCHRONOUS: process(CLK_IN) -begin - if (rising_edge(CLK_IN)) then - if(RESET_IN = '1') then - state <= idle; - rama_a <= (others => '0'); - ramb_a <= (others => '0'); - ramb_data <= (others => '0'); - ramb_we <= '0'; - else - state <= state_next; - rama_a <= rama_a_next; - ramb_a <= ramb_a_next; - ramb_data <= ramb_data_next; - ramb_we <= ramb_we_next; - end if; - end if; -end process; - -COMB: process (state, TRIGGER_COPY_IN, RAMA_D_IN, rama_a, ramb_a, ramb_data ) -begin - rama_a_next <= rama_a; - ramb_a_next <= ramb_a; - ramb_data_next <= ramb_data; - state_next <= state; - ramb_we_next <= '0'; - - case state is - when IDLE => - if(TRIGGER_COPY_IN = '1') then - rama_a_next <= (others => '0'); - state_next <= READ0; - end if; - when READ0 => - -- counting up rama_a and ramb_a individually is this ok? or how big is the probability that they get asynchronous?? - rama_a_next <= std_logic_vector(unsigned(rama_a)+1); -- word 1 - state_next <= READ1; - when READ1 => - -- counting up rama_a and ramb_a individually is this ok? or how big is the probability that they get asynchronous?? - rama_a_next <= std_logic_vector(unsigned(rama_a)+1); -- word 2 - ramb_a_next <= (others => '0'); -- ramb_a should become zero in two clock cycles - ramb_data_next <= RAMA_D_IN; - ramb_we_next <= '1'; - state_next <= WRITE_I; - when WRITE_I => - rama_a_next <= std_logic_vector(unsigned(rama_a)+1); -- word 3, 4,... - -- write word to RAMB - ramb_a_next <= std_logic_vector(unsigned(ramb_a)+1); - ramb_data_next <= RAMA_D_IN; - ramb_we_next <= '1'; - if(ramb_a = addr_end) then - state_next <= IDLE; --last word is written during idle - end if; - end case; -end process; - - -end architecture; \ No newline at end of file diff --git a/vhdl/code/crc_32.vhd b/vhdl/code/crc_32.vhd deleted file mode 100644 index b941909..0000000 --- a/vhdl/code/crc_32.vhd +++ /dev/null @@ -1,99 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -library work; - -entity CRC_32 is - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(31 downto 0); - CRC_OUT : out std_logic_vector(31 downto 0); - CRC_match : out std_logic - ); -end entity; - --- architecture CRC32_disabled of CRC32 is --- begin --- CRC_match <= '1'; --- CRC_OUT <= (others=>'0'); --- end architecture; - - -------------------------------------------------------------------------------- --- Copyright (C) 2009 OutputLogic.com --- This source file may be used and distributed without restriction --- provided that this copyright statement is not removed from the file --- and that any derivative work contains the original copyright notice --- and the associated disclaimer. --- --- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS --- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED --- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. -------------------------------------------------------------------------------- --- CRC module for data(31:0) --- lfsr(31:0)=1+x^1+x^2+x^4+x^5+x^7+x^8+x^10+x^11+x^12+x^16+x^22+x^23+x^26+x^32; -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; - - -architecture imp_crc32 of CRC_32 is - signal lfsr_q: std_logic_vector (31 downto 0); - signal lfsr_c: std_logic_vector (31 downto 0); -begin - CRC_OUT <= lfsr_q; - - lfsr_c(0) <= lfsr_q(0) xor lfsr_q(6) xor lfsr_q(9) xor lfsr_q(10) xor lfsr_q(12) xor lfsr_q(16) xor lfsr_q(24) xor lfsr_q(25) xor lfsr_q(26) xor lfsr_q(28) xor lfsr_q(29) xor lfsr_q(30) xor lfsr_q(31) xor DATA_IN(0) xor DATA_IN(6) xor DATA_IN(9) xor DATA_IN(10) xor DATA_IN(12) xor DATA_IN(16) xor DATA_IN(24) xor DATA_IN(25) xor DATA_IN(26) xor DATA_IN(28) xor DATA_IN(29) xor DATA_IN(30) xor DATA_IN(31); - lfsr_c(1) <= lfsr_q(0) xor lfsr_q(1) xor lfsr_q(6) xor lfsr_q(7) xor lfsr_q(9) xor lfsr_q(11) xor lfsr_q(12) xor lfsr_q(13) xor lfsr_q(16) xor lfsr_q(17) xor lfsr_q(24) xor lfsr_q(27) xor lfsr_q(28) xor DATA_IN(0) xor DATA_IN(1) xor DATA_IN(6) xor DATA_IN(7) xor DATA_IN(9) xor DATA_IN(11) xor DATA_IN(12) xor DATA_IN(13) xor DATA_IN(16) xor DATA_IN(17) xor DATA_IN(24) xor DATA_IN(27) xor DATA_IN(28); - lfsr_c(2) <= lfsr_q(0) xor lfsr_q(1) xor lfsr_q(2) xor lfsr_q(6) xor lfsr_q(7) xor lfsr_q(8) xor lfsr_q(9) xor lfsr_q(13) xor lfsr_q(14) xor lfsr_q(16) xor lfsr_q(17) xor lfsr_q(18) xor lfsr_q(24) xor lfsr_q(26) xor lfsr_q(30) xor lfsr_q(31) xor DATA_IN(0) xor DATA_IN(1) xor DATA_IN(2) xor DATA_IN(6) xor DATA_IN(7) xor DATA_IN(8) xor DATA_IN(9) xor DATA_IN(13) xor DATA_IN(14) xor DATA_IN(16) xor DATA_IN(17) xor DATA_IN(18) xor DATA_IN(24) xor DATA_IN(26) xor DATA_IN(30) xor DATA_IN(31); - lfsr_c(3) <= lfsr_q(1) xor lfsr_q(2) xor lfsr_q(3) xor lfsr_q(7) xor lfsr_q(8) xor lfsr_q(9) xor lfsr_q(10) xor lfsr_q(14) xor lfsr_q(15) xor lfsr_q(17) xor lfsr_q(18) xor lfsr_q(19) xor lfsr_q(25) xor lfsr_q(27) xor lfsr_q(31) xor DATA_IN(1) xor DATA_IN(2) xor DATA_IN(3) xor DATA_IN(7) xor DATA_IN(8) xor DATA_IN(9) xor DATA_IN(10) xor DATA_IN(14) xor DATA_IN(15) xor DATA_IN(17) xor DATA_IN(18) xor DATA_IN(19) xor DATA_IN(25) xor DATA_IN(27) xor DATA_IN(31); - lfsr_c(4) <= lfsr_q(0) xor lfsr_q(2) xor lfsr_q(3) xor lfsr_q(4) xor lfsr_q(6) xor lfsr_q(8) xor lfsr_q(11) xor lfsr_q(12) xor lfsr_q(15) xor lfsr_q(18) xor lfsr_q(19) xor lfsr_q(20) xor lfsr_q(24) xor lfsr_q(25) xor lfsr_q(29) xor lfsr_q(30) xor lfsr_q(31) xor DATA_IN(0) xor DATA_IN(2) xor DATA_IN(3) xor DATA_IN(4) xor DATA_IN(6) xor DATA_IN(8) xor DATA_IN(11) xor DATA_IN(12) xor DATA_IN(15) xor DATA_IN(18) xor DATA_IN(19) xor DATA_IN(20) xor DATA_IN(24) xor DATA_IN(25) xor DATA_IN(29) xor DATA_IN(30) xor DATA_IN(31); - lfsr_c(5) <= lfsr_q(0) xor lfsr_q(1) xor lfsr_q(3) xor lfsr_q(4) xor lfsr_q(5) xor lfsr_q(6) xor lfsr_q(7) xor lfsr_q(10) xor lfsr_q(13) xor lfsr_q(19) xor lfsr_q(20) xor lfsr_q(21) xor lfsr_q(24) xor lfsr_q(28) xor lfsr_q(29) xor DATA_IN(0) xor DATA_IN(1) xor DATA_IN(3) xor DATA_IN(4) xor DATA_IN(5) xor DATA_IN(6) xor DATA_IN(7) xor DATA_IN(10) xor DATA_IN(13) xor DATA_IN(19) xor DATA_IN(20) xor DATA_IN(21) xor DATA_IN(24) xor DATA_IN(28) xor DATA_IN(29); - lfsr_c(6) <= lfsr_q(1) xor lfsr_q(2) xor lfsr_q(4) xor lfsr_q(5) xor lfsr_q(6) xor lfsr_q(7) xor lfsr_q(8) xor lfsr_q(11) xor lfsr_q(14) xor lfsr_q(20) xor lfsr_q(21) xor lfsr_q(22) xor lfsr_q(25) xor lfsr_q(29) xor lfsr_q(30) xor DATA_IN(1) xor DATA_IN(2) xor DATA_IN(4) xor DATA_IN(5) xor DATA_IN(6) xor DATA_IN(7) xor DATA_IN(8) xor DATA_IN(11) xor DATA_IN(14) xor DATA_IN(20) xor DATA_IN(21) xor DATA_IN(22) xor DATA_IN(25) xor DATA_IN(29) xor DATA_IN(30); - lfsr_c(7) <= lfsr_q(0) xor lfsr_q(2) xor lfsr_q(3) xor lfsr_q(5) xor lfsr_q(7) xor lfsr_q(8) xor lfsr_q(10) xor lfsr_q(15) xor lfsr_q(16) xor lfsr_q(21) xor lfsr_q(22) xor lfsr_q(23) xor lfsr_q(24) xor lfsr_q(25) xor lfsr_q(28) xor lfsr_q(29) xor DATA_IN(0) xor DATA_IN(2) xor DATA_IN(3) xor DATA_IN(5) xor DATA_IN(7) xor DATA_IN(8) xor DATA_IN(10) xor DATA_IN(15) xor DATA_IN(16) xor DATA_IN(21) xor DATA_IN(22) xor DATA_IN(23) xor DATA_IN(24) xor DATA_IN(25) xor DATA_IN(28) xor DATA_IN(29); - lfsr_c(8) <= lfsr_q(0) xor lfsr_q(1) xor lfsr_q(3) xor lfsr_q(4) xor lfsr_q(8) xor lfsr_q(10) xor lfsr_q(11) xor lfsr_q(12) xor lfsr_q(17) xor lfsr_q(22) xor lfsr_q(23) xor lfsr_q(28) xor lfsr_q(31) xor DATA_IN(0) xor DATA_IN(1) xor DATA_IN(3) xor DATA_IN(4) xor DATA_IN(8) xor DATA_IN(10) xor DATA_IN(11) xor DATA_IN(12) xor DATA_IN(17) xor DATA_IN(22) xor DATA_IN(23) xor DATA_IN(28) xor DATA_IN(31); - lfsr_c(9) <= lfsr_q(1) xor lfsr_q(2) xor lfsr_q(4) xor lfsr_q(5) xor lfsr_q(9) xor lfsr_q(11) xor lfsr_q(12) xor lfsr_q(13) xor lfsr_q(18) xor lfsr_q(23) xor lfsr_q(24) xor lfsr_q(29) xor DATA_IN(1) xor DATA_IN(2) xor DATA_IN(4) xor DATA_IN(5) xor DATA_IN(9) xor DATA_IN(11) xor DATA_IN(12) xor DATA_IN(13) xor DATA_IN(18) xor DATA_IN(23) xor DATA_IN(24) xor DATA_IN(29); - lfsr_c(10) <= lfsr_q(0) xor lfsr_q(2) xor lfsr_q(3) xor lfsr_q(5) xor lfsr_q(9) xor lfsr_q(13) xor lfsr_q(14) xor lfsr_q(16) xor lfsr_q(19) xor lfsr_q(26) xor lfsr_q(28) xor lfsr_q(29) xor lfsr_q(31) xor DATA_IN(0) xor DATA_IN(2) xor DATA_IN(3) xor DATA_IN(5) xor DATA_IN(9) xor DATA_IN(13) xor DATA_IN(14) xor DATA_IN(16) xor DATA_IN(19) xor DATA_IN(26) xor DATA_IN(28) xor DATA_IN(29) xor DATA_IN(31); - lfsr_c(11) <= lfsr_q(0) xor lfsr_q(1) xor lfsr_q(3) xor lfsr_q(4) xor lfsr_q(9) xor lfsr_q(12) xor lfsr_q(14) xor lfsr_q(15) xor lfsr_q(16) xor lfsr_q(17) xor lfsr_q(20) xor lfsr_q(24) xor lfsr_q(25) xor lfsr_q(26) xor lfsr_q(27) xor lfsr_q(28) xor lfsr_q(31) xor DATA_IN(0) xor DATA_IN(1) xor DATA_IN(3) xor DATA_IN(4) xor DATA_IN(9) xor DATA_IN(12) xor DATA_IN(14) xor DATA_IN(15) xor DATA_IN(16) xor DATA_IN(17) xor DATA_IN(20) xor DATA_IN(24) xor DATA_IN(25) xor DATA_IN(26) xor DATA_IN(27) xor DATA_IN(28) xor DATA_IN(31); - lfsr_c(12) <= lfsr_q(0) xor lfsr_q(1) xor lfsr_q(2) xor lfsr_q(4) xor lfsr_q(5) xor lfsr_q(6) xor lfsr_q(9) xor lfsr_q(12) xor lfsr_q(13) xor lfsr_q(15) xor lfsr_q(17) xor lfsr_q(18) xor lfsr_q(21) xor lfsr_q(24) xor lfsr_q(27) xor lfsr_q(30) xor lfsr_q(31) xor DATA_IN(0) xor DATA_IN(1) xor DATA_IN(2) xor DATA_IN(4) xor DATA_IN(5) xor DATA_IN(6) xor DATA_IN(9) xor DATA_IN(12) xor DATA_IN(13) xor DATA_IN(15) xor DATA_IN(17) xor DATA_IN(18) xor DATA_IN(21) xor DATA_IN(24) xor DATA_IN(27) xor DATA_IN(30) xor DATA_IN(31); - lfsr_c(13) <= lfsr_q(1) xor lfsr_q(2) xor lfsr_q(3) xor lfsr_q(5) xor lfsr_q(6) xor lfsr_q(7) xor lfsr_q(10) xor lfsr_q(13) xor lfsr_q(14) xor lfsr_q(16) xor lfsr_q(18) xor lfsr_q(19) xor lfsr_q(22) xor lfsr_q(25) xor lfsr_q(28) xor lfsr_q(31) xor DATA_IN(1) xor DATA_IN(2) xor DATA_IN(3) xor DATA_IN(5) xor DATA_IN(6) xor DATA_IN(7) xor DATA_IN(10) xor DATA_IN(13) xor DATA_IN(14) xor DATA_IN(16) xor DATA_IN(18) xor DATA_IN(19) xor DATA_IN(22) xor DATA_IN(25) xor DATA_IN(28) xor DATA_IN(31); - lfsr_c(14) <= lfsr_q(2) xor lfsr_q(3) xor lfsr_q(4) xor lfsr_q(6) xor lfsr_q(7) xor lfsr_q(8) xor lfsr_q(11) xor lfsr_q(14) xor lfsr_q(15) xor lfsr_q(17) xor lfsr_q(19) xor lfsr_q(20) xor lfsr_q(23) xor lfsr_q(26) xor lfsr_q(29) xor DATA_IN(2) xor DATA_IN(3) xor DATA_IN(4) xor DATA_IN(6) xor DATA_IN(7) xor DATA_IN(8) xor DATA_IN(11) xor DATA_IN(14) xor DATA_IN(15) xor DATA_IN(17) xor DATA_IN(19) xor DATA_IN(20) xor DATA_IN(23) xor DATA_IN(26) xor DATA_IN(29); - lfsr_c(15) <= lfsr_q(3) xor lfsr_q(4) xor lfsr_q(5) xor lfsr_q(7) xor lfsr_q(8) xor lfsr_q(9) xor lfsr_q(12) xor lfsr_q(15) xor lfsr_q(16) xor lfsr_q(18) xor lfsr_q(20) xor lfsr_q(21) xor lfsr_q(24) xor lfsr_q(27) xor lfsr_q(30) xor DATA_IN(3) xor DATA_IN(4) xor DATA_IN(5) xor DATA_IN(7) xor DATA_IN(8) xor DATA_IN(9) xor DATA_IN(12) xor DATA_IN(15) xor DATA_IN(16) xor DATA_IN(18) xor DATA_IN(20) xor DATA_IN(21) xor DATA_IN(24) xor DATA_IN(27) xor DATA_IN(30); - lfsr_c(16) <= lfsr_q(0) xor lfsr_q(4) xor lfsr_q(5) xor lfsr_q(8) xor lfsr_q(12) xor lfsr_q(13) xor lfsr_q(17) xor lfsr_q(19) xor lfsr_q(21) xor lfsr_q(22) xor lfsr_q(24) xor lfsr_q(26) xor lfsr_q(29) xor lfsr_q(30) xor DATA_IN(0) xor DATA_IN(4) xor DATA_IN(5) xor DATA_IN(8) xor DATA_IN(12) xor DATA_IN(13) xor DATA_IN(17) xor DATA_IN(19) xor DATA_IN(21) xor DATA_IN(22) xor DATA_IN(24) xor DATA_IN(26) xor DATA_IN(29) xor DATA_IN(30); - lfsr_c(17) <= lfsr_q(1) xor lfsr_q(5) xor lfsr_q(6) xor lfsr_q(9) xor lfsr_q(13) xor lfsr_q(14) xor lfsr_q(18) xor lfsr_q(20) xor lfsr_q(22) xor lfsr_q(23) xor lfsr_q(25) xor lfsr_q(27) xor lfsr_q(30) xor lfsr_q(31) xor DATA_IN(1) xor DATA_IN(5) xor DATA_IN(6) xor DATA_IN(9) xor DATA_IN(13) xor DATA_IN(14) xor DATA_IN(18) xor DATA_IN(20) xor DATA_IN(22) xor DATA_IN(23) xor DATA_IN(25) xor DATA_IN(27) xor DATA_IN(30) xor DATA_IN(31); - lfsr_c(18) <= lfsr_q(2) xor lfsr_q(6) xor lfsr_q(7) xor lfsr_q(10) xor lfsr_q(14) xor lfsr_q(15) xor lfsr_q(19) xor lfsr_q(21) xor lfsr_q(23) xor lfsr_q(24) xor lfsr_q(26) xor lfsr_q(28) xor lfsr_q(31) xor DATA_IN(2) xor DATA_IN(6) xor DATA_IN(7) xor DATA_IN(10) xor DATA_IN(14) xor DATA_IN(15) xor DATA_IN(19) xor DATA_IN(21) xor DATA_IN(23) xor DATA_IN(24) xor DATA_IN(26) xor DATA_IN(28) xor DATA_IN(31); - lfsr_c(19) <= lfsr_q(3) xor lfsr_q(7) xor lfsr_q(8) xor lfsr_q(11) xor lfsr_q(15) xor lfsr_q(16) xor lfsr_q(20) xor lfsr_q(22) xor lfsr_q(24) xor lfsr_q(25) xor lfsr_q(27) xor lfsr_q(29) xor DATA_IN(3) xor DATA_IN(7) xor DATA_IN(8) xor DATA_IN(11) xor DATA_IN(15) xor DATA_IN(16) xor DATA_IN(20) xor DATA_IN(22) xor DATA_IN(24) xor DATA_IN(25) xor DATA_IN(27) xor DATA_IN(29); - lfsr_c(20) <= lfsr_q(4) xor lfsr_q(8) xor lfsr_q(9) xor lfsr_q(12) xor lfsr_q(16) xor lfsr_q(17) xor lfsr_q(21) xor lfsr_q(23) xor lfsr_q(25) xor lfsr_q(26) xor lfsr_q(28) xor lfsr_q(30) xor DATA_IN(4) xor DATA_IN(8) xor DATA_IN(9) xor DATA_IN(12) xor DATA_IN(16) xor DATA_IN(17) xor DATA_IN(21) xor DATA_IN(23) xor DATA_IN(25) xor DATA_IN(26) xor DATA_IN(28) xor DATA_IN(30); - lfsr_c(21) <= lfsr_q(5) xor lfsr_q(9) xor lfsr_q(10) xor lfsr_q(13) xor lfsr_q(17) xor lfsr_q(18) xor lfsr_q(22) xor lfsr_q(24) xor lfsr_q(26) xor lfsr_q(27) xor lfsr_q(29) xor lfsr_q(31) xor DATA_IN(5) xor DATA_IN(9) xor DATA_IN(10) xor DATA_IN(13) xor DATA_IN(17) xor DATA_IN(18) xor DATA_IN(22) xor DATA_IN(24) xor DATA_IN(26) xor DATA_IN(27) xor DATA_IN(29) xor DATA_IN(31); - lfsr_c(22) <= lfsr_q(0) xor lfsr_q(9) xor lfsr_q(11) xor lfsr_q(12) xor lfsr_q(14) xor lfsr_q(16) xor lfsr_q(18) xor lfsr_q(19) xor lfsr_q(23) xor lfsr_q(24) xor lfsr_q(26) xor lfsr_q(27) xor lfsr_q(29) xor lfsr_q(31) xor DATA_IN(0) xor DATA_IN(9) xor DATA_IN(11) xor DATA_IN(12) xor DATA_IN(14) xor DATA_IN(16) xor DATA_IN(18) xor DATA_IN(19) xor DATA_IN(23) xor DATA_IN(24) xor DATA_IN(26) xor DATA_IN(27) xor DATA_IN(29) xor DATA_IN(31); - lfsr_c(23) <= lfsr_q(0) xor lfsr_q(1) xor lfsr_q(6) xor lfsr_q(9) xor lfsr_q(13) xor lfsr_q(15) xor lfsr_q(16) xor lfsr_q(17) xor lfsr_q(19) xor lfsr_q(20) xor lfsr_q(26) xor lfsr_q(27) xor lfsr_q(29) xor lfsr_q(31) xor DATA_IN(0) xor DATA_IN(1) xor DATA_IN(6) xor DATA_IN(9) xor DATA_IN(13) xor DATA_IN(15) xor DATA_IN(16) xor DATA_IN(17) xor DATA_IN(19) xor DATA_IN(20) xor DATA_IN(26) xor DATA_IN(27) xor DATA_IN(29) xor DATA_IN(31); - lfsr_c(24) <= lfsr_q(1) xor lfsr_q(2) xor lfsr_q(7) xor lfsr_q(10) xor lfsr_q(14) xor lfsr_q(16) xor lfsr_q(17) xor lfsr_q(18) xor lfsr_q(20) xor lfsr_q(21) xor lfsr_q(27) xor lfsr_q(28) xor lfsr_q(30) xor DATA_IN(1) xor DATA_IN(2) xor DATA_IN(7) xor DATA_IN(10) xor DATA_IN(14) xor DATA_IN(16) xor DATA_IN(17) xor DATA_IN(18) xor DATA_IN(20) xor DATA_IN(21) xor DATA_IN(27) xor DATA_IN(28) xor DATA_IN(30); - lfsr_c(25) <= lfsr_q(2) xor lfsr_q(3) xor lfsr_q(8) xor lfsr_q(11) xor lfsr_q(15) xor lfsr_q(17) xor lfsr_q(18) xor lfsr_q(19) xor lfsr_q(21) xor lfsr_q(22) xor lfsr_q(28) xor lfsr_q(29) xor lfsr_q(31) xor DATA_IN(2) xor DATA_IN(3) xor DATA_IN(8) xor DATA_IN(11) xor DATA_IN(15) xor DATA_IN(17) xor DATA_IN(18) xor DATA_IN(19) xor DATA_IN(21) xor DATA_IN(22) xor DATA_IN(28) xor DATA_IN(29) xor DATA_IN(31); - lfsr_c(26) <= lfsr_q(0) xor lfsr_q(3) xor lfsr_q(4) xor lfsr_q(6) xor lfsr_q(10) xor lfsr_q(18) xor lfsr_q(19) xor lfsr_q(20) xor lfsr_q(22) xor lfsr_q(23) xor lfsr_q(24) xor lfsr_q(25) xor lfsr_q(26) xor lfsr_q(28) xor lfsr_q(31) xor DATA_IN(0) xor DATA_IN(3) xor DATA_IN(4) xor DATA_IN(6) xor DATA_IN(10) xor DATA_IN(18) xor DATA_IN(19) xor DATA_IN(20) xor DATA_IN(22) xor DATA_IN(23) xor DATA_IN(24) xor DATA_IN(25) xor DATA_IN(26) xor DATA_IN(28) xor DATA_IN(31); - lfsr_c(27) <= lfsr_q(1) xor lfsr_q(4) xor lfsr_q(5) xor lfsr_q(7) xor lfsr_q(11) xor lfsr_q(19) xor lfsr_q(20) xor lfsr_q(21) xor lfsr_q(23) xor lfsr_q(24) xor lfsr_q(25) xor lfsr_q(26) xor lfsr_q(27) xor lfsr_q(29) xor DATA_IN(1) xor DATA_IN(4) xor DATA_IN(5) xor DATA_IN(7) xor DATA_IN(11) xor DATA_IN(19) xor DATA_IN(20) xor DATA_IN(21) xor DATA_IN(23) xor DATA_IN(24) xor DATA_IN(25) xor DATA_IN(26) xor DATA_IN(27) xor DATA_IN(29); - lfsr_c(28) <= lfsr_q(2) xor lfsr_q(5) xor lfsr_q(6) xor lfsr_q(8) xor lfsr_q(12) xor lfsr_q(20) xor lfsr_q(21) xor lfsr_q(22) xor lfsr_q(24) xor lfsr_q(25) xor lfsr_q(26) xor lfsr_q(27) xor lfsr_q(28) xor lfsr_q(30) xor DATA_IN(2) xor DATA_IN(5) xor DATA_IN(6) xor DATA_IN(8) xor DATA_IN(12) xor DATA_IN(20) xor DATA_IN(21) xor DATA_IN(22) xor DATA_IN(24) xor DATA_IN(25) xor DATA_IN(26) xor DATA_IN(27) xor DATA_IN(28) xor DATA_IN(30); - lfsr_c(29) <= lfsr_q(3) xor lfsr_q(6) xor lfsr_q(7) xor lfsr_q(9) xor lfsr_q(13) xor lfsr_q(21) xor lfsr_q(22) xor lfsr_q(23) xor lfsr_q(25) xor lfsr_q(26) xor lfsr_q(27) xor lfsr_q(28) xor lfsr_q(29) xor lfsr_q(31) xor DATA_IN(3) xor DATA_IN(6) xor DATA_IN(7) xor DATA_IN(9) xor DATA_IN(13) xor DATA_IN(21) xor DATA_IN(22) xor DATA_IN(23) xor DATA_IN(25) xor DATA_IN(26) xor DATA_IN(27) xor DATA_IN(28) xor DATA_IN(29) xor DATA_IN(31); - lfsr_c(30) <= lfsr_q(4) xor lfsr_q(7) xor lfsr_q(8) xor lfsr_q(10) xor lfsr_q(14) xor lfsr_q(22) xor lfsr_q(23) xor lfsr_q(24) xor lfsr_q(26) xor lfsr_q(27) xor lfsr_q(28) xor lfsr_q(29) xor lfsr_q(30) xor DATA_IN(4) xor DATA_IN(7) xor DATA_IN(8) xor DATA_IN(10) xor DATA_IN(14) xor DATA_IN(22) xor DATA_IN(23) xor DATA_IN(24) xor DATA_IN(26) xor DATA_IN(27) xor DATA_IN(28) xor DATA_IN(29) xor DATA_IN(30); - lfsr_c(31) <= lfsr_q(5) xor lfsr_q(8) xor lfsr_q(9) xor lfsr_q(11) xor lfsr_q(15) xor lfsr_q(23) xor lfsr_q(24) xor lfsr_q(25) xor lfsr_q(27) xor lfsr_q(28) xor lfsr_q(29) xor lfsr_q(30) xor lfsr_q(31) xor DATA_IN(5) xor DATA_IN(8) xor DATA_IN(9) xor DATA_IN(11) xor DATA_IN(15) xor DATA_IN(23) xor DATA_IN(24) xor DATA_IN(25) xor DATA_IN(27) xor DATA_IN(28) xor DATA_IN(29) xor DATA_IN(30) xor DATA_IN(31); - - process(lfsr_q) begin - if(lfsr_q = 0) then - CRC_match <= '1'; - else - CRC_match <= '0'; - end if; - end process; - - process (CLK,RESET) begin - if (RESET = '1') then - lfsr_q <= b"11111111111111111111111111111111"; - elsif (rising_edge(CLK)) then - if (CLK_EN = '1') then - lfsr_q <= lfsr_c; - end if; - end if; - end process; -end architecture imp_crc32; \ No newline at end of file diff --git a/vhdl/code/jtag_bypassreg_testchain_m10.vhd b/vhdl/code/jtag_bypassreg_testchain_m10.vhd deleted file mode 100755 index b8a72b7..0000000 --- a/vhdl/code/jtag_bypassreg_testchain_m10.vhd +++ /dev/null @@ -1,325 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; - -library work; ---use work.version.all; -use work.jtag_constants.all; -use work.jtag_misc.all; - -entity jtag_bypassreg_testchain_m10 is - generic ( --- delay : integer := 0; -- this is the same value as in jtag_delay_expected_values - MAX_NUMCHIPS : integer; - MAX_NUMCHIPS_LD : integer; - JTAG_M26_IRLEN : integer; - - max_bitcounter_ld : integer;-- set to: MAX_NUMCHIPS_LD+JTAG_M26_IRLEN_LD + 7-- bitcounter counts to ir_fill_ones_length, to zerofill_length aswell as from begin of sending pattern to end of receiving pattern (zerofill_length). should write something like: max(MAX_NUMCHIPS_LD+JTAG_M26_IRLEN_LD, 7)+1. - - ld_maxdelay : integer := 2; -- floor of ld maxdelay - pattern_length : integer := 4; - pattern : std_logic_vector(4-1 downto 0) := "1001"; - zerofill_numzeros_required : integer := 5 -- minimum number of zeros appearing at tdo while first zero filling phase - ); - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - BEGIN_JTAGBITCALC_IN : in std_logic; - TRIGGER_BEGIN_TESTCHAIN_IN : in std_logic; - IDLE_OUT : out std_logic; - - -- length in chips of the chain -- corresponds to the number of bits the - -- output is shifted compared to the input, because the BYPASS registers - -- are selected, which are only one bit long - CHAIN_LENGTH_OUT : out std_logic_vector(max_bitcounter_ld-1 downto 0); - -- if after feeding in a sufficiently long sequence - -- the expected output pattern doesnt occur - CHAIN_BROKEN_OUT : out std_logic; - - ENABLE_JTAG_CLOCK_OUT : out std_logic; - LAST_TCK_CYCLE_OUT : out std_logic; - TMS_OUT : out std_logic; - TDI_OUT : out std_logic; - TDO_IN : in std_logic; - DELAY_IN : in std_logic_vector(ld_maxdelay-1 downto 0) - ); -end entity; - - -architecture jtag_bypassreg_testchain_m10_arch of jtag_bypassreg_testchain_m10 is -constant ir_fill_ones_length : integer := MAX_NUMCHIPS*JTAG_M26_IRLEN+100; -constant zerofill_length : integer := MAX_NUMCHIPS + 10; - -signal bitcounter, bitcounter_next : unsigned(max_bitcounter_ld-1 downto 0); -signal nfa_state, nfa_state_next : std_logic_vector (pattern_length-1 downto 0); -signal input_bit : std_logic; - - --- COPIED FROM jtag_write_m10: --- this state controls the global behaviour. on reset state idle is entered, --- on trigger wait_begin_jtagbitcalc is entered --- when begin_jtagbitcalc is set, state becomes either idle or --- processing and after finished wait_begin_jtagbitcalc is entered again -type state_type is (IDLE, WAIT_BEGIN_JTAGBITCALC, PROCESSING); -signal state, state_next : state_type; --- the substate represents the processing state we are in, the name suffix _pi tells how many clock cycles have been spent up to the current state, processing. i must be smaller than 10 so that with 100MHz system clock the JTAG clock can be operated at 10 MHz. -type substate_type is (none_p1, ir_ones_p1, dr_zeros_p1, dr_pattern_p1, dr_pattern2_p2); -signal substate, substate_next : substate_type; --- COPIED FROM jtag_write_m10: --- operation = "00": JTAG_RESET, operation = "01" : WRITE_IR, operation = "10": WRITE_DR, operation = "11": none --- the operation is set on entering processing state, in setup operation is set to none -signal operation, operation_next : unsigned(1 downto 0); --- COPIED FROM jtag_write_m10, modified --- JTAG_RESET: operation_phase = 0000-0101 : set TMS=1 for JTAG reset --- WRITE_IR: operation_phase = 0000 : set TMS=0 => Run-Test/Idle --- operation_phase = 0001 : set TMS=1 => Select-DR-Scan --- operation_phase = 0010 : set TMS=1 => Select-IR-Scan --- operation_phase = 0011 : set TMS=0 => Capture-IR --- operation_phase = 0100 : set TMS=0 => Shift-IR --- operation_phase = 0101 : set TMS=0 => Shift-IR, HERE SHIFTING OF DATA HAPPENS --- operation_phase = 0110 : set TMS=1 => Exit1-IR, HERE LAST BIT OF IR IS SHIFTED --- operation_phase = 0111 : set TMS=1 => Update-IR --- operation_phase = 1000 : set TMS=0 => Run-Test/Idle --- WRITE_DR: operation_phase = 0000 : set TMS=1 => Select-DR-Scan --- operation_phase = 0001 : set TMS=0 => Capture-DR --- operation_phase = 0010 : set TMS=0 => Shift-DR --- operation_phase = 0011 : set TMS=0 => Shift-DR, HERE SHIFTING OF DATA HAPPENS, shift zeros --- operation_phase = 0100 : set TMS=0 => Shift-DR, HERE SHIFTING OF DATA HAPPENS, shift pattern followed by zeros --- operation_phase = 0101 : set TMS=1 => Exit1-DR, HERE LAST BIT OF IR IS SHIFTED --- operation_phase = 0110 : set TMS=1 => Update-DR --- operation_phase = 0111 : set TMS=0 => Run-Test/Idle --- warning: operation phase may change during processing (because length of register is retrieved from RAM) --- but will settle from setOutputs_p8 on -signal operation_phase, operation_phase_next : unsigned(3 downto 0); - --- helper signals -signal tmp_input_vect : std_logic; -signal pattern_detected : std_logic; --- other signals -signal last_tck_cycle, last_tck_cycle_next : std_logic; -signal zerocounter, zerocounter_next : unsigned (max_bitcounter_ld-1 downto 0); -signal chain_broken, chain_broken_next : std_logic; -signal chain_length, chain_length_next : std_logic_vector (max_bitcounter_ld-1 downto 0); --- should a JTAG clock pulse be generated this global_jtag_counter cycle? -signal enable_jtag_clock, enable_jtag_clock_next : std_logic; --- JTAG output signal: TDI -signal tdi, tdi_next : std_logic; - --- JTAG output signal: TMS -signal tms, tms_next : std_logic; - --- INSERTLABEL: signals -begin --- helper signals ---tmp_input_vect <= (others => input_bit); -- doesn't work -pattern_detected <= nfa_state(pattern_length-1); -input_bit <= TDO_IN; -CHAIN_BROKEN_OUT <= chain_broken; -CHAIN_LENGTH_OUT <= chain_length; -IDLE_OUT <= '1' when state = idle else '0'; -ENABLE_JTAG_CLOCK_OUT <= enable_jtag_clock; -LAST_TCK_CYCLE_OUT <= last_tck_cycle; -TMS_OUT <= tms; -TDI_OUT <= tdi; - -SYNCHRONOUS_MAIN : process (CLK_IN) -begin - if (rising_edge(CLK_IN)) then - if(RESET_IN = '1') then - bitcounter <= (others =>'0'); - nfa_state <= (others => '0'); - last_tck_cycle <= '0'; - zerocounter <= (others => '0'); - state <= IDLE; - substate <= none_p1; - chain_broken <= '1'; - chain_length <= (others => '0'); - enable_jtag_clock <= '0'; - tdi <= '0'; - tms <= '0'; - operation <= "11"; - operation_phase <= "0000"; - -- INSERTLABEL: SYNCHRONOUS reset - else - bitcounter <= bitcounter_next; - nfa_state <= nfa_state_next; - last_tck_cycle <= last_tck_cycle_next; - zerocounter <= zerocounter_next; - state <= state_next; - substate <= substate_next; - chain_broken <= chain_broken_next; - chain_length <= chain_length_next; - enable_jtag_clock <= enable_jtag_clock_next; - tdi <= tdi_next; - tms <= tms_next; - operation <= operation_next; - operation_phase <= operation_phase_next; - -- INSERTLABEL: SYNCHRONOUS update - end if; - end if; -end process; - -COMB_MAIN: process(bitcounter, input_bit, nfa_state,last_tck_cycle,zerocounter,state, TRIGGER_BEGIN_TESTCHAIN_IN, BEGIN_JTAGBITCALC_IN, operation, operation_phase, substate, enable_jtag_clock, chain_broken, chain_length, tdi, tms, pattern_detected, DELAY_IN ) -- INSERTLABEL: sensitivity list -begin - bitcounter_next <= bitcounter; - last_tck_cycle_next <= last_tck_cycle; - zerocounter_next <= zerocounter; - state_next <= state; - substate_next <= substate; - operation_next <= operation; - operation_phase_next <= operation_phase; - enable_jtag_clock_next <= enable_jtag_clock; - nfa_state_next <= nfa_state; - chain_broken_next <= chain_broken; - chain_length_next <= chain_length; - tdi_next <= tdi; - tms_next <= tms; - - -- INSERTLABEL: COMB defaults - case state is - when IDLE => - if(TRIGGER_BEGIN_TESTCHAIN_IN = '1') then - state_next <= WAIT_BEGIN_JTAGBITCALC; - operation_next <= "11"; -- none - chain_length_next <= (others =>'0'); - chain_broken_next <= '1'; - end if; - when WAIT_BEGIN_JTAGBITCALC => - if(BEGIN_JTAGBITCALC_IN='1') then - state_next <= PROCESSING; - operation_phase_next <= operation_phase + 1; - substate_next <= none_p1; -- do nothing other than output tms=1 - if(operation = "11") then - -- last operation was none - operation_next <= "00"; -- JTAG_RESET - operation_phase_next <= "0000"; -- Bit Nr. 0 - enable_jtag_clock_next <= '1'; -- enable JTAG clock for WRITE operation - elsif(operation = "00") then - -- last operation was: JTAG_RESET - if(operation_phase = "0101") then - operation_next <= "01"; -- WRITE_IR - operation_phase_next <= "0000"; - bitcounter_next <= (others => '0'); - end if; - elsif(operation = "01") then - -- last operation was: WRITE_IR - if(operation_phase = "0101") then -- Shift-IR - -- stay in this phase until the instruction registers (of all chips) have been filled with ones - substate_next <= ir_ones_p1; -- fill ir with ones - if(to_integer(bitcounter) < ir_fill_ones_length - 1) then - operation_phase_next <= operation_phase; - bitcounter_next <= bitcounter + 1; - else - operation_phase_next <= operation_phase+1; -- shift last bit - end if; - elsif(operation_phase = "1000") then -- Run-Test-Idle - operation_next <= "10"; -- WRITE_DR - operation_phase_next <= "0000"; -- Select-DR-Scan - bitcounter_next <= (others => '0'); -- reset bitcounter - end if; - elsif(operation = "10") then - --last operation was: WRITE_DR - if(operation_phase = "0010") then -- Shift-DR - substate_next <= dr_zeros_p1; -- fill dr with zeros - elsif(operation_phase = "0011") then -- Shift-DR - -- stay in this phase until the bypass registers (of all chips) have filles with zeros - bitcounter_next <= bitcounter + 1; - operation_phase_next <= operation_phase; - substate_next <= dr_zeros_p1; -- fill dr with zeros - if(to_integer(bitcounter) +1 >= zerofill_length + to_integer(unsigned(DELAY_IN))) then - if(to_integer(zerocounter) > zerofill_numzeros_required) then - -- enough zeros appeared at tdo - operation_phase_next <= operation_phase + 1; - bitcounter_next <= (others =>'0'); - substate_next <= dr_pattern_p1; -- write pattern into dr - else - operation_phase_next <= operation_phase + 2; -- skip writing pattern, thus yielding CHAIN_BROKEN='1' and CHAIN_LENGTH=0 - bitcounter_next <= (others =>'0'); - end if; - end if; - elsif(operation_phase = "0100") then -- Shift-DR: shift pattern - bitcounter_next <= bitcounter + 1; - operation_phase_next <= operation_phase; - substate_next <= dr_pattern_p1; -- write pattern into dr/look for pattern - if(to_integer(bitcounter) +1 >= zerofill_length + pattern_length + to_integer(unsigned(DELAY_IN))) then - operation_phase_next <= operation_phase + 1; - end if; - elsif(operation_phase = "0110") then -- Update DR - last_tck_cycle_next <= '1'; - elsif(operation_phase = "0111") then -- Run-Test-Idle - enable_jtag_clock_next <= '0'; -- disable JTAG clock for WRITE operation - last_tck_cycle_next <= '0'; - state_next <= IDLE; - end if; - end if; - end if; - when PROCESSING => - -- set TMS, copied from jtag_write_m10, modified - tms_next <= '1'; -- JTAG_RESET if operation = "00" - if(operation = "01") then -- WRITE_IR - if(operation_phase = "0001") then - tms_next <= '1'; - elsif(operation_phase = "0010") then - tms_next <= '1'; - elsif(operation_phase = "0110") then - tms_next <= '1'; - elsif(operation_phase = "0111") then - tms_next <= '1'; - else - tms_next <= '0'; - end if; - elsif(operation = "10") then -- WRITE_DR - if(operation_phase = "0000") then - tms_next <= '1'; - elsif(operation_phase = "0101") then - tms_next <= '1'; - elsif(operation_phase = "0110") then - tms_next <= '1'; - else - tms_next <= '0'; - end if; - end if; - tdi_next <= '0'; - case substate is - when none_p1 => - state_next <= WAIT_BEGIN_JTAGBITCALC; - when ir_ones_p1 => - tdi_next <= '1'; - state_next <= WAIT_BEGIN_JTAGBITCALC; - when dr_zeros_p1 => - tdi_next <= '0'; - -- as the comparison of input_bit always happens in the first processing substate (*_p1), - -- the delay is fixed (always the same sampling time is used) - if(input_bit = '1') then - zerocounter_next <= (others =>'0'); - else - zerocounter_next <= zerocounter + 1; - end if; - state_next <= WAIT_BEGIN_JTAGBITCALC; - when dr_pattern_p1 => - -- as the comparison of input_bit always happens in the first processing substate (*_p1), - -- the delay is fixed (always the same sampling time is used) - -- this way: the first bit of the pattern always sets the first bit in nfa_state - -- nfa_state(i) means the (i+1)'th bit has arrived in a row. - -- if nfa_state(pattern_length-1) is set, this obviously means the full pattern has been detected. - nfa_state_next(pattern_length-1 downto 0) <= (nfa_state(pattern_length-2 downto 0) & '1') and std_logic_vector_scalar_compare(pattern, input_bit); - substate_next <= dr_pattern2_p2; - --nfa_state_next(pattern_length downto 1) <= nfa_state(pattern_length-1 downto 0) and (pattern = tmp_input_vect); - when dr_pattern2_p2 => - if(pattern_detected = '1') then - chain_broken_next <= '0'; - chain_length_next <= std_logic_vector(to_unsigned(to_integer(bitcounter)-to_integer(unsigned(DELAY_IN))-pattern_length, max_bitcounter_ld)); - end if; - if(to_integer(bitcounter) < pattern_length) then - tdi_next <= pattern(to_integer(bitcounter)); - else - tdi_next <= '0'; - end if; - state_next <= WAIT_BEGIN_JTAGBITCALC; - end case; - end case; -end process; - -end architecture; - diff --git a/vhdl/code/jtag_check_crc_ram1a.vhd b/vhdl/code/jtag_check_crc_ram1a.vhd deleted file mode 100755 index c62ccac..0000000 --- a/vhdl/code/jtag_check_crc_ram1a.vhd +++ /dev/null @@ -1,200 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; - -library work; -use work.jtag_constants.all; - -entity jtag_check_crc_ram1a is - generic ( - RAM_JTAG_REGISTERS_DEPTH : integer; - MAX_NUMCHIPS : integer; - MAX_NUMCHIPS_LD : integer; - MAX_NUMCHIPS_PLUS_ONE_LD : integer; - MAX_REGLEN_PLUS_ONE_LD : integer; - MAX_REGISTERS_LD : integer - ); - port ( - CLK_IN : std_logic; - RESET_IN : std_logic; - TRIGGER_CHECK_IN : std_logic; - -- RAM1a - RAM1A_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); - RAM1A_D_IN : in std_logic_vector(31 downto 0); - - NUMCHIPS_IN : in std_logic_vector(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0); - CRC_OK_OUT : out std_logic_vector(MAX_NUMCHIPS-1 downto 0); - IDLE_OUT : out std_logic - ); -end entity; - -architecture jtag_check_crc_ram1a_arch of jtag_check_crc_ram1a is -component CRC_32 is - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(31 downto 0); - CRC_OUT : out std_logic_vector(31 downto 0); - CRC_match : out std_logic - ); -end component; - -type state_type is (idle, prepare_read, readA0, readAi, wait_check, wait_check2, wait_check3); -signal state, state_next : state_type; -signal wordcounter, wordcounter_next : unsigned(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0); -signal numregs, numregs_next : unsigned(MAX_REGISTERS_LD-1 downto 0); -signal dr_pointer, dr_pointer_next : unsigned(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0); -signal length, length_next : unsigned(MAX_REGLEN_PLUS_ONE_LD-1 downto 0); -signal wordlength : unsigned(MAX_REGLEN_PLUS_ONE_LD-1-5 downto 0); - -signal ram1a_a, ram1a_a_next : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); -signal crc32_en, crc32_en_next : std_logic; -signal crc32_data, crc32_data_next : std_logic_vector(31 downto 0); -signal crc32_match : std_logic; -signal crc32_reset, crc32_reset_next : std_logic; --- is first CRC32 ok? reset on TRIGGER_CHECK_IN -signal crc1_ok, crc1_ok_next : std_logic; --- is second CRC32 ok? reset on TRIGGER_CHECK_IN -signal crc2_ok, crc2_ok_next : std_logic; --- are both CRCs ok? -signal crc_ok, crc_ok_next : std_logic_vector(MAX_NUMCHIPS-1 downto 0); --- check first/second CRC in next clock cycle -signal check_crc1, check_crc1_next, check_crc1_next_next : std_logic; -signal check_crc2, check_crc2_next, check_crc2_next_next : std_logic; -signal chipcounter, chipcounter_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0); - -begin - -the_crc32 : CRC_32 port map (CLK => CLK_IN, RESET => crc32_reset, CLK_EN => crc32_en, - DATA_IN => crc32_data, CRC_OUT => open, CRC_match =>crc32_match); - -CRC_OK_OUT <= crc_ok; -IDLE_OUT <= '1' when state = idle else '0'; -RAM1A_A_OUT <= ram1a_a; -wordlength <= length(MAX_REGLEN_PLUS_ONE_LD-1 downto 5) when length(4 downto 0) = "00000" else length(MAX_REGLEN_PLUS_ONE_LD-1 downto 5) + 1; - -SYNCHRONOUS: process(CLK_IN) -begin - if (rising_edge(CLK_IN)) then - if(RESET_IN = '1') then - state <= idle; - ram1a_a <= (others => '0'); - wordcounter <= (others => '0'); - crc32_data <= (others => '0'); - crc32_en <= '0'; - numregs <= (others => '0'); - dr_pointer <= (others => '0'); - length <= (others => '0'); - crc1_ok <= '0'; - crc2_ok <= '0'; - crc_ok <= (others => '0'); - check_crc1 <= '0'; - check_crc2 <= '0'; - check_crc1_next <= '0'; - check_crc2_next <= '0'; - chipcounter <= (others => '0'); - crc32_reset <= '0'; - else - state <= state_next; - ram1a_a <= ram1a_a_next; - wordcounter <= wordcounter_next; - crc32_data <= crc32_data_next; - crc32_en <= crc32_en_next; - numregs <= numregs_next; - dr_pointer <= dr_pointer_next; - length <= length_next; - crc1_ok <= crc1_ok_next; - crc2_ok <= crc2_ok_next; - crc_ok <= crc_ok_next; - check_crc1 <= check_crc1_next; - check_crc2 <= check_crc2_next; - check_crc1_next <= check_crc1_next_next; - check_crc2_next <= check_crc2_next_next; - chipcounter <= chipcounter_next; - crc32_reset <= crc32_reset_next; - end if; - end if; -end process; - -STATE_COMB: process (state, TRIGGER_CHECK_IN, RAM1A_D_IN, ram1a_a, wordcounter, crc32_data, crc32_match, numregs, dr_pointer, length, crc1_ok, crc2_ok, crc_ok, check_crc1, check_crc2, NUMCHIPS_IN, chipcounter, wordlength) -begin - ram1a_a_next <= ram1a_a; - state_next <= state; - wordcounter_next <= wordcounter; - crc32_data_next <= crc32_data; - crc32_en_next <= '0'; - crc32_reset_next <= '0'; - numregs_next <= numregs; - dr_pointer_next <= dr_pointer; - length_next <= length; - crc1_ok_next <= crc1_ok; - crc2_ok_next <= crc2_ok; - crc_ok_next <= crc_ok; - check_crc1_next_next <= '0'; - check_crc2_next_next <= '0'; - chipcounter_next <= chipcounter; - if(check_crc1 = '1') then - crc1_ok_next <= crc32_match; - end if; - if(check_crc2 = '1') then - crc2_ok_next <= crc32_match; - end if; - case state is - when idle => - if(TRIGGER_CHECK_IN = '1') then - state_next <= prepare_read; - chipcounter_next <= (others => '0'); -- reset chipcounter - end if; - when prepare_read => - state_next <= readA0; - ram1a_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(chipcounter); - ram1a_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= (others => '0'); - crc1_ok_next <= '0'; - crc2_ok_next <= '0'; - crc32_reset_next <= '1'; -- reset CRC component before processing a new chip (which has independently generated crcs) - when readA0 => - state_next <= readAi; - ram1a_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(to_unsigned(1,RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD)); -- word 1; - wordcounter_next <= to_unsigned(0,RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD); - numregs_next <= to_unsigned(1,MAX_REGISTERS_LD); -- 1 (because it should't be zero in the next step) - when readAi => - ram1a_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(wordcounter + 2); -- word i+2; - crc32_data_next <= RAM1A_D_IN; - crc32_en_next <= '1'; - wordcounter_next <= wordcounter + 1; - if(to_integer(wordcounter) = 0) then - numregs_next <= unsigned(RAM1A_D_IN(MAX_REGISTERS_LD-1 downto 0)); - end if; - if(to_integer(wordcounter) = to_integer(2*numregs)) then -- last DR Pointer - dr_pointer_next <= unsigned(RAM1A_D_IN(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0)); - elsif(to_integer(wordcounter) = to_integer(2*numregs+1)) then -- last DR length - length_next <= unsigned(RAM1A_D_IN(MAX_REGLEN_PLUS_ONE_LD-1 downto 0)); - elsif(to_integer(wordcounter) = to_integer(2*numregs+2)) then -- first CRC-32 - check_crc1_next_next <= '1'; - elsif(to_integer(wordcounter) > to_integer(2*numregs+2)) then - -- here the condition dr_pointer+length <= 2*numregs+2 has to be caught - if(to_integer(dr_pointer+length) <= to_integer(2*numregs+2)) then - -- abort because CRC, after end of last DR, lies at an invalid location < = 2*numregs+2 - state_next <= idle; - elsif(to_integer(wordcounter) = to_integer(dr_pointer+wordlength)) then -- second CRC-32 - check_crc2_next_next <= '1'; - state_next <= wait_check; - end if; - end if; - when wait_check => - state_next <= wait_check2; - when wait_check2 => - state_next <= wait_check3; - when wait_check3 => - crc_ok_next(to_integer(chipcounter)) <= crc1_ok and crc2_ok; - if(chipcounter >= unsigned(NUMCHIPS_IN) - 1) then - state_next <= idle; - else - chipcounter_next <= chipcounter + 1; - state_next <= prepare_read; - end if; - end case; -end process; - -end architecture; diff --git a/vhdl/code/jtag_cmd_m26c.vhd b/vhdl/code/jtag_cmd_m26c.vhd deleted file mode 100644 index 479beb8..0000000 --- a/vhdl/code/jtag_cmd_m26c.vhd +++ /dev/null @@ -1,2262 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; ---USE IEEE.std_logic_ARITH.ALL; ---USE IEEE.std_logic_UNSIGNED.ALL; -USE IEEE.numeric_std.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; --- use work.trb_net16_hub_func.all; -use work.version.all; -use work.jtag_constants.all; -use work.jtag_misc.all; ---use work.minmax.all; ---use work.monitor_config.all; ---use debug.fifo32bit; -use work.mathhelpers.all; - - - -entity jtag_cmd_m26c is - generic( - MAX_NUMCHIPS : integer := 7; -- maximum number of chips in this chain controllers chain (because number of chips can be 0, best chose 2^n-1 as maximum to save logic. if memory should be used completely, choose 2^n.) - MAX_REGISTERS : integer := 14; -- maximum number of registers per chip. Because of ram3 layout, values of 2^n-2 should be chosen. - MAX_REGLEN : integer := 4095; -- maximum number of bits for one register. Should be chosen as 2^n-1 - WRITE_ERROR_THRESHOLD : integer := 3; -- if at least WRITE_ERROR_THRESHOLD bits are different from written value, count as WRITE_ERROR/DATA_CHANGED. - - READ_ERROR_THRESHOLD : integer := 4; -- if at least READ_ERROR_THRESHOLD bits are different from 32 bit ID, set - - JTAG_M26_IRLEN : integer := 5; -- length of the instruction register of the connected chips - JTAG_M26_IR_ID_CODE : std_logic_vector(4 downto 0) := "01110"; -- Code selecting DEV_ID register of Mimosa26 - JTAG_M26_DEV_ID : std_logic_vector(31 downto 0) := x"4D323601"; -- Mimosa26 DEV_ID, which the sensor should send. - - RAM_JTAG_REGISTERS_DEPTH : integer := 11; -- will be split up into MAX_NUMCHIPS_LD bits for chip address, rest is for addressing words in that chip block. word size is 32 bit. --- GLOBAL_JTAG_COUNTER_BITS : integer := 10; -- - JTAG_CHAIN_BROKEN_COUNTER_BITS : integer := 10; -- counter width - JTAG_TDO_EXPECTED_MAXDELAY : integer := 3; -- set range to 0..value for delay of expected TDO value - RESET_WAIT_DURATION : unsigned := "10000000" -- 128 clock cycles at 100 mhz -); - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - JTAG_TMS_OUT : out std_logic; - JTAG_TCK_OUT : out std_logic; - JTAG_TDI_OUT : out std_logic; - JTAG_TDO_IN : in std_logic; - - BUS_DATA_IN : in std_logic_vector(31 downto 0); - BUS_DATA_OUT : out std_logic_vector(31 downto 0); - BUS_ADDR_IN : in std_logic_vector(9 downto 0); - BUS_READ_IN : in std_logic; - BUS_WRITE_IN : in std_logic; - - BUS_DATAREADY_OUT : out std_logic; - BUS_NO_MORE_DATA_OUT : out std_logic; - BUS_WRITE_ACK_OUT : out std_logic; - BUS_UNKNOWN_ADDR_OUT : out std_logic; - - --OFF_SPILL_IN : in std_logic; - RUN_REQUEST_IN : in std_logic; - WRITE_ONCE_REQUEST_IN : in std_logic; - MY_STATUS_OUT : out std_logic_vector(8 downto 0); - --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0); - --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0); - REQUEST_RESET_OUT : out std_logic; - IDLE_OUT : out std_logic; - PROG_JTAG_FINISHED_OUT:out std_logic; - READ_ID_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0); - WRITE_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0); - DATA_CHANGED_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0); - SAMPLING_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0); - RUN_COUNTER_OUT : out std_logic_vector(31 downto 0); - - STARTED_OUT : out std_logic; - LAST_RUN_SUCCESSFUL_OUT : out std_logic; - LAST_DATA_CHANGED_OUT : out std_logic; - LAST_WRITE_ERRORS_OUT : out std_logic; - LAST_READ_ERRORS_OUT : out std_logic; - CRC_ERROR_OUT : out std_logic - - --BUS_TIMEOUT_IN : in std_logic; - ); -end entity; - - -architecture arch_cmd_m26c of jtag_cmd_m26c is - -constant MAX_NUMCHIPS_PLUS_ONE_LD : integer := log2_ceil(MAX_NUMCHIPS+1); - -- LD of value plus one, rounded up, or ld rounded down + 1, because the next binary digit needs one bit more (i.e, 2 needs second bit) -constant MAX_NUMCHIPS_LD : integer := log2_ceil(MAX_NUMCHIPS); -- LD of value, rounded up -constant MAX_REGISTERS_LD : integer := log2_ceil(MAX_REGISTERS); -- LD of value, rounded up. -constant MAX_REGISTERS_PLUS_ONE_LD : integer := log2_ceil(MAX_REGISTERS+1); -- LD of (value plus one) -constant MAX_REGISTERS_PLUS_TWO_LD : integer := log2_ceil(MAX_REGISTERS+2); -- LD of (value plus two) -constant MAX_REGLEN_LD : integer := log2_ceil(MAX_REGLEN); -- LD of naximum register length. -constant MAX_REGLEN_PLUS_ONE_LD : integer := log2_ceil(MAX_REGLEN+1); -- LD of (register length+1) -constant JTAG_M26_IRLEN_LD : integer := log2_ceil(JTAG_M26_IRLEN); -- ld of value, rounded up -constant JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD : integer := log2_ceil(JTAG_TDO_EXPECTED_MAXDELAY+1); -- ceil of ld( value plus one) - --- constant STATUS_JTAG_ERROR : integer := 0; -- length MAX_NUMCHIPS --- constant STATUS_WRITE_ERROR : integer := MAX_NUMCHIPS; --- constant STATUS_WRITE_ERROR2 : integer := 2*MAX_NUMCHIPS; --- constant STATUS_READ_ERROR : integer := 3*MAX_NUMCHIPS; --- constant STATUS_READ_ERROR2 : integer := 4*MAX_NUMCHIPS; --- constant STATUS_DATA_CHANGED : integer := 5*MAX_NUMCHIPS; - --- constant WRITE_STATUS_JTAG_ERROR : integer := 0; -- length MAX_NUMCHIPS --- constant WRITE_STATUS_DATA_CHANGED : integer := MAX_NUMCHIPS; -- length MAX_NUMCHIPS --- constant WRITE_STATUS_DATA_CHANGED_OVER_THRESHOLD : integer := 2*MAX_NUMCHIPS; -- length MAX_NUMCHIPS --- constant READ_STATUS_JTAG_ERROR : integer := 0; -- length MAX_NUMCHIPS --- constant READ_STATUS_BIT_ERROR : integer := MAX_NUMCHIPS; -- length MAX_NUMCHIPS --- constant READ_STATUS_BIT_ERROR_OVER_THRESHOLD : integer := 2*MAX_NUMCHIPS; -- length MAX_NUMCHIPS - -constant RAM_MATCH_DIFF_COUNT_DEPTH : integer := MAX_NUMCHIPS_LD + MAX_REGISTERS_PLUS_ONE_LD + 1;--9; - -- maximum 32 counts / chip (one for read DEV_ID register, rest for read/write data registers), maximum 16 chips, each count 32 bits -constant RAM_ERROR_COUNTS_DEPTH : integer := MAX_REGISTERS_PLUS_TWO_LD+2+MAX_NUMCHIPS_LD; - --10; -- ld(8+4*MAX_REGISTERS)+MAX_NUMCHIPS_LD= MAX_REGISTERS_PLUS_TWO_LD+2+MAX_NUMCHIPS_LD - - - - -signal jtag_refresh_active : std_logic; -signal jtag_check1_active : std_logic; -signal jtag_refresh_active_last : std_logic; - --- has to fit number of 32 bit words needed to represent the status register ---signal status_register_pos, status_register_pos_next : std_logic_vector(MAX_NUMCHIPS_LD+2+MAX_REGISTERS_LD-5 downto 0); ---signal status_register_read_running, status_register_read_running_next : std_logic; - --- mostly for debug purposes: status bits ---signal my_status, my_status_next : std_logic_vector(8 downto 0); - --- status register layout: --- bits MAX_NUMCHIPS -1 downto 0 : JTAG ERROR --- bits 2*MAX_NUMCHIPS -1 downto MAX_NUMCHIPS : WRITE ERROR --- bits 3*MAX_NUMCHIPS -1 downto 2*MAX_NUMCHIPS : WRITE ERROR2 --- bits 4*MAX_NUMCHIPS -1 downto 3*MAX_NUMCHIPS : READ ERROR --- bits 5*MAX_NUMCHIPS -1 downto 4*MAX_NUMCHIPS : READ ERROR2 --- bits 6*MAX_NUMCHIPS -1 downto 5*MAX_NUMCHIPS : DATA CHANGED - ---signal status_register, status_register_next : std_logic_vector(6*MAX_NUMCHIPS-1 downto 0); -signal crc_status_register, crc_status_register_next : std_logic_vector(MAX_NUMCHIPS-1 downto 0); - - --- contains a "1" at the positions of deactivated sensors -signal removed_chips : std_logic_vector(MAX_NUMCHIPS -1 downto 0); -signal last_not_removed, last_not_removed_next : unsigned(MAX_NUMCHIPS_LD - 1 downto 0); -signal first_not_removed, first_not_removed_next : unsigned(MAX_NUMCHIPS_LD - 1 downto 0); - -signal cc_chip_i, cc_chip_i_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0); -signal cc_nextnotremoved_i, cc_nextnotremoved_i_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0); -signal chip_counter_start, chip_counter_start_next : std_logic; -type CC_STATE_TYPE is (CC_IDLE, CC_COUNT_SENSOR, CC_SETNUMCHIPS); -signal cc_state, cc_state_next : CC_STATE_TYPE; - -signal ram1a_a2 : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); -signal ram1a_dout2 : std_logic_vector(31 downto 0); - -signal ram1a_a1_base_addr : std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0); -signal ram1a_a1_rel_addr : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0); -signal ram1a_a1 : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); -signal ram1a_din1 : std_logic_vector(31 downto 0); -signal ram1a_wr1 : std_logic; -signal ram1a_dout1 : std_logic_vector(31 downto 0); - -signal ram1b_a2, ram1b_a2_next : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); -signal ram1b_dout2 : std_logic_vector(31 downto 0); - -signal ram1a_select, ram1a_select_next : std_logic_vector(1 downto 0); - -signal ram1b_a1 : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); -signal ram1b_din1 : std_logic_vector(31 downto 0); -signal ram1b_wr1 : std_logic; -signal ram1b_dout1 : std_logic_vector(31 downto 0); -signal ram1b_select, ram1b_select_next : std_logic; - -signal init_ram1b_ram1a_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); -signal init_ram1b_ram1a_d : std_logic_vector(31 downto 0); -signal init_ram1b_ram1b_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); -signal init_ram1b_ram1b_dout : std_logic_vector(31 downto 0); -signal init_ram1b_ram1b_din : std_logic_vector(31 downto 0); -signal init_ram1b_ram1b_wr : std_logic; - -signal jtag_data_to_ram_ram1b_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); -signal jtag_data_to_ram_ram1b_dout : std_logic_vector(31 downto 0); -signal jtag_data_to_ram_ram1b_din : std_logic_vector(31 downto 0); -signal jtag_data_to_ram_ram1b_wr : std_logic; - -signal jtag_check_crc_ram1a_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); -signal jtag_check_crc_ram1a_d : std_logic_vector(31 downto 0); - - --- ram2 port 2: local flipflops ---signal ram2_a2, ram2_a2_next : std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0); ---signal ram2_dout2 : std_logic_vector(31 downto 0); --- ram2 port 1: non local flipflops, all connected to components -signal ram2_a1 : std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0); -signal ram2_din1 : std_logic_vector(31 downto 0); -signal ram2_wr1 : std_logic; -signal ram2_dout1 : std_logic_vector(31 downto 0); -signal ram2_select, ram2_select_next : std_logic; - --- ram3a port 2: local flipflops -signal ram3a_a2 : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0); -signal ram3a_dout2 : std_logic_vector(31 downto 0); - --- ram3a port 1: non local flipflops, all connected to components -signal ram3a_a1 : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0); -signal ram3a_din1 : std_logic_vector(31 downto 0); -signal ram3a_wr1 : std_logic; -signal ram3a_dout1 : std_logic_vector(31 downto 0); - --- ram3b port 1: non local flipflops, all connected to components - -- see jtag_copy_ram3* signals --- ram3b port 2: local flipflops -signal ram3b_a2_base_addr : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-4-1 downto 0); -signal ram3b_a2_rel_addr : std_logic_vector(3 downto 0); -signal ram3b_a2 : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0); -signal ram3b_dout2 : std_logic_vector(31 downto 0); - -signal ram3a_select, ram3a_select_next : std_logic; -signal ram3a_rd_select, ram3a_rd_select_next : std_logic; - -signal jtag_tdo_compare_count_ram_a : std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0); -signal jtag_tdo_compare_count_ram_dout : std_logic_vector(31 downto 0); -signal jtag_tdo_compare_count_ram_din : std_logic_vector(31 downto 0); -signal jtag_tdo_compare_count_ram_wr : std_logic; - -signal idle_out_signal, idle_out_signal_next : std_logic; - -signal numchips_configured : unsigned(MAX_NUMCHIPS_LD-1 downto 0); -signal numchips_active, numchips_active_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0); -signal numchips_active_acc, numchips_active_acc_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0); - -signal debug_m26cs_state : std_logic_vector(7 downto 0); -signal debug_test : std_logic_vector(31 downto 0); - -signal debug_trigger_counter, debug_trigger_counter_next : unsigned(31 downto 0); - -signal bus2_ram_addr_out : std_logic_vector(15 downto 0); -signal bus2_ram_data_out : std_logic_vector(31 downto 0); -signal bus2_ram_read_enable_out : std_logic; -signal bus2_ram_write_enable_out : std_logic; -signal bus2_ram_data_in : std_logic_vector(31 downto 0); -signal bus2_ram_ack_in : std_logic; -signal bus2_ram_nack_in : std_logic; -signal ram1a_read_delay, ram1a_read_delay2 : std_logic; - -signal status2_run_counter, status2_run_counter_next : unsigned(31 downto 0); - -signal status2_chain_status, status2_chain_status_next : std_logic_vector(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0); -signal status2_copy_finished: std_logic; - - --- monitoring ---signal read_mon_write_out : std_logic; --- off_spill timer (htcounter) ---signal htcounter_next, htcounter : unsigned(26 downto 0); -- 27 bit = approx 1.34 seconds ---signal have_time_for_write, have_time_for_write_next : std_logic; -signal prog_jtag_finished, prog_jtag_finished_next : std_logic; ---signal last_write_successful, last_write_successful_next : std_logic; - --- BEGIN NEW SIGNALS -signal jtag_next_not_removed, jtag_next_not_removed_next : std_logic_vector(MAX_NUMCHIPS_PLUS_ONE_LD*(MAX_NUMCHIPS+1)-1 downto 0); -signal jtag_write_ram1a_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); -signal jtag_write_ram1a_d : std_logic_vector(31 downto 0); -signal trigger_jtag_write, trigger_jtag_write_next : std_logic; -signal jtag_write_is_dr_bit : std_logic; -signal jtag_write_is_firstbit : std_logic; -signal jtag_write_is_lastbit : std_logic; -signal jtag_write_chipnum : std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0); -signal jtag_write_regnum : std_logic_vector(MAX_REGISTERS_LD-1 downto 0); -signal jtag_write_enable_jtag_clock : std_logic; -signal jtag_write_last_tck_cycle : std_logic; -signal jtag_write_tms : std_logic; -signal jtag_write_tdi : std_logic; -signal jtag_write_expected_tdo : std_logic; -signal jtag_write_idle : std_logic; -signal jtag_write_last_error_code: std_logic_vector(2 downto 0); -signal jtag_write_numregs_configured : std_logic_vector(MAX_NUMCHIPS*(MAX_REGISTERS_PLUS_ONE_LD)-1 downto 0); - -signal jtag_read_ram1a_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); -signal jtag_read_ram1a_d : std_logic_vector(31 downto 0); -signal trigger_jtag_read, trigger_jtag_read_next : std_logic; -signal jtag_read_is_dr_bit : std_logic; -signal jtag_read_is_firstbit : std_logic; -signal jtag_read_is_lastbit : std_logic; -signal jtag_read_chipnum : std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0); -signal jtag_read_enable_jtag_clock : std_logic; -signal jtag_read_last_tck_cycle : std_logic; -signal jtag_read_tms : std_logic; -signal jtag_read_tdi : std_logic; -signal jtag_read_expected_tdo : std_logic; -signal jtag_read_idle : std_logic; - ---signal trigger_bypassreg, trigger_bypassreg_next : std_logic; -signal jtag_bypassreg_idle : std_logic; -signal jtag_bypassreg_length : std_logic_vector(MAX_NUMCHIPS_LD+JTAG_M26_IRLEN_LD + 7-1 downto 0); -signal jtag_bypassreg_chain_broken : std_logic; -signal jtag_bypassreg_enable_jtag_clock : std_logic; -signal jtag_bypassreg_last_tck_cycle : std_logic; -signal jtag_bypassreg_tms : std_logic; -signal jtag_bypassreg_tdi : std_logic; --- begin: global_jtag_counter settings -signal jtag_clock_cycle_length : unsigned(9 downto 0); -- 10 bit linear adjustment of tck cycle length (10ns-10us) -signal jtag_clock_time1 : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution -signal jtag_clock_time2 : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution -signal jtag_sample_time1 : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution -signal jtag_sample_time2 : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution -signal jtag_sample_time3 : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution -signal jtag_set_data_time: unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution --- begin: periodic pulses, periodic with global_jtag_counter -signal begin_jtag_bitcalc : std_logic; -signal jtag_sample_pulse1 : std_logic; -signal jtag_sample_pulse2 : std_logic; -signal jtag_sample_pulse3 : std_logic; -signal jtag_sample_pulse3_d1, jtag_sample_pulse3_d1_next : std_logic; -signal jtag_set_data_pulse : std_logic; --- end: periodic pulses - -signal jtag_tdo_sampled : std_logic; -signal jtag_tdo_sampling_error : std_logic; - -signal jtag_tms : std_logic; -signal jtag_tdi : std_logic; -signal jtag_enable_clock : std_logic; - -signal jtag_meta_is_dr_bit : std_logic; -signal jtag_meta_is_firstbit : std_logic; -signal jtag_meta_is_lastbit : std_logic; -signal jtag_meta_chipnum : std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0); -signal jtag_meta_regnum : std_logic_vector(MAX_REGISTERS_LD-1 downto 0); -signal jtag_meta_last_tck_cycle : std_logic; -signal jtag_meta_expected_tdo : std_logic; - -signal jtag_delayed_is_dr_bit : std_logic; -signal jtag_delayed_is_firstbit : std_logic; -signal jtag_delayed_is_lastbit : std_logic; -signal jtag_delayed_chipnum : std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0); -signal jtag_delayed_regnum : std_logic_vector(MAX_REGISTERS_LD-1 downto 0); -signal jtag_delayed_tdo_expected : std_logic; - --- jtag_update_error_counts -signal trigger_juec_update_d_ch, trigger_juec_update_d_ch_next : std_logic; -signal trigger_juec_update_rd_err, trigger_juec_update_rd_err_next : std_logic; -signal trigger_juec_update_wr_err, trigger_juec_update_wr_err_next : std_logic; -signal trigger_juec_update_run_counter, trigger_juec_update_run_counter_next : std_logic; -signal juec_ram2_a : std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0); -signal juec_ram2_dout : std_logic_vector(31 downto 0); -signal juec_ram3a_a : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0); -signal juec_ram3a_dout : std_logic_vector(31 downto 0); -signal juec_ram3a_din : std_logic_vector(31 downto 0); -signal juec_ram3a_wr : std_logic; -signal juec_idle : std_logic; -signal juec_data_changed : std_logic; -signal juec_read_errors : std_logic; -signal juec_write_errors : std_logic; - -signal jtag_copy_ram3_ram3a_a : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0); -signal jtag_copy_ram3_ram3a_dout : std_logic_vector(31 downto 0); -signal jtag_copy_ram3_ram3b_a : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0); -signal jtag_copy_ram3_ram3b_din : std_logic_vector(31 downto 0); -signal jtag_copy_ram3_ram3b_wr : std_logic; -signal jtag_copy_ram3_idle : std_logic; - - -signal trigger_blank_ram3a, trigger_blank_ram3a_next : std_logic; -signal jtag_blank_ram3a_ram3a_a : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0); -signal jtag_blank_ram3a_ram3a_din : std_logic_vector(31 downto 0); -signal jtag_blank_ram3a_ram3a_wr : std_logic; -signal jtag_blank_ram3a_idle : std_logic; - - -type M26CS_STATE_TYPE is (M26CSS_STOPPED, M26CSS_CHECK1_WAIT_FOR_HAVE_TIME, M26CSS_WAIT_FOR_TRIGGER, - M26CSS_CHECK_CRC_RAM1A_BEGIN, M26CSS_CHECK_CRC_RAM1A_WAIT, M26CSS_INIT_RAM1B_BEGIN, - M26CSS_INIT_RAM1B_WAIT, M26CSS_DATA_CHANGED_BEGIN, M26CSS_DATA_CHANGED_WAIT, - M26CSS_BLANK_RAM3A_WAIT, M26CSS_JUEC_DATA_CHANGED_BEGIN, M26CSS_JUEC_DATA_CHANGED_WAIT, - M26CSS_COUNT_CHIPS_BEGIN, M26CSS_COUNT_CHIPS_WAIT, M26CSS_BYPASSREG_BEGIN, - M26CSS_BYPASSREG_WAIT, M26CSS_READ1_BEGIN, M26CSS_READ1_WAIT, M26CSS_JUEC_READ_BEGIN, - M26CSS_JUEC_READ_WAIT, M26CSS_REQUEST_RESET_BEGIN, M26CSS_REQUEST_RESET_WAIT, - M26CSS_REQUESTED_RESET_WAIT, M26CSS_WRITE1_BEGIN, M26CSS_WRITE1_WAIT, - M26CSS_WRITE2_BEGIN, M26CSS_WRITE2_WAIT, M26CSS_JUEC_WRITE_BEGIN, - M26CSS_JUEC_WRITE_WAIT, M26CSS_JUEC_RUN_COUNTER_BEGIN, M26CSS_JUEC_RUN_COUNTER_WAIT, - M26CSS_WRITEONCE_CHECK_CRC_RAM1A_BEGIN, M26CSS_WRITEONCE_CHECK_CRC_RAM1A_WAIT, - M26CSS_WRITEONCE_INIT_RAM1B_BEGIN, M26CSS_WRITEONCE_INIT_RAM1B_WAIT, - M26CSS_WRITEONCE_COUNT_CHIPS_BEGIN, M26CSS_WRITEONCE_COUNT_CHIPS_WAIT, - M26CSS_WRITEONCE_WRITE1_BEGIN, M26CSS_WRITEONCE_WRITE1_WAIT ); -signal m26cs_state, m26cs_state_next : M26CS_STATE_TYPE; ---signal write_count, write_count_next : std_logic_vector(31 downto 0); -signal m26cs_stopped : std_logic; -signal m26cs_firstrun, m26cs_firstrun_next : std_logic; -signal breakpoint_active : std_logic_vector(9 downto 0); --- chain_status: --- bit 0: chain broken --- bit 1: CRC_error(s) --- bit 2: programmed --- bits 3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 3: chain length -signal chain_status, chain_status_next : std_logic_vector(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0); - -signal trigger_begin_bypassreg, trigger_begin_bypassreg_next : std_logic; -signal trigger_copy_ram3, trigger_copy_ram3_next : std_logic; ---signal jtag_tdo_compare_count_internal_error : std_logic; -signal run_counter, run_counter_next : unsigned(31 downto 0); -signal jtag_status2_copy_requested, jtag_status2_copy_requested_next : std_logic; - -signal jtag_status2_copy_request_strobe : std_logic; -type CPS2_STATE_TYPE is (CPS2_IDLE, CPS2_COPY_BEGIN, CPS2_COPY_WAIT); -signal cps2_state, cps2_state_next : CPS2_STATE_TYPE; -signal jtag_clock_pulse1 : std_logic; -signal jtag_clock_pulse2 : std_logic; -signal jtag_tck : std_logic; - -signal jtag_pulses_reset : std_logic; -signal jtag_pulses_reset_complete : std_logic; - -signal jtag_chain_broken_counter, jtag_chain_broken_counter_next : unsigned(JTAG_CHAIN_BROKEN_COUNTER_BITS-1 downto 0); - -signal jtag_check_crc_ram1a_crc_ok : std_logic_vector(MAX_NUMCHIPS-1 downto 0); -signal jtag_check_crc_ram1a_idle : std_logic; -signal trigger_check_crc_ram1a, trigger_check_crc_ram1a_next : std_logic; -signal trigger_init_ram1b, trigger_init_ram1b_next : std_logic; -signal jtag_init_ram1b_idle : std_logic; - -signal ram1b1c_copy_trigger_strobe : std_logic_vector(3 downto 0); -signal trigger_copy_ram1b1c : std_logic; -signal copy_ram1b1c_ram1b_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); -signal copy_ram1b1c_ram1b_dout : std_logic_vector(31 downto 0); -signal copy_ram1b1c_ram1c_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); -signal copy_ram1b1c_ram1c_din : std_logic_vector(31 downto 0); -signal copy_ram1b1c_ram1c_wr : std_logic; -signal copy_ram1b1c_idle : std_logic; - -signal ram1c_a2 : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); -signal ram1c_dout2 : std_logic_vector(31 downto 0); - -signal ram1b1c_copy_trigger_active : std_logic_vector(3 downto 0); -signal ram1b_copy_requested : std_logic; -signal ram1c_run_counter : unsigned(31 downto 0); -signal ram1c_chain_status : std_logic_vector(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0); - -type CPR1BC_STATE_TYPE is (CPR1BC_IDLE, CPR1BC_COPY_BEGIN, CPR1BC_COPY_WAIT); -signal cpr1bc_state, cpr1bc_state_next : CPR1BC_STATE_TYPE; - --- DEBUGTDO fifo and control signals --- signal tdodebugsamples : std_logic_vector(31 downto 0); --- signal debugtdo_rd_en : std_logic; --- signal debugtdo_wr_en : std_logic; --- signal debugtdo_dout : std_logic_vector(31 downto 0); --- signal debugtdo_empty : std_logic; --- signal debugtdo_full : std_logic; --- signal debugtdo_overflow : std_logic; --- signal debugtdo_underflow : std_logic; --- signal resetdebugtdo_toffifo : std_logic; --- signal resetdebugtdo_strobe : std_logic; --- signal debugtdo_activate_strobe : std_logic; --- signal debugtdo_active : std_logic; --- signal debugtdo_timeout : std_logic_vector(31 downto 0); --- signal debugtdo_counter : std_logic_vector(31 downto 0); --- signal debugtdo_ran : std_logic; - -signal crc_error_on_last_check, crc_error_on_last_check_next : std_logic; -signal last_run_successful, last_run_successful_next : std_logic; -signal last_run_successful_tmp, last_run_successful_tmp_next : std_logic; -signal begin_count_read_errors :std_logic; -signal begin_count_write_errors :std_logic; -signal begin_count_data_changed :std_logic; -signal end_count_read_errors :std_logic; -signal end_count_write_errors :std_logic; -signal end_count_data_changed :std_logic; -signal begin_count_read_errors_next :std_logic; -signal begin_count_write_errors_next :std_logic; -signal begin_count_data_changed_next :std_logic; -signal end_count_read_errors_next :std_logic; -signal end_count_write_errors_next :std_logic; -signal end_count_data_changed_next :std_logic; -signal last_read_error : std_logic; -signal last_write_error : std_logic; -signal last_data_changed : std_logic; - -signal sREAD_ID_ERRORS_COUNT_OUT : std_logic_vector(COUNTER_WIDTHS-1 downto 0); -signal sWRITE_ERRORS_COUNT_OUT : std_logic_vector(COUNTER_WIDTHS-1 downto 0); -signal sDATA_CHANGED_COUNT_OUT : std_logic_vector(COUNTER_WIDTHS-1 downto 0); - --- INSERTLABEL: signals - -signal m26csoptions : std_logic_vector(0 downto 0); -signal jtag_delay_expvalues : std_logic_vector(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0); - -signal request_reset, request_reset_next : std_logic; -signal reset_wait, reset_wait_next : unsigned(7 downto 0); -constant reset_wait_zero : unsigned(7 downto 0) := "00000000"; - -signal run_requested, run_requested_next : std_logic; -signal write_once_requested, write_once_requested_next : std_logic; -signal write_once_count, write_once_count_next : unsigned(COUNTER_WIDTHS-1 downto 0); - -signal bus_command_ack : std_logic; -signal bus_command_addr : std_logic_vector(15 downto 0); -signal bus_command_data_in : std_logic_vector(31 downto 0); -signal bus_command_data_out: std_logic_vector(31 downto 0); -signal bus_command_nack : std_logic; -signal bus_command_write : std_logic; -signal bus_command_read : std_logic; -signal bus_command_retry : std_logic; - -signal bus_ram3b_ack : std_logic; -signal bus_ram3b_ack_next : std_logic; -signal bus_ram3b_ack_next2 : std_logic; -signal bus_ram3b_addr : std_logic_vector(15 downto 0); -signal bus_ram3b_data_in : std_logic_vector(31 downto 0); -signal bus_ram3b_nack : std_logic; -signal bus_ram3b_read : std_logic; -signal bus_ram3b_unkwn : std_logic; -signal bus_ram3b_write : std_logic; - -signal bus_ram1c_ack : std_logic; -signal bus_ram1c_ack_next : std_logic; -signal bus_ram1c_ack_next2 : std_logic; -signal bus_ram1c_addr : std_logic_vector(15 downto 0); -signal bus_ram1c_data_in : std_logic_vector(31 downto 0); -signal bus_ram1c_nack : std_logic; -signal bus_ram1c_read : std_logic; -signal bus_ram1c_unkwn : std_logic; -signal bus_ram1c_write : std_logic; - - -begin - -jtag_bypassreg_enable_jtag_clock <= '0'; - - --- resetdebugtdo_toffifo <= resetdebugtdo_strobe OR RESET_IN; --- debugtdo_wr_en <= '1' when debugtdo_active = '1' and debugtdo_timeout <= debugtdo_counter else '0'; - --- tdodebugsamples(31) <= begin_jtag_bitcalc; --- tdodebugsamples(30) <= jtag_clock_pulse1; --- tdodebugsamples(29) <= jtag_clock_pulse2; --- tdodebugsamples(28) <= jtag_sample_pulse1; --- tdodebugsamples(27) <= jtag_sample_pulse2; --- tdodebugsamples(26) <= jtag_sample_pulse3; --- tdodebugsamples(25) <= jtag_set_data_pulse; --- tdodebugsamples(1) <= JTAG_TDO_IN; - -RUN_COUNTER_OUT <= std_logic_vector(run_counter); -STARTED_OUT <= jtag_refresh_active; -CRC_ERROR_OUT <= crc_error_on_last_check; -LAST_RUN_SUCCESSFUL_OUT <= last_run_successful; -LAST_DATA_CHANGED_OUT <= last_data_changed; -LAST_WRITE_ERRORS_OUT <= last_write_error; -LAST_READ_ERRORS_OUT <= last_read_error; - -REQUEST_RESET_OUT <= request_reset; - -the_bus_handler : trb_net16_regio_bus_handler - generic map( - PORT_NUMBER => 4, - PORT_ADDRESSES => (0 => x"0000", 1 => x"0100", 2 => x"0200", 3 => x"0300", others => (others => '0')), - PORT_ADDR_MASK => (0 => 8, 1 => 8, 2 => 8, 3 => 8, others => 0) - ) - port map( - CLK => CLK_IN, - RESET => RESET_IN, - DAT_ADDR_IN(15 downto 10) => "000000", - DAT_ADDR_IN(9 downto 0)=> BUS_ADDR_IN, -- address bus - DAT_DATA_IN => BUS_DATA_IN, -- data from TRB endpoint - DAT_DATA_OUT => BUS_DATA_OUT, -- data to TRB endpoint - DAT_READ_ENABLE_IN => BUS_READ_IN, -- read pulse - DAT_WRITE_ENABLE_IN => BUS_WRITE_IN, -- write pulse - DAT_TIMEOUT_IN => '0', -- access timed out - DAT_DATAREADY_OUT => BUS_DATAREADY_OUT, -- your data, master, as requested - DAT_WRITE_ACK_OUT => BUS_WRITE_ACK_OUT, -- data accepted - DAT_NO_MORE_DATA_OUT => BUS_NO_MORE_DATA_OUT, -- don't disturb me now - DAT_UNKNOWN_ADDR_OUT => BUS_UNKNOWN_ADDR_OUT, -- noone here to answer your request - - BUS_ADDR_OUT(0*16+15 downto 0*16) => bus2_ram_addr_out, - BUS_ADDR_OUT(1*16+15 downto 1*16) => bus_ram1c_addr, - BUS_ADDR_OUT(2*16+15 downto 2*16) => bus_command_addr, - BUS_ADDR_OUT(3*16+15 downto 3*16) => bus_ram3b_addr, - BUS_DATA_OUT(0*32+31 downto 0*32) => bus2_ram_data_out, - BUS_DATA_OUT(1*32+31 downto 1*32) => open, - BUS_DATA_OUT(2*32+31 downto 2*32) => bus_command_data_out, - BUS_DATA_OUT(3*32+31 downto 3*32) => open, - BUS_READ_ENABLE_OUT(0) => bus2_ram_read_enable_out, - BUS_READ_ENABLE_OUT(1) => bus_ram1c_read, - BUS_READ_ENABLE_OUT(2) => bus_command_read, - BUS_READ_ENABLE_OUT(3) => bus_ram3b_read, - BUS_WRITE_ENABLE_OUT(0) => bus2_ram_write_enable_out, - BUS_WRITE_ENABLE_OUT(1) => bus_ram1c_write, - BUS_WRITE_ENABLE_OUT(2) => bus_command_write, - BUS_WRITE_ENABLE_OUT(3) => bus_ram3b_write, - BUS_TIMEOUT_OUT => open, - - BUS_DATA_IN(0*32+31 downto 0*32) => bus2_ram_data_in, - BUS_DATA_IN(1*32+31 downto 1*32) => bus_ram1c_data_in, - BUS_DATA_IN(2*32+31 downto 2*32) => bus_command_data_in, - BUS_DATA_IN(3*32+31 downto 3*32) => bus_ram3b_data_in, - BUS_DATAREADY_IN(0) => bus2_ram_ack_in, - BUS_DATAREADY_IN(1) => bus_ram1c_ack, - BUS_DATAREADY_IN(2) => bus_command_ack, - BUS_DATAREADY_IN(3) => bus_ram3b_ack, - BUS_WRITE_ACK_IN(0) => bus2_ram_ack_in, - BUS_WRITE_ACK_IN(1) => '0', - BUS_WRITE_ACK_IN(2) => bus_command_ack, - BUS_WRITE_ACK_IN(3) => '0', - BUS_NO_MORE_DATA_IN(0) => bus2_ram_nack_in, - BUS_NO_MORE_DATA_IN(1) => bus_ram1c_nack, - BUS_NO_MORE_DATA_IN(2) => bus_command_retry, - BUS_NO_MORE_DATA_IN(3) => bus_ram3b_nack, - BUS_UNKNOWN_ADDR_IN(0) => '0', - BUS_UNKNOWN_ADDR_IN(1) => bus_ram1c_unkwn, - BUS_UNKNOWN_ADDR_IN(2) => bus_command_nack, - BUS_UNKNOWN_ADDR_IN(3) => bus_ram3b_unkwn - ); - - -ram1a_a1 <= ram1a_a1_base_addr & ram1a_a1_rel_addr; - --- RAM1a holds JTAG registers, written via trbnet -ram_jtag_registers : entity work.ram_dp - generic map( - depth => RAM_JTAG_REGISTERS_DEPTH, - width => 32 - ) - port map ( CLK => CLK_IN, - wr1 => ram1a_wr1, - a1 => ram1a_a1, - dout1 => ram1a_dout1, - din1 => ram1a_din1, - a2 => ram1a_a2, - dout2 => ram1a_dout2 - ); - -ram1a_readport_mux: entity work.ram_mux4to1_readport - generic map( - depth => RAM_JTAG_REGISTERS_DEPTH, - width => 32 - ) - port map ( - SELECT_IN => ram1a_select, - A0_IN => jtag_read_ram1a_a, - D0_OUT => jtag_read_ram1a_d, - A1_IN => jtag_write_ram1a_a, - D1_OUT => jtag_write_ram1a_d, - A2_IN => init_ram1b_ram1a_a, - D2_OUT => init_ram1b_ram1a_d, - A3_IN => jtag_check_crc_ram1a_a, - D3_OUT => jtag_check_crc_ram1a_d, - - RAM_A_OUT => ram1a_a2, - RAM_DOUT_IN => ram1a_dout2 - ); - --- RAM1b holds JTAG registers, read from JTAG chain -ram_jtag_registers_read : entity work.ram_dp - generic map( - depth => RAM_JTAG_REGISTERS_DEPTH, - width => 32 - ) - port map ( CLK => CLK_IN, - wr1 => ram1b_wr1, - a1 => ram1b_a1, - dout1 => ram1b_dout1, - din1 => ram1b_din1, - a2 => copy_ram1b1c_ram1b_a,--ram1b_a2, - dout2 => copy_ram1b1c_ram1b_dout--ram1b_dout2 - ); - --- RAM1b holds JTAG registers, read from JTAG chain -ram_jtag_registers_copy_read : entity work.ram_dp - generic map( - depth => RAM_JTAG_REGISTERS_DEPTH, - width => 32 - ) - port map ( CLK => CLK_IN, - wr1 => copy_ram1b1c_ram1c_wr, - a1 => copy_ram1b1c_ram1c_a, - dout1 => open, - din1 => copy_ram1b1c_ram1c_din, - a2 => ram1c_a2, - dout2 => ram1c_dout2 - ); - - -ram1b_mux2to1_writeport : entity work.ram_mux2to1_writeport - generic map ( - depth => RAM_JTAG_REGISTERS_DEPTH, - width => 32 - ) - port map ( SELECT_IN => ram1b_select, - A0_IN => init_ram1b_ram1b_a, - D0_OUT => init_ram1b_ram1b_dout, - WR0_IN => init_ram1b_ram1b_wr, - DIN0_IN => init_ram1b_ram1b_din, - - A1_IN => jtag_data_to_ram_ram1b_a, - D1_OUT => jtag_data_to_ram_ram1b_dout, - WR1_IN => jtag_data_to_ram_ram1b_wr, - DIN1_IN => jtag_data_to_ram_ram1b_din, - - RAM_A_OUT => ram1b_a1, - RAM_DOUT_IN => ram1b_dout1, - RAM_WR_OUT => ram1b_wr1, - RAM_DIN_OUT => ram1b_din1 - ); - - --- RAM2 holds counts of matching/not matching bits of each register of each chip -ram_match_diff_count : entity work.ram_dp - generic map( - depth => RAM_MATCH_DIFF_COUNT_DEPTH, - width => 32 - ) - port map ( CLK => CLK_IN, - wr1 => ram2_wr1, - a1 => ram2_a1, - dout1 => ram2_dout1, - din1 => ram2_din1, - a2 => "00000000",--ram2_a2, - dout2 => open --ram2_dout2 - ); - -ram2_mux2to1_writeport : entity work.ram_mux2to1_writeport - generic map ( - depth => RAM_MATCH_DIFF_COUNT_DEPTH, - width => 32 - ) - port map ( SELECT_IN => ram2_select, - A0_IN => jtag_tdo_compare_count_ram_a, - D0_OUT => jtag_tdo_compare_count_ram_dout, - WR0_IN => jtag_tdo_compare_count_ram_wr, - DIN0_IN => jtag_tdo_compare_count_ram_din, - - A1_IN => juec_ram2_a, - D1_OUT => juec_ram2_dout, - WR1_IN => '0', - DIN1_IN => x"0000_0000", - - RAM_A_OUT => ram2_a1, - RAM_DOUT_IN => ram2_dout1, - RAM_WR_OUT => ram2_wr1, - RAM_DIN_OUT => ram2_din1 - ); - --- RAM3 holds counts of errors and 'error over threshold's of each register of each chip -ram_error_counts_A : entity work.ram_dp - generic map( - depth => RAM_ERROR_COUNTS_DEPTH, - width => 32 - ) - port map ( CLK => CLK_IN, - wr1 => ram3a_wr1, - a1 => ram3a_a1, - dout1 => ram3a_dout1, - din1 => ram3a_din1, - a2 => ram3a_a2, - dout2 => ram3a_dout2 - ); - --- RAM3B is an on demand copy of RAM3A -ram_error_counts_B : entity work.ram_dp - generic map( - depth => RAM_ERROR_COUNTS_DEPTH, - width => 32 - ) - port map ( - CLK => CLK_IN, - wr1 => jtag_copy_ram3_ram3b_wr, - a1 => jtag_copy_ram3_ram3b_a, - dout1 => open, - din1 => jtag_copy_ram3_ram3b_din, - a2 => ram3b_a2, - dout2 => ram3b_dout2 - ); - -ram3a_mux2to1_writeport : entity work.ram_mux2to1_writeport - generic map ( - depth => RAM_ERROR_COUNTS_DEPTH, - width => 32 - ) - port map ( - SELECT_IN => ram3a_select, - A0_IN => juec_ram3a_a, - D0_OUT => juec_ram3a_dout, - WR0_IN => juec_ram3a_wr, - DIN0_IN => juec_ram3a_din, - - A1_IN => jtag_blank_ram3a_ram3a_a, - D1_OUT => open, - WR1_IN => jtag_blank_ram3a_ram3a_wr, - DIN1_IN => jtag_blank_ram3a_ram3a_din, - - RAM_A_OUT => ram3a_a1, - RAM_DOUT_IN => ram3a_dout1, - RAM_WR_OUT => ram3a_wr1, - RAM_DIN_OUT => ram3a_din1 - ); - -ram3a_readport_mux: entity work.ram_mux2to1_readport - generic map( - depth => RAM_ERROR_COUNTS_DEPTH, - width => 32 - ) - port map ( - SELECT_IN => ram3a_rd_select, - A0_IN => jtag_copy_ram3_ram3a_a, - D0_OUT => jtag_copy_ram3_ram3a_dout, - A1_IN => "000000000", - D1_OUT => open, - - RAM_A_OUT => ram3a_a2, - RAM_DOUT_IN => ram3a_dout2 - ); - - - -the_jtag_init_ram1b: entity work.jtag_init_ram1b - generic map( - RAM_JTAG_REGISTERS_DEPTH => RAM_JTAG_REGISTERS_DEPTH, - MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD, - MAX_REGISTERS_LD => MAX_REGISTERS_LD - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - TRIGGER_INIT_IN => trigger_init_ram1b, - -- RAM1a - RAM1A_A_OUT => init_ram1b_ram1a_a, - RAM1A_D_IN => init_ram1b_ram1a_d, - -- RAM1b - RAM1B_A_OUT => init_ram1b_ram1b_a, - RAM1B_D_IN => init_ram1b_ram1b_dout, - RAM1B_WE_OUT => init_ram1b_ram1b_wr, - RAM1B_D_OUT => init_ram1b_ram1b_din, - - IDLE_OUT => jtag_init_ram1b_idle - ); - -the_jtag_copy_ram1b1c : entity work.copy_ram - generic map ( - ram_depth => RAM_JTAG_REGISTERS_DEPTH, - ram_width => 32 - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - TRIGGER_COPY_IN => trigger_copy_ram1b1c, - -- RAM3a - RAMA_A_OUT => copy_ram1b1c_ram1b_a, - RAMA_D_IN => copy_ram1b1c_ram1b_dout, - -- RAM3b - RAMB_A_OUT => copy_ram1b1c_ram1c_a, - RAMB_D_OUT => copy_ram1b1c_ram1c_din, - RAMB_WR_OUT => copy_ram1b1c_ram1c_wr, - - IDLE_OUT => copy_ram1b1c_idle - ); - - - -the_jtag_copy_ram3 : entity work.copy_ram - generic map ( - ram_depth => RAM_ERROR_COUNTS_DEPTH, - ram_width => 32 - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - TRIGGER_COPY_IN => trigger_copy_ram3, - -- RAM3a - RAMA_A_OUT => jtag_copy_ram3_ram3a_a, - RAMA_D_IN => jtag_copy_ram3_ram3a_dout, - -- RAM3b - RAMB_A_OUT => jtag_copy_ram3_ram3b_a, - RAMB_D_OUT => jtag_copy_ram3_ram3b_din, - RAMB_WR_OUT => jtag_copy_ram3_ram3b_wr, - - IDLE_OUT => jtag_copy_ram3_idle - ); - -the_jtag_blank_ram3a : entity work.blank_ram - generic map ( - ram_depth => RAM_ERROR_COUNTS_DEPTH, - ram_width => 32 - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - TRIGGER_BLANK_IN => trigger_blank_ram3a, - -- RAM --- RAM_A_OUT => jtag_blank_ram3a_ram3a_a, - RAM_A_OUT => open, --- RAM_D_OUT => jtag_blank_ram3a_ram3a_din, - RAM_D_OUT => open, --- RAM_WR_OUT => jtag_blank_ram3a_ram3a_wr, -- disabling blanking ram 29.10.2012 - RAM_WR_OUT => open, - - IDLE_OUT => jtag_blank_ram3a_idle - ); -jtag_blank_ram3a_ram3a_a <= (others => '0'); -jtag_blank_ram3a_ram3a_din <= (others => '0'); -jtag_blank_ram3a_ram3a_wr <= '0'; - - -the_jtag_update_error_counts_ram3a : entity work.jtag_update_error_counts_ram3a - generic map ( - MAX_NUMCHIPS => MAX_NUMCHIPS, - MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD, - MAX_NUMCHIPS_PLUS_ONE_LD => MAX_NUMCHIPS_PLUS_ONE_LD, - MAX_REGISTERS_LD => MAX_REGISTERS_LD, - MAX_REGISTERS_PLUS_ONE_LD => MAX_REGISTERS_PLUS_ONE_LD, - MAX_REGISTERS_PLUS_TWO_LD => MAX_REGISTERS_PLUS_TWO_LD, - RAM_MATCH_DIFF_COUNT_DEPTH => RAM_MATCH_DIFF_COUNT_DEPTH, - RAM_ERROR_COUNTS_DEPTH => RAM_ERROR_COUNTS_DEPTH, - WRITE_ERROR_THRESHOLD => WRITE_ERROR_THRESHOLD, - READ_ERROR_THRESHOLD => READ_ERROR_THRESHOLD - ) - port map( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - TRIGGER_UPDATE_DATA_CHANGED_IN => trigger_juec_update_d_ch, - TRIGGER_UPDATE_READ_ERRORS_IN => trigger_juec_update_rd_err, - TRIGGER_UPDATE_WRITE_ERRORS_IN => trigger_juec_update_wr_err, - TRIGGER_UPDATE_RUN_COUNTER_IN => trigger_juec_update_run_counter, - RUN_COUNTER_IN => std_logic_vector(run_counter), - -- RAM2 - RAM2_A_OUT => juec_ram2_a, - RAM2_D_IN => juec_ram2_dout, - -- RAM3a - RAM3A_A_OUT => juec_ram3a_a, - RAM3A_D_IN => juec_ram3a_dout, - RAM3A_D_OUT => juec_ram3a_din, - RAM3A_WR_OUT => juec_ram3a_wr, - - REMOVED_CHIPS_IN => removed_chips, - NUMCHIPS_CONFIGURED_IN => std_logic_vector(numchips_configured), - NUMREGS_CONFIGURED_IN => jtag_write_numregs_configured, - - DATA_CHANGED_OUT => juec_data_changed, - READ_ERRORS_OUT => juec_read_errors, - WRITE_ERRORS_OUT => juec_write_errors, - - IDLE_OUT => juec_idle - ); - - -the_jtag_read_m26devid_m10: entity work.jtag_read_m26devid_m10 - generic map ( - RAM_JTAG_REGISTERS_DEPTH => RAM_JTAG_REGISTERS_DEPTH, - MAX_NUMCHIPS_PLUS_ONE_LD => MAX_NUMCHIPS_PLUS_ONE_LD, - MAX_NUMCHIPS => MAX_NUMCHIPS, - MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD - ) - port map( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - RAM_JTAG_REGISTERS_A_OUT => jtag_read_ram1a_a, - RAM_JTAG_REGISTERS_D_IN => jtag_read_ram1a_d, - NEXT_NOT_REMOVED_IN => jtag_next_not_removed, - BEGIN_JTAGBITCALC_IN => begin_jtag_bitcalc, - TRIGGER_BEGIN_READ_IN => trigger_jtag_read, - IS_DR_BIT_OUT => jtag_read_is_dr_bit, - IS_FIRSTBIT_OUT => jtag_read_is_firstbit, - IS_LASTBIT_OUT => jtag_read_is_lastbit, - CHIPNUM_OUT => jtag_read_chipnum, - ENABLE_JTAG_CLOCK_OUT => jtag_read_enable_jtag_clock, - LAST_TCK_CYCLE_OUT => jtag_read_last_tck_cycle, - TMS_OUT => jtag_read_tms, - TDI_OUT => jtag_read_tdi, - EXPECTED_TDO_OUT => jtag_read_expected_tdo, - IDLE_OUT => jtag_read_idle - ); - -the_jtag_tdo_data_to_ram_m10 : entity work.jtag_tdo_data_to_ram_m10 - generic map ( - enable_ram1b => '1', - MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD, - MAX_REGISTERS_PLUS_ONE_LD => MAX_REGISTERS_PLUS_ONE_LD, - MAX_REGLEN_LD => MAX_REGLEN_LD, - RAM_JTAG_REGISTERS_DEPTH => RAM_JTAG_REGISTERS_DEPTH - ) - port map( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - SAMPLE_PULSE3_D1_IN => jtag_sample_pulse3_d1, - CHIPNUM_IN => jtag_delayed_chipnum, - REGNUM_IN => jtag_delayed_regnum, - ENABLE_DATAOUT_IN => jtag_delayed_is_dr_bit, - IS_FIRSTBIT_IN => jtag_delayed_is_firstbit, - IS_LASTBIT_IN => jtag_delayed_is_lastbit, - TDO_SAMPLED_IN => jtag_tdo_sampled, - -- RAM1b - RAM_JTAG_REGISTERS_READOUT_A_OUT => jtag_data_to_ram_ram1b_a, - RAM_JTAG_REGISTERS_READOUT_D_IN => jtag_data_to_ram_ram1b_dout, - RAM_JTAG_REGISTERS_READOUT_WE_OUT => jtag_data_to_ram_ram1b_wr, - RAM_JTAG_REGISTERS_READOUT_D_OUT => jtag_data_to_ram_ram1b_din - --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0); - --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0); - ); - -the_jtag_tdo_compare_count_m10 : entity work.jtag_tdo_compare_count_m10 - generic map ( - MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD, - MAX_REGISTERS_PLUS_ONE_LD => MAX_REGISTERS_PLUS_ONE_LD, - RAM_MATCH_DIFF_COUNT_DEPTH => RAM_MATCH_DIFF_COUNT_DEPTH, - MAX_REGLEN_LD => MAX_REGLEN_LD - ) - port map( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - SAMPLE_PULSE3_D1_IN => jtag_sample_pulse3_d1, - CHIPNUM_IN => jtag_delayed_chipnum, - REGNUM_IN => jtag_delayed_regnum, - ENABLE_COUNTERS_IN => jtag_delayed_is_dr_bit, - IS_FIRSTBIT_IN => jtag_delayed_is_firstbit, - IS_LASTBIT_IN => jtag_delayed_is_lastbit, - TDO_EXPECTED_IN => jtag_delayed_tdo_expected, - TDO_SAMPLED_IN => jtag_tdo_sampled, - TDO_SAMPLING_ERROR_IN => jtag_tdo_sampling_error, - RAM_MATCH_DIFF_COUNT_A_OUT => jtag_tdo_compare_count_ram_a, - RAM_MATCH_DIFF_COUNT_WE_OUT => jtag_tdo_compare_count_ram_wr, - RAM_MATCH_DIFF_COUNT_D_OUT => jtag_tdo_compare_count_ram_din - --INTERNAL_ERROR_OUT => jtag_tdo_compare_count_internal_error - --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0); - --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0); - ); - - -the_jtag_tdo_compare_counttotal_noram_m10 : entity work.jtag_tdo_compare_counttotal_noram_m10 - generic map ( - numcounts => 3, - se_counter_width => COUNTER_WIDTHS, -- sampling error counter width - diff_counter_width => COUNTER_WIDTHS -- counter width for number of runs in which there were differences - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - SAMPLE_PULSE3_D1_IN => jtag_sample_pulse3_d1, - ENABLE_COUNTERS_IN => jtag_delayed_is_dr_bit, - TDO_EXPECTED_IN => jtag_delayed_tdo_expected, - TDO_SAMPLED_IN => jtag_tdo_sampled, - TDO_SAMPLING_ERROR_IN => jtag_tdo_sampling_error, - BEGIN_COUNT_I_IN(2) => begin_count_read_errors, - BEGIN_COUNT_I_IN(1) => begin_count_write_errors, - BEGIN_COUNT_I_IN(0) => begin_count_data_changed, - - END_COUNT_I_IN(2) => end_count_read_errors, - END_COUNT_I_IN(1) => end_count_write_errors, - END_COUNT_I_IN(0) => end_count_data_changed, - - SAMPLING_ERRORS_COUNT_OUT => SAMPLING_ERRORS_COUNT_OUT, - COUNTS_OUT(0*COUNTER_WIDTHS+COUNTER_WIDTHS-1 downto 0*COUNTER_WIDTHS) => sDATA_CHANGED_COUNT_OUT, - COUNTS_OUT(1*COUNTER_WIDTHS+COUNTER_WIDTHS-1 downto 1*COUNTER_WIDTHS) => sWRITE_ERRORS_COUNT_OUT, - COUNTS_OUT(2*COUNTER_WIDTHS+COUNTER_WIDTHS-1 downto 2*COUNTER_WIDTHS) => sREAD_ID_ERRORS_COUNT_OUT, - LAST_VALUES_OUT(2) => last_read_error, - LAST_VALUES_OUT(1) => last_write_error, - LAST_VALUES_OUT(0) => last_data_changed - ); - -the_jtag_delay_expected_values: entity work.jtag_delay_expected_values - generic map ( - ld_maxdelay => JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD, - MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD, - MAX_REGISTERS_PLUS_ONE_LD => MAX_REGISTERS_PLUS_ONE_LD - ) - port map( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - SAMPLE_PULSE1_IN => jtag_sample_pulse1, - CHIPNUM_IN => jtag_meta_chipnum, - REGNUM_IN => jtag_meta_regnum, - IS_DR_BIT_IN => jtag_meta_is_dr_bit, - IS_FIRSTBIT_IN => jtag_meta_is_firstbit, - IS_LASTBIT_IN => jtag_meta_is_lastbit, - TDO_EXPECTED_IN => jtag_meta_expected_tdo, - OUT_CHIPNUM_OUT => jtag_delayed_chipnum, - OUT_REGNUM_OUT => jtag_delayed_regnum, - OUT_IS_DR_BIT_OUT => jtag_delayed_is_dr_bit, - OUT_IS_FIRSTBIT_OUT => jtag_delayed_is_firstbit, - OUT_IS_LASTBIT_OUT => jtag_delayed_is_lastbit, - OUT_TDO_EXPECTED_OUT => jtag_delayed_tdo_expected, - DELAY_IN => jtag_delay_expvalues -); - -the_jtag_mux_buffer_tms_tdi_out_and_metainfo : entity work.jtag_mux_buffer_tms_tdi_out_and_metainfo - generic map ( - MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD, - MAX_REGISTERS_LD => MAX_REGISTERS_LD - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - JTAG_SET_DATA_IN => jtag_set_data_pulse, - -- read DEV_ID inputs - RD_TMS_IN => jtag_read_tms, - RD_TDI_IN => jtag_read_tdi, - RD_IS_DR_BIT_IN => jtag_read_is_dr_bit, - RD_IS_FIRSTBIT_IN => jtag_read_is_firstbit, - RD_IS_LASTBIT_IN => jtag_read_is_lastbit, - RD_CHIPNUM_IN => jtag_read_chipnum, - RD_ENABLE_JTAG_CLOCK_IN => jtag_read_enable_jtag_clock, - RD_LAST_TCK_CYCLE_IN => jtag_read_last_tck_cycle, - RD_EXPECTED_TDO_IN => jtag_read_expected_tdo, - -- write registers inputs - WR_TMS_IN => jtag_write_tms, - WR_TDI_IN => jtag_write_tdi, - WR_IS_DR_BIT_IN => jtag_write_is_dr_bit, - WR_IS_FIRSTBIT_IN => jtag_write_is_firstbit, - WR_IS_LASTBIT_IN => jtag_write_is_lastbit, - WR_CHIPNUM_IN => jtag_write_chipnum, - WR_REGNUM_IN => jtag_write_regnum, - WR_ENABLE_JTAG_CLOCK_IN => jtag_write_enable_jtag_clock, - WR_LAST_TCK_CYCLE_IN => jtag_write_last_tck_cycle, - WR_EXPECTED_TDO_IN => jtag_write_expected_tdo, - -- test chain inputs - TC_TMS_IN => jtag_bypassreg_tms, - TC_TDI_IN => jtag_bypassreg_tdi, - TC_ENABLE_JTAG_CLOCK_IN => jtag_bypassreg_enable_jtag_clock, - TC_LAST_TCK_CYCLE_IN => jtag_bypassreg_last_tck_cycle, - - TMS_OUT => jtag_tms, - TDI_OUT => jtag_tdi, - IS_DR_BIT_OUT => jtag_meta_is_dr_bit, - IS_FIRSTBIT_OUT => jtag_meta_is_firstbit, - IS_LASTBIT_OUT => jtag_meta_is_lastbit, - CHIPNUM_OUT => jtag_meta_chipnum, - REGNUM_OUT => jtag_meta_regnum, - ENABLE_JTAG_CLOCK_OUT => jtag_enable_clock, - LAST_TCK_CYCLE_OUT => jtag_meta_last_tck_cycle, - EXPECTED_TDO_OUT => jtag_meta_expected_tdo - ); - -the_jtag_tdo_sampler : entity work.jtag_tdo_sample - port map( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - SAMPLE_PULSE1_IN => jtag_sample_pulse1, - SAMPLE_PULSE2_IN => jtag_sample_pulse2, - SAMPLE_PULSE3_IN => jtag_sample_pulse3, - -- TDO signal, which is to be sampled - TDO_IN => JTAG_TDO_IN, - -- sampled value of TDO - TDO_SAMPLED_OUT => jtag_tdo_sampled, - -- sampling error - SAMPLING_ERROR_OUT => jtag_tdo_sampling_error - ); - -the_jtag_write_m10: entity work.jtag_write_m10 - generic map ( - RAM_JTAG_REGISTERS_DEPTH => RAM_JTAG_REGISTERS_DEPTH, - MAX_NUMCHIPS => MAX_NUMCHIPS, - MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD, - MAX_NUMCHIPS_PLUS_ONE_LD => MAX_NUMCHIPS_PLUS_ONE_LD, - MAX_REGISTERS_LD => MAX_REGISTERS_LD, - MAX_REGISTERS_PLUS_ONE_LD => MAX_REGISTERS_PLUS_ONE_LD, - MAX_REGLEN_LD => MAX_REGLEN_LD, - MAX_REGLEN_PLUS_ONE_LD => MAX_REGLEN_PLUS_ONE_LD - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - RAM_JTAG_REGISTERS_A_OUT => jtag_write_ram1a_a, - RAM_JTAG_REGISTERS_D_IN => jtag_write_ram1a_d, - NEXT_NOT_REMOVED_IN => jtag_next_not_removed, - BEGIN_JTAGBITCALC_IN => begin_jtag_bitcalc, - TRIGGER_BEGIN_WRITE_IN => trigger_jtag_write, - IS_DR_BIT_OUT => jtag_write_is_dr_bit, - IS_FIRSTBIT_OUT => jtag_write_is_firstbit, - IS_LASTBIT_OUT => jtag_write_is_lastbit, - CHIPNUM_OUT => jtag_write_chipnum, - REGNUM_OUT => jtag_write_regnum, - ENABLE_JTAG_CLOCK_OUT => jtag_write_enable_jtag_clock, - LAST_TCK_CYCLE_OUT => jtag_write_last_tck_cycle, - TMS_OUT => jtag_write_tms, - TDI_OUT => jtag_write_tdi, - EXPECTED_TDO_OUT => jtag_write_expected_tdo, - IDLE_OUT => jtag_write_idle, - NUMREGS_CONFIGURED_OUT => jtag_write_numregs_configured, - LAST_ERROR_CODE_OUT => jtag_write_last_error_code - ); - -the_jtag_tck_out: entity work.jtag_tck_out_component - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - - JTAG_CLOCK_PULSE1_IN => jtag_clock_pulse1, - JTAG_CLOCK_PULSE2_IN => jtag_clock_pulse2, - ENABLE_JTAG_TCK_IN => jtag_enable_clock, - - TCK_OUT => jtag_tck - ); - -the_jtag_pulses : entity work.jtag_pulses - generic map ( - time_bits => 10 - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => jtag_pulses_reset_complete, - -- input times - JTAG_CLOCK_TIME1_IN => std_logic_vector(jtag_clock_time1), - JTAG_CLOCK_TIME2_IN => std_logic_vector(jtag_clock_time2), - JTAG_SAMPLE_TIME1_IN => std_logic_vector(jtag_sample_time1), - JTAG_SAMPLE_TIME2_IN => std_logic_vector(jtag_sample_time2), - JTAG_SAMPLE_TIME3_IN => std_logic_vector(jtag_sample_time3), - JTAG_SET_DATA_TIME_IN => std_logic_vector(jtag_set_data_time), - - JTAG_CLOCK_CYCLE_LENGTH_IN => std_logic_vector(jtag_clock_cycle_length), - - -- output pulses - BEGIN_JTAGBITCALC_OUT => begin_jtag_bitcalc, - JTAG_CLOCK_PULSE1_OUT => jtag_clock_pulse1, - JTAG_CLOCK_PULSE2_OUT => jtag_clock_pulse2, - JTAG_SAMPLE_PULSE1_OUT => jtag_sample_pulse1, - JTAG_SAMPLE_PULSE2_OUT => jtag_sample_pulse2, - JTAG_SAMPLE_PULSE3_OUT => jtag_sample_pulse3, - JTAG_SET_DATA_PULSE_OUT => jtag_set_data_pulse - ); - -the_jtag_check_crc_ram1a: entity work.jtag_check_crc_ram1a - generic map ( - RAM_JTAG_REGISTERS_DEPTH => RAM_JTAG_REGISTERS_DEPTH, - MAX_NUMCHIPS => MAX_NUMCHIPS, - MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD, - MAX_NUMCHIPS_PLUS_ONE_LD => MAX_NUMCHIPS_PLUS_ONE_LD, - MAX_REGLEN_PLUS_ONE_LD => MAX_REGLEN_PLUS_ONE_LD, - MAX_REGISTERS_LD => MAX_REGISTERS_LD - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - TRIGGER_CHECK_IN => trigger_check_crc_ram1a, - -- RAM1a - RAM1A_A_OUT => jtag_check_crc_ram1a_a, - RAM1A_D_IN => jtag_check_crc_ram1a_d, - NUMCHIPS_IN => std_logic_vector(numchips_configured), - CRC_OK_OUT => jtag_check_crc_ram1a_crc_ok, - IDLE_OUT => jtag_check_crc_ram1a_idle - ); - - ---BUS_DATA_OUT <= bus_data_out_buffer; ---BUS_DATAREADY_OUT <= bus_dataready; ---BUS_NO_MORE_DATA_OUT <= bus_no_more_data; ---BUS_WRITE_ACK_OUT <= bus_write_ack; ---BUS_UNKNOWN_ADDR_OUT <= bus_unknown_addr; -MY_STATUS_OUT <= (others => '0'); --my_status; -JTAG_TCK_OUT <= jtag_tck; -JTAG_TMS_OUT <= jtag_tms; -JTAG_TDI_OUT <= jtag_tdi; -PROG_JTAG_FINISHED_OUT <= prog_jtag_finished; -READ_ID_ERRORS_COUNT_OUT <= sREAD_ID_ERRORS_COUNT_OUT; -WRITE_ERRORS_COUNT_OUT <= sWRITE_ERRORS_COUNT_OUT; -DATA_CHANGED_COUNT_OUT <= sDATA_CHANGED_COUNT_OUT; - - -jtag_pulses_reset_complete <= jtag_pulses_reset or RESET_IN; - -m26cs_stopped <= '1' when m26cs_state = M26CSS_STOPPED else '0'; - -jtag_sample_pulse3_d1_next <= jtag_sample_pulse3; - - -SEQUENTIAL : process (CLK_IN) -begin - if (rising_edge(CLK_IN)) then - if(RESET_IN = '1') then - idle_out_signal <= '0'; - crc_status_register <= (others => '0'); - chip_counter_start <= '0'; - prog_jtag_finished <= '0'; - -- NEW SIGNALS - jtag_status2_copy_requested <= '0'; - cps2_state <= CPS2_IDLE; - status2_run_counter <= (others =>'0'); - status2_chain_status <= (others =>'0'); - jtag_sample_pulse3_d1 <= '0'; - - - - crc_error_on_last_check <= '0'; - last_run_successful <= '0'; - last_run_successful_tmp <= '0'; - else - idle_out_signal <= idle_out_signal_next; - crc_status_register <= crc_status_register_next; - chip_counter_start <= chip_counter_start_next; - prog_jtag_finished <= prog_jtag_finished_next; - --last_write_successful <= last_write_successful_next; - -- NEW SIGNALS - jtag_status2_copy_requested <= jtag_status2_copy_requested_next; - cps2_state <= cps2_state_next; - status2_run_counter <= status2_run_counter_next; - status2_chain_status <= status2_chain_status_next; - jtag_sample_pulse3_d1 <= jtag_sample_pulse3_d1_next; - - crc_error_on_last_check <= crc_error_on_last_check_next; - last_run_successful <= last_run_successful_next; - last_run_successful_tmp <= last_run_successful_tmp_next; - end if; - end if; -end process; - - -SYNCHRONOUS_CHIP_COUNTER : process (CLK_IN) -begin - if (rising_edge(CLK_IN)) then - if(RESET_IN = '1') then - cc_state <= CC_IDLE; - numchips_active <= (others =>'0'); - numchips_active_acc <= (others =>'0'); - cc_chip_i <= (others =>'0'); - cc_nextnotremoved_i <= (others =>'0'); - last_not_removed <= (others =>'0'); - first_not_removed <= (others =>'0'); - jtag_next_not_removed <= (others =>'0'); - else - cc_state <= cc_state_next; - numchips_active <= numchips_active_next; - numchips_active_acc <= numchips_active_acc_next; - cc_chip_i <= cc_chip_i_next; - cc_nextnotremoved_i <= cc_nextnotremoved_i_next; - last_not_removed <= last_not_removed_next; - first_not_removed <= first_not_removed_next; - jtag_next_not_removed <= jtag_next_not_removed_next; - end if; - end if; -end process; - -COMB_CHIP_COUNTER : process (cc_state, removed_chips, chip_counter_start, numchips_configured, - cc_chip_i, cc_nextnotremoved_i, numchips_active, - numchips_active_acc, last_not_removed, first_not_removed, jtag_next_not_removed) -begin - cc_state_next <= cc_state; - numchips_active_next <= numchips_active; - numchips_active_acc_next <= numchips_active_acc; - -- index, running through chips - cc_chip_i_next <= cc_chip_i; - -- index, last not removed sensor - cc_nextnotremoved_i_next <= cc_nextnotremoved_i; - last_not_removed_next <= last_not_removed; - first_not_removed_next <= first_not_removed; - - jtag_next_not_removed_next <= jtag_next_not_removed; - case cc_state is - when CC_IDLE => - if(chip_counter_start = '1') then - -- determine number of chips connected in serial to jtag chain - cc_chip_i_next <= (others => '0'); - cc_nextnotremoved_i_next <= (others => '0'); --position in jtag_next_not_removed, - -- with the following initialization no chip will be unremoved, because - -- last_not_removed < first_not_removed - -- and numchips_active will be set to 0 if really all chips are removed - first_not_removed_next <= (others => '1'); - last_not_removed_next <= (others =>'0'); - jtag_next_not_removed_next <= (others =>'0'); - numchips_active_acc_next <= (others => '0'); - cc_state_next <= CC_COUNT_SENSOR; - end if; - when CC_COUNT_SENSOR => - if(removed_chips(to_integer(cc_chip_i)) = '0') then - numchips_active_acc_next <= numchips_active_acc + 1; - last_not_removed_next <= cc_chip_i; - -- if first_not_removed unset - if(std_logic_vector_all_components_equal_scalar(std_logic_vector(first_not_removed), '1') = '1') then - first_not_removed_next <= cc_chip_i; - end if; - cc_nextnotremoved_i_next <= cc_chip_i + 1; -- next not removed chip after chip i is stored at location (i+1) in jtag_next_not_removed - jtag_next_not_removed_next(to_integer(cc_nextnotremoved_i)*MAX_NUMCHIPS_PLUS_ONE_LD+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto to_integer(cc_nextnotremoved_i)*MAX_NUMCHIPS_PLUS_ONE_LD) <= - std_logic_vector(cc_chip_i); - end if; - if(cc_chip_i = numchips_configured - 1) then - cc_state_next <= CC_SETNUMCHIPS; -- finished counting active chips - else - cc_chip_i_next <= cc_chip_i + 1; - end if; - when CC_SETNUMCHIPS => - jtag_next_not_removed_next((to_integer(cc_nextnotremoved_i))*MAX_NUMCHIPS_PLUS_ONE_LD+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto (to_integer(cc_nextnotremoved_i))*MAX_NUMCHIPS_PLUS_ONE_LD) <= (others => '1'); -- set next chip for last chip to invalid - numchips_active_next <= numchips_active_acc; - cc_state_next <= CC_IDLE; - end case; -end process; - - --- delay one clock cycle -jtag_refresh_active_last <= jtag_refresh_active when rising_edge(CLK_IN); - - --- monitoring ---MON_FIFO_WRITE_OUT(0) <= read_mon_write_out; ---MON_FIFO_WRITE_OUT(1) <= read_mon_write_out; ---MON_FIFO_WRITE_OUT(2) <= read_mon_write_out; --- monitoring debug test ---MON_FIFO_DATA_OUT(79 downto 64) <= JTAG_M26_DEV_ID(15 downto 0); ---MON_FIFO_DATA_OUT(111 downto 96) <= JTAG_M26_DEV_ID(31 downto 16); ---MON_FIFO_WRITE_OUT(2) <= '1'; ---MON_FIFO_WRITE_OUT(3) <= '1'; - -SYNCHRONOUS_M26_CONTROLLER_SIMPLE : process (CLK_IN) -begin - if (rising_edge(CLK_IN)) then - if(RESET_IN = '1') then - m26cs_state <= M26CSS_STOPPED; - trigger_begin_bypassreg <= '0'; - trigger_jtag_read <= '0'; - trigger_jtag_write <= '0'; - trigger_copy_ram3 <= '0'; - trigger_juec_update_d_ch <= '0'; - trigger_juec_update_rd_err <= '0'; - trigger_juec_update_wr_err <= '0'; - trigger_juec_update_run_counter <= '0'; - trigger_check_crc_ram1a <= '0'; - trigger_init_ram1b <= '0'; - trigger_blank_ram3a <= '0'; - run_counter <= (others =>'0'); - m26cs_firstrun <= '0'; - jtag_chain_broken_counter <= (others =>'0'); - ram1a_select <= (others =>'0'); - ram1b_select <= '0'; - ram2_select <= '0'; - ram3a_select <= '0'; - ram3a_rd_select <= '0'; - chain_status <= (others =>'0'); - request_reset <= '0'; - reset_wait <= (others =>'0'); - run_requested <= '0'; - write_once_requested <= '0'; - write_once_count <= (others =>'0'); - begin_count_read_errors <= '0'; - begin_count_write_errors <= '0'; - begin_count_data_changed <= '0'; - end_count_read_errors <= '0'; - end_count_write_errors <= '0'; - end_count_data_changed <= '0'; - -- INSERTLABEL: SYNCHRONOUS reset - else - m26cs_state <= m26cs_state_next; - trigger_begin_bypassreg <= trigger_begin_bypassreg_next; - trigger_jtag_read <= trigger_jtag_read_next; - trigger_jtag_write <= trigger_jtag_write_next; - trigger_copy_ram3 <= trigger_copy_ram3_next; - trigger_juec_update_d_ch <= trigger_juec_update_d_ch_next; - trigger_juec_update_rd_err <= trigger_juec_update_rd_err_next; - trigger_juec_update_wr_err <= trigger_juec_update_wr_err_next; - trigger_juec_update_run_counter <= trigger_juec_update_run_counter_next; - trigger_check_crc_ram1a <= trigger_check_crc_ram1a_next; - trigger_init_ram1b <= trigger_init_ram1b_next; - trigger_blank_ram3a <= trigger_blank_ram3a_next; - run_counter <= run_counter_next; - m26cs_firstrun <= m26cs_firstrun_next; - jtag_chain_broken_counter <= jtag_chain_broken_counter_next; - ram1a_select <= ram1a_select_next; - ram1b_select <= ram1b_select_next; - ram2_select <= ram2_select_next; - ram3a_select <= ram3a_select_next; - ram3a_rd_select <= ram3a_rd_select_next; - chain_status <= chain_status_next; - request_reset <= request_reset_next; - reset_wait <= reset_wait_next; - run_requested <= run_requested_next; - write_once_requested <= write_once_requested_next; - write_once_count <= write_once_count_next; - begin_count_read_errors <= begin_count_read_errors_next; - begin_count_write_errors <= begin_count_write_errors_next; - begin_count_data_changed <= begin_count_data_changed_next; - end_count_read_errors <= end_count_read_errors_next; - end_count_write_errors <= end_count_write_errors_next; - end_count_data_changed <= end_count_data_changed_next; - - -- INSERTLABEL: SYNCHRONOUS update - end if; - end if; -end process; - -COMB_M26_CONTROLLER_SIMPLE : process (RUN_REQUEST_IN, WRITE_ONCE_REQUEST_IN, m26cs_state, jtag_bypassreg_last_tck_cycle, - jtag_bypassreg_idle, jtag_read_idle, jtag_write_last_tck_cycle, jtag_write_idle, - juec_idle, cc_state, breakpoint_active, run_counter, m26cs_firstrun, - jtag_status2_copy_requested, jtag_check1_active, jtag_refresh_active, - jtag_chain_broken_counter, prog_jtag_finished, ram1a_select, - jtag_check_crc_ram1a_idle, jtag_check_crc_ram1a_crc_ok, numchips_configured, - ram1a_select, ram1b_select, ram2_select, ram3a_select, ram3a_rd_select, - chain_status, jtag_init_ram1b_idle, jtag_bypassreg_chain_broken, - jtag_bypassreg_length, crc_status_register, jtag_blank_ram3a_idle, - ram1b_copy_requested, jtag_refresh_active_last, m26csoptions, - crc_error_on_last_check, last_run_successful, last_run_successful_tmp, - last_read_error, last_write_error, request_reset, reset_wait, run_requested, - write_once_requested, write_once_count) -- INSERTLABEL: sensitivity list --jtag_read_last_tck_cycle, -variable output : std_logic; -variable i : integer; -begin - m26cs_state_next <= m26cs_state; - trigger_begin_bypassreg_next <= '0'; - trigger_jtag_read_next <= '0'; - trigger_jtag_write_next <= '0'; - trigger_juec_update_d_ch_next <= '0'; - trigger_juec_update_rd_err_next <= '0'; - trigger_juec_update_wr_err_next <= '0'; - trigger_juec_update_run_counter_next <= '0'; - trigger_check_crc_ram1a_next <= '0'; - trigger_init_ram1b_next <= '0'; - trigger_blank_ram3a_next <= '0'; - run_counter_next <= run_counter; - m26cs_firstrun_next <= m26cs_firstrun; - idle_out_signal_next <= '0'; - jtag_chain_broken_counter_next <= jtag_chain_broken_counter; - chip_counter_start_next <= '0'; - prog_jtag_finished_next <= prog_jtag_finished; - chain_status_next <= chain_status; - crc_status_register_next <= crc_status_register; - - -- ram multiplexers - ram1a_select_next <= ram1a_select; - ram1b_select_next <= ram1b_select; - ram2_select_next <= ram2_select; - ram3a_select_next <= ram3a_select; - ram3a_rd_select_next <= ram3a_rd_select; - - crc_error_on_last_check_next <= crc_error_on_last_check; - last_run_successful_next <= last_run_successful; - last_run_successful_tmp_next <= last_run_successful_tmp; - begin_count_read_errors_next <= '0'; -- added 201210 - begin_count_write_errors_next <= '0'; -- added 201210 - begin_count_data_changed_next <= '0'; -- added 201210 - end_count_read_errors_next <= '0'; -- added 201210 - end_count_write_errors_next <= '0'; -- added 201210 - end_count_data_changed_next <= '0'; -- added 201210 - request_reset_next <= request_reset; - reset_wait_next <= reset_wait; - run_requested_next <= run_requested; - write_once_requested_next <= write_once_requested; - write_once_count_next <= write_once_count; - -- INSERTLABEL: COMB defaults - - - - case m26cs_state is - when M26CSS_STOPPED => - -- if stopped, start again if jtag_refresh_active is set - if(jtag_check1_active = '1' and jtag_status2_copy_requested = '0' and ram1b_copy_requested = '0') then - m26cs_state_next <= M26CSS_CHECK1_WAIT_FOR_HAVE_TIME; - elsif(jtag_refresh_active = '1' and jtag_status2_copy_requested = '0' and ram1b_copy_requested = '0') then - m26cs_state_next <= M26CSS_WAIT_FOR_TRIGGER; - -- if just started, reset all counters - if(jtag_refresh_active_last = '0') then - m26cs_firstrun_next <= '1'; - end if; - end if; - when M26CSS_CHECK1_WAIT_FOR_HAVE_TIME => - --if(have_time_for_check) then - m26cs_state_next <= M26CSS_COUNT_CHIPS_BEGIN; - --end if; - - when M26CSS_WAIT_FOR_TRIGGER => - idle_out_signal_next <= '1'; - last_run_successful_next <= last_run_successful_tmp; - -- if not stopped, test if we should stop - if(jtag_refresh_active = '0' or jtag_status2_copy_requested = '1' or ram1b_copy_requested = '1') then - ram3a_rd_select_next <= '0'; -- select jtag_copy_ram3_ram3a - m26cs_state_next <= M26CSS_STOPPED; - else - -- if we should not stop, check for off_spill and if we have time for writing - if(run_requested = '1') then - -- increment run counter (exclusively done here) - run_counter_next <= run_counter + 1; - prog_jtag_finished_next <= '0'; - trigger_check_crc_ram1a_next <= '1'; - ram1a_select_next <= "11"; -- select check_crc_ram1a - if(m26cs_firstrun = '1') then - trigger_blank_ram3a_next <= '1'; - ram3a_select_next <= '1'; -- blank_ram3a (at same time) - end if; - last_run_successful_tmp_next <= '0'; - m26cs_state_next <= M26CSS_CHECK_CRC_RAM1A_BEGIN; - elsif(write_once_requested = '1') then - trigger_check_crc_ram1a_next <= '1'; - ram1a_select_next <= "11"; -- select check_crc_ram1a - m26cs_state_next <= M26CSS_WRITEONCE_CHECK_CRC_RAM1A_BEGIN; - end if; - end if; - when M26CSS_CHECK_CRC_RAM1A_BEGIN => - m26cs_state_next <= M26CSS_CHECK_CRC_RAM1A_WAIT; - when M26CSS_CHECK_CRC_RAM1A_WAIT => - if(jtag_check_crc_ram1a_idle = '1') then - crc_status_register_next <= jtag_check_crc_ram1a_crc_ok; - output := '1'; - for i in MAX_NUMCHIPS-1 downto 0 loop - if(jtag_check_crc_ram1a_crc_ok(i) /= '1' and i < to_integer(numchips_configured)) then - output := '0'; - end if; - end loop; - --if(std_logic_vector_all_components_equal_scalar(jtag_check_crc_ram1a_crc_ok(to_integer(numchips_configured)-1 downto 0), '1') = '1') then - if(output = '1') then - -- if no crc errors for configured chips (consider changing this to checking the whole vector, and also let zeros be ok for crc check) - crc_error_on_last_check_next <= '0'; - trigger_init_ram1b_next <= '1'; - ram1b_select_next <= '0'; -- select init ram1b - ram1a_select_next <= "10"; -- select init ram1b - m26cs_state_next <= M26CSS_INIT_RAM1B_BEGIN; - else - -- crc error in configured chips, don't continue - crc_error_on_last_check_next <= '1'; - -- clear requests - run_requested_next <= '0'; - write_once_requested_next <= '0'; - m26cs_state_next <= M26CSS_WAIT_FOR_TRIGGER; - end if; - end if; - when M26CSS_INIT_RAM1B_BEGIN => - m26cs_state_next <= M26CSS_INIT_RAM1B_WAIT; - when M26CSS_INIT_RAM1B_WAIT => - if(jtag_init_ram1b_idle = '1') then - if(m26cs_firstrun = '1') then - -- skip data changed - chip_counter_start_next <= '1'; - m26cs_state_next <= M26CSS_COUNT_CHIPS_BEGIN; - else - trigger_jtag_write_next <= '1'; - ram1a_select_next <= "01"; -- select jtag_write_ram1a_a - ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b - ram2_select_next <= '0'; -- tdo_compare_count - begin_count_data_changed_next <= '1';-- added 201210 - m26cs_state_next <= M26CSS_DATA_CHANGED_BEGIN; - end if; - end if; - when M26CSS_DATA_CHANGED_BEGIN => - m26cs_state_next <= M26CSS_DATA_CHANGED_WAIT; - when M26CSS_DATA_CHANGED_WAIT => - if(jtag_write_last_tck_cycle = '1' or jtag_write_idle = '1') then - end_count_data_changed_next <= '1'; -- added 201210 - m26cs_state_next <= M26CSS_BLANK_RAM3A_WAIT; - end if; - when M26CSS_BLANK_RAM3A_WAIT => - if(jtag_blank_ram3a_idle = '1') then - if(breakpoint_active(0) = '1') then - --stay in state - --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT; - else - trigger_juec_update_d_ch_next <= '1'; - ram2_select_next <= '1'; -- juec - ram3a_select_next <= '0'; -- juec - m26cs_state_next <= M26CSS_JUEC_DATA_CHANGED_BEGIN; - end if; - end if; - when M26CSS_JUEC_DATA_CHANGED_BEGIN => - m26cs_state_next <= M26CSS_JUEC_DATA_CHANGED_WAIT; - when M26CSS_JUEC_DATA_CHANGED_WAIT => - if(juec_idle = '1') then - if(breakpoint_active(1) = '1') then - --stay in state - --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT; - else - chip_counter_start_next <= '1'; - m26cs_state_next <= M26CSS_COUNT_CHIPS_BEGIN; - end if; - end if; - - when M26CSS_COUNT_CHIPS_BEGIN => - m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT; - when M26CSS_COUNT_CHIPS_WAIT => - if(cc_state = CC_IDLE) then - if(breakpoint_active(2) = '1') then - --stay in state - --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT; - else --- if(m26csoptions(0) = '1') then - -- skip BYPASSREG CHAIN TEST - -- and set CHAIN status to BROKEN - chain_status_next(0) <= '1'; - chain_status_next(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 3) <= (others => '0'); - -- next state: - ram2_select_next <= '0'; -- tdo_compare_count - ram1a_select_next <= "00"; -- select jtag_read_ram1a_a - ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b - trigger_jtag_read_next <= '1';-- temporarily go on (for testing without mimosa26 emulator) - begin_count_read_errors_next <= '1'; -- added 201210 - m26cs_state_next <= M26CSS_READ1_BEGIN; -- temporarily go on (for testing without mimosa26 emulator) --- else --- trigger_begin_bypassreg_next <= '1'; --- m26cs_state_next <= M26CSS_BYPASSREG_BEGIN; --- end if; - end if; - end if; - when M26CSS_BYPASSREG_BEGIN => - m26cs_state_next <= M26CSS_BYPASSREG_WAIT; - when M26CSS_BYPASSREG_WAIT => - if(jtag_bypassreg_last_tck_cycle = '1' or jtag_bypassreg_idle = '1') then - if(breakpoint_active(3) = '1') then - --stay in state - --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT; - else - chain_status_next(0) <= jtag_bypassreg_chain_broken; -- chain broken - if(unsigned(jtag_bypassreg_length) < 2**MAX_NUMCHIPS_PLUS_ONE_LD) then - chain_status_next(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 3) <= jtag_bypassreg_length(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0); -- chain length - else - chain_status_next(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 3) <= (others => '0'); -- chain length: set to zero because to long chain found - end if; - if(jtag_bypassreg_chain_broken = '1') then - jtag_chain_broken_counter_next <= jtag_chain_broken_counter + 1; - - --m26cs_state_next <= M26CSS_WAIT_FOR_TRIGGER; - ram2_select_next <= '0'; -- tdo_compare_count - ram1a_select_next <= "00"; -- select jtag_read_ram1a_a - ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b - trigger_jtag_read_next <= '1';-- temporarily go on (for testing without mimosa26 emulator) - begin_count_read_errors_next <= '1'; -- added 201210 - m26cs_state_next <= M26CSS_READ1_BEGIN; -- temporarily go on (for testing without mimosa26 emulator) - else - ram2_select_next <= '0'; -- tdo_compare_count - ram1a_select_next <= "00"; -- select jtag_read_ram1a_a - ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b - trigger_jtag_read_next <= '1'; - begin_count_read_errors_next <= '1'; -- added 201210 - m26cs_state_next <= M26CSS_READ1_BEGIN; - end if; - end if; - end if; - when M26CSS_READ1_BEGIN => - m26cs_state_next <= M26CSS_READ1_WAIT; - when M26CSS_READ1_WAIT => - if(jtag_read_idle = '1') then -- removed (jtag_read_last_tck_cycle = '1' or ) because writing to RAM needs time - end_count_read_errors_next <= '1'; -- added 201210 - if(breakpoint_active(4) = '1') then - --stay in state - --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT; - else - trigger_juec_update_rd_err_next <= '1'; - ram2_select_next <= '1'; -- juec - ram3a_select_next <= '0'; -- juec - m26cs_state_next <= M26CSS_JUEC_READ_BEGIN; - end if; - end if; - when M26CSS_JUEC_READ_BEGIN => - m26cs_state_next <= M26CSS_JUEC_READ_WAIT; - when M26CSS_JUEC_READ_WAIT => - if(juec_idle = '1') then - if(breakpoint_active(5) = '1') then - --stay in state - --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT; - elsif(jtag_check1_active = '1') then - -- in case of check1 set, don't write registers - -- in order to save time - -- clear requests - run_requested_next <= '0'; - write_once_requested_next <= '0'; - m26cs_state_next <= M26CSS_STOPPED; - else - -- do the following later! - --trigger_jtag_write_next <= '1'; - --ram1a_select_next <= "01"; -- select jtag_write_ram1a_a - --ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b - --ram2_select_next <= '0'; -- tdo_compare_count - m26cs_state_next <= M26CSS_REQUEST_RESET_BEGIN; - end if; - end if; - when M26CSS_REQUEST_RESET_BEGIN => - request_reset_next <= '1'; - m26cs_state_next <= M26CSS_REQUEST_RESET_WAIT; - when M26CSS_REQUEST_RESET_WAIT => - request_reset_next <= '0'; - reset_wait_next <= RESET_WAIT_DURATION; - m26cs_state_next <= M26CSS_REQUESTED_RESET_WAIT; - when M26CSS_REQUESTED_RESET_WAIT => - reset_wait_next <= reset_wait - 1; - request_reset_next <= '0'; - if(reset_wait = reset_wait_zero) then - trigger_jtag_write_next <= '1'; - ram1a_select_next <= "01"; -- select jtag_write_ram1a_a - if(ram1b_copy_requested = '0') then -- this is a hack, to only change ram1b if not yet data changed triggered copy request - ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b - else - ram1b_select_next <= '0'; - end if; - ram2_select_next <= '0'; -- tdo_compare_count - m26cs_state_next <= M26CSS_WRITE1_BEGIN; - end if; - when M26CSS_WRITE1_BEGIN => - m26cs_state_next <= M26CSS_WRITE1_WAIT; - when M26CSS_WRITE1_WAIT => - if(jtag_write_idle = '1') then - if(breakpoint_active(6) = '1') then - --stay in state - --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT; - else - trigger_jtag_write_next <= '1'; - begin_count_write_errors_next <= '1'; -- added 201210 - m26cs_state_next <= M26CSS_WRITE2_BEGIN; - end if; - end if; - when M26CSS_WRITE2_BEGIN => - m26cs_state_next <= M26CSS_WRITE2_WAIT; - when M26CSS_WRITE2_WAIT => - if(jtag_write_idle = '1') then - end_count_write_errors_next <= '1'; -- added 201210 - if(breakpoint_active(7) = '1') then - --stay in state - --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT; - else - prog_jtag_finished_next <= '1'; - trigger_juec_update_wr_err_next <= '1'; - ram2_select_next <= '1'; -- juec - ram3a_select_next <= '0'; -- juec - m26cs_state_next <= M26CSS_JUEC_WRITE_BEGIN; - end if; - end if; - when M26CSS_JUEC_WRITE_BEGIN => - m26cs_state_next <= M26CSS_JUEC_WRITE_WAIT; - when M26CSS_JUEC_WRITE_WAIT => - if(juec_idle = '1') then - if(breakpoint_active(8) = '1') then - --stay in state - --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT; - else - trigger_juec_update_run_counter_next <= '1'; - m26cs_state_next <= M26CSS_JUEC_RUN_COUNTER_BEGIN; - end if; - end if; - when M26CSS_JUEC_RUN_COUNTER_BEGIN => - m26cs_state_next <= M26CSS_JUEC_RUN_COUNTER_WAIT; - when M26CSS_JUEC_RUN_COUNTER_WAIT => - if(juec_idle = '1') then - if(breakpoint_active(9) = '1') then - --stay in state - --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT; - else - m26cs_firstrun_next <= '0'; - last_run_successful_tmp_next <= not (last_read_error or last_write_error); -- added 201210 - -- clear requests - run_requested_next <= '0'; - write_once_requested_next <= '0'; - m26cs_state_next <= M26CSS_WAIT_FOR_TRIGGER; - end if; - end if; - - - -- WRITE_ONCE states - when M26CSS_WRITEONCE_CHECK_CRC_RAM1A_BEGIN => - m26cs_state_next <= M26CSS_WRITEONCE_CHECK_CRC_RAM1A_WAIT; - when M26CSS_WRITEONCE_CHECK_CRC_RAM1A_WAIT => - if(jtag_check_crc_ram1a_idle = '1') then - crc_status_register_next <= jtag_check_crc_ram1a_crc_ok; - output := '1'; - for i in MAX_NUMCHIPS-1 downto 0 loop - if(jtag_check_crc_ram1a_crc_ok(i) /= '1' and i < to_integer(numchips_configured)) then - output := '0'; - end if; - end loop; - --if(std_logic_vector_all_components_equal_scalar(jtag_check_crc_ram1a_crc_ok(to_integer(numchips_configured)-1 downto 0), '1') = '1') then - if(output = '1') then - -- if no crc errors for configured chips (consider changing this to checking the whole vector, and also let zeros be ok for crc check) - crc_error_on_last_check_next <= '0'; - trigger_init_ram1b_next <= '1'; - ram1b_select_next <= '0'; -- select init ram1b - ram1a_select_next <= "10"; -- select init ram1b - m26cs_state_next <= M26CSS_WRITEONCE_INIT_RAM1B_BEGIN; - else - -- crc error in configured chips, don't continue - crc_error_on_last_check_next <= '1'; - run_requested_next <= '0'; - write_once_requested_next <= '0'; - m26cs_state_next <= M26CSS_WAIT_FOR_TRIGGER; - end if; - end if; - when M26CSS_WRITEONCE_INIT_RAM1B_BEGIN => - m26cs_state_next <= M26CSS_WRITEONCE_INIT_RAM1B_WAIT; - when M26CSS_WRITEONCE_INIT_RAM1B_WAIT => - if(jtag_init_ram1b_idle = '1') then - chip_counter_start_next <= '1'; - m26cs_state_next <= M26CSS_WRITEONCE_COUNT_CHIPS_BEGIN; - end if; - when M26CSS_WRITEONCE_COUNT_CHIPS_BEGIN => - m26cs_state_next <= M26CSS_WRITEONCE_COUNT_CHIPS_WAIT; - when M26CSS_WRITEONCE_COUNT_CHIPS_WAIT => - trigger_jtag_write_next <= '1'; - ram1a_select_next <= "01"; -- select jtag_write_ram1a_a - ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b - ram2_select_next <= '0'; -- tdo_compare_count - m26cs_state_next <= M26CSS_WRITEONCE_WRITE1_BEGIN; - when M26CSS_WRITEONCE_WRITE1_BEGIN => - m26cs_state_next <= M26CSS_WRITEONCE_WRITE1_WAIT; - when M26CSS_WRITEONCE_WRITE1_WAIT => - if(jtag_write_idle = '1') then - -- clear requests - run_requested_next <= '0'; - write_once_requested_next <= '0'; - write_once_count_next <= write_once_count + 1; - m26cs_state_next <= M26CSS_WAIT_FOR_TRIGGER; - end if; - end case; - if(RUN_REQUEST_IN = '1') then - run_requested_next <= '1'; - end if; - if(WRITE_ONCE_REQUEST_IN = '1') then - write_once_requested_next <= '1'; - end if; - -end process; - - -status2_copy_finished <= not jtag_status2_copy_requested and not jtag_status2_copy_request_strobe; -CP_STATUS2 : process(jtag_status2_copy_requested, jtag_status2_copy_request_strobe, status2_chain_status, - status2_run_counter, cps2_state, m26cs_state, jtag_copy_ram3_idle, run_counter, chain_status) -begin - jtag_status2_copy_requested_next <= jtag_status2_copy_requested; - -- these are all copies of the registers changed in M26CS - status2_run_counter_next <= status2_run_counter; - status2_chain_status_next <= status2_chain_status; - cps2_state_next <= cps2_state; - trigger_copy_ram3_next <= '0'; - case cps2_state is - when CPS2_IDLE => - if(jtag_status2_copy_requested = '1' and m26cs_state = M26CSS_STOPPED) then - trigger_copy_ram3_next <= '1'; - cps2_state_next <= CPS2_COPY_BEGIN; - end if; - when CPS2_COPY_BEGIN => - status2_run_counter_next <= run_counter; - status2_chain_status_next <= chain_status; - cps2_state_next <= CPS2_COPY_WAIT; - when CPS2_COPY_WAIT => - if(jtag_copy_ram3_idle = '1') then - jtag_status2_copy_requested_next <= '0'; - cps2_state_next <= CPS2_IDLE; - end if; - end case; --finishing needs 2 clock cycles, after 2 clock cycles the next jtag_status2_copy_request_strobe - -- will be accepted. the copying itself needs much longer, so if the querying agent waits till - -- after the copy has finished until the next is requested, the new request not be missed due to this delay - if(jtag_status2_copy_request_strobe = '1') then - jtag_status2_copy_requested_next <= '1'; - end if; -end process; - ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ - - -TRIGGER_CP_RAM1B1C : process begin - wait until rising_edge(CLK_IN); - -- these are all copies of the registers changed in M26CS - trigger_copy_ram1b1c <= '0'; - ram1b1c_copy_trigger_active <= ram1b1c_copy_trigger_active or ram1b1c_copy_trigger_strobe; - case cpr1bc_state is - when CPR1BC_IDLE => - if(ram1b_copy_requested = '1' and m26cs_state = M26CSS_STOPPED) then - trigger_copy_ram1b1c <= '1'; - cpr1bc_state <= CPR1BC_COPY_BEGIN; - end if; - when CPR1BC_COPY_BEGIN => - ram1c_run_counter <= run_counter; - ram1c_chain_status <= chain_status; - cpr1bc_state <= CPR1BC_COPY_WAIT; - when CPR1BC_COPY_WAIT => - if(copy_ram1b1c_idle = '1') then - ram1b_copy_requested <= '0'; - cpr1bc_state <= CPR1BC_IDLE; - end if; - end case; --finishing needs 2 clock cycles, after 2 clock cycles the next jtag_status2_copy_request_strobe - -- will be accepted. the copying itself needs much longer, so if the querying agent waits till - -- after the copy has finished until the next is requested, the new request not be missed due to this delay - if(juec_read_errors = '1' and ram1b1c_copy_trigger_active(0) = '1') or - (juec_write_errors = '1' and ram1b1c_copy_trigger_active(1) = '1') or - (juec_data_changed = '1' and ram1b1c_copy_trigger_active(2) = '1') or - (ram1b1c_copy_trigger_active(3) = '1') then - ram1b_copy_requested <= '1'; - ram1b1c_copy_trigger_active <= (others => '0'); - end if; - if RESET_IN = '1' then - cpr1bc_state <= CPR1BC_IDLE; - end if; -end process; - - - -BUS2_RAM_RW : process begin - wait until rising_edge(CLK_IN); - bus2_ram_ack_in <= '0'; - bus2_ram_nack_in <= '0'; - ram1a_wr1 <= '0'; - ram1a_read_delay <= '0'; - ram1a_read_delay2 <= ram1a_read_delay; - - if(bus2_ram_write_enable_out='1') then - ram1a_din1 <= bus2_ram_data_out; - ram1a_a1_rel_addr <= bus2_ram_addr_out(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0); - -- only allow ram1a to be changed if stopped! - if(m26cs_stopped = '1') then - ram1a_wr1 <= '1'; - bus2_ram_ack_in <= '1'; - else - bus2_ram_nack_in <= '1'; - end if; - elsif(bus2_ram_read_enable_out='1') then - ram1a_a1_rel_addr <= bus2_ram_addr_out(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0); - ram1a_read_delay <= '1'; - - elsif(ram1a_read_delay2 = '1') then - bus2_ram_data_in <= ram1a_dout1; - bus2_ram_ack_in <= '1'; - end if; -end process; - - -BUS2_COMMAND_RW : process begin - wait until rising_edge(CLK_IN); - bus_command_ack <= '0'; - bus_command_nack <= '0'; - bus_command_retry <= '0'; - bus_command_data_in <= (others => '0'); - jtag_pulses_reset <= '0'; - jtag_status2_copy_request_strobe <= '0'; - ram1b1c_copy_trigger_strobe <= (others => '0'); - - if bus_command_read = '1' then - bus_command_ack <= '1'; - case bus_command_addr(7 downto 0) is - when M26C_CMD_START => - bus_command_data_in(0) <= jtag_refresh_active; - bus_command_data_in(1) <= jtag_check1_active; - when M26C_CMD_REMOVE_SENSOR => - bus_command_data_in(MAX_NUMCHIPS -1 downto 0) <= removed_chips; - when M26C_CMD_SET_NUMCHIPS_CONFIGURED => - bus_command_data_in(MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(numchips_configured); - when M26C_CMD_GET_NUMCHIPS_ACTIVE => - bus_command_data_in(MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(numchips_active); - when M26C_CMD_GET_TRIGGER_COUNT => - bus_command_data_in <= std_logic_vector(debug_trigger_counter); - when M26C_CMD_GET_LAST_NOT_REMOVED => - bus_command_data_in(MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(last_not_removed); - when M26C_CMD_SET_BREAKPOINTS => - bus_command_data_in(9 downto 0) <= breakpoint_active; - when M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH => - bus_command_data_in(9 downto 0) <= std_logic_vector(jtag_clock_cycle_length); - when M26C_CMD_SET_JTAG_CLOCK_TIME1 => - bus_command_data_in(9 downto 0) <= std_logic_vector(jtag_clock_time1); - when M26C_CMD_SET_JTAG_CLOCK_TIME2 => - bus_command_data_in(9 downto 0) <= std_logic_vector(jtag_clock_time2); - when M26C_CMD_SET_JTAG_SAMPLE_TIME1 => - bus_command_data_in(9 downto 0) <= std_logic_vector(jtag_sample_time1); - when M26C_CMD_SET_JTAG_SAMPLE_TIME2 => - bus_command_data_in(9 downto 0) <= std_logic_vector(jtag_sample_time2); - when M26C_CMD_SET_JTAG_SAMPLE_TIME3 => - bus_command_data_in(9 downto 0) <= std_logic_vector(jtag_sample_time3); - when M26C_CMD_SET_JTAG_SET_DATA_TIME => - bus_command_data_in(9 downto 0) <= std_logic_vector(jtag_set_data_time); - when M26C_CMD_GET_RUN_COUNT => - bus_command_data_in(31 downto 0) <= std_logic_vector(run_counter); - when M26C_CMD_GET_CRC_STATUS => - bus_command_data_in(MAX_NUMCHIPS - 1 downto 0) <= crc_status_register(MAX_NUMCHIPS - 1 downto 0); - when M26C_CMD_SET_RAMBASE => - bus_command_data_in(MAX_NUMCHIPS_LD-1 downto 0) <= ram1a_a1_base_addr; - when M26C_CMD_GET_M26CS_STATE => - bus_command_data_in(7 downto 0) <= debug_m26cs_state; - when M26C_CMD_GET_RAM1C_RUN_COUNTER => - bus_command_data_in <= std_logic_vector(ram1c_run_counter); - when M26C_CMD_GET_RAM1C_CHAIN_STATUS => - bus_command_data_in(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0) <= ram1c_chain_status; - when M26C_CMD_GET_RAM3B_RUN_COUNTER => - bus_command_data_in <= std_logic_vector(status2_run_counter); - when M26C_CMD_GET_RAM3B_CHAIN_STATUS => - bus_command_data_in(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0) <= status2_chain_status; - when M26C_CMD_SET_CSOPTIONS => - bus_command_data_in(0 downto 0) <= m26csoptions(0 downto 0); -- bit 0 => skip bypassreg chaintest - when M26C_CMD_SET_DELAY_EXPECTED_VALUES => - bus_command_data_in(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0) <= jtag_delay_expvalues; - when others => - bus_command_ack <= '0'; - bus_command_nack <= '1'; - end case; - - - elsif bus_command_write = '1' then - bus_command_ack <= '1'; - case bus_command_addr(7 downto 0) is - when M26C_CMD_START => - jtag_refresh_active <= bus_command_data_out(0); - jtag_check1_active <= bus_command_data_out(1); - when M26C_CMD_REMOVE_SENSOR => - if m26cs_stopped = '1' then - if(unsigned(bus_command_data_out(15 downto 0)) - numchips_configured <= unsigned(bus_command_data_out(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0)); - when M26C_CMD_SET_BREAKPOINTS => - breakpoint_active <= bus_command_data_out(9 downto 0); - when M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH => - jtag_clock_cycle_length <= unsigned(bus_command_data_out(9 downto 0)); - jtag_pulses_reset <= '1'; -- reset counter (because maximum value of counter could be exceeded) - when M26C_CMD_SET_JTAG_CLOCK_TIME1 => - jtag_clock_time1 <= unsigned(bus_command_data_out(9 downto 0)); - when M26C_CMD_SET_JTAG_CLOCK_TIME2 => - jtag_clock_time2 <= unsigned(bus_command_data_out(9 downto 0)); - when M26C_CMD_SET_JTAG_SAMPLE_TIME1 => - jtag_sample_time1 <= unsigned(bus_command_data_out(9 downto 0)); - when M26C_CMD_SET_JTAG_SAMPLE_TIME2 => - jtag_sample_time2 <= unsigned(bus_command_data_out(9 downto 0)); - when M26C_CMD_SET_JTAG_SAMPLE_TIME3 => - jtag_sample_time3 <= unsigned(bus_command_data_out(9 downto 0)); - when M26C_CMD_SET_JTAG_SET_DATA_TIME => - jtag_set_data_time <= unsigned(bus_command_data_out(9 downto 0)); - when M26C_CMD_COPY_TO_STATUS2 => - jtag_status2_copy_request_strobe <= '1'; - when M26C_CMD_SET_RAMBASE => - ram1a_a1_base_addr <= bus_command_data_out(MAX_NUMCHIPS_LD-1 downto 0); - when M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER => - ram1b1c_copy_trigger_strobe(3 downto 0) <= bus_command_data_out(3 downto 0); - -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed, 3=>next run - when M26C_CMD_SET_CSOPTIONS => - m26csoptions(0 downto 0) <= bus_command_data_out(0 downto 0); -- bit 0 => skip bypassreg chaintest - when M26C_CMD_SET_DELAY_EXPECTED_VALUES => - jtag_delay_expvalues <= bus_command_data_out(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0); - when others => - bus_command_ack <= '0'; - bus_command_nack <= '1'; - end case; - end if; - if RESET_IN = '1' then - jtag_refresh_active <= '0'; - jtag_check1_active <= '0'; - breakpoint_active <= (others => '0'); - numchips_configured <= (others => '0'); - m26csoptions <= (others => '0'); - end if; -end process; - - - -PROC_READ_1C : process begin - wait until rising_edge(CLK_IN); - bus_ram1c_ack <= '0'; - bus_ram1c_nack <= '0'; - bus_ram1c_unkwn <= '0'; - bus_ram1c_ack_next <= '0'; - bus_ram1c_ack_next2 <= '0'; - - if bus_ram1c_read = '1' then - if status2_copy_finished = '1' then - bus_ram1c_ack_next<= '1'; - ram1c_a2 <= ram1a_a1_base_addr & bus_ram1c_addr(7 downto 0); - else - bus_ram1c_nack <= '1'; - end if; - elsif bus_ram1c_write = '1' then - bus_ram1c_unkwn <= '1'; - elsif bus_ram1c_ack_next = '1' then - bus_ram1c_ack_next2 <= '1'; - elsif bus_ram1c_ack_next2 = '1' then - bus_ram1c_data_in <= ram1c_dout2; - bus_ram1c_ack <= '1'; - end if; -end process; - - - -PROC_READ_3B : process begin - wait until rising_edge(CLK_IN); - bus_ram3b_ack <= '0'; - bus_ram3b_nack <= '0'; - bus_ram3b_unkwn <= '0'; - bus_ram3b_ack_next <= '0'; - bus_ram3b_ack_next2 <= '0'; - - if bus_ram3b_read = '1' then - if status2_copy_finished = '1' then - bus_ram3b_ack_next<= '1'; - ram3b_a2 <= '0' & bus_ram3b_addr(7 downto 0); - else - bus_ram3b_nack <= '1'; - end if; - elsif bus_ram3b_write = '1' then - bus_ram3b_unkwn <= '1'; - elsif bus_ram3b_ack_next = '1' then - bus_ram3b_ack_next2 <= '1'; - elsif bus_ram3b_ack_next2 = '1' then - bus_ram3b_data_in <= ram3b_dout2; - bus_ram3b_ack <= '1'; - end if; -end process; - - - -debug_m26cs_state_process : process begin - wait until rising_edge(CLK_IN); - case m26cs_state is - when M26CSS_WAIT_FOR_TRIGGER => debug_m26cs_state <= x"00"; - when M26CSS_CHECK_CRC_RAM1A_BEGIN => debug_m26cs_state <= x"20"; - when M26CSS_CHECK_CRC_RAM1A_WAIT => debug_m26cs_state <= x"21"; - when M26CSS_INIT_RAM1B_BEGIN => debug_m26cs_state <= x"22"; - when M26CSS_INIT_RAM1B_WAIT => debug_m26cs_state <= x"23"; - when M26CSS_DATA_CHANGED_BEGIN => debug_m26cs_state <= x"01"; - when M26CSS_DATA_CHANGED_WAIT => debug_m26cs_state <= x"02"; - when M26CSS_BLANK_RAM3A_WAIT => debug_m26cs_state <= x"24"; - when M26CSS_JUEC_DATA_CHANGED_BEGIN => debug_m26cs_state <= x"03"; - when M26CSS_JUEC_DATA_CHANGED_WAIT => debug_m26cs_state <= x"04"; - when M26CSS_COUNT_CHIPS_BEGIN => debug_m26cs_state <= x"05"; - when M26CSS_COUNT_CHIPS_WAIT => debug_m26cs_state <= x"06"; - when M26CSS_BYPASSREG_BEGIN => debug_m26cs_state <= x"07"; - when M26CSS_BYPASSREG_WAIT => debug_m26cs_state <= x"08"; - when M26CSS_READ1_BEGIN => debug_m26cs_state <= x"09"; - when M26CSS_READ1_WAIT => debug_m26cs_state <= x"0a"; - when M26CSS_JUEC_READ_BEGIN => debug_m26cs_state <= x"0b"; - when M26CSS_JUEC_READ_WAIT => debug_m26cs_state <= x"0c"; - when M26CSS_WRITE1_BEGIN => debug_m26cs_state <= x"0d"; - when M26CSS_WRITE1_WAIT => debug_m26cs_state <= x"0e"; - when M26CSS_WRITE2_BEGIN => debug_m26cs_state <= x"0f"; - when M26CSS_WRITE2_WAIT => debug_m26cs_state <= x"10"; - when M26CSS_JUEC_WRITE_BEGIN => debug_m26cs_state <= x"11"; - when M26CSS_JUEC_WRITE_WAIT => debug_m26cs_state <= x"12"; - when M26CSS_CHECK1_WAIT_FOR_HAVE_TIME => debug_m26cs_state <= x"13"; - when M26CSS_STOPPED => debug_m26cs_state <= x"14"; - when M26CSS_JUEC_RUN_COUNTER_BEGIN => debug_m26cs_state <= x"15"; - when M26CSS_JUEC_RUN_COUNTER_WAIT => debug_m26cs_state <= x"16"; - when M26CSS_REQUEST_RESET_BEGIN => debug_m26cs_state <= x"17"; - when M26CSS_REQUEST_RESET_WAIT => debug_m26cs_state <= x"18"; - when M26CSS_REQUESTED_RESET_WAIT => debug_m26cs_state <= x"19"; - when M26CSS_WRITEONCE_CHECK_CRC_RAM1A_BEGIN => debug_m26cs_state <= x"1a"; - when M26CSS_WRITEONCE_CHECK_CRC_RAM1A_WAIT => debug_m26cs_state <= x"1b"; - when M26CSS_WRITEONCE_INIT_RAM1B_BEGIN => debug_m26cs_state <= x"1c"; - when M26CSS_WRITEONCE_INIT_RAM1B_WAIT => debug_m26cs_state <= x"1d"; - when M26CSS_WRITEONCE_COUNT_CHIPS_BEGIN => debug_m26cs_state <= x"1e"; - when M26CSS_WRITEONCE_COUNT_CHIPS_WAIT => debug_m26cs_state <= x"1f"; - when M26CSS_WRITEONCE_WRITE1_BEGIN => debug_m26cs_state <= x"25"; - when M26CSS_WRITEONCE_WRITE1_WAIT => debug_m26cs_state <= x"26"; - end case; -end process; - - -IDLE_OUT <= idle_out_signal; - - --- ALL_debugtdo : process( CLK_IN) --- begin --- if(rising_edge(CLK_IN)) then --- if(RESET_IN= '1') then --- debugtdo_counter <= (others => '0'); --- debugtdo_active <= '0'; --- debugtdo_ran <= '0'; --- else --- -- COUNTER --- debugtdo_counter <= std_logic_vector(unsigned(debugtdo_counter) + 1); --- -- reset counter in idle/stopped states => counter times the elapsed time since start of m26cs state machine --- -- also clear debugtdo_active --- if(m26cs_state = M26CSS_WAIT_FOR_TRIGGER or m26cs_state = M26CSS_STOPPED) then --- debugtdo_counter <= (others => '0'); --- if(debugtdo_ran = '1') then --- debugtdo_active <= '0'; --- end if; --- debugtdo_ran <= '0'; --- else --- debugtdo_ran <= '1'; --- end if; --- if(debugtdo_activate_strobe = '1') then --- debugtdo_active <= '1'; --- end if; --- end if; --- end if; --- end process; -end architecture; diff --git a/vhdl/code/jtag_constants.vhd b/vhdl/code/jtag_constants.vhd deleted file mode 100644 index 03805eb..0000000 --- a/vhdl/code/jtag_constants.vhd +++ /dev/null @@ -1,103 +0,0 @@ -library ieee; -USE IEEE.std_logic_1164.ALL; -use ieee.numeric_std.all; - -package jtag_constants is - -constant CMD_NONE : std_logic_vector (3 downto 0) := x"0"; -constant CMD_SELECT_DR : std_logic_vector (3 downto 0) := x"1"; -constant CMD_SELECT_IR : std_logic_vector (3 downto 0) := x"2"; -constant CMD_SHIFT_DR : std_logic_vector (3 downto 0) := x"3"; -constant CMD_SHIFT_IR : std_logic_vector (3 downto 0) := x"4"; -constant CMD_UPDATE_IR : std_logic_vector (3 downto 0) := x"5"; -constant CMD_UPDATE_DR : std_logic_vector (3 downto 0) := x"6"; -constant CMD_RESET_JTAG : std_logic_vector (3 downto 0) := x"7"; -constant CMD_READ_TDO : std_logic_vector (3 downto 0) := x"8"; - -constant M26C_CMD_SET_NUMCHIPS_CONFIGURED : std_logic_vector (7 downto 0) := x"00"; -constant M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH : std_logic_vector (7 downto 0) := x"01"; -constant M26C_CMD_SET_JTAG_CLOCK_TIME1 : std_logic_vector (7 downto 0) := x"02"; -constant M26C_CMD_SET_JTAG_CLOCK_TIME2 : std_logic_vector (7 downto 0) := x"03"; -constant M26C_CMD_SET_JTAG_SAMPLE_TIME1 : std_logic_vector (7 downto 0) := x"04"; -constant M26C_CMD_SET_JTAG_SAMPLE_TIME2 : std_logic_vector (7 downto 0) := x"05"; -constant M26C_CMD_SET_JTAG_SAMPLE_TIME3 : std_logic_vector (7 downto 0) := x"06"; -constant M26C_CMD_SET_JTAG_SET_DATA_TIME : std_logic_vector (7 downto 0) := x"07"; -constant M26C_CMD_SET_DELAY_EXPECTED_VALUES : std_logic_vector (7 downto 0) := x"08"; -- bits 1 downto 0 as unsigned number of TCK clocks expected values are delayed -constant M26C_CMD_GET_RUN_COUNT : std_logic_vector (7 downto 0) := x"10"; -constant M26C_CMD_GET_NUMCHIPS_ACTIVE : std_logic_vector (7 downto 0) := x"11"; -constant M26C_CMD_GET_TRIGGER_COUNT : std_logic_vector (7 downto 0) := x"12"; -constant M26C_CMD_GET_LAST_NOT_REMOVED : std_logic_vector (7 downto 0) := x"13"; -constant M26C_CMD_GET_CRC_STATUS : std_logic_vector (7 downto 0) := x"14"; -constant M26C_CMD_START : std_logic_vector (7 downto 0) := x"40"; -constant M26C_CMD_REMOVE_SENSOR : std_logic_vector (7 downto 0) := x"41"; -constant M26C_CMD_SET_CSOPTIONS : std_logic_vector (7 downto 0) := x"42"; -- bit 0 => skip BYPASS CHAINTEST -constant M26C_CMD_SET_RAMBASE : std_logic_vector (7 downto 0) := x"43"; -- bit 0 => skip BYPASS CHAINTEST -constant M26C_CMD_SET_BREAKPOINTS : std_logic_vector (7 downto 0) := x"50"; -constant M26C_CMD_COPY_TO_STATUS2 : std_logic_vector (7 downto 0) := x"51"; -constant M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER : std_logic_vector (7 downto 0) := x"52"; -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed -constant M26C_CMD_GET_M26CS_STATE : std_logic_vector (7 downto 0) := x"53"; -constant M26C_CMD_GET_RAM1C_RUN_COUNTER : std_logic_vector (7 downto 0) := x"54"; -constant M26C_CMD_GET_RAM1C_CHAIN_STATUS : std_logic_vector (7 downto 0) := x"55"; -constant M26C_CMD_GET_RAM3B_RUN_COUNTER : std_logic_vector (7 downto 0) := x"56"; -constant M26C_CMD_GET_RAM3B_CHAIN_STATUS : std_logic_vector (7 downto 0) := x"57"; - --- 0xb100 - 0xb2ff --- RAM: 0xb000 - 0xb0ff --- Status registers: 0xb100 - 0xb11f --- Control registers: 0xb120 - 0xb13f --- Debug registers: 0xb140 - 0xb15f -constant ADDR_RAM : std_logic_vector (15 downto 0) := x"b000"; -constant ADDR_STATUS : std_logic_vector (15 downto 0) := x"b100"; -constant ADDR_CONTROL : std_logic_vector (15 downto 0) := x"b120"; -constant ADDR_DEBUG : std_logic_vector (15 downto 0) := x"b140"; -constant ADDR_STATUS2 : std_logic_vector (15 downto 0) := x"b160"; - --- constant ADDR_CONTROL_CMD : std_logic_vector (4 downto 0) := "00000"; -constant ADDR_CONTROL_RAM_BASEADDR : std_logic_vector (4 downto 0) := "00001"; --- constant ADDR_CONTROL_DATA_REGISTER : std_logic_vector (4 downto 0) := "00010"; - -constant ADDR_DEBUG_TEST : std_logic_vector(4 downto 0) := "00000"; -constant ADDR_DEBUG_M26CS_STATE : std_logic_vector(4 downto 0) := "00001"; -constant ADDR_DEBUG_M26C_READ_STATE : std_logic_vector(4 downto 0) := "00010"; -constant ADDR_DEBUG_M26C_WRITE_STATE : std_logic_vector(4 downto 0) := "00011"; -constant ADDR_DEBUG_JTAG_DRIVER_STATE : std_logic_vector(4 downto 0) := "00100"; -constant ADDR_DEBUG_TRIGGER_COUNT : std_logic_vector(4 downto 0) := "00101"; -constant ADDR_DEBUG_VERSION : std_logic_vector(4 downto 0) := "00110"; -constant ADDR_DEBUG_RAM1BADDR : std_logic_vector(4 downto 0) := "00111"; -constant ADDR_DEBUG_RAM1B_DATA : std_logic_vector(4 downto 0) := "01000"; -constant ADDR_DEBUG_RAM1CADDR : std_logic_vector(4 downto 0) := "01001"; -constant ADDR_DEBUG_RAM1C_DATA : std_logic_vector(4 downto 0) := "01010"; -constant ADDR_DEBUG_RAM1C_RUN_COUNTER : std_logic_vector(4 downto 0) := "01011"; -constant ADDR_DEBUG_RAM1C_CHAIN_STATUS : std_logic_vector(4 downto 0) := "01100"; -constant ADDR_DEBUG_DEBUGTDO_SAMPLES : std_logic_vector(4 downto 0) := "01101"; -constant ADDR_DEBUG_DEBUGTDO_GETFIFOSTATUS : std_logic_vector(4 downto 0) := "01110"; -constant ADDR_DEBUG_DEBUGTDO_TIMEOUT : std_logic_vector(4 downto 0) := "01111"; -constant ADDR_DEBUG_DEBUGTDO_ACTIVATE : std_logic_vector(4 downto 0) := "10000"; -constant ADDR_DEBUG_DEBUGTDO_CONTROLFIFO : std_logic_vector(4 downto 0) := "10001"; -constant ADDR_DEBUG_WRONCE_COUNT : std_logic_vector(4 downto 0) := "10010"; - - -constant ADDR_STATUS_VERSION : std_logic_vector(4 downto 0) := "00110"; - -constant ADDR_STATUS2_TRIGGERCOUNTER_COPY : std_logic_vector(4 downto 0) := "00000"; -constant ADDR_STATUS2_CHAIN_STATUS_COPY : std_logic_vector(4 downto 0) := "00001"; -constant ADDR_STATUS2_UPDATING : std_logic_vector(4 downto 0) := "00010"; -constant ADDR_STATUS2_RAM3B_BASEADDR : std_logic_vector(4 downto 0) := "00011"; -constant ADDR_STATUS2_STARTED : std_logic_vector(4 downto 0) := "00100"; -constant ADDR_STATUS2_RAM3B_BEGIN : std_logic_vector(4 downto 0) := "10000"; -- lower 4 bits used as address into ram3b from baseaddr - - - ---constant ADDR_DATA : std_logic_vector (8 downto 0) := "000000001"; ---constant ADDR_LENGTH : std_logic_vector (8 downto 0) := "000000010"; - - -constant STATUS_OK : std_logic_vector (15 downto 0) := x"0000"; -constant STATUS_INVALID_COMMAND : std_logic_vector (15 downto 0) := x"FFFF"; - --- constraint: MAX_NUMCHIPS can be at most 2**MAX_NUMCHIPS_LD --- if MAX_NUMCHIPS is 2^n-1 then the number of chips can be stored in n bits, thats the reason to choose this odd max. number - -constant COUNTER_WIDTHS : integer := 16; -- width of counters for jtag_cmd_m26c entity port, must be static. - -end package jtag_constants; diff --git a/vhdl/code/jtag_delay_expected_values.vhd b/vhdl/code/jtag_delay_expected_values.vhd deleted file mode 100755 index b818647..0000000 --- a/vhdl/code/jtag_delay_expected_values.vhd +++ /dev/null @@ -1,121 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; - -library work; -use work.jtag_constants.all; - -entity jtag_delay_expected_values is - generic ( --- delay : integer := 0 -- number of whole jtag clock cycles to delay the expected values --- -- because of total distance of the tck-line to the last chip and --- -- the length of tdo of this chip back to the fpga - ld_maxdelay : integer := 2; -- floor of ld maxdelay - MAX_NUMCHIPS_LD : integer; - MAX_REGISTERS_PLUS_ONE_LD : integer - ); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - SAMPLE_PULSE1_IN : in std_logic; - - -- chipcount as unsigned - CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD -1 downto 0); - -- active register as unsigned, =register 1,2,... of jtag_write_m10 or 0 for jtag_read_m10 - REGNUM_IN : in std_logic_vector(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0); - - IS_DR_BIT_IN : in std_logic; - -- firstbit signal: reset counters before sampling this bit - IS_FIRSTBIT_IN : in std_logic; - -- finish signal: dataout => RAM1b, compareout => RAM2 - IS_LASTBIT_IN : in std_logic; - - TDO_EXPECTED_IN : in std_logic; - - - -- chipcount as unsigned - OUT_CHIPNUM_OUT : out std_logic_vector(MAX_NUMCHIPS_LD -1 downto 0); - -- active register as unsigned, =register 1,2,... of jtag_write_m10 or 0 for jtag_read_m10 - OUT_REGNUM_OUT : out std_logic_vector(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0); - - OUT_IS_DR_BIT_OUT : out std_logic; - -- firstbit signal: reset counters before sampling this bit - OUT_IS_FIRSTBIT_OUT : out std_logic; - -- finish signal: dataout => RAM1b, compareout => RAM2 - OUT_IS_LASTBIT_OUT : out std_logic; - - OUT_TDO_EXPECTED_OUT : out std_logic; - - DELAY_IN : in std_logic_vector(ld_maxdelay-1 downto 0) - - - - ); -end entity; -architecture jtag_delay_expected_values_arch of jtag_delay_expected_values is -type REGNUM_BUF_TYPE is array (2**ld_maxdelay-1 downto 0) of std_logic_vector(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0); - signal regnum_buf, regnum_buf_next : REGNUM_BUF_TYPE; -type CHIPNUM_BUF_TYPE is array (2**ld_maxdelay-1 downto 0) of std_logic_vector(MAX_NUMCHIPS_LD -1 downto 0); - signal chipnum_buf, chipnum_buf_next : CHIPNUM_BUF_TYPE; -type STD_LOGIC_BUF_TYPE is array (2**ld_maxdelay-1 downto 0) of std_logic; - signal is_dr_bit_buf, is_dr_bit_buf_next : STD_LOGIC_BUF_TYPE; - signal is_firstbit_buf, is_firstbit_buf_next : STD_LOGIC_BUF_TYPE; - signal is_lastbit_buf, is_lastbit_buf_next : STD_LOGIC_BUF_TYPE; - signal tdo_expected_buf, tdo_expected_buf_next : STD_LOGIC_BUF_TYPE; -begin -OUT_CHIPNUM_OUT <= chipnum_buf(to_integer(unsigned(DELAY_IN))); -OUT_REGNUM_OUT <= regnum_buf(to_integer(unsigned(DELAY_IN))); -OUT_IS_DR_BIT_OUT <= is_dr_bit_buf(to_integer(unsigned(DELAY_IN))); -OUT_IS_FIRSTBIT_OUT <= is_firstbit_buf(to_integer(unsigned(DELAY_IN))); -OUT_IS_LASTBIT_OUT <= is_lastbit_buf(to_integer(unsigned(DELAY_IN))); -OUT_TDO_EXPECTED_OUT <= tdo_expected_buf(to_integer(unsigned(DELAY_IN))); - -SYNCHRONOUS_MAIN : process (CLK_IN) -begin - if (rising_edge(CLK_IN)) then - if(RESET_IN = '1') then - is_dr_bit_buf <= (others => '0'); - is_firstbit_buf <= (others => '0'); - is_lastbit_buf <= (others => '0'); - tdo_expected_buf <= (others => '0'); - regnum_buf <= (others => (others => '0')); - chipnum_buf <= (others => (others => '0')); - else - is_dr_bit_buf <= is_dr_bit_buf_next; - is_firstbit_buf <= is_firstbit_buf_next; - is_lastbit_buf <= is_lastbit_buf_next; - tdo_expected_buf <= tdo_expected_buf_next; - regnum_buf <= regnum_buf_next; - chipnum_buf <= chipnum_buf_next; - end if; - end if; -end process; - -COMB_MAIN: process(SAMPLE_PULSE1_IN, IS_LASTBIT_IN, IS_DR_BIT_IN, IS_FIRSTBIT_IN, TDO_EXPECTED_IN, REGNUM_IN, CHIPNUM_IN, is_lastbit_buf, is_dr_bit_buf, is_firstbit_buf, tdo_expected_buf, regnum_buf, chipnum_buf) -begin - is_lastbit_buf_next <= is_lastbit_buf; - is_dr_bit_buf_next <= is_dr_bit_buf; - is_firstbit_buf_next <= is_firstbit_buf; - tdo_expected_buf_next <= tdo_expected_buf; - regnum_buf_next <= regnum_buf; - chipnum_buf_next <= chipnum_buf; - -- shift registers - if(SAMPLE_PULSE1_IN = '1') then - if(2**ld_maxdelay-1 >= 1) then - is_lastbit_buf_next(2**ld_maxdelay-1 downto 1) <= is_lastbit_buf(2**ld_maxdelay-1 -1 downto 0); - is_dr_bit_buf_next(2**ld_maxdelay-1 downto 1) <= is_dr_bit_buf(2**ld_maxdelay-1 -1 downto 0); - is_firstbit_buf_next(2**ld_maxdelay-1 downto 1) <= is_firstbit_buf(2**ld_maxdelay-1 -1 downto 0); - tdo_expected_buf_next(2**ld_maxdelay-1 downto 1) <= tdo_expected_buf(2**ld_maxdelay-1 -1 downto 0); - regnum_buf_next(2**ld_maxdelay-1 downto 1) <= regnum_buf(2**ld_maxdelay-1 -1 downto 0); - chipnum_buf_next(2**ld_maxdelay-1 downto 1) <= chipnum_buf(2**ld_maxdelay-1 -1 downto 0); - end if; - is_lastbit_buf_next(0) <= IS_LASTBIT_IN; - is_dr_bit_buf_next(0) <= IS_DR_BIT_IN; - is_firstbit_buf_next(0) <= IS_FIRSTBIT_IN; - tdo_expected_buf_next(0) <= TDO_EXPECTED_IN; - regnum_buf_next(0) <= REGNUM_IN; - chipnum_buf_next(0) <= CHIPNUM_IN; - end if; -end process; - -end architecture; diff --git a/vhdl/code/jtag_init_ram1b.vhd b/vhdl/code/jtag_init_ram1b.vhd deleted file mode 100755 index 599e7e6..0000000 --- a/vhdl/code/jtag_init_ram1b.vhd +++ /dev/null @@ -1,142 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; - -library work; - -use work.jtag_constants.all; -use work.jtag_misc.all; - -entity jtag_init_ram1b is - generic ( - RAM_JTAG_REGISTERS_DEPTH : integer; - MAX_NUMCHIPS_LD : integer; - MAX_REGISTERS_LD : integer - ); - port ( - CLK_IN : std_logic; - RESET_IN : std_logic; - TRIGGER_INIT_IN : std_logic; - -- RAM1a - RAM1A_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); - RAM1A_D_IN : in std_logic_vector(31 downto 0); - -- RAM1b - RAM1B_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); - RAM1B_D_IN : in std_logic_vector(31 downto 0); - RAM1B_WE_OUT : out std_logic; - RAM1B_D_OUT : out std_logic_vector(31 downto 0); - - IDLE_OUT : out std_logic - ); -end entity; - -architecture jtag_init_ram1b_arch of jtag_init_ram1b is -type state_type is (idle, read_numregs0, read_numregs1, write_i, nextchip); -signal state, state_next : state_type; -signal wordcounter, wordcounter_next : unsigned(RAM_JTAG_REGISTERS_DEPTH-1-MAX_NUMCHIPS_LD downto 0); -signal chipcounter, chipcounter_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0); -constant chipcounter_end : unsigned(MAX_NUMCHIPS_LD-1 downto 0) := (others => '1'); -signal ram1a_a, ram1a_a_next : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1-MAX_NUMCHIPS_LD downto 0); -signal ram1b_a, ram1b_a_next : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1-MAX_NUMCHIPS_LD downto 0); -signal ram1b_data, ram1b_data_next : std_logic_vector(31 downto 0); -signal ram1b_we, ram1b_we_next : std_logic; -signal numregs, numregs_next : unsigned(MAX_REGISTERS_LD-1 downto 0); -constant wordcounter_end : unsigned(RAM_JTAG_REGISTERS_DEPTH-1 downto 0) := (others => '1'); -- this should be a constant -begin ---wordcounter_end <= (others => '1'); -- maximum RAM address -IDLE_OUT <= '1' when state = idle else '0'; -RAM1A_A_OUT(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-1-MAX_NUMCHIPS_LD+1) <= std_logic_vector(chipcounter); -RAM1A_A_OUT(RAM_JTAG_REGISTERS_DEPTH-1-MAX_NUMCHIPS_LD downto 0) <= ram1a_a; -RAM1B_A_OUT(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-1-MAX_NUMCHIPS_LD+1) <= std_logic_vector(chipcounter); -RAM1B_A_OUT(RAM_JTAG_REGISTERS_DEPTH-1-MAX_NUMCHIPS_LD downto 0) <= ram1b_a; -RAM1B_WE_OUT <= ram1b_we; -RAM1B_D_OUT <= ram1b_data; -SYNCHRONOUS: process(CLK_IN) -begin - if (rising_edge(CLK_IN)) then - if(RESET_IN = '1') then - state <= idle; - ram1a_a <= (others => '0'); - ram1b_a <= (others => '0'); - ram1b_data <= (others => '0'); - ram1b_we <= '0'; - wordcounter <= (others => '0'); - chipcounter <= (others => '0'); - numregs <= (others => '0'); - else - state <= state_next; - ram1a_a <= ram1a_a_next; - ram1b_a <= ram1b_a_next; - ram1b_data <= ram1b_data_next; - ram1b_we <= ram1b_we_next; - wordcounter <= wordcounter_next; - chipcounter <= chipcounter_next; - numregs <= numregs_next; - end if; - end if; -end process; - -COMB: process (state, TRIGGER_INIT_IN, RAM1A_D_IN, numregs, ram1a_a, ram1b_a, ram1b_data, wordcounter, chipcounter ) -begin - ram1a_a_next <= ram1a_a; - ram1b_a_next <= ram1b_a; - ram1b_data_next <= ram1b_data; - state_next <= state; - wordcounter_next <= wordcounter; - chipcounter_next <= chipcounter; - ram1b_we_next <= '0'; - numregs_next <= numregs; - - case state is - when IDLE => - if(TRIGGER_INIT_IN = '1') then - chipcounter_next <= (others => '0'); - ram1a_a_next <= (others => '0'); -- numregs - state_next <= READ_NUMREGS0; - end if; - when READ_NUMREGS0 => - ram1a_a_next <= std_logic_vector(to_unsigned(1,RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD)); -- word 1 - state_next <= READ_NUMREGS1; - when READ_NUMREGS1 => - ram1a_a_next <= std_logic_vector(to_unsigned(2,RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD)); -- word 2 - numregs_next <= unsigned(RAM1A_D_IN(MAX_REGISTERS_LD-1 downto 0)); - wordcounter_next <= to_unsigned(1,RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD); -- which word to write in next step - -- write word to RAM1b - ram1b_a_next <= (others => '0'); -- numregs - ram1b_data_next <= RAM1A_D_IN; - ram1b_we_next <= '1'; - state_next <= WRITE_I; - when WRITE_I => - wordcounter_next <= wordcounter + 1; - ram1b_a_next <= std_logic_vector(wordcounter); - ram1b_we_next <= '1'; - -- the following block guarantees that the DEV_ID at wordcounter=1 in ram1a is not copied to ram1b - if(wordcounter < 2*numregs+2) then - ram1a_a_next <= std_logic_vector(to_unsigned(to_integer(wordcounter)+2,RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD)); -- might need next word - if(to_integer(wordcounter) = 1) then - -- write zeros to reserved (for DEV_ID) - ram1b_data_next <= (others => '0'); - else - -- write Ptr/Length fields to RAM1b - ram1b_data_next <= RAM1A_D_IN; - end if; - else - -- blank rest of RAM - ram1b_data_next <= (others => '0'); - end if; - if(std_logic_vector_all_components_equal_scalar(std_logic_vector(wordcounter), '1') = '1') then - state_next <= NEXTCHIP; - end if; - when NEXTCHIP => - if(chipcounter /= chipcounter_end) then - chipcounter_next <= chipcounter + 1; - ram1a_a_next <= (others => '0'); -- numregs - state_next <= READ_NUMREGS0; - else - state_next <= IDLE; - end if; - end case; -end process; - - -end architecture; diff --git a/vhdl/code/jtag_misc.vhd b/vhdl/code/jtag_misc.vhd deleted file mode 100644 index 5a5daa6..0000000 --- a/vhdl/code/jtag_misc.vhd +++ /dev/null @@ -1,50 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -library work; - -package jtag_misc is - function MYMIN(x : integer; y : integer) return integer; - function std_logic_vector_scalar_compare(vect: std_logic_vector; scalar : std_logic) return std_logic_vector; - function std_logic_vector_all_components_equal_scalar(vect: std_logic_vector; scalar : std_logic) return std_logic; -end package jtag_misc; - -package body jtag_misc is - -function MYMIN(x : integer; y : integer) - return integer is - begin - if x > y then - return y; - else - return x; - end if; - end MYMIN; - -function std_logic_vector_scalar_compare(vect: std_logic_vector; scalar : std_logic) return std_logic_vector is -variable output : std_logic_vector(vect'range); -variable i : integer; -begin - for i in vect'range loop - if(vect(i) = scalar) then - output(i) := '1'; - else - output(i) := '0'; - end if; - end loop; - return output; -end std_logic_vector_scalar_compare; - -function std_logic_vector_all_components_equal_scalar(vect: std_logic_vector; scalar : std_logic) return std_logic is -variable output : std_logic; -variable i : integer; -begin - output := '1'; - for i in vect'range loop - if(vect(i) /= scalar) then - output := '0'; - end if; - end loop; - return output; -end std_logic_vector_all_components_equal_scalar; -end package body jtag_misc; diff --git a/vhdl/code/jtag_mux_buffer_tms_tdi_out_and_metainfo.vhd b/vhdl/code/jtag_mux_buffer_tms_tdi_out_and_metainfo.vhd deleted file mode 100755 index 273917c..0000000 --- a/vhdl/code/jtag_mux_buffer_tms_tdi_out_and_metainfo.vhd +++ /dev/null @@ -1,188 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; ---USE IEEE.std_logic_ARITH.ALL; ---USE IEEE.std_logic_UNSIGNED.ALL; -USE IEEE.numeric_std.ALL; - -library work; ---use work.trb_net_std.all; ---use work.trb_net_components.all; --- use work.trb_net16_hub_func.all; ---use work.version.all; -use work.jtag_constants.all; --- this entity is a multiplexer, based on which *_ENABLE_JTAG_CLOCK_IN signal is '1' on a pulse on JTAG_SET_DATA_IN, it loads the corresponding input values for TMS, TDI, IS_DR_BIT, ... into the buffers -entity jtag_mux_buffer_tms_tdi_out_and_metainfo is - generic ( - MAX_NUMCHIPS_LD : integer; - MAX_REGISTERS_LD : integer - ); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - -- pulse when READ/WRITE/... entity's data should be taken and update - -- the output values for TMS,TDI - JTAG_SET_DATA_IN : in std_logic; - - -- read DEV_ID inputs - RD_TMS_IN : in std_logic; - RD_TDI_IN : in std_logic; - RD_IS_DR_BIT_IN: in std_logic; - RD_IS_FIRSTBIT_IN : in std_logic; - RD_IS_LASTBIT_IN : in std_logic; - RD_CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0); - RD_ENABLE_JTAG_CLOCK_IN : in std_logic; - RD_LAST_TCK_CYCLE_IN : in std_logic; - RD_EXPECTED_TDO_IN : in std_logic; - - -- write registers inputs - WR_TMS_IN : in std_logic; - WR_TDI_IN : in std_logic; - WR_IS_DR_BIT_IN: in std_logic; - WR_IS_FIRSTBIT_IN : in std_logic; - WR_IS_LASTBIT_IN : in std_logic; - WR_CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0); - WR_REGNUM_IN : in std_logic_vector(MAX_REGISTERS_LD-1 downto 0); - WR_ENABLE_JTAG_CLOCK_IN : in std_logic; - WR_LAST_TCK_CYCLE_IN : in std_logic; - WR_EXPECTED_TDO_IN : in std_logic; - - -- test chain inputs - TC_TMS_IN : in std_logic; - TC_TDI_IN : in std_logic; - TC_ENABLE_JTAG_CLOCK_IN : in std_logic; - TC_LAST_TCK_CYCLE_IN : in std_logic; - - TMS_OUT : out std_logic; - TDI_OUT : out std_logic; - IS_DR_BIT_OUT: out std_logic; - IS_FIRSTBIT_OUT : out std_logic; - IS_LASTBIT_OUT : out std_logic; - CHIPNUM_OUT : out std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0); - REGNUM_OUT : out std_logic_vector(MAX_REGISTERS_LD-1 downto 0); - ENABLE_JTAG_CLOCK_OUT : out std_logic; - LAST_TCK_CYCLE_OUT : out std_logic; - EXPECTED_TDO_OUT : out std_logic - ); -end entity; - -architecture jtag_mux_buffer_tms_tdi_out_and_metainfo_arch of jtag_mux_buffer_tms_tdi_out_and_metainfo is --- buffers -signal tms, tms_next : std_logic; -signal tdi, tdi_next : std_logic; -signal is_dr_bit, is_dr_bit_next : std_logic; -signal is_firstbit, is_firstbit_next : std_logic; -signal is_lastbit, is_lastbit_next : std_logic; -signal chipnum, chipnum_next : unsigned (MAX_NUMCHIPS_LD-1 downto 0); -signal regnum, regnum_next : unsigned (MAX_REGISTERS_LD-1 downto 0); - -signal enable_jtag_clock, enable_jtag_clock_next : std_logic; -signal last_tck_cycle, last_tck_cycle_next : std_logic; -signal expected_tdo, expected_tdo_next : std_logic; --- INSERTLABEL: signals -begin -TMS_OUT <= tms; -TDI_OUT <= tdi; -IS_DR_BIT_OUT <= is_dr_bit; -IS_FIRSTBIT_OUT <= is_firstbit; -IS_LASTBIT_OUT <= is_lastbit; -CHIPNUM_OUT <= std_logic_vector(chipnum); -REGNUM_OUT <= std_logic_vector(regnum); -ENABLE_JTAG_CLOCK_OUT <= enable_jtag_clock; -LAST_TCK_CYCLE_OUT <= last_tck_cycle; -EXPECTED_TDO_OUT <= expected_tdo; -SYNCHRONOUS_MAIN: process(CLK_IN) -begin - if(rising_edge(CLK_IN)) then - if(RESET_IN='1') then - tms <= '1'; - tdi <= '0'; - is_dr_bit <= '0'; - is_firstbit <= '0'; - is_lastbit <= '0'; - chipnum <= (others => '0'); - regnum <= (others => '0'); - enable_jtag_clock <= '0'; - last_tck_cycle <= '0'; - expected_tdo <= '0'; - -- INSERTLABEL: SYNCHRONOUS reset - else - tms <= tms_next; - tdi <= tdi_next; - is_dr_bit <= is_dr_bit_next; - is_firstbit <= is_firstbit_next; - is_lastbit <= is_lastbit_next; - chipnum <= chipnum_next; - regnum <= regnum_next; - enable_jtag_clock <= enable_jtag_clock_next; - last_tck_cycle <= last_tck_cycle_next; - expected_tdo <= expected_tdo_next; - -- INSERTLABEL: SYNCHRONOUS update - end if; - end if; -end process; - -COMB_MAIN: process(JTAG_SET_DATA_IN, RD_ENABLE_JTAG_CLOCK_IN, WR_ENABLE_JTAG_CLOCK_IN, TC_ENABLE_JTAG_CLOCK_IN, RD_TMS_IN, RD_TDI_IN, RD_IS_DR_BIT_IN, RD_IS_FIRSTBIT_IN, RD_IS_LASTBIT_IN, RD_CHIPNUM_IN, RD_LAST_TCK_CYCLE_IN, RD_EXPECTED_TDO_IN, WR_TMS_IN, WR_TDI_IN, WR_IS_DR_BIT_IN, WR_IS_FIRSTBIT_IN, WR_IS_LASTBIT_IN, WR_CHIPNUM_IN, WR_REGNUM_IN, WR_LAST_TCK_CYCLE_IN, WR_EXPECTED_TDO_IN, TC_TMS_IN, TC_TDI_IN, TC_LAST_TCK_CYCLE_IN, tdi, tms,is_dr_bit,is_firstbit,is_lastbit,chipnum,regnum,enable_jtag_clock,last_tck_cycle,expected_tdo) -- INSERTLABEL: sensitivity list -begin - tms_next <= tms; - tdi_next <= tdi; - is_dr_bit_next <= is_dr_bit; - is_firstbit_next <= is_firstbit; - is_lastbit_next <= is_lastbit; - chipnum_next <= chipnum; - regnum_next <= regnum; - enable_jtag_clock_next <= enable_jtag_clock; - last_tck_cycle_next <= last_tck_cycle; - expected_tdo_next <= expected_tdo; - -- INSERTLABEL: COMB defaults - if(JTAG_SET_DATA_IN = '1') then - if(RD_ENABLE_JTAG_CLOCK_IN = '1') then - tms_next <= RD_TMS_IN; - tdi_next <= RD_TDI_IN; - is_dr_bit_next <= RD_IS_DR_BIT_IN; - is_firstbit_next <= RD_IS_FIRSTBIT_IN; - is_lastbit_next <= RD_IS_LASTBIT_IN; - chipnum_next <= unsigned(RD_CHIPNUM_IN); - -- read dev_id is treated as register 0 - regnum_next <= (others => '0'); - enable_jtag_clock_next <= RD_ENABLE_JTAG_CLOCK_IN; - last_tck_cycle_next <= RD_LAST_TCK_CYCLE_IN; - expected_tdo_next <= RD_EXPECTED_TDO_IN; - elsif(WR_ENABLE_JTAG_CLOCK_IN = '1') then - tms_next <= WR_TMS_IN; - tdi_next <= WR_TDI_IN; - is_dr_bit_next <= WR_IS_DR_BIT_IN; - is_firstbit_next <= WR_IS_FIRSTBIT_IN; - is_lastbit_next <= WR_IS_LASTBIT_IN; - chipnum_next <= unsigned(WR_CHIPNUM_IN); - -- read dev_id is stored as register 0, the write registers are stored as WR_REGNUM+1 - regnum_next <= unsigned(WR_REGNUM_IN) + 1; - enable_jtag_clock_next <= WR_ENABLE_JTAG_CLOCK_IN; - last_tck_cycle_next <= WR_LAST_TCK_CYCLE_IN; - expected_tdo_next <= WR_EXPECTED_TDO_IN; - elsif(TC_ENABLE_JTAG_CLOCK_IN = '1') then - tms_next <= TC_TMS_IN; - tdi_next <= TC_TDI_IN; - is_dr_bit_next <= '0'; - is_firstbit_next <= '0'; - is_lastbit_next <= '0'; - chipnum_next <= (others =>'0'); - regnum_next <= (others =>'0'); - enable_jtag_clock_next <= TC_ENABLE_JTAG_CLOCK_IN; - last_tck_cycle_next <= TC_LAST_TCK_CYCLE_IN; - expected_tdo_next <= '0'; - else - tms_next <= '1'; - tdi_next <= '0'; - is_dr_bit_next <= '0'; - is_firstbit_next <= '0'; - is_lastbit_next <= '0'; - chipnum_next <= (others =>'0'); - regnum_next <= (others =>'0'); - enable_jtag_clock_next <= '0'; - last_tck_cycle_next <= '0'; - expected_tdo_next <= '0'; - end if; - end if; -end process; -end architecture; diff --git a/vhdl/code/jtag_mvd.vhd b/vhdl/code/jtag_mvd.vhd deleted file mode 100644 index 012a9aa..0000000 --- a/vhdl/code/jtag_mvd.vhd +++ /dev/null @@ -1,670 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.jtag_constants.all; -use work.trb3_components.all; -use work.trb_net_components.all; -use work.trb_net_std.all; - -library ecp3; -use ecp3.components.all; - - -entity jtag_mvd is - generic( - NUM_CHAINS : integer := 1 - ); - port( - CLK_IN : in std_logic; - CLK_MAPS_IN : in std_logic; --200 MHz for PLL! - RESET : in std_logic; - - MAPS_CLK_OUT : out std_logic_vector(NUM_CHAINS-1 downto 0); - MAPS_START_OUT : out std_logic_vector(NUM_CHAINS-1 downto 0); - MAPS_RESET_OUT : out std_logic_vector(NUM_CHAINS-1 downto 0); - - JTAG_TDI_OUT : out std_logic_vector(NUM_CHAINS-1 downto 0); - JTAG_TMS_OUT : out std_logic_vector(NUM_CHAINS-1 downto 0); - JTAG_TCK_OUT : out std_logic_vector(NUM_CHAINS-1 downto 0); - JTAG_TDO_IN : in std_logic_vector(NUM_CHAINS-1 downto 0); - - BUS_DATA_IN : in std_logic_vector(31 downto 0); - BUS_DATA_OUT : out std_logic_vector(31 downto 0); - BUS_ADDR_IN : in std_logic_vector(12 downto 0); - BUS_WRITE_IN : in std_logic; - BUS_READ_IN : in std_logic; - BUS_DATAREADY_OUT : out std_logic; - BUS_WRITE_ACK_OUT : out std_logic; - BUS_NO_MORE_DATA_OUT : out std_logic; - BUS_UNKNOWN_OUT : out std_logic; - - STATUS_OUT : out std_logic_vector(NUM_CHAINS*256-1 downto 0); --common status register, a.t.m. - DEBUG_OUT : out std_logic_vector(31 downto 0) - ); -end entity; - - - - - - -architecture jtag_mvd_arch of jtag_mvd is - signal clk_sys : std_logic; - signal clk_maps : std_logic; - signal reset_i : std_logic; - signal reset_i_mclk : std_logic; - - - -- COM_SETTINGS signals: for settings in this entity - signal com_settings_addr_in : std_logic_vector(7 downto 0); - signal com_settings_data_in : std_logic_vector(31 downto 0); - signal com_settings_read_enable_in : std_logic; - signal com_settings_write_enable_in : std_logic; - signal com_settings_write_enable_in_last : std_logic; - signal com_settings_data_out : std_logic_vector(31 downto 0); - signal com_settings_dataready_out : std_logic; - signal com_settings_write_ack_out : std_logic; - signal com_settings_no_more_data_out : std_logic; - signal com_settings_unknown_addr_out : std_logic; - - signal statreg_ack : std_logic; - signal statreg_addr : std_logic_vector(7 downto 0); - signal statreg_data : std_logic_vector(31 downto 0); - signal statreg_nack : std_logic; - signal statreg_read_en : std_logic; - signal statreg_write_en : std_logic; - - -- JTAG Chain slow control bus - signal jtag_cmd_m26c_addr_in : std_logic_vector(NUM_CHAINS*16-1 downto 0); - signal jtag_cmd_m26c_data_in : std_logic_vector(NUM_CHAINS*32-1 downto 0); - signal jtag_cmd_m26c_read_enable_in : std_logic_vector(NUM_CHAINS-1 downto 0); - signal jtag_cmd_m26c_write_enable_in : std_logic_vector(NUM_CHAINS-1 downto 0); - signal jtag_cmd_m26c_data_out : std_logic_vector(NUM_CHAINS*32-1 downto 0); - signal jtag_cmd_m26c_dataready_out : std_logic_vector(NUM_CHAINS-1 downto 0); - signal jtag_cmd_m26c_write_ack_out : std_logic_vector(NUM_CHAINS-1 downto 0); - signal jtag_cmd_m26c_no_more_data_out : std_logic_vector(NUM_CHAINS-1 downto 0); - signal jtag_cmd_m26c_unknown_addr_out : std_logic_vector(NUM_CHAINS-1 downto 0); - - constant num_bus_handler_ports : integer := NUM_CHAINS + 3; - type jtag_counters_t is array(NUM_CHAINS-1 downto 0) of std_logic_vector(COUNTER_WIDTHS-1 downto 0); - type jtag_long_counters_t is array(NUM_CHAINS-1 downto 0) of std_logic_vector(31 downto 0); - signal jtagcmd_read_id_errors_count_out : jtag_counters_t; - signal jtagcmd_write_errors_count_out : jtag_counters_t; - signal jtagcmd_data_changed_count_out : jtag_counters_t; - signal jtagcmd_sampling_errors_count_out : jtag_counters_t; - signal jtagcmd_run_counter_out : jtag_long_counters_t; - signal jtagcmd_started_out : std_logic_vector(num_chaINS-1 downto 0); - signal jtagcmd_last_run_successful_out : std_logic_vector(num_chaINS-1 downto 0); - signal jtagcmd_last_data_changed_out : std_logic_vector(num_chaINS-1 downto 0); - signal jtagcmd_last_write_errors_out : std_logic_vector(num_chaINS-1 downto 0); - signal jtagcmd_crc_error_out : std_logic_vector(num_chaINS-1 downto 0); - signal jtagcmd_last_read_errors_out : std_logic_vector(num_chaINS-1 downto 0); - - signal run_jtag : std_logic_vector(NUM_CHAINS-1 downto 0); - signal run_jtag_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); - signal trbnet_trigger_jtag_write_once : std_logic_vector(NUM_CHAINS-1 downto 0); - signal idle_out : std_logic_vector(NUM_CHAINS-1 downto 0); - signal request_reset : std_logic_vector(NUM_CHAINS-1 downto 0); - signal request_reset_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); - signal prog_jtag_finished : std_logic_vector(NUM_CHAINS-1 downto 0); - signal idle_out_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); - signal prog_jtag_finished_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); - - signal clk_maps_tmp_p : std_logic_vector(NUM_CHAINS-1 downto 0); - signal clk_maps_tmp_n : std_logic_vector(NUM_CHAINS-1 downto 0); - - signal maps_start : std_logic_vector(NUM_CHAINS-1 downto 0); - signal maps_reset : std_logic_vector(NUM_CHAINS-1 downto 0); - signal jtag_tms : std_logic_vector(NUM_CHAINS-1 downto 0); - signal jtag_tdi : std_logic_vector(NUM_CHAINS-1 downto 0); - signal jtag_tdo : std_logic_vector(NUM_CHAINS-1 downto 0); - signal jtag_tck : std_logic_vector(NUM_CHAINS-1 downto 0); - - - type sig_inv_t is array(NUM_CHAINS-1 downto 0) of std_logic_vector(13 downto 0); - signal signals_invert : sig_inv_t; - - attribute ODDRAPPS : string; - attribute ODDRAPPS of THE_CLK_OUT: label is "SCLK_ALIGNED"; - - signal trbnet_trigger_allchains_init_seq : std_logic; - signal trbnet_trigger_allchains_reset_pulse : std_logic; - signal trbnet_trigger_allchains_start_pulse : std_logic; - signal trbnet_trigger_init_seq : std_logic_vector(NUM_CHAINS-1 downto 0); - signal trbnet_trigger_reset_pulse : std_logic_vector(NUM_CHAINS-1 downto 0); - signal trbnet_trigger_start_pulse : std_logic_vector(NUM_CHAINS-1 downto 0); - signal trbnet_trigger_jtag_run_noreset : std_logic_vector(NUM_CHAINS-1 downto 0); - signal resetafterfirstwrite : std_logic_vector(NUM_CHAINS-1 downto 0); - signal resetbeforeinit : std_logic_vector(NUM_CHAINS-1 downto 0); - signal status_regs : std_logic_vector(NUM_CHAINS*256-1 downto 0); - - signal trbnet_trigger_allchains_init_seq_mclk : std_logic; - signal trbnet_trigger_allchains_reset_pulse_mclk : std_logic; - signal trbnet_trigger_allchains_start_pulse_mclk : std_logic; - signal trbnet_trigger_init_seq_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); - signal trbnet_trigger_reset_pulse_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); - signal trbnet_trigger_start_pulse_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); - signal trbnet_trigger_jtag_run_noreset_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); - - signal trigger_reset_pulse_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); - signal trigger2_reset_pulse_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); - signal trigger_start_pulse_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); - signal trigger_allchains_start_pulse_mclk : std_logic; - signal trigger_jtag_run_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); - signal trigger_jtag_run2_mclk : std_logic_vector(NUM_CHAINS-1 downto 0); - - type maps_reset_cnt_t is array (NUM_CHAINS-1 downto 0) of unsigned(6 downto 0); - signal maps_reset_count : maps_reset_cnt_t; - signal maps_start_count : maps_reset_cnt_t; - - type init_seq_t is (isIDLE, isRUN_JTAG_WAIT1, isRUN_JTAG_WAIT2, isRUN_JTAG_WAIT3, - isRUN_JTAG_WAIT4, isRUN_JTAG_WAIT5, isRUN_JTAG_WAIT6, isRUN_JTAG_WAIT7, isRUN_JTAG, isWAITBEFORESTART ); - type init_seq_mult_t is array (NUM_CHAINS-1 downto 0) of init_seq_t; - signal init_seq_mclk : init_seq_mult_t; - signal init_seq_allchains_mclk : init_seq_t; - - type cnt_t is array (0 to NUM_CHAINS-1) of unsigned(27 downto 0); - signal waitbeforestart_counter : cnt_t; - signal waitbeforestart : unsigned(27 downto 0); - signal waitbeforestart_counter_allchains : unsigned(27 downto 0); - signal waitbeforestart_mclk : unsigned(27 downto 0); - -begin - ---------------------------------------------------------------------------- --- Clock & Reset ---------------------------------------------------------------------------- - clk_sys <= CLK_IN; --- clk_maps <= CLK_MAPS_IN; - reset_i <= RESET when rising_edge(clk_sys); - reset_i_mclk <= reset_i when rising_edge(clk_maps); - - ---------------------------------------------------------------------------- --- The JTAG Bus Handler 0: control registers, 1-N: JTAG controllers ---------------------------------------------------------------------------- - -THE_BUS_HANDLER : trb_net16_regio_bus_handler - generic map( - PORT_NUMBER => num_bus_handler_ports, - PORT_ADDRESSES => (0 => x"1000", 1 => x"1800", 2 => x"0000", 3 => x"0400", 4 => x"0800", 5 => x"0A00", others => x"0000"), - PORT_ADDR_MASK => (0 => 8, 1 => 8, 2 => 10, 3 => 10, 4 => 10, 5 => 10, others => 0) - ) - port map( - CLK => clk_sys, - RESET => reset_i, - - DAT_ADDR_IN(12 downto 0) => BUS_ADDR_IN, - DAT_ADDR_IN(15 downto 13)=> "000", - DAT_DATA_IN => BUS_DATA_IN, - DAT_DATA_OUT => BUS_DATA_OUT, - DAT_READ_ENABLE_IN => BUS_READ_IN, - DAT_WRITE_ENABLE_IN => BUS_WRITE_IN, - DAT_TIMEOUT_IN => '0', - DAT_DATAREADY_OUT => BUS_DATAREADY_OUT, - DAT_WRITE_ACK_OUT => BUS_WRITE_ACK_OUT, - DAT_NO_MORE_DATA_OUT => BUS_NO_MORE_DATA_OUT, - DAT_UNKNOWN_ADDR_OUT => BUS_UNKNOWN_OUT, - - --Common Registers - BUS_READ_ENABLE_OUT(0) => com_settings_read_enable_in, - BUS_WRITE_ENABLE_OUT(0) => com_settings_write_enable_in, - BUS_DATA_OUT(0*32+31 downto 0*32) => com_settings_data_in, - BUS_ADDR_OUT(0*16+7 downto 0*16) => com_settings_addr_in, - BUS_ADDR_OUT(0*16+15 downto 0*16+8) => open, - BUS_TIMEOUT_OUT(0) => open, - BUS_DATA_IN(0*32+31 downto 0*32) => com_settings_data_out, - BUS_DATAREADY_IN(0) => com_settings_dataready_out, - BUS_WRITE_ACK_IN(0) => com_settings_write_ack_out, - BUS_NO_MORE_DATA_IN(0) => com_settings_no_more_data_out, - BUS_UNKNOWN_ADDR_IN(0) => com_settings_unknown_addr_out, - - --Status Registers - BUS_READ_ENABLE_OUT(1) => statreg_read_en, - BUS_WRITE_ENABLE_OUT(1) => statreg_write_en, - BUS_DATA_OUT(1*32+31 downto 1*32) => open, - BUS_ADDR_OUT(1*16+7 downto 1*16) => statreg_addr, - BUS_ADDR_OUT(1*16+15 downto 1*16+8) => open, - BUS_TIMEOUT_OUT(1) => open, - BUS_DATA_IN(1*32+31 downto 1*32) => statreg_data, - BUS_DATAREADY_IN(1) => statreg_ack, - BUS_WRITE_ACK_IN(1) => '0', - BUS_NO_MORE_DATA_IN(1) => '0', - BUS_UNKNOWN_ADDR_IN(1) => statreg_nack, - - --JTAG chains - BUS_READ_ENABLE_OUT((NUM_CHAINS+1) downto 2) => jtag_cmd_m26c_read_enable_in, - BUS_WRITE_ENABLE_OUT((NUM_CHAINS+1) downto 2) => jtag_cmd_m26c_write_enable_in, - BUS_DATA_OUT((NUM_CHAINS+1)*32+31 downto 2*32) => jtag_cmd_m26c_data_in, - BUS_ADDR_OUT((NUM_CHAINS+1)*16+15 downto 2*16) => jtag_cmd_m26c_addr_in, - BUS_TIMEOUT_OUT((NUM_CHAINS+1) downto 2) => open, - BUS_DATA_IN((NUM_CHAINS+1)*32+31 downto 2*32) => jtag_cmd_m26c_data_out, - BUS_DATAREADY_IN((NUM_CHAINS+1) downto 2) => jtag_cmd_m26c_dataready_out, - BUS_WRITE_ACK_IN((NUM_CHAINS+1) downto 2) => jtag_cmd_m26c_write_ack_out, - BUS_NO_MORE_DATA_IN((NUM_CHAINS+1) downto 2) => jtag_cmd_m26c_no_more_data_out, - BUS_UNKNOWN_ADDR_IN((NUM_CHAINS+1) downto 2) => jtag_cmd_m26c_unknown_addr_out, - - STAT_DEBUG => open - ); - - ---------------------------------------------------------------------------- --- The MAPS Clock PLL ---------------------------------------------------------------------------- - - THE_MAPS_PLL : entity work.pll_in100_out80 --currently: 200 MHz in! - port map( - CLK => CLK_MAPS_IN, - CLKOP => clk_maps, - LOCK => open - ); - - ---------------------------------------------------------------------------- --- Generic status register ---------------------------------------------------------------------------- - gen_status_out : for i in 0 to NUM_CHAINS-1 generate - status_regs(i*256+31 downto i*256+0) <= jtagcmd_write_errors_count_out(i) & jtagcmd_read_id_errors_count_out(i); - status_regs(i*256+63 downto i*256+32) <= jtagcmd_sampling_errors_count_out(i) & jtagcmd_data_changed_count_out(i); - status_regs(i*256+95 downto i*256+64) <= jtagcmd_run_counter_out(i); - status_regs(i*256+127 downto i*256+96) <= "000" & '0' & "000" & '0' & - "000" & jtagcmd_crc_error_out(i) & "000" & jtagcmd_last_read_errors_out(i) & - "000" & jtagcmd_last_write_errors_out(i) & "000" & jtagcmd_last_data_changed_out(i) & - "000" & jtagcmd_last_run_successful_out(i) & "000" & jtagcmd_started_out(i); - status_regs(i*256+255 downto i*256+128) <= (others => '1'); - end generate; - - STATUS_OUT(NUM_CHAINS*256-1 downto 0) <= status_regs; - - - THE_STAT_REG_MUX : process(clk_sys) - variable addr : integer; - begin - if rising_edge(clk_sys) then - addr := to_integer(unsigned(statreg_addr)); - statreg_ack <= '0'; - statreg_nack <= '0'; - if statreg_read_en = '1' then - if (addr < NUM_CHAINS * 8) then - statreg_data <= status_regs(addr*32+31 downto addr*32); - statreg_ack <= '1'; - else - statreg_nack <= '1'; - end if; - elsif statreg_write_en = '1' then - statreg_nack <= '1'; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- Inputs & Outputs ---------------------------------------------------------------------------- - gen_clock_out : for i in 0 to NUM_CHAINS-1 generate - MAPS_RESET_OUT(i) <= (maps_reset(i) xor signals_invert(i)(10)) when signals_invert(i)(11) = '1' else signals_invert(i)(10); - MAPS_START_OUT(i) <= (maps_start(i) xor signals_invert(i)(8)) when signals_invert(i)(9) = '1' else signals_invert(i)(8); - JTAG_TCK_OUT(i) <= (jtag_tck(i) xor signals_invert(i)(6)) when signals_invert(i)(7) = '1' else signals_invert(i)(6); - JTAG_TMS_OUT(i) <= (jtag_tms(i) xor signals_invert(i)(4)) when signals_invert(i)(5) = '1' else signals_invert(i)(4); - JTAG_TDI_OUT(i) <= (jtag_tdi(i) xor signals_invert(i)(2)) when signals_invert(i)(3) = '1' else signals_invert(i)(2); - jtag_tdo(i) <= (JTAG_TDO_IN(i) xor signals_invert(i)(0)) when signals_invert(i)(1) = '1' else signals_invert(i)(0); - - clk_maps_tmp_p(i) <= signals_invert(i)(12) when signals_invert(i)(13) = '1' else signals_invert(i)(12); - clk_maps_tmp_n(i) <= not signals_invert(i)(12) when signals_invert(i)(13) = '1' else signals_invert(i)(12); - - THE_CLK_OUT : ODDRXD1 - port map( - sclk => clk_maps, - da => clk_maps_tmp_p(i), - db => clk_maps_tmp_n(i), - q => MAPS_CLK_OUT(i) - ); - - end generate; - - ---------------------------------------------------------------------------- --- JTAG Chain ---------------------------------------------------------------------------- -gen_chains : for i in 0 to NUM_CHAINS-1 generate - THE_JTAG_CMD_M26C : entity work.jtag_cmd_m26c - port map( - CLK_IN => clk_sys, - RESET_IN => reset_i, - - JTAG_TMS_OUT => jtag_tms(i), - JTAG_TCK_OUT => jtag_tck(i), - JTAG_TDI_OUT => jtag_tdi(i), - JTAG_TDO_IN => jtag_tdo(i), - - BUS_DATA_IN => jtag_cmd_m26c_data_in(32*i+31 downto 32*i), - BUS_DATA_OUT => jtag_cmd_m26c_data_out(32*i+31 downto 32*i), - BUS_ADDR_IN => jtag_cmd_m26c_addr_in(16*i+9 downto 16*i), - BUS_READ_IN => jtag_cmd_m26c_read_enable_in(i), - BUS_WRITE_IN => jtag_cmd_m26c_write_enable_in(i), - - BUS_DATAREADY_OUT => jtag_cmd_m26c_dataready_out(i), - BUS_NO_MORE_DATA_OUT => jtag_cmd_m26c_no_more_data_out(i), - BUS_WRITE_ACK_OUT => jtag_cmd_m26c_write_ack_out(i), - BUS_UNKNOWN_ADDR_OUT => jtag_cmd_m26c_unknown_addr_out(i), - - RUN_REQUEST_IN => run_jtag(i), - WRITE_ONCE_REQUEST_IN => trbnet_trigger_jtag_write_once(i), - MY_STATUS_OUT => open, - IDLE_OUT => idle_out(i), - REQUEST_RESET_OUT => request_reset(i), - PROG_JTAG_FINISHED_OUT => prog_jtag_finished(i), - - READ_ID_ERRORS_COUNT_OUT => jtagcmd_read_id_errors_count_out(i), - WRITE_ERRORS_COUNT_OUT => jtagcmd_write_errors_count_out(i), - DATA_CHANGED_COUNT_OUT => jtagcmd_data_changed_count_out(i), - SAMPLING_ERRORS_COUNT_OUT => jtagcmd_sampling_errors_count_out(i), - RUN_COUNTER_OUT => jtagcmd_run_counter_out(i), - - STARTED_OUT => jtagcmd_started_out(i), - LAST_RUN_SUCCESSFUL_OUT => jtagcmd_last_run_successful_out(i), - LAST_DATA_CHANGED_OUT => jtagcmd_last_data_changed_out(i), - LAST_WRITE_ERRORS_OUT => jtagcmd_last_write_errors_out(i), - LAST_READ_ERRORS_OUT => jtagcmd_last_read_errors_out(i), - CRC_ERROR_OUT => jtagcmd_crc_error_out(i) - ); -end generate; - - ---------------------------------------------------------------------------- --- Clock domain transfers ---------------------------------------------------------------------------- - - - gen_sync_per_chain : for i in 0 to NUM_CHAINS-1 generate - ps00 : pulse_sync port map(clk_sys, reset_i, request_reset(i), - clk_maps, reset_i_mclk, request_reset_mclk(i)); - ps01 : pulse_sync port map(clk_sys, reset_i, trbnet_trigger_init_seq(i), - clk_maps, reset_i_mclk, trbnet_trigger_init_seq_mclk(i)); - ps02 : pulse_sync port map(clk_sys, reset_i, trbnet_trigger_reset_pulse(i), - clk_maps, reset_i_mclk, trbnet_trigger_reset_pulse_mclk(i)); - ps03 : pulse_sync port map(clk_sys, reset_i, trbnet_trigger_start_pulse(i), - clk_maps, reset_i_mclk, trbnet_trigger_start_pulse_mclk(i)); - ps04 : pulse_sync port map(clk_sys, reset_i, trbnet_trigger_jtag_run_noreset(i), - clk_maps, reset_i_mclk, trbnet_trigger_jtag_run_noreset_mclk(i)); - end generate; - - - ps11 : pulse_sync port map(clk_sys, reset_i, trbnet_trigger_allchains_init_seq, - clk_maps, reset_i_mclk, trbnet_trigger_allchains_init_seq_mclk); - ps12 : pulse_sync port map(clk_sys, reset_i, trbnet_trigger_allchains_reset_pulse, - clk_maps, reset_i_mclk, trbnet_trigger_allchains_reset_pulse_mclk); - ps13 : pulse_sync port map(clk_sys, reset_i, trbnet_trigger_allchains_start_pulse, - clk_maps, reset_i_mclk, trbnet_trigger_allchains_start_pulse_mclk); - - - idle_out_mclk <= idle_out when rising_edge(clk_maps); - prog_jtag_finished_mclk <= prog_jtag_finished when rising_edge(clk_maps); - waitbeforestart_mclk <= waitbeforestart when rising_edge(clk_maps); - ---------------------------------------------------------------------------- --- Generate control signals for MAPS ----------------------------------------------------- ----------------------- - gen_maps_signals : for i in 0 to NUM_CHAINS-1 generate - MAPS_RESET_PULSE : process - begin - wait until rising_edge(clk_maps); - if(maps_reset_count(i) = 0 or reset_i_mclk = '1') then - maps_reset(i) <= '0'; - else - maps_reset_count(i) <= maps_reset_count(i) - 1; - end if; - - if ( trbnet_trigger_reset_pulse_mclk(i) = '1' - or trigger_reset_pulse_mclk(i) = '1' - or trigger2_reset_pulse_mclk(i) = '1' - or trbnet_trigger_allchains_reset_pulse_mclk = '1') then - maps_reset_count(i) <= "1100100"; -- 101 clock cycles reset (on for 100,...,4,3,2,1,0) - maps_reset(i) <= '1'; - end if; - end process; - - MAPS_START_PULSE : process - begin - wait until rising_edge(clk_maps); - if(maps_start_count(i) = 0 or reset_i_mclk = '1') then - maps_start(i) <= '0'; - else - maps_start_count(i) <= maps_start_count(i) - 1; - end if; - - if ( trbnet_trigger_start_pulse_mclk(i) = '1' - or trigger_start_pulse_mclk(i) = '1' - or trbnet_trigger_allchains_start_pulse_mclk = '1' - or trigger_allchains_start_pulse_mclk = '1') then - maps_start_count(i) <= "1000000"; -- 65 clock cycles start (on for 64,...,4,3,2,1,0) - maps_start(i) <= '1'; - end if; - - end process; - - end generate; - - --JTAG_RUN_NORESET / RUN_JTAG_SYNC - run_jtag_mclk <= trbnet_trigger_jtag_run_noreset_mclk or trigger_jtag_run_mclk or trigger_jtag_run2_mclk when rising_edge(clk_maps); - run_jtag <= run_jtag_mclk when rising_edge(clk_sys); - - - gen_init_sequence : for i in 0 to NUM_CHAINS-1 generate - TRIGGER_INITIALIZATION_SEQUENCE_PULSE : process(clk_maps) - begin - if(rising_edge(clk_maps)) then - trigger_start_pulse_mclk(i) <= '0'; - trigger_reset_pulse_mclk(i) <= '0'; - trigger_jtag_run_mclk(i) <= '0'; - case init_seq_mclk(i) is - when isIDLE => - when isRUN_JTAG_WAIT1 => - init_seq_mclk(i) <= isRUN_JTAG_WAIT2; - when isRUN_JTAG_WAIT2 => - init_seq_mclk(i) <= isRUN_JTAG_WAIT3; - when isRUN_JTAG_WAIT3 => - init_seq_mclk(i) <= isRUN_JTAG_WAIT4; - when isRUN_JTAG_WAIT4 => - init_seq_mclk(i) <= isRUN_JTAG_WAIT5; - when isRUN_JTAG_WAIT5 => - init_seq_mclk(i) <= isRUN_JTAG_WAIT6; - when isRUN_JTAG_WAIT6 => - init_seq_mclk(i) <= isRUN_JTAG_WAIT7; - when isRUN_JTAG_WAIT7 => - init_seq_mclk(i) <= isRUN_JTAG; - when isRUN_JTAG => - if(resetafterfirstwrite(i) = '1' and request_reset_mclk(i) = '1') then - trigger_reset_pulse_mclk(i) <= '1'; - end if; - - -- wait for completion of potential copy ram request and then finishing of run - if(idle_out_mclk(i) = '1') then - init_seq_mclk(i) <= isWAITBEFORESTART; - waitbeforestart_counter(i) <= waitbeforestart_mclk; - end if; - when isWAITBEFORESTART => - waitbeforestart_counter(i) <= waitbeforestart_counter(i) -1; - if(waitbeforestart_counter(i) = 0) then - trigger_start_pulse_mclk(i) <= '1'; - init_seq_mclk(i) <= isIDLE; - end if; - end case; - - if(trbnet_trigger_init_seq_mclk(i) = '1') then - if(resetbeforeinit(i) = '1') then - trigger_reset_pulse_mclk(i) <= '1'; - end if; - trigger_jtag_run_mclk(i) <= '1'; - init_seq_mclk(i) <= isRUN_JTAG_WAIT1; - end if; - if(reset_i_mclk = '1') then - init_seq_mclk(i) <= isIDLE; - end if; - end if; - end process; - end generate; - - - TRIGGER_ALLCHAINS_INITIALIZATION_SEQUENCE_PULSE : process(clk_maps) - begin - if(rising_edge(clk_maps)) then - trigger2_reset_pulse_mclk <= (others => '0'); - trigger_jtag_run2_mclk <= (others => '0'); - trigger_allchains_start_pulse_mclk <= '0'; - case init_seq_allchains_mclk is - when isIDLE => - when isRUN_JTAG_WAIT1 => - init_seq_allchains_mclk <= isRUN_JTAG_WAIT2; - when isRUN_JTAG_WAIT2 => - init_seq_allchains_mclk <= isRUN_JTAG_WAIT3; - when isRUN_JTAG_WAIT3 => - init_seq_allchains_mclk <= isRUN_JTAG_WAIT4; - when isRUN_JTAG_WAIT4 => - init_seq_allchains_mclk <= isRUN_JTAG_WAIT5; - when isRUN_JTAG_WAIT5 => - init_seq_allchains_mclk <= isRUN_JTAG_WAIT6; - when isRUN_JTAG_WAIT6 => - init_seq_allchains_mclk <= isRUN_JTAG_WAIT7; - when isRUN_JTAG_WAIT7 => - init_seq_allchains_mclk <= isRUN_JTAG; - when isRUN_JTAG => - trigger2_reset_pulse_mclk <= resetafterfirstwrite and request_reset_mclk; - - if(and_all(idle_out_mclk) = '1') then - init_seq_allchains_mclk <= isWAITBEFORESTART; - waitbeforestart_counter_allchains <= waitbeforestart_mclk; - end if; - when isWAITBEFORESTART => - waitbeforestart_counter_allchains <= waitbeforestart_counter_allchains -1; - if(waitbeforestart_counter_allchains = 0) then - trigger_allchains_start_pulse_mclk <= '1'; - init_seq_allchains_mclk <= isIDLE; - end if; - end case; - if(trbnet_trigger_allchains_init_seq_mclk = '1') then - trigger2_reset_pulse_mclk <= resetbeforeinit; - trigger_jtag_run2_mclk <= (others => '1'); - init_seq_allchains_mclk <= isRUN_JTAG_WAIT1; - end if; - - if(reset_i_mclk = '1') then - init_seq_allchains_mclk <= isIDLE; - end if; - end if; - end process; - - - --- 3: trbnet_trigger_allchains_init_seq nodata --- 6,8,9: signals_invert 14bit / N regs -> move to 0x20... 0x2F --- 7: waitbeforestart 28bit --- a: trbnet_trigger_allchains_reset_pulse nodata --- b: trbnet_trigger_allchains_start_pulse nodata --- c: trbnet_trigger_init_seq N bit --- d: trbnet_trigger_reset_pulse N bit --- e: trbnet_trigger_start_pulse N bit --- f: trbnet_trigger_jtag_run_noreset N bit --- 10: resetbeforeinit N bit --- 11: resetafterfirstwrite N bit --- 14: trbnet_trigger_jtag_write_once N bit - - ---------------------------------------------------------------------------- --- Control Registers ---------------------------------------------------------------------------- - com_settings_all : process - begin - wait until rising_edge(clk_sys); - com_settings_write_ack_out <= '0'; - com_settings_dataready_out <= '0'; - com_settings_unknown_addr_out <= '0'; - com_settings_no_more_data_out <= '0'; - com_settings_data_out <= (others => '0'); - -- MUST NOW BE 1 CYCLE ONLY. Before it was: - -- reset triggers after 2 clock cycles at 100 MHz, to be able to sample at 80 MHz - trbnet_trigger_allchains_init_seq <= '0'; - trbnet_trigger_allchains_reset_pulse <= '0'; - trbnet_trigger_allchains_start_pulse <= '0'; - trbnet_trigger_init_seq <= (others => '0'); - trbnet_trigger_reset_pulse <= (others => '0'); - trbnet_trigger_start_pulse <= (others => '0'); - trbnet_trigger_jtag_run_noreset <= (others => '0'); - trbnet_trigger_jtag_write_once <= (others => '0'); - - if(com_settings_write_enable_in = '1') then - com_settings_write_ack_out <= '1'; - case com_settings_addr_in is - when x"03" => - trbnet_trigger_allchains_init_seq <= '1'; - when x"07" => - waitbeforestart <= unsigned(com_settings_data_in(27 downto 0)); - when x"0a" => - trbnet_trigger_allchains_reset_pulse <= com_settings_data_in(0); - when x"0b" => - trbnet_trigger_allchains_start_pulse <= com_settings_data_in(0); - when x"0c" => - trbnet_trigger_init_seq <= com_settings_data_in(NUM_CHAINS-1 downto 0); - when x"0d" => - trbnet_trigger_reset_pulse <= com_settings_data_in(NUM_CHAINS-1 downto 0); - when x"0e" => - trbnet_trigger_start_pulse <= com_settings_data_in(NUM_CHAINS-1 downto 0); - when x"0f" => - trbnet_trigger_jtag_run_noreset <= com_settings_data_in(NUM_CHAINS-1 downto 0); - when x"10" => - resetbeforeinit <= com_settings_data_in(NUM_CHAINS-1 downto 0); - when x"11" => - resetafterfirstwrite <= com_settings_data_in(NUM_CHAINS-1 downto 0); - when x"14" => - trbnet_trigger_jtag_write_once <= com_settings_data_in(NUM_CHAINS-1 downto 0); - when others => - if(com_settings_addr_in(7 downto 4) = x"2" and com_settings_addr_in(3 downto 0) < std_logic_vector(to_unsigned(NUM_CHAINS,4))) then - signals_invert(to_integer(unsigned(com_settings_addr_in(3 downto 0)))) <= com_settings_data_in(13 downto 0); - else - com_settings_write_ack_out <= '0'; - com_settings_unknown_addr_out <= '1'; - end if; - end case; - - elsif(com_settings_read_enable_in = '1') then - com_settings_dataready_out <= '1'; - case com_settings_addr_in is - when x"07" => - com_settings_data_out(27 downto 0) <= std_logic_vector(waitbeforestart); - when x"10" => - com_settings_data_out(NUM_CHAINS-1 downto 0) <= resetbeforeinit; - when x"11" => - com_settings_data_out(NUM_CHAINS-1 downto 0) <= resetafterfirstwrite; - when x"12" => - com_settings_data_out(6 downto 0) <= std_logic_vector(maps_reset_count(0)(6 downto 0)); - when x"13" => - com_settings_data_out(6 downto 0) <= std_logic_vector(maps_start_count(0)(6 downto 0)); - when others => - if(com_settings_addr_in(7 downto 4) = x"2" and com_settings_addr_in(3 downto 0) < std_logic_vector(to_unsigned(NUM_CHAINS,4))) then - com_settings_data_out(13 downto 0) <= signals_invert(to_integer(unsigned(com_settings_addr_in(3 downto 0)))); - else - com_settings_dataready_out <= '0'; - com_settings_unknown_addr_out <= '1'; - end if; - end case; - end if; - - if(reset_i = '1') then - resetbeforeinit <= (others => '0'); - resetafterfirstwrite <= (others => '0'); - waitbeforestart <= (others => '0'); - - - end if; - end process; - - ---------------------------------------------------------------------------- --- Here be dragons (the stuff I didn't touch yet) ---------------------------------------------------------------------------- - - - - -end architecture; diff --git a/vhdl/code/jtag_pulses.vhd b/vhdl/code/jtag_pulses.vhd deleted file mode 100644 index 1f91388..0000000 --- a/vhdl/code/jtag_pulses.vhd +++ /dev/null @@ -1,120 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; - -library work; - -use work.jtag_constants.all; -use work.jtag_misc.all; - -entity jtag_pulses is - generic ( - time_bits : integer := 10 - ); - port ( - CLK_IN : std_logic; - RESET_IN : std_logic; - -- input times - JTAG_CLOCK_TIME1_IN: in std_logic_vector(time_bits -1 downto 0); - JTAG_CLOCK_TIME2_IN: in std_logic_vector(time_bits -1 downto 0); - JTAG_SAMPLE_TIME1_IN: in std_logic_vector(time_bits -1 downto 0); - JTAG_SAMPLE_TIME2_IN: in std_logic_vector(time_bits -1 downto 0); - JTAG_SAMPLE_TIME3_IN: in std_logic_vector(time_bits -1 downto 0); - JTAG_SET_DATA_TIME_IN: in std_logic_vector(time_bits -1 downto 0); - - JTAG_CLOCK_CYCLE_LENGTH_IN: in std_logic_vector(time_bits -1 downto 0); - - -- output pulses - BEGIN_JTAGBITCALC_OUT : out std_logic; - JTAG_CLOCK_PULSE1_OUT : out std_logic; - JTAG_CLOCK_PULSE2_OUT : out std_logic; - JTAG_SAMPLE_PULSE1_OUT : out std_logic; - JTAG_SAMPLE_PULSE2_OUT : out std_logic; - JTAG_SAMPLE_PULSE3_OUT : out std_logic; - JTAG_SET_DATA_PULSE_OUT : out std_logic - - ); -end entity; - -architecture jtag_pulses_arch of jtag_pulses is -signal jtag_counter, jtag_counter_next : unsigned(time_bits-1 downto 0); -signal begin_jtagbitcalc, begin_jtagbitcalc_next : std_logic; -signal jtag_clock_pulse1, jtag_clock_pulse1_next : std_logic; -signal jtag_clock_pulse2, jtag_clock_pulse2_next : std_logic; -signal jtag_sample_pulse1, jtag_sample_pulse1_next : std_logic; -signal jtag_sample_pulse2, jtag_sample_pulse2_next : std_logic; -signal jtag_sample_pulse3, jtag_sample_pulse3_next : std_logic; -signal jtag_set_data_pulse, jtag_set_data_pulse_next : std_logic; -begin ---wordcounter_end <= (others => '1'); -- maximum RAM address - BEGIN_JTAGBITCALC_OUT <= begin_jtagbitcalc; - JTAG_CLOCK_PULSE1_OUT <= jtag_clock_pulse1; - JTAG_CLOCK_PULSE2_OUT <= jtag_clock_pulse2; - JTAG_SAMPLE_PULSE1_OUT <= jtag_sample_pulse1; - JTAG_SAMPLE_PULSE2_OUT <= jtag_sample_pulse2; - JTAG_SAMPLE_PULSE3_OUT <= jtag_sample_pulse3; - JTAG_SET_DATA_PULSE_OUT <= jtag_set_data_pulse; -SYNCHRONOUS: process(CLK_IN, RESET_IN) -begin - if (rising_edge(CLK_IN)) then - if(RESET_IN = '1') then - begin_jtagbitcalc <= '0'; - jtag_clock_pulse1 <= '0'; - jtag_clock_pulse2 <= '0'; - jtag_sample_pulse1 <= '0'; - jtag_sample_pulse2 <= '0'; - jtag_sample_pulse3 <= '0'; - jtag_set_data_pulse <= '0'; - jtag_counter <= (others => '0'); - else - begin_jtagbitcalc <= begin_jtagbitcalc_next; - jtag_clock_pulse1 <= jtag_clock_pulse1_next; - jtag_clock_pulse2 <= jtag_clock_pulse2_next; - jtag_sample_pulse1 <= jtag_sample_pulse1_next; - jtag_sample_pulse2 <= jtag_sample_pulse2_next; - jtag_sample_pulse3 <= jtag_sample_pulse3_next; - jtag_set_data_pulse <= jtag_set_data_pulse_next; - jtag_counter <= jtag_counter_next; - end if; - end if; -end process; - - - -COMB: process (jtag_counter, JTAG_CLOCK_CYCLE_LENGTH_IN, JTAG_CLOCK_TIME1_IN, JTAG_CLOCK_TIME2_IN, JTAG_SAMPLE_TIME1_IN, JTAG_SAMPLE_TIME2_IN, JTAG_SAMPLE_TIME3_IN, JTAG_SET_DATA_TIME_IN ) -begin -jtag_counter_next <= jtag_counter + 1; -begin_jtagbitcalc_next <= '0'; -jtag_clock_pulse1_next <= '0'; -jtag_clock_pulse2_next <= '0'; -jtag_sample_pulse1_next <= '0'; -jtag_sample_pulse2_next <= '0'; -jtag_sample_pulse3_next <= '0'; -jtag_set_data_pulse_next <= '0'; - if(jtag_counter = unsigned(JTAG_CLOCK_CYCLE_LENGTH_IN)-1) then - begin_jtagbitcalc_next <= '1'; - jtag_counter_next <= (others => '0'); -- reset counter - end if; - - if(jtag_counter = unsigned(JTAG_CLOCK_TIME1_IN)) then - jtag_clock_pulse1_next <= '1'; - end if; - if(jtag_counter = unsigned(JTAG_CLOCK_TIME2_IN)) then - jtag_clock_pulse2_next <= '1'; - end if; - if(jtag_counter = unsigned(JTAG_SAMPLE_TIME1_IN)) then - jtag_sample_pulse1_next <= '1'; - end if; - if(jtag_counter = unsigned(JTAG_SAMPLE_TIME2_IN)) then - jtag_sample_pulse2_next <= '1'; - end if; - if(jtag_counter = unsigned(JTAG_SAMPLE_TIME3_IN)) then - jtag_sample_pulse3_next <= '1'; - end if; - if(jtag_counter = unsigned(JTAG_SET_DATA_TIME_IN)) then - jtag_set_data_pulse_next <= '1'; - end if; -end process; - - -end architecture; diff --git a/vhdl/code/jtag_read_m26devid_m10.vhd b/vhdl/code/jtag_read_m26devid_m10.vhd deleted file mode 100644 index d79d0f2..0000000 --- a/vhdl/code/jtag_read_m26devid_m10.vhd +++ /dev/null @@ -1,288 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; - -library work; ---use work.version.all; -use work.jtag_constants.all; -use work.jtag_misc.all; - -entity jtag_read_m26devid_m10 is - generic ( - RAM_JTAG_REGISTERS_DEPTH : integer; - MAX_NUMCHIPS_PLUS_ONE_LD : integer; - MAX_NUMCHIPS : integer; - MAX_NUMCHIPS_LD : integer - ); - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - RAM_JTAG_REGISTERS_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); - RAM_JTAG_REGISTERS_D_IN : in std_logic_vector(31 downto 0); - - -- number of next chip which is not removed from the jtag chain. for chip i ( in range 0...N) this next chip is - -- encoded by the bits NEXT_NOT_REMOVED((i+1)*MAX_NUMCHIPS_LD + MAX_NUMCHIPS_LD-1 downto (i+1)*MAX_NUMCHIPS_LD) - -- which should be interpreted as unsigned - -- the zero'th entry points to the first not removed chip - -- a value of (others => '1') means that no more non-removed chips follow - NEXT_NOT_REMOVED_IN : in std_logic_vector(MAX_NUMCHIPS_PLUS_ONE_LD*(MAX_NUMCHIPS+1)-1 downto 0); - - BEGIN_JTAGBITCALC_IN : in std_logic; - TRIGGER_BEGIN_READ_IN : in std_logic; - - - - IS_DR_BIT_OUT : out std_logic; - IS_FIRSTBIT_OUT : out std_logic; - IS_LASTBIT_OUT : out std_logic; - CHIPNUM_OUT : out std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0); - ENABLE_JTAG_CLOCK_OUT : out std_logic; - LAST_TCK_CYCLE_OUT : out std_logic; - TMS_OUT : out std_logic; - TDI_OUT : out std_logic; - EXPECTED_TDO_OUT : out std_logic; - IDLE_OUT : out std_logic - ); -end entity; - - -architecture jtag_read_m26devid_m10_arch of jtag_read_m26devid_m10 is --- 32 bit dev_id -signal bitcounter, bitcounter_next : unsigned(5-1 downto 0); - --- COPIED FROM jtag_write_m10: --- this state controls the global behaviour. on reset state idle is entered, --- on trigger wait_begin_jtagbitcalc is entered --- when begin_jtagbitcalc is set, state becomes either idle or --- processing and after finished wait_begin_jtagbitcalc is entered again -type state_type is (idle, wait_begin_jtagbitcalc, processing); -signal state, state_next : state_type; --- the substate represents the processing state we are in, the name suffix _pi tells how many clock cycles have been spent up to the current state, processing. i must be smaller than 10 so that with 100MHz system clock the JTAG clock can be operated at 10 MHz. -type substate_type is (none_p1, dr_read_p1 ,dr_read_p2, dr_read_p3, dr_read_p4); -signal substate, substate_next : substate_type; --- COPIED FROM jtag_write_m10: --- operation = "00": JTAG_RESET, operation = "01" : WRITE_IR, operation = "10": SCAN_DR, operation = "11": none --- the operation is set on entering processing state, in setup operation is set to none -signal operation, operation_next : unsigned(1 downto 0); --- COPIED FROM jtag_write_m10, modified --- JTAG_RESET: operation_phase = 0000-0101 : set TMS=1 for JTAG reset --- operation_phase = 0110 : set TMS=0 => Run-Test/Idle --- WRITE_IR: this state should never be reached --- SCAN_DR: operation_phase = 0000 : set TMS=1 => Select-DR-Scan --- operation_phase = 0001 : set TMS=0 => Capture-DR --- operation_phase = 0010 : set TMS=0 => Shift-DR --- operation_phase = 0011 : set TMS=0 => Shift-DR, HERE SHIFTING OF DATA HAPPENS, --- operation_phase = 0100 : set TMS=1 => Exit1-DR, HERE LAST BIT OF IR IS SHIFTED --- operation_phase = 0101 : set TMS=1 => Update-DR --- operation_phase = 0110 : set TMS=0 => Run-Test/Idle --- warning: operation phase may change during processing (because length of register is retrieved from RAM) --- but will settle from setOutputs_p8 on -signal operation_phase, operation_phase_next : unsigned(3 downto 0); - - --- other signals -signal last_tck_cycle, last_tck_cycle_next : std_logic; -signal chipcounter, chipcounter_next : unsigned (MAX_NUMCHIPS_LD-1 downto 0); --- should a JTAG clock pulse be generated this global_jtag_counter cycle? -signal enable_jtag_clock, enable_jtag_clock_next : std_logic; --- JTAG output signal: TDI -signal tdi, tdi_next : std_logic; - --- JTAG output signal: TMS -signal tms, tms_next : std_logic; - -signal is_dr_bit, is_dr_bit_next : std_logic; -signal is_firstbit, is_firstbit_next : std_logic; -signal is_lastbit, is_lastbit_next : std_logic; -signal expected_tdo, expected_tdo_next : std_logic; - -signal ram_jtag_registers_a, ram_jtag_registers_a_next : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); --- the correct slice from NEXT_NOT_REMOVED_IN, depending on the current value of chipcounter -signal nxt_not_removed_chip : unsigned(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0); -signal first_not_removed_chip : unsigned(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0); -constant invalid_chip : unsigned(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0) := (others => '1'); -signal dev_id, dev_id_next : std_logic_vector(31 downto 0); --- INSERTLABEL: signals -begin --- helper signals ---tmp_input_vect <= (others => input_bit); -- doesn't work -IDLE_OUT <= '1' when state = idle else '0'; -ENABLE_JTAG_CLOCK_OUT <= enable_jtag_clock; -LAST_TCK_CYCLE_OUT <= last_tck_cycle; -TMS_OUT <= tms; -TDI_OUT <= tdi; -IS_DR_BIT_OUT <= '1' when operation = "10" and (operation_phase = "0011" or operation_phase = "0100") else '0'; -IS_FIRSTBIT_OUT <= '1' when to_integer(bitcounter) = 0 else '0'; -IS_LASTBIT_OUT <= '1' when to_integer(bitcounter)+1 = 32 else '0'; -CHIPNUM_OUT <= std_logic_vector(chipcounter); -EXPECTED_TDO_OUT <= expected_tdo; -RAM_JTAG_REGISTERS_A_OUT <= ram_jtag_registers_a; -nxt_not_removed_chip <= unsigned(NEXT_NOT_REMOVED_IN((to_integer(chipcounter)+1)*MAX_NUMCHIPS_PLUS_ONE_LD+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto (to_integer(chipcounter)+1)*MAX_NUMCHIPS_PLUS_ONE_LD)); -- first entry points to first not removed chip -first_not_removed_chip <= unsigned(NEXT_NOT_REMOVED_IN(MAX_NUMCHIPS_PLUS_ONE_LD - 1 downto 0)); - -SYNCHRONOUS_MAIN : process (CLK_IN) -begin - if (rising_edge(CLK_IN)) then - if(RESET_IN = '1') then - bitcounter <= (others =>'0'); - chipcounter <= (others =>'0'); - last_tck_cycle <= '0'; - state <= idle; - substate <= none_p1; - enable_jtag_clock <= '0'; - tdi <= '0'; - tms <= '0'; - operation <= "11"; - operation_phase <= "0000"; - is_dr_bit <= '0'; - is_firstbit <= '0'; - is_lastbit <= '0'; - expected_tdo <= '0'; - ram_jtag_registers_a <= (others => '0'); - dev_id <= (others => '0'); - -- INSERTLABEL: SYNCHRONOUS reset - else - bitcounter <= bitcounter_next; - chipcounter <= chipcounter_next; - last_tck_cycle <= last_tck_cycle_next; - state <= state_next; - substate <= substate_next; - enable_jtag_clock <= enable_jtag_clock_next; - tdi <= tdi_next; - tms <= tms_next; - operation <= operation_next; - operation_phase <= operation_phase_next; - is_dr_bit <= is_dr_bit_next; - is_firstbit <= is_firstbit_next; - is_lastbit <= is_lastbit_next; - expected_tdo <= expected_tdo_next; - ram_jtag_registers_a <= ram_jtag_registers_a_next; - dev_id <= dev_id_next; - -- INSERTLABEL: SYNCHRONOUS update - end if; - end if; -end process; - -COMB_MAIN: process(bitcounter, chipcounter, dev_id, last_tck_cycle, state, TRIGGER_BEGIN_READ_IN, BEGIN_JTAGBITCALC_IN, operation, operation_phase, substate, enable_jtag_clock, tdi, tms, RAM_JTAG_REGISTERS_D_IN, expected_tdo, first_not_removed_chip, nxt_not_removed_chip, ram_jtag_registers_a, is_lastbit, is_firstbit, is_dr_bit) -- INSERTLABEL: sensitivity list -begin - bitcounter_next <= bitcounter; - last_tck_cycle_next <= last_tck_cycle; - state_next <= state; - substate_next <= substate; - operation_next <= operation; - operation_phase_next <= operation_phase; - enable_jtag_clock_next <= enable_jtag_clock; - tdi_next <= tdi; - tms_next <= tms; - chipcounter_next <= chipcounter; - dev_id_next <= dev_id; - expected_tdo_next <= expected_tdo; - is_dr_bit_next <= is_dr_bit; - is_firstbit_next <= is_firstbit; - is_lastbit_next <= is_lastbit; - ram_jtag_registers_a_next <= ram_jtag_registers_a; - - -- INSERTLABEL: COMB defaults - case state is - when idle => - if(TRIGGER_BEGIN_READ_IN = '1') then - state_next <= wait_begin_jtagbitcalc; - operation_next <= "11"; -- none - - end if; - when wait_begin_jtagbitcalc => - if(BEGIN_JTAGBITCALC_IN='1') then - state_next <= processing; - operation_phase_next <= operation_phase + 1; - substate_next <= none_p1; -- do nothing other than output tms=1 - if(operation = "11") then - -- last operation was none - operation_next <= "00"; -- JTAG_RESET - operation_phase_next <= "0000"; -- Bit Nr. 0 - enable_jtag_clock_next <= '1'; -- enable JTAG clock for WRITE operation - elsif(operation = "00") then - -- last operation was: JTAG_RESET - if(operation_phase = "0110") then - operation_next <= "10"; -- skip WRITE_IR, because after JTAG_RESET, DEV_ID register is selected automatically - operation_phase_next <= "0000"; - bitcounter_next <= (others => '0'); - chipcounter_next <= first_not_removed_chip; - end if; - elsif(operation = "01") then - -- this state should never be reached - state_next <= idle; - elsif(operation = "10") then - --last operation was: WRITE_DR - if(operation_phase = "0010") then -- Shift-DR - substate_next <= dr_read_p1; - elsif(operation_phase = "0011") then -- Shift-DR - -- stay in this phase until the dr of all chips is read out - bitcounter_next <= bitcounter + 1; - operation_phase_next <= operation_phase; - substate_next <= dr_read_p1; -- fill dr with zeros - -- assume 32-bit DEV_ID per chip - if(nxt_not_removed_chip /= invalid_chip) then - if(to_integer(bitcounter) >= 31) then - chipcounter_next <= nxt_not_removed_chip; - bitcounter_next <= (others => '0'); - substate_next <= dr_read_p1; - end if; - else - if (to_integer(bitcounter) >= 30) then - -- if the current chip is the last chip and we finish the register with the next bit - operation_phase_next <= operation_phase + 1; - -- bitcounter_next <= bitcounter + 1; - end if; - end if; - elsif(operation_phase = "0101") then -- Update DR - last_tck_cycle_next <= '1'; - elsif(operation_phase = "0110") then -- Run-Test-Idle - enable_jtag_clock_next <= '0'; -- disable JTAG clock for WRITE operation - last_tck_cycle_next <= '0'; - elsif(operation_phase = "0111") then -- Wait for Data to be written to RAM - state_next <= idle; - end if; - end if; - end if; - when processing => - -- set TMS, copied from jtag_write_m10, modified - tms_next <= '1'; -- JTAG_RESET if operation = "00" - if(operation = "00") then - if(operation_phase = "0110") then -- go into Run-Test/Idle - tms_next <= '0'; - end if; - elsif(operation = "10") then -- Scan DR - if(operation_phase = "0000") then - tms_next <= '1'; - elsif(operation_phase = "0100") then -- enter Exit1-DR - tms_next <= '1'; - elsif(operation_phase = "0101") then -- enter Update-DR - tms_next <= '1'; - else - tms_next <= '0'; - end if; - end if; - tdi_next <= '0'; - case substate is - when none_p1 => - state_next <= wait_begin_jtagbitcalc; - when dr_read_p1 => - ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(chipcounter); -- chip address - ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(to_unsigned(1, RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD)); -- DEV_ID - tdi_next <= '0'; - substate_next <= dr_read_p2; - when dr_read_p2 => - -- wait one clock cycle - substate_next <= dr_read_p3; - when dr_read_p3 => - dev_id_next <= RAM_JTAG_REGISTERS_D_IN; - substate_next <= dr_read_p4; - when dr_read_p4 => - expected_tdo_next <= dev_id(to_integer(bitcounter)); - state_next <= wait_begin_jtagbitcalc; - end case; - end case; -end process; - -end architecture; - diff --git a/vhdl/code/jtag_tck_out_component.vhd b/vhdl/code/jtag_tck_out_component.vhd deleted file mode 100644 index be6c01a..0000000 --- a/vhdl/code/jtag_tck_out_component.vhd +++ /dev/null @@ -1,52 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; ---USE IEEE.std_logic_ARITH.ALL; ---USE IEEE.std_logic_UNSIGNED.ALL; -USE IEEE.numeric_std.ALL; - -library work; ---use work.trb_net_std.all; ---use work.trb_net_components.all; --- use work.trb_net16_hub_func.all; ---use work.version.all; -use work.jtag_constants.all; - -entity jtag_tck_out_component is - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - JTAG_CLOCK_PULSE1_IN : in std_logic; - JTAG_CLOCK_PULSE2_IN : in std_logic; - ENABLE_JTAG_TCK_IN : in std_logic; - - TCK_OUT : out std_logic - ); -end entity; - -architecture jtag_tck_out_component_arch of jtag_tck_out_component is -signal tck, tck_next : std_logic; -begin -TCK_OUT <= tck; - -process(CLK_IN) -begin - if(rising_edge(CLK_IN)) then - if(RESET_IN='1') then - tck <= '0'; - else - tck <= tck_next; - end if; - end if; -end process; - -COMB_MAIN: process(ENABLE_JTAG_TCK_IN, JTAG_CLOCK_PULSE1_IN, JTAG_CLOCK_PULSE2_IN, tck) -begin - tck_next <= tck; - if((JTAG_CLOCK_PULSE1_IN = '1') and (ENABLE_JTAG_TCK_IN = '1')) then - tck_next <= '1'; - elsif(JTAG_CLOCK_PULSE2_IN = '1') then - tck_next <= '0'; - end if; -end process; -end architecture; \ No newline at end of file diff --git a/vhdl/code/jtag_tdo_compare_count_m10.vhd b/vhdl/code/jtag_tdo_compare_count_m10.vhd deleted file mode 100644 index b86ada6..0000000 --- a/vhdl/code/jtag_tdo_compare_count_m10.vhd +++ /dev/null @@ -1,224 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; - -library work; ---use work.trb_net_std.all; ---use work.trb_net_components.all; --- use work.trb_net16_hub_func.all; ---use work.version.all; -use work.jtag_constants.all; - --- counts for one register of one chip: --- sampling errors : those cases in which not all sampled values are equal. --- matches : sampled value = expected value --- differences : sampled value /= expected value --- --- the following equation should hold: --- matches+differences = register size --- RAM2: stores for each register --- MCOUNT = number of bits for which the sampled value --- matches the expected value --- DCOUNT (16 lower bits of DSECOUNT)= number of bits for which the sampled value --- does not match the expected value --- SECOUNT (16 higher bits of DSECOUNT) = number of bits which had an unstable value --- (not all sampled values equal) --- this should of course be 0 --- - - -entity jtag_tdo_compare_count_m10 is - generic ( - MAX_NUMCHIPS_LD : integer; - MAX_REGISTERS_PLUS_ONE_LD : integer; - RAM_MATCH_DIFF_COUNT_DEPTH : integer; - MAX_REGLEN_LD : integer - ); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- pulse always comes in same interval (at fixed distance to begin_jtag_bitcalc) - -- sample_pulse3 delayed by one clock cycle - SAMPLE_PULSE3_D1_IN : in std_logic; - -- inputs from jtag_write_m10/jtag_read_m26devid - -- chipcount as unsigned - CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD -1 downto 0); - -- active register as unsigned, 0=read dev_id, 1,2,...=register 0,1,... of jtag_write_m10 - REGNUM_IN : in std_logic_vector(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0); - - ENABLE_COUNTERS_IN : in std_logic; - -- firstbit signal: reset counters before sampling this bit - IS_FIRSTBIT_IN : in std_logic; - -- finish signal: dataout => RAM1b, compareout => RAM2 - IS_LASTBIT_IN : in std_logic; - - TDO_EXPECTED_IN : in std_logic; - TDO_SAMPLED_IN : in std_logic; - TDO_SAMPLING_ERROR_IN : in std_logic; - - -- RAM2 - RAM_MATCH_DIFF_COUNT_A_OUT : out std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0); - --RAM_MATCH_DIFF_COUNT_D_IN : in std_logic_vector(31 downto 0); - RAM_MATCH_DIFF_COUNT_WE_OUT : out std_logic; - RAM_MATCH_DIFF_COUNT_D_OUT : out std_logic_vector(31 downto 0) - - ---- internal error out: signals that read/write sampling has been mixed - --INTERNAL_ERROR_OUT : out std_logic - - -- Monitoring: 16 bit usable per FIFO, depth=512 = 8192 bits, this is enough for a 7 Mi26 chain (registers 1152 bits each) - --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0); - --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0); - ); -end entity; - -architecture jtag_tdo_compare_count_m10_arch of jtag_tdo_compare_count_m10 is - --- state machine for main controlling state machine for TDO sampling: - type state_type is (WAIT_END_SAMPLING, COUNT_AND_TRIGGER_WRITE_RAM); - signal state, state_next : state_type; - - -- counters for SAMPLING_ERROR: value changed in between sampling points - -- COMPARE_NEQ: sampled value is not equal expected value - -- COMPARE_EQUAL: sampled value is equal expected value - -- need at maximum to count to one register length which is 1152 for Mimosa26 - signal sampling_error_count, sampling_error_count_next : unsigned(MAX_REGLEN_LD-1 downto 0); - signal compare_neq_count, compare_neq_count_next : unsigned(MAX_REGLEN_LD-1 downto 0); - signal compare_equal_count, compare_equal_count_next : unsigned(MAX_REGLEN_LD-1 downto 0); - - -- write reg_counts, pulse to start state machine with state ram2_write_state - signal write_reg_counts : std_logic; - --- state machine for write to RAM2: - type ram2_write_state_type is (RWC_IDLE, WRITE_MCOUNT, WRITE_DSECOUNT -- first line : writing counter values to RAM2 - -- write_dr_mcount: write compare_equal_count - -- write_dr_dsecount: write compare_neq_count (low 16 bit of RAM word, DCOUNT) and compare_sampling_error (high 16 bit of RAM word, SECOUNT) - ); - signal ram2_write_state, ram2_write_state_next : ram2_write_state_type; - --signal ram2_regnum, ram2_regnum_next: unsigned(MAX_REGISTERS_LD -1 downto 0); - -- RAM2 driving signals - signal ram_match_diff_count_a, ram_match_diff_count_a_next : std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0); - signal ram_match_diff_count_data, ram_match_diff_count_data_next : std_logic_vector(31 downto 0); - signal ram_match_diff_count_we, ram_match_diff_count_we_next : std_logic; - -begin -RAM_MATCH_DIFF_COUNT_A_OUT <= ram_match_diff_count_a; -RAM_MATCH_DIFF_COUNT_D_OUT <= ram_match_diff_count_data; -RAM_MATCH_DIFF_COUNT_WE_OUT <= ram_match_diff_count_we; - - - -SYNCHRONOUS_MAIN : process (CLK_IN) -begin - if (rising_edge(CLK_IN)) then - if(RESET_IN = '1') then - state <= WAIT_END_SAMPLING; - sampling_error_count <= (others =>'0'); - compare_neq_count <= (others =>'0'); - compare_equal_count <= (others =>'0'); - else - state <= state_next; - sampling_error_count <= sampling_error_count_next; - compare_neq_count <= compare_neq_count_next; - compare_equal_count <= compare_equal_count_next; - end if; - end if; -end process; - -COMB_MAIN: process(state, SAMPLE_PULSE3_D1_IN, ENABLE_COUNTERS_IN, TDO_SAMPLED_IN, TDO_SAMPLING_ERROR_IN, -TDO_EXPECTED_IN, IS_FIRSTBIT_IN, IS_LASTBIT_IN, sampling_error_count, compare_neq_count, compare_equal_count) -begin - write_reg_counts <= '0'; - sampling_error_count_next <= sampling_error_count; - compare_neq_count_next <= compare_neq_count; - compare_equal_count_next <= compare_equal_count; - state_next <= state; - case state is - when WAIT_END_SAMPLING => - -- this is the idle state, on SAMPLE_PULSE3 check the ENABLE_COUNTERS signal - -- first sample taken leaving this state - if (SAMPLE_PULSE3_D1_IN ='1') then - -- if the bit should be counted - if(ENABLE_COUNTERS_IN = '1') then - if(IS_FIRSTBIT_IN = '1') then - sampling_error_count_next <= (others =>'0'); - compare_neq_count_next <= (others =>'0'); - compare_equal_count_next <= (others =>'0'); - end if; - state_next <= count_and_trigger_write_ram; - end if; - end if; - -- trigger RAM writes, increment counts - when COUNT_AND_TRIGGER_WRITE_RAM => - if(IS_LASTBIT_IN = '1') then - write_reg_counts <= '1'; - end if; - -- increment counts: sampling errors, equal / not equal counts - if(TDO_SAMPLING_ERROR_IN = '1') then - sampling_error_count_next <= sampling_error_count + 1; - end if; - if(TDO_SAMPLED_IN = TDO_EXPECTED_IN) then - compare_equal_count_next <= compare_equal_count + 1; - else - compare_neq_count_next <= compare_neq_count + 1; - end if; - state_next <= wait_end_sampling; - end case; -end process; - -SYNCHRONOUS_RAM2_WRITE : process (CLK_IN) -begin - if (rising_edge(CLK_IN)) then - if(RESET_IN = '1') then - ram2_write_state <= RWC_IDLE; - ram_match_diff_count_we <= '0'; - ram_match_diff_count_a <= (others => '0'); - ram_match_diff_count_data <= (others => '0'); --- ram2_regnum <= (others => '0'); - else - ram2_write_state <= ram2_write_state_next; - ram_match_diff_count_we <= ram_match_diff_count_we_next; - ram_match_diff_count_a <= ram_match_diff_count_a_next; - ram_match_diff_count_data <= ram_match_diff_count_data_next; --- ram2_regnum <= ram2_regnum_next; - end if; - end if; -end process; - -COMB_RAM2_WRITE: process(ram2_write_state, ram_match_diff_count_a, ram_match_diff_count_data, write_reg_counts, REGNUM_IN, CHIPNUM_IN, compare_equal_count, compare_neq_count, sampling_error_count) -begin - ram2_write_state_next <= ram2_write_state; - ram_match_diff_count_we_next <= '0'; - ram_match_diff_count_a_next <= ram_match_diff_count_a; - ram_match_diff_count_data_next <= ram_match_diff_count_data; - - case ram2_write_state is - when RWC_IDLE => - if(write_reg_counts = '1') then --- ram2_regnum_next <= REGNUM_IN; - ram2_write_state_next <= write_mcount; - end if; - when WRITE_MCOUNT => - ram_match_diff_count_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD) <= CHIPNUM_IN; -- chip address - --ram_match_diff_count_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD-1 downto MAX_REGISTERS_PLUS_ONE_LD+1) <= (others => '0'); -- this could possibly be 0 bits, does this work, then? (gives a warning in modelsim) - --ram_match_diff_count_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD downto 0) <= std_logic_vector(2*unsigned(REGNUM_IN)); - ram_match_diff_count_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD-1 downto 1) <= REGNUM_IN; - ram_match_diff_count_a_next(0) <= '0'; - ram_match_diff_count_data_next(31 downto MAX_REGLEN_LD) <= (others => '0'); - ram_match_diff_count_data_next(MAX_REGLEN_LD-1 downto 0) <= std_logic_vector(compare_equal_count); - ram_match_diff_count_we_next <= '1'; - ram2_write_state_next <= WRITE_DSECOUNT; - when WRITE_DSECOUNT => - ram_match_diff_count_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD) <= CHIPNUM_IN; -- chip address - --ram_match_diff_count_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(2*unsigned(REGNUM_IN)+1); - ram_match_diff_count_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD-1 downto 1) <= REGNUM_IN; - ram_match_diff_count_a_next(0) <= '1'; - ram_match_diff_count_data_next(31 downto MAX_REGLEN_LD+16) <= (others => '0'); - ram_match_diff_count_data_next(MAX_REGLEN_LD-1+16 downto 16) <= std_logic_vector(sampling_error_count); - ram_match_diff_count_data_next(15 downto MAX_REGLEN_LD) <= (others => '0'); - ram_match_diff_count_data_next(MAX_REGLEN_LD-1 downto 0) <= std_logic_vector(compare_neq_count); - ram_match_diff_count_we_next <= '1'; - ram2_write_state_next <= rwc_idle; - end case; -end process; - -end architecture; diff --git a/vhdl/code/jtag_tdo_compare_counttotal_noram_m10.vhd b/vhdl/code/jtag_tdo_compare_counttotal_noram_m10.vhd deleted file mode 100644 index 9e0fbf1..0000000 --- a/vhdl/code/jtag_tdo_compare_counttotal_noram_m10.vhd +++ /dev/null @@ -1,134 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; - -library work; ---use work.trb_net_std.all; ---use work.trb_net_components.all; --- use work.trb_net16_hub_func.all; ---use work.version.all; -use work.jtag_constants.all; - --- counts for one register of one chip: --- sampling errors : those cases in which not all sampled values are equal. --- matches : sampled value = expected value --- differences : sampled value /= expected value --- --- the following equation should hold: --- matches+differences = register size --- RAM2: stores for each register --- MCOUNT = number of bits for which the sampled value --- matches the expected value --- DCOUNT (16 lower bits of DSECOUNT)= number of bits for which the sampled value --- does not match the expected value --- SECOUNT (16 higher bits of DSECOUNT) = number of bits which had an unstable value --- (not all sampled values equal) --- this should of course be 0 --- - - -entity jtag_tdo_compare_counttotal_noram_m10 is - generic ( - numcounts : integer := 3; - se_counter_width : integer := 32; -- sampling error counter width - diff_counter_width : integer := 16 -- counter width for number of runs in which there were differences - ); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- pulse always comes in same interval (at fixed distance to begin_jtag_bitcalc) - -- sample_pulse3 delayed by one clock cycle - SAMPLE_PULSE3_D1_IN : in std_logic; - -- should this bit be counted as error if not matching expected value? (e.g. is this a dr bit while writing register or reading device id?) - ENABLE_COUNTERS_IN : in std_logic; - - TDO_EXPECTED_IN : in std_logic; - TDO_SAMPLED_IN : in std_logic; - TDO_SAMPLING_ERROR_IN : in std_logic; - BEGIN_COUNT_I_IN : in std_logic_vector(numcounts-1 downto 0); - END_COUNT_I_IN : in std_logic_vector(numcounts-1 downto 0); - - -- should be zero if timing is good - SAMPLING_ERRORS_COUNT_OUT : out std_logic_vector(diff_counter_width-1 downto 0); - COUNTS_OUT : out std_logic_vector(numcounts*diff_counter_width-1 downto 0); - LAST_VALUES_OUT : out std_logic_vector(numcounts-1 downto 0) - - ); -end entity; - -architecture jtag_tdo_compare_counttotal_noram_m10_arch of jtag_tdo_compare_counttotal_noram_m10 is - --- state machine for main controlling state machine for TDO sampling: - signal count_i_errors_occured : std_logic_vector(numcounts-1 downto 0); - signal count_i_lookingforerrors : std_logic_vector(numcounts-1 downto 0); - - signal sampling_error_count : unsigned(se_counter_width-1 downto 0); - type counts_array_t is array (numcounts-1 downto 0) of unsigned(diff_counter_width-1 downto 0); - signal counts : counts_array_t; - signal SAMPLE_PULSE3_D2 : std_logic; -begin -COUNTS_OUT_ALL: for i in 0 to numcounts-1 generate - COUNTS_OUT(i*diff_counter_width+diff_counter_width-1 downto i*diff_counter_width) <= std_logic_vector(counts(i)); -end generate; - -SAMPLING_ERRORS_COUNT_OUT <= std_logic_vector(sampling_error_count); -LAST_VALUES_OUT <= count_i_errors_occured; - -ONE_PROC: process (CLK_IN) -variable i : integer; -begin - if (rising_edge(CLK_IN)) then - ALL_PROC: for i in 0 to numcounts-1 loop - if(ENABLE_COUNTERS_IN = '1') then - if(SAMPLE_PULSE3_D2 = '1') then -- when this pulse arrives, the tdo-input from the last chip has been sampled - if(not(TDO_SAMPLED_IN = TDO_EXPECTED_IN)) then - if(count_i_lookingforerrors(i) = '1') then - -- remember that an error has occured since begin signal - count_i_errors_occured(i) <= '1'; - end if; - end if; - end if; - end if; - - if(BEGIN_COUNT_I_IN(i) = '1') then - -- reset states if begin signal received - count_i_lookingforerrors(i) <= '1'; - count_i_errors_occured(i) <= '0'; - end if; - if(END_COUNT_I_IN(i) = '1') then - -- on end signal update counter - count_i_lookingforerrors(i) <= '0'; -- stop looking for errors - if(count_i_errors_occured(i) = '1') then - -- increment count - counts(i) <= counts(i) + 1; - end if; - end if; - if(RESET_IN = '1') then - count_i_errors_occured(i) <= '0'; - count_i_lookingforerrors(i) <= '0'; - counts(i) <= (others => '0'); - end if; - end loop; - end if; -end process; - -SAMPLING_ERRORS : process (CLK_IN) -variable i : integer; -begin - if (rising_edge(CLK_IN)) then - if(SAMPLE_PULSE3_D2 = '1') then - if(TDO_SAMPLING_ERROR_IN = '1') then - sampling_error_count <= sampling_error_count + 1; - end if; - end if; - -- delayed pulse - SAMPLE_PULSE3_D2 <= SAMPLE_PULSE3_D1_IN; - if(RESET_IN = '1') then - sampling_error_count <= (others => '0'); - end if; - end if; - -end process; - - -end architecture; diff --git a/vhdl/code/jtag_tdo_data_to_ram_m10.vhd b/vhdl/code/jtag_tdo_data_to_ram_m10.vhd deleted file mode 100644 index ae64bdc..0000000 --- a/vhdl/code/jtag_tdo_data_to_ram_m10.vhd +++ /dev/null @@ -1,209 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; - -library work; ---use work.trb_net_std.all; ---use work.trb_net_components.all; --- use work.trb_net16_hub_func.all; ---use work.version.all; -use work.jtag_constants.all; - --- RAM1b: stores the data register values --- read out while writing (so the old values this is) to a RAM with the --- same layout as the RAM with the remotely configurable register contents. --- NOTE: the inputs don't need to be buffered again, as they change directly after SAMPLE_PULSE3 and this entity needs the inputs (chipnum_in for example) at maximum ~ 4 clock cycles after SAMPLE_PULSE3_D1 to operate --- NOTE: this RAM is purely for debugging purposes, and can be removed by --- by setting the generic enable_ram1b := 0 --- then the compiler should optimize away the constantly idle state machine --- for writing to the ram, but i'm not sure if this works - - - -entity jtag_tdo_data_to_ram_m10 is - generic ( - enable_ram1b : std_logic := '1'; - MAX_NUMCHIPS_LD : integer; - MAX_REGISTERS_PLUS_ONE_LD : integer; - MAX_REGLEN_LD : integer; - RAM_JTAG_REGISTERS_DEPTH : integer - ); - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - SAMPLE_PULSE3_D1_IN : in std_logic; - -- active chip as unsigned - CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD -1 downto 0); - -- active register as unsigned, 0=read dev_id, 1,2,...=register 0,1,... of jtag_write_m10 - REGNUM_IN : in std_logic_vector(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0); - - -- dataout => RAM1b - ENABLE_DATAOUT_IN : in std_logic; - IS_FIRSTBIT_IN : in std_logic; - IS_LASTBIT_IN : in std_logic; - TDO_SAMPLED_IN : in std_logic; - -- RAM1b - RAM_JTAG_REGISTERS_READOUT_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); - RAM_JTAG_REGISTERS_READOUT_D_IN : in std_logic_vector(31 downto 0); - RAM_JTAG_REGISTERS_READOUT_WE_OUT : out std_logic; - RAM_JTAG_REGISTERS_READOUT_D_OUT : out std_logic_vector(31 downto 0) - - -- Monitoring: 16 bit usable per FIFO, depth=512 = 8192 bits, this is enough for a 7 Mi26 chain (registers 1152 bits each) - --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0); - --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0); - ); -end entity; - -architecture jtag_tdo_data_to_ram_m10_arch of jtag_tdo_data_to_ram_m10 is - --- state machine for main controlling state machine for TDO sampling: - type state_type is (S_WAIT_BEGIN_SAMPLE, S_TRIGGER_RAM_WRITE); - signal state, state_next : state_type; - - -- store one 32bit word to write to RAM1b - signal data, data_next: std_logic_vector(31 downto 0); - - -- the bit we are at in the current chip register. used to address memory, and to write to the right bit of the "data" word. - signal dataout_bitcount, dataout_bitcount_next : unsigned(MAX_REGLEN_LD-1 downto 0); - --- write data register or device id to RAM, pulses to start state machine with state ram1b_write_state - signal write_dr, write_dev_id : std_logic; --- -- write reg_counts, pulse to start state machine with state ram2_write_state --- signal write_reg_counts : std_logic; - - --- state machine for read/write to RAM1b: - type ram1b_write_state_type is (RW_IDLE, RW_READ_DR_ADDR, RW_WAIT_READ_DR_ADDR, RW_WRITE_DR_DATA, -- first line : writing to data register in RAM1b - RW_WRITE_DEV_ID); -- second line: writing dev id to fixed address in memory area of chip in RAM1b - signal ram1b_write_state, ram1b_write_state_next : ram1b_write_state_type; - - -- dr pointer, used to address register in RAM1b - signal dr_pointer, dr_pointer_next : unsigned(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0); - - -- RAM1b driving signals - signal ram_jtag_registers_readout_a, ram_jtag_registers_readout_a_next : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); - signal ram_jtag_registers_readout_data, ram_jtag_registers_readout_data_next : std_logic_vector(31 downto 0); - signal ram_jtag_registers_readout_wr, ram_jtag_registers_readout_wr_next : std_logic; - signal ram_jtag_registers_readout_data_in_signal : std_logic_vector(31 downto 0); - -begin -RAM_JTAG_REGISTERS_READOUT_A_OUT <= ram_jtag_registers_readout_a when enable_ram1b = '1' else (others => '0'); -RAM_JTAG_REGISTERS_READOUT_D_OUT <= ram_jtag_registers_readout_data when enable_ram1b = '1' else (others => '0'); -RAM_JTAG_REGISTERS_READOUT_WE_OUT <= ram_jtag_registers_readout_wr when enable_ram1b = '1' else '0'; -ram_jtag_registers_readout_data_in_signal <= RAM_JTAG_REGISTERS_READOUT_D_IN when enable_ram1b = '1' else (others => '0'); - -SYNCHRONOUS_MAIN : process (CLK_IN) -begin - if (rising_edge(CLK_IN)) then - if(RESET_IN = '1') then - state <= S_WAIT_BEGIN_SAMPLE; - data <= (others => '0'); - dataout_bitcount <= (others => '0'); - else - state <= state_next; - data <= data_next; - dataout_bitcount <= dataout_bitcount_next; - end if; - end if; -end process; - -COMB_MAIN: process(state, SAMPLE_PULSE3_D1_IN, REGNUM_IN, IS_FIRSTBIT_IN, IS_LASTBIT_IN, TDO_SAMPLED_IN, data, dataout_bitcount, ENABLE_DATAOUT_IN) -begin - write_dr <= '0'; - write_dev_id <= '0'; - data_next <= data; - dataout_bitcount_next <= dataout_bitcount; - state_next <= state; - - case state is - when S_WAIT_BEGIN_SAMPLE => - -- this is the idle state, on SAMPLE_PULSE3_D1_IN check the ENABLE_DATAOUT signal - -- first sample taken leaving this state - if (SAMPLE_PULSE3_D1_IN ='1') then - -- if the bit should be counted - if(ENABLE_DATAOUT_IN = '1') then - if(IS_FIRSTBIT_IN = '1') then - data_next <= (others =>'0'); - dataout_bitcount_next <= (others =>'0'); - else - -- if next word starts, clear old data - if(to_integer(dataout_bitcount(4 downto 0))=31) then - data_next <= (others => '0'); - end if; - dataout_bitcount_next <= dataout_bitcount + 1; - end if; - state_next <= S_TRIGGER_RAM_WRITE; - end if; - end if; - -- set data, trigger RAM writes - when S_TRIGGER_RAM_WRITE => - data_next(to_integer(dataout_bitcount(4 downto 0))) <= TDO_SAMPLED_IN; - if((to_integer(dataout_bitcount(4 downto 0)) = 31) or IS_LASTBIT_IN = '1') then - if(to_integer(unsigned(REGNUM_IN)) = 0) then - write_dev_id <= '1'; - else - write_dr <= '1'; - end if; - end if; - state_next <= S_WAIT_BEGIN_SAMPLE; - end case; -end process; - - -SYNCHRONOUS_RAM1B_WRITE : process (CLK_IN) -begin - if (rising_edge(CLK_IN)) then - if(RESET_IN = '1') then - ram1b_write_state <= RW_IDLE; - ram_jtag_registers_readout_a <= (others => '0'); - ram_jtag_registers_readout_data <= (others => '0'); - ram_jtag_registers_readout_wr <= '0'; - dr_pointer <= (others => '0'); - else - ram1b_write_state <= ram1b_write_state_next; - ram_jtag_registers_readout_a <= ram_jtag_registers_readout_a_next; - ram_jtag_registers_readout_data <= ram_jtag_registers_readout_data_next; - ram_jtag_registers_readout_wr <= ram_jtag_registers_readout_wr_next; - dr_pointer <= dr_pointer_next; - end if; - end if; -end process; - -COMB_RAM1B_WRITE: process(ram1b_write_state, ram_jtag_registers_readout_a, ram_jtag_registers_readout_data, dr_pointer, write_dr, write_dev_id, CHIPNUM_IN, REGNUM_IN, data, ram_jtag_registers_readout_data_in_signal, dataout_bitcount ) -begin - ram1b_write_state_next <= ram1b_write_state; - ram_jtag_registers_readout_a_next <= ram_jtag_registers_readout_a; - ram_jtag_registers_readout_data_next <= ram_jtag_registers_readout_data; - ram_jtag_registers_readout_wr_next <= '0'; - dr_pointer_next <= dr_pointer; - case ram1b_write_state is - when RW_IDLE => - if(write_dr = '1') then - ram_jtag_registers_readout_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(CHIPNUM_IN); -- chip address - ram_jtag_registers_readout_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto MAX_REGISTERS_PLUS_ONE_LD+1) <= (others => '0'); - ram_jtag_registers_readout_a_next(MAX_REGISTERS_PLUS_ONE_LD downto 1) <= REGNUM_IN; -- DR Pointer (REGNUM_IN is write_register+1), multiply that by two - ram_jtag_registers_readout_a_next(0) <= '0'; -- DR Pointer (REGNUM_IN is write_register+1), multiply that by two - ram1b_write_state_next <= RW_READ_DR_ADDR; - elsif(write_dev_id = '1') then - ram1b_write_state_next <= RW_WRITE_DEV_ID; - end if; - when RW_READ_DR_ADDR => - ram1b_write_state_next <= RW_WAIT_READ_DR_ADDR; - when RW_WAIT_READ_DR_ADDR => - dr_pointer_next <= unsigned(ram_jtag_registers_readout_data_in_signal(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0)); - ram1b_write_state_next <= RW_WRITE_DR_DATA; - when RW_WRITE_DR_DATA => - ram_jtag_registers_readout_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(CHIPNUM_IN); -- chip address - ram_jtag_registers_readout_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(dr_pointer+dataout_bitcount(MAX_REGLEN_LD-1 downto 5)); -- DR word address - ram_jtag_registers_readout_data_next <= data; - ram_jtag_registers_readout_wr_next <= '1'; - ram1b_write_state_next <= RW_IDLE; - when RW_WRITE_DEV_ID => - ram_jtag_registers_readout_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(CHIPNUM_IN); -- chip address - ram_jtag_registers_readout_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(to_unsigned(1,RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD)); -- reserved: DEV_ID - ram_jtag_registers_readout_data_next <= data; - ram_jtag_registers_readout_wr_next <= '1'; - ram1b_write_state_next <= RW_IDLE; - end case; -end process; -end architecture; diff --git a/vhdl/code/jtag_tdo_sample.vhd b/vhdl/code/jtag_tdo_sample.vhd deleted file mode 100644 index e4fc70c..0000000 --- a/vhdl/code/jtag_tdo_sample.vhd +++ /dev/null @@ -1,110 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; - -library work; ---use work.trb_net_std.all; ---use work.trb_net_components.all; --- use work.trb_net16_hub_func.all; ---use work.version.all; -use work.jtag_constants.all; - --- this entity samples TDO at three time points --- given by pulses SAMPLE_PULSE1_IN, SAMPLE_PULSE2_IN, SAMPLE_PULSE3_IN --- it always takes the value of the middle point (at SAMPLE_PULSE2_IN), --- but signals a sampling error if not all sampled values are equal --- output is updated two clock cycles after SAMPLE_PULSE3_IN is 1 - - - - -entity jtag_tdo_sample is - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- pulse always comes in same interval (at fixed distance to begin_jtag_bitcalc) - -- the first sample is taken directly after this pulse - SAMPLE_PULSE1_IN : in std_logic; - SAMPLE_PULSE2_IN : in std_logic; - SAMPLE_PULSE3_IN : in std_logic; - - -- TDO signal, which is to be sampled - TDO_IN : in std_logic; - -- sampled value of TDO - TDO_SAMPLED_OUT : out std_logic; - -- sampling error - SAMPLING_ERROR_OUT : out std_logic - --SAMPLING_FINISHED_PULSE_OUT : out std_logic; - ); -end entity; - -architecture jtag_tdo_sample_arch of jtag_tdo_sample is - --- state machine for main controlling state machine for TDO sampling: - type state_type is (WAIT_SAMPLE_PULSES, FINISH_SAMPLING); - signal state, state_next : state_type; - - -- the sampled TDO line at times sample_pulse1 + 1, sample_pulse2 + 1, sample_pulse3 + 1 - signal sampled, sampled_next : std_logic_vector(2 downto 0); - -- updated 2 clocks after sample_pulse3 occurs - signal sampling_error, sampling_error_next : std_logic; - signal tdo_sampled, tdo_sampled_next : std_logic; - -begin ---SAMPLING_FINISHED_PULSE_OUT <= sampling_finished_pulse; -SAMPLING_ERROR_OUT <= sampling_error; -TDO_SAMPLED_OUT <= tdo_sampled; - -SYNCHRONOUS_MAIN : process (CLK_IN) -begin - if (rising_edge(CLK_IN)) then - if(RESET_IN = '1') then - state <= WAIT_SAMPLE_PULSES; - sampled <= (others => '0'); --- sampling_finished_pulse <= '0'; - tdo_sampled <= '0'; - sampling_error <= '0'; - else - state <= state_next; - sampled <= sampled_next; --- sampling_finished_pulse <= sampling_finished_pulse_next; - tdo_sampled <= tdo_sampled_next; - sampling_error <= sampling_error_next; - end if; - end if; -end process; - -COMB_MAIN: process(state, SAMPLE_PULSE1_IN, SAMPLE_PULSE2_IN, SAMPLE_PULSE3_IN, TDO_IN, sampled, tdo_sampled, sampling_error) -begin - state_next <= state; - sampled_next <= sampled; - sampling_error_next <= sampling_error; - tdo_sampled_next <= tdo_sampled; --- sampling_finished_pulse_next <= '0'; - case state is - when WAIT_SAMPLE_PULSES => - -- this is the idle state, on BEGIN_SAMPLE_IN check the ENABLE_* signals - -- first sample taken leaving this state - if (SAMPLE_PULSE1_IN ='1') then - sampled_next(0) <= TDO_IN; - end if; - if (SAMPLE_PULSE2_IN ='1') then - sampled_next(1) <= TDO_IN; - end if; - if (SAMPLE_PULSE3_IN ='1') then - sampled_next(2) <= TDO_IN; - state_next <= FINISH_SAMPLING; - end if; - -- set sampling_error - when FINISH_SAMPLING => - if(sampled(2) = sampled(1) and sampled(1) = sampled(0) ) then - sampling_error_next <= '0'; - else - sampling_error_next <= '1'; - end if; - tdo_sampled_next <= sampled(1); --- sampling_finished_pulse_next <= '1'; - state_next <= WAIT_SAMPLE_PULSES; - end case; -end process; -end architecture; diff --git a/vhdl/code/jtag_update_error_counts_ram3a.vhd b/vhdl/code/jtag_update_error_counts_ram3a.vhd deleted file mode 100644 index c6896b7..0000000 --- a/vhdl/code/jtag_update_error_counts_ram3a.vhd +++ /dev/null @@ -1,522 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; - -library work; -use work.jtag_constants.all; -use work.jtag_misc.all; ---use work.monitor_config.all; - --- this entity adds 1 to the error counts in RAM3a, for those registers in which errors occured. --- it is a simple implementation, not looking at the number of chips configured, --- simply processing the entire memory, thereby going to the maximum number of chips (2**MAX_NUMCHIPS_LD) and the maximum number of registers ( MAX_REGISTERS) --- the read_error, data_changed and write_error counting is done separately. always going through the whole memory would take a bit longer, actually this only takes 512 times 7 clock cycles, so 35us.-- we need 7 clock cycles per register because two 32bit integers have to be read from ram3a (4), changed (1) and written back to ram3a (2). the minimum would be some constant + 2 clock cycles/register, because 2 words have to be read from ram (and 2 words have to be written to ram). - -entity jtag_update_error_counts_ram3a is - generic ( - MAX_NUMCHIPS : integer; - MAX_NUMCHIPS_LD : integer; - MAX_NUMCHIPS_PLUS_ONE_LD : integer; - MAX_REGISTERS_LD : integer; - MAX_REGISTERS_PLUS_ONE_LD : integer; - MAX_REGISTERS_PLUS_TWO_LD : integer; - RAM_MATCH_DIFF_COUNT_DEPTH : integer; - RAM_ERROR_COUNTS_DEPTH : integer; - WRITE_ERROR_THRESHOLD : integer; - READ_ERROR_THRESHOLD : integer - ); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - TRIGGER_UPDATE_DATA_CHANGED_IN : in std_logic; - TRIGGER_UPDATE_READ_ERRORS_IN : in std_logic; - TRIGGER_UPDATE_WRITE_ERRORS_IN : in std_logic; - TRIGGER_UPDATE_RUN_COUNTER_IN : in std_logic; - RUN_COUNTER_IN : in std_logic_vector(31 downto 0); - -- RAM2 - RAM2_A_OUT : out std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0); - RAM2_D_IN : in std_logic_vector(31 downto 0); - -- RAM3a - RAM3A_A_OUT : out std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0); - RAM3A_D_IN : in std_logic_vector(31 downto 0); - RAM3A_D_OUT : out std_logic_vector(31 downto 0); - RAM3A_WR_OUT :out std_logic; - - - -- * need this because only for not-removed chips errors should be counted - REMOVED_CHIPS_IN : in std_logic_vector(MAX_NUMCHIPS -1 downto 0); - -- * only go up to the number of chips configured - NUMCHIPS_CONFIGURED_IN : in std_logic_vector(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0); - -- from (i+1)*MAX_REGISTERS_PLUS_ONE_LD-1 downto (i)*MAX_REGISTERS_PLUS_ONE_LD: numregs configured of chip i=(0, 1, 2, ...) - NUMREGS_CONFIGURED_IN : in std_logic_vector(MAX_NUMCHIPS*(MAX_REGISTERS_PLUS_ONE_LD)-1 downto 0); - - -- if true, there were read errors in last dev_id read - READ_ERRORS_OUT : out std_logic; - -- if true, there were read errors the last double write to registers (value read the second time didn't equal programmed value) - WRITE_ERRORS_OUT : out std_logic; - -- if true, the data read from the registers wasn't equal to the data programmed a period before (for example in the last spill break) - DATA_CHANGED_OUT : out std_logic; - IDLE_OUT : out std_logic - ); -end entity; - -architecture jtag_update_error_counts_ram3a_arch of jtag_update_error_counts_ram3a is -type upd_state_type is (UPD_IDLE, --- upd1s*: update DATA_CHANGED counts -UPD1S_START_REG, UPD1S_SETUP_READ_DATA_CH, UPD1S_SETUP_READ_DATA_CH_OV_TH, UPD1S_READ_DATA_CH_OV_TH, -UPD1S_WRITE_CALC_NEW_DATA_CHANGED, UPD1S_WRITE_DR_DATA_CHANGED, UPD1S_WRITE_DR_DATA_CHANGED_OV_TH, -UPD1S_START_FINISH, UPD1S_FINISH_SETUP_READ_DATA_CH, UPD1S_FINISH_SETUP_READ_WAIT, UPD1S_FINISH_READ_DATA_CH_OV_TH, -UPD1S_FINISH_CALC_NEW_DATA_CHANGED, UPD1S_FINISH_WRITE_DATA_CHANGED, UPD1S_FINISH_WRITE_DATA_CHANGED_OV_TH, - -UPD3S_START_REG, UPD3S_SETUP_READ_DATA_CH, UPD3S_SETUP_READ_DATA_CH_OV_TH, UPD3S_READ_DATA_CH_OV_TH, -UPD3S_WRITE_CALC_NEW_DATA_CHANGED, UPD3S_WRITE_DR_DATA_CHANGED, UPD3S_WRITE_DR_DATA_CHANGED_OV_TH, -UPD3S_START_FINISH, UPD3S_FINISH_SETUP_READ_DATA_CH, UPD3S_FINISH_SETUP_READ_WAIT, UPD3S_FINISH_READ_DATA_CH_OV_TH, -UPD3S_FINISH_CALC_NEW_DATA_CHANGED, UPD3S_FINISH_WRITE_DATA_CHANGED, UPD3S_FINISH_WRITE_DATA_CHANGED_OV_TH, - -UPD2S_START_REG, UPD2S_SETUP_READ_DATA_CH, UPD2S_SETUP_READ_DATA_CH_OV_TH, UPD2S_READ_DATA_CH_OV_TH, -UPD2S_WRITE_CALC_NEW_DATA_CHANGED, UPD2S_WRITE_DR_DATA_CHANGED, UPD2S_WRITE_DR_DATA_CHANGED_OV_TH, --- upd2s*: update READ_ERROR counts ---,UPD2S_SETUP,UPD2S_READ_MCOUNT, UPD2S_READ_DCOUNT, --- upd3s*: update WRITE_ERROR counts ---UPD3S_SETUP, UPD3S_READ_MCOUNT, UPD3S_READ_DCOUNT,UPD3S_WRITE_WRITE_ERRORS, UPD3S_WRITE_WRITE_ERRORS_OV_TH - --- following states unneeded because ram has one clock cycle delay for reading, not two ---, UPD1S_SETUP_READ_DATA_CH2, UPD3S_SETUP_READ_DATA_CH2, UPD2S_SETUP_READ_DATA_CH2 --- , UPD1S_FINISH_SETUP_READ_DATA_CH_OV_TH, UPD3S_FINISH_SETUP_READ_DATA_CH_OV_TH -UPD4S_WRITE_RUN_COUNTER -); -signal state, state_next : upd_state_type; - -signal chipnum, chipnum_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0); -signal regnum, regnum_next : unsigned(MAX_REGISTERS_LD -1 downto 0); -signal any_data_changed, any_data_changed_next : std_logic; -signal any_data_changed_ov_th, any_data_changed_ov_th_next : std_logic; -signal ram2_a, ram2_a_next : std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0); -signal ram3a_a, ram3a_a_next : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0); -signal ram3a_d, ram3a_d_next : std_logic_vector(31 downto 0); -signal ram3a_wr, ram3a_wr_next : std_logic; -signal changed_count, changed_count_next : unsigned(31 downto 0); -signal changed_ov_th_count, changed_ov_th_count_next : unsigned(31 downto 0); -signal mcount, mcount_next : std_logic_vector(31 downto 0); -signal dcount, dcount_next : std_logic_vector(31 downto 0); -signal removed_chips : std_logic_vector(2**MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0); --- global data_changed/read_errors/write_errors -signal gdata_changed, gdata_changed_next : std_logic; -signal gread_errors, gread_errors_next : std_logic; -signal gwrite_errors, gwrite_errors_next : std_logic; -signal numregs : unsigned(MAX_REGISTERS_PLUS_ONE_LD - 1 downto 0); -signal numregs_vect : std_logic_vector((2**MAX_NUMCHIPS_LD)*MAX_REGISTERS_PLUS_ONE_LD-1 downto 0); - - -begin - -IDLE_OUT <= '1' when state = UPD_IDLE else '0'; -RAM2_A_OUT <= ram2_a; -RAM3A_A_OUT <= ram3a_a; -RAM3A_D_OUT <= ram3a_d; -RAM3A_WR_OUT <= ram3a_wr; --- only maximum of MAX_NUMCHIPS is allowed, so don't need external signals for these chips, --- but internally the integer can go up to 2**MAX_NUMCHIPS_PLUS_ONE_LD-1 -removed_chips(2**MAX_NUMCHIPS_PLUS_ONE_LD-1 downto MAX_NUMCHIPS) <= (others => '1'); -removed_chips(MAX_NUMCHIPS-1 downto 0) <= REMOVED_CHIPS_IN; -numregs_vect((2**MAX_NUMCHIPS_LD)*MAX_REGISTERS_PLUS_ONE_LD-1 downto MAX_NUMCHIPS*MAX_REGISTERS_PLUS_ONE_LD) <= (others => '0'); -- fill unavailable bits with zeros (to make slices computable) -numregs_vect(MAX_NUMCHIPS*MAX_REGISTERS_PLUS_ONE_LD-1 downto 0) <= NUMREGS_CONFIGURED_IN; -numregs <= unsigned(NUMREGS_CONFIGURED_IN((to_integer(chipnum)+1)*MAX_REGISTERS_PLUS_ONE_LD - 1 downto to_integer(chipnum)*MAX_REGISTERS_PLUS_ONE_LD)); - -READ_ERRORS_OUT <= gread_errors; -WRITE_ERRORS_OUT <= gwrite_errors; -DATA_CHANGED_OUT <= gdata_changed; - -SEQUENTIAL: process(CLK_IN) -begin - if (rising_edge(CLK_IN)) then - if(RESET_IN = '1') then - state <= UPD_IDLE; - ram2_a <= (others => '0'); - ram3a_a <= (others => '0'); - ram3a_wr <= '0'; - ram3a_d <= (others => '0'); - changed_count <= (others => '0'); - changed_ov_th_count <= (others => '0'); - mcount <= (others => '0'); - dcount <= (others => '0'); - chipnum <= (others => '0'); - any_data_changed <= '0'; - any_data_changed_ov_th <= '0'; - regnum <= (others => '0'); - gdata_changed <= '0'; - gread_errors <= '0'; - gwrite_errors <= '0'; - else - state <= state_next; - ram2_a <= ram2_a_next; - ram3a_a <= ram3a_a_next; - ram3a_wr <= ram3a_wr_next; - ram3a_d <= ram3a_d_next; - changed_count <= changed_count_next; - changed_ov_th_count <= changed_ov_th_count_next; - mcount <= mcount_next; - dcount <= dcount_next; - chipnum <= chipnum_next; - any_data_changed <= any_data_changed_next; - any_data_changed_ov_th <= any_data_changed_ov_th_next; - regnum <= regnum_next; - gdata_changed <= gdata_changed_next; - gread_errors <= gread_errors_next; - gwrite_errors <= gwrite_errors_next; - end if; - end if; -end process; - -COMB: process(state, TRIGGER_UPDATE_DATA_CHANGED_IN, TRIGGER_UPDATE_READ_ERRORS_IN, TRIGGER_UPDATE_WRITE_ERRORS_IN, TRIGGER_UPDATE_RUN_COUNTER_IN, RUN_COUNTER_IN, numregs, removed_chips, NUMCHIPS_CONFIGURED_IN, ram3a_d, RAM3A_D_IN, ram3a_a, ram2_a, RAM2_D_IN, chipnum, regnum, any_data_changed, any_data_changed_ov_th, changed_count, changed_ov_th_count, dcount, mcount, gdata_changed, gwrite_errors, gread_errors) -begin - state_next <= state; - ram2_a_next <= ram2_a; - ram3a_a_next <= ram3a_a; - ram3a_d_next <= ram3a_d; - ram3a_wr_next <= '0'; - chipnum_next <= chipnum; - regnum_next <= regnum; - any_data_changed_next <= any_data_changed; - any_data_changed_ov_th_next <= any_data_changed_ov_th; - changed_count_next <= changed_count; - changed_ov_th_count_next <= changed_ov_th_count; - dcount_next <= dcount; - mcount_next <= mcount; - - gdata_changed_next <= gdata_changed; - gwrite_errors_next <= gwrite_errors; - gread_errors_next <= gread_errors; - - case state is - when UPD_IDLE => - if(TRIGGER_UPDATE_DATA_CHANGED_IN = '1') then - chipnum_next <= (others => '0'); - regnum_next <= (others => '0'); - any_data_changed_next <= '0'; - any_data_changed_ov_th_next <= '0'; - gdata_changed_next <= '0'; - state_next <= UPD1S_START_REG; - elsif(TRIGGER_UPDATE_READ_ERRORS_IN = '1') then - chipnum_next <= (others => '0'); - regnum_next <= (others => '0'); - gread_errors_next <= '0'; - state_next <= UPD2S_START_REG; - elsif(TRIGGER_UPDATE_WRITE_ERRORS_IN = '1') then - chipnum_next <= (others => '0'); - regnum_next <= (others => '0'); - any_data_changed_next <= '0'; - any_data_changed_ov_th_next <= '0'; - gwrite_errors_next <= '0'; - state_next <= UPD3S_START_REG; - elsif(TRIGGER_UPDATE_RUN_COUNTER_IN = '1') then - chipnum_next <= (others => '0'); - state_next <= UPD4S_WRITE_RUN_COUNTER; - end if; - when UPD1S_START_REG => - ram2_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD ) <= std_logic_vector(chipnum); - ram2_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD-1 downto 1 ) <= std_logic_vector(to_unsigned(to_integer(regnum) + 1, MAX_REGISTERS_PLUS_TWO_LD)); -- dr counts start after two read counts, and for each register there are two words. - ram2_a_next(0 ) <= '0'; - ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-1 downto RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD ) <= std_logic_vector(chipnum); - ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD -1) <= '1'; -- data changed - ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD-2 downto 1) <= std_logic_vector(to_unsigned(to_integer(regnum)+2, MAX_REGISTERS_PLUS_TWO_LD)); -- dr1 - ram3a_a_next(0) <= '0'; --d_ch - state_next <= UPD1S_SETUP_READ_DATA_CH; - when UPD1S_SETUP_READ_DATA_CH => - -- only need to increment the lower address part which corresponds to the register number, chipnumber doesn't change - ram2_a_next(0) <= '1'; - ram3a_a_next(0) <= '1'; - -- state_next <= UPD1S_SETUP_READ_DATA_CH2; - --when UPD1S_SETUP_READ_DATA_CH2 => - state_next <= UPD1S_SETUP_READ_DATA_CH_OV_TH; - when UPD1S_SETUP_READ_DATA_CH_OV_TH => - changed_count_next <= unsigned(RAM3A_D_IN); - mcount_next <= RAM2_D_IN; - state_next <= UPD1S_READ_DATA_CH_OV_TH; - - when UPD1S_READ_DATA_CH_OV_TH => - changed_ov_th_count_next <= unsigned(RAM3A_D_IN); - dcount_next <= RAM2_D_IN; - state_next <= UPD1S_WRITE_CALC_NEW_DATA_CHANGED; - - when UPD1S_WRITE_CALC_NEW_DATA_CHANGED => - -- if 0 bits match, or at least one error, add one to data changed count - if((std_logic_vector_all_components_equal_scalar(mcount, '0')='1') or ( std_logic_vector_all_components_equal_scalar(dcount, '0') = '0')) then - -- increment error counter - changed_count_next <= changed_count + 1; -- 32 bit so overflow will occur with enough time to detect - if(removed_chips(to_integer(chipnum)) = '0') then - any_data_changed_next <= '1'; - gdata_changed_next <= '1'; - end if; - end if; - - if(unsigned(mcount) = 0 or not unsigned(dcount)< WRITE_ERROR_THRESHOLD) then - -- increment error counter - changed_ov_th_count_next <= changed_ov_th_count + 1; -- 32 bit so overflow will occur with enough time to detect - if(removed_chips(to_integer(chipnum)) = '0') then - any_data_changed_ov_th_next <= '1'; - gdata_changed_next <= '1'; - end if; - end if; - state_next <= UPD1S_WRITE_DR_DATA_CHANGED; - - when UPD1S_WRITE_DR_DATA_CHANGED => - ram3a_a_next(0) <= '0'; - ram3a_d_next <= std_logic_vector(changed_count); - ram3a_wr_next <= '1'; - state_next <= UPD1S_WRITE_DR_DATA_CHANGED_OV_TH; - when UPD1S_WRITE_DR_DATA_CHANGED_OV_TH => - ram3a_a_next(0) <= '1'; - ram3a_d_next <= std_logic_vector(changed_ov_th_count); - ram3a_wr_next <= '1'; - if((to_integer(regnum) + 1 = numregs) or (numregs = 0) ) then - -- finished - state_next <= UPD1S_START_FINISH; - else - regnum_next <= regnum + 1; - state_next <= UPD1S_START_REG; - end if; - - when UPD1S_START_FINISH => - ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD-2 downto 0) <= std_logic_vector(to_unsigned(2,MAX_REGISTERS_PLUS_TWO_LD+1)); -- DATA_CHANGED (total) - state_next <= UPD1S_FINISH_SETUP_READ_DATA_CH; - when UPD1S_FINISH_SETUP_READ_DATA_CH => - ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD-2 downto 0) <= std_logic_vector(to_unsigned(3,MAX_REGISTERS_PLUS_TWO_LD+1)); -- DATA_CHANGED_OVER_TH (total) - -- state_next <= UPD1S_FINISH_SETUP_READ_DATA_CH_OV_TH; - --when UPD1S_FINISH_SETUP_READ_DATA_CH_OV_TH => - state_next <= UPD1S_FINISH_SETUP_READ_WAIT; - when UPD1S_FINISH_SETUP_READ_WAIT => - changed_count_next <= unsigned(RAM3A_D_IN); - state_next <= UPD1S_FINISH_READ_DATA_CH_OV_TH; - when UPD1S_FINISH_READ_DATA_CH_OV_TH => - changed_ov_th_count_next <= unsigned(RAM3A_D_IN); - state_next <= UPD1S_FINISH_CALC_NEW_DATA_CHANGED; - when UPD1S_FINISH_CALC_NEW_DATA_CHANGED => - if(any_data_changed = '1') then - changed_count_next <= changed_count + 1; -- 32 bit so overflow will occur with enough time to detect - end if; - if(any_data_changed_ov_th = '1') then - changed_ov_th_count_next <= changed_ov_th_count + 1; -- 32 bit so overflow will occur with enough time to detect - end if; - state_next <= UPD1S_FINISH_WRITE_DATA_CHANGED; - - when UPD1S_FINISH_WRITE_DATA_CHANGED => - ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD-2 downto 0) <= std_logic_vector(to_unsigned(2,MAX_REGISTERS_PLUS_TWO_LD+1)); -- DATA_CHANGED (total) - ram3a_d_next <= std_logic_vector(changed_count); - ram3a_wr_next <= '1'; - state_next <= UPD1S_FINISH_WRITE_DATA_CHANGED_OV_TH; - when UPD1S_FINISH_WRITE_DATA_CHANGED_OV_TH => - ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD-2 downto 0) <= std_logic_vector(to_unsigned(3,MAX_REGISTERS_PLUS_TWO_LD+1)); -- DATA_CHANGED_OVER_TH (total) - ram3a_d_next <= std_logic_vector(changed_ov_th_count); - ram3a_wr_next <= '1'; - if(to_integer(chipnum) + 1 /= unsigned(NUMCHIPS_CONFIGURED_IN)) then - -- process next chip - chipnum_next <= chipnum + 1; - regnum_next <= (others => '0'); - any_data_changed_next <= '0'; - any_data_changed_ov_th_next <= '0'; - state_next <= UPD1S_START_REG; - else - -- finally really finished - state_next <= UPD_IDLE; - end if; - - -- UPDATE WRITE ERROR COUNTS - when UPD3S_START_REG => - ram2_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD ) <= std_logic_vector(chipnum); - ram2_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD-1 downto 1 ) <= std_logic_vector(to_unsigned(to_integer(regnum) + 1, MAX_REGISTERS_PLUS_TWO_LD)); -- dr counts start after two read counts, and for each register there are two words. - ram2_a_next(0 ) <= '0'; - ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-1 downto RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD ) <= std_logic_vector(chipnum); - ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD -1) <= '0'; -- write errors - ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD-2 downto 1) <= std_logic_vector(to_unsigned(to_integer(regnum)+2, MAX_REGISTERS_PLUS_TWO_LD)); -- dr1 - ram3a_a_next(0) <= '0'; -- normal count - state_next <= UPD3S_SETUP_READ_DATA_CH; - when UPD3S_SETUP_READ_DATA_CH => - -- only need to increment the lower address part which corresponds to the register number, chipnumber doesn't change - ram2_a_next(0) <= '1'; - ram3a_a_next(0) <= '1'; -- count over th - -- state_next <= UPD3S_SETUP_READ_DATA_CH2; - --when UPD3S_SETUP_READ_DATA_CH2 => - state_next <= UPD3S_SETUP_READ_DATA_CH_OV_TH; - when UPD3S_SETUP_READ_DATA_CH_OV_TH => - changed_count_next <= unsigned(RAM3A_D_IN); -- changed_count now is write error count - mcount_next <= RAM2_D_IN; - state_next <= UPD3S_READ_DATA_CH_OV_TH; - - when UPD3S_READ_DATA_CH_OV_TH => - changed_ov_th_count_next <= unsigned(RAM3A_D_IN); -- changed_ov_th_count now is write errors over threshold count - dcount_next <= RAM2_D_IN; - state_next <= UPD3S_WRITE_CALC_NEW_DATA_CHANGED; - - when UPD3S_WRITE_CALC_NEW_DATA_CHANGED => - -- if 0 bits match, or at least one error, add one to data changed count - if((std_logic_vector_all_components_equal_scalar(mcount, '0')='1') or ( std_logic_vector_all_components_equal_scalar(dcount, '0') = '0')) then - -- increment error counter - changed_count_next <= changed_count + 1; -- 32 bit so overflow will occur with enough time to detect - -- onlly add chip errors of not removed chips to global error counter - if(removed_chips(to_integer(chipnum)) = '0') then - any_data_changed_next <= '1'; - gwrite_errors_next <= '1'; - end if; - end if; - - if(unsigned(mcount) = 0 or not unsigned(dcount)< WRITE_ERROR_THRESHOLD) then - -- increment error counter - changed_ov_th_count_next <= changed_ov_th_count + 1; -- 32 bit so overflow will occur with enough time to detect - -- onlly add chip errors of not removed chips to global error counter - if(removed_chips(to_integer(chipnum)) = '0') then - any_data_changed_ov_th_next <= '1'; - gwrite_errors_next <= '1'; - - end if; - end if; - state_next <= UPD3S_WRITE_DR_DATA_CHANGED; - - when UPD3S_WRITE_DR_DATA_CHANGED => - ram3a_a_next(0) <= '0'; - ram3a_d_next <= std_logic_vector(changed_count); - ram3a_wr_next <= '1'; - state_next <= UPD3S_WRITE_DR_DATA_CHANGED_OV_TH; - when UPD3S_WRITE_DR_DATA_CHANGED_OV_TH => - ram3a_a_next(0) <= '1'; - ram3a_d_next <= std_logic_vector(changed_ov_th_count); - ram3a_wr_next <= '1'; - if((to_integer(regnum) + 1 = numregs) or (numregs = 0) ) then - -- finished - state_next <= UPD3S_START_FINISH; - else - regnum_next <= regnum + 1; - state_next <= UPD3S_START_REG; - end if; - - when UPD3S_START_FINISH => - ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD-2 downto 0) <= std_logic_vector(to_unsigned(2,MAX_REGISTERS_PLUS_TWO_LD+1)); -- DATA_CHANGED (total) - state_next <= UPD3S_FINISH_SETUP_READ_DATA_CH; - when UPD3S_FINISH_SETUP_READ_DATA_CH => - ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD-2 downto 0) <= std_logic_vector(to_unsigned(3,MAX_REGISTERS_PLUS_TWO_LD+1)); -- DATA_CHANGED_OVER_TH (total) --- state_next <= UPD3S_FINISH_SETUP_READ_DATA_CH_OV_TH; --- when UPD3S_FINISH_SETUP_READ_DATA_CH_OV_TH => - state_next <= UPD3S_FINISH_SETUP_READ_WAIT; - when UPD3S_FINISH_SETUP_READ_WAIT => - changed_count_next <= unsigned(RAM3A_D_IN); - state_next <= UPD3S_FINISH_READ_DATA_CH_OV_TH; - when UPD3S_FINISH_READ_DATA_CH_OV_TH => - changed_ov_th_count_next <= unsigned(RAM3A_D_IN); - state_next <= UPD3S_FINISH_CALC_NEW_DATA_CHANGED; - when UPD3S_FINISH_CALC_NEW_DATA_CHANGED => - if(any_data_changed = '1') then - changed_count_next <= changed_count + 1; -- 32 bit so overflow will occur with enough time to detect - end if; - if(any_data_changed_ov_th = '1') then - changed_ov_th_count_next <= changed_ov_th_count + 1; -- 32 bit so overflow will occur with enough time to detect - end if; - state_next <= UPD3S_FINISH_WRITE_DATA_CHANGED; - - when UPD3S_FINISH_WRITE_DATA_CHANGED => - ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD-2 downto 0) <= std_logic_vector(to_unsigned(2,MAX_REGISTERS_PLUS_TWO_LD+1)); -- DATA_CHANGED (total) - ram3a_d_next <= std_logic_vector(changed_count); - ram3a_wr_next <= '1'; - state_next <= UPD3S_FINISH_WRITE_DATA_CHANGED_OV_TH; - when UPD3S_FINISH_WRITE_DATA_CHANGED_OV_TH => - ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD-2 downto 0) <= std_logic_vector(to_unsigned(3,MAX_REGISTERS_PLUS_TWO_LD+1)); -- DATA_CHANGED_OVER_TH (total) - ram3a_d_next <= std_logic_vector(changed_ov_th_count); - ram3a_wr_next <= '1'; - if(to_integer(chipnum)+1 /= unsigned(NUMCHIPS_CONFIGURED_IN)) then - -- process next chip - chipnum_next <= chipnum + 1; - regnum_next <= (others => '0'); - any_data_changed_next <= '0'; - any_data_changed_ov_th_next <= '0'; - state_next <= UPD3S_START_REG; - else - -- finally really finished - state_next <= UPD_IDLE; - end if; - - - -- UPDATE READ ERROR COUNTS - when UPD2S_START_REG => - ram2_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD ) <= std_logic_vector(chipnum); - ram2_a_next(RAM_MATCH_DIFF_COUNT_DEPTH-MAX_NUMCHIPS_LD-1 downto 1 ) <= (others => '0'); -- the two read counts are the first two words. - ram2_a_next(0 ) <= '0'; - ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-1 downto RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD ) <= std_logic_vector(chipnum); - ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD -1) <= '0'; -- read errors - ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD-2 downto 1) <= (others => '0'); -- read errors - ram3a_a_next(0) <= '0'; -- normal count - state_next <= UPD2S_SETUP_READ_DATA_CH; - when UPD2S_SETUP_READ_DATA_CH => - -- only need to increment the lower address part which corresponds to the register number, chipnumber doesn't change - ram2_a_next(0) <= '1'; - ram3a_a_next(0) <= '1'; -- count over th - -- state_next <= UPD2S_SETUP_READ_DATA_CH2; - --when UPD2S_SETUP_READ_DATA_CH2 => - state_next <= UPD2S_SETUP_READ_DATA_CH_OV_TH; - when UPD2S_SETUP_READ_DATA_CH_OV_TH => - changed_count_next <= unsigned(RAM3A_D_IN); -- changed_count now is write error count - mcount_next <= RAM2_D_IN; - state_next <= UPD2S_READ_DATA_CH_OV_TH; - - when UPD2S_READ_DATA_CH_OV_TH => - changed_ov_th_count_next <= unsigned(RAM3A_D_IN); -- changed_ov_th_count now is write errors over threshold count - dcount_next <= RAM2_D_IN; - state_next <= UPD2S_WRITE_CALC_NEW_DATA_CHANGED; - - when UPD2S_WRITE_CALC_NEW_DATA_CHANGED => - -- if 0 bits match, or at least one error, add one to data changed count - if((std_logic_vector_all_components_equal_scalar(mcount, '0')='1') or ( std_logic_vector_all_components_equal_scalar(dcount, '0') = '0')) then - -- onlly add chip errors of not removed chips to global error counter - if(removed_chips(to_integer(chipnum)) = '0') then - -- increment error counter - changed_count_next <= changed_count + 1; -- 32 bit so overflow will occur with enough time to detect - gread_errors_next <= '1'; - end if; - --any_data_changed_next <= '1'; - end if; - - if(unsigned(mcount) = 0 or not unsigned(dcount)< READ_ERROR_THRESHOLD) then - -- onlly add chip errors of not removed chips to global error counter - if(removed_chips(to_integer(chipnum)) = '0') then - -- increment error counter - changed_ov_th_count_next <= changed_ov_th_count + 1; -- 32 bit so overflow will occur with enough time to detect - gread_errors_next <= '1'; - end if; - --any_data_changed_ov_th_next <= '1'; - end if; - state_next <= UPD2S_WRITE_DR_DATA_CHANGED; - - when UPD2S_WRITE_DR_DATA_CHANGED => - ram3a_a_next(0) <= '0'; - ram3a_d_next <= std_logic_vector(changed_count); - ram3a_wr_next <= '1'; - state_next <= UPD2S_WRITE_DR_DATA_CHANGED_OV_TH; - when UPD2S_WRITE_DR_DATA_CHANGED_OV_TH => - ram3a_a_next(0) <= '1'; - ram3a_d_next <= std_logic_vector(changed_ov_th_count); - ram3a_wr_next <= '1'; - if(to_integer(chipnum)+1 /= unsigned(NUMCHIPS_CONFIGURED_IN)) then - -- process next chip - chipnum_next <= chipnum + 1; - --any_data_changed_next <= '0'; - --any_data_changed_ov_th_next <= '0'; - state_next <= UPD2S_START_REG; - else - -- finished - state_next <= UPD_IDLE; - end if; - - -- UPDATE RUN COUNTER part - when UPD4S_WRITE_RUN_COUNTER => - ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-1 downto RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD ) <= std_logic_vector(chipnum); - ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD -1) <= '1'; -- data_changed/run_counter - ram3a_a_next(RAM_ERROR_COUNTS_DEPTH-MAX_NUMCHIPS_LD -2 downto 0) <= (others => '0'); -- data_changed/run_counter - ram3a_d_next <= RUN_COUNTER_IN; - ram3a_wr_next <= '1'; - if(to_integer(chipnum)+1 /= unsigned(NUMCHIPS_CONFIGURED_IN)) then - chipnum_next <= chipnum + 1; - else - state_next <= UPD_IDLE; - end if; -end case; -end process; - -end architecture; diff --git a/vhdl/code/jtag_write_m10.vhd b/vhdl/code/jtag_write_m10.vhd deleted file mode 100644 index d94cb2b..0000000 --- a/vhdl/code/jtag_write_m10.vhd +++ /dev/null @@ -1,586 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; ---USE IEEE.std_logic_ARITH.ALL; ---USE IEEE.std_logic_UNSIGNED.ALL; -USE IEEE.numeric_std.ALL; - -library work; ---use work.trb_net_std.all; ---use work.trb_net_components.all; --- use work.trb_net16_hub_func.all; ---use work.version.all; -use work.jtag_constants.all; - -entity jtag_write_m10 is - generic ( - RAM_JTAG_REGISTERS_DEPTH : integer; - MAX_NUMCHIPS : integer; - MAX_NUMCHIPS_LD : integer; - MAX_NUMCHIPS_PLUS_ONE_LD : integer; - MAX_REGISTERS_LD : integer; - MAX_REGISTERS_PLUS_ONE_LD : integer; - MAX_REGLEN_LD : integer; - MAX_REGLEN_PLUS_ONE_LD : integer - ); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - RAM_JTAG_REGISTERS_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); - RAM_JTAG_REGISTERS_D_IN : in std_logic_vector(31 downto 0); - - --RAM_JTAG_REGISTERS_READ_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_READ_DEPTH-1 downto 0); - --RAM_JTAG_REGISTERS_READ_D_OUT : out std_logic_vector(31 downto 0); - -- number of next chip which is not removed from the jtag chain. for chip i ( in range 0...N) this next chip is - -- encoded by the bits NEXT_NOT_REMOVED((i+1)*MAX_NUMCHIPS_LD + MAX_NUMCHIPS_LD-1 downto (i+1)*MAX_NUMCHIPS_LD) - -- which should be interpreted as unsigned - -- the zero'th entry points to the first not removed chip - -- a value of (others => '1') means that no more non-removed chips follow - NEXT_NOT_REMOVED_IN : in std_logic_vector(MAX_NUMCHIPS_PLUS_ONE_LD*(MAX_NUMCHIPS+1)-1 downto 0); - - BEGIN_JTAGBITCALC_IN : in std_logic; - TRIGGER_BEGIN_WRITE_IN : in std_logic; - IDLE_OUT : out std_logic; - - - IS_DR_BIT_OUT : out std_logic; - IS_FIRSTBIT_OUT : out std_logic; - IS_LASTBIT_OUT : out std_logic; - CHIPNUM_OUT : out std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0); - REGNUM_OUT : out std_logic_vector(MAX_REGISTERS_LD-1 downto 0); - ENABLE_JTAG_CLOCK_OUT : out std_logic; - - LAST_TCK_CYCLE_OUT : out std_logic; - TMS_OUT : out std_logic; - TDI_OUT : out std_logic; - EXPECTED_TDO_OUT : out std_logic; - --- from (i+1)*MAX_REGISTERS_PLUS_ONE_LD-1 downto (i)*MAX_REGISTERS_PLUS_ONE_LD: numregs configured of chip i=(0, 1, 2, ...) - NUMREGS_CONFIGURED_OUT : out std_logic_vector(MAX_NUMCHIPS*(MAX_REGISTERS_PLUS_ONE_LD)-1 downto 0); - - LAST_ERROR_CODE_OUT : out std_logic_vector(2 downto 0) - - - ); -end entity; - -architecture jtag_write_m10_arch of jtag_write_m10 is - --- this state controls the global behaviour. on reset state idle is entered, --- on trigger wait_begin_jtagbitcalc is entered --- when begin_jtagbitcalc is set, state becomes either idle or --- processing and after finished wait_begin_jtagbitcalc is entered again -type state_type is (idle, wait_begin_jtagbitcalc, processing); -signal state, state_next : state_type; --- the substate represents the processing state we are in, the name suffix _pi tells how many clock cycles have been spent up to the current state, processing. i must be smaller than 10 so that with 100MHz system clock the JTAG clock can be operated at 10 MHz. -type substate_type is (newchip_p1, newchip_IR_wait_p2, newchip_IR_wait_p3, newchip_IR_p4, newchip_DR_p2, newchip_DR_p3, newchip_DR_wait_p4, newchip_DR_p5, samechip_newword_DR_p1, newword_wait_p6, newword_p7, setOutputs_p8); -signal substate, substate_next : substate_type; - --- operation = "00": JTAG_RESET, operation = "01" : WRITE_IR, operation = "10": WRITE_DR, operation = "11": none --- the operation is set on entering processing state, in setup operation is set to none -signal operation, operation_next : unsigned(1 downto 0); --- --- JTAG_RESET: operation_phase = 0000-0101 : set TMS=1 for JTAG reset --- WRITE_IR: operation_phase = 0000 : set TMS=0 => Run-Test/Idle --- operation_phase = 0001 : set TMS=1 => Select-DR-Scan --- operation_phase = 0010 : set TMS=1 => Select-IR-Scan --- operation_phase = 0011 : set TMS=0 => Capture-IR --- operation_phase = 0100 : set TMS=0 => Shift-IR --- operation_phase = 0101 : set TMS=0 => Shift-IR, HERE SHIFTING OF DATA HAPPENS --- operation_phase = 0110 : set TMS=1 => Exit1-IR, HERE LAST BIT OF IR IS SHIFTED --- operation_phase = 0111 : set TMS=1 => Update-IR --- operation_phase = 1000 : set TMS=0 => Run-Test/Idle --- WRITE_DR: operation_phase = 0000 : set TMS=1 => Select-DR-Scan --- operation_phase = 0001 : set TMS=0 => Capture-DR --- operation_phase = 0010 : set TMS=0 => Shift-DR --- operation_phase = 0011 : set TMS=0 => Shift-DR, HERE SHIFTING OF DATA HAPPENS --- operation_phase = 0100 : set TMS=1 => Exit1-DR, HERE LAST BIT OF IR IS SHIFTED --- operation_phase = 0101 : set TMS=1 => Update-DR --- operation_phase = 0110 : set TMS=0 => Run-Test/Idle --- warning: operation phase may change during processing (because length of register is retrieved from RAM) --- but will settle from setOutputs_p8 on -signal operation_phase, operation_phase_next : unsigned(3 downto 0); - --- In processing state: the register that is currently being written. if regcounter >= numregs of the current chip, --- the bypass register is selected (IR=FFFF...F, opcode all ones, see http://en.wikipedia.org/wiki/Joint_Test_Action_Group). - -- set to 0 in setup, valid when entering processing, incremented on first JTAG clock cycle belonging to next register - -- this means it is incremented on entering processing with JTAG_RESET operation -signal regcounter, regcounter_next : unsigned(MAX_REGISTERS_LD -1 downto 0); - --- number of registers for current chip, --- warning: set while processing -signal numregs, numregs_next : unsigned(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0); - --- after the first run through WRITE_IR, maxnumregs equals the maximum value of numregs entry in RAM_JTAG_REGISTERS structure -signal maxnumregs, maxnumregs_next : unsigned(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0); - --- chipcounter: in processing state: chip-nr. to which the requested bit belongs --- set to value for next processing run when leaving state wait_begin_jtagbitcalc -signal chipcounter, chipcounter_next : unsigned(MAX_NUMCHIPS_LD -1 downto 0); - --- bitcounter: in processing state: bit-nr. inside current chip --- set to value for next processing run when leaving state wait_begin_jtagbitcalc, --- reset to 0 when chipcounter is changed -signal bitcounter, bitcounter_next : unsigned(MAX_REGLEN_LD-1 downto 0); - - --- length: this is the length of the DR/IR respectively of the currently active chip, --- warning: this becomes valid only after some processing steps of the first bit for each chip, --- but will be valid 10 clock cycles after begin_jtagbitcalc --- length = 0 is not allowed -signal length, length_next : unsigned(MAX_REGLEN_PLUS_ONE_LD-1 downto 0); - --- data_word: value of 32 bit DR/IR word -signal data_word, data_word_next : std_logic_vector(31 downto 0); - --- dr_pointer: Pointer to DR inside memory area of chip, --- so only the lower bits of the address are stored, the rest is stored as chipcounter -signal dr_pointer, dr_pointer_next : unsigned(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0); - --- JTAG output signal: TDI -signal tdi, tdi_next : std_logic; - --- JTAG output signal: TMS -signal tms, tms_next : std_logic; - --- indicates this is the last TCK clock cycle for this write operation -signal last_tck_cycle, last_tck_cycle_next : std_logic; - --- RAM address -signal ram_jtag_registers_a, ram_jtag_registers_a_next : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); - --- debugging register --- "001": length 0 register found, this is not allowed -signal last_error_code, last_error_code_next : std_logic_vector(2 downto 0); - --- next_not_removed_chip: --- the correct slice from NEXT_NOT_REMOVED_IN, depending on the current value of chipcounter -signal nxt_not_removed_chip : unsigned(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0); - -signal first_not_removed_chip : unsigned(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0); - -constant invalid_chip : unsigned(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0) := (others => '1'); - --- should a JTAG clock pulse be generated this global_jtag_counter cycle? -signal enable_jtag_clock, enable_jtag_clock_next : std_logic; - -signal numregs_configured, numregs_configured_next : std_logic_vector(MAX_NUMCHIPS*(MAX_REGISTERS_PLUS_ONE_LD)-1 downto 0); - --- INSERTLABEL: signals -begin - -NUMREGS_CONFIGURED_OUT <= numregs_configured; - -process(CLK_IN) -begin - if(rising_edge(CLK_IN)) then - if(RESET_IN='1') then - state <= idle; - substate <= newchip_p1; - operation <= "11"; - operation_phase <= "0000"; - regcounter <= (others => '0'); - numregs <= (others => '0'); - maxnumregs <= (others => '0'); - chipcounter <= (others => '0'); - bitcounter <= (others => '0'); - length <= (others => '0'); - data_word <= (others => '0'); - dr_pointer <= (others => '0'); - last_error_code <= (others => '0'); - tdi <= '0'; - tms <= '0'; - last_tck_cycle <= '0'; - ram_jtag_registers_a <= (others => '0'); - enable_jtag_clock <= '0'; - numregs_configured <= (others => '0'); - -- INSERTLABEL: SYNCHRONOUS reset - else - state <= state_next; - substate <= substate_next; - operation <= operation_next; - operation_phase <= operation_phase_next; - regcounter <= regcounter_next; - numregs <= numregs_next; - maxnumregs <= maxnumregs_next; - chipcounter <= chipcounter_next; - bitcounter <= bitcounter_next; - length <= length_next; - data_word <= data_word_next; - dr_pointer <= dr_pointer_next; - last_error_code <= last_error_code_next; - tdi <= tdi_next; - tms <= tms_next; - last_tck_cycle <= last_tck_cycle_next; - ram_jtag_registers_a <= ram_jtag_registers_a_next; - enable_jtag_clock <= enable_jtag_clock_next; - numregs_configured <= numregs_configured_next; - - -- INSERTLABEL: SYNCHRONOUS update - end if; - end if; -end process; - -RAM_JTAG_REGISTERS_A_OUT <= ram_jtag_registers_a; -LAST_TCK_CYCLE_OUT <= last_tck_cycle; -ENABLE_JTAG_CLOCK_OUT <= enable_jtag_clock; -TDI_OUT <= tdi; -TMS_OUT <= tms; -IS_DR_BIT_OUT <= '1' when operation = "10" and (operation_phase = "0011" or operation_phase = "0100") else '0'; -IS_FIRSTBIT_OUT <= '1' when to_integer(bitcounter) = 0 else '0'; -IS_LASTBIT_OUT <= '1' when to_integer(bitcounter)+1 = to_integer(length) else '0'; -CHIPNUM_OUT <= std_logic_vector(chipcounter); -REGNUM_OUT <= std_logic_vector(regcounter); -EXPECTED_TDO_OUT <= tdi; -IDLE_OUT <= '1' when state = idle else '0'; --- for this assignment to be valid, 0 <= chipcounter< MAX_NUMCHIPS has to be true -nxt_not_removed_chip <= unsigned(NEXT_NOT_REMOVED_IN((to_integer(chipcounter)+1)*MAX_NUMCHIPS_PLUS_ONE_LD+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto (to_integer(chipcounter)+1)*MAX_NUMCHIPS_PLUS_ONE_LD)); -- first entry points to first not removed chip -first_not_removed_chip <= unsigned(NEXT_NOT_REMOVED_IN(MAX_NUMCHIPS_PLUS_ONE_LD - 1 downto 0)); - -LAST_ERROR_CODE_OUT <= last_error_code; - -process(regcounter, maxnumregs, chipcounter, bitcounter, TRIGGER_BEGIN_WRITE_IN, BEGIN_JTAGBITCALC_IN, state, substate, operation, operation_phase, length, data_word, numregs, tdi, tms, dr_pointer, last_error_code, ram_jtag_registers_a, RAM_JTAG_REGISTERS_D_IN,enable_jtag_clock, first_not_removed_chip, nxt_not_removed_chip, last_tck_cycle, numregs_configured) -- INSERTLABEL: sensitivity list -begin - bitcounter_next <= bitcounter; - chipcounter_next <= chipcounter; - regcounter_next <= regcounter; - maxnumregs_next <= maxnumregs; - operation_next <= operation; - operation_phase_next <= operation_phase; - state_next <= state; - substate_next <= substate; - length_next <= length; - data_word_next <= data_word; - numregs_next <= numregs; - tdi_next <= tdi; - tms_next <= tms; - dr_pointer_next <= dr_pointer; - last_error_code_next <= last_error_code; - ram_jtag_registers_a_next <= ram_jtag_registers_a; - last_tck_cycle_next <= last_tck_cycle; - enable_jtag_clock_next <= enable_jtag_clock; - numregs_configured_next <= numregs_configured; - -- INSERTLABEL: COMB defaults - case state is - when idle => - last_tck_cycle_next <= '0'; - if(TRIGGER_BEGIN_WRITE_IN = '1') then - state_next <= wait_begin_jtagbitcalc; - operation_next <= "11"; -- none - end if; - when wait_begin_jtagbitcalc => - if(BEGIN_JTAGBITCALC_IN='1') then - state_next <= processing; - operation_phase_next <= operation_phase + 1; - -- last operation was: none => first JTAG clock cycle, reset - if(operation = "11") then - regcounter_next <= (others => '0'); - maxnumregs_next <= (others => '0'); - operation_next <= "00"; -- JTAG_RESET - operation_phase_next <= "0000"; -- Bit Nr. 0 - enable_jtag_clock_next <= '1'; -- enable JTAG clock for WRITE operation - substate_next <= setOutputs_p8; -- only output for JTAG_RESET - - - -- last operation was: JTAG_RESET - elsif(operation = "00") then - if(operation_phase = "0101") then - if(first_not_removed_chip /= invalid_chip) then - chipcounter_next <= first_not_removed_chip; - operation_next <= "01"; -- WRITE_IR - operation_phase_next <= "0000"; - bitcounter_next <= (others => '0'); - else - -- ERROR: no not removed chips - state_next <= idle; - end if; - end if; - - -- last operation was: WRITE_IR - elsif(operation = "01") then - substate_next <= setOutputs_p8; -- output has to be done in all cases, only sometimes need to do more - if(operation_phase = "0100") then -- Shift-IR entered in last operation - substate_next <= newchip_p1; - elsif(operation_phase = "0101") then -- Shift-IR - -- stay in this phase until the instruction registers (of all chips) have been shifted - operation_phase_next <= operation_phase; - -- -- we do not need to get a new word, because IR is at most 32 bits. - --if(bitcounter(4 downto 0) = "11111" ) then - -- substate_next <= getIRword_p3; - --end if; - - -- do we need to change to the next not removed chip or finish the register? - if(bitcounter >= length -1) then - bitcounter_next <= (others => '0'); - -- set the next not removed chip as the chip the following data is for - chipcounter_next <= nxt_not_removed_chip; - -- treat as new chip (get numregs, length, IRWord..) - substate_next <= newchip_p1; - else - bitcounter_next <= bitcounter + 1; - end if; - if (bitcounter = length -2) then - -- if next chip is 0, this means the current chip is the last chip and we finish the register with the next bit - if(nxt_not_removed_chip = invalid_chip) then - -- finish register - operation_phase_next <= operation_phase + 1; - end if; - end if; - -- length is set, because first operation already finished, here, so we can test it - if(to_integer(length) > 32) then - state_next <= idle; - last_error_code_next <= "011"; -- IR larger than 32 bit - end if; - elsif(operation_phase = "1000") then -- Run-Test-Idle - operation_next <= "10"; -- WRITE_DR - operation_phase_next <= "0000"; -- Select-DR-Scan - chipcounter_next <= first_not_removed_chip; -- reset chipcounter -- bug fixed (was set to 0) - bitcounter_next <= (others => '0'); -- reset bitcounter - end if; - - --last operation was: WRITE_DR - elsif(operation = "10") then - substate_next <= setOutputs_p8; -- output has to be done in all cases, only sometimes need to do more - if(operation_phase = "0010") then -- Shift-DR entered in last operation, but nothing shifted yet - substate_next <= newchip_p1; - elsif(operation_phase = "0011") then -- Shift-DR - -- stay in this phase until the data registers (of all chips) have been shifted - operation_phase_next <= operation_phase; - -- do we need to get a new word - if(bitcounter(4 downto 0) = "11111") then - substate_next <= samechip_newword_DR_p1; - end if; - -- do we need to change to the next not removed chip or finish the register? - if(bitcounter >= length -1) then - -- last bit of chip chipcounter has been sent as last operation - -- and we know, that it's not the last chip, otherwise we would be in the next phase - -- (this is changed in the processing state, if the last bit of the last chip is reached!) - bitcounter_next <= (others => '0'); - substate_next <= newchip_p1; - -- set this as the chip the following data is for - chipcounter_next <= nxt_not_removed_chip; - else - bitcounter_next <= bitcounter + 1; - end if; - if (bitcounter = length -2) then - -- if next chip is 0, this means the current chip is the last chip and we finish the register with the next bit - if(nxt_not_removed_chip = invalid_chip) then - -- finish register - operation_phase_next <= operation_phase + 1; - end if; - end if; - elsif(operation_phase = "0101") then -- Update DR - if(regcounter + 1 >= maxnumregs) then --this is the last JTAG clock cycle needed (going back to Run-Test-Idle) - last_tck_cycle_next <= '1'; - end if; - elsif(operation_phase = "0110") then -- Run-Test-Idle - if(regcounter + 1 < maxnumregs) then - regcounter_next <= regcounter + 1; -- start with next register - operation_next <= "00"; -- JTAG_RESET - operation_phase_next <= "0000"; -- Bit Nr. 0 - else - --operation_next <= "11"; -- none (finished) - --operation_phase_next <= "0000"; - -- the following will deactivate the jtag clock for one cycle, if another write follows, - enable_jtag_clock_next <= '0'; -- disable JTAG clock for WRITE operation - last_tck_cycle_next <= '0'; - state_next <= idle; - end if; - end if; - end if; - - end if; - when processing => - case substate is - when newchip_p1 => -- RAM_ADDR_NEXT: Numregs - ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(chipcounter); -- chip address - ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= (others => '0'); -- length&numregs - if(operation = "01") then - substate_next <= newchip_IR_wait_p2; - elsif(operation = "10") then - substate_next <= newchip_DR_p2; - else - state_next <= idle; - last_error_code_next <= "010"; -- unallowed operation for newchip_p1 - end if; - when newchip_IR_wait_p2 => -- WAIT - need numregs to get IR word - substate_next <= newchip_IR_wait_p3; - when newchip_IR_wait_p3 => -- WAIT - numregs_next <= unsigned(RAM_JTAG_REGISTERS_D_IN(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0)); -- numregs - numregs_configured_next((to_integer(chipcounter)+1)*MAX_REGISTERS_PLUS_ONE_LD-1 downto to_integer(chipcounter)*MAX_REGISTERS_PLUS_ONE_LD) <= RAM_JTAG_REGISTERS_D_IN(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0); - length_next <= unsigned(RAM_JTAG_REGISTERS_D_IN(MAX_REGLEN_PLUS_ONE_LD -1+16 downto 16)); -- IRLen - substate_next <= newchip_IR_p4; - when newchip_IR_p4 => -- RAM_ADDR_NEXT: IR Word - -- Update maxnumregs - if(maxnumregs < numregs) then - maxnumregs_next <= numregs; - end if; - -- *** RAM address for next next step *** -- WARNING: copy and pasted this block to samechip_newword_IR_p0 - ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(chipcounter); -- chip address - -- no more registers for this chip? - if(regcounter >= numregs) then - ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(to_unsigned(2*(to_integer(numregs)+1)+1 + to_integer(numregs), RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD)); -- BYPASS IR word - else - ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(to_unsigned(2*(to_integer(numregs)+1)+1 + to_integer(regcounter), RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD)); -- IR word - end if; - -- *** RAM address for next next step *** - substate_next <= newword_wait_p6; - - when newchip_DR_p2 => -- RAM_ADDR_NEXT: DR Pointer - -- WRITE_DR - -- *** RAM address for next next step *** - ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(chipcounter); -- chip address - ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(to_unsigned(2*to_integer(regcounter) + 2, RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD)); -- DR Pointer - -- *** RAM address for next next step *** - substate_next <= newchip_DR_p3; - when newchip_DR_p3 => -- RAM_ADDR_NEXT: DRLength - numregs_next <= unsigned(RAM_JTAG_REGISTERS_D_IN(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0)); - -- *** RAM address for next next step *** - ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(chipcounter); -- chip address - ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(to_unsigned(2*to_integer(regcounter) + 3, RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD)); - -- *** RAM address for next next step *** - substate_next <= newchip_DR_wait_p4; - when newchip_DR_wait_p4 => - -- Check if bypass register is loaded - if(to_integer(regcounter) >= to_integer(numregs)) then - -- BYPASS register loaded - length_next <= to_unsigned(1,MAX_REGLEN_PLUS_ONE_LD); - data_word_next <= (others => '0'); - if(to_integer(nxt_not_removed_chip ) = 0) then - operation_phase_next <= operation_phase + 1; - end if; - substate_next <= setOutputs_p8; - else -- normal operation - dr_pointer_next <= unsigned(RAM_JTAG_REGISTERS_D_IN(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0)); - substate_next <= newchip_DR_p5; - end if; - when newchip_DR_p5 => -- RAM_ADDR_NEXT: DR data word - length_next <= unsigned(RAM_JTAG_REGISTERS_D_IN(MAX_REGLEN_PLUS_ONE_LD-1 downto 0)); - -- *** RAM address for next next step *** -- WARNING: copy and pasted this block to samechip_newword_DR_p1 - ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(chipcounter); -- chip address - --ram_jtag_registers_a(7 downto 0) <= std_logic_vector(to_unsigned(2*to_integer(regcounter), 8) + 3); - ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(dr_pointer + bitcounter(MAX_REGLEN_LD-1 downto 5)); -- DR Word - -- *** RAM address for next next step *** - substate_next <= newword_wait_p6; - when newword_wait_p6 => - if(to_integer(length) = 0) then - state_next <= idle; - last_error_code_next <= "001"; - else - -- if only one bit in ir/dr, and this is the last chip, then we have to go to Exit1-IR/DR in this operation, this is why the decision can't be taken before processing in all cases - if((length = 1) and (nxt_not_removed_chip = invalid_chip)) then - operation_phase_next <= operation_phase + 1; - end if; - substate_next <= newword_p7; - end if; - when newword_p7 => -- get data word - data_word_next <= RAM_JTAG_REGISTERS_D_IN; - substate_next <= setOutputs_p8; - --- IR only has maximum of 32 bit, so there is no state samechip_newword_IR_p1 - when samechip_newword_DR_p1 => - -- *** RAM address for next next step *** -- WARNING: copy and pasted this block from newchip_DR_p5 - ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(chipcounter); -- chip address - --ram_jtag_registers_a(7 downto 0) <= std_logic_vector(to_unsigned(2*to_integer(regcounter), 8) + 3); - ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(dr_pointer + bitcounter(MAX_REGLEN_LD-1 downto 5)); -- DR Word - -- *** RAM address for next next step *** - substate_next <= newword_wait_p6; --- --- when getDRptr_p2 => --- -- *** do stuff with data from last step --- if(maxnumregs < numregs) then --- maxnumregs_next <= numregs; --- end if; --- -- *** end stuff with data from last step --- --- dr_pointer_next <= unsigned(RAM_JTAG_REGISTERS_D_IN(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0)); --- -- *** RAM address for next step *** --- ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(chipcounter); -- chip address --- -- no more registers for this chip? --- if(regcounter >= numregs) then --- length_next <= to_unsigned(1, length'length); -- Loaded BYPASS register (length=1) --- substate_next <= setOutputs_p5; --- else --- --ram_jtag_registers_a(7 downto 0) <= std_logic_vector(to_unsigned(2*to_integer(regcounter), 8) + 3); --- ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(2*regcounter + 3); --- substate_next <= getDRlength_p3; --- end if; --- -- *** RAM address for next step *** --- when getDRlength_p3 => --- length_next <= unsigned(RAM_JTAG_REGISTERS_D_IN(MAX_REGLEN_PLUS_ONE_LD-1 downto 0)); --- -- *** RAM address for next step: getDRword *** --- ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(chipcounter); -- chip address --- --ram_jtag_registers_a(7 downto 0) <= std_logic_vector(to_unsigned(2*to_integer(regcounter), 8) + 3); --- ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(dr_pointer + bitcounter(MAX_REGLEN_LD-1 downto 5)); -- DR Word --- -- *** RAM address for next step *** --- substate_next <= getDRword_p4; --- when getDRword_p4 => --- if(to_integer(length) = 0) then --- state_next <= idle; --- last_error_code_next <= "001"; --- else --- -- if only one bit in dr, then we have to go to Exit1-DR in this operation --- if(to_integer(length) = 1) then --- operation_phase_next <= operation_phase + 1; --- end if; --- data_word_next <= RAM_JTAG_REGISTERS_D_IN; --- substate_next <= setOutputs_p5; --- end if; --- when getIRlength_p2 => --- length_next <= unsigned(RAM_JTAG_REGISTERS_D_IN(MAX_REGLEN_PLUS_ONE_LD-1 downto 0)); --- -- *** RAM address for next step: getIRword *** --- ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-1 downto RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD) <= std_logic_vector(chipcounter); -- chip address --- -- no more registers for this chip? --- if(regcounter >= numregs) then --- ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(2*(numregs+1)+1 + numregs); -- BYPASS IR word --- else --- ram_jtag_registers_a_next(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(2*(numregs+1)+1 + regcounter); -- IR word --- end if; --- -- *** RAM address for next step *** --- substate_next <= getIRword_p3; --- when getIRword_p3 => --- if(to_integer(length) = 0) then --- state_next <= idle; --- last_error_code_next <= "001"; --- else --- -- if only one bit in ir, then we have to go to Exit1-IR in this operation --- if(to_integer(length) = 1) then --- operation_phase_next <= operation_phase + 1; --- end if; --- data_word_next <= RAM_JTAG_REGISTERS_D_IN; --- substate_next <= setOutputs_p5; --- end if; - when setOutputs_p8 => - tdi_next <= data_word(to_integer(bitcounter(4 downto 0))); - if(operation = "00") then -- JTAG_RESET - tms_next <= '1'; - elsif(operation = "01") then -- WRITE_IR - if(operation_phase = "0001") then - tms_next <= '1'; - elsif(operation_phase = "0010") then - tms_next <= '1'; - elsif(operation_phase = "0110") then - tms_next <= '1'; - elsif(operation_phase = "0111") then - tms_next <= '1'; - else - tms_next <= '0'; - end if; - elsif(operation = "10") then -- WRITE_DR - if(operation_phase = "0000") then - tms_next <= '1'; - elsif(operation_phase = "0100") then - tms_next <= '1'; - elsif(operation_phase = "0101") then - tms_next <= '1'; - else - tms_next <= '0'; - end if; - end if; - -- finished processing - state_next <= wait_begin_jtagbitcalc; - end case; - end case; -end process; - - -end architecture; diff --git a/vhdl/code/mathhelpers.vhd b/vhdl/code/mathhelpers.vhd deleted file mode 100644 index bbc99b2..0000000 --- a/vhdl/code/mathhelpers.vhd +++ /dev/null @@ -1,40 +0,0 @@ -library work; - -package mathhelpers is ---- find minimum number of bits required to ---- represent N as an unsigned binary number ---- -function log2_ceil(N: natural) return integer; -function plus_one_log2_ceil(N: natural) return positive; -end; - -package body mathhelpers is ---- Calculate the rounded up logarithm dualis (binary logarithm) CEIL(log2(N)) ---- represent N as an unsigned binary number ---- -function log2_ceil(N: natural) return integer is -begin -if N = 1 then - return 0; -elsif N < 3 then -return 1; -else -return 1 + log2_ceil((N-1)/2+1); -end if; -end; - - ---- from http://www.velocityreviews.com/forums/t22799-log2-n.html: ---- find minimum number of bits required to ---- represent N as an unsigned binary number ---- -function plus_one_log2_ceil(N: natural) return positive is -begin -if N < 2 then -return 1; -else -return 1 + plus_one_log2_ceil(N/2); -end if; -end; - -end; diff --git a/vhdl/code/ram_dp.vhd b/vhdl/code/ram_dp.vhd deleted file mode 100755 index 8dcce95..0000000 --- a/vhdl/code/ram_dp.vhd +++ /dev/null @@ -1,44 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; ---use work.trb_net_std.all; - -entity ram_dp is - generic( - depth : integer := 3; - width : integer := 16 - ); - port( - CLK : in std_logic; - wr1 : in std_logic; - a1 : in std_logic_vector(depth-1 downto 0); - dout1 : out std_logic_vector(width-1 downto 0); - din1 : in std_logic_vector(width-1 downto 0); - a2 : in std_logic_vector(depth-1 downto 0); - dout2 : out std_logic_vector(width-1 downto 0) - ); -end entity; - -architecture ram_dp_arch of ram_dp is - type ram_t is array(0 to 2**depth-1) of std_logic_vector(width-1 downto 0); - SIGNAL ram : ram_t ; -- := (others => (others => '0')); -begin - - - process(CLK) - begin - if rising_edge(CLK) then - if wr1 = '1' then - ram((conv_integer(a1))) <= din1; - dout1 <= din1; - else - dout1 <= ram(conv_integer(a1)); - end if; - dout2 <= ram(conv_integer(a2)); - end if; - end process; - -end architecture; diff --git a/vhdl/code/ram_mux2to1_readport.vhd b/vhdl/code/ram_mux2to1_readport.vhd deleted file mode 100755 index 0c06535..0000000 --- a/vhdl/code/ram_mux2to1_readport.vhd +++ /dev/null @@ -1,34 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; - -library work; - -entity ram_mux2to1_readport is - generic ( - depth : integer; - width : integer := 32 - ); - port ( - SELECT_IN : std_logic; - A0_IN : in std_logic_vector(depth-1 downto 0); - D0_OUT : out std_logic_vector(width-1 downto 0); - A1_IN : in std_logic_vector(depth-1 downto 0); - D1_OUT : out std_logic_vector(width-1 downto 0); - - RAM_A_OUT : out std_logic_vector(depth-1 downto 0); - RAM_DOUT_IN : in std_logic_vector(width-1 downto 0) - ); -end entity; - -architecture ram_mux2to1_readport_arch of ram_mux2to1_readport is -signal addr : std_logic_vector(depth-1 downto 0); -begin - -addr <= A0_IN when SELECT_IN = '0' else A1_IN; -RAM_A_OUT <= addr; - -D0_OUT <= RAM_DOUT_IN; -D1_OUT <= RAM_DOUT_IN; - -end architecture; diff --git a/vhdl/code/ram_mux2to1_writeport.vhd b/vhdl/code/ram_mux2to1_writeport.vhd deleted file mode 100755 index 1d2430f..0000000 --- a/vhdl/code/ram_mux2to1_writeport.vhd +++ /dev/null @@ -1,48 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; - -library work; - -entity ram_mux2to1_writeport is - generic ( - depth : integer; - width : integer := 32 - ); - port ( - SELECT_IN : in std_logic; - A0_IN : in std_logic_vector(depth-1 downto 0); - D0_OUT : out std_logic_vector(width-1 downto 0); - WR0_IN : in std_logic; - DIN0_IN : in std_logic_vector(width-1 downto 0); - - A1_IN : in std_logic_vector(depth-1 downto 0); - D1_OUT : out std_logic_vector(width-1 downto 0); - WR1_IN : in std_logic; - DIN1_IN : in std_logic_vector(width-1 downto 0); - - RAM_A_OUT : out std_logic_vector(depth-1 downto 0); - RAM_DOUT_IN : in std_logic_vector(width-1 downto 0); - RAM_WR_OUT : out std_logic; - RAM_DIN_OUT : out std_logic_vector(width-1 downto 0) - ); -end entity; - -architecture ram_mux2to1_writeport_arch of ram_mux2to1_writeport is -signal addr : std_logic_vector(depth-1 downto 0); -signal wr : std_logic; -signal din : std_logic_vector(width-1 downto 0); -begin - -addr <= A0_IN when SELECT_IN = '0' else A1_IN; -RAM_A_OUT <= addr; - -wr <= WR0_IN when SELECT_IN = '0' else WR1_IN; -RAM_WR_OUT <= wr; - -din <= DIN0_IN when SELECT_IN = '0' else DIN1_IN; -RAM_DIN_OUT <= din; -D0_OUT <= RAM_DOUT_IN; -D1_OUT <= RAM_DOUT_IN; - -end architecture; diff --git a/vhdl/code/ram_mux4to1_readport.vhd b/vhdl/code/ram_mux4to1_readport.vhd deleted file mode 100755 index b43173b..0000000 --- a/vhdl/code/ram_mux4to1_readport.vhd +++ /dev/null @@ -1,47 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; - -library work; - -entity ram_mux4to1_readport is - generic ( - depth : integer; - width : integer := 32 - ); - port ( - SELECT_IN : in std_logic_vector(1 downto 0); -- two bit select input - A0_IN : in std_logic_vector(depth-1 downto 0); - D0_OUT : out std_logic_vector(width-1 downto 0); - A1_IN : in std_logic_vector(depth-1 downto 0); - D1_OUT : out std_logic_vector(width-1 downto 0); - A2_IN : in std_logic_vector(depth-1 downto 0); - D2_OUT : out std_logic_vector(width-1 downto 0); - A3_IN : in std_logic_vector(depth-1 downto 0); - D3_OUT : out std_logic_vector(width-1 downto 0); - - RAM_A_OUT : out std_logic_vector(depth-1 downto 0); - RAM_DOUT_IN : in std_logic_vector(width-1 downto 0) - ); -end entity; - -architecture ram_mux4to1_readport_arch of ram_mux4to1_readport is ---signal addr : std_logic_vector(depth-1 downto 0); -begin - ---addr <= A0_IN when SELECT_IN = "00" else A1_IN when SELECT_IN = "01" else --- A2_IN when SELECT_IN = "10" else A3_IN; - ---process (addr, SELECT_IN, A0_IN, A1_IN, A2_IN, A3_IN) ---begin --- RAM_A_OUT <= addr; ---end process; -RAM_A_OUT <= A0_IN when SELECT_IN = "00" else A1_IN when SELECT_IN = "01" else - A2_IN when SELECT_IN = "10" else A3_IN; - -D0_OUT <= RAM_DOUT_IN; -D1_OUT <= RAM_DOUT_IN; -D2_OUT <= RAM_DOUT_IN; -D3_OUT <= RAM_DOUT_IN; - -end architecture; diff --git a/vhdl/code/tb/jtag_cmd_m26c_test.vhd b/vhdl/code/tb/jtag_cmd_m26c_test.vhd deleted file mode 100644 index 9ff2811..0000000 --- a/vhdl/code/tb/jtag_cmd_m26c_test.vhd +++ /dev/null @@ -1,3399 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; ---USE IEEE.std_logic_ARITH.ALL; ---USE IEEE.std_logic_UNSIGNED.ALL; -USE IEEE.numeric_std.ALL; -library work; ---use work.trb_net_std.all; ---use work.trb_net_components.all; --- use work.trb_net16_hub_func.all; ---use work.version.all; -use work.jtag_constants.all; - - - -entity jtag_cmd_m26c_test is -end entity; - - -architecture arch of jtag_cmd_m26c_test is -component CRC_32 is - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(31 downto 0); - CRC_OUT : out std_logic_vector(31 downto 0); - CRC_match : out std_logic - ); -end component; --- -component jtag_cmd_m26c is - generic( - MAX_NUMCHIPS : integer := 7; -- maximum number of chips in this chain controllers chain (because number of chips can be 0, best chose 2^n-1 as maximum to save logic. if memory should be used completely, choose 2^n.) - MAX_NUMCHIPS_PLUS_ONE_LD : integer := 3; -- LD of value plus one, rounded up, or ld rounded down + 1, because the next binary digit needs one bit more (i.e, 2 needs second bit) - MAX_NUMCHIPS_LD : integer := 3; -- LD of value, rounded up - MAX_REGISTERS : integer := 14; -- number of registers per chip. Because of ram3 layout, values of 2^n-2 should be chosen. - MAX_REGISTERS_LD : integer := 4; -- LD of value, rounded up. - MAX_REGISTERS_PLUS_ONE_LD : integer := 4; -- LD of (value plus one) - MAX_REGISTERS_PLUS_TWO_LD : integer := 4; -- LD of (value plus two) - MAX_REGLEN_LD : integer := 12; -- LD of naximum register length. - MAX_REGLEN_PLUS_ONE_LD : integer := 12; -- LD of (register length+1) - - WRITE_ERROR_THRESHOLD : integer := 3; -- if at least WRITE_ERROR_THRESHOLD bits are different from written value, count as WRITE_ERROR/DATA_CHANGED. - - READ_ERROR_THRESHOLD : integer := 4; -- if at least READ_ERROR_THRESHOLD bits are different from 32 bit ID, set - - JTAG_M26_IRLEN : integer := 5; -- length of the instruction register of the connected chips - JTAG_M26_IRLEN_LD : integer := 3; -- ld of value, rounded up - JTAG_M26_IR_ID_CODE : std_logic_vector(4 downto 0) := "01110"; -- Code selecting DEV_ID register of Mimosa26 - JTAG_M26_DEV_ID : std_logic_vector(31 downto 0) := x"4D323601"; -- Mimosa26 DEV_ID, which the sensor should send. - - RAM_JTAG_REGISTERS_DEPTH : integer := 11; -- will be split up into MAX_NUMCHIPS_LD bits for chip address, rest is for addressing words in that chip block. word size is 32 bit. --- GLOBAL_JTAG_COUNTER_BITS : integer := 10; -- - JTAG_CHAIN_BROKEN_COUNTER_BITS : integer := 10; -- counter width - JTAG_TDO_EXPECTED_MAXDELAY : integer := 3; -- set range to 0..value for delay of expected TDO value - JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD : integer := 2 -- ceil of ld( value plus one) -); - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - JTAG_TMS_OUT : out std_logic; - JTAG_TCK_OUT : out std_logic; - JTAG_TDI_OUT : out std_logic; - JTAG_TDO_IN : in std_logic; - - BUS_DATA_IN : in std_logic_vector(31 downto 0); - BUS_DATA_OUT : out std_logic_vector(31 downto 0); - BUS_ADDR_IN : in std_logic_vector(8 downto 0); - BUS_READ_IN : in std_logic; - BUS_WRITE_IN : in std_logic; - - BUS_DATAREADY_OUT : out std_logic; - BUS_NO_MORE_DATA_OUT : out std_logic; - BUS_WRITE_ACK_OUT : out std_logic; - BUS_UNKNOWN_ADDR_OUT : out std_logic; - - OFF_SPILL_IN : in std_logic; - MY_STATUS_OUT : out std_logic_vector(8 downto 0); - --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0); - --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0); - IDLE_OUT : out std_logic; - PROG_JTAG_FINISHED_OUT:out std_logic; - READ_ID_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0); - WRITE_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0); - DATA_CHANGED_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0); - SAMPLING_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0); - RUN_COUNTER_OUT : out std_logic_vector(31 downto 0); - - STARTED_OUT : out std_logic; - LAST_RUN_SUCCESSFUL_OUT : out std_logic; - LAST_DATA_CHANGED_OUT : out std_logic; - LAST_WRITE_ERRORS_OUT : out std_logic; - LAST_READ_ERRORS_OUT : out std_logic; - CRC_ERROR_OUT : out std_logic - - --BUS_TIMEOUT_IN : in std_logic; - ); -end component; ---component jtag_cmd_m26c is --- port( --- CLK_IN : in std_logic; --- RESET_IN : in std_logic; --- --- JTAG_TMS_OUT : out std_logic; --- JTAG_TCK_OUT : out std_logic; --- JTAG_TDI_OUT : out std_logic; --- JTAG_TDO_IN : in std_logic; --- --- BUS_DATA_IN : in std_logic_vector(31 downto 0); --- BUS_DATA_OUT : out std_logic_vector(31 downto 0); --- BUS_ADDR_IN : in std_logic_vector(8 downto 0); --- BUS_READ_IN : in std_logic; --- BUS_WRITE_IN : in std_logic; --- BUS_DATAREADY_OUT : out std_logic; --- BUS_NO_MORE_DATA_OUT : out std_logic; --- BUS_WRITE_ACK_OUT : out std_logic; --- BUS_UNKNOWN_ADDR_OUT : out std_logic; --- OFF_SPILL_IN : in std_logic; --- MY_STATUS_OUT : out std_logic_vector(8 downto 0); --- --MON_FIFO_DATA_OUT : out std_logic_vector(511 downto 0); --- --MON_FIFO_WRITE_OUT : out std_logic_vector(15 downto 0); --- --- IDLE_OUT : out std_logic; --- PROG_JTAG_FINISHED_OUT:out std_logic --- ); ---end component; -component top is -port( - TCK_EMU: in std_logic; - TMS_EMU: in std_logic; - TDI_EMU: in std_logic; - TDO_EMU: out std_logic; - TRSTB_EMU: in std_logic - ); - -end component; -signal clk_in, reset_in : std_logic; -signal jtag_tms_out, jtag_tck_out, jtag_tdi_out, jtag_tdo_in, trstb : std_logic; -signal bus_data_in : std_logic_vector(31 downto 0); -signal bus_data_out : std_logic_vector(31 downto 0); -signal bus_addr_in : std_logic_vector(15 downto 0); -signal bus_read_in : std_logic; -signal bus_write_in : std_logic; -signal bus_dataready_out : std_logic; -signal bus_no_more_data_out : std_logic; -signal bus_write_ack_out : std_logic; -signal bus_unknown_addr_out : std_logic; -signal trigger_jtag_write : std_logic; -signal prog_jtag_finished_out : std_logic; -signal idle_out : std_logic; -constant RAM_JTAG_REGISTERS_DEPTH : integer := 11; - -signal ramcounter : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); -signal statuscounter : std_logic_vector(4 downto 0); -signal crc32_1_clk_en : std_logic; -signal crc32_reset_in : std_logic; -signal crc32_1_data_in : std_logic_vector(31 downto 0); -signal crc32_1_crc_out : std_logic_vector(31 downto 0); -signal a,b : std_logic_vector(3 downto 0); -signal ergebnis : std_logic_vector(7 downto 0); -signal jtag1_out : std_logic; -signal jtag2_out : std_logic; -signal jtag3_in : std_logic; -signal broken : std_logic; - ---signal data_in, ready_for_cmd_out, data_out, data_arrived_out : std_logic; -begin -crc32_1: CRC_32 port map( - CLK => clk_in, - RESET => crc32_reset_in, - CLK_EN => crc32_1_clk_en, - DATA_IN => crc32_1_data_in, - CRC_OUT => crc32_1_crc_out, - CRC_match => open - ); -jtag_test1 : jtag_cmd_m26c port map( CLK_IN => clk_in, - RESET_IN => reset_in, - JTAG_TMS_OUT => jtag_tms_out, - JTAG_TCK_OUT => jtag_tck_out, - JTAG_TDI_OUT => jtag_tdi_out, - JTAG_TDO_IN => jtag_tdo_in, - BUS_DATA_IN => bus_data_in, - BUS_DATA_OUT => bus_data_out, - BUS_ADDR_IN => bus_addr_in(8 downto 0), - BUS_READ_IN => bus_read_in, - BUS_WRITE_IN => bus_write_in, - BUS_DATAREADY_OUT => bus_dataready_out, - BUS_NO_MORE_DATA_OUT => bus_no_more_data_out, - BUS_WRITE_ACK_OUT => bus_write_ack_out, - BUS_UNKNOWN_ADDR_OUT => bus_unknown_addr_out, - OFF_SPILL_IN => trigger_jtag_write, - IDLE_OUT => idle_out, - PROG_JTAG_FINISHED_OUT => prog_jtag_finished_out -); ---top1 : top port map( TCK_EMU => jtag_tck_out, --- TMS_EMU => jtag_tms_out, --- TDI_EMU => jtag_tdi_out, --- TDO_EMU => jtag1_out, --- TRSTB_EMU => trstb ---); ---top2 : top port map( TCK_EMU => jtag_tck_out, --- TMS_EMU => jtag_tms_out, --- TDI_EMU => jtag1_out, --- TDO_EMU => jtag2_out, --- TRSTB_EMU => trstb ---); ---top3 : top port map( TCK_EMU => jtag_tck_out, --- TMS_EMU => jtag_tms_out, --- TDI_EMU => jtag3_in, --- TDO_EMU => jtag_tdo_in, --- TRSTB_EMU => trstb ---); - -jtag3_in <= jtag2_out when broken = '0' else '0'; -testtest_commands : process -begin - --jtag_tdo_in <= '0'; - broken <= '0'; - bus_addr_in(15 downto 0) <= x"0000"; - bus_data_in(31 downto 8) <= x"000000"; - bus_data_in(7 downto 0) <= M26C_CMD_NONE; - bus_write_in <= '0'; - bus_read_in <= '0'; - trigger_jtag_write <= '0'; - ramcounter <= (others => '0'); - statuscounter <= (others => '0'); - crc32_1_data_in <= x"00000000"; - crc32_1_clk_en <= '0'; - trstb <= '1'; - reset_in <= '1'; - crc32_reset_in <= '1'; - wait for 200 ns; - trstb <= '0'; - reset_in <= '0'; - crc32_reset_in <= '0'; - wait for 200 ns; - trstb <= '1'; - wait for 100 ns; - - - - CHIPLOOP: for i in 2 downto 0 loop - crc32_reset_in <= '1'; - wait for 200 ns; - crc32_reset_in <= '0'; - wait for 200 ns; - ramcounter <= (others => '0'); - - bus_data_in(31 downto 0) <= std_logic_vector(to_unsigned(i,32)); - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_RAM_BASEADDR; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - wait until rising_edge(bus_write_ack_out); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"0005000B"; -- line 1 - crc32_1_data_in <= x"0005000B"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"4D323601"; -- line 2 - crc32_1_data_in <= x"4D323601"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000025"; -- line 3 - crc32_1_data_in <= x"00000025"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000098"; -- line 4 - crc32_1_data_in <= x"00000098"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"0000002A"; -- line 5 - crc32_1_data_in <= x"0000002A"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000008"; -- line 6 - crc32_1_data_in <= x"00000008"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"0000002B"; -- line 7 - crc32_1_data_in <= x"0000002B"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000008"; -- line 8 - crc32_1_data_in <= x"00000008"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"0000002C"; -- line 9 - crc32_1_data_in <= x"0000002C"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000028"; -- line 10 - crc32_1_data_in <= x"00000028"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"0000002E"; -- line 11 - crc32_1_data_in <= x"0000002E"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000080"; -- line 12 - crc32_1_data_in <= x"00000080"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000032"; -- line 13 - crc32_1_data_in <= x"00000032"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000040"; -- line 14 - crc32_1_data_in <= x"00000040"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000034"; -- line 15 - crc32_1_data_in <= x"00000034"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000030"; -- line 16 - crc32_1_data_in <= x"00000030"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000036"; -- line 17 - crc32_1_data_in <= x"00000036"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"000000A0"; -- line 18 - crc32_1_data_in <= x"000000A0"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"0000003B"; -- line 19 - crc32_1_data_in <= x"0000003B"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000480"; -- line 20 - crc32_1_data_in <= x"00000480"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"0000005F"; -- line 21 - crc32_1_data_in <= x"0000005F"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000480"; -- line 22 - crc32_1_data_in <= x"00000480"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000083"; -- line 23 - crc32_1_data_in <= x"00000083"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000480"; -- line 24 - crc32_1_data_in <= x"00000480"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"51ED658E"; -- line 25 - crc32_1_data_in <= x"51ED658E"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"0000000F"; -- line 26 - crc32_1_data_in <= x"0000000F"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"0000001E"; -- line 27 - crc32_1_data_in <= x"0000001E"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"0000001D"; -- line 28 - crc32_1_data_in <= x"0000001D"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000013"; -- line 29 - crc32_1_data_in <= x"00000013"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000012"; -- line 30 - crc32_1_data_in <= x"00000012"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000016"; -- line 31 - crc32_1_data_in <= x"00000016"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000017"; -- line 32 - crc32_1_data_in <= x"00000017"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000015"; -- line 33 - crc32_1_data_in <= x"00000015"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000011"; -- line 34 - crc32_1_data_in <= x"00000011"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000010"; -- line 35 - crc32_1_data_in <= x"00000010"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000014"; -- line 36 - crc32_1_data_in <= x"00000014"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"0000001F"; -- line 37 - crc32_1_data_in <= x"0000001F"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"0A0A0A64"; -- line 38 - crc32_1_data_in <= x"0A0A0A64"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"8020280A"; -- line 39 - crc32_1_data_in <= x"8020280A"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"FFFF3276"; -- line 40 - crc32_1_data_in <= x"FFFF3276"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"2076FFAA"; -- line 41 - crc32_1_data_in <= x"2076FFAA"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00643220"; -- line 42 - crc32_1_data_in <= x"00643220"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000002"; -- line 43 - crc32_1_data_in <= x"00000002"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 44 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"23F00000"; -- line 45 - crc32_1_data_in <= x"23F00000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 46 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"7FFFFFFF"; -- line 47 - crc32_1_data_in <= x"7FFFFFFF"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"001C6000"; -- line 48 - crc32_1_data_in <= x"001C6000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"01C03C00"; -- line 49 - crc32_1_data_in <= x"01C03C00"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"7FFF0040"; -- line 50 - crc32_1_data_in <= x"7FFF0040"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"FFFFFFFF"; -- line 51 - crc32_1_data_in <= x"FFFFFFFF"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"AAAAAAAA"; -- line 52 - crc32_1_data_in <= x"AAAAAAAA"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"FC00E000"; -- line 53 - crc32_1_data_in <= x"FC00E000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000008"; -- line 54 - crc32_1_data_in <= x"00000008"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"05552000"; -- line 55 - crc32_1_data_in <= x"05552000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"E0016000"; -- line 56 - crc32_1_data_in <= x"E0016000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"82AA0555"; -- line 57 - crc32_1_data_in <= x"82AA0555"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"10000555"; -- line 58 - crc32_1_data_in <= x"10000555"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"05553000"; -- line 59 - crc32_1_data_in <= x"05553000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 60 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 61 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 62 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 63 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 64 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 65 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 66 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 67 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 68 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 69 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 70 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 71 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 72 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 73 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 74 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 75 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 76 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 77 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 78 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 79 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 80 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 81 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 82 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 83 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 84 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 85 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 86 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 87 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 88 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 89 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 90 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 91 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 92 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 93 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"50000000"; -- line 94 - crc32_1_data_in <= x"50000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"05555555"; -- line 95 - crc32_1_data_in <= x"05555555"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"33310000"; -- line 96 - crc32_1_data_in <= x"33310000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 97 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 98 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 99 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 100 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 101 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 102 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 103 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 104 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 105 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 106 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 107 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 108 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 109 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 110 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 111 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 112 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 113 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 114 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 115 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 116 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 117 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 118 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 119 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 120 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 121 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 122 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 123 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 124 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 125 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 126 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 127 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 128 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000000"; -- line 129 - crc32_1_data_in <= x"00000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"30000000"; -- line 130 - crc32_1_data_in <= x"30000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00000333"; -- line 131 - crc32_1_data_in <= x"00000333"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"F6F6FFF1"; -- line 132 - crc32_1_data_in <= x"F6F6FFF1"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111116"; -- line 133 - crc32_1_data_in <= x"11111116"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 134 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 135 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 136 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 137 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 138 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 139 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 140 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 141 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 142 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 143 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 144 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 145 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 146 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 147 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 148 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 149 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 150 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 151 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 152 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 153 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 154 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 155 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 156 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 157 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 158 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 159 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 160 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 161 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 162 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 163 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"11111111"; -- line 164 - crc32_1_data_in <= x"11111111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"00011111"; -- line 165 - crc32_1_data_in <= x"00011111"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"40000000"; -- line 166 - crc32_1_data_in <= x"40000000"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"16464646"; -- line 167 - crc32_1_data_in <= x"16464646"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - - wait for 100 ns; - bus_data_in(31 downto 0) <= x"1CC3851D"; -- line 168 - crc32_1_data_in <= x"1CC3851D"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - crc32_1_clk_en <= '0'; - wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - - end loop; - - wait for 100 ns; - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(3,8)); - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ; - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - - wait for 100 ns; - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= M26C_CMD_SET_NUMCHIPS_CONFIGURED; - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - - wait for 100 ns; - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(10,8)); - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ; - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - - wait for 100 ns; - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH; - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - - wait for 100 ns; - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(5,8)); - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER; - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - - wait for 100 ns; - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_CLOCK_TIME1; - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - - wait for 100 ns; - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(0,8)); - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ; - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - - wait for 100 ns; - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_CLOCK_TIME2; - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - - wait for 100 ns; - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(5,8)); - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ; - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - - wait for 100 ns; - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_SAMPLE_TIME1; - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - - wait for 100 ns; - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(6,8)); - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ; - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - - wait for 100 ns; - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_SAMPLE_TIME2; - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - - wait for 100 ns; - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(7,8)); - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ; - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - - wait for 100 ns; - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_SAMPLE_TIME3; - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - - wait for 100 ns; - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(9,8)); - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ; - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - - wait for 100 ns; - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_SET_DATA_TIME; - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - - - wait for 500*8 ns; - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= M26C_CMD_START; - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - wait for 30 ns; - bus_write_in <= '0'; --- wait until jtag_tck_out = '1'; --- wait until jtag_tck_out = '0'; --- --jtag_tdo_in <= '1'; --- wait until jtag_tck_out = '1'; --- wait until jtag_tck_out = '0'; --- --jtag_tdo_in <= '0'; - - - -trigger_jtag_write <= '1'; -wait until idle_out = '0'; - trigger_jtag_write <= '0'; - -wait until idle_out <= '1'; -trigger_jtag_write <= '1'; -wait until idle_out = '0'; - trigger_jtag_write <= '0'; - - - wait for 100 ns; - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= x"07"; -- trigger copy ram1b to ram1c on next read-/write-error/datachanged - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ; - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - - wait for 100 ns; - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER; - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - broken <= '1'; - -wait until idle_out <= '1'; -trigger_jtag_write <= '1'; -wait until idle_out = '0'; - trigger_jtag_write <= '0'; - - -wait until idle_out <= '1'; -trigger_jtag_write <= '1'; -wait until idle_out = '0'; - trigger_jtag_write <= '0'; -broken <= '0'; - - wait until idle_out <= '1'; -trigger_jtag_write <= '1'; -wait until idle_out = '0'; - trigger_jtag_write <= '0'; - - wait until idle_out <= '1'; -trigger_jtag_write <= '1'; -wait until idle_out = '0'; - trigger_jtag_write <= '0'; - - wait until idle_out <= '1'; -trigger_jtag_write <= '1'; -wait until idle_out = '0'; - trigger_jtag_write <= '0'; - -wait until idle_out = '1'; - - - wait for 500*8 ns; - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= M26C_CMD_COPY_TO_STATUS2; - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - - wait for 500*8 ns; - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= (others => '0'); - bus_addr_in(15 downto 5) <= ADDR_STATUS2(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_STATUS2_UPDATING; - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - - wait for 500*8 ns; - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= (others => '0'); -- set baseaddr to 0 - bus_addr_in(15 downto 5) <= ADDR_STATUS2(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_STATUS2_RAM3B_BASEADDR; - wait for 20 ns; - wait until CLK_IN = '1'; - bus_write_in <= '1'; - wait for 30 ns; - bus_write_in <= '0'; - --- read status2 ram (error counters etc...) - STATUS2LOOP: for i in 0 to 15 loop - wait for 500*8 ns; - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= (others => '0'); - bus_addr_in(15 downto 5) <= ADDR_STATUS2(15 downto 5); - bus_addr_in(4 downto 0) <= std_logic_vector(unsigned(ADDR_STATUS2_RAM3B_BEGIN) + to_unsigned(i,4)); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_read_in <= '1'; - wait for 30 ns; - bus_read_in <= '0'; - end loop; - -wait for 500*8 ns; - bus_addr_in(15 downto 5) <= ADDR_STATUS(15 downto 5); - bus_addr_in(4 downto 0) <= statuscounter; - statuscounter <= std_logic_vector(unsigned(statuscounter)+1); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_read_in <= '1'; - wait for 30 ns; - bus_read_in <= '0'; -wait for 500*8 ns; - bus_addr_in(15 downto 5) <= ADDR_STATUS(15 downto 5); - bus_addr_in(4 downto 0) <= statuscounter; - statuscounter <= std_logic_vector(unsigned(statuscounter)+1); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_read_in <= '1'; - wait for 30 ns; - bus_read_in <= '0'; -wait for 500*8 ns; - bus_addr_in(15 downto 5) <= ADDR_STATUS(15 downto 5); - bus_addr_in(4 downto 0) <= statuscounter; - statuscounter <= std_logic_vector(unsigned(statuscounter)+1); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_read_in <= '1'; - wait for 30 ns; - bus_read_in <= '0'; -wait for 500*8 ns; - bus_addr_in(15 downto 5) <= ADDR_STATUS(15 downto 5); - bus_addr_in(4 downto 0) <= statuscounter; - statuscounter <= std_logic_vector(unsigned(statuscounter)+1); - wait for 20 ns; - wait until CLK_IN = '1'; - bus_read_in <= '1'; - wait for 30 ns; - bus_read_in <= '0'; --- --- wait for 500*8 ns; --- bus_data_in(31 downto 0) <= x"80FFFF01"; --- bus_addr_in(3 downto 0) <= ADDR_DATA; --- wait for 20 ns; --- wait until CLK_IN = '1'; --- bus_write_in <= '1'; --- wait for 20 ns; --- bus_write_in <= '0'; --- --- wait for 500*8 ns; --- bus_data_in(31 downto 0) <= x"00000020"; --- bus_addr_in(3 downto 0) <= ADDR_LENGTH; --- wait for 20 ns; --- wait until CLK_IN = '1'; --- bus_write_in <= '1'; --- wait for 20 ns; --- bus_write_in <= '0'; --- --- wait for 500*8 ns; --- bus_data_in(3 downto 0) <= CMD_SHIFT_DR; --- bus_addr_in(3 downto 0) <= ADDR_CMD; --- wait for 20 ns; --- wait until CLK_IN = '1'; --- bus_write_in <= '1'; --- wait for 20 ns; --- bus_write_in <= '0'; --- wait until jtag_tck_out = '1'; --- wait until jtag_tck_out = '0'; --- --jtag_tdo_in <= '1'; --- wait until jtag_tck_out = '1'; --- wait until jtag_tck_out = '0'; --- --jtag_tdo_in <= '0'; --- --- wait for 60*8 us; --- wait for 500*8 ns; --- bus_data_in(3 downto 0) <= "0000"; --- bus_addr_in(3 downto 0) <= ADDR_DATA; --- wait for 20 ns; --- wait until CLK_IN = '1'; --- bus_write_in <= '1'; --- wait for 20 ns; --- bus_write_in <= '0'; --- --- wait for 500*8 ns; --- bus_data_in(3 downto 0) <= CMD_UPDATE_DR; --- bus_addr_in(3 downto 0) <= ADDR_CMD; --- wait for 20 ns; --- wait until CLK_IN = '1'; --- bus_write_in <= '1'; --- wait for 20 ns; --- bus_write_in <= '0'; --- --- wait for 30*8 us; --- bus_data_in(3 downto 0) <= "0000"; --- bus_addr_in(3 downto 0) <= ADDR_DATA; --- wait for 20 ns; --- wait until CLK_IN = '1'; --- bus_read_in <= '1'; --- wait for 20 ns; --- bus_read_in <= '0'; --- --- wait for 30*8 us; --- jtag_tdo_in <= '1'; --- bus_data_in(3 downto 0) <= CMD_RESET_JTAG; --- bus_addr_in(3 downto 0) <= ADDR_CMD; --- wait for 20 ns; --- wait until CLK_IN = '1'; --- bus_write_in <= '1'; --- wait for 20 ns; --- bus_write_in <= '0'; - - --- cmd_in <= CMD_NONE; --- wait until READY_FOR_CMD_OUT = '1'; --- data_in <= '1'; --- cmd_in <= CMD_SHIFT_DR; --- wait for 30 ns; --- cmd_in <= CMD_NONE; --- wait until jtag_tck_out = '1'; --- wait until jtag_tck_out = '0'; --- jtag_tdo_in <= '1'; --- wait until READY_FOR_CMD_OUT = '1'; --- data_in <= '1'; --- cmd_in <= CMD_SHIFT_DR; --- wait for 30 ns; --- cmd_in <= CMD_NONE; --- wait until jtag_tck_out = '1'; --- wait until jtag_tck_out = '0'; --- jtag_tdo_in <= '0'; --- wait until READY_FOR_CMD_OUT = '1'; --- cmd_in <= CMD_UPDATE_DR; --- wait for 30 ns; --- cmd_in <= CMD_NONE; --- wait until READY_FOR_CMD_OUT = '1'; --- wait for 30 ns; --- cmd_in <= CMD_NONE; - wait; -end process; -testdriver_clk : process -begin - clk_in <= '0'; - wait for 5 ns; - clk_in <= '1'; - wait for 5 ns; -end process; - - -end architecture; diff --git a/vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2.vhd b/vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2.vhd deleted file mode 100644 index 974316a..0000000 --- a/vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2.vhd +++ /dev/null @@ -1,1063 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; ---USE IEEE.std_logic_ARITH.ALL; ---USE IEEE.std_logic_UNSIGNED.ALL; -USE IEEE.numeric_std.ALL; -library work; ---use work.trb_net_std.all; ---use work.trb_net_components.all; --- use work.trb_net16_hub_func.all; ---use work.version.all; -use work.jtag_constants.all; -use work.jtag_simulation_constants.all; - --- use TAP MI26 HARD -entity jtag_cmd_m26c_test_regvaluesfrominput2 is -generic( - numregs : integer := 11; - maxreglen : integer := 1152; - -- instruction_codes : instrArray := (0 => "10000", 1 => "10001", 2 => "10010", others => (others => '1')); -- in the given order these are the instruction codes of the registers to be programmed by the JTAG-Chain-Controller - --drlen : drlenArray := (0 => 32, 1=> 8, 2=> 1024, others => 32); -- length of the registers (same order as instruction_codes) - instruction_codes : instrArray := (0 => "01111", --BIAS_GEN - 1 => "10000", --LINE0_PATTERN_REG - 2 => "10001", --DIS_DISCRI - 3 => "10010", --SEQ_PIX_REG - 4 => "10011", --CTRL_PIX_REG - 5 => "10100", --LINE1_PATTERN_REG - 6 => "10101", --SEQ_SUZE_REG - 7 => "10110", --HEADER_TRAILER_REG - 8 => "10111", --CTRL_SUZE_REG - 9 => "11101", --RO_MODE1 - 10 => "11110", --RO_MODE0 - others => (others => '1')); - drlen : drlenArray := (0 => 152, 1=> 1152, 2=> 1152, 3=>128, 4=>40, 5=>1152, 6=>160, 7=>64, 8=>48, 9=>8, 10=>8, others => 0); - - numchips : integer := 3 -); -port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - REGISTERS_IN : in std_logic_vector(numchips*numregs*maxreglen-1 downto 0); - TRIGGER_IN : in std_logic - ); -end entity; - - -architecture arch of jtag_cmd_m26c_test_regvaluesfrominput2 is -component CRC_32 is - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(31 downto 0); - CRC_OUT : out std_logic_vector(31 downto 0); - CRC_match : out std_logic - ); -end component; --- -component jtag_cmd_m26c is - generic( - MAX_NUMCHIPS : integer := 7; -- maximum number of chips in this chain controllers chain (because number of chips can be 0, best chose 2^n-1 as maximum to save logic. if memory should be used completely, choose 2^n.) - MAX_REGISTERS : integer := 14; -- maximum number of registers per chip. Because of ram3 layout, values of 2^n-2 should be chosen. - MAX_REGLEN : integer := 4095; -- maximum number of bits for one register. Should be chosen as 2^n-1 - WRITE_ERROR_THRESHOLD : integer := 3; -- if at least WRITE_ERROR_THRESHOLD bits are different from written value, count as WRITE_ERROR/DATA_CHANGED. - - READ_ERROR_THRESHOLD : integer := 4; -- if at least READ_ERROR_THRESHOLD bits are different from 32 bit ID, set - - JTAG_M26_IRLEN : integer := 5; -- length of the instruction register of the connected chips - JTAG_M26_IR_ID_CODE : std_logic_vector(4 downto 0) := "01110"; -- Code selecting DEV_ID register of Mimosa26 - JTAG_M26_DEV_ID : std_logic_vector(31 downto 0) := x"4D323601"; -- Mimosa26 DEV_ID, which the sensor should send. - - RAM_JTAG_REGISTERS_DEPTH : integer := 11; -- will be split up into MAX_NUMCHIPS_LD bits for chip address, rest is for addressing words in that chip block. word size is 32 bit. --- GLOBAL_JTAG_COUNTER_BITS : integer := 10; -- - JTAG_CHAIN_BROKEN_COUNTER_BITS : integer := 10; -- counter width - JTAG_TDO_EXPECTED_MAXDELAY : integer := 3; -- set range to 0..value for delay of expected TDO value - RESET_WAIT_DURATION : unsigned := "10000000" -- 128 clock cycles at 100 mhz -); - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - JTAG_TMS_OUT : out std_logic; - JTAG_TCK_OUT : out std_logic; - JTAG_TDI_OUT : out std_logic; - JTAG_TDO_IN : in std_logic; - - BUS_DATA_IN : in std_logic_vector(31 downto 0); - BUS_DATA_OUT : out std_logic_vector(31 downto 0); - BUS_ADDR_IN : in std_logic_vector(8 downto 0); - BUS_READ_IN : in std_logic; - BUS_WRITE_IN : in std_logic; - - BUS_DATAREADY_OUT : out std_logic; - BUS_NO_MORE_DATA_OUT : out std_logic; - BUS_WRITE_ACK_OUT : out std_logic; - BUS_UNKNOWN_ADDR_OUT : out std_logic; - - --OFF_SPILL_IN : in std_logic; - RUN_REQUEST_IN : in std_logic; - WRITE_ONCE_REQUEST_IN : in std_logic; - MY_STATUS_OUT : out std_logic_vector(8 downto 0); - --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0); - --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0); - REQUEST_RESET_OUT : out std_logic; - IDLE_OUT : out std_logic; - PROG_JTAG_FINISHED_OUT:out std_logic; - READ_ID_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0); - WRITE_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0); - DATA_CHANGED_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0); - SAMPLING_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0); - RUN_COUNTER_OUT : out std_logic_vector(31 downto 0); - - STARTED_OUT : out std_logic; - LAST_RUN_SUCCESSFUL_OUT : out std_logic; - LAST_DATA_CHANGED_OUT : out std_logic; - LAST_WRITE_ERRORS_OUT : out std_logic; - LAST_READ_ERRORS_OUT : out std_logic; - CRC_ERROR_OUT : out std_logic - - --BUS_TIMEOUT_IN : in std_logic; - ); -end component; ---component jtag_cmd_m26c is --- port( --- CLK_IN : in std_logic; --- RESET_IN : in std_logic; --- --- JTAG_TMS_OUT : out std_logic; --- JTAG_TCK_OUT : out std_logic; --- JTAG_TDI_OUT : out std_logic; --- JTAG_TDO_IN : in std_logic; --- --- BUS_DATA_IN : in std_logic_vector(31 downto 0); --- BUS_DATA_OUT : out std_logic_vector(31 downto 0); --- BUS_ADDR_IN : in std_logic_vector(8 downto 0); --- BUS_READ_IN : in std_logic; --- BUS_WRITE_IN : in std_logic; --- BUS_DATAREADY_OUT : out std_logic; --- BUS_NO_MORE_DATA_OUT : out std_logic; --- BUS_WRITE_ACK_OUT : out std_logic; --- BUS_UNKNOWN_ADDR_OUT : out std_logic; --- OFF_SPILL_IN : in std_logic; --- MY_STATUS_OUT : out std_logic_vector(8 downto 0); --- --MON_FIFO_DATA_OUT : out std_logic_vector(511 downto 0); --- --MON_FIFO_WRITE_OUT : out std_logic_vector(15 downto 0); --- --- IDLE_OUT : out std_logic; --- PROG_JTAG_FINISHED_OUT:out std_logic --- ); ---end component; -component jtag_tap_mi26_hard is -port( - TCK_EMU: in std_logic; - TMS_EMU: in std_logic; - TDI_EMU: in std_logic; - TDO_EMU: out std_logic; - TRSTB_EMU: in std_logic; - - REGISTERS_OUT: out std_logic_vector(12*maxreglen-1 downto 0) - ); -end component; - ---signal clk_in, reset_in : std_logic; ---signal REGISTERS_IN : std_logic_vector(numchips*numregs*maxreglen-1 downto 0); -constant numchips_ld : integer := 2; - -signal jtag_tms_out, jtag_tck_out, jtag_tdi_out, jtag_tdo_in, trstb : std_logic; -signal bus_data_in : std_logic_vector(31 downto 0); -signal bus_data_out : std_logic_vector(31 downto 0); -signal bus_addr_in : std_logic_vector(15 downto 0); -signal bus_read_in : std_logic; -signal bus_write_in : std_logic; -signal bus_dataready_out : std_logic; -signal bus_no_more_data_out : std_logic; -signal bus_write_ack_out : std_logic; -signal bus_unknown_addr_out : std_logic; -signal trigger_jtag_write : std_logic; -signal prog_jtag_finished_out : std_logic; -signal idle_out : std_logic; -constant RAM_JTAG_REGISTERS_DEPTH : integer := 11; - -signal phase : unsigned(11 downto 0); -signal chip : unsigned(numchips_ld-1 downto 0); -signal ramcounter : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); -signal regpointer : std_logic_vector(7 downto 0); -signal regu : unsigned(3 downto 0); -signal wordu : unsigned(7 downto 0); -signal statuscounter : std_logic_vector(4 downto 0); -signal crc32_1_clk_en : std_logic; -signal crc32_reset_in : std_logic; -signal crc32_1_data_in : std_logic_vector(31 downto 0); -signal crc32_1_crc_out : std_logic_vector(31 downto 0); -signal a,b : std_logic_vector(3 downto 0); -signal ergebnis : std_logic_vector(7 downto 0); -signal jtag1_out : std_logic; -signal jtag2_out : std_logic; -signal jtag3_in : std_logic; -signal broken : std_logic; -type REG_ARRAY is array (numregs-1 downto 0) of std_logic_vector(maxreglen-1 downto 0); -type SENSORREGS is array (numchips-1 downto 0) of REG_ARRAY; -signal sensor_registers : SENSORREGS; - -type TAP_REGISTERS_ARRAY is array (numchips-1 downto 0) of std_logic_vector(12*maxreglen-1 downto 0); -signal tap_registers : TAP_REGISTERS_ARRAY; -signal registers_match : std_logic; -- contains result of asynchronous check, if registers input to the JTAG-Chain-Controller match - -- the output registers of the simulated MIMOSA-26 sensors -signal crc32_match_out : std_logic; -signal reset_request : std_logic; -signal taps_reset : std_logic; ---signal data_in, ready_for_cmd_out, data_out, data_arrived_out : std_logic; -begin -crc32_1: CRC_32 port map( - CLK => clk_in, - RESET => crc32_reset_in, - CLK_EN => crc32_1_clk_en, - DATA_IN => crc32_1_data_in, - CRC_OUT => crc32_1_crc_out, - CRC_match => crc32_match_out - ); -jtag_test1 : jtag_cmd_m26c port map( CLK_IN => clk_in, - RESET_IN => reset_in, - JTAG_TMS_OUT => jtag_tms_out, - JTAG_TCK_OUT => jtag_tck_out, - JTAG_TDI_OUT => jtag_tdi_out, - JTAG_TDO_IN => jtag_tdo_in, - BUS_DATA_IN => bus_data_in, - BUS_DATA_OUT => bus_data_out, - BUS_ADDR_IN => bus_addr_in(8 downto 0), - BUS_READ_IN => bus_read_in, - BUS_WRITE_IN => bus_write_in, - BUS_DATAREADY_OUT => bus_dataready_out, - BUS_NO_MORE_DATA_OUT => bus_no_more_data_out, - BUS_WRITE_ACK_OUT => bus_write_ack_out, - BUS_UNKNOWN_ADDR_OUT => bus_unknown_addr_out, - RUN_REQUEST_IN => trigger_jtag_write, - WRITE_ONCE_REQUEST_IN => '0', - REQUEST_RESET_OUT => reset_request, - IDLE_OUT => idle_out, - PROG_JTAG_FINISHED_OUT => prog_jtag_finished_out -); -tap1: jtag_tap_mi26_hard --- default_ir => "01110" -- ID_CODE -port map (TCK_EMU => jtag_tck_out, - TMS_EMU => jtag_tms_out, - TDI_EMU => jtag_tdi_out, - TDO_EMU => jtag1_out, - TRSTB_EMU => taps_reset, - REGISTERS_OUT => tap_registers(2) -); -tap2: jtag_tap_mi26_hard -port map (TCK_EMU => jtag_tck_out, - TMS_EMU => jtag_tms_out, - TDI_EMU => jtag1_out, - TDO_EMU => jtag2_out, - TRSTB_EMU => taps_reset, - REGISTERS_OUT => tap_registers(1) -); -tap3: jtag_tap_mi26_hard -port map (TCK_EMU => jtag_tck_out, - TMS_EMU => jtag_tms_out, - TDI_EMU => jtag2_out, - TDO_EMU => jtag_tdo_in, - TRSTB_EMU => taps_reset, - REGISTERS_OUT => tap_registers(0) -); ---top1 : top port map( TCK_EMU => jtag_tck_out, --- TMS_EMU => jtag_tms_out, --- TDI_EMU => jtag_tdi_out, --- TDO_EMU => jtag1_out, --- TRSTB_EMU => trstb ---); ---top2 : top port map( TCK_EMU => jtag_tck_out, --- TMS_EMU => jtag_tms_out, --- TDI_EMU => jtag1_out, --- TDO_EMU => jtag2_out, --- TRSTB_EMU => trstb ---); ---top3 : top port map( TCK_EMU => jtag_tck_out, --- TMS_EMU => jtag_tms_out, --- TDI_EMU => jtag3_in, --- TDO_EMU => jtag_tdo_in, --- TRSTB_EMU => trstb ---); --- psl EVENTUALLY_REGISTERS_MATCH: assert (eventually! registers_match = '1') @(rising_edge(CLK_IN)); --- psl EVENTUALLY_REGISTERS_MATCH_AND_FINISHED: assert (eventually! (registers_match = '1' and prog_jtag_finished_out = '1')) @(rising_edge(CLK_IN)); - -jtag3_in <= jtag2_out when broken = '0' else '0'; --- sensor_registers -SENSOR_REGISTERS_FROM_INPUT : process(REGISTERS_IN) -begin - SENSORLOOP: for si in 0 to numchips-1 loop - REGLOOP: for regi in 0 to numregs-1 loop - sensor_registers(si)(regi) <= REGISTERS_IN(si*maxreglen*numregs+(regi+1)*maxreglen-1 downto si*maxreglen*numregs+regi*maxreglen); - end loop; - end loop; -end process; - -compare_registers : process(sensor_registers, tap_registers) -variable deviation : std_logic; -begin - deviation := '0'; - SENSORLOOP: for si in 0 to numchips-1 loop - REGLOOP: for regi in 0 to numregs-1 loop - -- for bits in 0 to drlen(regi)-1 - if(sensor_registers(si)(regi)(drlen(regi)-1 downto 0) /= tap_registers(si)(regi*maxreglen+drlen(regi)-1 downto regi*maxreglen)) then - deviation := '1'; - else - -- this is purposefully wrong to test verification - -- deviation := '1'; - end if; - end loop; - end loop; - registers_match <= not deviation; - --wait for 100ns; -end process; - - -stimulus_statemachine : process (CLK_IN) -begin - if(rising_edge(CLK_IN)) then - phase <= phase + 1; - taps_reset <= '0'; - case phase is - when x"000" => - if( not(TRIGGER_IN = '1')) then - phase <= phase; - - end if; - when x"001" => - --trstb <= '1'; - taps_reset <= '1'; - - when x"002" => - --trstb <= '0'; - taps_reset <= '0'; - when x"003" => - chip <= (others => '0'); - when x"004" => - --CHIPLOOP: for i in 0 to numchips-1 loop - if (not(chip < numchips)) then - phase <= x"005"; - else - phase <= x"100"; -- chiploop - end if; - when x"100" => - ramcounter <= (others => '0'); - bus_data_in(31 downto numchips_ld) <= (others => '0'); - bus_data_in(numchips_ld - 1 downto 0) <= std_logic_vector(chip); -- select ram1a window - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_RAM_BASEADDR; - when x"101" => - bus_write_in <= '1'; - when x"102" => - crc32_reset_in <= '1'; - when x"103" => - crc32_reset_in <= '0'; - when x"104" => - bus_write_in <= '0'; - when x"105" => - when x"106" => - when x"107" => - when x"108" => - bus_data_in(31 downto 0) <= x"0005" & std_logic_vector(to_unsigned(numregs,16)); -- line 1: numregs (lower 16 bits) and irlen (higher 16 bits) - crc32_1_data_in <= x"0005" & std_logic_vector(to_unsigned(numregs,16)); - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - when x"109" => - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; --wait for 15 ns; - when x"10A" => - crc32_1_clk_en <= '0'; - when x"10B" => - when x"10C" => - bus_write_in <= '0'; - when x"10D" => - when x"10E" => - when x"10F" => - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - when x"110" => - bus_data_in(31 downto 0) <= x"4D323601"; -- line 2 - crc32_1_data_in <= x"4D323601"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - when x"111" => - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; --wait for 15 ns; - when x"112" => - crc32_1_clk_en <= '0'; - when x"113" => - when x"114" => - bus_write_in <= '0'; - when x"115" => - when x"116" => - when x"117" => - --wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - -- header pointer+len CRC IRs - -- there are 2 + 2*numregs +1 +(numregs+1) - -- = 3*numregs+4 - -- words in front of the DRs section - regpointer <= std_logic_vector(to_unsigned(3*numregs+4, 8)); -- max 8kbit with 32 bit words ==> 8 address bits - regu <= (others => '0'); - when x"118" => - --REGLOOP1: for regi in 0 to numregs-1 loop - if (not (regu < numregs)) then - phase <= x"119"; - else - phase <= x"200"; -- REGLOOP1 - end if; - when x"200" => - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= regpointer; -- pointer - crc32_1_data_in(31 downto 8) <= (others => '0'); - crc32_1_data_in(7 downto 0) <= regpointer; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - when x"201" => - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; --wait for 15 ns; - when x"202" => - crc32_1_clk_en <= '0'; - when x"203" => - when x"204" => - bus_write_in <= '0'; - when x"205" => - when x"206" => - when x"207" => - --wait until rising_edge(bus_write_ack_out); - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - regpointer <= std_logic_vector(unsigned(regpointer) + (drlen(to_integer(regu))+31)/32); - when x"208" => - bus_data_in(31 downto 0) <= std_logic_vector(to_unsigned(drlen(to_integer(regu)),32)); -- length - crc32_1_data_in <= std_logic_vector(to_unsigned(drlen(to_integer(regu)),32)); - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - when x"209" => - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; --wait for 15 ns; - when x"20A" => - crc32_1_clk_en <= '0'; - when x"20B" => - when x"20C" => - bus_write_in <= '0'; - when x"20D" => - when x"20E" => - when x"20F" => - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - regu <= regu + 1; - phase <= x"118"; - --end loop; - - when x"119" => - bus_data_in(31 downto 0) <= crc32_1_crc_out; -- CRC x"51ED658E"; -- line 25 - crc32_1_data_in <= crc32_1_crc_out; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - when x"11A" => - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; --wait for 15 ns; - when x"11B" => - crc32_1_clk_en <= '0'; - when x"11C" => - when x"11D" => - bus_write_in <= '0'; - when x"11E" => - when x"11F" => - when x"120" => - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - regu <= (others => '0'); - when x"121" => - -- REGLOOP2: for regi in 0 to numregs-1 loop - if (not (regu < numregs)) then - phase <= x"122"; - else - phase <= x"300"; -- REGLOOP2 - end if; - when x"300" => - bus_data_in(31 downto IRLEN) <= (others => '0'); - bus_data_in(IRLEN-1 downto 0) <= instruction_codes(to_integer(regu)); -- IR regi - crc32_1_data_in(31 downto IRLEN) <= (others => '0'); - crc32_1_data_in(IRLEN-1 downto 0) <= instruction_codes(to_integer(regu)); - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - when x"301" => - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; --wait for 15 ns; - when x"302" => - crc32_1_clk_en <= '0'; - when x"303" => - when x"304" => - bus_write_in <= '0'; - when x"305" => - when x"306" => - when x"307" => - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - when x"308" => - -- REGLOOP2: for regi in 0 to numregs-1 loop - --end loop; - regu <= regu + 1; - phase <= x"121"; - when x"122" => - -- Bypass Register IR - bus_data_in(31 downto 0) <= x"0000001F"; -- line 37 - crc32_1_data_in <= x"0000001F"; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - when x"123" => - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; --wait for 15 ns; - when x"124" => - crc32_1_clk_en <= '0'; - when x"125" => - when x"126" => - bus_write_in <= '0'; - when x"127" => - when x"128" => - when x"129" => - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - regu <= (others => '0'); - when x"12A" => - when x"12B" => - -- REGLOOP3: for regi in 0 to numregs-1 loop - if (not (regu < numregs)) then - phase <= x"12C"; - else - phase <= x"400"; -- REGLOOP3 - wordu <= (others => '0'); - end if; - when x"400" => - -- WORDLOOP: for wi in 0 to (drlen(regi)-1)/32 loop - if (not (wordu < (drlen(to_integer(regu))-1)/32+1)) then - phase <= x"401"; - else - phase <= x"500"; -- WORDLOOP - end if; - when x"500" => - -- data registers - -- loop over words - bus_data_in(31 downto 0) <= sensor_registers(to_integer(chip))(to_integer(regu))(32*(to_integer(wordu)+1)-1 downto 32*to_integer(wordu)); -- DR regi, word wi, sensor i - crc32_1_data_in(31 downto 0) <= sensor_registers(to_integer(chip))(to_integer(regu))(32*(to_integer(wordu)+1)-1 downto 32*to_integer(wordu)); - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - when x"501" => - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; --wait for 15 ns; - when x"502" => - crc32_1_clk_en <= '0'; - when x"503" => - when x"504" => - bus_write_in <= '0'; - when x"505" => - when x"506" => - when x"507" => - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - when x"508" => - when x"509" => - --end loop; - wordu <= wordu + 1; - phase <= x"400"; - when x"401" => - --end loop; - regu <= regu + 1; - phase <= x"12B"; - when x"12C" => - -- write CRC - bus_data_in(31 downto 0) <= crc32_1_crc_out; - crc32_1_data_in <= crc32_1_crc_out; - bus_addr_in(15 downto 8) <= ADDR_RAM(15 downto 8); - bus_addr_in(7 downto 0) <= ramcounter(7 downto 0); - when x"12D" => - bus_write_in <= '1'; - crc32_1_clk_en <= '1'; --wait for 15 ns; - when x"12E" => - crc32_1_clk_en <= '0'; - when x"12F" => - when x"130" => - bus_write_in <= '0'; - when x"131" => - when x"132" => - when x"133" => - ramcounter <= std_logic_vector(unsigned(ramcounter) + 1); - when x"134" => - when x"135" => - chip <= chip + 1; - phase <= x"004"; - -- end loop; - - - when x"005" => - when x"006" => - -- continue: CHIPSLOOP done - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(numchips,8)); - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ; - when x"007" => - bus_write_in <= '1'; - when x"008" => - when x"009" => - when x"00A" => - bus_write_in <= '0'; - when x"00B" => - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= M26C_CMD_SET_NUMCHIPS_CONFIGURED; - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; - when x"00C" => - bus_write_in <= '1'; - when x"00D" => - when x"00E" => - when x"00F" => - bus_write_in <= '0'; - when x"010" => - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(10,8)); - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ; - when x"011" => - bus_write_in <= '1'; - when x"012" => - when x"013" => - when x"014" => - bus_write_in <= '0'; - --when x"014" => - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH; - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; - when x"015" => - bus_write_in <= '1'; - when x"016" => - when x"017" => - when x"018" => - bus_write_in <= '0'; - when x"019" => - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(5,8)); - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER; - when x"01A" => - bus_write_in <= '1'; - when x"01B" => - when x"01C" => - when x"01D" => - bus_write_in <= '0'; - when x"01E" => - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_CLOCK_TIME1; - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; - when x"01F" => - bus_write_in <= '1'; - when x"020" => - when x"021" => - when x"022" => - bus_write_in <= '0'; - when x"023" => - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(0,8)); - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ; - when x"024" => - bus_write_in <= '1'; - when x"025" => - when x"026" => - when x"027" => - bus_write_in <= '0'; - when x"028" => - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_CLOCK_TIME2; - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; - when x"029" => - bus_write_in <= '1'; - when x"02A" => - when x"02B" => - when x"02C" => - bus_write_in <= '0'; - when x"02D" => - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(5,8)); - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ; - when x"02E" => - bus_write_in <= '1'; - when x"02F" => - when x"030" => - when x"031" => - bus_write_in <= '0'; - when x"032" => - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_SAMPLE_TIME1; - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; - when x"033" => - bus_write_in <= '1'; - when x"034" => - when x"035" => - when x"036" => - bus_write_in <= '0'; - when x"037" => - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(6,8)); - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ; - when x"038" => - bus_write_in <= '1'; - when x"039" => - when x"03A" => - when x"03B" => - bus_write_in <= '0'; - when x"03C" => - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_SAMPLE_TIME2; - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; - when x"03D" => - bus_write_in <= '1'; - when x"03E" => - when x"03F" => - when x"040" => - bus_write_in <= '0'; - when x"041" => - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(7,8)); - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ; - when x"042" => - bus_write_in <= '1'; - when x"043" => - when x"044" => - when x"045" => - bus_write_in <= '0'; - when x"046" => - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_SAMPLE_TIME3; - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; - when x"047" => - bus_write_in <= '1'; - when x"048" => - when x"049" => - when x"04A" => - bus_write_in <= '0'; - when x"04B" => - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= std_logic_vector(to_unsigned(9,8)); - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ; - when x"04C" => - bus_write_in <= '1'; - when x"04D" => - when x"04E" => - when x"04F" => - bus_write_in <= '0'; - phase <= x"05A"; - when x"05A" => - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= M26C_CMD_SET_JTAG_SET_DATA_TIME; - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; - when x"05B" => - bus_write_in <= '1'; - when x"05C" => - when x"05D" => - when x"05E" => - bus_write_in <= '0'; - when x"05F" => - - --- -- REMOVE sensor 2 (last sensor in chain from end) --- wait for 100 ns; --- bus_data_in(31 downto 8) <= (others => '0'); --- bus_data_in(7 downto 0) <= x"02"; -- select sensor --- bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); --- bus_addr_in(4 downto 0) <= ADDR_CONTROL_DATA_REGISTER ; --- wait for 20 ns; --- wait until CLK_IN = '1'; --- bus_write_in <= '1'; --- wait for 30 ns; --- bus_write_in <= '0'; --- --- wait for 100 ns; --- bus_data_in(31 downto 8) <= (others => '0'); --- bus_data_in(7 downto 0) <= M26C_CMD_REMOVE_SENSOR; --- bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); --- bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; --- wait for 20 ns; --- wait until CLK_IN = '1'; --- bus_write_in <= '1'; --- wait for 30 ns; --- bus_write_in <= '0'; - - when x"060" => - bus_data_in(31 downto 8) <= (others => '0'); - bus_data_in(7 downto 0) <= M26C_CMD_START; - bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); - bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; - when x"061" => - bus_write_in <= '1'; - when x"062" => - when x"063" => - when x"064" => - bus_write_in <= '0'; - when x"065" => - --- wait until jtag_tck_out = '1'; --- wait until jtag_tck_out = '0'; --- --jtag_tdo_in <= '1'; --- wait until jtag_tck_out = '1'; --- wait until jtag_tck_out = '0'; --- --jtag_tdo_in <= '0'; - when x"066" => - if not (idle_out = '1') then - if(reset_request = '1') then - taps_reset <= '1'; - end if; - phase <= phase; -- wait - end if; - when x"067" => - trigger_jtag_write <= '1'; - taps_reset <= '0'; - when x"068" => - - when x"069" => - trigger_jtag_write <= '0'; - when x"06A" => - if (idle_out = '1') then - trigger_jtag_write <= '1'; - else - phase <= phase; - end if; - when x"06B" => - if not (idle_out = '0') then - phase <= phase; -- wait - end if; - when x"06C" => - trigger_jtag_write <= '0'; - if(reset_request = '1') then - taps_reset <= '1'; - end if; - phase <= phase; -- end - when others => - phase <= x"000"; - end case; - if(RESET_IN = '1') then - broken <= '0'; - bus_addr_in(15 downto 0) <= x"0000"; - bus_data_in(31 downto 8) <= x"000000"; - bus_data_in(7 downto 0) <= M26C_CMD_NONE; - bus_write_in <= '0'; - bus_read_in <= '0'; - trigger_jtag_write <= '0'; - ramcounter <= (others => '0'); - statuscounter <= (others => '0'); - crc32_1_data_in <= x"00000000"; - crc32_1_clk_en <= '0'; - --trstb <= '1'; - taps_reset <= '1'; - crc32_reset_in <= '1'; - phase <= x"000"; - chip <= (others => '0'); - regu <= (others => '0'); - wordu <= (others => '0'); - regpointer <= (others => '0'); - - end if; - end if; -end process; - --- GET_STATUS: process --- begin --- wait for 500*8 ns; --- bus_data_in(31 downto 8) <= (others => '0'); --- bus_data_in(7 downto 0) <= M26C_CMD_COPY_TO_STATUS2; --- bus_addr_in(15 downto 5) <= ADDR_CONTROL(15 downto 5); --- bus_addr_in(4 downto 0) <= ADDR_CONTROL_CMD; --- wait for 20 ns; --- wait until CLK_IN = '1'; --- bus_write_in <= '1'; --- wait for 30 ns; --- bus_write_in <= '0'; --- --- wait for 500*8 ns; --- bus_data_in(31 downto 8) <= (others => '0'); --- bus_data_in(7 downto 0) <= (others => '0'); --- bus_addr_in(15 downto 5) <= ADDR_STATUS2(15 downto 5); --- bus_addr_in(4 downto 0) <= ADDR_STATUS2_UPDATING; --- wait for 20 ns; --- wait until CLK_IN = '1'; --- bus_write_in <= '1'; --- wait for 30 ns; --- bus_write_in <= '0'; --- --- wait for 500*8 ns; --- bus_data_in(31 downto 8) <= (others => '0'); --- bus_data_in(7 downto 0) <= (others => '0'); -- set baseaddr to 0 --- bus_addr_in(15 downto 5) <= ADDR_STATUS2(15 downto 5); --- bus_addr_in(4 downto 0) <= ADDR_STATUS2_RAM3B_BASEADDR; --- wait for 20 ns; --- wait until CLK_IN = '1'; --- bus_write_in <= '1'; --- wait for 30 ns; --- bus_write_in <= '0'; --- --- -- read status2 ram (error counters etc...) --- STATUS2LOOP: for i in 0 to 15 loop --- wait for 500*8 ns; --- bus_data_in(31 downto 8) <= (others => '0'); --- bus_data_in(7 downto 0) <= (others => '0'); --- bus_addr_in(15 downto 5) <= ADDR_STATUS2(15 downto 5); --- bus_addr_in(4 downto 0) <= std_logic_vector(unsigned(ADDR_STATUS2_RAM3B_BEGIN) + to_unsigned(i,4)); --- wait for 20 ns; --- wait until CLK_IN = '1'; --- bus_read_in <= '1'; --- wait for 30 ns; --- bus_read_in <= '0'; --- end loop; --- --- wait for 500*8 ns; --- bus_addr_in(15 downto 5) <= ADDR_STATUS(15 downto 5); --- bus_addr_in(4 downto 0) <= statuscounter; --- statuscounter <= std_logic_vector(unsigned(statuscounter)+1); --- wait for 20 ns; --- wait until CLK_IN = '1'; --- bus_read_in <= '1'; --- wait for 30 ns; --- bus_read_in <= '0'; --- wait for 500*8 ns; --- bus_addr_in(15 downto 5) <= ADDR_STATUS(15 downto 5); --- bus_addr_in(4 downto 0) <= statuscounter; --- statuscounter <= std_logic_vector(unsigned(statuscounter)+1); --- wait for 20 ns; --- wait until CLK_IN = '1'; --- bus_read_in <= '1'; --- wait for 30 ns; --- bus_read_in <= '0'; --- wait for 500*8 ns; --- bus_addr_in(15 downto 5) <= ADDR_STATUS(15 downto 5); --- bus_addr_in(4 downto 0) <= statuscounter; --- statuscounter <= std_logic_vector(unsigned(statuscounter)+1); --- wait for 20 ns; --- wait until CLK_IN = '1'; --- bus_read_in <= '1'; --- wait for 30 ns; --- bus_read_in <= '0'; --- wait for 500*8 ns; --- bus_addr_in(15 downto 5) <= ADDR_STATUS(15 downto 5); --- bus_addr_in(4 downto 0) <= statuscounter; --- statuscounter <= std_logic_vector(unsigned(statuscounter)+1); --- wait for 20 ns; --- wait until CLK_IN = '1'; --- bus_read_in <= '1'; --- wait for 30 ns; --- bus_read_in <= '0'; --- -- --- -- wait for 500*8 ns; --- -- bus_data_in(31 downto 0) <= x"80FFFF01"; --- -- bus_addr_in(3 downto 0) <= ADDR_DATA; --- -- wait for 20 ns; --- -- wait until CLK_IN = '1'; --- -- bus_write_in <= '1'; --- -- wait for 20 ns; --- -- bus_write_in <= '0'; --- -- --- -- wait for 500*8 ns; --- -- bus_data_in(31 downto 0) <= x"00000020"; --- -- bus_addr_in(3 downto 0) <= ADDR_LENGTH; --- -- wait for 20 ns; --- -- wait until CLK_IN = '1'; --- -- bus_write_in <= '1'; --- -- wait for 20 ns; --- -- bus_write_in <= '0'; --- -- --- -- wait for 500*8 ns; --- -- bus_data_in(3 downto 0) <= CMD_SHIFT_DR; --- -- bus_addr_in(3 downto 0) <= ADDR_CMD; --- -- wait for 20 ns; --- -- wait until CLK_IN = '1'; --- -- bus_write_in <= '1'; --- -- wait for 20 ns; --- -- bus_write_in <= '0'; --- -- wait until jtag_tck_out = '1'; --- -- wait until jtag_tck_out = '0'; --- -- --jtag_tdo_in <= '1'; --- -- wait until jtag_tck_out = '1'; --- -- wait until jtag_tck_out = '0'; --- -- --jtag_tdo_in <= '0'; --- -- --- -- wait for 60*8 us; --- -- wait for 500*8 ns; --- -- bus_data_in(3 downto 0) <= "0000"; --- -- bus_addr_in(3 downto 0) <= ADDR_DATA; --- -- wait for 20 ns; --- -- wait until CLK_IN = '1'; --- -- bus_write_in <= '1'; --- -- wait for 20 ns; --- -- bus_write_in <= '0'; --- -- --- -- wait for 500*8 ns; --- -- bus_data_in(3 downto 0) <= CMD_UPDATE_DR; --- -- bus_addr_in(3 downto 0) <= ADDR_CMD; --- -- wait for 20 ns; --- -- wait until CLK_IN = '1'; --- -- bus_write_in <= '1'; --- -- wait for 20 ns; --- -- bus_write_in <= '0'; --- -- --- -- wait for 30*8 us; --- -- bus_data_in(3 downto 0) <= "0000"; --- -- bus_addr_in(3 downto 0) <= ADDR_DATA; --- -- wait for 20 ns; --- -- wait until CLK_IN = '1'; --- -- bus_read_in <= '1'; --- -- wait for 20 ns; --- -- bus_read_in <= '0'; --- -- --- -- wait for 30*8 us; --- -- jtag_tdo_in <= '1'; --- -- bus_data_in(3 downto 0) <= CMD_RESET_JTAG; --- -- bus_addr_in(3 downto 0) <= ADDR_CMD; --- -- wait for 20 ns; --- -- wait until CLK_IN = '1'; --- -- bus_write_in <= '1'; --- -- wait for 20 ns; --- -- bus_write_in <= '0'; --- --- --- -- cmd_in <= CMD_NONE; --- -- wait until READY_FOR_CMD_OUT = '1'; --- -- data_in <= '1'; --- -- cmd_in <= CMD_SHIFT_DR; --- -- wait for 30 ns; --- -- cmd_in <= CMD_NONE; --- -- wait until jtag_tck_out = '1'; --- -- wait until jtag_tck_out = '0'; --- -- jtag_tdo_in <= '1'; --- -- wait until READY_FOR_CMD_OUT = '1'; --- -- data_in <= '1'; --- -- cmd_in <= CMD_SHIFT_DR; --- -- wait for 30 ns; --- -- cmd_in <= CMD_NONE; --- -- wait until jtag_tck_out = '1'; --- -- wait until jtag_tck_out = '0'; --- -- jtag_tdo_in <= '0'; --- -- wait until READY_FOR_CMD_OUT = '1'; --- -- cmd_in <= CMD_UPDATE_DR; --- -- wait for 30 ns; --- -- cmd_in <= CMD_NONE; --- -- wait until READY_FOR_CMD_OUT = '1'; --- -- wait for 30 ns; --- -- cmd_in <= CMD_NONE; --- wait; --- end process; ---testdriver_clk : process ---begin --- clk_in <= '0'; --- wait for 5 ns; --- clk_in <= '1'; --- wait for 5 ns; ---end process; - - -end architecture; diff --git a/vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2_test.vhd b/vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2_test.vhd deleted file mode 100644 index 9dc5396..0000000 --- a/vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2_test.vhd +++ /dev/null @@ -1,77 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; ---USE IEEE.std_logic_ARITH.ALL; ---USE IEEE.std_logic_UNSIGNED.ALL; -USE IEEE.numeric_std.ALL; -library work; -use work.jtag_constants.all; -use work.jtag_simulation_constants.all; - -entity jtag_cmd_m26c_test_regvaluesfrominput2_test is -end entity; - -architecture arch_sim of jtag_cmd_m26c_test_regvaluesfrominput2_test is - -component jtag_cmd_m26c_test_regvaluesfrominput2 is -generic( - numregs : integer := 11; - maxreglen : integer := 1152; - -- instruction_codes : instrArray := (0 => "10000", 1 => "10001", 2 => "10010", others => (others => '1')); -- in the given order these are the instruction codes of the registers to be programmed by the JTAG-Chain-Controller - --drlen : drlenArray := (0 => 32, 1=> 8, 2=> 1024, others => 32); -- length of the registers (same order as instruction_codes) - instruction_codes : instrArray := (0 => "01111", --BIAS_GEN - 1 => "10000", --LINE0_PATTERN_REG - 2 => "10001", --DIS_DISCRI - 3 => "10010", --SEQ_PIX_REG - 4 => "10011", --CTRL_PIX_REG - 5 => "10100", --LINE1_PATTERN_REG - 6 => "10101", --SEQ_SUZE_REG - 7 => "10110", --HEADER_TRAILER_REG - 8 => "10111", --CTRL_SUZE_REG - 9 => "11101", --RO_MODE1 - 10 => "11110", --RO_MODE0 - others => (others => '1')); - drlen : drlenArray := (0 => 152, 1=> 1152, 2=> 1152, 3=>128, 4=>40, 5=>1152, 6=>160, 7=>64, 8=>48, 9=>8, 10=>8, others => 0); - - numchips : integer := 3 -); -port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - REGISTERS_IN : in std_logic_vector(numchips*numregs*maxreglen-1 downto 0); - TRIGGER_IN : in std_logic - ); -end component; - -signal regs : std_logic_vector(3*11*1152-1 downto 0); -signal clk_in, reset_in, trigger : std_logic; -begin - regs(3*11*1152-1 downto 1152*2)<= (others => '0'); - regs(2*1152-1 downto 1152+5) <= (others => '0'); - regs(1152+4 downto 1152) <= "11101"; - regs(1152-1 downto 5) <= (others => '0'); - regs(4 downto 0) <= "11110"; - - -the_jtag_cmd_m26c_test_regvaluesfrominput2 : jtag_cmd_m26c_test_regvaluesfrominput2 port map (CLK_IN => clk_in, RESET_IN => reset_in, REGISTERS_IN => regs, TRIGGER_IN => trigger); - -testdriver_clk : process -begin - clk_in <= '0'; - wait for 5 ns; - clk_in <= '1'; - wait for 5 ns; -end process; - - -stim1 : process -begin - reset_in <= '1'; - wait for 100 ns; - reset_in <= '0'; - wait for 20 ns; - trigger <= '1'; - wait for 20 ns; - trigger <= '0'; - wait; -end process; -end architecture; diff --git a/vhdl/code/tb/jtag_simulation_constants.vhd b/vhdl/code/tb/jtag_simulation_constants.vhd deleted file mode 100644 index 6a57651..0000000 --- a/vhdl/code/tb/jtag_simulation_constants.vhd +++ /dev/null @@ -1,11 +0,0 @@ -library ieee; -USE IEEE.std_logic_1164.ALL; -use ieee.numeric_std.all; - -package jtag_simulation_constants is - -constant IRLEN : integer := 5; -- number of bits for JTAG instruction register -constant MAXNUMREGS : integer := 40; -type instrArray is array(MAXNUMREGS-1 downto 0) of std_logic_vector(IRLEN-1 downto 0); -type drlenArray is array(MAXNUMREGS-1 downto 0) of integer; -end package jtag_simulation_constants; diff --git a/vhdl/code/tb/jtag_tap_mi26_hard.vhd b/vhdl/code/tb/jtag_tap_mi26_hard.vhd deleted file mode 100644 index 5c5dd07..0000000 --- a/vhdl/code/tb/jtag_tap_mi26_hard.vhd +++ /dev/null @@ -1,504 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; ---USE IEEE.std_logic_ARITH.ALL; ---USE IEEE.std_logic_UNSIGNED.ALL; -USE IEEE.numeric_std.ALL; -library work; ---use work.trb_net_std.all; ---use work.trb_net_components.all; --- use work.trb_net16_hub_func.all; ---use work.version.all; -use work.jtag_constants.all; - -use work.jtag_simulation_constants.all; - - -entity jtag_tap_mi26_hard is -generic( - default_ir : std_logic_vector(IRLEN-1 downto 0) := "01110"; - maxreglen : integer := 1152; - dev_id : std_logic_vector := x"4d323601" -); -port( - TCK_EMU: in std_logic; - TMS_EMU: in std_logic; - TDI_EMU: in std_logic; - TDO_EMU: out std_logic; - TRSTB_EMU: in std_logic; - - REGISTERS_OUT: out std_logic_vector(12*maxreglen-1 downto 0) - ); -end entity; - - -architecture jtag_tap_mi26_hard_arch of jtag_tap_mi26_hard is -type TAP_STATE_TYPE is (TS_TEST_LOGIC_RESET, TS_RUN_TEST, TS_SELECT_DR, TS_CAPTURE_DR, TS_SHIFT_DR, TS_EXIT1_DR, TS_PAUSE_DR, TS_EXIT2_DR, TS_UPDATE_DR, TS_SELECT_IR, TS_CAPTURE_IR, TS_SHIFT_IR, TS_EXIT1_IR, TS_PAUSE_IR, TS_EXIT2_IR, TS_UPDATE_IR); - -signal tap_state : TAP_STATE_TYPE; -constant instruction_codes : instrArray := (0 => "01111", --BIAS_GEN - 1 => "10000", --LINE0_PATTERN_REG - 2 => "10001", --DIS_DISCRI - 3 => "10010", --SEQ_PIX_REG - 4 => "10011", --CTRL_PIX_REG - 5 => "10100", --LINE1_PATTERN_REG - 6 => "10101", --SEQ_SUZE_REG - 7 => "10110", --HEADER_TRAILER_REG - 8 => "10111", --CTRL_SUZE_REG - 9 => "11101", --RO_MODE1 - 10 => "11110", --RO_MODE0 - 11 => "01110", --ID_CODE - others => (others => '1')); --- drlen : drlenArray := (0 => 152, 1=> 1152, 2=> 1152, 3=>128, 4=>40, 5=>1152, 6=>160, 7=>64, 8=>48, 9=>8, 10=>8, 11=>32, others => 0); - -signal register0 : std_logic_vector(152-1 downto 0); -signal register1 : std_logic_vector(1152-1 downto 0); -signal register2 : std_logic_vector(1152-1 downto 0); -signal register3 : std_logic_vector(128-1 downto 0); -signal register4 : std_logic_vector(40-1 downto 0); -signal register5 : std_logic_vector(1152-1 downto 0); -signal register6 : std_logic_vector(160-1 downto 0); -signal register7 : std_logic_vector(64-1 downto 0); -signal register8 : std_logic_vector(48-1 downto 0); -signal register9 : std_logic_vector(8-1 downto 0); -signal register10 : std_logic_vector(8-1 downto 0); -signal register11 : std_logic_vector(32-1 downto 0); ---signal register_id_code : std_logic_vector(32-1 downto 0); - ---type REG_ARRAY is array (numregs-1 downto 0) of std_logic_vector(maxreglen-1 downto 0); ---signal registers_shift : REG_ARRAY; -signal ir_shift : std_logic_vector(IRLEN-1 downto 0); - --- -1 is the invalid selection, which means no register selected --- signal selected_dr : integer range -1 to numregs-1; --replaced for ifv. helped?? -signal selected_dr : integer range 0 to 12-1; -signal bypassreg : std_logic; ---signal tdi_sampled : std_logic; -- value of TDI_EMU sampled at rising edge of TCK_EMU - -begin - -REGISTERS_OUT(maxreglen-1 downto register0'left+1) <= (others => '0'); -REGISTERS_OUT(register0'left downto 0) <= register0; -REGISTERS_OUT(1*maxreglen+maxreglen-1 downto 1*maxreglen+register1'left+1) <= (others => '0'); -REGISTERS_OUT(1*maxreglen+register1'left downto 1*maxreglen) <= register1; -REGISTERS_OUT(2*maxreglen+maxreglen-1 downto 2*maxreglen+register2'left+1) <= (others => '0'); -REGISTERS_OUT(2*maxreglen+register2'left downto 2*maxreglen) <= register2; -REGISTERS_OUT(3*maxreglen+maxreglen-1 downto 3*maxreglen+register3'left+1) <= (others => '0'); -REGISTERS_OUT(3*maxreglen+register3'left downto 3*maxreglen) <= register3; -REGISTERS_OUT(4*maxreglen+maxreglen-1 downto 4*maxreglen+register4'left+1) <= (others => '0'); -REGISTERS_OUT(4*maxreglen+register4'left downto 4*maxreglen) <= register4; -REGISTERS_OUT(5*maxreglen+maxreglen-1 downto 5*maxreglen+register5'left+1) <= (others => '0'); -REGISTERS_OUT(5*maxreglen+register5'left downto 5*maxreglen) <= register5; -REGISTERS_OUT(6*maxreglen+maxreglen-1 downto 6*maxreglen+register6'left+1) <= (others => '0'); -REGISTERS_OUT(6*maxreglen+register6'left downto 6*maxreglen) <= register6; -REGISTERS_OUT(7*maxreglen+maxreglen-1 downto 7*maxreglen+register7'left+1) <= (others => '0'); -REGISTERS_OUT(7*maxreglen+register7'left downto 7*maxreglen) <= register7; -REGISTERS_OUT(8*maxreglen+maxreglen-1 downto 8*maxreglen+register8'left+1) <= (others => '0'); -REGISTERS_OUT(8*maxreglen+register8'left downto 8*maxreglen) <= register8; -REGISTERS_OUT(9*maxreglen+maxreglen-1 downto 9*maxreglen+register9'left+1) <= (others => '0'); -REGISTERS_OUT(9*maxreglen+register9'left downto 9*maxreglen) <= register9; -REGISTERS_OUT(10*maxreglen+maxreglen-1 downto 10*maxreglen+register10'left+1) <= (others => '0'); -REGISTERS_OUT(10*maxreglen+register10'left downto 10*maxreglen) <= register10; -REGISTERS_OUT(12*maxreglen - 1 downto 11*maxreglen) <= (others => '0'); -tap_state_transition: process(TCK_EMU, TRSTB_EMU) -begin - if(rising_edge(TCK_EMU)) then - case tap_state is - when TS_TEST_LOGIC_RESET => - if(TMS_EMU = '0') then - tap_state <= TS_RUN_TEST; - end if; - - when TS_RUN_TEST => - if(TMS_EMU = '1') then - tap_state <= TS_SELECT_DR; - end if; - - when TS_SELECT_DR => - if(TMS_EMU = '1') then - tap_state <= TS_SELECT_IR; - else - tap_state <= TS_CAPTURE_DR; - end if; - - when TS_CAPTURE_DR => - if(TMS_EMU = '1') then - tap_state <= TS_EXIT1_DR; - else - tap_state <= TS_SHIFT_DR; - end if; - - when TS_SHIFT_DR => - if(TMS_EMU = '1') then - tap_state <= TS_EXIT1_DR; - end if; - - when TS_EXIT1_DR => - if(TMS_EMU = '1') then - tap_state <= TS_UPDATE_DR; - else - tap_state <= TS_PAUSE_DR; - end if; - - when TS_PAUSE_DR => - if(TMS_EMU = '1') then - tap_state <= TS_EXIT2_DR; - end if; - - when TS_EXIT2_DR => - if(TMS_EMU = '1') then - tap_state <= TS_UPDATE_DR; - else - tap_state <= TS_SHIFT_DR; - end if; - - when TS_UPDATE_DR => - if(TMS_EMU = '1') then - tap_state <= TS_SELECT_DR; - else - tap_state <= TS_RUN_TEST; - end if; - - -- equivalent states for IR - when TS_SELECT_IR => - if(TMS_EMU = '1') then - tap_state <= TS_TEST_LOGIC_RESET; - else - tap_state <= TS_CAPTURE_IR; - end if; - - when TS_CAPTURE_IR => - if(TMS_EMU = '1') then - tap_state <= TS_EXIT1_IR; - else - tap_state <= TS_SHIFT_IR; - end if; - - when TS_SHIFT_IR => - if(TMS_EMU = '1') then - tap_state <= TS_EXIT1_IR; - end if; - - when TS_EXIT1_IR => - if(TMS_EMU = '1') then - tap_state <= TS_UPDATE_IR; - else - tap_state <= TS_PAUSE_IR; - end if; - - when TS_PAUSE_IR => - if(TMS_EMU = '1') then - tap_state <= TS_EXIT2_IR; - end if; - - when TS_EXIT2_IR => - if(TMS_EMU = '1') then - tap_state <= TS_UPDATE_IR; - else - tap_state <= TS_SHIFT_IR; - end if; - - when TS_UPDATE_IR => - if(TMS_EMU = '1') then - tap_state <= TS_SELECT_DR; - else - tap_state <= TS_RUN_TEST; - end if; - - end case; - end if; - - if(TRSTB_EMU = '1') then - tap_state <= TS_TEST_LOGIC_RESET; - end if; - - -end process; - -tap_registers: process (TCK_EMU, TRSTB_EMU) -variable i: integer; -begin - -- update registers - if(rising_edge(TCK_EMU)) then - case tap_state is - when TS_TEST_LOGIC_RESET => - --selected_dr <= -1; --replaced for ifv. helped?? - selected_dr <= 0; - for i in 12-1 downto 0 loop - if instruction_codes(i) = default_ir then - selected_dr <= i; - end if; - end loop; - ir_shift <= default_ir; - - when TS_RUN_TEST => - - when TS_SELECT_DR => - if(selected_dr = 11) then --ID_CODE - register11(31 downto 0) <= dev_id; - end if; - when TS_CAPTURE_DR => - -- in first version: DONt copy register value to shift register --- if(selected_dr>=0) then --- registers_shift(selected_dr) <= registers((selected_dr+1)*maxreglen-1 downto selected_dr*maxreglen); --- end if; - - - - when TS_SHIFT_DR => - case selected_dr is - when 0 => - register0(register0'left-1 downto 0) <= register0(register0'left downto 1); - register0(register0'left) <= TDI_EMU; - when 1 => - register1(register1'left-1 downto 0) <= register1(register1'left downto 1); - register1(register1'left) <= TDI_EMU; - when 2 => - register2(register2'left-1 downto 0) <= register2(register2'left downto 1); - register2(register2'left) <= TDI_EMU; - when 3 => - register3(register3'left-1 downto 0) <= register3(register3'left downto 1); - register3(register3'left) <= TDI_EMU; - when 4 => - register4(register4'left-1 downto 0) <= register4(register4'left downto 1); - register4(register4'left) <= TDI_EMU; - when 5 => - register5(register5'left-1 downto 0) <= register5(register5'left downto 1); - register5(register5'left) <= TDI_EMU; - when 6 => - register6(register6'left-1 downto 0) <= register6(register6'left downto 1); - register6(register6'left) <= TDI_EMU; - when 7 => - register7(register7'left-1 downto 0) <= register7(register7'left downto 1); - register7(register7'left) <= TDI_EMU; - when 8 => - register8(register8'left-1 downto 0) <= register8(register8'left downto 1); - register8(register8'left) <= TDI_EMU; - when 9 => - register9(register9'left-1 downto 0) <= register9(register9'left downto 1); - register9(register9'left) <= TDI_EMU; - when 10 => - register10(register10'left-1 downto 0) <= register10(register10'left downto 1); - register10(register10'left) <= TDI_EMU; - when 11 => -- ID_CODE - -- emulate shift register - register11(register11'left-1 downto 0) <= register11(register11'left downto 1); - register11(register11'left) <= TDI_EMU; - when others => - bypassreg <= TDI_EMU; - end case; - --- 1 => "10000", --LINE0_PATTERN_REG --- 2 => "10001", --DIS_DISCRI --- 3 => "10010", --SEQ_PIX_REG --- 4 => "10011", --CTRL_PIX_REG --- 5 => "10100", --LINE1_PATTERN_REG --- 6 => "10101", --SEQ_SUZE_REG --- 7 => "10110", --HEADER_TRAILER_REG --- 8 => "10111", --CTRL_SUZE_REG --- 9 => "11101", --RO_MODE1 --- 10 => "11110", --RO_MODE0 --- others => (others => '1')); --- --- --registers_shift(selected_dr)(drlen(selected_dr)-2 downto 0) <= registers_shift(selected_dr)(drlen(selected_dr)-1 downto 1); -- shift register with size of DR, LSB first --- --registers_shift(selected_dr)(maxreglen-2 downto 0) <= registers_shift(selected_dr)(maxreglen-1 downto 1); -- replaced by this const expr for ifv-- shift register with size of DR, LSB first --- --registers_shift(selected_dr)(drlen(selected_dr)-1) <= TDI_EMU; -- use sampled TDI input, store in shift register --- for i in 0 to maxreglen-2 loop --- if(i - - when TS_PAUSE_DR => - - when TS_EXIT2_DR => - - when TS_UPDATE_DR => - -- for mi26 hard first implementation DONt do the following --- if(selected_dr>=0) then --- -- store shift register value to register number selected_dr --- registers((selected_dr+1)*maxreglen-1 downto selected_dr*maxreglen) <= registers_shift(selected_dr); --- end if; - - -- equivalent states for IR - when TS_SELECT_IR => - - when TS_CAPTURE_IR => - - - when TS_SHIFT_IR => - ir_shift(irlen-2 downto 0) <= ir_shift(irlen-1 downto 1); - --ir_shift(irlen-1) <= tdi_sampled; -- LSB first - ir_shift(irlen-1) <= TDI_EMU; -- LSB first - - - when TS_EXIT1_IR => - - when TS_PAUSE_IR => - - when TS_EXIT2_IR => - - when TS_UPDATE_IR => - for i in 12-1 downto 0 loop - if instruction_codes(i) = ir_shift then - selected_dr <= i; - end if; - end loop; - end case; - end if; - if(TRSTB_EMU = '1') then - register0 <= (others => '0'); - register1 <= (others => '0'); - register2 <= (others => '0'); - register3 <= (others => '0'); - register4 <= (others => '0'); - register5 <= (others => '0'); - register6 <= (others => '0'); - register7 <= (others => '0'); - register8 <= (others => '0'); - register9 <= (others => '0'); - register10 <= (others => '0'); - end if; -end process; - -tap_output: process (TCK_EMU, TRSTB_EMU) -variable i: integer; -begin --- output on falling edge - if(falling_edge(TCK_EMU)) then - case tap_state is - when TS_CAPTURE_DR => - -- copy register value to shift register - -- case selected_dr is --- when 0 => --- TDO_EMU <= register0(0); --- when 1 => --- TDO_EMU <= register1(0); --- when 2 => --- TDO_EMU <= register2(0); --- when 3 => --- TDO_EMU <= register3(0); --- when 4 => --- TDO_EMU <= register4(0); --- when 5 => --- TDO_EMU <= register5(0); --- when 6 => --- TDO_EMU <= register6(0); --- when 7 => --- TDO_EMU <= register7(0); --- when 8 => --- TDO_EMU <= register8(0); --- when 9 => --- TDO_EMU <= register9(0); --- when 10 => --- TDO_EMU <= register10(0); --- when 11 => --- TDO_EMU <= register11(0); --- when others => --- TDO_EMU <= bypassreg; --- end case; - when TS_SHIFT_DR => - case selected_dr is - when 0 => - TDO_EMU <= register0(0); - when 1 => - TDO_EMU <= register1(0); - when 2 => - TDO_EMU <= register2(0); - when 3 => - TDO_EMU <= register3(0); - when 4 => - TDO_EMU <= register4(0); - when 5 => - TDO_EMU <= register5(0); - when 6 => - TDO_EMU <= register6(0); - when 7 => - TDO_EMU <= register7(0); - when 8 => - TDO_EMU <= register8(0); - when 9 => - TDO_EMU <= register9(0); - when 10 => - TDO_EMU <= register10(0); - when 11 => - TDO_EMU <= register11(0); - when others => - TDO_EMU <= bypassreg; - end case; - when TS_EXIT1_DR => - -- the same: update output because in last shift operation register has been shifted - case selected_dr is - when 0 => - TDO_EMU <= register0(0); - when 1 => - TDO_EMU <= register1(0); - when 2 => - TDO_EMU <= register2(0); - when 3 => - TDO_EMU <= register3(0); - when 4 => - TDO_EMU <= register4(0); - when 5 => - TDO_EMU <= register5(0); - when 6 => - TDO_EMU <= register6(0); - when 7 => - TDO_EMU <= register7(0); - when 8 => - TDO_EMU <= register8(0); - when 9 => - TDO_EMU <= register9(0); - when 10 => - TDO_EMU <= register10(0); - when 11 => - TDO_EMU <= register11(0); - when others => - TDO_EMU <= bypassreg; - end case; - when TS_UPDATE_DR => - -- added as test for errors - TDO_EMU <= '1'; - when TS_CAPTURE_IR => - TDO_EMU <= ir_shift(0); - when TS_SHIFT_IR => - TDO_EMU <= ir_shift(0); - when TS_EXIT1_IR => - -- the same: update output because in last shift operation register has been shifted - TDO_EMU <= ir_shift(0); - when others => - end case; - end if; - if(TRSTB_EMU = '1') then - TDO_EMU <= '0'; - end if; -end process; - --- tap_sample_input: process (TCK_EMU, TRSTB_EMU) --- --- begin --- if(rising_edge(TCK_EMU)) then --- tdi_sampled <= TDI_EMU; --- --- end if; --- if(TRSTB_EMU = '1') then --- tdi_sampled <= '0'; --- end if; --- --- end process; - - -end architecture; diff --git a/vhdl/code/tb/jtag_write_m10_test.vhd b/vhdl/code/tb/jtag_write_m10_test.vhd deleted file mode 100644 index 26cbe14..0000000 --- a/vhdl/code/tb/jtag_write_m10_test.vhd +++ /dev/null @@ -1,363 +0,0 @@ -LIBRARY ieee; -use ieee.std_logic_1164.all; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; ---USE IEEE.numeric_std.ALL; - -library work; ---use work.trb_net_std.all; ---use work.trb_net_components.all; --- use work.trb_net16_hub_func.all; ---use work.version.all; -use work.jtag_constants.all; - -entity jtag_write_m10_test is -end entity; - -architecture jtag_write_m10_test_arch of jtag_write_m10_test is -component jtag_write_m10 is - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - RAM_JTAG_REGISTERS_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); - RAM_JTAG_REGISTERS_D_IN : in std_logic_vector(31 downto 0); - - --RAM_JTAG_REGISTERS_READ_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_READ_DEPTH-1 downto 0); - --RAM_JTAG_REGISTERS_READ_D_OUT : out std_logic_vector(31 downto 0); - -- number of next chip which is not removed from the jtag chain. for chip i ( in range 0...N) this next chip is - -- encoded by the bits NEXT_NOT_REMOVED(i*MAX_NUMCHIPS_LD + MAX_NUMCHIPS_LD-1 downto i*MAX_NUMCHIPS_LD) - -- which should be interpreted as unsigned - NEXT_NOT_REMOVED_IN : in std_logic_vector(MAX_NUMCHIPS_LD*MAX_NUMCHIPS-1 downto 0); - - BEGIN_JTAGBITCALC_IN : in std_logic; - TRIGGER_BEGIN_WRITE_IN : in std_logic; - - ENABLE_COMPARE_OUT : out std_logic; - FINISH_COMPARE_OUT : out std_logic; - CHIP_COUNTER_OUT : out std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0); - REG_COUNTER_OUT : out std_logic_vector(MAX_REGISTERS_LD-1 downto 0); - ENABLE_JTAG_CLOCK_OUT : out std_logic; - TMS_OUT : out std_logic; - TDI_OUT : out std_logic; - - LAST_ERROR_CODE_OUT : out std_logic_vector(2 downto 0) - - - ); -end component; - - -component CRC_32 is - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(31 downto 0); - CRC_OUT : out std_logic_vector(31 downto 0); - CRC_match : out std_logic - ); -end component; -component ram_dp is - generic( - depth : integer := RAM_JTAG_REGISTERS_DEPTH; - width : integer := 32 - ); - port( - CLK : in std_logic; - wr1 : in std_logic; - a1 : in std_logic_vector(depth-1 downto 0); - dout1 : out std_logic_vector(width-1 downto 0); - din1 : in std_logic_vector(width-1 downto 0); - a2 : in std_logic_vector(depth-1 downto 0); - dout2 : out std_logic_vector(width-1 downto 0) - ); -end component; - -signal chip : std_logic_vector(3 downto 0); -signal CLK, RESET : std_logic; -signal ram_read_addr, ram_write_addr : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); -signal ram_read_data, ram_write_datain, ram_write_dataout : std_logic_vector(31 downto 0); -signal ram_write_wr : std_logic; -signal ramcounter : std_logic_vector(7 downto 0); -signal next_not_removed : std_logic_vector(MAX_NUMCHIPS_LD*MAX_NUMCHIPS-1 downto 0); -signal begin_jtagbitcalc, trigger_begin_write: std_logic; -begin - -the_jtag_write_m10 : jtag_write_m10 port map (CLK_IN => CLK, RESET_IN => RESET,RAM_JTAG_REGISTERS_A_OUT=> ram_read_addr, RAM_JTAG_REGISTERS_D_IN => ram_read_data, NEXT_NOT_REMOVED_IN => next_not_removed, BEGIN_JTAGBITCALC_IN => begin_jtagbitcalc, TRIGGER_BEGIN_WRITE_IN => trigger_begin_write, ENABLE_COMPARE_OUT => open, FINISH_COMPARE_OUT => open, CHIP_COUNTER_OUT => open, REG_COUNTER_OUT => open, ENABLE_JTAG_CLOCK_OUT => open, TMS_OUT => open, TDI_OUT => open, LAST_ERROR_CODE_OUT => open); - -the_ram : ram_dp generic map( - depth => RAM_JTAG_REGISTERS_DEPTH, - width => 32 - ) - port map ( CLK=> CLK, wr1=>ram_write_wr, a1 =>ram_write_addr, dout1=>ram_write_dataout, din1=>ram_write_datain, a2=>ram_read_addr, dout2=>ram_read_data); - -test_process : process -begin - trigger_begin_write <= '0'; - begin_jtagbitcalc <= '0'; - ram_write_wr <= '0'; - chip <= (others =>'0'); - ramcounter <= (others =>'0'); - next_not_removed <= (others =>'0'); - - - RESET <= '1'; - wait for 40 ns; - RESET <= '0'; - wait for 20 ns; - - ramcounter <= ramcounter + 1; - - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"00050002"; -- numregs, IRLen - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"00000000"; -- reserved - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"0000000a"; -- Ptr1 - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"00000029"; -- Length1 = 41 bit - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"0000000c"; -- Ptr2 - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"00000040"; -- Length1 = 64 bit - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"00000029"; -- CRC-32 - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"0000001E"; -- IR1 - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"0000000E"; -- IR2 - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"0000001F"; -- IR3 (BYPASS) - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"0F0F0F0F"; -- DR1 - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"0F0F0F0F"; -- DR1 - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"11111111"; -- DR2 - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"11111111"; -- DR2 - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"0000000E"; -- CRC-32 - ram_write_wr <= '1'; - wait for 20 ns; - - - - - - - - - - ramcounter <= (others => '0'); - ram_write_wr <= '0'; - chip <= "0001"; - - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"00050001"; -- numregs, IRLen - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"00000000"; -- reserved - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"0000000a"; -- Ptr1 - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"00000029"; -- Length1 = 41 bit - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"0000000c"; -- Ptr2 - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"00000040"; -- Length1 = 64 bit - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"00000029"; -- CRC-32 - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"0000001E"; -- IR1 - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"0000000E"; -- IR2 - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"0000001F"; -- IR3 (BYPASS) - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"AAAAAAAA"; -- DR1 - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"AAAAAAAA"; -- DR1 - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"00FF00FF"; -- DR2 - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"00FF00FF"; -- DR2 - ram_write_wr <= '1'; - wait for 20 ns; - ramcounter <= ramcounter + 1; - - ram_write_addr(11 downto 8) <= chip; - ram_write_addr(7 downto 0) <= ramcounter; - ram_write_datain <= x"0000000E"; -- CRC-32 - ram_write_wr <= '1'; - wait for 20 ns; - ram_write_wr <= '0'; - - - next_not_removed(MAX_NUMCHIPS_LD-1 downto 0) <= "0001"; - next_not_removed(MAX_NUMCHIPS_LD+MAX_NUMCHIPS_LD-1 downto MAX_NUMCHIPS_LD) <= "0000"; - - - trigger_begin_write <= '1'; - wait for 20 ns; - while(true) loop - begin_jtagbitcalc <= '1'; - wait for 20 ns; - begin_jtagbitcalc <= '0'; - wait for 200 ns; - end loop; - - - -end process; - -testdriver_clk : process -begin - CLK <= '0'; - wait for 10 ns; - CLK <= '1'; - wait for 10 ns; -end process; -end architecture; \ No newline at end of file diff --git a/vhdl/compile_mvdjtag_frankfurt.pl b/vhdl/compile_mvdjtag_frankfurt.pl deleted file mode 100755 index 969528b..0000000 --- a/vhdl/compile_mvdjtag_frankfurt.pl +++ /dev/null @@ -1,158 +0,0 @@ -#!/usr/bin/perl -use Data::Dumper; -use warnings; -use strict; - - - - -################################################################################### -#Settings for this project -my $TOPNAME = "trb3_periph_mvdjtag"; #Name of top-level entity -my $lattice_path = '/d/jspc29/lattice/diamond/2.2_x64'; -my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/'; -my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; -#my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; -my $lm_license_file_for_par = "1710\@cronos.e12.physik.tu-muenchen.de"; -################################################################################### - -$ENV{'PAR_DESIGN_NAME'}=$TOPNAME; - - - - - - -use FileHandle; - -$ENV{'SYNPLIFY'}=$synplify_path; -$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; -$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; - - - - -my $FAMILYNAME="LatticeECP3"; -my $DEVICENAME="LFE3-150EA"; -my $PACKAGE="FPBGA672"; -my $SPEEDGRADE="8"; - - -#create full lpf file -system("cp ../../trb3/base/$TOPNAME.lpf workdir/$TOPNAME.lpf"); -system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); - - -#set -e -#set -o errexit - -#generate timestamp -my $t=time; -my $fh = new FileHandle(">version.vhd"); -die "could not open file" if (! defined $fh); -print $fh <close; - -system("env| grep LM_"); -my $r = ""; - -my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; -$r=execute($c, "do_not_exit" ); - - -chdir "workdir"; -$fh = new FileHandle("<$TOPNAME".".srr"); -my @a = <$fh>; -$fh -> close; - - - -foreach (@a) -{ - if(/\@E:/) - { - print "\n"; - $c="cat $TOPNAME.srr | grep \"\@E\""; - system($c); - print "\n\n"; - exit 129; - } -} - - -$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; - - -$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; -execute($c); - -my $tpmap = $TOPNAME . "_map" ; - -$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; -execute($c); - -system("rm $TOPNAME.ncd"); - -$c=qq|mpartrce -p "../$TOPNAME.p2t" -f "../$TOPNAME.p3t" -tf "$TOPNAME.pt" "|.$TOPNAME.qq|_map.ncd" "$TOPNAME.ncd"|; -#$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; -#$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -# IOR IO Timing Report -# $c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; -# execute($c); - -# TWR Timing Report -$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|; -# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -chdir ".."; - -exit; - -sub execute { - my ($c, $op) = @_; - #print "option: $op \n"; - $op = "" if(!$op); - print "\n\ncommand to execute: $c \n"; - $r=system($c); - if($r) { - print "$!"; - if($op ne "do_not_exit") { - exit; - } - } - - return $r; - -} diff --git a/vhdl/sim/sim_jtag_cmd_m26c.prj.mpf b/vhdl/sim/sim_jtag_cmd_m26c.prj.mpf deleted file mode 100644 index c2547d0..0000000 --- a/vhdl/sim/sim_jtag_cmd_m26c.prj.mpf +++ /dev/null @@ -1,1754 +0,0 @@ -; Copyright 1991-2011 Mentor Graphics Corporation -; -; All Rights Reserved. -; -; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF -; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. -; - -[Library] -std = $MODEL_TECH/../std -ieee = $MODEL_TECH/../ieee -vital2000 = $MODEL_TECH/../vital2000 -; -; VITAL concerns: -; -; The library ieee contains (among other packages) the packages of the -; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use -; the physical library ieee (recommended), or use the physical library -; vital2000, but not both. The design can use logical library ieee and/or -; vital2000 as long as each of these maps to the same physical library, either -; ieee or vital2000. -; -; A design using the 1995 version of the VITAL packages, whether or not -; it also uses the 2000 version of the VITAL packages, must have logical library -; name ieee mapped to physical library vital1995. (A design cannot use library -; vital1995 directly because some packages in this library use logical name ieee -; when referring to the other packages in the library.) The design source -; should use logical name ieee when referring to any packages there except the -; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical -; name vital2000 (mapped to physical library vital2000) to refer to those -; packages. -; ieee = $MODEL_TECH/../vital1995 -; -; For compatiblity with previous releases, logical library name vital2000 maps -; to library vital2000 (a different library than library ieee, containing the -; same packages). -; A design should not reference VITAL from both the ieee library and the -; vital2000 library because the vital packages are effectively different. -; A design that references both the ieee and vital2000 libraries must have -; both logical names ieee and vital2000 mapped to the same library, either of -; these: -; $MODEL_TECH/../ieee -; $MODEL_TECH/../vital2000 -; -verilog = $MODEL_TECH/../verilog -std_developerskit = $MODEL_TECH/../std_developerskit -synopsys = $MODEL_TECH/../synopsys -modelsim_lib = $MODEL_TECH/../modelsim_lib -sv_std = $MODEL_TECH/../sv_std -mtiAvm = $MODEL_TECH/../avm -mtiOvm = $MODEL_TECH/../ovm-2.1.2 -mtiUvm = $MODEL_TECH/../uvm-1.1 -mtiUPF = $MODEL_TECH/../upf_lib -mtiPA = $MODEL_TECH/../pa_lib -floatfixlib = $MODEL_TECH/../floatfixlib -mc2_lib = $MODEL_TECH/../mc2_lib -;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release -;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release -;mvc_lib = $MODEL_TECH/../mvc_lib - -work = work -[vcom] -; VHDL93 variable selects language version as the default. -; Default is VHDL-2002. -; Value of 0 or 1987 for VHDL-1987. -; Value of 1 or 1993 for VHDL-1993. -; Default or value of 2 or 2002 for VHDL-2002. -; Value of 3 or 2008 for VHDL-2008 -VHDL93 = 2002 - -; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. -; ignoreStandardRealVector = 1 - -; Show source line containing error. Default is off. -; Show_source = 1 - -; Turn off unbound-component warnings. Default is on. -; Show_Warning1 = 0 - -; Turn off process-without-a-wait-statement warnings. Default is on. -; Show_Warning2 = 0 - -; Turn off null-range warnings. Default is on. -; Show_Warning3 = 0 - -; Turn off no-space-in-time-literal warnings. Default is on. -; Show_Warning4 = 0 - -; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. -; Show_Warning5 = 0 - -; Turn off optimization for IEEE std_logic_1164 package. Default is on. -; Optimize_1164 = 0 - -; Turn on resolving of ambiguous function overloading in favor of the -; "explicit" function declaration (not the one automatically created by -; the compiler for each type declaration). Default is off. -; The .ini file has Explicit enabled so that std_logic_signed/unsigned -; will match the behavior of synthesis tools. -Explicit = 1 - -; Turn off acceleration of the VITAL packages. Default is to accelerate. -; NoVital = 1 - -; Turn off VITAL compliance checking. Default is checking on. -; NoVitalCheck = 1 - -; Ignore VITAL compliance checking errors. Default is to not ignore. -; IgnoreVitalErrors = 1 - -; Turn off VITAL compliance checking warnings. Default is to show warnings. -; Show_VitalChecksWarnings = 0 - -; Turn off PSL assertion warning messages. Default is to show warnings. -; Show_PslChecksWarnings = 0 - -; Enable parsing of embedded PSL assertions. Default is enabled. -; EmbeddedPsl = 0 - -; Keep silent about case statement static warnings. -; Default is to give a warning. -; NoCaseStaticError = 1 - -; Keep silent about warnings caused by aggregates that are not locally static. -; Default is to give a warning. -; NoOthersStaticError = 1 - -; Treat as errors: -; case statement static warnings -; warnings caused by aggregates that are not locally static -; Overrides NoCaseStaticError, NoOthersStaticError settings. -; PedanticErrors = 1 - -; Turn off inclusion of debugging info within design units. -; Default is to include debugging info. -; NoDebug = 1 - -; Turn off "Loading..." messages. Default is messages on. -; Quiet = 1 - -; Turn on some limited synthesis rule compliance checking. Checks only: -; -- signals used (read) by a process must be in the sensitivity list -; CheckSynthesis = 1 - -; Activate optimizations on expressions that do not involve signals, -; waits, or function/procedure/task invocations. Default is off. -; ScalarOpts = 1 - -; Turns on lint-style checking. -; Show_Lint = 1 - -; Require the user to specify a configuration for all bindings, -; and do not generate a compile time default binding for the -; component. This will result in an elaboration error of -; 'component not bound' if the user fails to do so. Avoids the rare -; issue of a false dependency upon the unused default binding. -; RequireConfigForAllDefaultBinding = 1 - -; Perform default binding at compile time. -; Default is to do default binding at load time. -; BindAtCompile = 1; - -; Inhibit range checking on subscripts of arrays. Range checking on -; scalars defined with subtypes is inhibited by default. -; NoIndexCheck = 1 - -; Inhibit range checks on all (implicit and explicit) assignments to -; scalar objects defined with subtypes. -; NoRangeCheck = 1 - -; Run the 0-in compiler on the VHDL source files -; Default is off. -; ZeroIn = 1 - -; Set the options to be passed to the 0-in compiler. -; Default is "". -; ZeroInOptions = "" - -; Set the synthesis prefix to be honored for synthesis pragma recognition. -; Default is "". -; SynthPrefix = "" - -; Turn on code coverage in VHDL design units. Default is off. -; Coverage = sbceft - -; Turn off code coverage in VHDL subprograms. Default is on. -; CoverageSub = 0 - -; Automatically exclude VHDL case statement OTHERS choice branches. -; This includes OTHERS choices in selected signal assigment statements. -; Default is to not exclude. -; CoverExcludeDefault = 1 - -; Control compiler and VOPT optimizations that are allowed when -; code coverage is on. Refer to the comment for this in the [vlog] area. -; CoverOpt = 3 - -; Turn on or off clkOpt optimization for code coverage. Default is on. -; CoverClkOpt = 1 - -; Turn on or off clkOpt optimization builtins for code coverage. Default is on. -; CoverClkOptBuiltins = 0 - -; Inform code coverage optimizations to respect VHDL 'H' and 'L' -; values on signals in conditions and expressions, and to not automatically -; convert them to '1' and '0'. Default is to not convert. -; CoverRespectHandL = 0 - -; Increase or decrease the maximum number of rows allowed in a UDP table -; implementing a VHDL condition coverage or expression coverage expression. -; More rows leads to a longer compile time, but more expressions covered. -; CoverMaxUDPRows = 192 - -; Increase or decrease the maximum number of input patterns that are present -; in FEC table. This leads to a longer compile time with more expressions -; covered with FEC metric. -; CoverMaxFECRows = 192 - -; Enable or disable Focused Expression Coverage analysis for conditions and -; expressions. Focused Expression Coverage data is provided by default when -; expression and/or condition coverage is active. -; CoverFEC = 0 - -; Enable or disable UDP Coverage analysis for conditions and expressions. -; UDP Coverage data is provided by default when expression and/or condition -; coverage is active. -; CoverUDP = 0 - -; Enable or disable short circuit evaluation of conditions and expressions when -; condition or expression coverage is active. Short circuit evaluation is enabled -; by default. -; CoverShortCircuit = 0 - -; Enable code coverage reporting of code that has been optimized away. -; The default is not to report. -; CoverReportCancelled = 1 - -; Use this directory for compiler temporary files instead of "work/_temp" -; CompilerTempDir = /tmp - -; Set this to cause the compilers to force data to be committed to disk -; when the files are closed. -; SyncCompilerFiles = 1 - -; Add VHDL-AMS declarations to package STANDARD -; Default is not to add -; AmsStandard = 1 - -; Range and length checking will be performed on array indices and discrete -; ranges, and when violations are found within subprograms, errors will be -; reported. Default is to issue warnings for violations, because subprograms -; may not be invoked. -; NoDeferSubpgmCheck = 0 - -; Turn ON detection of FSMs having single bit current state variable. -; FsmSingle = 1 - -; Turn off reset state transitions in FSM. -; FsmResetTrans = 0 - -; Turn ON detection of FSM Implicit Transitions. -; FsmImplicitTrans = 1 - -; Controls whether or not to show immediate assertions with constant expressions -; in GUI/report/UCDB etc. By default, immediate assertions with constant -; expressions are shown in GUI/report/UCDB etc. This does not affect -; evaluation of immediate assertions. -; ShowConstantImmediateAsserts = 0 - -; Controls how VHDL basic identifiers are stored with the design unit. -; Does not make the language case-sensitive, effects only how declarations -; declared with basic identifiers have their names stored and printed -; (examine, etc.). -; Default is to preserve the case as originally depicted in the VHDL source. -; Value of 0 indicates to change basic identifiers to lower case. -; PreserveCase = 0 - -; For Configuration Declarations, controls the effect that USE clauses have -; on visibility inside the configuration items being configured. If 1 -; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance -; extend the visibility of objects made visible through USE clauses into nested -; component configurations. -; OldVHDLConfigurationVisibility = 0 - -; Allows VHDL configuration declarations to be in a different library from -; the corresponding configured entity. Default is to not allow this for -; stricter LRM-compliance -; SeparateConfigLibrary = 1; - -; Change how subprogram out parameter of type array and record are treated. -; If 1, always initial the out parameter to its default value. -; If 2, do not initialize the out parameter. -; The value 0 indicates use the default for the langauge version being compiled. -; Prior to 10.1 all langauge version did not initialize out composite parameters. -; 10.1 and later files compile with -2008 initialize by default -; InitOutCompositeParam = 0 - -[vlog] -; Turn off inclusion of debugging info within design units. -; Default is to include debugging info. -; NoDebug = 1 - -; Turn on `protect compiler directive processing. -; Default is to ignore `protect directives. -; Protect = 1 - -; Turn off "Loading..." messages. Default is messages on. -; Quiet = 1 - -; Turn on Verilog hazard checking (order-dependent accessing of global vars). -; Default is off. -; Hazard = 1 - -; Turn on converting regular Verilog identifiers to uppercase. Allows case -; insensitivity for module names. Default is no conversion. -; UpCase = 1 - -; Activate optimizations on expressions that do not involve signals, -; waits, or function/procedure/task invocations. Default is off. -; ScalarOpts = 1 - -; Turns on lint-style checking. -; Show_Lint = 1 - -; Show source line containing error. Default is off. -; Show_source = 1 - -; Turn on bad option warning. Default is off. -; Show_BadOptionWarning = 1 - -; Revert back to IEEE 1364-1995 syntax, default is 0 (off). -; vlog95compat = 1 - -; Turn off PSL warning messages. Default is to show warnings. -; Show_PslChecksWarnings = 0 - -; Enable parsing of embedded PSL assertions. Default is enabled. -; EmbeddedPsl = 0 - -; Set the threshold for automatically identifying sparse Verilog memories. -; A memory with depth equal to or more than the sparse memory threshold gets -; marked as sparse automatically, unless specified otherwise in source code -; or by +nosparse commandline option of vlog or vopt. -; The default is 1M. (i.e. memories with depth equal -; to or greater than 1M are marked as sparse) -; SparseMemThreshold = 1048576 - -; Run the 0-in compiler on the Verilog source files -; Default is off. -; ZeroIn = 1 - -; Set the options to be passed to the 0-in compiler. -; Default is "". -; ZeroInOptions = "" - -; Set the synthesis prefix to be honored for synthesis pragma recognition. -; Default is "". -; SynthPrefix = "" - -; Set the option to treat all files specified in a vlog invocation as a -; single compilation unit. The default value is set to 0 which will treat -; each file as a separate compilation unit as specified in the P1800 draft standard. -; MultiFileCompilationUnit = 1 - -; Turn on code coverage in Verilog design units. Default is off. -; Coverage = sbceft - -; Automatically exclude Verilog case statement default branches. -; Default is to not automatically exclude defaults. -; CoverExcludeDefault = 1 - -; Increase or decrease the maximum number of rows allowed in a UDP table -; implementing a Verilog condition coverage or expression coverage expression. -; More rows leads to a longer compile time, but more expressions covered. -; CoverMaxUDPRows = 192 - -; Increase or decrease the maximum number of input patterns that are present -; in FEC table. This leads to a longer compile time with more expressions -; covered with FEC metric. -; CoverMaxFECRows = 192 - -; Enable or disable Focused Expression Coverage analysis for conditions and -; expressions. Focused Expression Coverage data is provided by default when -; expression and/or condition coverage is active. -; CoverFEC = 0 - -; Enable or disable UDP Coverage analysis for conditions and expressions. -; UDP Coverage data is provided by default when expression and/or condition -; coverage is active. -; CoverUDP = 0 - -; Enable or disable short circuit evaluation of conditions and expressions when -; condition or expression coverage is active. Short circuit evaluation is enabled -; by default. -; CoverShortCircuit = 0 - - -; Turn on code coverage in VLOG `celldefine modules and modules included -; using vlog -v and -y. Default is off. -; CoverCells = 1 - -; Enable code coverage reporting of code that has been optimized away. -; The default is not to report. -; CoverReportCancelled = 1 - -; Control compiler and VOPT optimizations that are allowed when -; code coverage is on. This is a number from 1 to 4, with the following -; meanings (the default is 3): -; 1 -- Turn off all optimizations that affect coverage reports. -; 2 -- Allow optimizations that allow large performance improvements -; by invoking sequential processes only when the data changes. -; This may make major reductions in coverage counts. -; 3 -- In addition, allow optimizations that may change expressions or -; remove some statements. Allow constant propagation. Allow VHDL -; subprogram inlining and VHDL FF recognition. -; 4 -- In addition, allow optimizations that may remove major regions of -; code by changing assignments to built-ins or removing unused -; signals. Change Verilog gates to continuous assignments. -; CoverOpt = 3 - -; Specify the override for the default value of "cross_num_print_missing" -; option for the Cross in Covergroups. If not specified then LRM default -; value of 0 (zero) is used. This is a compile time option. -; SVCrossNumPrintMissingDefault = 0 - -; Setting following to 1 would cause creation of variables which -; would represent the value of Coverpoint expressions. This is used -; in conjunction with "SVCoverpointExprVariablePrefix" option -; in the modelsim.ini -; EnableSVCoverpointExprVariable = 0 - -; Specify the override for the prefix used in forming the variable names -; which represent the Coverpoint expressions. This is used in conjunction with -; "EnableSVCoverpointExprVariable" option of the modelsim.ini -; The default prefix is "expr". -; The variable name is -; variable name => _ -; SVCoverpointExprVariablePrefix = expr - -; Override for the default value of the SystemVerilog covergroup, -; coverpoint, and cross option.goal (defined to be 100 in the LRM). -; NOTE: It does not override specific assignments in SystemVerilog -; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" -; in the [vsim] section can override this value. -; SVCovergroupGoalDefault = 100 - -; Override for the default value of the SystemVerilog covergroup, -; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) -; NOTE: It does not override specific assignments in SystemVerilog -; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" -; in the [vsim] section can override this value. -; SVCovergroupTypeGoalDefault = 100 - -; Specify the override for the default value of "strobe" option for the -; Covergroup Type. This is a compile time option which forces "strobe" to -; a user specified default value and supersedes SystemVerilog specified -; default value of '0'(zero). NOTE: This can be overriden by a runtime -; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. -; SVCovergroupStrobeDefault = 0 - -; Specify the override for the default value of "merge_instances" option for -; the Covergroup Type. This is a compile time option which forces -; "merge_instances" to a user specified default value and supersedes -; SystemVerilog specified default value of '0'(zero). -; SVCovergroupMergeInstancesDefault = 0 - -; Specify the override for the default value of "per_instance" option for the -; Covergroup variables. This is a compile time option which forces "per_instance" -; to a user specified default value and supersedes SystemVerilog specified -; default value of '0'(zero). -; SVCovergroupPerInstanceDefault = 0 - -; Specify the override for the default value of "get_inst_coverage" option for the -; Covergroup variables. This is a compile time option which forces -; "get_inst_coverage" to a user specified default value and supersedes -; SystemVerilog specified default value of '0'(zero). -; SVCovergroupGetInstCoverageDefault = 0 - -; -; A space separated list of resource libraries that contain precompiled -; packages. The behavior is identical to using the "-L" switch. -; -; LibrarySearchPath = [ ...] -LibrarySearchPath = mtiAvm mtiOvm mtiUvm mtiUPF - -; The behavior is identical to the "-mixedansiports" switch. Default is off. -; MixedAnsiPorts = 1 - -; Enable SystemVerilog 3.1a $typeof() function. Default is off. -; EnableTypeOf = 1 - -; Only allow lower case pragmas. Default is disabled. -; AcceptLowerCasePragmaOnly = 1 - -; Set the maximum depth permitted for a recursive include file nesting. -; IncludeRecursionDepthMax = 5 - -; Turn ON detection of FSMs having single bit current state variable. -; FsmSingle = 1 - -; Turn off reset state transitions in FSM. -; FsmResetTrans = 0 - -; Turn off detections of FSMs having x-assignment. -; FsmXAssign = 0 - -; Turn ON detection of FSM Implicit Transitions. -; FsmImplicitTrans = 1 - -; List of file suffixes which will be read as SystemVerilog. White space -; in extensions can be specified with a back-slash: "\ ". Back-slashes -; can be specified with two consecutive back-slashes: "\\"; -; SVFileExtensions = sv svp svh - -; This setting is the same as the vlog -sv command line switch. -; Enables SystemVerilog features and keywords when true (1). -; When false (0), the rules of IEEE Std 1364-2001 are followed and -; SystemVerilog keywords are ignored. -; Svlog = 0 - -; Prints attribute placed upon SV packages during package import -; when true (1). The attribute will be ignored when this -; entry is false (0). The attribute name is "package_load_message". -; The value of this attribute is a string literal. -; Default is true (1). -; PrintSVPackageLoadingAttribute = 1 - -; Do not show immediate assertions with constant expressions in -; GUI/reports/UCDB etc. By default immediate assertions with constant -; expressions are shown in GUI/reports/UCDB etc. This does not affect -; evaluation of immediate assertions. -; ShowConstantImmediateAsserts = 0 - -; Controls if untyped parameters that are initialized with values greater -; than 2147483647 are mapped to generics of type INTEGER or ignored. -; If mapped to VHDL Integers, values greater than 2147483647 -; are mapped to negative values. -; Default is to map these parameter to generic of type INTEGER -; ForceUnsignedToVHDLInteger = 1 - -; Enable AMS wreal (wired real) extensions. Default is 0. -; WrealType = 1 - -[sccom] -; Enable use of SCV include files and library. Default is off. -; UseScv = 1 - -; Add C++ compiler options to the sccom command line by using this variable. -; CppOptions = -g - -; Use custom C++ compiler located at this path rather than the default path. -; The path should point directly at a compiler executable. -; CppPath = /usr/bin/g++ - -; Enable verbose messages from sccom. Default is off. -; SccomVerbose = 1 - -; sccom logfile. Default is no logfile. -; SccomLogfile = sccom.log - -; Enable use of SC_MS include files and library. Default is off. -; UseScMs = 1 - -[vopt] -; Turn on code coverage in vopt. Default is off. -; Coverage = sbceft - -; Control compiler optimizations that are allowed when -; code coverage is on. Refer to the comment for this in the [vlog] area. -; CoverOpt = 3 - -; Increase or decrease the maximum number of rows allowed in a UDP table -; implementing a vopt condition coverage or expression coverage expression. -; More rows leads to a longer compile time, but more expressions covered. -; CoverMaxUDPRows = 192 - -; Increase or decrease the maximum number of input patterns that are present -; in FEC table. This leads to a longer compile time with more expressions -; covered with FEC metric. -; CoverMaxFECRows = 192 - -; Enable code coverage reporting of code that has been optimized away. -; The default is not to report. -; CoverReportCancelled = 1 - -; Do not show immediate assertions with constant expressions in -; GUI/reports/UCDB etc. By default immediate assertions with constant -; expressions are shown in GUI/reports/UCDB etc. This does not affect -; evaluation of immediate assertions. -; ShowConstantImmediateAsserts = 0 - -; Set the maximum number of iterations permitted for a generate loop. -; Restricting this permits the implementation to recognize infinite -; generate loops. -; GenerateLoopIterationMax = 100000 - -; Set the maximum depth permitted for a recursive generate instantiation. -; Restricting this permits the implementation to recognize infinite -; recursions. -; GenerateRecursionDepthMax = 200 - - -[vsim] -; vopt flow -; Set to turn on automatic optimization of a design. -; Default is on -VoptFlow = 1 - -; Simulator resolution -; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. -Resolution = ns - -; Disable certain code coverage exclusions automatically. -; Assertions and FSM are exluded from the code coverage by default -; Set AutoExclusionsDisable = fsm to enable code coverage for fsm -; Set AutoExclusionsDisable = assertions to enable code coverage for assertions -; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions -; Or specify comma or space separated list -;AutoExclusionsDisable = fsm,assertions - -; User time unit for run commands -; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the -; unit specified for Resolution. For example, if Resolution is 100ps, -; then UserTimeUnit defaults to ps. -; Should generally be set to default. -UserTimeUnit = default - -; Default run length -RunLength = 5 ms - -; Maximum iterations that can be run without advancing simulation time -IterationLimit = 5000 - -; Control PSL and Verilog Assume directives during simulation -; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts -; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts -; SimulateAssumeDirectives = 1 - -; Control the simulation of PSL and SVA -; These switches can be overridden by the vsim command line switches: -; -psl, -nopsl, -sva, -nosva. -; Set SimulatePSL = 0 to disable PSL simulation -; Set SimulatePSL = 1 to enable PSL simulation (default) -; SimulatePSL = 1 -; Set SimulateSVA = 0 to disable SVA simulation -; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) -; SimulateSVA = 1 - -; Directives to license manager can be set either as single value or as -; space separated multi-values: -; vhdl Immediately reserve a VHDL license -; vlog Immediately reserve a Verilog license -; plus Immediately reserve a VHDL and Verilog license -; noqueue Do not wait in the license queue when a license is not available -; viewsim Try for viewer license but accept simulator license(s) instead -; of queuing for viewer license (PE ONLY) -; noviewer Disable checkout of msimviewer and vsim-viewer license -; features (PE ONLY) -; noslvhdl Disable checkout of qhsimvh and vsim license features -; noslvlog Disable checkout of qhsimvl and vsimvlog license features -; nomix Disable checkout of msimhdlmix and hdlmix license features -; nolnl Disable checkout of msimhdlsim and hdlsim license features -; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license -; features -; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix, -; hdlmix license features -; Single value: -; License = plus -; Multi-value: -; License = noqueue plus - -; Severity level of a VHDL assertion message or of a SystemVerilog immediate assertion -; which will cause a running simulation to stop. -; VHDL assertions and SystemVerilog immediate assertions that occur with the -; given severity or higher will cause a running simulation to stop. -; This value is ignored during elaboration. -; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal -BreakOnAssertion = 3 - -; Message Format conversion specifications: -; %S - Severity Level of message/assertion -; %R - Text of message -; %T - Time of message -; %D - Delta value (iteration number) of Time -; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected -; %i - Instance/Region/Signal pathname with Process name (if available) -; %I - shorthand for one of these: -; " %K: %i" -; " %K: %i File: %F" (when path is not Process or Signal) -; except that the %i in this case does not report the Process name -; %O - Process name -; %P - Instance/Region path without leaf process -; %F - File name -; %L - Line number; if assertion message, then line number of assertion or, if -; assertion is in a subprogram, line from which the call is made -; %u - Design unit name in form library.primary -; %U - Design unit name in form library.primary(secondary) -; %% - The '%' character itself -; -; If specific format for Severity Level is defined, use that format. -; Else, for a message that occurs during elaboration: -; -- Failure/Fatal message in VHDL region that is not a Process, and in -; certain non-VHDL regions, uses MessageFormatBreakLine; -; -- Failure/Fatal message otherwise uses MessageFormatBreak; -; -- Note/Warning/Error message uses MessageFormat. -; Else, for a message that occurs during runtime and triggers a breakpoint because -; of the BreakOnAssertion setting: -; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; -; -- otherwise uses MessageFormatBreak. -; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. -; -; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" -; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" -; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" -; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" - -; Error File - alternate file for storing error messages -; ErrorFile = error.log - -; Simulation Breakpoint messages -; This flag controls the display of function names when reporting the location -; where the simulator stops because of a breakpoint or fatal error. -; Example with function name: # Break in Process ctr at counter.vhd line 44 -; Example without function name: # Break at counter.vhd line 44 -; Default value is 1. -ShowFunctions = 1 - -; Default radix for all windows and commands. -; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned -DefaultRadix = symbolic - -; VSIM Startup command -; Startup = do startup.do - -; VSIM Shutdown file -; Filename to save u/i formats and configurations. -; ShutdownFile = restart.do -; To explicitly disable auto save: -; ShutdownFile = --disable-auto-save - -; File for saving command transcript -TranscriptFile = transcript - -; File for saving command history -; CommandHistory = cmdhist.log - -; Specify whether paths in simulator commands should be described -; in VHDL or Verilog format. -; For VHDL, PathSeparator = / -; For Verilog, PathSeparator = . -; Must not be the same character as DatasetSeparator. -PathSeparator = / - -; Specify the dataset separator for fully rooted contexts. -; The default is ':'. For example: sim:/top -; Must not be the same character as PathSeparator. -DatasetSeparator = : - -; Specify a unique path separator for the Signal Spy set of functions. -; The default will be to use the PathSeparator variable. -; Must not be the same character as DatasetSeparator. -; SignalSpyPathSeparator = / - -; Used to control parsing of HDL identifiers input to the tool. -; This includes CLI commands, vsim/vopt/vlog/vcom options, -; string arguments to FLI/VPI/DPI calls, etc. -; If set to 1, accept either Verilog escaped Id syntax or -; VHDL extended id syntax, regardless of source language. -; If set to 0, the syntax of the source language must be used. -; Each identifier in a hierarchical name may need different syntax, -; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or -; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" -; GenerousIdentifierParsing = 1 - -; Disable VHDL assertion messages -; IgnoreNote = 1 -; IgnoreWarning = 1 -; IgnoreError = 1 -; IgnoreFailure = 1 - -; Disable SystemVerilog assertion messages -; IgnoreSVAInfo = 1 -; IgnoreSVAWarning = 1 -; IgnoreSVAError = 1 -; IgnoreSVAFatal = 1 - -; Do not print any additional information from Severity System tasks. -; Only the message provided by the user is printed along with severity -; information. -; SVAPrintOnlyUserMessage = 1; - -; Default force kind. May be freeze, drive, deposit, or default -; or in other terms, fixed, wired, or charged. -; A value of "default" will use the signal kind to determine the -; force kind, drive for resolved signals, freeze for unresolved signals -; DefaultForceKind = freeze - -; Control the iteration of events when a VHDL signal is forced to a value -; This flag can be set to honour the signal update event in next iteration, -; the default is to update and propagate in the same iteration. -; ForceSigNextIter = 1 - - -; If zero, open files when elaborated; otherwise, open files on -; first read or write. Default is 0. -; DelayFileOpen = 1 - -; Control VHDL files opened for write. -; 0 = Buffered, 1 = Unbuffered -UnbufferedOutput = 0 - -; Control the number of VHDL files open concurrently. -; This number should always be less than the current ulimit -; setting for max file descriptors. -; 0 = unlimited -ConcurrentFileLimit = 40 - -; Control the number of hierarchical regions displayed as -; part of a signal name shown in the Wave window. -; A value of zero tells VSIM to display the full name. -; The default is 0. -; WaveSignalNameWidth = 0 - -; Turn off warnings when changing VHDL constants and generics -; Default is 1 to generate warning messages -; WarnConstantChange = 0 - -; Turn off warnings from accelerated versions of the std_logic_arith, -; std_logic_unsigned, and std_logic_signed packages. -; StdArithNoWarnings = 1 - -; Turn off warnings from accelerated versions of the IEEE numeric_std -; and numeric_bit packages. -; NumericStdNoWarnings = 1 - -; Use old-style (pre-6.6) VHDL FOR generate statement iteration names -; in the design hierarchy. -; This style is controlled by the value of the GenerateFormat -; value described next. Default is to use new-style names, which -; comprise the generate statement label, '(', the value of the generate -; parameter, and a closing ')'. -; Uncomment this to use old-style names. -; OldVhdlForGenNames = 1 - -; Enable changes in VHDL elaboration to allow for Variable Logging -; This trades off simulation performance for the ability to log variables -; efficiently. By default this is disable for maximum simulation performance -; VhdlVariableLogging = 1 - -; Control the format of the old-style VHDL FOR generate statement region -; name for each iteration. Do not quote it. -; The format string here must contain the conversion codes %s and %d, -; in that order, and no other conversion codes. The %s represents -; the generate statement label; the %d represents the generate parameter value -; at a particular iteration (this is the position number if the generate parameter -; is of an enumeration type). Embedded whitespace is allowed (but discouraged); -; leading and trailing whitespace is ignored. -; Application of the format must result in a unique region name over all -; loop iterations for a particular immediately enclosing scope so that name -; lookup can function properly. The default is %s__%d. -; GenerateFormat = %s__%d - -; Specify whether checkpoint files should be compressed. -; The default is 1 (compressed). -; CheckpointCompressMode = 0 - -; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. -; Use custom gcc compiler located at this path rather than the default path. -; The path should point directly at a compiler executable. -; DpiCppPath = /bin/gcc - -; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. -; The term "out-of-the-blue" refers to SystemVerilog export function calls -; made from C functions that don't have the proper context setup -; (as is the case when running under "DPI-C" import functions). -; When this is enabled, one can call a DPI export function -; (but not task) from any C code. -; the setting of this variable can be one of the following values: -; 0 : dpioutoftheblue call is disabled (default) -; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. -; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. -; DpiOutOfTheBlue = 1 - -; Specify whether continuous assignments are run before other normal priority -; processes scheduled in the same iteration. This event ordering minimizes race -; differences between optimized and non-optimized designs, and is the default -; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set -; ImmediateContinuousAssign to 0. -; The default is 1 (enabled). -; ImmediateContinuousAssign = 0 - -; List of dynamically loaded objects for Verilog PLI applications -; Veriuser = veriuser.sl - -; Which default VPI object model should the tool conform to? -; The 1364 modes are Verilog-only, for backwards compatibility with older -; libraries, and SystemVerilog objects are not available in these modes. -; -; In the absence of a user-specified default, the tool default is the -; latest available LRM behavior. -; Options for PliCompatDefault are: -; VPI_COMPATIBILITY_VERSION_1364v1995 -; VPI_COMPATIBILITY_VERSION_1364v2001 -; VPI_COMPATIBILITY_VERSION_1364v2005 -; VPI_COMPATIBILITY_VERSION_1800v2005 -; VPI_COMPATIBILITY_VERSION_1800v2008 -; -; Synonyms for each string are also recognized: -; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) -; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) -; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) -; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) -; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) - - -; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 - -; Specify default options for the restart command. Options can be one -; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions -; DefaultRestartOptions = -force - -; Turn on (1) or off (0) WLF file compression. -; The default is 1 (compress WLF file). -; WLFCompress = 0 - -; Specify whether to save all design hierarchy (1) in the WLF file -; or only regions containing logged signals (0). -; The default is 0 (save only regions with logged signals). -; WLFSaveAllRegions = 1 - -; WLF file time limit. Limit WLF file by time, as closely as possible, -; to the specified amount of simulation time. When the limit is exceeded -; the earliest times get truncated from the file. -; If both time and size limits are specified the most restrictive is used. -; UserTimeUnits are used if time units are not specified. -; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} -; WLFTimeLimit = 0 - -; WLF file size limit. Limit WLF file size, as closely as possible, -; to the specified number of megabytes. If both time and size limits -; are specified then the most restrictive is used. -; The default is 0 (no limit). -; WLFSizeLimit = 1000 - -; Specify whether or not a WLF file should be deleted when the -; simulation ends. A value of 1 will cause the WLF file to be deleted. -; The default is 0 (do not delete WLF file when simulation ends). -; WLFDeleteOnQuit = 1 - -; Specify whether or not a WLF file should be optimized during -; simulation. If set to 0, the WLF file will not be optimized. -; The default is 1, optimize the WLF file. -; WLFOptimize = 0 - -; Specify the name of the WLF file. -; The default is vsim.wlf -; WLFFilename = vsim.wlf - -; Specify whether to lock the WLF file. -; Locking the file prevents other invocations of ModelSim/Questa tools from -; inadvertently overwriting the WLF file. -; The default is 1, lock the WLF file. -; WLFFileLock = 0 - -; Specify the WLF reader cache size limit for each open WLF file. -; The size is giving in megabytes. A value of 0 turns off the -; WLF cache. -; WLFSimCacheSize allows a different cache size to be set for -; simulation WLF file independent of post-simulation WLF file -; viewing. If WLFSimCacheSize is not set it defaults to the -; WLFCacheSize setting. -; The default WLFCacheSize setting is enabled to 256M per open WLF file. -; WLFCacheSize = 2000 -; WLFSimCacheSize = 500 - -; Specify the WLF file event collapse mode. -; 0 = Preserve all events and event order. (same as -wlfnocollapse) -; 1 = Only record values of logged objects at the end of a simulator iteration. -; (same as -wlfcollapsedelta) -; 2 = Only record values of logged objects at the end of a simulator time step. -; (same as -wlfcollapsetime) -; The default is 1. -; WLFCollapseMode = 0 - -; Specify whether WLF file logging can use threads on multi-processor machines -; if 0, no threads will be used, if 1, threads will be used if the system has -; more than one processor -; WLFUseThreads = 1 - -; Turn on/off undebuggable SystemC type warnings. Default is on. -; ShowUndebuggableScTypeWarning = 0 - -; Turn on/off unassociated SystemC name warnings. Default is off. -; ShowUnassociatedScNameWarning = 1 - -; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. -; ScShowIeeeDeprecationWarnings = 1 - -; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. -; ScEnableScSignalWriteCheck = 1 - -; Set SystemC default time unit. -; Set to fs, ps, ns, us, ms, or sec with optional -; prefix of 1, 10, or 100. The default is 1 ns. -; The ScTimeUnit value is honored if it is coarser than Resolution. -; If ScTimeUnit is finer than Resolution, it is set to the value -; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, -; then the default time unit will be 1 ns. However if Resolution -; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. -ScTimeUnit = ns - -; Set SystemC sc_main stack size. The stack size is set as an integer -; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or -; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends -; on the amount of data on the sc_main() stack and the memory required -; to succesfully execute the longest function call chain of sc_main(). -ScMainStackSize = 10 Mb - -; Turn on/off execution of remainder of sc_main upon quitting the current -; simulation session. If the cumulative length of sc_main() in terms of -; simulation time units is less than the length of the current simulation -; run upon quit or restart, sc_main() will be in the middle of execution. -; This switch gives the option to execute the remainder of sc_main upon -; quitting simulation. The drawback of not running sc_main till the end -; is memory leaks for objects created by sc_main. If on, the remainder of -; sc_main will be executed ignoring all delays. This may cause the simulator -; to crash if the code in sc_main is dependent on some simulation state. -; Default is on. -ScMainFinishOnQuit = 1 - -; Set the SCV relationship name that will be used to identify phase -; relations. If the name given to a transactor relation matches this -; name, the transactions involved will be treated as phase transactions -ScvPhaseRelationName = mti_phase - -; Customize the vsim kernel shutdown behavior at the end of the simulation. -; Some common causes of the end of simulation are $finish (implicit or explicit), -; sc_stop(), tf_dofinish(), and assertion failures. -; This should be set to "ask", "exit", or "stop". The default is "ask". -; "ask" -- In batch mode, the vsim kernel will abruptly exit. -; In GUI mode, a dialog box will pop up and ask for user confirmation -; whether or not to quit the simulation. -; "stop" -- Cause the simulation to stay loaded in memory. This can make some -; post-simulation tasks easier. -; "exit" -- The simulation will abruptly exit without asking for any confirmation. -; "final" -- Run SystemVerilog final blocks then behave as "stop". -; Note: This variable can be overridden with the vsim "-onfinish" command line switch. -OnFinish = ask - -; Print pending deferred assertion messages. -; Deferred assertion messages may be scheduled after the $finish in the same -; time step. Deferred assertions scheduled to print after the $finish are -; printed before exiting with severity level NOTE since it's not known whether -; the assertion is still valid due to being printed in the active region -; instead of the reactive region where they are normally printed. -; OnFinishPendingAssert = 1; - -; Print "simstats" result -; 0 == do not print simstats -; 1 == print at end of simulation -; 2 == print at end of run -; 3 == print at end of run and end of simulation -; default == 0 -; PrintSimStats = 1 - - -; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages -; AssertFile = assert.log - -; Enable assertion counts. Default is off. -; AssertionCover = 1 - -; Run simulator in assertion debug mode. Default is off. -; AssertionDebug = 1 - -; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. -; AssertionEnable = 0 - -; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. -; Any positive integer, -1 for infinity. -; AssertionLimit = 1 - -; Turn on/off concurrent assertion pass log. Default is off. -; Assertion pass logging is only enabled when assertion is browseable -; and assertion debug is enabled. -; AssertionPassLog = 1 - -; Turn on/off PSL concurrent assertion fail log. Default is on. -; The flag does not affect SVA -; AssertionFailLog = 0 - -; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. -; AssertionFailLocalVarLog = 0 - -; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. -; 0 = Continue 1 = Break 2 = Exit -; AssertionFailAction = 1 - -; Enable the active thread monitor in the waveform display when assertion debug is enabled. -; AssertionActiveThreadMonitor = 1 - -; Control how many waveform rows will be used for displaying the active threads. Default is 5. -; AssertionActiveThreadMonitorLimit = 5 - -; Assertion thread limit after which assertion would be killed/switched off. -; The default is -1 (unlimited). If the number of threads for an assertion go -; beyond this limit, the assertion would be either switched off or killed. This -; limit applies to only assert directives. -;AssertionThreadLimit = -1 - -; Action to be taken once the assertion thread limit is reached. Default -; is kill. It can have a value of off or kill. In case of kill, all the existing -; threads are terminated and no new attempts are started. In case of off, the -; existing attempts keep on evaluating but no new attempts are started. This -; variable applies to only assert directives. -;AssertionThreadLimitAction = kill - -; Cover thread limit after which cover would be killed/switched off. -; The default is -1 (unlimited). If the number of threads for a cover go -; beyond this limit, the cover would be either switched off or killed. This -; limit applies to only cover directives. -;CoverThreadLimit = -1 - -; Action to be taken once the cover thread limit is reached. Default -; is kill. It can have a value of off or kill. In case of kill, all the existing -; threads are terminated and no new attempts are started. In case of off, the -; existing attempts keep on evaluating but no new attempts are started. This -; variable applies to only cover directives. -;CoverThreadLimitAction = kill - - -; By default immediate assertions do not participate in Assertion Coverage calculations -; unless they are executed. This switch causes all immediate assertions in the design -; to participate in Assertion Coverage calculations, whether attempted or not. -; UnattemptedImmediateAssertions = 0 - -; By default immediate covers participate in Coverage calculations -; whether they are attempted or not. This switch causes all unattempted -; immediate covers in the design to stop participating in Coverage -; calculations. -; UnattemptedImmediateCovers = 0 - -; By default pass action block is not executed for assertions on vacuous -; success. The following variable is provided to enable execution of -; pass action block on vacuous success. The following variable is only effective -; if the user does not disable pass action block execution by using either -; system tasks or CLI. Also there is a performance penalty for enabling -; the following variable. -;AssertionEnableVacuousPassActionBlock = 1 - -; As per strict 1850-2005 PSL LRM, an always property can either pass -; or fail. However, by default, Questa reports multiple passes and -; multiple fails on top always/never property (always/never operator -; is the top operator under Verification Directive). The reason -; being that Questa reports passes and fails on per attempt of the -; top always/never property. Use the following flag to instruct -; Questa to strictly follow LRM. With this flag, all assert/never -; directives will start an attempt once at start of simulation. -; The attempt can either fail, match or match vacuously. -; For e.g. if always is the top operator under assert, the always will -; keep on checking the property at every clock. If the property under -; always fails, the directive will be considered failed and no more -; checking will be done for that directive. A top always property, -; if it does not fail, will show a pass at end of simulation. -; The default value is '0' (i.e. zero is off). For example: -; PslOneAttempt = 1 - -; Specify the number of clock ticks to represent infinite clock ticks. -; This affects eventually!, until! and until_!. If at End of Simulation -; (EOS) an active strong-property has not clocked this number of -; clock ticks then neither pass or fail (vacuous match) is returned -; else respective fail/pass is returned. The default value is '0' (zero) -; which effectively does not check for clock tick condition. For example: -; PslInfinityThreshold = 5000 - -; Control how many thread start times will be preserved for ATV viewing for a given assertion -; instance. Default is -1 (ALL). -; ATVStartTimeKeepCount = -1 - -; Turn on/off code coverage -; CodeCoverage = 0 - -; Count all code coverage condition and expression truth table rows that match. -; CoverCountAll = 1 - -; Turn off automatic inclusion of VHDL integers in toggle coverage. Default -; is to include them. -; ToggleNoIntegers = 1 - -; Set the maximum number of values that are collected for toggle coverage of -; VHDL integers. Default is 100; -; ToggleMaxIntValues = 100 - -; Set the maximum number of values that are collected for toggle coverage of -; Verilog real. Default is 100; -; ToggleMaxRealValues = 100 - -; Turn on automatic inclusion of Verilog integers in toggle coverage, except -; for enumeration types. Default is to include them. -; ToggleVlogIntegers = 0 - -; Turn on automatic inclusion of Verilog real type in toggle coverage, except -; for shortreal types. Default is to not include them. -; ToggleVlogReal = 1 - -; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays -; and VHDL arrays-of-arrays in toggle coverage. -; Default is to not include them. -; ToggleFixedSizeArray = 1 - -; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, -; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. -; This leads to a longer simulation time with bigger arrays covered with toggle coverage. -; Default is 1024. -; ToggleMaxFixedSizeArray = 1024 - -; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized -; one-dimensional packed vectors for toggle coverage. Default is 0. -; TogglePackedAsVec = 0 - -; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for -; toggle coverage. Default is 0. -; ToggleVlogEnumBits = 0 - -; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. -; For unlimited width, set to 0. -; ToggleWidthLimit = 128 - -; Limit the counts that are tracked for toggle coverage. When all edges for a bit have -; reached this count, further activity on the bit is ignored. Default is 1. -; For unlimited counts, set to 0. -; ToggleCountLimit = 1 - -; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. -; Following is the toggle coverage calculation criteria based on extended toggle mode: -; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). -; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. -; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. -; ExtendedToggleMode = 3 - -; Enable toggle statistics collection only for ports. Default is 0. -; TogglePortsOnly = 1 - -; Turn on/off all PSL/SVA cover directive enables. Default is on. -; CoverEnable = 0 - -; Turn on/off PSL/SVA cover log. Default is off "0". -; CoverLog = 1 - -; Set "at_least" value for all PSL/SVA cover directives. Default is 1. -; CoverAtLeast = 2 - -; Set "limit" value for all PSL/SVA cover directives. Default is -1. -; Any positive integer, -1 for infinity. -; CoverLimit = 1 - -; Specify the coverage database filename. -; Default is "" (i.e. database is NOT automatically saved on close). -; UCDBFilename = vsim.ucdb - -; Specify the maximum limit for the number of Cross (bin) products reported -; in XML and UCDB report against a Cross. A warning is issued if the limit -; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this -; setting. -; MaxReportRhsSVCrossProducts = 1000 - -; Specify the override for the "auto_bin_max" option for the Covergroups. -; If not specified then value from Covergroup "option" is used. -; SVCoverpointAutoBinMax = 64 - -; Specify the override for the value of "cross_num_print_missing" -; option for the Cross in Covergroups. If not specified then value -; specified in the "option.cross_num_print_missing" is used. This -; is a runtime option. NOTE: This overrides any "cross_num_print_missing" -; value specified by user in source file and any SVCrossNumPrintMissingDefault -; specified in modelsim.ini. -; SVCrossNumPrintMissing = 0 - -; Specify whether to use the value of "cross_num_print_missing" -; option in report and GUI for the Cross in Covergroups. If not specified then -; cross_num_print_missing is ignored for creating reports and displaying -; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". -; UseSVCrossNumPrintMissing = 0 - -; Specify the threshold of Coverpoint wildcard bin value range size, above which -; a warning will be triggered. The default is 4K -- 12 wildcard bits. -; SVCoverpointWildCardBinValueSizeWarn = 4096 - -; Specify the override for the value of "strobe" option for the -; Covergroup Type. If not specified then value in "type_option.strobe" -; will be used. This is runtime option which forces "strobe" to -; user specified value and supersedes user specified values in the -; SystemVerilog Code. NOTE: This also overrides the compile time -; default value override specified using "SVCovergroupStrobeDefault" -; SVCovergroupStrobe = 0 - -; Override for explicit assignments in source code to "option.goal" of -; SystemVerilog covergroup, coverpoint, and cross. It also overrides the -; default value of "option.goal" (defined to be 100 in the SystemVerilog -; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". -; SVCovergroupGoal = 100 - -; Override for explicit assignments in source code to "type_option.goal" of -; SystemVerilog covergroup, coverpoint, and cross. It also overrides the -; default value of "type_option.goal" (defined to be 100 in the SystemVerilog -; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". -; SVCovergroupTypeGoal = 100 - -; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() -; builtin functions, and report. This setting changes the default values of -; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 -; behavior if explicit assignments are not made on option.get_inst_coverage and -; type_option.merge_instances by the user. There are two vsim command line -; options, -cvg63 and -nocvg63 to override this setting from vsim command line. -; The default value of this variable from release 6.6 onwards is 0. This default -; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. -; SVCovergroup63Compatibility = 0 - -; Enforce the 6.5 default behavior of covergroup get_coverage() builtin -; functions, GUI, and report. This setting changes the default values of -; type_option.merge_instances to ensure the 6.5 default behavior if explicit -; assignments are not made on type_option.merge_instances by the user. -; There are two vsim command line options, -cvgmergeinstances and -; -nocvgmergeinstances to override this setting from vsim command line. -; The default value of this variable from release 6.6 onwards is 0. This default -; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. -; SvCovergroupMergeInstancesDefault = 1 - -; Enable or disable generation of more detailed information about the sampling -; of covergroup, cross, and coverpoints. It provides the details of the number -; of times the covergroup instance and type were sampled, as well as details -; about why covergroup, cross and coverpoint were not covered. A non-zero value -; is to enable this feature. 0 is to disable this feature. Default is 0 -; SVCovergroupSampleInfo = 0 - -; Specify the maximum number of Coverpoint bins in whole design for -; all Covergroups. -; MaxSVCoverpointBinsDesign = 2147483648 - -; Specify maximum number of Coverpoint bins in any instance of a Covergroup -; MaxSVCoverpointBinsInst = 2147483648 - -; Specify the maximum number of Cross bins in whole design for -; all Covergroups. -; MaxSVCrossBinsDesign = 2147483648 - -; Specify maximum number of Cross bins in any instance of a Covergroup -; MaxSVCrossBinsInst = 2147483648 - -; Specify a space delimited list of double quoted TCL style -; regular expressions which will be matched against the text of all messages. -; If any regular expression is found to be contained within any message, the -; status for that message will not be propagated to the UCDB TESTSTATUS. -; If no match is detected, then the status will be propagated to the -; UCDB TESTSTATUS. More than one such regular expression text is allowed, -; and each message text is compared for each regular expression in the list. -; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" - -; Set weight for all PSL/SVA cover directives. Default is 1. -; CoverWeight = 2 - -; Check vsim plusargs. Default is 0 (off). -; 0 = Don't check plusargs -; 1 = Warning on unrecognized plusarg -; 2 = Error and exit on unrecognized plusarg -; CheckPlusargs = 1 - -; Load the specified shared objects with the RTLD_GLOBAL flag. -; This gives global visibility to all symbols in the shared objects, -; meaning that subsequently loaded shared objects can bind to symbols -; in the global shared objects. The list of shared objects should -; be whitespace delimited. This option is not supported on the -; Windows or AIX platforms. -; GlobalSharedObjectList = example1.so example2.so example3.so - -; Run the 0in tools from within the simulator. -; Default is off. -; ZeroIn = 1 - -; Set the options to be passed to the 0in runtime tool. -; Default value set to "". -; ZeroInOptions = "" - -; Initial seed for the random number generator of the root thread (SystemVerilog). -; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. -; The default value is 0. -; Sv_Seed = 0 - -; Specify the solver "engine" that vsim will select for constrained random -; generation. -; Valid values are: -; "auto" - automatically select the best engine for the current -; constraint scenario -; "bdd" - evaluate all constraint scenarios using the BDD solver engine -; "act" - evaluate all constraint scenarios using the ACT solver engine -; While the BDD solver engine is generally efficient with constraint scenarios -; involving bitwise logical relationships, the ACT solver engine can exhibit -; superior performance with constraint scenarios involving large numbers of -; random variables related via arithmetic operators (+, *, etc). -; NOTE: This variable can be overridden with the vsim "-solveengine" command -; line switch. -; The default value is "auto". -; SolveEngine = auto - -; Specify if the solver should attempt to ignore overflow/underflow semantics -; for arithmetic constraints (multiply, addition, subtraction) in order to -; improve performance. The "solveignoreoverflow" attribute can be specified on -; a per-call basis to randomize() to override this setting. -; The default value is 0 (overflow/underflow is not ignored). Set to 1 to -; ignore overflow/underflow. -; SolveIgnoreOverflow = 0 - -; Specifies the maximum size that a dynamic array may be resized to by the -; solver. If the solver attempts to resize a dynamic array to a size greater -; than the specified limit, the solver will abort with an error. -; The default value is 2000. A value of 0 indicates no limit. -; SolveArrayResizeMax = 2000 - -; Error message severity when randomize() failure is detected (SystemVerilog). -; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal -; The default is 0 (no error). -; SolveFailSeverity = 0 - -; Enable/disable debug information for randomize() failures. -; NOTE: This variable can be overridden with the vsim "-solvefaildbug" command -; line switch. -; The default is 0 (disabled). Set to 1 to enable. -; SolveFailDebug = 0 - -; Specify the maximum size of the solution graph generated by the BDD solver. -; This value can be used to force the BDD solver to abort the evaluation of a -; complex constraint scenario that cannot be evaluated with finite memory. -; This value is specified in 1000s of nodes. -; The default value is 10000. A value of 0 indicates no limit. -; SolveGraphMaxSize = 10000 - -; Specify the maximum number of evaluations that may be performed on the -; solution graph by the BDD solver. This value can be used to force the BDD -; solver to abort the evaluation of a complex constraint scenario that cannot -; be evaluated in finite time. This value is specified in 10000s of evaluations. -; The default value is 10000. A value of 0 indicates no limit. -; SolveGraphMaxEval = 10000 - -; Specify the maximum number of tests that the ACT solver may evaluate before -; abandoning an attempt to solve a particular constraint scenario. -; The default value is 20000000. A value of 0 indicates no limit. -; SolveACTMaxTests = 20000000 - -; Specify the maximum number of operations that the ACT solver may perform -; before abandoning an attempt to solve a particular constraint scenario. The -; value is specified in 1000000s of operations. The default value is 1000. A -; value of 0 indicates no limit. -; SolveACTMaxOps = 1000 - -; Specify the number of times the ACT solver will retry to evaluate a constraint -; scenario that fails due to the SolveACTMaxTests threshold. -; The default value is 0 (no retry). -; SolveACTRetryCount = 0 - -; SolveSpeculateLevel controls whether or not the solver performs speculation -; during the evaluation of a constraint scenario. -; Speculation is an attempt to partition complex constraint scenarios by -; choosing a 'speculation' subset of the variables and constraints. This -; 'speculation' set is solved independently of the remaining constraints. -; The solver then attempts to solve the remaining variables and constraints -; (the 'dependent' set). If this attempt fails, the solver backs up and -; re-solves the 'speculation' set, then retries the 'dependent' set. -; Valid values are: -; 0 - no speculation -; 1 - enable speculation that maintains LRM specified distribution -; 2 - enable other speculation - may yield non-LRM distribution -; Currently, distribution constraints and solve-before constraints are -; used in selecting the 'speculation' sets for speculation level 1. Non-LRM -; compliant speculation includes random variables in condition expressions. -; The default value is 0. -; SolveSpeculateLevel = 0 - -; By default, when speculation is enabled, the solver first tries to solve a -; constraint scenario *without* speculation. If the solver fails to evaluate -; the constraint scenario (due to time/memory limits) then the solver will -; re-evaluate the constraint scenario with speculation. If SolveSpeculateFirst -; is set to 1, the solver will skip the initial non-speculative attempt to -; evaluate the constraint scenario. (Only applies when SolveSpeculateLevel is -; non-zero) -; The default value is 0. -; SolveSpeculateFirst = 0 - -; Specify the maximum bit width of a variable in a conditional expression that -; may be considered as the basis for "conditional" speculation. (Only applies -; when SolveSpeculateLevel=2) -; The default value is 6. -; SolveSpeculateMaxCondWidth = 6 - -; Specify the maximum number of attempts to solve a speculative set of random -; variables and constraints. Exceeding this limit will cause the solver to -; abandon the current speculative set. (Only applies when SolveSpeculateLevel -; is non-zero) -; The default value is 100. -; SolveSpeculateMaxIterations = 100 - -; Specifies whether to attempt speculation on solve-before constraints or -; distribution constraints first. A value of 0 specifies that solve-before -; constraints are attempted first as the basis for speculative randomization. -; A value of 1 specifies that distribution constraints are attempted first -; as the basis for speculative randomization. -; The default value is 0. -; SolveSpeculateDistFirst = 0 - -; If the non-speculative BDD solver fails to evaluate a constraint scenario -; (due to time/memory limits) then the solver can be instructed to automatically -; re-evaluate the constraint scenario with the ACT solver engine. Set -; SolveACTbeforeSpeculate to 1 to enable this feature. -; The default value is 0 (do not re-evaluate with the ACT solver). -; SolveACTbeforeSpeculate = 0 - -; Use SolveFlags to specify options that will guide the behavior of the -; constraint solver. These options may improve the performance of the -; constraint solver for some testcases, and decrease the performance of the -; constraint solver for others. -; Valid flags are: -; i = disable bit interleaving for >, >=, <, <= constraints (BDD engine) -; n = disable bit interleaving for all constraints (BDD engine) -; r = reverse bit interleaving (BDD engine) -; The default value is "" (no options). -; SolveFlags = - -; Specify random sequence compatiblity with a prior letter release. This -; option is used to get the same random sequences during simulation as -; as a prior letter release. Only prior letter releases (of the current -; number release) are allowed. -; NOTE: Only those random sequence changes due to solver optimizations are -; reverted by this variable. Random sequence changes due to solver bugfixes -; cannot be un-done. -; NOTE: This variable can be overridden with the vsim "-solverev" command -; line switch. -; Default value set to "" (no compatibility). -; SolveRev = - -; Environment variable expansion of command line arguments has been depricated -; in favor shell level expansion. Universal environment variable expansion -; inside -f files is support and continued support for MGC Location Maps provide -; alternative methods for handling flexible pathnames. -; The following line may be uncommented and the value set to 1 to re-enable this -; deprecated behavior. The default value is 0. -; DeprecatedEnvironmentVariableExpansion = 0 - -; Turn on/off collapsing of bus ports in VCD dumpports output -DumpportsCollapse = 1 - -; Location of Multi-Level Verification Component (MVC) installation. -; The default location is the product installation directory. -; MvcHome = $MODEL_TECH/... - -; Initialize SystemVerilog enums using the base type's default value -; instead of the leftmost value. -; EnumBaseInit = 1 - -[lmc] -; The simulator's interface to Logic Modeling's SmartModel SWIFT software -libsm = $MODEL_TECH/libsm.sl -; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) -; libsm = $MODEL_TECH/libsm.dll -; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) -; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl -; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) -; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o -; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) -; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so -; Logic Modeling's SmartModel SWIFT software (Windows NT) -; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll -; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) -; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so -; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) -; libswift = $LMC_HOME/lib/linux.lib/libswift.so - -; The simulator's interface to Logic Modeling's hardware modeler SFI software -libhm = $MODEL_TECH/libhm.sl -; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) -; libhm = $MODEL_TECH/libhm.dll -; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) -; libsfi = /lib/hp700/libsfi.sl -; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) -; libsfi = /lib/rs6000/libsfi.a -; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) -; libsfi = /lib/sun4.solaris/libsfi.so -; Logic Modeling's hardware modeler SFI software (Windows NT) -; libsfi = /lib/pcnt/lm_sfi.dll -; Logic Modeling's hardware modeler SFI software (Linux) -; libsfi = /lib/linux/libsfi.so - -[msg_system] -; Change a message severity or suppress a message. -; The format is: = [,...] -; suppress can be used to achieve +nowarn functionality -; The format is: suppress = ,,[,,...] -; Examples: -suppress = 8780 -; note = 3009 -; warning = 3033 -; error = 3010,3016 -; fatal = 3016,3033 -; suppress = 3009,3016,3043 -; suppress = 3009,CNNODP,3043,TFMPC -; suppress = 8683,8684 -; The command verror can be used to get the complete -; description of a message. - -; Control transcripting of Verilog display system task messages and -; PLI/FLI print function call messages. The system tasks include -; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They -; also include the analogous file I/O tasks that write to STDOUT -; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, -; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default -; is to have messages appear only in the transcript. The other -; settings are to send messages to the wlf file only (messages that -; are recorded in the wlf file can be viewed in the MsgViewer) or -; to both the transcript and the wlf file. The valid values are -; tran {transcript only (default)} -; wlf {wlf file only} -; both {transcript and wlf file} -; displaymsgmode = tran - -; Control transcripting of elaboration/runtime messages not -; addressed by the displaymsgmode setting. The default is to -; have messages appear in the transcript and recorded in the wlf -; file (messages that are recorded in the wlf file can be viewed -; in the MsgViewer). The other settings are to send messages -; only to the transcript or only to the wlf file. The valid -; values are -; both {default} -; tran {transcript only} -; wlf {wlf file only} -; msgmode = both -[Project] -; Warning -- Do not edit the project properties directly. -; Property names are dynamic in nature and property -; values have special syntax. Changing property data directly -; can result in a corrupt MPF file. All project properties -; can be modified through project window dialogs. -Project_Version = 6 -Project_DefaultLib = work -Project_SortMethod = unused -Project_Files_Count = 33 -Project_File_0 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/mathhelpers.vhd -Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363372165 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 20 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_1 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_tdo_sample.vhd -Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 17 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_2 = /local/bneumann/vhdl/jtag_proj/NEW/trbnet/trb_net_components.vhd -Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363358600 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 27 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_3 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2.vhd -Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1364208502 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 25 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_4 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_tdo_compare_counttotal_noram_m10.vhd -Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363972805 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 15 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_5 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_tdo_compare_count_m10.vhd -Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_6 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_tck_out_component.vhd -Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 13 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_7 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_pulses.vhd -Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_8 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/tb/jtag_tap_mi26_hard.vhd -Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1364208958 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 31 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_9 = /local/bneumann/vhdl/jtag_proj/NEW/trb3/mvdjtag/version.vhd -Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363972809 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 29 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_10 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_constants.vhd -Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_11 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_tdo_data_to_ram_m10.vhd -Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 16 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_12 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/ram_dp.vhd -Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 21 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_13 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_bypassreg_testchain_m10.vhd -Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_14 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_delay_expected_values.vhd -Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_15 = /local/bneumann/vhdl/jtag_proj/NEW/trbnet/trb_net_std.vhd -Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363358600 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 28 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_16 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_write_m10.vhd -Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363371102 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 19 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_17 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_mux_buffer_tms_tdi_out_and_metainfo.vhd -Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363798313 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_18 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_read_m26devid_m10.vhd -Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_19 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/ram_mux2to1_writeport.vhd -Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 23 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_20 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/tb/jtag_cmd_m26c_test_regvaluesfrominput2_test.vhd -Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363801035 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 26 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_21 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/blank_ram.vhd -Project_File_P_21 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_22 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_update_error_counts_ram3a.vhd -Project_File_P_22 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 18 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_23 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/ram_mux2to1_readport.vhd -Project_File_P_23 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 22 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_24 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_cmd_m26c.vhd -Project_File_P_24 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363970246 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_25 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_misc.vhd -Project_File_P_25 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_26 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/ram_mux4to1_readport.vhd -Project_File_P_26 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 24 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_27 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/copy_ram.vhd -Project_File_P_27 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_28 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_check_crc_ram1a.vhd -Project_File_P_28 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_29 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/jtag_init_ram1b.vhd -Project_File_P_29 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_30 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/tb/jtag_simulation_constants.vhd -Project_File_P_30 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363801664 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 30 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_31 = /local/bneumann/vhdl/jtag_proj/NEW/jtag_mvd/vhdl/code/crc_32.vhd -Project_File_P_31 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1362136123 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_32 = /local/bneumann/vhdl/jtag_proj/NEW/trbnet/trb_net16_regio_bus_handler.vhd -Project_File_P_32 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1363358598 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 32 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_Sim_Count = 0 -Project_Folder_Count = 0 -Echo_Compile_Output = 0 -Save_Compile_Report = 1 -Project_Opt_Count = 0 -ForceSoftPaths = 0 -ProjectStatusDelay = 5000 -VERILOG_DoubleClick = Edit -VERILOG_CustomDoubleClick = -SYSTEMVERILOG_DoubleClick = Edit -SYSTEMVERILOG_CustomDoubleClick = -VHDL_DoubleClick = Edit -VHDL_CustomDoubleClick = -PSL_DoubleClick = Edit -PSL_CustomDoubleClick = -TEXT_DoubleClick = Edit -TEXT_CustomDoubleClick = -SYSTEMC_DoubleClick = Edit -SYSTEMC_CustomDoubleClick = -TCL_DoubleClick = Edit -TCL_CustomDoubleClick = -MACRO_DoubleClick = Edit -MACRO_CustomDoubleClick = -VCD_DoubleClick = Edit -VCD_CustomDoubleClick = -SDF_DoubleClick = Edit -SDF_CustomDoubleClick = -XML_DoubleClick = Edit -XML_CustomDoubleClick = -LOGFILE_DoubleClick = Edit -LOGFILE_CustomDoubleClick = -UCDB_DoubleClick = Edit -UCDB_CustomDoubleClick = -UPF_DoubleClick = Edit -UPF_CustomDoubleClick = -PCF_DoubleClick = Edit -PCF_CustomDoubleClick = -PROJECT_DoubleClick = Edit -PROJECT_CustomDoubleClick = -Project_Major_Version = 10 -Project_Minor_Version = 0 diff --git a/vhdl/trb3_periph_mvdjtag.p2t b/vhdl/trb3_periph_mvdjtag.p2t deleted file mode 100644 index de1c3be..0000000 --- a/vhdl/trb3_periph_mvdjtag.p2t +++ /dev/null @@ -1,20 +0,0 @@ --w --i 15 --l 5 --n 1 --y --s 12 --t 10 --c 1 --e 2 --m nodelist.txt -# -w -# -i 6 -# -l 5 -# -n 1 -# -t 1 -# -s 1 -# -c 0 -# -e 0 -# --exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1: diff --git a/vhdl/trb3_periph_mvdjtag.p3t b/vhdl/trb3_periph_mvdjtag.p3t deleted file mode 100644 index 8d41a22..0000000 --- a/vhdl/trb3_periph_mvdjtag.p3t +++ /dev/null @@ -1,5 +0,0 @@ --rem --distrce --log "trb3_periph_mvdjtag.log" --o "trb3_periph_mvdjtag.csv" --pr "trb3_periph_mvdjtag.prf" diff --git a/vhdl/trb3_periph_mvdjtag.prj b/vhdl/trb3_periph_mvdjtag.prj deleted file mode 100644 index 2cbbf37..0000000 --- a/vhdl/trb3_periph_mvdjtag.prj +++ /dev/null @@ -1,174 +0,0 @@ - -# implementation: "workdir" -impl -add workdir -type fpga - -# device options -set_option -technology LATTICE-ECP3 -set_option -part LFE3_150EA -set_option -package FN672C -set_option -speed_grade -8 -set_option -part_companion "" - -# compilation/mapping options -set_option -default_enum_encoding sequential -set_option -symbolic_fsm_compiler 1 -set_option -top_module "trb3_periph_mvdjtag" -set_option -resource_sharing true - -# map options -set_option -frequency 200 -set_option -fanout_limit 100 -set_option -disable_io_insertion 0 -set_option -retiming 0 -set_option -pipe 0 -#set_option -force_gsr -set_option -force_gsr false -set_option -fixgatedclocks false #3 -set_option -fixgeneratedclocks false #3 -set_option -compiler_compatible true - - -# simulation options -set_option -write_verilog 0 -set_option -write_vhdl 1 - -# automatic place and route (vendor) options -set_option -write_apr_constraint 0 - -# set result format/file last -project -result_format "edif" -project -result_file "workdir/trb3_periph_mvdjtag.edf" - -#implementation attributes - -set_option -vlog_std v2001 -set_option -project_relative_includes 1 -impl -active "workdir" - -#################### - - - -#add_file options - -add_file -vhdl -lib work "version.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" -add_file -vhdl -lib "work" "../../trb3/base/trb3_components.vhd" - -add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" -add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" -add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" -add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" -add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" -add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" -add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" -add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" -add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" -add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" -add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" - -add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" -add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" -add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" -add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" -add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd" -add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" - -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" - -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" - -add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" -add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" -add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" -add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" - -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" - -add_file -vhdl -lib "work" "../../trb3/base/cores/pll_in200_out100.vhd" -add_file -vhdl -lib "work" "../../trb3/base/cores/pll_in100_out80.vhd" -add_file -vhdl -lib "work" "../../trb3/base/cores/oddr.vhd" - -add_file -vhdl -lib "work" "code/jtag_constants.vhd" -add_file -vhdl -lib "work" "code/jtag_misc.vhd" -add_file -vhdl -lib "work" "code/mathhelpers.vhd" -add_file -vhdl -lib "work" "code/jtag_mvd.vhd" -add_file -vhdl -lib "work" "code/jtag_cmd_m26c.vhd" - -add_file -vhdl -lib "work" "code/blank_ram.vhd" -add_file -vhdl -lib "work" "code/copy_ram.vhd" -add_file -vhdl -lib "work" "code/crc_32.vhd" -add_file -vhdl -lib "work" "code/jtag_bypassreg_testchain_m10.vhd" -add_file -vhdl -lib "work" "code/jtag_check_crc_ram1a.vhd" -add_file -vhdl -lib "work" "code/jtag_delay_expected_values.vhd" -add_file -vhdl -lib "work" "code/jtag_init_ram1b.vhd" -add_file -vhdl -lib "work" "code/jtag_mux_buffer_tms_tdi_out_and_metainfo.vhd" -add_file -vhdl -lib "work" "code/jtag_pulses.vhd" -add_file -vhdl -lib "work" "code/jtag_read_m26devid_m10.vhd" -add_file -vhdl -lib "work" "code/jtag_tck_out_component.vhd" -add_file -vhdl -lib "work" "code/jtag_tdo_compare_count_m10.vhd" -add_file -vhdl -lib "work" "code/jtag_tdo_compare_counttotal_noram_m10.vhd" -add_file -vhdl -lib "work" "code/jtag_tdo_data_to_ram_m10.vhd" -add_file -vhdl -lib "work" "code/jtag_tdo_sample.vhd" -add_file -vhdl -lib "work" "code/jtag_update_error_counts_ram3a.vhd" -add_file -vhdl -lib "work" "code/jtag_write_m10.vhd" -add_file -vhdl -lib "work" "code/ram_mux2to1_readport.vhd" -add_file -vhdl -lib "work" "code/ram_mux2to1_writeport.vhd" -add_file -vhdl -lib "work" "code/ram_mux4to1_readport.vhd" - - - - -add_file -vhdl -lib "work" "trb3_periph_mvdjtag.vhd" - diff --git a/vhdl/trb3_periph_mvdjtag.pt b/vhdl/trb3_periph_mvdjtag.pt deleted file mode 100644 index b5319a3..0000000 --- a/vhdl/trb3_periph_mvdjtag.pt +++ /dev/null @@ -1,10 +0,0 @@ --v -10 - - - - --gt --sethld --sp 8 --sphld m diff --git a/vhdl/trb3_periph_mvdjtag.vhd b/vhdl/trb3_periph_mvdjtag.vhd deleted file mode 100644 index bd4630c..0000000 --- a/vhdl/trb3_periph_mvdjtag.vhd +++ /dev/null @@ -1,653 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; -use work.version.all; -use work.jtag_constants.all; - - ---Connector pinout, INP_n is the number of wire pair --- LOCATE COMP "MAPS_CLK_OUT_0" #9 INP_2 --- LOCATE COMP "MAPS_START_OUT_0" #17 INP_4 --- LOCATE COMP "MAPS_RESET_OUT_0" #21 INP_5 --- LOCATE COMP "JTAG_TCK_OUT_0" #29 INP_7 --- LOCATE COMP "JTAG_TMS_OUT_0" #41 INP_10 --- LOCATE COMP "JTAG_TDI_OUT_0" #45 INP_11 --- LOCATE COMP "JTAG_TDO_IN_0" #33 INP_8 - - - -entity trb3_periph_mvdjtag is - generic( - NUM_CHAINS : integer := 1; - SYNC_MODE : integer range 0 to 1 := c_NO --use the RX clock for internal logic and transmission. - ); - port( - --Clocks - CLK_GPLL_LEFT : in std_logic; --Clock Manager 6 - CLK_GPLL_RIGHT : in std_logic; --Clock Manager 4 <-- MAIN CLOCK for FPGA - CLK_PCLK_LEFT : in std_logic; --Clock Manager 3 - CLK_PCLK_RIGHT : in std_logic; --Clock Manager 1 - --CLK_PCLK_RIGHT is the only clock with external termination !? - CLK_EXTERNAL : in std_logic; --Clock Manager 9 - - --Trigger - TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out - TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out - - --Serdes - CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 0, not used - SERDES_TX : out std_logic_vector(3 downto 2); - SERDES_RX : in std_logic_vector(3 downto 2); - - FPGA5_COMM : inout std_logic_vector(11 downto 0); - --Bit 0/1 input, serial link RX active - --Bit 2/3 output, serial link TX active - - --Connections - MAPS_CLK_OUT : out std_logic_vector(NUM_CHAINS-1 downto 0); - MAPS_START_OUT : out std_logic_vector(NUM_CHAINS-1 downto 0); - MAPS_RESET_OUT : out std_logic_vector(NUM_CHAINS-1 downto 0); - JTAG_TCK_OUT : out std_logic_vector(NUM_CHAINS-1 downto 0); - JTAG_TMS_OUT : out std_logic_vector(NUM_CHAINS-1 downto 0); - JTAG_TDI_OUT : out std_logic_vector(NUM_CHAINS-1 downto 0); - JTAG_TDO_IN : in std_logic_vector(NUM_CHAINS-1 downto 0); - - --Flash ROM & Reboot - FLASH_CLK : out std_logic; - FLASH_CS : out std_logic; - FLASH_DIN : out std_logic; - FLASH_DOUT : in std_logic; - PROGRAMN : out std_logic; --reboot FPGA - - --Misc - TEMPSENS : inout std_logic; --Temperature Sensor - CODE_LINE : in std_logic_vector(1 downto 0); - LED_GREEN : out std_logic; - LED_ORANGE : out std_logic; - LED_RED : out std_logic; - LED_YELLOW : out std_logic; - - --Test Connectors - TEST_LINE : out std_logic_vector(15 downto 0) - ); - - - attribute syn_useioff : boolean; - --no IO-FF for LEDs relaxes timing constraints - attribute syn_useioff of LED_GREEN : signal is false; - attribute syn_useioff of LED_ORANGE : signal is false; - attribute syn_useioff of LED_RED : signal is false; - attribute syn_useioff of LED_YELLOW : signal is false; - attribute syn_useioff of TEMPSENS : signal is false; - attribute syn_useioff of PROGRAMN : signal is false; - - --important signals _with_ IO-FF - attribute syn_useioff of FLASH_CLK : signal is true; - attribute syn_useioff of FLASH_CS : signal is true; - attribute syn_useioff of FLASH_DIN : signal is true; - attribute syn_useioff of FLASH_DOUT : signal is true; - attribute syn_useioff of TEST_LINE : signal is true; - attribute syn_useioff of JTAG_TCK_OUT : signal is true; - attribute syn_useioff of JTAG_TDI_OUT : signal is true; - attribute syn_useioff of JTAG_TMS_OUT : signal is true; - attribute syn_useioff of JTAG_TDO_IN : signal is true; - - -end entity; - -architecture trb3_periph_mvdjtag_arch of trb3_periph_mvdjtag is - --Constants - constant REGIO_NUM_STAT_REGS : integer := 4; - constant REGIO_NUM_CTRL_REGS : integer := 2; - - attribute syn_keep : boolean; - attribute syn_preserve : boolean; - - --Clock / Reset - signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL - signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL - signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. - signal clear_i : std_logic; - signal reset_i : std_logic; - signal GSR_N : std_logic; - attribute syn_keep of GSR_N : signal is true; - attribute syn_preserve of GSR_N : signal is true; - signal clk_100_internal : std_logic; - signal clk_200_internal : std_logic; - signal rx_clock_100 : std_logic; - signal rx_clock_200 : std_logic; --- signal clk_tdc : std_logic; - signal time_counter, time_counter2 : unsigned(31 downto 0); - --Media Interface - signal med_stat_op : std_logic_vector (1*16-1 downto 0); - signal med_ctrl_op : std_logic_vector (1*16-1 downto 0); - signal med_stat_debug : std_logic_vector (1*64-1 downto 0); - signal med_ctrl_debug : std_logic_vector (1*64-1 downto 0); - signal med_data_out : std_logic_vector (1*16-1 downto 0); - signal med_packet_num_out : std_logic_vector (1*3-1 downto 0); - signal med_dataready_out : std_logic; - signal med_read_out : std_logic; - signal med_data_in : std_logic_vector (1*16-1 downto 0); - signal med_packet_num_in : std_logic_vector (1*3-1 downto 0); - signal med_dataready_in : std_logic; - signal med_read_in : std_logic; - - --Slow Control channel - signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); - signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0) := (others => '0'); - signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0) := (others => '0'); - signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0) := (others => '0'); - signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); - signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); - signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0); - signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0); - - --RegIO - signal my_address : std_logic_vector (15 downto 0); - signal regio_addr_out : std_logic_vector (15 downto 0); - signal regio_read_enable_out : std_logic; - signal regio_write_enable_out : std_logic; - signal regio_data_out : std_logic_vector (31 downto 0); - signal regio_data_in : std_logic_vector (31 downto 0); - signal regio_dataready_in : std_logic; - signal regio_no_more_data_in : std_logic; - signal regio_write_ack_in : std_logic; - signal regio_unknown_addr_in : std_logic; - signal regio_timeout_out : std_logic; - - --Timer - signal global_time : std_logic_vector(31 downto 0); - signal local_time : std_logic_vector(7 downto 0); - signal time_since_last_trg : std_logic_vector(31 downto 0); - signal timer_ticks : std_logic_vector(1 downto 0); - - --Flash - signal spictrl_read_en : std_logic; - signal spictrl_write_en : std_logic; - signal spictrl_data_in : std_logic_vector(31 downto 0); - signal spictrl_addr : std_logic; - signal spictrl_data_out : std_logic_vector(31 downto 0); - signal spictrl_ack : std_logic; - signal spictrl_busy : std_logic; - signal spimem_read_en : std_logic; - signal spimem_write_en : std_logic; - signal spimem_data_in : std_logic_vector(31 downto 0); - signal spimem_addr : std_logic_vector(5 downto 0); - signal spimem_data_out : std_logic_vector(31 downto 0); - signal spimem_ack : std_logic; - - signal spi_bram_addr : std_logic_vector(7 downto 0); - signal spi_bram_wr_d : std_logic_vector(7 downto 0); - signal spi_bram_rd_d : std_logic_vector(7 downto 0); - signal spi_bram_we : std_logic; - - --Serdes registers - signal sci1_ack : std_logic; - signal sci1_write : std_logic; - signal sci1_read : std_logic; - signal sci1_data_in : std_logic_vector(7 downto 0); - signal sci1_data_out : std_logic_vector(7 downto 0); - signal sci1_addr : std_logic_vector(8 downto 0); - - -- JTAG_CMD_M26C connection signals - signal jtag_addr_in : std_logic_vector(12 downto 0); - signal jtag_data_in : std_logic_vector(31 downto 0); - signal jtag_read_enable_in : std_logic; - signal jtag_write_enable_in : std_logic; - signal jtag_data_out : std_logic_vector(31 downto 0); - signal jtag_dataready_out : std_logic; - signal jtag_write_ack_out : std_logic; - signal jtag_no_more_data_out : std_logic; - signal jtag_unknown_addr_out : std_logic; - - signal jtag_status : std_logic_vector(256*NUM_CHAINS-1 downto 0); - signal jtag_tck : std_logic_vector(NUM_CHAINS-1 downto 0); - signal jtag_tms : std_logic_vector(NUM_CHAINS-1 downto 0); - signal jtag_tdi : std_logic_vector(NUM_CHAINS-1 downto 0); - signal jtag_tdo : std_logic_vector(NUM_CHAINS-1 downto 0); - signal maps_clk : std_logic_vector(NUM_CHAINS-1 downto 0); - signal maps_start : std_logic_vector(NUM_CHAINS-1 downto 0); - signal maps_reset : std_logic_vector(NUM_CHAINS-1 downto 0); - - - - -begin ---------------------------------------------------------------------------- --- Reset Generation ---------------------------------------------------------------------------- - - GSR_N <= pll_lock; - - THE_RESET_HANDLER : trb_net_reset_handler - generic map( - RESET_DELAY => x"FEEE" - ) - port map( - CLEAR_IN => '0', -- reset input (high active, async) - CLEAR_N_IN => '1', -- reset input (low active, async) - CLK_IN => clk_200_internal, -- raw master clock, NOT from PLL/DLL! - SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock - PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) - RESET_IN => '0', -- general reset signal (SYSCLK) - TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) - CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! - RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) - DEBUG_OUT => open - ); - - ---------------------------------------------------------------------------- --- Clock Handling ---------------------------------------------------------------------------- - - THE_MAIN_PLL : pll_in200_out100 - port map( - CLK => CLK_PCLK_LEFT, - CLKOP => clk_100_internal, - CLKOK => clk_200_internal, - LOCK => pll_lock - ); - - gen_sync_clocks : if SYNC_MODE = c_YES generate - clk_100_i <= rx_clock_100; - clk_200_i <= rx_clock_200; --- clk_tdc <= rx_clock_200; - end generate; - - gen_local_clocks : if SYNC_MODE = c_NO generate - clk_100_i <= clk_100_internal; - clk_200_i <= clk_200_internal; --- clk_tdc <= CLK_PCLK_LEFT; - end generate; - ---------------------------------------------------------------------------- --- The TrbNet media interface (to other FPGA) ---------------------------------------------------------------------------- - THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp - generic map( - SERDES_NUM => 1, --number of serdes in quad - EXT_CLOCK => c_NO, --use internal clock - USE_200_MHZ => c_YES, --run on 200 MHz clock - USE_CTC => c_NO, - USE_SLAVE => SYNC_MODE - ) - port map( - CLK => clk_200_internal, - SYSCLK => clk_100_i, - RESET => reset_i, - CLEAR => clear_i, - CLK_EN => '1', - --Internal Connection - MED_DATA_IN => med_data_out, - MED_PACKET_NUM_IN => med_packet_num_out, - MED_DATAREADY_IN => med_dataready_out, - MED_READ_OUT => med_read_in, - MED_DATA_OUT => med_data_in, - MED_PACKET_NUM_OUT => med_packet_num_in, - MED_DATAREADY_OUT => med_dataready_in, - MED_READ_IN => med_read_out, - REFCLK2CORE_OUT => open, - CLK_RX_HALF_OUT => rx_clock_100, - CLK_RX_FULL_OUT => rx_clock_200, - - --SFP Connection - SD_RXD_P_IN => SERDES_RX(2), - SD_RXD_N_IN => SERDES_RX(3), - SD_TXD_P_OUT => SERDES_TX(2), - SD_TXD_N_OUT => SERDES_TX(3), - SD_REFCLK_P_IN => open, - SD_REFCLK_N_IN => open, - SD_PRSNT_N_IN => FPGA5_COMM(0), - SD_LOS_IN => FPGA5_COMM(0), - SD_TXDIS_OUT => FPGA5_COMM(2), - - SCI_DATA_IN => sci1_data_in, - SCI_DATA_OUT => sci1_data_out, - SCI_ADDR => sci1_addr, - SCI_READ => sci1_read, - SCI_WRITE => sci1_write, - SCI_ACK => sci1_ack, - -- Status and control port - STAT_OP => med_stat_op, - CTRL_OP => med_ctrl_op, - STAT_DEBUG => med_stat_debug, - CTRL_DEBUG => (others => '0') - ); - - ---------------------------------------------------------------------------- --- Endpoint ---------------------------------------------------------------------------- - THE_ENDPOINT : trb_net16_endpoint_hades_full_handler - generic map( - REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg - REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg - ADDRESS_MASK => x"FFFF", - BROADCAST_BITMASK => x"FF", - BROADCAST_SPECIAL_ADDR => x"45", - REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), - REGIO_HARDWARE_VERSION => x"91000000", - REGIO_INIT_ADDRESS => x"f308", - REGIO_USE_VAR_ENDPOINT_ID => c_YES, - CLOCK_FREQUENCY => 100, - TIMING_TRIGGER_RAW => c_YES, - --Configure data handler - DATA_INTERFACE_NUMBER => 1, - DATA_BUFFER_DEPTH => 9, --13 - DATA_BUFFER_WIDTH => 32, - DATA_BUFFER_FULL_THRESH => 2**9-100, - TRG_RELEASE_AFTER_DATA => c_YES, - HEADER_BUFFER_DEPTH => 9, - HEADER_BUFFER_FULL_THRESH => 2**9-16 - ) - port map( - CLK => clk_100_i, - RESET => reset_i, - CLK_EN => '1', - MED_DATAREADY_OUT => med_dataready_out, - MED_DATA_OUT => med_data_out, - MED_PACKET_NUM_OUT => med_packet_num_out, - MED_READ_IN => med_read_in, - MED_DATAREADY_IN => med_dataready_in, - MED_DATA_IN => med_data_in, - MED_PACKET_NUM_IN => med_packet_num_in, - MED_READ_OUT => med_read_out, - MED_STAT_OP_IN => med_stat_op, - MED_CTRL_OP_OUT => med_ctrl_op, - - --Timing trigger in - TRG_TIMING_TRG_RECEIVED_IN => '0', - --LVL1 trigger to FEE - LVL1_TRG_DATA_VALID_OUT => open, - LVL1_VALID_TIMING_TRG_OUT => open, - LVL1_VALID_NOTIMING_TRG_OUT => open, - LVL1_INVALID_TRG_OUT => open, - - LVL1_TRG_TYPE_OUT => open, - LVL1_TRG_NUMBER_OUT => open, - LVL1_TRG_CODE_OUT => open, - LVL1_TRG_INFORMATION_OUT => open, - LVL1_INT_TRG_NUMBER_OUT => open, - - --Information about trigger handler errors - TRG_MULTIPLE_TRG_OUT => open, - TRG_TIMEOUT_DETECTED_OUT => open, - TRG_SPURIOUS_TRG_OUT => open, - TRG_MISSING_TMG_TRG_OUT => open, - TRG_SPIKE_DETECTED_OUT => open, - - --Response from FEE - FEE_TRG_RELEASE_IN(0) => '1', - FEE_TRG_STATUSBITS_IN => x"00000000", - FEE_DATA_IN => x"00000000", - FEE_DATA_WRITE_IN(0) => '0', - FEE_DATA_FINISHED_IN(0) => '1', - FEE_DATA_ALMOST_FULL_OUT(0) => open, - - -- Slow Control Data Port - REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 - REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 - REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe, - REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe, - REGIO_STAT_REG_IN => stat_reg, --start 0x80 - REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0 - REGIO_STAT_STROBE_OUT => stat_reg_strobe, - REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe, - REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE, - REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'), - - BUS_ADDR_OUT => regio_addr_out, - BUS_READ_ENABLE_OUT => regio_read_enable_out, - BUS_WRITE_ENABLE_OUT => regio_write_enable_out, - BUS_DATA_OUT => regio_data_out, - BUS_DATA_IN => regio_data_in, - BUS_DATAREADY_IN => regio_dataready_in, - BUS_NO_MORE_DATA_IN => regio_no_more_data_in, - BUS_WRITE_ACK_IN => regio_write_ack_in, - BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in, - BUS_TIMEOUT_OUT => regio_timeout_out, - ONEWIRE_INOUT => TEMPSENS, - ONEWIRE_MONITOR_OUT => open, - - TIME_GLOBAL_OUT => global_time, - TIME_LOCAL_OUT => local_time, - TIME_SINCE_LAST_TRG_OUT => time_since_last_trg, - TIME_TICKS_OUT => timer_ticks, - - STAT_DEBUG_IPU => open, - STAT_DEBUG_1 => open, - STAT_DEBUG_2 => open, - STAT_DEBUG_DATA_HANDLER_OUT => open, - STAT_DEBUG_IPU_HANDLER_OUT => open, - STAT_TRIGGER_OUT => open, - CTRL_MPLEX => (others => '0'), - IOBUF_CTRL_GEN => (others => '0'), - STAT_ONEWIRE => open, - STAT_ADDR_DEBUG => open, - DEBUG_LVL1_HANDLER_OUT => open - ); - - ---------------------------------------------------------------------------- --- Bus Handler ---------------------------------------------------------------------------- - THE_BUS_HANDLER : trb_net16_regio_bus_handler - generic map( - PORT_NUMBER => 4, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"e000", 3 => x"a000", others => x"0000"), - PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 9, 3 => 13, others => 0) - ) - port map( - CLK => clk_100_i, - RESET => reset_i, - - DAT_ADDR_IN => regio_addr_out, - DAT_DATA_IN => regio_data_out, - DAT_DATA_OUT => regio_data_in, - DAT_READ_ENABLE_IN => regio_read_enable_out, - DAT_WRITE_ENABLE_IN => regio_write_enable_out, - DAT_TIMEOUT_IN => regio_timeout_out, - DAT_DATAREADY_OUT => regio_dataready_in, - DAT_WRITE_ACK_OUT => regio_write_ack_in, - DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, - DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, - - --Bus Handler (SPI CTRL) - BUS_READ_ENABLE_OUT(0) => spictrl_read_en, - BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en, - BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in, - BUS_ADDR_OUT(0*16) => spictrl_addr, - BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open, - BUS_TIMEOUT_OUT(0) => open, - BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out, - BUS_DATAREADY_IN(0) => spictrl_ack, - BUS_WRITE_ACK_IN(0) => spictrl_ack, - BUS_NO_MORE_DATA_IN(0) => spictrl_busy, - BUS_UNKNOWN_ADDR_IN(0) => '0', - --Bus Handler (SPI Memory) - BUS_READ_ENABLE_OUT(1) => spimem_read_en, - BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, - BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in, - BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr, - BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open, - BUS_TIMEOUT_OUT(1) => open, - BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out, - BUS_DATAREADY_IN(1) => spimem_ack, - BUS_WRITE_ACK_IN(1) => spimem_ack, - BUS_NO_MORE_DATA_IN(1) => '0', - BUS_UNKNOWN_ADDR_IN(1) => '0', - - --SCI first Media Interface - BUS_READ_ENABLE_OUT(2) => sci1_read, - BUS_WRITE_ENABLE_OUT(2) => sci1_write, - BUS_DATA_OUT(2*32+7 downto 2*32) => sci1_data_in, - BUS_DATA_OUT(2*32+31 downto 2*32+8) => open, - BUS_ADDR_OUT(2*16+8 downto 2*16) => sci1_addr, - BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open, - BUS_TIMEOUT_OUT(2) => open, - BUS_DATA_IN(2*32+7 downto 2*32) => sci1_data_out, - BUS_DATA_IN(2*32+31 downto 2*32+8) => (others => '0'), - BUS_DATAREADY_IN(2) => sci1_ack, - BUS_WRITE_ACK_IN(2) => sci1_ack, - BUS_NO_MORE_DATA_IN(2) => '0', - BUS_UNKNOWN_ADDR_IN(2) => '0', - - --First JTAG Chain - BUS_ADDR_OUT(3*16+12 downto 3*16) => jtag_addr_in, - BUS_ADDR_OUT(3*16+15 downto 3*16+13) => open, - BUS_DATA_OUT(3*32+31 downto 3*32) => jtag_data_in, - BUS_READ_ENABLE_OUT(3) => jtag_read_enable_in, - BUS_WRITE_ENABLE_OUT(3) => jtag_write_enable_in, - BUS_TIMEOUT_OUT(3) => open, - BUS_DATA_IN(3*32+31 downto 3*32) => jtag_data_out, - BUS_DATAREADY_IN(3) => jtag_dataready_out, - BUS_WRITE_ACK_IN(3) => jtag_write_ack_out, - BUS_NO_MORE_DATA_IN(3) => jtag_no_more_data_out, - BUS_UNKNOWN_ADDR_IN(3) => jtag_unknown_addr_out, - - STAT_DEBUG => open - ); - ---------------------------------------------------------------------------- --- SPI / Flash ---------------------------------------------------------------------------- - - THE_SPI_MASTER : spi_master - port map( - CLK_IN => clk_100_i, - RESET_IN => reset_i, - -- Slave bus - BUS_READ_IN => spictrl_read_en, - BUS_WRITE_IN => spictrl_write_en, - BUS_BUSY_OUT => spictrl_busy, - BUS_ACK_OUT => spictrl_ack, - BUS_ADDR_IN(0) => spictrl_addr, - BUS_DATA_IN => spictrl_data_in, - BUS_DATA_OUT => spictrl_data_out, - -- SPI connections - SPI_CS_OUT => FLASH_CS, - SPI_SDI_IN => FLASH_DOUT, - SPI_SDO_OUT => FLASH_DIN, - SPI_SCK_OUT => FLASH_CLK, - -- BRAM for read/write data - BRAM_A_OUT => spi_bram_addr, - BRAM_WR_D_IN => spi_bram_wr_d, - BRAM_RD_D_OUT => spi_bram_rd_d, - BRAM_WE_OUT => spi_bram_we, - -- Status lines - STAT => open - ); - --- data memory for SPI accesses - THE_SPI_MEMORY : spi_databus_memory - port map( - CLK_IN => clk_100_i, - RESET_IN => reset_i, - -- Slave bus - BUS_ADDR_IN => spimem_addr, - BUS_READ_IN => spimem_read_en, - BUS_WRITE_IN => spimem_write_en, - BUS_ACK_OUT => spimem_ack, - BUS_DATA_IN => spimem_data_in, - BUS_DATA_OUT => spimem_data_out, - -- state machine connections - BRAM_ADDR_IN => spi_bram_addr, - BRAM_WR_D_OUT => spi_bram_wr_d, - BRAM_RD_D_IN => spi_bram_rd_d, - BRAM_WE_IN => spi_bram_we, - -- Status lines - STAT => open - ); - ---------------------------------------------------------------------------- --- Reboot FPGA ---------------------------------------------------------------------------- - THE_FPGA_REBOOT : fpga_reboot - port map( - CLK => clk_100_i, - RESET => reset_i, - DO_REBOOT => common_ctrl_reg(15), - PROGRAMN => PROGRAMN - ); - - ---------------------------------------------------------------------------- --- JTAG Chain ---------------------------------------------------------------------------- -THE_JTAG : entity work.jtag_mvd - generic map( - NUM_CHAINS => NUM_CHAINS - ) - port map( - CLK_IN => clk_100_i, - CLK_MAPS_IN => CLK_PCLK_LEFT, - RESET => reset_i, - - MAPS_CLK_OUT => maps_clk, - MAPS_START_OUT => maps_start, - MAPS_RESET_OUT => maps_reset, - - JTAG_TDI_OUT => jtag_tdi, - JTAG_TMS_OUT => jtag_tms, - JTAG_TCK_OUT => jtag_tck, - JTAG_TDO_IN => jtag_tdo, - - BUS_DATA_IN => jtag_data_in, - BUS_DATA_OUT => jtag_data_out, - BUS_ADDR_IN => jtag_addr_in, - BUS_WRITE_IN => jtag_write_enable_in, - BUS_READ_IN => jtag_read_enable_in, - BUS_DATAREADY_OUT => jtag_dataready_out, - BUS_WRITE_ACK_OUT => jtag_write_ack_out, - BUS_NO_MORE_DATA_OUT => jtag_no_more_data_out, - BUS_UNKNOWN_OUT => jtag_unknown_addr_out, - - STATUS_OUT => jtag_status, - DEBUG_OUT => open - ); - - stat_reg(255 downto 0) <= (others => '0'); - stat_reg(511 downto 256) <= jtag_status; - ---------------------------------------------------------------------------- --- I/O connections ---------------------------------------------------------------------------- - JTAG_TDI_OUT <= jtag_tdi; - JTAG_TMS_OUT <= jtag_tms; - JTAG_TCK_OUT <= jtag_tck; - jtag_tdo <= JTAG_TDO_IN; - - MAPS_CLK_OUT <= maps_clk; - MAPS_START_OUT <= maps_start; - MAPS_RESET_OUT <= maps_reset; - ---------------------------------------------------------------------------- --- LED ---------------------------------------------------------------------------- - LED_ORANGE <= not reset_i when rising_edge(clk_100_internal); - LED_YELLOW <= '1'; - LED_GREEN <= not med_stat_op(9); - LED_RED <= not (med_stat_op(10) or med_stat_op(11)); - ---------------------------------------------------------------------------- --- Test Connector ---------------------------------------------------------------------------- --- TEST_LINE(15 downto 0) <= (others => '0'); ---------------------------------------------------------------------------- --- Test Circuits ---------------------------------------------------------------------------- - process - begin - wait until rising_edge(clk_100_internal); - time_counter <= time_counter + 1; - end process; - - - -end architecture; diff --git a/vhdl/trb3_periph_mvdjtag_constraints.lpf b/vhdl/trb3_periph_mvdjtag_constraints.lpf deleted file mode 100644 index 3ee6513..0000000 --- a/vhdl/trb3_periph_mvdjtag_constraints.lpf +++ /dev/null @@ -1,78 +0,0 @@ -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -BLOCK RD_DURING_WR_PATHS ; - - -################################################################# -# Basic Settings -################################################################# - FREQUENCY NET "clk_100_internal_c" 100.0 MHz; - FREQUENCY NET "clk_200_internal_c" 200.0 MHz; - - SYSCONFIG MCCLK_FREQ = 20; - - -################################################################# -# Reset Nets -################################################################# -GSR_NET NET "reset_i"; - -################################################################# -# Locate Serdes and media interfaces -################################################################# -LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; - -REGION "MEDIA_UPLINK" "R105C104D" 10 27; -REGION "REGION_SPI" "R4C121D" 15 18 DEVSIZE; - -LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; -LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; - -LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; - -#MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; -MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; -MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset*" 30 ns; -MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset_fas*" 20 ns; - - -#Jan: Placement of TrbNet components (at least, most of them) -REGION "REGION_TRBNET" "R38C104D" 67 27 DEVSIZE; -#UGROUP "TrbNet" BBOX 77 27 -# BLKNAME THE_ENDPOINT -# BLKNAME THE_ENDPOINT/THE_ENDPOINT -#LOCATE UGROUP "TrbNet" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_BUS_HANDLER/Bus_handler_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_2_gentermbuf_termbuf/TRMBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_INTERNAL_BUS_HANDLER/Bus_handler_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/MPLEX/MUX_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/HUBLOGIC_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/RegIO_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/API_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/API_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; - - -USE PRIMARY NET "CLK_PCLK_LEFT_c"; -MULTICYCLE FROM CELL "THE_JTAG/com_settings_all_signals_invert*" 30 ns; -MULTICYCLE FROM CELL "THE_JTAG/com_settings_all_signals_invert*" 30 ns; -MULTICYCLE FROM CELL "THE_JTAG/com_settings_all_waitbeforestart*" 30 ns; -MULTICYCLE FROM CELL "THE_JTAG/com_settings_all_resetbeforeinit*" 30 ns; -MULTICYCLE FROM CELL "THE_JTAG/com_settings_all_resetafterfirstwrite*" 30 ns; -MULTICYCLE FROM CELL "THE_JTAG/signals_invert*" 30 ns; -MULTICYCLE FROM CELL "THE_JTAG/signals_invert*" 30 ns; -MULTICYCLE FROM CELL "THE_JTAG/waitbeforestart*" 30 ns; -MULTICYCLE FROM CELL "THE_JTAG/resetbeforeinit*" 30 ns; -MULTICYCLE FROM CELL "THE_JTAG/resetafterfirstwrite*" 30 ns; -MULTICYCLE TO CELL "THE_JTAG/reset_i_mclk" 30 ns; -MULTICYCLE TO CELL "THE_JTAG/idle_out_mclk*" 30 ns; -MULTICYCLE TO CELL "THE_JTAG/*ps*/sync_q" 30 ns; - -- 2.43.0