From 3264c8ce1f6d3ce30eb7f8757f9fc5084ee43062 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Fri, 15 Feb 2008 16:12:47 +0000 Subject: [PATCH] *** empty log message *** --- trb_net16_api_base.vhd | 385 +++---- trb_net16_endpoint_0_trg_1_api.vhd | 10 +- trb_net16_ibuf.vhd | 36 +- trb_net16_io_multiplexer.vhd | 51 +- trb_net16_iobuf.vhd | 6 +- trb_net16_med_tlk.vhd | 81 +- trb_net16_obuf.vhd | 4 +- trb_net_pattern_gen.vhd | 29 +- trb_net_priority_arbiter.vhd | 2 +- trb_net_priority_encoder.vhd | 26 +- trb_net_std.vhd | 19 + .../trb_net_fifo_16bit_bram_dualport_arch.vhd | 994 +++++++++--------- .../virtex2/simulation/xilinx_fifo_18x16.vhd | 136 +++ .../virtex2/simulation/xilinx_fifo_18x1k.vhd | 136 +++ .../virtex2/simulation/xilinx_fifo_18x32.vhd | 136 +++ .../virtex2/simulation/xilinx_fifo_18x64.vhd | 136 +++ .../simulation/xilinx_fifo_dualport_18x1k.vhd | 139 +++ xilinx/virtex2/xilinx_fifo_dualport_18x1k.xco | 64 ++ .../virtex4/simulation/xilinx_fifo_18x16.vhd | 105 ++ .../virtex4/simulation/xilinx_fifo_18x1k.vhd | 108 ++ .../virtex4/simulation/xilinx_fifo_18x32.vhd | 105 ++ .../virtex4/simulation/xilinx_fifo_18x64.vhd | 105 ++ xilinx/virtex4/xilinx_fifo_dualport_18x1k.xco | 64 ++ 23 files changed, 2040 insertions(+), 837 deletions(-) create mode 100644 xilinx/virtex2/simulation/xilinx_fifo_18x16.vhd create mode 100644 xilinx/virtex2/simulation/xilinx_fifo_18x1k.vhd create mode 100644 xilinx/virtex2/simulation/xilinx_fifo_18x32.vhd create mode 100644 xilinx/virtex2/simulation/xilinx_fifo_18x64.vhd create mode 100644 xilinx/virtex2/simulation/xilinx_fifo_dualport_18x1k.vhd create mode 100644 xilinx/virtex2/xilinx_fifo_dualport_18x1k.xco create mode 100644 xilinx/virtex4/simulation/xilinx_fifo_18x16.vhd create mode 100644 xilinx/virtex4/simulation/xilinx_fifo_18x1k.vhd create mode 100644 xilinx/virtex4/simulation/xilinx_fifo_18x32.vhd create mode 100644 xilinx/virtex4/simulation/xilinx_fifo_18x64.vhd create mode 100644 xilinx/virtex4/xilinx_fifo_dualport_18x1k.xco diff --git a/trb_net16_api_base.vhd b/trb_net16_api_base.vhd index 4c9ad51..975071a 100644 --- a/trb_net16_api_base.vhd +++ b/trb_net16_api_base.vhd @@ -9,7 +9,7 @@ use work.trb_net_std.all; entity trb_net16_api_base is generic ( - API_TYPE : integer range 0 to 1 := c_API_ACTIVE; + API_TYPE : integer range 0 to 1 := c_API_PASSIVE; FIFO_TO_INT_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH; FIFO_TO_APL_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH; USE_REPLY_CHANNEL : integer range 0 to 1 := std_USE_REPLY_CHANNEL; @@ -225,7 +225,7 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is signal saved_fifo_to_apl_packet_type, current_fifo_to_apl_packet_type : std_logic_vector(2 downto 0); signal state_bits, state_bits_to_int, state_bits_to_apl : std_logic_vector(2 downto 0); - signal slave_running, next_slave_running, get_slave_running, release_slave_running : std_logic; +-- signal slave_running, next_slave_running, get_slave_running, release_slave_running : std_logic; signal next_INT_MASTER_DATA_OUT: std_logic_vector(c_DATA_WIDTH-1 downto 0); signal next_INT_MASTER_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0); @@ -238,7 +238,7 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is signal next_APL_TYP_OUT, reg_APL_TYP_OUT, buf_APL_TYP_OUT: std_logic_vector(2 downto 0); type OUTPUT_SELECT is (HDR, DAT, TRM, TRM_COMB); - signal out_select, last_out_select: OUTPUT_SELECT; + signal out_select: OUTPUT_SELECT; signal sequence_counter,next_sequence_counter : std_logic_vector(7 downto 0); signal combined_header_F1, combined_header_F2, combined_header_F3 : std_logic_vector(15 downto 0); signal combined_trailer_F1, combined_trailer_F2, combined_trailer_F3 : std_logic_vector(15 downto 0); @@ -247,18 +247,16 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is signal update_registered_trailer: std_logic; signal master_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal out_enable : std_logic_vector(1 downto 0); signal send_trm_wrong_addr, next_send_trm_wrong_addr : std_logic; - signal wait_for_answer, next_wait_for_answer : std_logic; - type PAS_API_TO_APL_STATE_T is (IDLE, WRONG_ADDR, MY_ADDR); + type PAS_API_TO_APL_STATE_T is (sa_IDLE, sa_INACTIVE, sa_WRONG_ADDR, sa_MY_ADDR); signal state_to_apl, next_state_to_apl : PAS_API_TO_APL_STATE_T; - type state_to_int_t is (IDLE, WAITING, SEND_SHORT, SEND_HEADER, RUNNING, SEND_TRAILER, SHUTDOWN); + type state_to_int_t is ( INACTIVE, IDLE, SEND_SHORT, SEND_HEADER, RUNNING, SEND_TRAILER, SHUTDOWN); signal state_to_int, next_state_to_int : state_to_int_t; - type API_STATE is (IDLE, SEND_HEADER, RUNNING, SHUTDOWN, SEND_SHORT, SEND_TRAILER, WAITING,MY_ERROR); - signal current_state, next_state : API_STATE; +-- type API_STATE is (IDLE, SEND_HEADER, RUNNING, SHUTDOWN, SEND_SHORT, SEND_TRAILER, WAITING,MY_ERROR); +-- signal current_state, next_state : API_STATE; signal throw_away : std_logic; signal fifo_to_apl_read_before : std_logic; signal fifo_to_int_read_before : std_logic; @@ -267,6 +265,9 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is signal sbuf_to_apl_free : std_logic; signal sbuf_apl_type_dataready : std_logic; + signal master_start, master_end, slave_start, slave_end : std_logic; + signal master_running, slave_running : std_logic; + begin --------------------------------------- -- termination for active api @@ -349,8 +350,9 @@ begin STAT_FIFO_TO_INT(15) <= fifo_to_int_empty; STAT_FIFO_TO_INT(7 downto 4) <= (others => '0'); STAT_FIFO_TO_INT(13 downto 12) <= (others => '0'); - STAT_FIFO_TO_INT(28 downto 16) <= (others => '0'); - STAT_FIFO_TO_INT(31 downto 29) <= state_bits; + STAT_FIFO_TO_INT(25 downto 16) <= (others => '0'); + STAT_FIFO_TO_INT(28 downto 26) <= state_bits_to_int; + STAT_FIFO_TO_INT(31 downto 29) <= state_bits_to_apl; --------------------------------------- -- fifo to apl --------------------------------------- @@ -624,14 +626,14 @@ begin end process; - gen_pas_api_fsm : if API_TYPE = 0 generate + --------------------------------------- ---state machine for passive api +--state machine for direction to APL --------------------------------------- to_apl : process(fifo_to_apl_full, reg_INT_SLAVE_READ_OUT, INT_SLAVE_DATAREADY_IN, fifo_to_apl_empty, fifo_to_apl_packet_num_out, state_to_apl, reg_APL_TYP_OUT, reg_APL_PACKET_NUM_OUT, sbuf_to_apl_free, INT_SLAVE_DATA_IN, INT_SLAVE_PACKET_NUM_IN, APL_MY_ADDRESS_IN, - reg_APL_DATAREADY_OUT, slave_running, fifo_to_apl_read_before, throw_away ) + reg_APL_DATAREADY_OUT, slave_running, fifo_to_apl_read_before, throw_away,state_to_int ) begin next_INT_SLAVE_READ_OUT <= not fifo_to_apl_full; fifo_to_apl_write <= reg_INT_SLAVE_READ_OUT and INT_SLAVE_DATAREADY_IN; @@ -639,37 +641,35 @@ begin next_APL_DATAREADY_OUT <= '0'; next_state_to_apl <= state_to_apl; next_send_trm_wrong_addr <= '0'; - next_wait_for_answer <= '0'; - get_slave_running <= '0'; throw_away <= '0'; - - if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT = "11" and (sbuf_to_apl_free = '1' or state_to_apl = WRONG_ADDR) then - next_state_to_apl <= IDLE; - end if; + slave_start <= '0'; + slave_end <= '0'; case state_to_apl is - when IDLE => + when sa_IDLE => if INT_SLAVE_DATAREADY_IN = '1' then if (INT_SLAVE_DATA_IN(2 downto 0) = TYPE_TRM and INT_SLAVE_PACKET_NUM_IN = "00") then - get_slave_running <= '1'; - next_wait_for_answer <= '1'; - next_state_to_apl <= MY_ADDR; + next_state_to_apl <= sa_MY_ADDR; + slave_start <= '1'; end if; if INT_SLAVE_PACKET_NUM_IN = "10" then if INT_SLAVE_DATA_IN = APL_MY_ADDRESS_IN or INT_SLAVE_DATA_IN = BROADCAST_ADDRESS then - get_slave_running <= '1'; - next_wait_for_answer <= '1'; - next_state_to_apl <= MY_ADDR; + next_state_to_apl <= sa_MY_ADDR; + slave_start <= '1'; else - next_state_to_apl <= WRONG_ADDR; + next_state_to_apl <= sa_WRONG_ADDR; next_send_trm_wrong_addr <= '1'; end if; end if; end if; - when WRONG_ADDR => + when sa_WRONG_ADDR => fifo_to_apl_read <= not fifo_to_apl_empty; throw_away <= '1'; - when MY_ADDR => + if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT = "11" then + next_state_to_apl <= sa_INACTIVE; + slave_end <= '1'; + end if; + when sa_MY_ADDR => if APL_WRITE_4_PACKETS = 0 then next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and (or_all(fifo_to_apl_packet_num_out)); throw_away <= not or_all(fifo_to_apl_packet_num_out); @@ -677,12 +677,29 @@ begin next_APL_DATAREADY_OUT <= fifo_to_apl_read_before; end if; fifo_to_apl_read <= not fifo_to_apl_empty and not (fifo_to_apl_read_before and not sbuf_to_apl_free and not throw_away); - throw_away <= not or_all(fifo_to_apl_packet_num_out); + if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT = "11" and sbuf_to_apl_free = '1' then + next_state_to_apl <= sa_INACTIVE; + slave_end <= '1'; + end if; + when sa_INACTIVE => + if API_TYPE = 0 then + if state_to_int = INACTIVE then + next_state_to_apl <= sa_IDLE; + end if; + elsif API_TYPE = 1 then + if state_to_int /= IDLE then + next_state_to_apl <= sa_IDLE; + end if; + end if; end case; end process; - to_int : process(state_to_int, send_trm_wrong_addr, wait_for_answer, APL_SHORT_TRANSFER_IN, APL_SEND_IN, - master_counter, sbuf_free, fifo_to_int_empty, sequence_counter, fifo_to_int_read_before) +--------------------------------------- +--state machine for direction to INT +--------------------------------------- + to_int : process(state_to_int, send_trm_wrong_addr, APL_SHORT_TRANSFER_IN, APL_SEND_IN, + master_counter, sbuf_free, fifo_to_int_empty, sequence_counter, fifo_to_int_read_before, + state_to_apl) begin next_state_to_int <= state_to_int; update_registered_trailer <= '0'; @@ -690,18 +707,25 @@ begin next_INT_MASTER_DATAREADY_OUT <= '0'; next_sequence_counter <= sequence_counter; fifo_to_int_read <= '0'; - release_slave_running <= '0'; - + master_start <= '0'; + master_end <= '0'; + case state_to_int is - when IDLE => - if wait_for_answer = '1' then - next_state_to_int <= WAITING; - end if; - if send_trm_wrong_addr = '1' then - next_state_to_int <= SEND_SHORT; + when INACTIVE => + if API_TYPE = 0 then + if slave_start = '1' then + next_state_to_int <= IDLE; + elsif send_trm_wrong_addr = '1' then + next_state_to_int <= SEND_SHORT; + end if; + else --API_TYPE = 1 + if state_to_apl = sa_INACTIVE then + next_state_to_int <= IDLE; + end if; end if; - when WAITING => + when IDLE => if APL_SEND_IN = '1' then + master_start <= '1'; if APL_SHORT_TRANSFER_IN = '1' then next_state_to_int <= SEND_SHORT; else @@ -724,10 +748,10 @@ begin next_INT_MASTER_DATAREADY_OUT <= sbuf_free and (fifo_to_int_read_before or not or_all(master_counter)); if APL_SEND_IN = '0' then -- terminate the transfer update_registered_trailer <= '1'; - if fifo_to_int_empty = '1' and master_counter = "11" and sbuf_free = '1' then -- immediate stop - next_state_to_int <= SEND_TRAILER; + if fifo_to_int_empty = '1' and master_counter = "11" and sbuf_free = '1' then + next_state_to_int <= SEND_TRAILER; -- immediate stop else - next_state_to_int <= SHUTDOWN; + next_state_to_int <= SHUTDOWN; -- send rest of data / padding end if; end if; when SHUTDOWN => @@ -742,209 +766,38 @@ begin out_select <= TRM; next_INT_MASTER_DATAREADY_OUT <= sbuf_free; if master_counter = "11" and sbuf_free = '1' then - next_state_to_int <= IDLE; + next_state_to_int <= INACTIVE; next_sequence_counter <= sequence_counter +1; - release_slave_running <= '1'; + master_end <= '1'; end if; end case; end process; - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' or release_slave_running = '1' then - slave_running <= '0'; - elsif get_slave_running = '1' then - slave_running <= '1'; - end if; - end if; - end process; process(CLK) begin if rising_edge(CLK) then if RESET = '1' then - state_to_apl <= IDLE; - state_to_int <= IDLE; + if API_TYPE = 0 then + state_to_apl <= sa_IDLE; + state_to_int <= INACTIVE; + else + state_to_apl <= sa_INACTIVE; + state_to_int <= IDLE; + end if; reg_INT_SLAVE_READ_OUT <= '0'; send_trm_wrong_addr <= '0'; - wait_for_answer <= '0'; sequence_counter <= (others => '0'); else state_to_apl <= next_state_to_apl; state_to_int <= next_state_to_int; reg_INT_SLAVE_READ_OUT <= next_INT_SLAVE_READ_OUT; send_trm_wrong_addr <= next_send_trm_wrong_addr; - wait_for_answer <= next_wait_for_answer; sequence_counter <= next_sequence_counter; end if; end if; end process; - end generate; - ---------------------------------------- ---the state machine for active api ---------------------------------------- - gen_act_api_fsm : if API_TYPE = 1 generate - STATE_COMB: process(current_state, APL_SEND_IN, slave_running, sequence_counter, - APL_SHORT_TRANSFER_IN, APL_WRITE_IN, fifo_to_int_empty, - sbuf_free, master_counter, fifo_to_apl_full, - reg_APL_DATAREADY_OUT, reg_INT_SLAVE_READ_OUT, - INT_SLAVE_DATAREADY_IN, fifo_to_apl_empty, sbuf_to_apl_free, - fifo_to_apl_packet_num_out, reg_APL_TYP_OUT, - reg_APL_PACKET_NUM_OUT, last_out_select, fifo_to_int_read_before) - begin - next_state <= current_state; - out_select <= DAT; - update_registered_trailer <= '0'; - fifo_to_int_read <= '0'; - --next_INT_SLAVE_READ_OUT <= '0'; - --fifo_to_apl_write <= '0'; - --next_APL_DATAREADY_OUT <= '0'; - --fifo_to_apl_read <= '0'; - next_slave_running <= slave_running; - next_sequence_counter <= sequence_counter; - - next_INT_MASTER_DATAREADY_OUT <= fifo_to_int_read_before; - - ------------------------------------------------------------------------------- - -- IDLE - ------------------------------------------------------------------------------- - if current_state = IDLE then - if APL_SEND_IN = '1' and sbuf_free = '1' then - if APL_SHORT_TRANSFER_IN = '1' then -- and APL_WRITE_IN = '0' and fifo_to_int_empty = '1' - next_state <= SEND_SHORT; -- no next data word, waiting for falling edge of APL_SEND_IN - update_registered_trailer <= '1'; -- moved from SEND_SHORT - else -- normal transfer, prepare the header - next_state <= SEND_HEADER; - out_select <= HDR; - next_INT_MASTER_DATAREADY_OUT <= '1'; - end if; -- next word will be a header - end if; -- APL_SEND_IN - ------------------------------------------------------------------------------- - -- SEND_SHORT - ------------------------------------------------------------------------------- - elsif current_state = SEND_SHORT then - out_select <= TRM; - if APL_SEND_IN = '0' and sbuf_free = '1' then -- terminate the transfer - next_state <= SEND_TRAILER; - next_INT_MASTER_DATAREADY_OUT <= '1'; - end if; - ------------------------------------------------------------------------------- - -- SEND_HEADER - ------------------------------------------------------------------------------- - elsif current_state = SEND_HEADER then - if master_counter = "00" then - next_state <= RUNNING; - out_select <= DAT; - --next_INT_MASTER_DATAREADY_OUT <= '0'; - else - out_select <= HDR; - next_INT_MASTER_DATAREADY_OUT <= '1'; - end if; - ------------------------------------------------------------------------------- - -- RUNNING - ------------------------------------------------------------------------------- - elsif current_state = RUNNING then - out_select <= DAT; - fifo_to_int_read <= not fifo_to_int_empty and not (fifo_to_int_read_before and not sbuf_free); - next_INT_MASTER_DATAREADY_OUT <= fifo_to_int_read_before or not or_all(master_counter); - if APL_SEND_IN = '0' then -- terminate the transfer - update_registered_trailer <= '1'; - if fifo_to_int_empty = '1' and fifo_to_int_read_before = '0' and sbuf_free = '1' then -- immediate stop - next_INT_MASTER_DATAREADY_OUT <= '1'; - if master_counter = "00" then --????? - next_state <= SEND_TRAILER; - out_select <= TRM_COMB; - end if; - else - next_state <= SHUTDOWN; - end if; - end if; - ------------------------------------------------------------------------------- - -- SHUTDOWN: Empty the pipe - ------------------------------------------------------------------------------- - elsif current_state = SHUTDOWN then - out_select <= DAT; - next_INT_MASTER_DATAREADY_OUT <= fifo_to_int_read_before or not or_all(master_counter); - fifo_to_int_read <= not fifo_to_int_empty and not (fifo_to_int_read_before and not sbuf_free); - if fifo_to_int_empty = '1' and fifo_to_int_read_before = '0' and sbuf_free = '1' then -- and master_counter = "00" - next_state <= SEND_TRAILER; - out_select <= TRM; - end if; - ------------------------------------------------------------------------------- - -- SEND_TRAILER - ------------------------------------------------------------------------------- - elsif current_state = SEND_TRAILER then - out_select <= TRM; - next_INT_MASTER_DATAREADY_OUT <= '1'; - if master_counter = "00" then - next_state <= WAITING; - next_INT_MASTER_DATAREADY_OUT <= '0'; - if API_TYPE = 0 then --here is the end of the passive transfer - next_sequence_counter <= sequence_counter +1; - next_slave_running <= '0'; - end if; - end if; - ------------------------------------------------------------------------------- - -- WAITING => for the answer or a request - ------------------------------------------------------------------------------- - elsif current_state = WAITING then - if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT = "11" and (sbuf_to_apl_free = '1' and reg_APL_DATAREADY_OUT = '1') then - -- - next_state <= IDLE; - next_sequence_counter <= sequence_counter +1; - end if; - -- MISSING: SEQNR check - end if; - if master_counter = "00" or fifo_to_int_empty = '1' then - fifo_to_int_read <= '0'; - end if; - if sbuf_free = '0' then - next_INT_MASTER_DATAREADY_OUT <= '0'; - end if; - end process; - - - next_INT_SLAVE_READ_OUT <= not fifo_to_apl_full; - fifo_to_apl_write <= reg_INT_SLAVE_READ_OUT and INT_SLAVE_DATAREADY_IN; - - fifo_to_apl_read <= sbuf_to_apl_free; - - process(fifo_to_apl_read_before, fifo_to_apl_packet_num_out) - begin - if APL_WRITE_4_PACKETS = 0 then - next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and or_all(fifo_to_apl_packet_num_out); - throw_away <= not or_all(fifo_to_apl_packet_num_out); - else - next_APL_DATAREADY_OUT <= fifo_to_apl_read_before; - throw_away <= '0'; - end if; - end process; - CLK_REG: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - sequence_counter <= (others => '0'); - reg_INT_SLAVE_READ_OUT <= '0'; - last_out_select <= DAT; - if API_TYPE = 1 then - current_state <= IDLE; - else - current_state <= WAITING; - end if; - slave_running <= '0'; - elsif CLK_EN = '1' then - sequence_counter <= next_sequence_counter; - last_out_select <= out_select; - reg_INT_SLAVE_READ_OUT <= next_INT_SLAVE_READ_OUT; - current_state <= next_state; - slave_running <= next_slave_running; - end if; - end if; - end process; - end generate; --------------------------------------- @@ -992,14 +845,49 @@ begin fifo_to_apl_packet_num_in <= INT_SLAVE_PACKET_NUM_IN; INT_SLAVE_READ_OUT <= reg_INT_SLAVE_READ_OUT; - genAPL_RUN_OUT_0: if API_TYPE = 0 generate - APL_RUN_OUT <= slave_running; - end generate; - genAPL_RUN_OUT_1: if API_TYPE = 1 generate - APL_RUN_OUT <= '0' when current_state = IDLE else '1'; - end generate; - + RUN_OUT_gen : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + APL_RUN_OUT <= '0'; + else + if API_TYPE = 0 then + if slave_start = '1' then + APL_RUN_OUT <= '1'; + elsif slave_running = '0' and state_to_int = INACTIVE then + APL_RUN_OUT <= '0'; + end if; + else --API_TYPE = 1 + if master_start = '1' then + APL_RUN_OUT <= '1'; + elsif master_running = '0' and state_to_apl = sa_INACTIVE then + APL_RUN_OUT <= '0'; + end if; + end if; + end if; + end if; + end process; + RUNNING_gen : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + master_running <= '0'; + slave_running <= '0'; + else + if master_start = '1' then + master_running <= '1'; + elsif master_end = '1' then + master_running <= '0'; + end if; + if slave_start = '1' then + slave_running <= '1'; + elsif slave_end = '1' then + slave_running <= '0'; + end if; + end if; + end if; + end process; REG3 : process(CLK) begin @@ -1017,33 +905,16 @@ begin end process; --for simulation only - gen_1: if API_TYPE = 1 generate - process(current_state) - begin - case current_state is - when IDLE => state_bits <= "000"; - when SEND_HEADER => state_bits <= "001"; - when RUNNING => state_bits <= "010"; - when SHUTDOWN => state_bits <= "011"; - when SEND_SHORT => state_bits <= "100"; - when SEND_TRAILER => state_bits <= "101"; - when WAITING => state_bits <= "110"; - when others => state_bits <= "111"; - end case; - end process; - state_bits_to_apl <= "000"; - state_bits_to_int <= "000"; - end generate; - gen_2: if API_TYPE = 0 generate - state_bits <= "000"; + process(state_to_apl) begin case state_to_apl is - when IDLE => state_bits_to_apl <= "000"; - when MY_ADDR => state_bits_to_apl <= "001"; - when WRONG_ADDR => state_bits_to_apl <= "100"; - when others => state_bits_to_apl <= "111"; + when sa_IDLE => state_bits_to_apl <= "000"; + when sa_MY_ADDR => state_bits_to_apl <= "001"; + when sa_WRONG_ADDR => state_bits_to_apl <= "010"; + when sa_INACTIVE => state_bits_to_apl <= "100"; + when others => state_bits_to_apl <= "111"; end case; end process; process(state_to_int) @@ -1055,10 +926,10 @@ begin when SHUTDOWN => state_bits_to_int <= "011"; when SEND_SHORT => state_bits_to_int <= "100"; when SEND_TRAILER => state_bits_to_int <= "101"; - when WAITING => state_bits_to_int <= "110"; + when INACTIVE => state_bits_to_int <= "110"; when others => state_bits_to_int <= "111"; end case; end process; - end generate; + end architecture; diff --git a/trb_net16_endpoint_0_trg_1_api.vhd b/trb_net16_endpoint_0_trg_1_api.vhd index faffa6c..c18b688 100644 --- a/trb_net16_endpoint_0_trg_1_api.vhd +++ b/trb_net16_endpoint_0_trg_1_api.vhd @@ -175,14 +175,16 @@ end component; component trb_net16_api_base is generic ( - API_TYPE : integer range 0 to 1 := c_API_PASSIVE; - FIFO_TO_INT_DEPTH : integer range 1 to 6 := std_FIFO_DEPTH; - FIFO_TO_APL_DEPTH : integer range 1 to 6 := std_FIFO_DEPTH; + API_TYPE : integer range 0 to 1 := c_API_ACTIVE; + FIFO_TO_INT_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH; + FIFO_TO_APL_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH; USE_REPLY_CHANNEL : integer range 0 to 1 := std_USE_REPLY_CHANNEL; FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY; SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES; - SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES + SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES; + APL_WRITE_4_PACKETS:integer range 0 to 1 := c_NO ); port( diff --git a/trb_net16_ibuf.vhd b/trb_net16_ibuf.vhd index a46539a..9abaff1 100644 --- a/trb_net16_ibuf.vhd +++ b/trb_net16_ibuf.vhd @@ -47,7 +47,8 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is component trb_net16_fifo is generic ( - DEPTH : integer := 4 + DEPTH : integer := 4; + USE_VENDOR_CORES : integer := c_YES ); port ( CLK : in std_logic; @@ -191,7 +192,7 @@ begin current_error_state, reg_read_out, current_packet_type) begin -- process got_ack_internal <= '0'; - next_read_out <= '0'; + next_read_out <= not fifo_full; fifo_write <= '0'; next_rec_buffer_size_out <= current_rec_buffer_size_out; next_error_state <= current_error_state; @@ -210,9 +211,6 @@ begin end if; end if; end if; - if fifo_full = '0' then - next_read_out <= '1'; - end if; end process; MED_READ_OUT <= reg_read_out; @@ -257,7 +255,12 @@ begin SYN_READ_IN => INT_READ_IN ); - sbuf_free <= comb_next_read; --sbuf killed + process(CLK) + begin + if rising_edge(CLK) then + sbuf_free <= comb_next_read; + end if; + end process; end generate; gen_notsecure : if SECURE_MODE = 0 generate INT_DATA_OUT <= tmp_INT_DATA_OUT; @@ -341,9 +344,6 @@ begin elsif CLK_EN = '1' then is_locked <= got_locked and not release_locked; reg_eob_out <= got_eob_out; - else - is_locked <= is_locked; - reg_eob_out <= reg_eob_out; end if; end if; end process; @@ -395,18 +395,14 @@ begin STAT_BUFFER(9 downto 4) <= (others => '0'); end generate; - - MAKE_ERROR_BITS : process(current_error_state) + process(current_error_state) begin - if current_error_state = IDLE then - STAT_BUFFER(11 downto 10) <= "00"; - elsif current_error_state = GOT_OVERFLOW_ERROR then - STAT_BUFFER(11 downto 10) <= "01"; - elsif current_error_state = GOT_LOCKED_ERROR then - STAT_BUFFER(11 downto 10) <= "10"; - else - STAT_BUFFER(11 downto 10) <= "11"; - end if; + case current_error_state is + when IDLE => STAT_BUFFER(11 downto 10) <= "00"; + when GOT_OVERFLOW_ERROR => STAT_BUFFER(11 downto 10) <= "01"; + when GOT_LOCKED_ERROR => STAT_BUFFER(11 downto 10) <= "10"; + when others => STAT_BUFFER(11 downto 10) <= "11"; + end case; end process; STAT_BUFFER(31 downto 12) <= (others => '0'); diff --git a/trb_net16_io_multiplexer.vhd b/trb_net16_io_multiplexer.vhd index 4b30af3..27ea0d8 100644 --- a/trb_net16_io_multiplexer.vhd +++ b/trb_net16_io_multiplexer.vhd @@ -107,20 +107,24 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is signal current_MED_READ_OUT, next_MED_READ_OUT: STD_LOGIC; signal final_INT_READ_OUT: STD_LOGIC_VECTOR ((2**c_MUX_WIDTH)-1 downto 0); --signal tmp_tmp_INT_READ_OUT: STD_LOGIC_VECTOR ((2**c_MUX_WIDTH)-1 downto 0); - signal mux_read, mux_enable, mux_next_READ: STD_LOGIC; + signal mux_read, mux_enable, mux_next_READ: STD_LOGIC; signal current_mux_buffer: STD_LOGIC_VECTOR (c_DATA_WIDTH+2-1 downto 0); signal endpoint_locked, next_endpoint_locked: std_logic; signal current_INT_READ_OUT : STD_LOGIC_VECTOR ((2**c_MUX_WIDTH)-1 downto 0); signal current_mux_packet_number : std_logic_vector (1 downto 0); signal last_mux_enable : std_logic; signal arbiter_CLK_EN : std_logic; + signal buf_INT_DATA_OUT: STD_LOGIC_VECTOR ((c_DATA_WIDTH)*(2**c_MUX_WIDTH)-1 downto 0); + signal buf_INT_PACKET_NUM_OUT: STD_LOGIC_VECTOR (2*(2**c_MUX_WIDTH)-1 downto 0); + signal demux_comb_dataready_in : std_logic_vector (2**c_MUX_WIDTH-1 downto 0); begin ------------------------------------------------------------------------------- -- DEMUX ------------------------------------------------------------------------------ - G1: for i in 0 to 2**c_MUX_WIDTH-1 generate - gensbuf: if MUX_SECURE_MODE = 1 generate + gensbuf: if MUX_SECURE_MODE = 1 generate + G1: for i in 0 to 2**c_MUX_WIDTH-1 generate + demux_comb_dataready_in(i) <= next_demux_dr(i) and MED_DATAREADY_IN; DEMUX_SBUF: trb_net16_sbuf generic map ( VERSION => std_SBUF_VERSION @@ -129,7 +133,7 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is CLK => CLK, RESET => RESET, CLK_EN => CLK_EN, - COMB_DATAREADY_IN => next_demux_dr(i), + COMB_DATAREADY_IN => demux_comb_dataready_in(i), COMB_next_READ_OUT => demux_next_READ(i), COMB_READ_IN => current_demux_READ(i), COMB_DATA_IN => MED_DATA_IN, @@ -140,23 +144,41 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is SYN_READ_IN => INT_READ_IN(i) ); end generate; - genff: if MUX_SECURE_MODE = 0 generate + end generate; + + genff: if MUX_SECURE_MODE = 0 generate + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + buf_INT_DATA_OUT ((c_DATA_WIDTH)-1 downto 0) <= (others => '0'); + buf_INT_PACKET_NUM_OUT(c_NUM_WIDTH-1 downto 0) <= (others => '0'); + INT_DATAREADY_OUT(0) <= '0'; + else + buf_INT_DATA_OUT ((c_DATA_WIDTH)-1 downto 0) <= MED_DATA_IN; + buf_INT_PACKET_NUM_OUT(c_NUM_WIDTH-1 downto 0) <= MED_PACKET_NUM_IN; + INT_DATAREADY_OUT(0) <= next_demux_dr(0) and MED_DATAREADY_IN; + end if; + end if; + end process; + G2: for i in 1 to 2**c_MUX_WIDTH-1 generate + buf_INT_DATA_OUT (c_DATA_WIDTH*(i+1)-1 downto c_DATA_WIDTH*i) <= buf_INT_DATA_OUT ((c_DATA_WIDTH)-1 downto 0); + buf_INT_PACKET_NUM_OUT(c_NUM_WIDTH*(i+1)-1 downto c_NUM_WIDTH*i) <= buf_INT_PACKET_NUM_OUT(c_NUM_WIDTH-1 downto 0); process(CLK) begin if rising_edge(CLK) then if RESET = '1' then - INT_DATA_OUT ((c_DATA_WIDTH)*(i+1)-1 downto (c_DATA_WIDTH)*(i)) <= (others => '0'); - INT_PACKET_NUM_OUT(2*(i+1)-1 downto 2*i) <= (others => '0'); INT_DATAREADY_OUT(i) <= '0'; else - INT_DATA_OUT ((c_DATA_WIDTH)*(i+1)-1 downto (c_DATA_WIDTH)*(i)) <= MED_DATA_IN; - INT_PACKET_NUM_OUT(2*(i+1)-1 downto 2*i) <= MED_PACKET_NUM_IN; INT_DATAREADY_OUT(i) <= next_demux_dr(i) and MED_DATAREADY_IN; end if; end if; end process; end generate; + INT_DATA_OUT <= buf_INT_DATA_OUT; + INT_PACKET_NUM_OUT <= buf_INT_PACKET_NUM_OUT; end generate; + --current_demux_READ <= INT_READ_IN; gen2: if MUX_SECURE_MODE = 0 generate demux_next_READ <= (others => '1'); @@ -167,7 +189,7 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is MED_DATAREADY_IN, current_MED_READ_OUT, MED_PACKET_NUM_IN, demux_dr_tmp) begin - next_demux_dr <= (others => '0'); + next_demux_dr <= demux_dr_tmp; --(others => '0'); current_demux_READ <= (others => '0'); -- generate the READ_OUT next_MED_READ_OUT <= and_all(demux_next_READ or INT_READ_IN); @@ -338,8 +360,15 @@ ARBITER: trb_net_priority_arbiter process (current_INT_READ_OUT, INT_DATA_IN, INT_PACKET_NUM_IN) variable var_mux_buffer : STD_LOGIC_VECTOR (c_DATA_WIDTH+2-1 downto 0); + variable j : integer range 0 to c_MUX_WIDTH-1 := 0; variable k : integer range 0 to 2**c_MUX_WIDTH-1 := 0; begin +-- j := get_bit_position(current_INT_READ_OUT); +-- current_mux_buffer(c_DATA_WIDTH-1 downto 0) <= INT_DATA_IN(c_DATA_WIDTH*(j+1)-1 downto c_DATA_WIDTH*j); +-- current_mux_buffer(c_DATA_WIDTH+c_NUM_WIDTH-1 downto c_DATA_WIDTH) <= INT_PACKET_NUM_IN(c_NUM_WIDTH*(j+1)-1 downto c_NUM_WIDTH*j); +-- if INT_PACKET_NUM_IN(c_NUM_WIDTH*(j+1)-1 downto c_NUM_WIDTH*j) = "00" then +-- current_mux_buffer(3+c_MUX_WIDTH-1 downto 3) <= conv_std_logic_vector(j, c_MUX_WIDTH); +-- end if; k := 0; var_mux_buffer := (others => '0'); for i in 0 to 2**c_MUX_WIDTH-1 loop @@ -360,8 +389,6 @@ ARBITER: trb_net_priority_arbiter current_mux_buffer <= var_mux_buffer; end process; - - mux_enable <= (mux_next_READ); -- or MED_READ_IN mux_read <= or_all(current_INT_READ_OUT and INT_DATAREADY_IN); diff --git a/trb_net16_iobuf.vhd b/trb_net16_iobuf.vhd index 1244e91..bf71378 100644 --- a/trb_net16_iobuf.vhd +++ b/trb_net16_iobuf.vhd @@ -499,7 +499,8 @@ begin else next_REPLY_IS_LOCKED <= '0'; end if; - end if; + end if; + if INIT_IS_LOCKED = '1' then -- listen to REPLYOBUF if REPLYOBUF_stat_locked(0) = '1' or CTRL_LOCKED(0) = '1' then @@ -529,9 +530,6 @@ begin elsif CLK_EN = '1' then INIT_IS_LOCKED <= next_INIT_IS_LOCKED; REPLY_IS_LOCKED <= next_REPLY_IS_LOCKED; - else - INIT_IS_LOCKED <= INIT_IS_LOCKED; - REPLY_IS_LOCKED <= REPLY_IS_LOCKED; end if; end if; end process; diff --git a/trb_net16_med_tlk.vhd b/trb_net16_med_tlk.vhd index 499eae0..857eb66 100644 --- a/trb_net16_med_tlk.vhd +++ b/trb_net16_med_tlk.vhd @@ -42,21 +42,24 @@ end trb_net16_med_tlk; architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is - component trb_net_fifo_16bit_bram_dualport + component trb_net_fifo_16bit_bram_dualport is generic( - USE_STATUS_FLAGS : integer range 0 to 1 := c_YES + USE_STATUS_FLAGS : integer := c_YES ); port ( read_clock_in: IN std_logic; write_clock_in: IN std_logic; read_enable_in: IN std_logic; write_enable_in: IN std_logic; - fifo_gsr_in: IN std_logic; --reset + fifo_gsr_in: IN std_logic; write_data_in: IN std_logic_vector(17 downto 0); read_data_out: OUT std_logic_vector(17 downto 0); full_out: OUT std_logic; empty_out: OUT std_logic; - fifostatus_out: OUT std_logic_vector(3 downto 0) + fifostatus_out: OUT std_logic_vector(3 downto 0); --counter for 1/16th of fifo + valid_read_out: OUT std_logic; + almost_empty_out:OUT std_logic; + underflow_out: OUT std_logic ); end component trb_net_fifo_16bit_bram_dualport; @@ -105,6 +108,10 @@ architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is signal buf_MED_ERROR_OUT, next_MED_ERROR_OUT : std_logic_vector(2 downto 0); signal state_bits : std_logic_vector(2 downto 0); signal counter_reset : std_logic; + signal fifo_almost_empty_m, fifo_almost_empty_a : std_logic; + signal fifo_valid_read_m, fifo_valid_read_a : std_logic; + signal fifo_underflow_a, fifo_underflow_m : std_logic; + begin TLK_ENABLE <= not RESET; @@ -134,15 +141,26 @@ begin read_data_out => fifo_dout_a, full_out => fifo_full_a, empty_out => fifo_empty_a, - fifostatus_out => fifo_status_a + fifostatus_out => fifo_status_a, + almost_empty_out=> fifo_almost_empty_a, + valid_read_out => fifo_valid_read_a, + underflow_out => fifo_underflow_a ); - fifo_wr_en_a <= reg_RX_DV and not reg_RX_ER and rx_allow; - fifo_din_a <= rx_allow & reg_RX_ER & reg_RXD; - fifo_rd_en_a <= '1';--not fifo_empty_a; - fifo_reset <= internal_reset; - buf_MED_DATAREADY_OUT <= last_fifo_rd_en_a and not fifo_dout_a(16) and fifo_dout_a(17); + fifo_wr_en_a <= ((reg_RX_DV and not reg_RX_ER) ) and rx_allow; + fifo_din_a <= fifo_almost_empty_a & (reg_RX_DV and not reg_RX_ER) & reg_RXD; + fifo_rd_en_a <= rx_allow; + buf_MED_DATAREADY_OUT <= fifo_valid_read_a and fifo_dout_a(16) and not fifo_underflow_a; + + +-- fifo_wr_en_a <= ((reg_RX_DV and not reg_RX_ER) or fifo_almost_empty_a) and rx_allow; +-- fifo_din_a <= fifo_almost_empty_a & (reg_RX_DV and not reg_RX_ER) & reg_RXD; +-- fifo_rd_en_a <= not fifo_almost_empty_a and rx_allow; +-- buf_MED_DATAREADY_OUT <= fifo_valid_read_a and fifo_dout_a(16) and not fifo_underflow_a and rx_allow; +-- + MED_ERROR_OUT <= buf_MED_ERROR_OUT; + fifo_reset <= internal_reset; process(CLK) begin @@ -169,11 +187,15 @@ begin STAT(7) <= fifo_empty_m; STAT(8) <= fifo_full_a; STAT(9) <= fifo_full_m; + STAT(10)<= last_fifo_rd_en_m; + STAT(11)<= last_fifo_rd_en_a; + STAT(12)<= fifo_almost_empty_m; + STAT(13)<= fifo_almost_empty_a; STAT(14) <= reg_RX_DV; STAT(15) <= reg_RX_ER; STAT(31 downto 16) <= reg_RXD; - STAT(32) <= buf_STAT(32); - STAT(33) <= buf_STAT(33); + STAT(32) <= fifo_valid_read_m; + STAT(33) <= fifo_valid_read_a; STAT(36 downto 34) <= state_bits; STAT(40 downto 37) <= fifo_status_a; STAT(44 downto 41) <= fifo_status_m; @@ -181,21 +203,11 @@ begin STAT(50 downto 49) <= fifo_dout_m(17 downto 16); STAT(54 downto 51) <= fifo_din_a(3 downto 0); STAT(56 downto 55) <= fifo_din_a(17 downto 16); - STAT(63 downto 57) <= (others => '0'); - - process(CLK) - begin - if rising_edge(CLK) then - if internal_reset = '1' then - buf_STAT(32) <= '0'; - buf_STAT(33) <= '0'; - else - buf_STAT(32) <= fifo_full_a or buf_STAT(32); - buf_STAT(33) <= fifo_full_m or buf_STAT(33); - end if; - end if; - end process; + STAT(57) <= fifo_underflow_a; + STAT(58) <= fifo_underflow_m; + --STAT(63 downto 57) <= (others => '0'); + process(TLK_RX_CLK) begin if rising_edge(TLK_RX_CLK) then @@ -278,9 +290,12 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); fifo_gsr_in => fifo_reset, write_data_in => fifo_din_m, read_data_out => fifo_dout_m, + valid_read_out => fifo_valid_read_m, + almost_empty_out=> fifo_almost_empty_m, full_out => fifo_full_m, empty_out => fifo_empty_m, - fifostatus_out => fifo_status_m + fifostatus_out => fifo_status_m, + underflow_out => fifo_underflow_m ); TLK_TX_ER <= '0'; @@ -294,13 +309,13 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); fifo_wr_en_m <= '0'; fifo_din_m <= (others => '0'); else - fifo_wr_en_m <= MED_DATAREADY_IN and buf_MED_READ_OUT; - fifo_din_m <= MED_PACKET_NUM_IN & MED_DATA_IN; + fifo_wr_en_m <= (MED_DATAREADY_IN and buf_MED_READ_OUT) or fifo_almost_empty_m; + fifo_din_m <= fifo_almost_empty_m & (MED_DATAREADY_IN and buf_MED_READ_OUT) & MED_DATA_IN; end if; end if; end process; - fifo_rd_en_m <= tx_allow; -- and not fifo_empty_m; + fifo_rd_en_m <= tx_allow and not fifo_almost_empty_m; -- and not fifo_empty_m; process(TLK_CLK_neg) begin @@ -312,7 +327,7 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); last_fifo_rd_en_m <= '0'; else reg_TXD <= fifo_dout_m(15 downto 0); - reg_TX_EN <= last_fifo_rd_en_m; + reg_TX_EN <= fifo_valid_read_m and fifo_dout_m(16) and not fifo_underflow_m; --last_fifo_rd_en_m; last_fifo_rd_en_m <= fifo_rd_en_m and not fifo_empty_m; end if; end if; @@ -322,8 +337,8 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); --Medium states ------------- - medium_states : process(current_state, tx_allow, rx_allow, internal_reset, counter, - reg_RX_ER, reg_RX_DV, buf_MED_ERROR_OUT) + medium_states : process(current_state, tx_allow, rx_allow, internal_reset, + reg_RX_ER, reg_RX_DV, buf_MED_ERROR_OUT, counter) begin next_state <= current_state; next_tx_allow <= tx_allow; diff --git a/trb_net16_obuf.vhd b/trb_net16_obuf.vhd index 1134d57..e8123f9 100644 --- a/trb_net16_obuf.vhd +++ b/trb_net16_obuf.vhd @@ -224,7 +224,7 @@ begin reg_INT_READ_OUT, saved_packet_type, sending_state, current_DATA_word, send_ACK, send_EOB, sbuf_free, current_ACK_word, current_EOB_word, - TRANSMITTED_BUFFERS, send_DATA) + TRANSMITTED_BUFFERS, send_DATA, comb_next_read) begin current_output_data_buffer <= current_NOP_word; @@ -296,7 +296,7 @@ begin next_INT_READ_OUT <= '0'; end if; - if sbuf_free = '0' or send_DATA = '0' then + if comb_next_read = '0' or send_DATA = '0' then next_INT_READ_OUT <= '0'; end if; end process; diff --git a/trb_net_pattern_gen.vhd b/trb_net_pattern_gen.vhd index f9d5beb..6f017db 100644 --- a/trb_net_pattern_gen.vhd +++ b/trb_net_pattern_gen.vhd @@ -23,20 +23,15 @@ END trb_net_pattern_gen; architecture trb_net_pattern_gen_arch of trb_net_pattern_gen is begin - - G1: for i in 0 to 2**WIDTH-1 generate - G2: process (INPUT_IN) - begin -- process - if i = INPUT_IN then - RESULT_OUT(i) <= '1'; - else - RESULT_OUT(i) <= '0'; - end if; - end process; - - - end generate; - - -end trb_net_pattern_gen_arch; - + RESULT_OUT <= conv_std_logic_vector(2**conv_integer(INPUT_IN),2**WIDTH); +-- G1: for i in 0 to 2**WIDTH-1 generate +-- G2: process (INPUT_IN) +-- begin -- process +-- if i = INPUT_IN then +-- RESULT_OUT(i) <= '1'; +-- else +-- RESULT_OUT(i) <= '0'; +-- end if; +-- end process; +-- end generate; +end trb_net_pattern_gen_arch; \ No newline at end of file diff --git a/trb_net_priority_arbiter.vhd b/trb_net_priority_arbiter.vhd index a812d1f..8e7f6dc 100755 --- a/trb_net_priority_arbiter.vhd +++ b/trb_net_priority_arbiter.vhd @@ -9,7 +9,7 @@ use work.trb_net_std.all; entity trb_net_priority_arbiter is generic ( - WIDTH : integer := 2 + WIDTH : integer := 8 ); port( -- Misc diff --git a/trb_net_priority_encoder.vhd b/trb_net_priority_encoder.vhd index 9eca237..a552dea 100755 --- a/trb_net_priority_encoder.vhd +++ b/trb_net_priority_encoder.vhd @@ -8,7 +8,7 @@ use work.trb_net_std.all; entity trb_net_priority_encoder is generic ( - WIDTH : integer := 4 + WIDTH : integer := 8 ); port ( INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); @@ -23,23 +23,27 @@ architecture trb_net_priority_encoder_arch of trb_net_priority_encoder is signal leading_pattern: STD_LOGIC_VECTOR (WIDTH-1 downto 0); begin + fixed_pattern(0) <= INPUT_IN(0); + F1: for i in 1 to WIDTH-1 generate + process(INPUT_IN) + begin + if INPUT_IN(i) = '1' and INPUT_IN(i-1 downto 0) = 0 then + fixed_pattern(i) <= '1'; + else + fixed_pattern(i) <= '0'; + end if; + end process; + end generate; - G1: for i in 0 to WIDTH-1 generate - G2: if i = 0 generate - fixed_pattern(0) <= INPUT_IN(0); - leading_pattern(0) <= INPUT_IN(0); - end generate; - G3: if i > 0 generate + leading_pattern(0) <= INPUT_IN(0); + G1: for i in 1 to WIDTH-1 generate comb : process (INPUT_IN, leading_pattern) begin - fixed_pattern(i) <= '0'; leading_pattern(i) <= leading_pattern(i-1); - if (INPUT_IN(i) = '1') and (leading_pattern(i-1) = '0') then - fixed_pattern(i) <= '1'; + if (INPUT_IN(i) = '1') then -- and (leading_pattern(i-1) = '0') leading_pattern(i) <= '1'; end if; end process; - end generate; end generate; RESULT_OUT <= fixed_pattern; diff --git a/trb_net_std.vhd b/trb_net_std.vhd index 0cc87bd..c3ac250 100644 --- a/trb_net_std.vhd +++ b/trb_net_std.vhd @@ -101,6 +101,9 @@ package trb_net_std is function xor_all (arg : std_logic_vector) return std_logic; + function get_bit_position (arg : std_logic_vector) + return integer; + end package trb_net_std; package body trb_net_std is @@ -148,6 +151,22 @@ package body trb_net_std is end loop; -- i return tmp; end function xor_all; + + function get_bit_position (arg : std_logic_vector) + return integer is + variable tmp : integer := 0; + begin + tmp := 0; + for i in arg'range loop + if arg(i) = '1' then + tmp := i; + end if; + --exit when arg(i) = '1'; + end loop; -- i + return tmp; + end get_bit_position; + + end package body trb_net_std; diff --git a/xilinx/trb_net_fifo_16bit_bram_dualport_arch.vhd b/xilinx/trb_net_fifo_16bit_bram_dualport_arch.vhd index 1c90bf0..008e66b 100644 --- a/xilinx/trb_net_fifo_16bit_bram_dualport_arch.vhd +++ b/xilinx/trb_net_fifo_16bit_bram_dualport_arch.vhd @@ -53,486 +53,528 @@ entity trb_net_fifo_16bit_bram_dualport is read_data_out: OUT std_logic_vector(17 downto 0); full_out: OUT std_logic; empty_out: OUT std_logic; - fifostatus_out: OUT std_logic_vector(3 downto 0) --counter for 1/16th of fifo - ); + fifostatus_out: OUT std_logic_vector(3 downto 0); --counter for 1/16th of fifo + valid_read_out: OUT std_logic; + almost_empty_out:OUT std_logic; + underflow_out : OUT std_logic + ); end entity trb_net_fifo_16bit_bram_dualport; architecture trb_net_fifo_16bit_bram_dualport_arch of trb_net_fifo_16bit_bram_dualport is - signal read_clock: std_logic; - signal write_clock: std_logic; - signal read_enable: std_logic; - signal write_enable: std_logic; - signal fifo_gsr: std_logic; - signal read_data: std_logic_vector(17 downto 0); - signal write_data: std_logic_vector(17 downto 0); - signal full: std_logic; - signal empty: std_logic; - signal read_addr: std_logic_vector(9 downto 0); - signal read_addrgray: std_logic_vector(8 downto 0); - signal read_nextgray: std_logic_vector(8 downto 0); - signal read_lastgray: std_logic_vector(8 downto 0); - signal write_addr: std_logic_vector(9 downto 0); - signal write_addrgray: std_logic_vector(8 downto 0); - signal write_nextgray: std_logic_vector(8 downto 0); - signal fifostatus: std_logic_vector(8 downto 0); - signal read_allow: std_logic; - signal write_allow: std_logic; - signal empty_allow: std_logic; - signal full_allow: std_logic; - signal ecomp: std_logic_vector(8 downto 0); - signal fcomp: std_logic_vector(8 downto 0); - signal emuxcyo: std_logic_vector(8 downto 0); - signal fmuxcyo: std_logic_vector(8 downto 0); - signal emptyg: std_logic; - signal fullg: std_logic; - signal read_truegray: std_logic_vector(8 downto 0); - signal rag_writesync: std_logic_vector(8 downto 0); - signal ra_writesync: std_logic_vector(8 downto 0); - signal write_addrr: std_logic_vector(8 downto 0); - signal xorout: std_logic_vector(1 downto 0); - signal gnd_bus: std_logic_vector(17 downto 0); - signal gnd: std_logic; - signal pwr: std_logic; - -component BUFG - port ( - I: IN std_logic; - O: OUT std_logic); -end component; - -component MUXCY_L - port ( - DI: IN std_logic; - CI: IN std_logic; - S: IN std_logic; - LO: OUT std_logic); -end component; -attribute BOX_TYPE of MUXCY_L : component is "BLACK_BOX"; - -component RAMB16_S18_S18 - port ( - ADDRA: IN std_logic_vector(9 downto 0); - ADDRB: IN std_logic_vector(9 downto 0); - DIA: IN std_logic_vector(15 downto 0); - DIB: IN std_logic_vector(15 downto 0); - DIPA: IN std_logic_vector(1 downto 0); - DIPB: IN std_logic_vector(1 downto 0); - WEA: IN std_logic; - WEB: IN std_logic; - CLKA: IN std_logic; - CLKB: IN std_logic; - SSRA: IN std_logic; - SSRB: IN std_logic; - ENA: IN std_logic; - ENB: IN std_logic; - DOA: OUT std_logic_vector(15 downto 0); - DOB: OUT std_logic_vector(15 downto 0); - DOPA: OUT std_logic_vector(1 downto 0); - DOPB: OUT std_logic_vector(1 downto 0)); -end component; -attribute BOX_TYPE of RAMB16_S18_S18 : component is "BLACK_BOX"; - - -BEGIN - read_enable <= read_enable_in; - write_enable <= write_enable_in; - fifo_gsr <= fifo_gsr_in; - write_data <= write_data_in; - read_data_out <= read_data; - full_out <= full; - empty_out <= empty; - fifostatus_out <= fifostatus(8 downto 5); - gnd_bus <= "000000000000000000"; - gnd <= '0'; - pwr <= '1'; - - read_addr(9) <= '0'; - write_addr(9) <= '0'; - - --------------------------------------------------------------------------- --- -- --- Global input clock buffers are instantianted for both the read_clock -- --- and the write_clock, to avoid skew problems. -- --- -- --------------------------------------------------------------------------- -read_clock <= read_clock_in; -write_clock <= write_clock_in; ---gclk1: BUFG port map (I => read_clock_in, O => read_clock); ---gclk2: BUFG port map (I => write_clock_in, O => write_clock); - --------------------------------------------------------------------------- --- -- --- Block RAM instantiation for FIFO. Module is 512x18, of which one -- --- address location is sacrificed for the overall speed of the design. -- --- -- --------------------------------------------------------------------------- - -bram1: RAMB16_S18_S18 port map (ADDRA => read_addr, ADDRB => write_addr, - DIA => gnd_bus(15 downto 0), DIPA => gnd_bus(17 downto 16), - DIB => write_data(15 downto 0), DIPB => write_data(17 downto 16), - WEA => gnd, WEB => pwr, CLKA => read_clock, CLKB => write_clock, - SSRA => gnd, SSRB => gnd, ENA => read_allow, ENB => write_allow, - DOA => read_data(15 downto 0), DOPA => read_data(17 downto 16) ); - ----------------------------------------------------------------- --- -- --- Allow flags determine whether FIFO control logic can -- --- operate. If read_enable is driven high, and the FIFO is -- --- not Empty, then Reads are allowed. Similarly, if the -- --- write_enable signal is high, and the FIFO is not Full, -- --- then Writes are allowed. -- --- -- ----------------------------------------------------------------- - -read_allow <= (read_enable AND NOT empty); -write_allow <= (write_enable AND NOT full); - -full_allow <= (full OR write_enable); -empty_allow <= (empty OR read_enable); - ---------------------------------------------------------------- --- -- --- Empty flag is set on fifo_gsr (initial), or when gray -- --- code counters are equal, or when there is one word in -- --- the FIFO, and a Read operation is about to be performed. -- --- -- ---------------------------------------------------------------- - -proc1: PROCESS (read_clock) -BEGIN - if rising_edge(read_clock) then - IF (fifo_gsr = '1') THEN - empty <= '1'; - ELSIF (empty_allow = '1') THEN - empty <= emptyg; - end IF; - end IF; -end PROCESS proc1; - ---------------------------------------------------------------- --- -- --- Full flag is set on fifo_gsr (initial, but it is cleared -- --- on the first valid write_clock edge after fifo_gsr is -- --- de-asserted), or when Gray-code counters are one away -- --- from being equal (the Write Gray-code address is equal -- --- to the Last Read Gray-code address), or when the Next -- --- Write Gray-code address is equal to the Last Read Gray- -- --- code address, and a Write operation is about to be -- --- performed. -- --- -- ---------------------------------------------------------------- - -proc2: PROCESS (write_clock) -BEGIN - if rising_edge(write_clock) then - IF (fifo_gsr = '1') THEN - full <= '1'; - ELSIF (full_allow = '1') THEN - full <= fullg; - end IF; - end IF; -end PROCESS proc2; - ----------------------------------------------------------------- --- -- --- Generation of Read address pointers. The primary one is -- --- binary (read_addr), and the Gray-code derivatives are -- --- generated via pipelining the binary-to-Gray-code result. -- --- The initial values are important, so they're in sequence. -- --- -- --- Grey-code addresses are used so that the registered -- --- Full and Empty flags are always clean, and never in an -- --- unknown state due to the asynchonous relationship of the -- --- Read and Write clocks. In the worst case scenario, Full -- --- and Empty would simply stay active one cycle longer, but -- --- it would not generate an error or give false values. -- --- -- ----------------------------------------------------------------- - -proc3: PROCESS (read_clock) -BEGIN - if rising_edge(read_clock) then - IF (fifo_gsr = '1') THEN - read_addr(8 downto 0) <= "000000000"; - ELSIF (read_allow = '1') THEN - read_addr(8 downto 0) <= read_addr(8 downto 0) + 1; - end IF; - end IF; -end PROCESS proc3; - -proc4: PROCESS (read_clock) -BEGIN - if rising_edge(read_clock) then - IF (fifo_gsr = '1') THEN - read_nextgray <= "100000000"; - ELSIF (read_allow = '1') THEN - read_nextgray(8) <= read_addr(8); - read_nextgray(7) <= read_addr(8) XOR read_addr(7); - read_nextgray(6) <= read_addr(7) XOR read_addr(6); - read_nextgray(5) <= read_addr(6) XOR read_addr(5); - read_nextgray(4) <= read_addr(5) XOR read_addr(4); - read_nextgray(3) <= read_addr(4) XOR read_addr(3); - read_nextgray(2) <= read_addr(3) XOR read_addr(2); - read_nextgray(1) <= read_addr(2) XOR read_addr(1); - read_nextgray(0) <= read_addr(1) XOR read_addr(0); - end IF; - end IF; -end PROCESS proc4; - -proc5: PROCESS (read_clock) -BEGIN - if rising_edge(read_clock) then - IF (fifo_gsr = '1') THEN - read_addrgray <= "100000001"; - ELSIF (read_allow = '1') THEN - read_addrgray <= read_nextgray; - end IF; - end IF; -end PROCESS proc5; - -proc6: PROCESS (read_clock) -BEGIN - if rising_edge(read_clock) then - IF (fifo_gsr = '1') THEN - read_lastgray <= "100000011"; - ELSIF (read_allow = '1') THEN - read_lastgray <= read_addrgray; - end IF; - end IF; -end PROCESS proc6; - ----------------------------------------------------------------- --- -- --- Generation of Write address pointers. Identical copy of -- --- read pointer generation above, except for names. -- --- -- ----------------------------------------------------------------- - -proc7: PROCESS (write_clock) +-- signal read_clock: std_logic; +-- signal write_clock: std_logic; +-- signal read_enable: std_logic; +-- signal write_enable: std_logic; +-- signal fifo_gsr: std_logic; +-- signal read_data: std_logic_vector(17 downto 0); +-- signal write_data: std_logic_vector(17 downto 0); +-- signal full: std_logic; +-- signal empty: std_logic; +-- signal read_addr: std_logic_vector(9 downto 0); +-- signal read_addrgray: std_logic_vector(8 downto 0); +-- signal read_nextgray: std_logic_vector(8 downto 0); +-- signal read_lastgray: std_logic_vector(8 downto 0); +-- signal write_addr: std_logic_vector(9 downto 0); +-- signal write_addrgray: std_logic_vector(8 downto 0); +-- signal write_nextgray: std_logic_vector(8 downto 0); +-- signal fifostatus: std_logic_vector(8 downto 0); +-- signal read_allow: std_logic; +-- signal write_allow: std_logic; +-- signal empty_allow: std_logic; +-- signal full_allow: std_logic; +-- signal ecomp: std_logic_vector(8 downto 0); +-- signal fcomp: std_logic_vector(8 downto 0); +-- signal emuxcyo: std_logic_vector(8 downto 0); +-- signal fmuxcyo: std_logic_vector(8 downto 0); +-- signal emptyg: std_logic; +-- signal fullg: std_logic; +-- signal read_truegray: std_logic_vector(8 downto 0); +-- signal rag_writesync: std_logic_vector(8 downto 0); +-- signal ra_writesync: std_logic_vector(8 downto 0); +-- signal write_addrr: std_logic_vector(8 downto 0); +-- signal xorout: std_logic_vector(1 downto 0); +-- signal gnd_bus: std_logic_vector(17 downto 0); +-- signal gnd: std_logic; +-- signal pwr: std_logic; +-- +-- component BUFG +-- port ( +-- I: IN std_logic; +-- O: OUT std_logic); +-- end component; +-- +-- component MUXCY_L +-- port ( +-- DI: IN std_logic; +-- CI: IN std_logic; +-- S: IN std_logic; +-- LO: OUT std_logic); +-- end component; +-- attribute BOX_TYPE of MUXCY_L : component is "BLACK_BOX"; +-- +-- component RAMB16_S18_S18 +-- port ( +-- ADDRA: IN std_logic_vector(9 downto 0); +-- ADDRB: IN std_logic_vector(9 downto 0); +-- DIA: IN std_logic_vector(15 downto 0); +-- DIB: IN std_logic_vector(15 downto 0); +-- DIPA: IN std_logic_vector(1 downto 0); +-- DIPB: IN std_logic_vector(1 downto 0); +-- WEA: IN std_logic; +-- WEB: IN std_logic; +-- CLKA: IN std_logic; +-- CLKB: IN std_logic; +-- SSRA: IN std_logic; +-- SSRB: IN std_logic; +-- ENA: IN std_logic; +-- ENB: IN std_logic; +-- DOA: OUT std_logic_vector(15 downto 0); +-- DOB: OUT std_logic_vector(15 downto 0); +-- DOPA: OUT std_logic_vector(1 downto 0); +-- DOPB: OUT std_logic_vector(1 downto 0)); +-- end component; +--attribute BOX_TYPE of RAMB16_S18_S18 : component is "BLACK_BOX"; + component xilinx_fifo_dualport_18x1k_4 + port ( + din: IN std_logic_VECTOR(17 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + prog_empty: OUT std_logic; + valid: OUT std_logic; + underflow: OUT std_logic); + end component; +-- read_clock_in: IN std_logic; +-- write_clock_in: IN std_logic; +-- read_enable_in: IN std_logic; +-- write_enable_in: IN std_logic; +-- fifo_gsr_in: IN std_logic; +-- write_data_in: IN std_logic_vector(17 downto 0); +-- read_data_out: OUT std_logic_vector(17 downto 0); +-- full_out: OUT std_logic; +-- empty_out: OUT std_logic; +-- fifostatus_out: OUT std_logic_vector(3 downto 0) --counter for 1/16th of fifo BEGIN - if rising_edge(write_clock) then - IF (fifo_gsr = '1') THEN - write_addr(8 downto 0) <= "000000000"; - ELSIF (write_allow = '1') THEN - write_addr(8 downto 0) <= write_addr(8 downto 0) + 1; - end IF; - end IF; -end PROCESS proc7; - -proc8: PROCESS (write_clock) -BEGIN - if rising_edge(write_clock) then - IF (fifo_gsr = '1') THEN - write_nextgray <= "100000000"; - ELSIF (write_allow = '1') THEN - write_nextgray(8) <= write_addr(8); - write_nextgray(7) <= write_addr(8) XOR write_addr(7); - write_nextgray(6) <= write_addr(7) XOR write_addr(6); - write_nextgray(5) <= write_addr(6) XOR write_addr(5); - write_nextgray(4) <= write_addr(5) XOR write_addr(4); - write_nextgray(3) <= write_addr(4) XOR write_addr(3); - write_nextgray(2) <= write_addr(3) XOR write_addr(2); - write_nextgray(1) <= write_addr(2) XOR write_addr(1); - write_nextgray(0) <= write_addr(1) XOR write_addr(0); - end IF; - end IF; -end PROCESS proc8; - -proc9: PROCESS (write_clock) -BEGIN - if rising_edge(write_clock) then - IF (fifo_gsr = '1') THEN - write_addrgray <= "100000001"; - ELSIF (write_allow = '1') THEN - write_addrgray <= write_nextgray; - end IF; - end IF; -end PROCESS proc9; - ----------------------------------------------------------------- --- -- --- Alternative generation of FIFOstatus outputs. Used to -- --- determine how full FIFO is, based on how far the Write -- --- pointer is ahead of the Read pointer. read_truegray -- --- is synchronized to write_clock (rag_writesync), converted -- --- to binary (ra_writesync), and then subtracted from the -- --- pipelined write_addr (write_addrr) to find out how many -- --- words are in the FIFO (fifostatus). The top bits are -- --- then 1/2 full, 1/4 full, etc. (not mutually exclusive). -- --- fifostatus has a one-cycle latency on write_clock; or, -- --- one cycle after the write address is incremented on a -- --- write operation, fifostatus is updated with the new -- --- capacity information. There is a two-cycle latency on -- --- read operations. -- --- -- --- If read_clock is much faster than write_clock, it is -- --- possible that the fifostatus counter could drop several -- --- positions in one write_clock cycle, so the low-order bits -- --- of fifostatus are not as reliable. -- --- -- --- NOTE: If the fifostatus flags are not needed, then this -- --- section of logic can be trimmed, saving 20+ slices and -- --- improving the circuit performance. -- --- -- ----------------------------------------------------------------- -gen_status0 : if USE_STATUS_FLAGS = 0 generate - fifostatus <= (others => '0'); -end generate; - -gen_status : if USE_STATUS_FLAGS = 1 generate - - proc10: PROCESS (read_clock, fifo_gsr) - BEGIN - IF (fifo_gsr = '1') THEN - read_truegray <= "000000000"; - ELSIF (read_clock'EVENT AND read_clock = '1') THEN - read_truegray(8) <= read_addr(8); - read_truegray(7) <= read_addr(8) XOR read_addr(7); - read_truegray(6) <= read_addr(7) XOR read_addr(6); - read_truegray(5) <= read_addr(6) XOR read_addr(5); - read_truegray(4) <= read_addr(5) XOR read_addr(4); - read_truegray(3) <= read_addr(4) XOR read_addr(3); - read_truegray(2) <= read_addr(3) XOR read_addr(2); - read_truegray(1) <= read_addr(2) XOR read_addr(1); - read_truegray(0) <= read_addr(1) XOR read_addr(0); - end IF; - end PROCESS proc10; - - proc11: PROCESS (write_clock, fifo_gsr) - BEGIN - IF (fifo_gsr = '1') THEN - rag_writesync <= "000000000"; - ELSIF (write_clock'EVENT AND write_clock = '1') THEN - rag_writesync <= read_truegray; - end IF; - end PROCESS proc11; - - xorout(0) <= (rag_writesync(8) XOR rag_writesync(7) XOR rag_writesync(6) XOR - rag_writesync(5)); - xorout(1) <= (rag_writesync(4) XOR rag_writesync(3) XOR rag_writesync(2) XOR - rag_writesync(1)); - - ra_writesync(8) <= rag_writesync(8); - ra_writesync(7) <= (rag_writesync(8) XOR rag_writesync(7)); - ra_writesync(6) <= (rag_writesync(8) XOR rag_writesync(7) XOR rag_writesync(6)); - ra_writesync(5) <= xorout(0); - ra_writesync(4) <= (xorout(0) XOR rag_writesync(4)); - ra_writesync(3) <= (xorout(0) XOR rag_writesync(4) XOR rag_writesync(3)); - ra_writesync(2) <= (xorout(0) XOR rag_writesync(4) XOR rag_writesync(3) - XOR rag_writesync(2)); - ra_writesync(1) <= (xorout(0) XOR xorout(1)); - ra_writesync(0) <= (xorout(0) XOR xorout(1) XOR rag_writesync(0)); - - proc12: PROCESS (write_clock, fifo_gsr) - BEGIN - IF (fifo_gsr = '1') THEN - write_addrr <= "000000000"; - ELSIF (write_clock'EVENT AND write_clock = '1') THEN - write_addrr <= write_addr(8 downto 0); - end IF; - end PROCESS proc12; - - proc13: PROCESS (write_clock, fifo_gsr) - BEGIN - IF (fifo_gsr = '1') THEN - fifostatus <= "000000000"; - ELSIF (write_clock'EVENT AND write_clock = '1') THEN - IF (full = '0') THEN - fifostatus <= (write_addrr - ra_writesync); - end IF; - end IF; - end PROCESS proc13; -end generate; ----------------------------------------------------------------- --- -- --- The two conditions decoded with special carry logic are -- --- Empty and Full (gated versions). These are used to -- --- determine the next state of the Full/Empty flags. Carry -- --- logic is used for optimal speed. (The previous -- --- implementation of AlmostEmpty and AlmostFull have been -- --- wrapped into the corresponding carry chains for faster -- --- performance). -- --- -- --- When write_addrgray is equal to read_addrgray, the FIFO -- --- is Empty, and emptyg (combinatorial) is asserted. Or, -- --- when write_addrgray is equal to read_nextgray (1 word in -- --- the FIFO) then the FIFO potentially could be going Empty, -- --- so emptyg is asserted, and the Empty flip-flop enable is -- --- gated with empty_allow, which is conditioned with a valid -- --- read. -- --- -- --- Similarly, when read_lastgray is equal to write_addrgray, -- --- the FIFO is full (511 addresses). Or, when read_lastgray -- --- is equal to write_nextgray, then the FIFO potentially -- --- could be going Full, so fullg is asserted, and the Full -- --- flip-flop enable is gated with full_allow, which is -- --- conditioned with a valid write. -- --- -- --- Note: To have utilized the full address space (512) -- --- would have required extra logic to determine Full/Empty -- --- on equal addresses, and this would have slowed down the -- --- overall performance, which was the top priority. -- --- -- ----------------------------------------------------------------- - -ecomp(0) <= (NOT (write_addrgray(0) XOR read_addrgray(0)) AND empty) OR - (NOT (write_addrgray(0) XOR read_nextgray(0)) AND NOT empty); -ecomp(1) <= (NOT (write_addrgray(1) XOR read_addrgray(1)) AND empty) OR - (NOT (write_addrgray(1) XOR read_nextgray(1)) AND NOT empty); -ecomp(2) <= (NOT (write_addrgray(2) XOR read_addrgray(2)) AND empty) OR - (NOT (write_addrgray(2) XOR read_nextgray(2)) AND NOT empty); -ecomp(3) <= (NOT (write_addrgray(3) XOR read_addrgray(3)) AND empty) OR - (NOT (write_addrgray(3) XOR read_nextgray(3)) AND NOT empty); -ecomp(4) <= (NOT (write_addrgray(4) XOR read_addrgray(4)) AND empty) OR - (NOT (write_addrgray(4) XOR read_nextgray(4)) AND NOT empty); -ecomp(5) <= (NOT (write_addrgray(5) XOR read_addrgray(5)) AND empty) OR - (NOT (write_addrgray(5) XOR read_nextgray(5)) AND NOT empty); -ecomp(6) <= (NOT (write_addrgray(6) XOR read_addrgray(6)) AND empty) OR - (NOT (write_addrgray(6) XOR read_nextgray(6)) AND NOT empty); -ecomp(7) <= (NOT (write_addrgray(7) XOR read_addrgray(7)) AND empty) OR - (NOT (write_addrgray(7) XOR read_nextgray(7)) AND NOT empty); -ecomp(8) <= (NOT (write_addrgray(8) XOR read_addrgray(8)) AND empty) OR - (NOT (write_addrgray(8) XOR read_nextgray(8)) AND NOT empty); - -emuxcy0: MUXCY_L port map (DI=>gnd,CI=>pwr, S=>ecomp(0),LO=>emuxcyo(0)); -emuxcy1: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(0),S=>ecomp(1),LO=>emuxcyo(1)); -emuxcy2: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(1),S=>ecomp(2),LO=>emuxcyo(2)); -emuxcy3: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(2),S=>ecomp(3),LO=>emuxcyo(3)); -emuxcy4: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(3),S=>ecomp(4),LO=>emuxcyo(4)); -emuxcy5: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(4),S=>ecomp(5),LO=>emuxcyo(5)); -emuxcy6: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(5),S=>ecomp(6),LO=>emuxcyo(6)); -emuxcy7: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(6),S=>ecomp(7),LO=>emuxcyo(7)); -emuxcy8: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(7),S=>ecomp(8),LO=>emptyg); - -fcomp(0) <= (NOT (read_lastgray(0) XOR write_addrgray(0)) AND full) OR - (NOT (read_lastgray(0) XOR write_nextgray(0)) AND NOT full); -fcomp(1) <= (NOT (read_lastgray(1) XOR write_addrgray(1)) AND full) OR - (NOT (read_lastgray(1) XOR write_nextgray(1)) AND NOT full); -fcomp(2) <= (NOT (read_lastgray(2) XOR write_addrgray(2)) AND full) OR - (NOT (read_lastgray(2) XOR write_nextgray(2)) AND NOT full); -fcomp(3) <= (NOT (read_lastgray(3) XOR write_addrgray(3)) AND full) OR - (NOT (read_lastgray(3) XOR write_nextgray(3)) AND NOT full); -fcomp(4) <= (NOT (read_lastgray(4) XOR write_addrgray(4)) AND full) OR - (NOT (read_lastgray(4) XOR write_nextgray(4)) AND NOT full); -fcomp(5) <= (NOT (read_lastgray(5) XOR write_addrgray(5)) AND full) OR - (NOT (read_lastgray(5) XOR write_nextgray(5)) AND NOT full); -fcomp(6) <= (NOT (read_lastgray(6) XOR write_addrgray(6)) AND full) OR - (NOT (read_lastgray(6) XOR write_nextgray(6)) AND NOT full); -fcomp(7) <= (NOT (read_lastgray(7) XOR write_addrgray(7)) AND full) OR - (NOT (read_lastgray(7) XOR write_nextgray(7)) AND NOT full); -fcomp(8) <= (NOT (read_lastgray(8) XOR write_addrgray(8)) AND full) OR - (NOT (read_lastgray(8) XOR write_nextgray(8)) AND NOT full); - -fmuxcy0: MUXCY_L port map (DI=>gnd,CI=>pwr, S=>fcomp(0),LO=>fmuxcyo(0)); -fmuxcy1: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(0),S=>fcomp(1),LO=>fmuxcyo(1)); -fmuxcy2: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(1),S=>fcomp(2),LO=>fmuxcyo(2)); -fmuxcy3: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(2),S=>fcomp(3),LO=>fmuxcyo(3)); -fmuxcy4: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(3),S=>fcomp(4),LO=>fmuxcyo(4)); -fmuxcy5: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(4),S=>fcomp(5),LO=>fmuxcyo(5)); -fmuxcy6: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(5),S=>fcomp(6),LO=>fmuxcyo(6)); -fmuxcy7: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(6),S=>fcomp(7),LO=>fmuxcyo(7)); -fmuxcy8: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(7),S=>fcomp(8),LO=>fullg); +FIFO_DP_BRAM : xilinx_fifo_dualport_18x1k_4 + port map ( + din => write_data_in, + rd_clk => read_clock_in, + rd_en => read_enable_in, + rst => fifo_gsr_in, + wr_clk => write_clock_in, + wr_en => write_enable_in, + dout => read_data_out, + empty => empty_out, + full => full_out, + prog_empty => almost_empty_out, + valid => valid_read_out, + underflow => underflow_out + ); +-- read_enable <= read_enable_in; +-- write_enable <= write_enable_in; +-- fifo_gsr <= fifo_gsr_in; +-- write_data <= write_data_in; +-- read_data_out <= read_data; +-- full_out <= full; +-- empty_out <= empty; +-- fifostatus_out <= fifostatus(8 downto 5); +-- gnd_bus <= "000000000000000000"; +-- gnd <= '0'; +-- pwr <= '1'; +-- +-- read_addr(9) <= '0'; +-- write_addr(9) <= '0'; +-- +-- +-- -------------------------------------------------------------------------- +-- -- -- +-- -- Global input clock buffers are instantianted for both the read_clock -- +-- -- and the write_clock, to avoid skew problems. -- +-- -- -- +-- -------------------------------------------------------------------------- +-- read_clock <= read_clock_in; +-- write_clock <= write_clock_in; +-- --gclk1: BUFG port map (I => read_clock_in, O => read_clock); +-- --gclk2: BUFG port map (I => write_clock_in, O => write_clock); +-- +-- -------------------------------------------------------------------------- +-- -- -- +-- -- Block RAM instantiation for FIFO. Module is 512x18, of which one -- +-- -- address location is sacrificed for the overall speed of the design. -- +-- -- -- +-- -------------------------------------------------------------------------- +-- +-- bram1: RAMB16_S18_S18 port map (ADDRA => read_addr, ADDRB => write_addr, +-- DIA => gnd_bus(15 downto 0), DIPA => gnd_bus(17 downto 16), +-- DIB => write_data(15 downto 0), DIPB => write_data(17 downto 16), +-- WEA => gnd, WEB => pwr, CLKA => read_clock, CLKB => write_clock, +-- SSRA => gnd, SSRB => gnd, ENA => read_allow, ENB => write_allow, +-- DOA => read_data(15 downto 0), DOPA => read_data(17 downto 16) ); +-- +-- ---------------------------------------------------------------- +-- -- -- +-- -- Allow flags determine whether FIFO control logic can -- +-- -- operate. If read_enable is driven high, and the FIFO is -- +-- -- not Empty, then Reads are allowed. Similarly, if the -- +-- -- write_enable signal is high, and the FIFO is not Full, -- +-- -- then Writes are allowed. -- +-- -- -- +-- ---------------------------------------------------------------- +-- +-- read_allow <= (read_enable AND NOT empty); +-- write_allow <= (write_enable AND NOT full); +-- +-- full_allow <= (full OR write_enable); +-- empty_allow <= (empty OR read_enable); +-- +-- --------------------------------------------------------------- +-- -- -- +-- -- Empty flag is set on fifo_gsr (initial), or when gray -- +-- -- code counters are equal, or when there is one word in -- +-- -- the FIFO, and a Read operation is about to be performed. -- +-- -- -- +-- --------------------------------------------------------------- +-- +-- proc1: PROCESS (read_clock) +-- BEGIN +-- if rising_edge(read_clock) then +-- IF (fifo_gsr = '1') THEN +-- empty <= '1'; +-- ELSIF (empty_allow = '1') THEN +-- empty <= emptyg; +-- end IF; +-- end IF; +-- end PROCESS proc1; +-- +-- --------------------------------------------------------------- +-- -- -- +-- -- Full flag is set on fifo_gsr (initial, but it is cleared -- +-- -- on the first valid write_clock edge after fifo_gsr is -- +-- -- de-asserted), or when Gray-code counters are one away -- +-- -- from being equal (the Write Gray-code address is equal -- +-- -- to the Last Read Gray-code address), or when the Next -- +-- -- Write Gray-code address is equal to the Last Read Gray- -- +-- -- code address, and a Write operation is about to be -- +-- -- performed. -- +-- -- -- +-- --------------------------------------------------------------- +-- +-- proc2: PROCESS (write_clock) +-- BEGIN +-- if rising_edge(write_clock) then +-- IF (fifo_gsr = '1') THEN +-- full <= '1'; +-- ELSIF (full_allow = '1') THEN +-- full <= fullg; +-- end IF; +-- end IF; +-- end PROCESS proc2; +-- +-- ---------------------------------------------------------------- +-- -- -- +-- -- Generation of Read address pointers. The primary one is -- +-- -- binary (read_addr), and the Gray-code derivatives are -- +-- -- generated via pipelining the binary-to-Gray-code result. -- +-- -- The initial values are important, so they're in sequence. -- +-- -- -- +-- -- Grey-code addresses are used so that the registered -- +-- -- Full and Empty flags are always clean, and never in an -- +-- -- unknown state due to the asynchonous relationship of the -- +-- -- Read and Write clocks. In the worst case scenario, Full -- +-- -- and Empty would simply stay active one cycle longer, but -- +-- -- it would not generate an error or give false values. -- +-- -- -- +-- ---------------------------------------------------------------- +-- +-- proc3: PROCESS (read_clock) +-- BEGIN +-- if rising_edge(read_clock) then +-- IF (fifo_gsr = '1') THEN +-- read_addr(8 downto 0) <= "000000000"; +-- ELSIF (read_allow = '1') THEN +-- read_addr(8 downto 0) <= read_addr(8 downto 0) + 1; +-- end IF; +-- end IF; +-- end PROCESS proc3; +-- +-- proc4: PROCESS (read_clock) +-- BEGIN +-- if rising_edge(read_clock) then +-- IF (fifo_gsr = '1') THEN +-- read_nextgray <= "100000000"; +-- ELSIF (read_allow = '1') THEN +-- read_nextgray(8) <= read_addr(8); +-- read_nextgray(7) <= read_addr(8) XOR read_addr(7); +-- read_nextgray(6) <= read_addr(7) XOR read_addr(6); +-- read_nextgray(5) <= read_addr(6) XOR read_addr(5); +-- read_nextgray(4) <= read_addr(5) XOR read_addr(4); +-- read_nextgray(3) <= read_addr(4) XOR read_addr(3); +-- read_nextgray(2) <= read_addr(3) XOR read_addr(2); +-- read_nextgray(1) <= read_addr(2) XOR read_addr(1); +-- read_nextgray(0) <= read_addr(1) XOR read_addr(0); +-- end IF; +-- end IF; +-- end PROCESS proc4; +-- +-- proc5: PROCESS (read_clock) +-- BEGIN +-- if rising_edge(read_clock) then +-- IF (fifo_gsr = '1') THEN +-- read_addrgray <= "100000001"; +-- ELSIF (read_allow = '1') THEN +-- read_addrgray <= read_nextgray; +-- end IF; +-- end IF; +-- end PROCESS proc5; +-- +-- proc6: PROCESS (read_clock) +-- BEGIN +-- if rising_edge(read_clock) then +-- IF (fifo_gsr = '1') THEN +-- read_lastgray <= "100000011"; +-- ELSIF (read_allow = '1') THEN +-- read_lastgray <= read_addrgray; +-- end IF; +-- end IF; +-- end PROCESS proc6; +-- +-- ---------------------------------------------------------------- +-- -- -- +-- -- Generation of Write address pointers. Identical copy of -- +-- -- read pointer generation above, except for names. -- +-- -- -- +-- ---------------------------------------------------------------- +-- +-- proc7: PROCESS (write_clock) +-- BEGIN +-- if rising_edge(write_clock) then +-- IF (fifo_gsr = '1') THEN +-- write_addr(8 downto 0) <= "000000000"; +-- ELSIF (write_allow = '1') THEN +-- write_addr(8 downto 0) <= write_addr(8 downto 0) + 1; +-- end IF; +-- end IF; +-- end PROCESS proc7; +-- +-- proc8: PROCESS (write_clock) +-- BEGIN +-- if rising_edge(write_clock) then +-- IF (fifo_gsr = '1') THEN +-- write_nextgray <= "100000000"; +-- ELSIF (write_allow = '1') THEN +-- write_nextgray(8) <= write_addr(8); +-- write_nextgray(7) <= write_addr(8) XOR write_addr(7); +-- write_nextgray(6) <= write_addr(7) XOR write_addr(6); +-- write_nextgray(5) <= write_addr(6) XOR write_addr(5); +-- write_nextgray(4) <= write_addr(5) XOR write_addr(4); +-- write_nextgray(3) <= write_addr(4) XOR write_addr(3); +-- write_nextgray(2) <= write_addr(3) XOR write_addr(2); +-- write_nextgray(1) <= write_addr(2) XOR write_addr(1); +-- write_nextgray(0) <= write_addr(1) XOR write_addr(0); +-- end IF; +-- end IF; +-- end PROCESS proc8; +-- +-- proc9: PROCESS (write_clock) +-- BEGIN +-- if rising_edge(write_clock) then +-- IF (fifo_gsr = '1') THEN +-- write_addrgray <= "100000001"; +-- ELSIF (write_allow = '1') THEN +-- write_addrgray <= write_nextgray; +-- end IF; +-- end IF; +-- end PROCESS proc9; +-- +-- ---------------------------------------------------------------- +-- -- -- +-- -- Alternative generation of FIFOstatus outputs. Used to -- +-- -- determine how full FIFO is, based on how far the Write -- +-- -- pointer is ahead of the Read pointer. read_truegray -- +-- -- is synchronized to write_clock (rag_writesync), converted -- +-- -- to binary (ra_writesync), and then subtracted from the -- +-- -- pipelined write_addr (write_addrr) to find out how many -- +-- -- words are in the FIFO (fifostatus). The top bits are -- +-- -- then 1/2 full, 1/4 full, etc. (not mutually exclusive). -- +-- -- fifostatus has a one-cycle latency on write_clock; or, -- +-- -- one cycle after the write address is incremented on a -- +-- -- write operation, fifostatus is updated with the new -- +-- -- capacity information. There is a two-cycle latency on -- +-- -- read operations. -- +-- -- -- +-- -- If read_clock is much faster than write_clock, it is -- +-- -- possible that the fifostatus counter could drop several -- +-- -- positions in one write_clock cycle, so the low-order bits -- +-- -- of fifostatus are not as reliable. -- +-- -- -- +-- -- NOTE: If the fifostatus flags are not needed, then this -- +-- -- section of logic can be trimmed, saving 20+ slices and -- +-- -- improving the circuit performance. -- +-- -- -- +-- ---------------------------------------------------------------- +-- gen_status0 : if USE_STATUS_FLAGS = 0 generate +-- fifostatus <= (others => '0'); +-- end generate; +-- +-- gen_status : if USE_STATUS_FLAGS = 1 generate +-- +-- proc10: PROCESS (read_clock, fifo_gsr) +-- BEGIN +-- IF (fifo_gsr = '1') THEN +-- read_truegray <= "000000000"; +-- ELSIF (read_clock'EVENT AND read_clock = '1') THEN +-- read_truegray(8) <= read_addr(8); +-- read_truegray(7) <= read_addr(8) XOR read_addr(7); +-- read_truegray(6) <= read_addr(7) XOR read_addr(6); +-- read_truegray(5) <= read_addr(6) XOR read_addr(5); +-- read_truegray(4) <= read_addr(5) XOR read_addr(4); +-- read_truegray(3) <= read_addr(4) XOR read_addr(3); +-- read_truegray(2) <= read_addr(3) XOR read_addr(2); +-- read_truegray(1) <= read_addr(2) XOR read_addr(1); +-- read_truegray(0) <= read_addr(1) XOR read_addr(0); +-- end IF; +-- end PROCESS proc10; +-- +-- proc11: PROCESS (write_clock, fifo_gsr) +-- BEGIN +-- IF (fifo_gsr = '1') THEN +-- rag_writesync <= "000000000"; +-- ELSIF (write_clock'EVENT AND write_clock = '1') THEN +-- rag_writesync <= read_truegray; +-- end IF; +-- end PROCESS proc11; +-- +-- xorout(0) <= (rag_writesync(8) XOR rag_writesync(7) XOR rag_writesync(6) XOR +-- rag_writesync(5)); +-- xorout(1) <= (rag_writesync(4) XOR rag_writesync(3) XOR rag_writesync(2) XOR +-- rag_writesync(1)); +-- +-- ra_writesync(8) <= rag_writesync(8); +-- ra_writesync(7) <= (rag_writesync(8) XOR rag_writesync(7)); +-- ra_writesync(6) <= (rag_writesync(8) XOR rag_writesync(7) XOR rag_writesync(6)); +-- ra_writesync(5) <= xorout(0); +-- ra_writesync(4) <= (xorout(0) XOR rag_writesync(4)); +-- ra_writesync(3) <= (xorout(0) XOR rag_writesync(4) XOR rag_writesync(3)); +-- ra_writesync(2) <= (xorout(0) XOR rag_writesync(4) XOR rag_writesync(3) +-- XOR rag_writesync(2)); +-- ra_writesync(1) <= (xorout(0) XOR xorout(1)); +-- ra_writesync(0) <= (xorout(0) XOR xorout(1) XOR rag_writesync(0)); +-- +-- proc12: PROCESS (write_clock, fifo_gsr) +-- BEGIN +-- IF (fifo_gsr = '1') THEN +-- write_addrr <= "000000000"; +-- ELSIF (write_clock'EVENT AND write_clock = '1') THEN +-- write_addrr <= write_addr(8 downto 0); +-- end IF; +-- end PROCESS proc12; +-- +-- proc13: PROCESS (write_clock, fifo_gsr) +-- BEGIN +-- IF (fifo_gsr = '1') THEN +-- fifostatus <= "000000000"; +-- ELSIF (write_clock'EVENT AND write_clock = '1') THEN +-- IF (full = '0') THEN +-- fifostatus <= (write_addrr - ra_writesync); +-- end IF; +-- end IF; +-- end PROCESS proc13; +-- end generate; +-- ---------------------------------------------------------------- +-- -- -- +-- -- The two conditions decoded with special carry logic are -- +-- -- Empty and Full (gated versions). These are used to -- +-- -- determine the next state of the Full/Empty flags. Carry -- +-- -- logic is used for optimal speed. (The previous -- +-- -- implementation of AlmostEmpty and AlmostFull have been -- +-- -- wrapped into the corresponding carry chains for faster -- +-- -- performance). -- +-- -- -- +-- -- When write_addrgray is equal to read_addrgray, the FIFO -- +-- -- is Empty, and emptyg (combinatorial) is asserted. Or, -- +-- -- when write_addrgray is equal to read_nextgray (1 word in -- +-- -- the FIFO) then the FIFO potentially could be going Empty, -- +-- -- so emptyg is asserted, and the Empty flip-flop enable is -- +-- -- gated with empty_allow, which is conditioned with a valid -- +-- -- read. -- +-- -- -- +-- -- Similarly, when read_lastgray is equal to write_addrgray, -- +-- -- the FIFO is full (511 addresses). Or, when read_lastgray -- +-- -- is equal to write_nextgray, then the FIFO potentially -- +-- -- could be going Full, so fullg is asserted, and the Full -- +-- -- flip-flop enable is gated with full_allow, which is -- +-- -- conditioned with a valid write. -- +-- -- -- +-- -- Note: To have utilized the full address space (512) -- +-- -- would have required extra logic to determine Full/Empty -- +-- -- on equal addresses, and this would have slowed down the -- +-- -- overall performance, which was the top priority. -- +-- -- -- +-- ---------------------------------------------------------------- +-- +-- ecomp(0) <= (NOT (write_addrgray(0) XOR read_addrgray(0)) AND empty) OR +-- (NOT (write_addrgray(0) XOR read_nextgray(0)) AND NOT empty); +-- ecomp(1) <= (NOT (write_addrgray(1) XOR read_addrgray(1)) AND empty) OR +-- (NOT (write_addrgray(1) XOR read_nextgray(1)) AND NOT empty); +-- ecomp(2) <= (NOT (write_addrgray(2) XOR read_addrgray(2)) AND empty) OR +-- (NOT (write_addrgray(2) XOR read_nextgray(2)) AND NOT empty); +-- ecomp(3) <= (NOT (write_addrgray(3) XOR read_addrgray(3)) AND empty) OR +-- (NOT (write_addrgray(3) XOR read_nextgray(3)) AND NOT empty); +-- ecomp(4) <= (NOT (write_addrgray(4) XOR read_addrgray(4)) AND empty) OR +-- (NOT (write_addrgray(4) XOR read_nextgray(4)) AND NOT empty); +-- ecomp(5) <= (NOT (write_addrgray(5) XOR read_addrgray(5)) AND empty) OR +-- (NOT (write_addrgray(5) XOR read_nextgray(5)) AND NOT empty); +-- ecomp(6) <= (NOT (write_addrgray(6) XOR read_addrgray(6)) AND empty) OR +-- (NOT (write_addrgray(6) XOR read_nextgray(6)) AND NOT empty); +-- ecomp(7) <= (NOT (write_addrgray(7) XOR read_addrgray(7)) AND empty) OR +-- (NOT (write_addrgray(7) XOR read_nextgray(7)) AND NOT empty); +-- ecomp(8) <= (NOT (write_addrgray(8) XOR read_addrgray(8)) AND empty) OR +-- (NOT (write_addrgray(8) XOR read_nextgray(8)) AND NOT empty); +-- +-- emuxcy0: MUXCY_L port map (DI=>gnd,CI=>pwr, S=>ecomp(0),LO=>emuxcyo(0)); +-- emuxcy1: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(0),S=>ecomp(1),LO=>emuxcyo(1)); +-- emuxcy2: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(1),S=>ecomp(2),LO=>emuxcyo(2)); +-- emuxcy3: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(2),S=>ecomp(3),LO=>emuxcyo(3)); +-- emuxcy4: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(3),S=>ecomp(4),LO=>emuxcyo(4)); +-- emuxcy5: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(4),S=>ecomp(5),LO=>emuxcyo(5)); +-- emuxcy6: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(5),S=>ecomp(6),LO=>emuxcyo(6)); +-- emuxcy7: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(6),S=>ecomp(7),LO=>emuxcyo(7)); +-- emuxcy8: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(7),S=>ecomp(8),LO=>emptyg); +-- +-- fcomp(0) <= (NOT (read_lastgray(0) XOR write_addrgray(0)) AND full) OR +-- (NOT (read_lastgray(0) XOR write_nextgray(0)) AND NOT full); +-- fcomp(1) <= (NOT (read_lastgray(1) XOR write_addrgray(1)) AND full) OR +-- (NOT (read_lastgray(1) XOR write_nextgray(1)) AND NOT full); +-- fcomp(2) <= (NOT (read_lastgray(2) XOR write_addrgray(2)) AND full) OR +-- (NOT (read_lastgray(2) XOR write_nextgray(2)) AND NOT full); +-- fcomp(3) <= (NOT (read_lastgray(3) XOR write_addrgray(3)) AND full) OR +-- (NOT (read_lastgray(3) XOR write_nextgray(3)) AND NOT full); +-- fcomp(4) <= (NOT (read_lastgray(4) XOR write_addrgray(4)) AND full) OR +-- (NOT (read_lastgray(4) XOR write_nextgray(4)) AND NOT full); +-- fcomp(5) <= (NOT (read_lastgray(5) XOR write_addrgray(5)) AND full) OR +-- (NOT (read_lastgray(5) XOR write_nextgray(5)) AND NOT full); +-- fcomp(6) <= (NOT (read_lastgray(6) XOR write_addrgray(6)) AND full) OR +-- (NOT (read_lastgray(6) XOR write_nextgray(6)) AND NOT full); +-- fcomp(7) <= (NOT (read_lastgray(7) XOR write_addrgray(7)) AND full) OR +-- (NOT (read_lastgray(7) XOR write_nextgray(7)) AND NOT full); +-- fcomp(8) <= (NOT (read_lastgray(8) XOR write_addrgray(8)) AND full) OR +-- (NOT (read_lastgray(8) XOR write_nextgray(8)) AND NOT full); +-- +-- fmuxcy0: MUXCY_L port map (DI=>gnd,CI=>pwr, S=>fcomp(0),LO=>fmuxcyo(0)); +-- fmuxcy1: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(0),S=>fcomp(1),LO=>fmuxcyo(1)); +-- fmuxcy2: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(1),S=>fcomp(2),LO=>fmuxcyo(2)); +-- fmuxcy3: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(2),S=>fcomp(3),LO=>fmuxcyo(3)); +-- fmuxcy4: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(3),S=>fcomp(4),LO=>fmuxcyo(4)); +-- fmuxcy5: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(4),S=>fcomp(5),LO=>fmuxcyo(5)); +-- fmuxcy6: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(5),S=>fcomp(6),LO=>fmuxcyo(6)); +-- fmuxcy7: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(6),S=>fcomp(7),LO=>fmuxcyo(7)); +-- fmuxcy8: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(7),S=>fcomp(8),LO=>fullg); +-- end architecture trb_net_fifo_16bit_bram_dualport_arch; diff --git a/xilinx/virtex2/simulation/xilinx_fifo_18x16.vhd b/xilinx/virtex2/simulation/xilinx_fifo_18x16.vhd new file mode 100644 index 0000000..c5cdd7a --- /dev/null +++ b/xilinx/virtex2/simulation/xilinx_fifo_18x16.vhd @@ -0,0 +1,136 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2005 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file xilinx_fifo_18x16.vhd when simulating +-- the core, xilinx_fifo_18x16. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synopsys directives "translate_off/translate_on" specified +-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synopsys translate_off +Library XilinxCoreLib; +-- synopsys translate_on +ENTITY xilinx_fifo_18x16 IS + port ( + clk: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + rd_en: IN std_logic; + rst: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + empty: OUT std_logic; + full: OUT std_logic); +END xilinx_fifo_18x16; + +ARCHITECTURE xilinx_fifo_18x16_a OF xilinx_fifo_18x16 IS +-- synopsys translate_off +component wrapped_xilinx_fifo_18x16 + port ( + clk: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + rd_en: IN std_logic; + rst: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + empty: OUT std_logic; + full: OUT std_logic); +end component; + +-- Configuration specification + for all : wrapped_xilinx_fifo_18x16 use entity XilinxCoreLib.fifo_generator_v2_1(behavioral) + generic map( + c_wr_response_latency => 1, + c_has_rd_data_count => 0, + c_din_width => 18, + c_has_wr_data_count => 0, + c_implementation_type => 1, + c_family => "virtex2", + c_has_wr_rst => 0, + c_underflow_low => 0, + c_has_meminit_file => 0, + c_has_overflow => 0, + c_preload_latency => 1, + c_dout_width => 18, + c_rd_depth => 64, + c_default_value => "BlankString", + c_mif_file_name => "BlankString", + c_has_underflow => 0, + c_has_rd_rst => 0, + c_has_almost_full => 0, + c_has_rst => 1, + c_data_count_width => 2, + c_has_wr_ack => 0, + c_wr_ack_low => 0, + c_common_clock => 1, + c_rd_pntr_width => 6, + c_has_almost_empty => 0, + c_rd_data_count_width => 2, + c_enable_rlocs => 0, + c_wr_pntr_width => 6, + c_overflow_low => 0, + c_prog_empty_type => 0, + c_optimization_mode => 0, + c_wr_data_count_width => 2, + c_preload_regs => 0, + c_dout_rst_val => "0", + c_has_data_count => 0, + c_prog_full_thresh_negate_val => 12, + c_wr_depth => 64, + c_prog_empty_thresh_negate_val => 4, + c_prog_empty_thresh_assert_val => 4, + c_has_valid => 0, + c_init_wr_pntr_val => 0, + c_prog_full_thresh_assert_val => 12, + c_has_backup => 0, + c_valid_low => 0, + c_prim_fifo_type => 512, + c_count_type => 0, + c_prog_full_type => 0, + c_memory_type => 3); +-- synopsys translate_on +BEGIN +-- synopsys translate_off +U0 : wrapped_xilinx_fifo_18x16 + port map ( + clk => clk, + din => din, + rd_en => rd_en, + rst => rst, + wr_en => wr_en, + dout => dout, + empty => empty, + full => full); +-- synopsys translate_on + +END xilinx_fifo_18x16_a; + diff --git a/xilinx/virtex2/simulation/xilinx_fifo_18x1k.vhd b/xilinx/virtex2/simulation/xilinx_fifo_18x1k.vhd new file mode 100644 index 0000000..7a10a72 --- /dev/null +++ b/xilinx/virtex2/simulation/xilinx_fifo_18x1k.vhd @@ -0,0 +1,136 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2005 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file xilinx_fifo_18x1k.vhd when simulating +-- the core, xilinx_fifo_18x1k. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synopsys directives "translate_off/translate_on" specified +-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synopsys translate_off +Library XilinxCoreLib; +-- synopsys translate_on +ENTITY xilinx_fifo_18x1k IS + port ( + clk: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + rd_en: IN std_logic; + rst: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + empty: OUT std_logic; + full: OUT std_logic); +END xilinx_fifo_18x1k; + +ARCHITECTURE xilinx_fifo_18x1k_a OF xilinx_fifo_18x1k IS +-- synopsys translate_off +component wrapped_xilinx_fifo_18x1k + port ( + clk: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + rd_en: IN std_logic; + rst: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + empty: OUT std_logic; + full: OUT std_logic); +end component; + +-- Configuration specification + for all : wrapped_xilinx_fifo_18x1k use entity XilinxCoreLib.fifo_generator_v2_1(behavioral) + generic map( + c_wr_response_latency => 1, + c_has_rd_data_count => 0, + c_din_width => 18, + c_has_wr_data_count => 0, + c_implementation_type => 0, + c_family => "virtex2", + c_has_wr_rst => 0, + c_underflow_low => 0, + c_has_meminit_file => 0, + c_has_overflow => 0, + c_preload_latency => 1, + c_dout_width => 18, + c_rd_depth => 1024, + c_default_value => "BlankString", + c_mif_file_name => "BlankString", + c_has_underflow => 0, + c_has_rd_rst => 0, + c_has_almost_full => 0, + c_has_rst => 1, + c_data_count_width => 2, + c_has_wr_ack => 0, + c_wr_ack_low => 0, + c_common_clock => 1, + c_rd_pntr_width => 10, + c_has_almost_empty => 0, + c_rd_data_count_width => 2, + c_enable_rlocs => 0, + c_wr_pntr_width => 10, + c_overflow_low => 0, + c_prog_empty_type => 0, + c_optimization_mode => 0, + c_wr_data_count_width => 2, + c_preload_regs => 0, + c_dout_rst_val => "0", + c_has_data_count => 0, + c_prog_full_thresh_negate_val => 768, + c_wr_depth => 1024, + c_prog_empty_thresh_negate_val => 256, + c_prog_empty_thresh_assert_val => 256, + c_has_valid => 0, + c_init_wr_pntr_val => 0, + c_prog_full_thresh_assert_val => 768, + c_has_backup => 0, + c_valid_low => 0, + c_prim_fifo_type => 1024, + c_count_type => 0, + c_prog_full_type => 0, + c_memory_type => 1); +-- synopsys translate_on +BEGIN +-- synopsys translate_off +U0 : wrapped_xilinx_fifo_18x1k + port map ( + clk => clk, + din => din, + rd_en => rd_en, + rst => rst, + wr_en => wr_en, + dout => dout, + empty => empty, + full => full); +-- synopsys translate_on + +END xilinx_fifo_18x1k_a; + diff --git a/xilinx/virtex2/simulation/xilinx_fifo_18x32.vhd b/xilinx/virtex2/simulation/xilinx_fifo_18x32.vhd new file mode 100644 index 0000000..de09a38 --- /dev/null +++ b/xilinx/virtex2/simulation/xilinx_fifo_18x32.vhd @@ -0,0 +1,136 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2005 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file xilinx_fifo_18x32.vhd when simulating +-- the core, xilinx_fifo_18x32. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synopsys directives "translate_off/translate_on" specified +-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synopsys translate_off +Library XilinxCoreLib; +-- synopsys translate_on +ENTITY xilinx_fifo_18x32 IS + port ( + clk: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + rd_en: IN std_logic; + rst: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + empty: OUT std_logic; + full: OUT std_logic); +END xilinx_fifo_18x32; + +ARCHITECTURE xilinx_fifo_18x32_a OF xilinx_fifo_18x32 IS +-- synopsys translate_off +component wrapped_xilinx_fifo_18x32 + port ( + clk: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + rd_en: IN std_logic; + rst: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + empty: OUT std_logic; + full: OUT std_logic); +end component; + +-- Configuration specification + for all : wrapped_xilinx_fifo_18x32 use entity XilinxCoreLib.fifo_generator_v2_1(behavioral) + generic map( + c_wr_response_latency => 1, + c_has_rd_data_count => 0, + c_din_width => 18, + c_has_wr_data_count => 0, + c_implementation_type => 1, + c_family => "virtex2", + c_has_wr_rst => 0, + c_underflow_low => 0, + c_has_meminit_file => 0, + c_has_overflow => 0, + c_preload_latency => 1, + c_dout_width => 18, + c_rd_depth => 32, + c_default_value => "BlankString", + c_mif_file_name => "BlankString", + c_has_underflow => 0, + c_has_rd_rst => 0, + c_has_almost_full => 0, + c_has_rst => 1, + c_data_count_width => 2, + c_has_wr_ack => 0, + c_wr_ack_low => 0, + c_common_clock => 1, + c_rd_pntr_width => 5, + c_has_almost_empty => 0, + c_rd_data_count_width => 2, + c_enable_rlocs => 0, + c_wr_pntr_width => 5, + c_overflow_low => 0, + c_prog_empty_type => 0, + c_optimization_mode => 0, + c_wr_data_count_width => 2, + c_preload_regs => 0, + c_dout_rst_val => "0", + c_has_data_count => 0, + c_prog_full_thresh_negate_val => 12, + c_wr_depth => 32, + c_prog_empty_thresh_negate_val => 4, + c_prog_empty_thresh_assert_val => 4, + c_has_valid => 0, + c_init_wr_pntr_val => 0, + c_prog_full_thresh_assert_val => 12, + c_has_backup => 0, + c_valid_low => 0, + c_prim_fifo_type => 512, + c_count_type => 0, + c_prog_full_type => 0, + c_memory_type => 3); +-- synopsys translate_on +BEGIN +-- synopsys translate_off +U0 : wrapped_xilinx_fifo_18x32 + port map ( + clk => clk, + din => din, + rd_en => rd_en, + rst => rst, + wr_en => wr_en, + dout => dout, + empty => empty, + full => full); +-- synopsys translate_on + +END xilinx_fifo_18x32_a; + diff --git a/xilinx/virtex2/simulation/xilinx_fifo_18x64.vhd b/xilinx/virtex2/simulation/xilinx_fifo_18x64.vhd new file mode 100644 index 0000000..cf0aa8a --- /dev/null +++ b/xilinx/virtex2/simulation/xilinx_fifo_18x64.vhd @@ -0,0 +1,136 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2005 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file xilinx_fifo_18x64.vhd when simulating +-- the core, xilinx_fifo_18x64. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synopsys directives "translate_off/translate_on" specified +-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synopsys translate_off +Library XilinxCoreLib; +-- synopsys translate_on +ENTITY xilinx_fifo_18x64 IS + port ( + clk: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + rd_en: IN std_logic; + rst: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + empty: OUT std_logic; + full: OUT std_logic); +END xilinx_fifo_18x64; + +ARCHITECTURE xilinx_fifo_18x64_a OF xilinx_fifo_18x64 IS +-- synopsys translate_off +component wrapped_xilinx_fifo_18x64 + port ( + clk: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + rd_en: IN std_logic; + rst: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + empty: OUT std_logic; + full: OUT std_logic); +end component; + +-- Configuration specification + for all : wrapped_xilinx_fifo_18x64 use entity XilinxCoreLib.fifo_generator_v2_1(behavioral) + generic map( + c_wr_response_latency => 1, + c_has_rd_data_count => 0, + c_din_width => 18, + c_has_wr_data_count => 0, + c_implementation_type => 1, + c_family => "virtex2", + c_has_wr_rst => 0, + c_underflow_low => 0, + c_has_meminit_file => 0, + c_has_overflow => 0, + c_preload_latency => 1, + c_dout_width => 18, + c_rd_depth => 64, + c_default_value => "BlankString", + c_mif_file_name => "BlankString", + c_has_underflow => 0, + c_has_rd_rst => 0, + c_has_almost_full => 0, + c_has_rst => 1, + c_data_count_width => 2, + c_has_wr_ack => 0, + c_wr_ack_low => 0, + c_common_clock => 1, + c_rd_pntr_width => 6, + c_has_almost_empty => 0, + c_rd_data_count_width => 2, + c_enable_rlocs => 0, + c_wr_pntr_width => 6, + c_overflow_low => 0, + c_prog_empty_type => 0, + c_optimization_mode => 0, + c_wr_data_count_width => 2, + c_preload_regs => 0, + c_dout_rst_val => "0", + c_has_data_count => 0, + c_prog_full_thresh_negate_val => 12, + c_wr_depth => 64, + c_prog_empty_thresh_negate_val => 4, + c_prog_empty_thresh_assert_val => 4, + c_has_valid => 0, + c_init_wr_pntr_val => 0, + c_prog_full_thresh_assert_val => 12, + c_has_backup => 0, + c_valid_low => 0, + c_prim_fifo_type => 512, + c_count_type => 0, + c_prog_full_type => 0, + c_memory_type => 3); +-- synopsys translate_on +BEGIN +-- synopsys translate_off +U0 : wrapped_xilinx_fifo_18x64 + port map ( + clk => clk, + din => din, + rd_en => rd_en, + rst => rst, + wr_en => wr_en, + dout => dout, + empty => empty, + full => full); +-- synopsys translate_on + +END xilinx_fifo_18x64_a; + diff --git a/xilinx/virtex2/simulation/xilinx_fifo_dualport_18x1k.vhd b/xilinx/virtex2/simulation/xilinx_fifo_dualport_18x1k.vhd new file mode 100644 index 0000000..0409ec2 --- /dev/null +++ b/xilinx/virtex2/simulation/xilinx_fifo_dualport_18x1k.vhd @@ -0,0 +1,139 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2005 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file xilinx_fifo_dualport_18x1k.vhd when simulating +-- the core, xilinx_fifo_dualport_18x1k. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synopsys directives "translate_off/translate_on" specified +-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synopsys translate_off +Library XilinxCoreLib; +-- synopsys translate_on +ENTITY xilinx_fifo_dualport_18x1k IS + port ( + din: IN std_logic_VECTOR(17 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + empty: OUT std_logic; + full: OUT std_logic); +END xilinx_fifo_dualport_18x1k; + +ARCHITECTURE xilinx_fifo_dualport_18x1k_a OF xilinx_fifo_dualport_18x1k IS +-- synopsys translate_off +component wrapped_xilinx_fifo_dualport_18x1k + port ( + din: IN std_logic_VECTOR(17 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + empty: OUT std_logic; + full: OUT std_logic); +end component; + +-- Configuration specification + for all : wrapped_xilinx_fifo_dualport_18x1k use entity XilinxCoreLib.fifo_generator_v2_1(behavioral) + generic map( + c_wr_response_latency => 1, + c_has_rd_data_count => 0, + c_din_width => 18, + c_has_wr_data_count => 0, + c_implementation_type => 2, + c_family => "virtex2", + c_has_wr_rst => 0, + c_underflow_low => 0, + c_has_meminit_file => 0, + c_has_overflow => 0, + c_preload_latency => 1, + c_dout_width => 18, + c_rd_depth => 1024, + c_default_value => "BlankString", + c_mif_file_name => "BlankString", + c_has_underflow => 0, + c_has_rd_rst => 0, + c_has_almost_full => 0, + c_has_rst => 1, + c_data_count_width => 2, + c_has_wr_ack => 0, + c_wr_ack_low => 0, + c_common_clock => 0, + c_rd_pntr_width => 10, + c_has_almost_empty => 0, + c_rd_data_count_width => 2, + c_enable_rlocs => 0, + c_wr_pntr_width => 10, + c_overflow_low => 0, + c_prog_empty_type => 0, + c_optimization_mode => 0, + c_wr_data_count_width => 2, + c_preload_regs => 0, + c_dout_rst_val => "0", + c_has_data_count => 0, + c_prog_full_thresh_negate_val => 768, + c_wr_depth => 1024, + c_prog_empty_thresh_negate_val => 256, + c_prog_empty_thresh_assert_val => 256, + c_has_valid => 0, + c_init_wr_pntr_val => 0, + c_prog_full_thresh_assert_val => 768, + c_has_backup => 0, + c_valid_low => 0, + c_prim_fifo_type => 1024, + c_count_type => 0, + c_prog_full_type => 0, + c_memory_type => 1); +-- synopsys translate_on +BEGIN +-- synopsys translate_off +U0 : wrapped_xilinx_fifo_dualport_18x1k + port map ( + din => din, + rd_clk => rd_clk, + rd_en => rd_en, + rst => rst, + wr_clk => wr_clk, + wr_en => wr_en, + dout => dout, + empty => empty, + full => full); +-- synopsys translate_on + +END xilinx_fifo_dualport_18x1k_a; + diff --git a/xilinx/virtex2/xilinx_fifo_dualport_18x1k.xco b/xilinx/virtex2/xilinx_fifo_dualport_18x1k.xco new file mode 100644 index 0000000..ba11e9c --- /dev/null +++ b/xilinx/virtex2/xilinx_fifo_dualport_18x1k.xco @@ -0,0 +1,64 @@ +# BEGIN Project Options +SET flowvendor = Foundation_iSE +SET vhdlsim = True +SET verilogsim = True +SET workingdirectory = . +SET speedgrade = -5 +SET simulationfiles = Behavioral +SET asysymbol = True +SET addpads = False +SET device = xc2v250 +SET implementationfiletype = Edif +SET busformat = BusFormatAngleBracketNotRipped +SET foundationsym = False +SET package = fg456 +SET createndf = False +SET designentry = VHDL +SET devicefamily = virtex2 +SET formalverification = False +SET removerpms = False +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 2.1 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET write_data_count=false +CSET full_threshold_negate_value=768 +CSET empty_threshold_negate_value=256 +CSET output_data_width=18 +CSET input_depth=1024 +CSET valid_flag=false +CSET empty_threshold_negate_presets=3/4_Empty +CSET write_acknowledge_flag=false +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET full_threshold_negate_presets=3/4_Full +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET underflow_flag=false +CSET use_extra_logic=false +CSET register_outputs=false +CSET valid_sense=Active_High +CSET write_data_count_width=2 +CSET data_count_width=2 +CSET output_depth=1024 +CSET dout_reset_value=0 +CSET underflow_sense=Active_High +CSET component_name=xilinx_fifo_dualport_18x1k +CSET overflow_sense=Active_High +CSET overflow_flag=false +CSET read_data_count=false +CSET data_count=false +CSET primitive_depth=1024 +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_data_count_width=2 +CSET read_latency=1 +CSET empty_threshold_assert_presets=3/4_Empty +CSET full_threshold_assert_value=768 +CSET almost_full_flag=false +CSET full_threshold_assert_presets=3/4_Full +CSET write_acknowledge_sense=Active_High +CSET empty_threshold_assert_value=256 +CSET input_data_width=18 +# END Parameters +GENERATE + diff --git a/xilinx/virtex4/simulation/xilinx_fifo_18x16.vhd b/xilinx/virtex4/simulation/xilinx_fifo_18x16.vhd new file mode 100644 index 0000000..c873934 --- /dev/null +++ b/xilinx/virtex4/simulation/xilinx_fifo_18x16.vhd @@ -0,0 +1,105 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2005 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file xilinx_fifo_18x16.vhd when simulating +-- the core, xilinx_fifo_18x16. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synopsys directives "translate_off/translate_on" specified +-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synopsys translate_off +Library XilinxCoreLib; +-- synopsys translate_on +ENTITY xilinx_fifo_18x16 IS + port ( + clk: IN std_logic; + sinit: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + wr_en: IN std_logic; + rd_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic); +END xilinx_fifo_18x16; + +ARCHITECTURE xilinx_fifo_18x16_a OF xilinx_fifo_18x16 IS +-- synopsys translate_off +component wrapped_xilinx_fifo_18x16 + port ( + clk: IN std_logic; + sinit: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + wr_en: IN std_logic; + rd_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic); +end component; + +-- Configuration specification + for all : wrapped_xilinx_fifo_18x16 use entity XilinxCoreLib.sync_fifo_v5_0(behavioral) + generic map( + c_read_data_width => 18, + c_has_wr_ack => 0, + c_dcount_width => 1, + c_has_wr_err => 0, + c_wr_err_low => 1, + c_wr_ack_low => 1, + c_enable_rlocs => 0, + c_has_dcount => 0, + c_rd_err_low => 1, + c_rd_ack_low => 1, + c_read_depth => 16, + c_has_rd_ack => 0, + c_write_depth => 16, + c_ports_differ => 0, + c_memory_type => 0, + c_write_data_width => 18, + c_has_rd_err => 0); +-- synopsys translate_on +BEGIN +-- synopsys translate_off +U0 : wrapped_xilinx_fifo_18x16 + port map ( + clk => clk, + sinit => sinit, + din => din, + wr_en => wr_en, + rd_en => rd_en, + dout => dout, + full => full, + empty => empty); +-- synopsys translate_on + +END xilinx_fifo_18x16_a; + diff --git a/xilinx/virtex4/simulation/xilinx_fifo_18x1k.vhd b/xilinx/virtex4/simulation/xilinx_fifo_18x1k.vhd new file mode 100644 index 0000000..f654692 --- /dev/null +++ b/xilinx/virtex4/simulation/xilinx_fifo_18x1k.vhd @@ -0,0 +1,108 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2005 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file xilinx_fifo_18x1k.vhd when simulating +-- the core, xilinx_fifo_18x1k. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synopsys directives "translate_off/translate_on" specified +-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synopsys translate_off +Library XilinxCoreLib; +-- synopsys translate_on +ENTITY xilinx_fifo_18x1k IS + port ( + clk: IN std_logic; + sinit: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + wr_en: IN std_logic; + rd_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic; + data_count: OUT std_logic_VECTOR(3 downto 0)); +END xilinx_fifo_18x1k; + +ARCHITECTURE xilinx_fifo_18x1k_a OF xilinx_fifo_18x1k IS +-- synopsys translate_off +component wrapped_xilinx_fifo_18x1k + port ( + clk: IN std_logic; + sinit: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + wr_en: IN std_logic; + rd_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic; + data_count: OUT std_logic_VECTOR(3 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_xilinx_fifo_18x1k use entity XilinxCoreLib.sync_fifo_v5_0(behavioral) + generic map( + c_read_data_width => 18, + c_has_wr_ack => 0, + c_dcount_width => 4, + c_has_wr_err => 0, + c_wr_err_low => 1, + c_wr_ack_low => 1, + c_enable_rlocs => 0, + c_has_dcount => 1, + c_rd_err_low => 1, + c_rd_ack_low => 1, + c_read_depth => 1024, + c_has_rd_ack => 0, + c_write_depth => 1024, + c_ports_differ => 0, + c_memory_type => 1, + c_write_data_width => 18, + c_has_rd_err => 0); +-- synopsys translate_on +BEGIN +-- synopsys translate_off +U0 : wrapped_xilinx_fifo_18x1k + port map ( + clk => clk, + sinit => sinit, + din => din, + wr_en => wr_en, + rd_en => rd_en, + dout => dout, + full => full, + empty => empty, + data_count => data_count); +-- synopsys translate_on + +END xilinx_fifo_18x1k_a; + diff --git a/xilinx/virtex4/simulation/xilinx_fifo_18x32.vhd b/xilinx/virtex4/simulation/xilinx_fifo_18x32.vhd new file mode 100644 index 0000000..3117180 --- /dev/null +++ b/xilinx/virtex4/simulation/xilinx_fifo_18x32.vhd @@ -0,0 +1,105 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2005 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file xilinx_fifo_18x32.vhd when simulating +-- the core, xilinx_fifo_18x32. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synopsys directives "translate_off/translate_on" specified +-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synopsys translate_off +Library XilinxCoreLib; +-- synopsys translate_on +ENTITY xilinx_fifo_18x32 IS + port ( + clk: IN std_logic; + sinit: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + wr_en: IN std_logic; + rd_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic); +END xilinx_fifo_18x32; + +ARCHITECTURE xilinx_fifo_18x32_a OF xilinx_fifo_18x32 IS +-- synopsys translate_off +component wrapped_xilinx_fifo_18x32 + port ( + clk: IN std_logic; + sinit: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + wr_en: IN std_logic; + rd_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic); +end component; + +-- Configuration specification + for all : wrapped_xilinx_fifo_18x32 use entity XilinxCoreLib.sync_fifo_v5_0(behavioral) + generic map( + c_read_data_width => 18, + c_has_wr_ack => 0, + c_dcount_width => 1, + c_has_wr_err => 0, + c_wr_err_low => 1, + c_wr_ack_low => 1, + c_enable_rlocs => 0, + c_has_dcount => 0, + c_rd_err_low => 1, + c_rd_ack_low => 1, + c_read_depth => 32, + c_has_rd_ack => 0, + c_write_depth => 32, + c_ports_differ => 0, + c_memory_type => 0, + c_write_data_width => 18, + c_has_rd_err => 0); +-- synopsys translate_on +BEGIN +-- synopsys translate_off +U0 : wrapped_xilinx_fifo_18x32 + port map ( + clk => clk, + sinit => sinit, + din => din, + wr_en => wr_en, + rd_en => rd_en, + dout => dout, + full => full, + empty => empty); +-- synopsys translate_on + +END xilinx_fifo_18x32_a; + diff --git a/xilinx/virtex4/simulation/xilinx_fifo_18x64.vhd b/xilinx/virtex4/simulation/xilinx_fifo_18x64.vhd new file mode 100644 index 0000000..905c353 --- /dev/null +++ b/xilinx/virtex4/simulation/xilinx_fifo_18x64.vhd @@ -0,0 +1,105 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2005 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file xilinx_fifo_18x64.vhd when simulating +-- the core, xilinx_fifo_18x64. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synopsys directives "translate_off/translate_on" specified +-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synopsys translate_off +Library XilinxCoreLib; +-- synopsys translate_on +ENTITY xilinx_fifo_18x64 IS + port ( + clk: IN std_logic; + sinit: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + wr_en: IN std_logic; + rd_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic); +END xilinx_fifo_18x64; + +ARCHITECTURE xilinx_fifo_18x64_a OF xilinx_fifo_18x64 IS +-- synopsys translate_off +component wrapped_xilinx_fifo_18x64 + port ( + clk: IN std_logic; + sinit: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + wr_en: IN std_logic; + rd_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic); +end component; + +-- Configuration specification + for all : wrapped_xilinx_fifo_18x64 use entity XilinxCoreLib.sync_fifo_v5_0(behavioral) + generic map( + c_read_data_width => 18, + c_has_wr_ack => 0, + c_dcount_width => 1, + c_has_wr_err => 0, + c_wr_err_low => 1, + c_wr_ack_low => 1, + c_enable_rlocs => 0, + c_has_dcount => 0, + c_rd_err_low => 1, + c_rd_ack_low => 1, + c_read_depth => 64, + c_has_rd_ack => 0, + c_write_depth => 64, + c_ports_differ => 0, + c_memory_type => 0, + c_write_data_width => 18, + c_has_rd_err => 0); +-- synopsys translate_on +BEGIN +-- synopsys translate_off +U0 : wrapped_xilinx_fifo_18x64 + port map ( + clk => clk, + sinit => sinit, + din => din, + wr_en => wr_en, + rd_en => rd_en, + dout => dout, + full => full, + empty => empty); +-- synopsys translate_on + +END xilinx_fifo_18x64_a; + diff --git a/xilinx/virtex4/xilinx_fifo_dualport_18x1k.xco b/xilinx/virtex4/xilinx_fifo_dualport_18x1k.xco new file mode 100644 index 0000000..836a3b7 --- /dev/null +++ b/xilinx/virtex4/xilinx_fifo_dualport_18x1k.xco @@ -0,0 +1,64 @@ +# BEGIN Project Options +SET flowvendor = Foundation_iSE +SET vhdlsim = True +SET verilogsim = True +SET workingdirectory = . +SET speedgrade = -10 +SET simulationfiles = Behavioral +SET asysymbol = True +SET addpads = False +SET device = xc4vlx40 +SET implementationfiletype = Edif +SET busformat = BusFormatAngleBracketNotRipped +SET foundationsym = False +SET package = ff1148 +SET createndf = False +SET designentry = VHDL +SET devicefamily = virtex4 +SET formalverification = False +SET removerpms = False +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 2.1 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET write_data_count=false +CSET full_threshold_negate_value=768 +CSET empty_threshold_negate_value=256 +CSET output_data_width=18 +CSET input_depth=1024 +CSET valid_flag=false +CSET empty_threshold_negate_presets=3/4_Empty +CSET write_acknowledge_flag=false +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET full_threshold_negate_presets=3/4_Full +CSET fifo_implementation=Independent_Clocks_Builtin_FIFO +CSET underflow_flag=false +CSET use_extra_logic=false +CSET register_outputs=false +CSET valid_sense=Active_High +CSET write_data_count_width=2 +CSET data_count_width=2 +CSET output_depth=1024 +CSET dout_reset_value=0 +CSET underflow_sense=Active_High +CSET component_name=xilinx_fifo_dualport_18x1k +CSET overflow_sense=Active_High +CSET overflow_flag=false +CSET read_data_count=false +CSET data_count=false +CSET primitive_depth=1024 +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_data_count_width=2 +CSET read_latency=1 +CSET empty_threshold_assert_presets=3/4_Empty +CSET full_threshold_assert_value=768 +CSET almost_full_flag=false +CSET full_threshold_assert_presets=3/4_Full +CSET write_acknowledge_sense=Active_High +CSET empty_threshold_assert_value=256 +CSET input_data_width=18 +# END Parameters +GENERATE + -- 2.43.0