From 32bd8706e2e8f011fae6cd5b5d6748ad9bf9b33e Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 28 Aug 2024 11:32:47 +0200 Subject: [PATCH] add more hit counters --- code/HitBuffer.vhd | 26 ++++++++++++++++---------- code/TDC_FF.vhd | 4 +++- 2 files changed, 19 insertions(+), 11 deletions(-) diff --git a/code/HitBuffer.vhd b/code/HitBuffer.vhd index 6046cfb..505c7d3 100644 --- a/code/HitBuffer.vhd +++ b/code/HitBuffer.vhd @@ -26,7 +26,7 @@ entity HitBuffer is DATA_EMPTY : out std_logic; DATA_READ : in std_logic; - STATUS_OUT : out std_logic_vector(95 downto 0) + STATUS_OUT : out std_logic_vector(127 downto 0) ); end entity; @@ -63,7 +63,7 @@ signal maxtot_timer : unsigned(7 downto 0) := (others => '0'); signal hit_store : std_logic_vector(35 downto 0); alias hit_store_coarse : std_logic_vector(8 downto 0) is hit_store(25 downto 17); -signal count_edges2, count_edges1 : unsigned(23 downto 0); +signal count_edges4, count_edges3, count_edges2, count_edges1 : unsigned(23 downto 0); type buffer_state_t is (EMPTY,WAIT_HIT,WAIT_HIT2,GOT_HIT,HAS_HIT,DO_READOUT,WAIT_READOUT); signal buffer_state : buffer_state_t; @@ -113,6 +113,7 @@ PROC_BUILD_HIT : process begin maxtot_timer <= maxtot_timer - 1; else edge_rising_valid <= '0'; + count_edges3 <= count_edges3 + 1; end if; @@ -130,12 +131,16 @@ PROC_BUILD_HIT : process begin elsif spike_timer /= x"0" then count_spike_en <= '1'; end if; + if cdc_data_error = '1' or edge_rising_error = '1' then + count_edges4 <= count_edges4 + 1; + end if; + end if; + + if cdc_valid = '1' and cdc_data(5) = '0' and edge_rising_valid = '0' then + count_edges4 <= count_edges4 + 1; end if; - --if RESET_IN = '1' then - --count_edges1 <= (others => '0'); - --end if; - + end process; process begin @@ -266,10 +271,11 @@ DATA_OUT <= hit_store(27 downto 0); ---------------------------------------------------------------------- -- Statistics ---------------------------------------------------------------------- -STATUS_OUT(31 downto 0) <= x"00" & std_logic_vector(count_edges1) when rising_edge(CLK_SYS); -STATUS_OUT(63 downto 32) <= x"00" & std_logic_vector(count_edges2) when rising_edge(CLK_SYS); -STATUS_OUT(71 downto 64) <= "00" & hit_buffer_level when rising_edge(CLK_SYS); -STATUS_OUT(75 downto 72) <= std_logic_vector(spike_timer) when rising_edge(CLK_SYS); +STATUS_OUT(31 downto 0) <= x"00" & std_logic_vector(count_edges1) when rising_edge(CLK_SYS); +STATUS_OUT(63 downto 32) <= x"00" & std_logic_vector(count_edges2) when rising_edge(CLK_SYS); +STATUS_OUT(71 downto 64) <= "00" & hit_buffer_level when rising_edge(CLK_SYS); +STATUS_OUT(95 downto 72) <= std_logic_vector(count_edges3) when rising_edge(CLK_SYS); +STATUS_OUT(127 downto 96) <= std_logic_vector(count_edges4) when rising_edge(CLK_SYS); ---------------------------------------------------------------------- diff --git a/code/TDC_FF.vhd b/code/TDC_FF.vhd index 23fb709..a04c99e 100644 --- a/code/TDC_FF.vhd +++ b/code/TDC_FF.vhd @@ -48,7 +48,7 @@ signal tdc_data : tdc_data_t(NUM_CHANNELS-1 downto 0); signal coarse_time, throwaway_time : unsigned(8 downto 0) := (others => '0'); -type status_t is array(0 to 31) of std_logic_vector(95 downto 0); +type status_t is array(0 to 31) of std_logic_vector(127 downto 0); signal hitbuffer_status : status_t; signal CONF_enable : std_logic_vector(31 downto 0) := (others => '1'); @@ -243,6 +243,8 @@ begin BUS_TX.data <= hitbuffer_status(addr)(63 downto 32); elsif BUS_RX.addr(15 downto 5) = x"01" & "010" then BUS_TX.data <= hitbuffer_status(addr)(95 downto 64); + elsif BUS_RX.addr(15 downto 5) = x"01" & "011" then + BUS_TX.data <= hitbuffer_status(addr)(127 downto 96); else BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; -- 2.43.0