From 33eec6ee8fef152c932e8c489907dedd0e4eada0 Mon Sep 17 00:00:00 2001 From: Andreas Neiser Date: Thu, 11 Jun 2015 13:17:39 +0200 Subject: [PATCH] Let's try with this ADC phase determination --- ADC/source/adc_handler.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ADC/source/adc_handler.vhd b/ADC/source/adc_handler.vhd index 6e875b2..2de252c 100644 --- a/ADC/source/adc_handler.vhd +++ b/ADC/source/adc_handler.vhd @@ -404,15 +404,15 @@ begin ); end generate; - ADC_CLK_TDC_OUT <= epoch_counter(10); - PROC_EPOCH_COUNTER : process is begin wait until rising_edge(adc_clk_left); epoch_counter <= epoch_counter + 1; trigger_in_i <= TRIGGER_IN; + ADC_CLK_TDC_OUT <= '0'; if trigger_in_i = '1' then epoch_counter_save <= epoch_counter; + ADC_CLK_TDC_OUT <= '1'; end if; end process PROC_EPOCH_COUNTER; -- 2.43.0