From 341a1cecf0b5de850b38a9a16369913f132b91fb Mon Sep 17 00:00:00 2001 From: Michael Traxler Date: Mon, 3 May 2021 04:06:44 +0200 Subject: [PATCH] added TDCv4 support, mt --- xml-db/database/TDCv4.xml | 664 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 664 insertions(+) create mode 100644 xml-db/database/TDCv4.xml diff --git a/xml-db/database/TDCv4.xml b/xml-db/database/TDCv4.xml new file mode 100644 index 0000000..bffcb30 --- /dev/null +++ b/xml-db/database/TDCv4.xml @@ -0,0 +1,664 @@ + + + An FPGA-based tapped-delay line time-to-digital converter (TDC) version 4.0 for DiRICH + + + + + + + + + Level of input signals. Rightmost box is channel 0. + + + + + Level of input signals. Rightmost box is channel 16. Bit31 is Reference Channel. + + + + + Status information about the TDC-Core + + Lock signal for all PLLs, 1: not locked 0: locked + Locked + Not Locked + + + Lock signal of the Sampling-PLL + Not Locked + Locked + + + Lock signal of the Halfclock-PLL + Not Locked + Locked + + + State of Reset-Signal for TDC-Core + TDC active + TDC in Reset + + + TDC was reset because of illegal FSM-State (SEU) + No SEU + SEU detected + + + DAQ-FIFO full detected, possible Data Loss + No Overflow + Overflow occurred + + + Delay-Line min/max has been reached + In-band + End reached + + + Trace Buffer Trigger Flag + Idle/Recording + Trigger Found + + + High-Rate Sampler Trigger Flag + Idle/Recording + Trigger Found + + + Delay-Line Adjustment in Progress + Done + Adjusting + + + + + Type and ID of last finished Trigger Command, for both DAQ FIFO and Data Container. + + + + + + + + Timeout occurred in Capture Block. Rightmost box is channel 0. + + + + + Timeout occurred in Capture Block. Rightmost box is channel 16. Bit31 is Reference Channel. + + + + + Programmable Stretcher Delay is too short. Rightmost box is channel 0. + + + + + Programmable Stretcher Delay is too short. Rightmost box is channel 16. + + + + + A second rising edge occurred during the deadtime. Rightmost box is channel 0. + + + + + A second rising edge occurred during the deadtime. Rightmost box is channel 16. + + + + + A solitary falling edge occurred after the deadtime. Rightmost box is channel 0. + + + + + A solitary falling edge occurred after the deadtime. Rightmost box is channel 16. + + + + + Data was discarded from the Hit FIFO. Rightmost box is channel 0. + + + + + Data was discarded from the Hit FIFO. Rightmost box is channel 16. Bit31 is Reference Channel. + + + + + Data was discarded from the Event FIFO. Rightmost box is channel 0. + + + + + Data was discarded from the Event FIFO. Rightmost box is channel 16. Bit31 is Reference Channel. + + + + + Illegal Combination of Channel Control Signals. One bit per channel pair. Rightmost box is channel pair 0. + + + + + Illegal Combination of Channel Control Signals. One bit per channel pair. Rightmost box is channel pair 8. + + + + + + + + + + + Control Bits for all Channels + + Programmable TDC Reset. When 1, keeps TDC but not Control Subsystem in Reset. + Released + Reset + + + Reset-Signal for Sampling Clock PLL. + Released + Reset + + + Reset-Signal for Half-Frequency Clock PLL. + Released + Reset + + + Dynamic Clock Selection Control. + Illegal + Clock from Pin + Clock from PLL + Illegal + + + DCS Switching Mode. + Glitchless + Non-glitchless + + + Standby-Signal (power-down) for all TDC-PLLs. + Powered-up + Standby + + + Reference Clock Select for Sampling Clock PLL. Not used on DiRICH. + Clock 0 + Clock 1 + + + Programmable Hit Counter Reset. When 1, keeps all Hit Counters at 0. + Released + Reset + + + Programmable Hit Counter Gate. When 0, no Hit Counter can count, instead keeps its value. + Stopped + Enabled + + + Programmable Reference Counter Reset. + Released + Reset + + + Enable Deadtime Violation Detection. + Disabled + Enabled + + + Deadman Timeout for Capture Block. When Timeout occurs, Capture Block will be reset. Disabled when bit 4 is set. + + + Suppress Reference Channel Data in Event Data Packet. + Include + Suppress + + + Suppress Epoch Words in Event Data Packet. + Include + Suppress + + + Append Trigger Timestamps to Event Data Packet. + Disabled + Enabled + + + Maximum Number of Hits per Event. If bit 4 is set, all hits are included. + + + Block Input Buffer of the Reference Channel. + Pass + Blocked + + + Input Signal Polarity Inversion for Reference Channel. + Non-Inverted + Inverted + + + Enable TDL for Reference Channel. + Disabled + Enabled + + + Input Select for Reference Channel. Only applies to TRB5sc. + RJ45 + Backplane + + + Rising Edge Select for Reference Channel. + Dual-Edge Mode + Only Rising Edge + + + Stretcher Select for Reference Channel. + Bypassed + Employed + + + Enable Sampling-TDC for Reference Channel. + Disabled + Enabled + + + + + Control Bits for all Channels + + Number of Calibration Pulses per Calibration Trigger. Actual number of pulses is NUMCP + 1. Program with SETCP. + + + Calibration Channel Set. 0: no Channels, 1: 1/4 round-robin, 2: 1/2 alternating, 3: all. Program with SETCP. + + + Calibration Clock Divider. Pulse Length is (CCDIV + 1) / Fosc. Program with SETCF. + + + Capture Block Delay. [7..4]: Stretcher, [3..0]: Unhit. Program with SETDP. + + + Delay Unit ID. Capture Block: (4 * Channel Number). IOBlock Delay: (4 * Channel Number) + 1. Program with SETDP. + + + Delay Line Step Direction. STEP or NSTEP will perform the Delay Adjustment. + Increase + Decrease + + + Built-in Selftest Mode 0. 0: INVA is passed to TDL, 1: one-clock Pulse from INVA-edge. + INVA to TDL + Pulse + + + Built-in Selftest Mode 9. BISTM[11..9] control INRD State Machine. + See Manual + See Manual + + + Used during calibration of the IO-Blocks for the Sampling-TDCs and the High-rate Samplers. See Manual. + + + + + Configuration of the Trigger Window. + + Defines the Trigger Window Start relative to the clock when the trigger command was received. Negative values are in the past. + + + Trigger Window Start Enable. If zero, all hits in the hit FIFO earlier than the Trigger Window End are included in an event. + Disabled + Enabled + + + Defines the Trigger Window End relative to the clock when the trigger command was received. Negative values are in the past. + + + Trigger Window End Enable. If 0, the Trigger Window End is the clock when the trigger command was received. + Disabled + Enabled + + + + + Control Bits for all Channels + + Write Mask for Calibration Table RAMs 12..0 (12: reference channel, 11..0: regular channels). Only one bit may be set. + + + Calibration Override. If 1, trigger types 1000 are changed into 1001. On-the-fly calibration is switched on for types 1000. + Disabled + Enabled + + + Calibration Table Read-back Length per trigger 0100 command. 00: 16, 01: 32, 10: 64, 11: 128 entries. + + + Built-in Selftest Mode 1. Overrides IO-Block Reset by BLCKIN. + See Manual + See Manual + + + Built-in Selftest Mode 2. For the hit counters, selects between the transition indicator pulses and the hit counter test signal. + See Manual + See Manual + + + Built-in Selftest Mode 10. BISTM[11..9] control INRD State Machine. + See Manual + See Manual + + + Calibration Clock Enable. When 0, blocks signal from on-board calibration clock oscillator. Can be used to reduce noise. Must be 1 for calibration triggers. + Blocked + Enabled + + + Temperature Change Warning Threshold. Format depends on Temperature Sensor on the Board. Used to compute the flag STC in the header. + + + + + Control Bits for all Channels + + Enable Trace Buffer. If 1, sampled input data will continuously be stored in the trace buffer. Applies also to the Micro Trace Buffer. + Disabled + Enabled + + + Trace Buffer Sampling Rate. 1--: 1/1, 011: 1/2, 010: 1/4, 001: 1/8, 000: 1/16 of sampling clock. + + + Trace Buffer Transfer Length. Number of sample vectors to be read per 0110 trigger. Actual number of vectors is 2^(5+TBTLEN). 1 Vector = 4 Words. + + + Trace Buffer Trigger Source. Not yet defined. + + + Trace Buffer Trigger Position in multiples of 16. Must never be 0. Most recent vector in Trace Buffer has number 0. Number increases with age. + + + Trace Buffer Source Select. 0: hit signals. 1: Outputs of first and second level Triglets. + Hit Signals + Triglets + + + Trace Buffer Automatic Re-Arm. If 1, Trace Buffer and Micro Trace Buffer will automatically resume data acquisition after a trigger 0111 command. + Explicit + Automatic + + + Built-in Selftest Mode 7. If 1, the Hit Counter test will run. The ring oscillator will operate. During regular operation, BISTM[7] should be 0. + See Manual + See Manual + + + Built-in Selftest Mode 8. When BISTM[7]=1, with BISTM[8]=1 a different internal signal can be measured. + See Manual + See Manual + + + Processing Time Scale Factor. Used to scale the trigger command processing time so that meaningful bits are in positions 19..16 of TRLB. + + + + + Control Bits for all Channels + + Programmable Trigger ID. This bit field has an auto-increment feature. Trigger will be launched by PTCMD in Activity Register. + + + Programmable Trigger Type. All trigger types can be launched internally via PTCMD in Activity Register. + + + Programmable Trigger Data Destination. 00: discard data. 01: DAQ FIFO. 10: Data Container. 11: Both. + + + Programmable Re-Arm Trigger Unit. Not yet defined. + + + Maximum Data Items per Event. Applies to the High-Rate Sampler channels. If bit 5 is set, no limit is applied. + + + High-Rate Sampler Trigger Source. To be defined. + + + Include High-Rate Sampler Data in Event Packet of Timing Trigger 1000 or 1001. + Exclude + Include + + + High-Rate Sampler Read-Out Order. 0: FIFO order, 1: LIFO order. + FIFO + LIFO + + + Automatic Clear of Status Registers CaptureBlockTimeout0 and CaptureBlockTimeout1 after respective read access (CBTO latches). + Disabled + Enabled + + + Automatic Clear of Status Registers StretcherDelayTooShort0 and StretcherDelayTooShort1 after respective read access (SDTS latches). + Disabled + Enabled + + + Automatic Clear of Status Registers DeadtimeViolationDetected0 and DeadtimeViolationDetected1 after respective read access (DTVD latches). + Disabled + Enabled + + + Automatic Clear of Status Registers SolitaryFallingEdgeDetected0 and SolitaryFallingEdgeDetected1 after respective read access (SFED FFs). + Disabled + Enabled + + + Automatic Clear of Status Registers HitFifoDataLoss0 and HitFifoDataLoss1 after respective read access (HFDL latches). + Disabled + Enabled + + + Automatic Clear of Status Registers EventFifoDataLoss0 and EventFifoDataLoss1 after respective read access (EFDL latches). + Disabled + Enabled + + + + + Blocks the Input Signals from entering the Circuitry. 0: allowed, 1: blocked. Rightmost box is channel 0. + + + + Blocks the Input Signals from entering the Circuitry. 0: allowed, 1: blocked. Rightmost box is channel 16. + + + + + Invert-Bits for the Input Signals. 0: true value, 1: inverted. Rightmost box is channel 0. + + + + Invert-Bits for the Input Signals. 0: true value, 1: inverted. Rightmost box is channel 16. + + + + + Enable TDL-TDC. Rightmost box is channel 0. + + + + Enable TDL-TDC. Rightmost box is channel 16. + + + + + Sends Pulses to alternating channels. 0: replicates, 1: alternates. Rightmost box is channel 0. + + + + Sends Pulses to alternating channels. 0: replicates, 1: alternates. Rightmost box is channel 16. + + + + + Selects input signal for a channel. 0: own input, 1: signal from sibling. Rightmost box is channel 0. + + + + Selects input signal for a channel. 0: own input, 1: signal from sibling. Rightmost box is channel 16. Bits 31..24: Sampling Frequency, bits 7..0 + + + + + + Second programmable Inverter. Used for Rising Edge in one Channel, Falling Edge in Sibling. Rightmost box is channel 0. + + + + Second programmable Inverter. Used for Rising Edge in one Channel, Falling Edge in Sibling. Rightmost box is channel 16. Bits 31..24: Sampling Frequency, bits 15..8 + + + + + + Rising Edge Select. If 1, only rising edges are measured. Rightmost box is channel 0. + + + + Rising Edge Select. If 1, only rising edges are measured. Rightmost box is channel 16. Bits 31..24: Calibration Oscillator Frequency, bits 7..0 + + + + + + Stretcher Select. 0: bypassed, 1: employed. Rightmost box is channel 0. + + + + Stretcher Select. 0: bypassed, 1: employed. Rightmost box is channel 16. Bits 31..24: Calibration Oscillator Frequency, bits 15..8 + + + + + + Enable Sampling-TDC using the DDR-FFs in the IO-Blocks. Rightmost box is channel 0. + + + + Enable Sampling-TDC using the DDR-FFs in the IO-Blocks. Rightmost box is channel 16. + + + Must be set to 1 if the parameter SAMFRQ is precise, to zero otherwise. This bit appears in bit 28 of Trailer B. + Approx + Precise + + + Must be set to 1 if the parameter CALFRQ is precise, to zero otherwise. This bit appears in bit 28 of Trailer C. + Approx + Precise + + + Built-in Selftest Mode 11. BISTM[11..9] control INRD State Machine. + See Manual + See Manual + + + + + Write-only bits for triggering Activities on the TDC + + Clears all latches that can be read via Register GeneralStatus. + + + Clears all Capture-Block-TimeOut latches. + + + Clears all Stretcher-Delay-Too-Short latches. + + + Clears all Deadtime-Violation-Detected latches. + + + Clears all Solitary-Falling-Edge-Detected latches. + + + Clears all Hit-FIFO-Data-Loss latches. + + + Clears all Event-FIFO-Data-Loss latches. + + + Initializes the TriggerCommandReturn Register to a trigger type of 1111 and an ID of 0. + + + Captures momentary state of all hit counters, the reference counter and the slow control timer. + + + Launch programmable trigger command. Programmable trigger ID will be incremented afterwards. + + + Set Trigger Command Attributes PTDD and PRATU for trigger type PTTY from the DAQ. All parameters in ControlReg5. + + + Set Calibration Parameters. Programs NUMCP and CALSET into the corresponding hardware units. + + + Set Calibration Clock Divider. Programs CCDIV into the corresponding hardware units. + + + Set programmed Delay Parameters. Will program CBDEL (CR1[15..8]) into the selected Capture Block. + + + Will increment or decrement the delay of the delay line (DELAYF) selected by DUID. + + + Performs N increment or decrement steps on the delay line (DELAYF) selected by DUID. N = CBDEL[6..0]. + + + Resets the delay line (DELAYF) selected by DUID to the default (configured) delay value. + + + Arms Trigger Data Container. Resets the write address to 0, and enables data storage again. + + + + + + + + + + + Hit Counter for Channel 0 + + + + Hit Counter for Channel 1 + + + + Hit Counter for Channel 2 + + + + Hit Counter for Channel 3 + + + + + + -- 2.43.0