From 34c7d5fff2515be4c7dfac1d6b911a3bb37459cd Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Mon, 4 Jun 2012 13:34:12 +0000 Subject: [PATCH] *** empty log message *** --- media_interfaces/ecp3_sfp/sfp_0_200_int.vhd | 20 +-- special/spi_ltc2600.vhd | 156 ++++++++++++++++++++ testbenches/tb_ltc2600.vhd | 103 +++++++++++++ trb_net_components.vhd | 62 +++++++- 4 files changed, 330 insertions(+), 11 deletions(-) create mode 100644 special/spi_ltc2600.vhd create mode 100644 testbenches/tb_ltc2600.vhd diff --git a/media_interfaces/ecp3_sfp/sfp_0_200_int.vhd b/media_interfaces/ecp3_sfp/sfp_0_200_int.vhd index bae3e22..59f7a45 100644 --- a/media_interfaces/ecp3_sfp/sfp_0_200_int.vhd +++ b/media_interfaces/ecp3_sfp/sfp_0_200_int.vhd @@ -1525,7 +1525,7 @@ use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -entity rx_reset_sm is +entity rx_reset_sm_200int is generic (count_index: integer :=18); port ( rst_n : in std_logic; @@ -1536,9 +1536,9 @@ port ( rx_los_low_ch_s : in std_logic; rx_pcs_rst_ch_c : out std_logic ); -end rx_reset_sm ; +end rx_reset_sm_200int ; -architecture rx_reset_sm_arch of rx_reset_sm is +architecture rx_reset_sm_arch of rx_reset_sm_200int is type statetype is (WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_LOS, WAIT_FOR_TIMER2, NORMAL); @@ -1713,7 +1713,7 @@ use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -entity tx_reset_sm is +entity tx_reset_sm_200int is generic (count_index: integer :=18); port ( rst_n : in std_logic; @@ -1722,9 +1722,9 @@ port ( rst_qd_c : out std_logic; tx_pcs_rst_ch_c : out std_logic ); -end tx_reset_sm; +end tx_reset_sm_200int; -architecture tx_reset_sm_arch of tx_reset_sm is +architecture tx_reset_sm_arch of tx_reset_sm_200int is type statetype is (QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NORMAL); @@ -1943,7 +1943,7 @@ port ( Z : out std_logic); end component; -component rx_reset_sm +component rx_reset_sm_200int generic (count_index: integer :=18); port ( rst_n : in std_logic; @@ -1956,7 +1956,7 @@ port ( ); end component ; -component tx_reset_sm +component tx_reset_sm_200int generic (count_index: integer :=18); port ( rst_n : in std_logic; @@ -3066,7 +3066,7 @@ port map ( END IF; END PROCESS; -rx_reset_sm_ch0 : rx_reset_sm +rx_reset_sm_ch0 : rx_reset_sm_200int --synopsys translate_off generic map (count_index => 4) --synopsys translate_on @@ -3093,7 +3093,7 @@ port map ( END PROCESS; -- reset sequence for tx -tx_reset_sm_ch : tx_reset_sm +tx_reset_sm_ch : tx_reset_sm_200int --synopsys translate_off generic map (count_index => 4) --synopsys translate_on diff --git a/special/spi_ltc2600.vhd b/special/spi_ltc2600.vhd new file mode 100644 index 0000000..5fb53c5 --- /dev/null +++ b/special/spi_ltc2600.vhd @@ -0,0 +1,156 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.all; + + +entity spi_ltc2600 is + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + BUS_READ_IN : in std_logic; + BUS_WRITE_IN : in std_logic; + BUS_BUSY_OUT : out std_logic; + BUS_ACK_OUT : out std_logic; + BUS_ADDR_IN : in std_logic_vector(4 downto 0); + BUS_DATA_IN : in std_logic_vector(31 downto 0); + BUS_DATA_OUT : out std_logic_vector(31 downto 0); + -- SPI connections + SPI_CS_OUT : out std_logic; + SPI_SDI_IN : in std_logic; + SPI_SDO_OUT : out std_logic; + SPI_SCK_OUT : out std_logic + ); +end entity; + + +architecture spi_ltc2600_arch of spi_ltc2600 is + + type ram_t is array(0 to 15) of std_logic_vector(31 downto 0); + signal ram : ram_t; + + signal ram_addr : integer range 0 to 15; + signal ram_data : std_logic_vector(31 downto 0); + signal ctrl_reg : std_logic_vector(31 downto 0); + signal start : std_logic; + + signal spi_cs : std_logic; + signal spi_sck : std_logic; + signal spi_sd : std_logic; + + signal word_count : integer range 0 to 15; + signal bit_count : integer range 0 to 31; + signal time_count : integer range 0 to 7; + + type fsm_t is (IDLE, WAIT_STATE, SET, FINISH); + signal fsm_state : fsm_t; + +begin + + PROC_MEM : process + variable addr : integer range 0 to 15; + begin + wait until rising_edge(CLK_IN); + addr := to_integer(unsigned(BUS_ADDR_IN(3 downto 0))); + + BUS_ACK_OUT <= '0'; + BUS_BUSY_OUT <= '0'; + start <= '0'; + + if BUS_WRITE_IN = '1' then + if BUS_ADDR_IN(4) = '0' then + ram(addr) <= BUS_DATA_IN; + BUS_ACK_OUT <= '1'; + else + if fsm_state = IDLE then + ctrl_reg <= BUS_DATA_IN; + BUS_ACK_OUT <= '1'; + start <= '1'; + else + BUS_BUSY_OUT <= '1'; + end if; + end if; + end if; + + if BUS_READ_IN = '1' then + if BUS_ADDR_IN(4) = '0' then + BUS_DATA_OUT <= ram(addr); + else + BUS_DATA_OUT <= ctrl_reg; + end if; + BUS_ACK_OUT <= '1'; + end if; + + ram_data <= ram(ram_addr); + + end process; + + + + + PROC_FSM : process begin + wait until rising_edge(CLK_IN); + case fsm_state is + when IDLE => + + if start = '1' then + ram_addr <= 0; + word_count <= to_integer(unsigned(ctrl_reg(3 downto 0))); + bit_count <= 31; + time_count <= 7; + fsm_state <= WAIT_STATE; + spi_cs <= '0'; + else + spi_cs <= '1'; + spi_sck <= '1'; + end if; + + when WAIT_STATE => + if time_count = 0 then + fsm_state <= SET; + else + time_count <= time_count - 1; + end if; + + when SET => + time_count <= 7; + spi_sck <= not spi_sck; + if spi_sck = '1' then + spi_sd <= ram_data(bit_count); + if bit_count /= 0 then + bit_count <= bit_count - 1; + fsm_state <= WAIT_STATE; + else + ram_addr <= ram_addr + 1; + bit_count <= 31; + if ram_addr /= word_count -1 then + fsm_state <= WAIT_STATE; + else + fsm_state <= FINISH; + end if; + end if; + else + fsm_state <= WAIT_STATE; + end if; + when FINISH => + if time_count = 0 and spi_sck = '0' then + time_count <= 7; + spi_sck <= not spi_sck; + elsif time_count = 0 and spi_sck = '1' then + fsm_state <= IDLE; + else + time_count <= time_count - 1; + end if; + end case; + end process; + + + +-- Outputs + SPI_CS_OUT <= spi_cs; + SPI_SCK_OUT <= spi_sck; + SPI_SDO_OUT <= spi_sd; + + + +end architecture; \ No newline at end of file diff --git a/testbenches/tb_ltc2600.vhd b/testbenches/tb_ltc2600.vhd new file mode 100644 index 0000000..fb6fa32 --- /dev/null +++ b/testbenches/tb_ltc2600.vhd @@ -0,0 +1,103 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.all; + + + +entity tb is +end entity; + + +architecture tb_arch of tb is + +component spi_ltc2600 is + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + BUS_READ_IN : in std_logic; + BUS_WRITE_IN : in std_logic; + BUS_BUSY_OUT : out std_logic; + BUS_ACK_OUT : out std_logic; + BUS_ADDR_IN : in std_logic_vector(4 downto 0); + BUS_DATA_IN : in std_logic_vector(31 downto 0); + BUS_DATA_OUT : out std_logic_vector(31 downto 0); + -- SPI connections + SPI_CS_OUT : out std_logic; + SPI_SDI_IN : in std_logic; + SPI_SDO_OUT : out std_logic; + SPI_SCK_OUT : out std_logic + ); +end component; + + +signal clk: std_logic := '1'; +signal reset: std_logic := '1'; + +signal write : std_logic := '0'; +signal addr : std_logic_vector(4 downto 0) := "00000"; +signal data : std_logic_vector(31 downto 0) := (others => '0'); + + +begin + +clk <= not clk after 5 ns; +reset <= '0' after 100 ns; + +the_ctrl: process begin + wait for 200 ns; + wait until rising_edge(clk); wait for 2 ns; + addr <= "00000"; + data <= x"affedead"; + write <= '1'; + + wait until rising_edge(clk); wait for 2 ns; + addr <= "00001"; + data <= x"beeffeed"; + write <= '1'; + + wait until rising_edge(clk); wait for 2 ns; + addr <= "00010"; + data <= x"face5555"; + write <= '1'; + + wait until rising_edge(clk); wait for 2 ns; + addr <= "10000"; + data <= x"00000003"; + write <= '1'; + + wait until rising_edge(clk); wait for 2 ns; + write <= '0'; + + wait for 1000 ns; + wait until rising_edge(clk); wait for 2 ns; + write <= '1'; + wait until rising_edge(clk); wait for 2 ns; + write <= '0'; + wait; + + end process; + + + +THE_DAC: spi_ltc2600 + port map( + CLK_IN => clk, + RESET_IN => reset, + -- Slave bus + BUS_READ_IN => '0', + BUS_WRITE_IN => write, + BUS_BUSY_OUT => open, + BUS_ACK_OUT => open, + BUS_ADDR_IN => addr, + BUS_DATA_IN => data, + BUS_DATA_OUT => open, + -- SPI connections + SPI_CS_OUT => open, + SPI_SDI_IN => '0', + SPI_SDO_OUT => open, + SPI_SCK_OUT => open + ); + + +end architecture; \ No newline at end of file diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 76800fb..ed4057c 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -2096,6 +2096,48 @@ port( ); end component; + +component trb_net16_med_ecp3_sfp_4 is + generic( + REVERSE_ORDER : integer range 0 to 1 := c_NO; + FREQUENCY : integer range 125 to 200 := 200 --200 or 125 + -- USED_PORTS : std_logic-vector(3 downto 0) := "1111" + ); + port( + CLK : in std_logic; -- SerDes clock + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; + --Internal Connection + MED_DATA_IN : in std_logic_vector(4*c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(4*c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic_vector(3 downto 0); + MED_READ_OUT : out std_logic_vector(3 downto 0); + MED_DATA_OUT : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic_vector(3 downto 0); + MED_READ_IN : in std_logic_vector(3 downto 0); + REFCLK2CORE_OUT : out std_logic; + --SFP Connection + SD_RXD_P_IN : in std_logic_vector(3 downto 0); + SD_RXD_N_IN : in std_logic_vector(3 downto 0); + SD_TXD_P_OUT : out std_logic_vector(3 downto 0); + SD_TXD_N_OUT : out std_logic_vector(3 downto 0); + SD_REFCLK_P_IN : in std_logic; + SD_REFCLK_N_IN : in std_logic; + SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic_vector(3 downto 0); -- SFP disable + -- Status and control port + STAT_OP : out std_logic_vector (4*16-1 downto 0); + CTRL_OP : in std_logic_vector (4*16-1 downto 0); + STAT_DEBUG : out std_logic_vector (64*4-1 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) + ); +end component; + + component trb_net16_med_16_CC is port( CLK : in std_logic; @@ -2991,7 +3033,25 @@ end component; - +component spi_ltc2600 is + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + BUS_READ_IN : in std_logic; + BUS_WRITE_IN : in std_logic; + BUS_BUSY_OUT : out std_logic; + BUS_ACK_OUT : out std_logic; + BUS_ADDR_IN : in std_logic_vector(4 downto 0); + BUS_DATA_IN : in std_logic_vector(31 downto 0); + BUS_DATA_OUT : out std_logic_vector(31 downto 0); + -- SPI connections + SPI_CS_OUT : out std_logic; + SPI_SDI_IN : in std_logic; + SPI_SDO_OUT : out std_logic; + SPI_SCK_OUT : out std_logic + ); +end component; component signal_sync is -- 2.43.0