From 34dae42880b51bf0370936cae044be2924e67bc0 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Thu, 19 Aug 2010 09:27:49 +0000 Subject: [PATCH] *** empty log message *** --- lattice/ecp2m/pll_in100_out25.lpc | 6 +-- lattice/ecp2m/pll_in100_out25.vhd | 13 +++--- media_interfaces/ecp2m_fot/msg_file.log | 5 +- .../ecp2m_fot/serdes_fot_full_quad_ctc.lpc | 28 ++++++++--- .../ecp2m_fot/serdes_fot_full_quad_ctc.txt | 2 +- media_interfaces/trb_net16_lsm_sfp.vhd | 34 +++++++------- media_interfaces/trb_net16_med_ecp_fot.vhd | 37 +++++++++++---- .../trb_net16_med_ecp_fot_4_ctc.vhd | 26 +++++++---- media_interfaces/trb_net16_rx_checker.vhd | 44 +++++++++--------- .../trb_net16_rx_comma_handler.vhd | 7 ++- media_interfaces/trb_net16_rx_control.vhd | 12 ++++- .../trb_net16_rx_full_packets.vhd | 3 +- media_interfaces/trb_net16_tx_control.vhd | 2 +- pinout/cts_fpga2.lpf | 2 +- special/handler_trigger_and_data.vhd | 2 +- trb_net16_api_base.vhd | 6 ++- trb_net16_endpoint_hades_full.vhd | 26 ++++++++--- trb_net16_endpoint_hades_full_handler.vhd | 2 + trb_net16_hub_base.vhd | 46 +++++++++++++++---- trb_net16_hub_func.vhd | 7 +++ trb_net16_hub_streaming_port.vhd | 2 + trb_net16_regIO.vhd | 4 +- trb_net_components.vhd | 8 +++- 23 files changed, 219 insertions(+), 105 deletions(-) diff --git a/lattice/ecp2m/pll_in100_out25.lpc b/lattice/ecp2m/pll_in100_out25.lpc index 91af49f..630d528 100644 --- a/lattice/ecp2m/pll_in100_out25.lpc +++ b/lattice/ecp2m/pll_in100_out25.lpc @@ -16,8 +16,8 @@ CoreRevision=5.1 ModuleName=pll_in100_out25 SourceFormat=Schematic/VHDL ParameterFileVersion=1.0 -Date=03/12/2010 -Time=18:02:06 +Date=08/16/2010 +Time=18:01:31 [Parameters] Verilog=0 @@ -40,7 +40,7 @@ Div=4 Mult=1 Post=48 SecD=2 -fb_mode=Internal +fb_mode=CLKOP PhaseDuty=Static DelayControl=AUTO_NO_DELAY External=AUTO diff --git a/lattice/ecp2m/pll_in100_out25.vhd b/lattice/ecp2m/pll_in100_out25.vhd index d76bbde..da6ff0f 100644 --- a/lattice/ecp2m/pll_in100_out25.vhd +++ b/lattice/ecp2m/pll_in100_out25.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41) --- Module Version: 5.1 ---/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n pll_in100_out25 -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 100 -phase_cntl STATIC -fclkop 25 -fclkop_tol 0.0 -delay_cntl AUTO_NO_DELAY -fb_mode INTERNAL -extcap AUTO -noclkos -noclkok -norst -e +-- VHDL netlist generated by SCUBA ispLever_v8.1_PROD_Build (20) +-- Module Version: 5.2 +--/d/sugar/lattice/ispLEVER8.1/isptools/ispfpga/bin/lin/scuba -w -n pll_in100_out25 -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 100 -phase_cntl STATIC -fclkop 25 -fclkop_tol 0.0 -delay_cntl AUTO_NO_DELAY -fb_mode CLOCKTREE -extcap AUTO -noclkos -noclkok -norst -e --- Fri Mar 12 18:02:07 2010 +-- Mon Aug 16 18:01:32 2010 library IEEE; use IEEE.std_logic_1164.all; @@ -24,7 +24,6 @@ architecture Structure of pll_in100_out25 is -- internal signal declarations signal CLKOP_t: std_logic; - signal CLKFB_t: std_logic; signal scuba_vlo: std_logic; signal CLK_t: std_logic; @@ -98,12 +97,12 @@ begin PHASE_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", CLKOP_DIV=> 48, CLKFB_DIV=> 1, CLKI_DIV=> 4) -- synopsys translate_on - port map (CLKI=>CLK_t, CLKFB=>CLKFB_t, RST=>scuba_vlo, + port map (CLKI=>CLK_t, CLKFB=>CLKOP_t, RST=>scuba_vlo, RSTK=>scuba_vlo, DPAMODE=>scuba_vlo, DRPAI3=>scuba_vlo, DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, DFPAI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>open, - LOCK=>LOCK, CLKINTFB=>CLKFB_t); + LOCK=>LOCK, CLKINTFB=>open); CLKOP <= CLKOP_t; CLK_t <= CLK; diff --git a/media_interfaces/ecp2m_fot/msg_file.log b/media_interfaces/ecp2m_fot/msg_file.log index b208e4d..0b9c9fd 100644 --- a/media_interfaces/ecp2m_fot/msg_file.log +++ b/media_interfaces/ecp2m_fot/msg_file.log @@ -2,11 +2,12 @@ Core Name: PCS LPC file : serdes_fot_full_quad_ctc.lpc Parameter File : serdes_fot_full_quad_ctc.pp - Command line: /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/orcapp -Fmaco serdes_fot_full_quad_ctc.pp + Command line: /d/sugar/lattice/ispLEVER8.1/isptools/ispfpga/bin/lin/orcapp -Fmaco serdes_fot_full_quad_ctc.pp Return Value: - Module PCS has been generated in /home/hadaq/jan/cvs/trbnet/media_interfaces/ecp2m_fot/. successfully! + + Module PCS has been generated in /d/jspc22/trb/cvs/trbnet/media_interfaces/ecp2m_fot successfully! /home/hadaq/.isplever_lin/ispcpld/bin/hdl2jhd -tfi -mod serdes_fot_full_quad_ctc -ext readme -out serdes_fot_full_quad_ctc -tpl serdes_fot_full_quad_ctc.tft serdes_fot_full_quad_ctc.vhd diff --git a/media_interfaces/ecp2m_fot/serdes_fot_full_quad_ctc.lpc b/media_interfaces/ecp2m_fot/serdes_fot_full_quad_ctc.lpc index 6cf511c..f8c2bf4 100644 --- a/media_interfaces/ecp2m_fot/serdes_fot_full_quad_ctc.lpc +++ b/media_interfaces/ecp2m_fot/serdes_fot_full_quad_ctc.lpc @@ -1,9 +1,9 @@ [Device] Family=latticeecp2m -PartType=LFE2M20E -PartName=LFE2M20E-5F256C +PartType=LFE2M100E +PartName=LFE2M100E-5F900C SpeedGrade=-5 -Package=FPBGA256 +Package=FPBGA900 OperatingCondition=COM Status=P @@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation CoreType=LPM CoreStatus=Demo CoreName=PCS -CoreRevision=7.0 +CoreRevision=8.1 ModuleName=serdes_fot_full_quad_ctc SourceFormat=Schematic/VHDL ParameterFileVersion=1.0 -Date=09/09/2009 -Time=13:37:15 +Date=08/18/2010 +Time=23:30:13 [Parameters] Verilog=0 @@ -138,3 +138,19 @@ Ports2=FALSE Ports3=FALSE Ports3_1=FALSE Ports4=FALSE +_rst_gen=DISABLED +_rx_los_port0=Internal +_rx_los_port1=Internal +_rx_los_port2=Internal +_rx_los_port3=Internal +Regen=auto +PAR1=0 +PARTrace1=0 +PAR3=0 +PARTrace3=0 + +[FilesGenerated] +serdes_fot_full_quad_ctc.pp=pp +serdes_fot_full_quad_ctc.tft=tft +serdes_fot_full_quad_ctc.txt=pcs_module +serdes_fot_full_quad_ctc.sym=sym diff --git a/media_interfaces/ecp2m_fot/serdes_fot_full_quad_ctc.txt b/media_interfaces/ecp2m_fot/serdes_fot_full_quad_ctc.txt index 855fb83..678e4a8 100644 --- a/media_interfaces/ecp2m_fot/serdes_fot_full_quad_ctc.txt +++ b/media_interfaces/ecp2m_fot/serdes_fot_full_quad_ctc.txt @@ -4,7 +4,7 @@ # selected in the IPexpress. This file is expected to be modified by the # end user to adjust the PCSC quad to the final design requirements. -DEVICE_NAME "LFE2M20E" +DEVICE_NAME "LFE2M100E" PROTOCOL "GIGE" CH0_MODE "SINGLE" CH1_MODE "SINGLE" diff --git a/media_interfaces/trb_net16_lsm_sfp.vhd b/media_interfaces/trb_net16_lsm_sfp.vhd index a325462..ea34c51 100644 --- a/media_interfaces/trb_net16_lsm_sfp.vhd +++ b/media_interfaces/trb_net16_lsm_sfp.vhd @@ -210,11 +210,12 @@ begin next_lane_rst <= '1'; end if; when WPAR => - if ( (sfp_missing_in = '1') or ( sfp_los_in = '1') ) then - NEXT_STATE <= SLEEP; -- SFP has been removed - next_lane_rst <= '1'; - next_ce_tctr <= '1'; - elsif( (sd_rxclk_bad_in = '0') and (sd_txclk_bad_in = '0') ) then -- +-- if ( (sfp_missing_in = '1') or ( sfp_los_in = '1') ) then +-- NEXT_STATE <= SLEEP; -- SFP has been removed +-- next_lane_rst <= '1'; +-- next_ce_tctr <= '1'; +-- els + if( (sd_rxclk_bad_in = '0') and (sd_txclk_bad_in = '0') ) then -- NEXT_STATE <= WLOS; -- PLLs locked, signal present next_rst_tctr <= '1'; else @@ -302,11 +303,12 @@ begin next_med_error <= ERROR_WAIT; end if; when LINK => - if ( (sfp_missing_in = '1') or (sfp_los_in = '1') ) then - NEXT_STATE <= SLEEP; - next_lane_rst <= '1'; - next_rst_tctr <= '1'; - elsif( sd_cv_in /= "00" ) and CHECK_FOR_CV = c_YES then +-- if ( (sfp_missing_in = '1') or (sfp_los_in = '1') ) then +-- NEXT_STATE <= SLEEP; +-- next_lane_rst <= '1'; +-- next_rst_tctr <= '1'; +-- els + if( sd_cv_in /= "00" ) and CHECK_FOR_CV = c_YES then NEXT_STATE <= CVFND; next_ce_cctr <= '1'; -- increment CV counter next_rx_allow <= '1'; @@ -336,15 +338,15 @@ begin next_med_error <= ERROR_FATAL; end if; when CVBAD => - if ( (sfp_missing_in = '1') or (sfp_los_in = '1') ) then - NEXT_STATE <= SLEEP; - next_lane_rst <= '1'; - next_rst_tctr <= '1'; - else +-- if ( (sfp_missing_in = '1') or (sfp_los_in = '1') ) then +-- NEXT_STATE <= SLEEP; +-- next_lane_rst <= '1'; +-- next_rst_tctr <= '1'; +-- else NEXT_STATE <= CVBAD; next_ce_tctr <= '1'; next_med_error <= ERROR_FATAL; - end if; +-- end if; when others => NEXT_STATE <= QRST; end case; if ( (sfp_missing_in = '1') or (sfp_los_in = '1') or RESET = '1') and CURRENT_STATE /= QRST then diff --git a/media_interfaces/trb_net16_med_ecp_fot.vhd b/media_interfaces/trb_net16_med_ecp_fot.vhd index e0b0942..41c025f 100644 --- a/media_interfaces/trb_net16_med_ecp_fot.vhd +++ b/media_interfaces/trb_net16_med_ecp_fot.vhd @@ -115,6 +115,7 @@ attribute HGROUP of trb_net16_med_ecp_fot_arch : architecture is "GROUP_PCS"; signal tx_allow : std_logic; signal rx_allow : std_logic; signal tx_allow_qtx : std_logic; + signal rx_allow_qrx : std_logic; signal sd_q : std_logic; signal sfp_los : std_logic; @@ -139,6 +140,8 @@ attribute HGROUP of trb_net16_med_ecp_fot_arch : architecture is "GROUP_PCS"; signal last_tx_k : std_logic; signal request_cnt_i : unsigned(7 downto 0); signal reset_rx_control : std_logic; + signal send_reset_words_ext : std_logic; + begin ----------------------------------------------------------------------- @@ -207,7 +210,7 @@ begin REQUEST_POSITION_IN => request_position_i, START_RETRANSMIT_IN => start_retransmit_i, START_POSITION_IN => start_position_i, - SEND_LINK_RESET_IN => send_reset_words, + SEND_LINK_RESET_IN => send_reset_words_ext, TX_ALLOW_IN => tx_allow, DEBUG_OUT => debug_txcontrol_i @@ -227,7 +230,7 @@ begin RX_K_IN => rx_k, RX_CV_IN => link_error(1), RX_DISP_ERR_IN => link_error(0), - RX_ALLOW_IN => rx_allow, + RX_ALLOW_IN => rx_allow_qrx, -- media interface SYSCLK_IN => CLK, MED_DATA_OUT => buf_med_data_out, @@ -246,6 +249,7 @@ begin -- Status signals PACKET_TIMEOUT_OUT => packet_timeout_i, -- Debugging + ENABLE_CORRECTION_IN => CTRL_OP(8), DEBUG_OUT => debug_rxcontrol_i ); @@ -298,22 +302,37 @@ reset_rx_control <= RESET or lane_rst or link_error_q(2) or link_error_q(7); --Synchronizer ----------------------------------------------------------------------- + CLK_TO_RX_SYNC : signal_sync + generic map( + DEPTH => 2, + WIDTH => 1 + ) + port map( + RESET => '0', + D_IN(0) => rx_allow, + CLK0 => CLK, + CLK1 => ff_rxfullclk, + D_OUT(0)=> rx_allow_qrx + ); + CLK_TO_TX_SYNC: signal_sync generic map( DEPTH => 2, - WIDTH => 3 + WIDTH => 4 ) port map( - RESET => reset, + RESET => '0', D_IN(0) => tx_allow, D_IN(1) => lane_rst, D_IN(2) => quad_rst, + D_IN(3) => CTRL_OP(15), CLK0 => CLK, CLK1 => ff_txfullclk, D_OUT(0) => tx_allow_qtx, D_OUT(1) => lane_rst_qtx, - D_OUT(2) => quad_rst_qtx + D_OUT(2) => quad_rst_qtx, + D_OUT(3) => send_reset_words_ext ); RX_TO_CLK_SYNC: signal_sync @@ -322,7 +341,7 @@ reset_rx_control <= RESET or lane_rst or link_error_q(2) or link_error_q(7); WIDTH => 9 ) port map( - RESET => reset, + RESET => '0', D_IN(7 downto 0) => link_error, D_IN(8) => link_ok, CLK0 => ff_rxfullclk, @@ -337,7 +356,7 @@ reset_rx_control <= RESET or lane_rst or link_error_q(2) or link_error_q(7); WIDTH => 1 ) port map( - RESET => reset, + RESET => '0', D_IN(0) => sd, CLK0 => CLK, CLK1 => CLK, @@ -385,14 +404,14 @@ reset_rx_control <= RESET or lane_rst or link_error_q(2) or link_error_q(7); STAT_REG_OUT(11 downto 0) <= (others => '0'); --reserved for trigger information STAT_REG_OUT(23 downto 12) <= (others => '0'); - STAT_REG_OUT(31 downto 24) <= std_logic_vector(request_cnt_i); + STAT_REG_OUT(31 downto 24) <= (others => '0'); STAT_OP(7 downto 0) <= FSM_STAT_OP(7 downto 0); STAT_OP(8) <= start_retransmit_i; STAT_OP(9) <= FSM_STAT_OP(9); STAT_OP(10) <= rx_led; STAT_OP(11) <= tx_led; - STAT_OP(12) <= request_retransmit_i; + STAT_OP(12) <= request_retransmit_i when CTRL_OP(8) = '1' else (link_error(1) and not send_reset_words and tx_allow); STAT_OP(13) <= make_trbnet_reset; STAT_OP(14) <= FSM_STAT_OP(14); STAT_OP(15) <= send_reset_words; diff --git a/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd b/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd index e111003..175d5c1 100644 --- a/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd +++ b/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd @@ -16,6 +16,7 @@ port( CLK_25 : in std_logic; CLK_EN : in std_logic; RESET : in std_logic; + CLEAR : in std_logic; --Internal Connection MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH*4-1 downto 0); @@ -211,6 +212,8 @@ signal tx_allow_qtx : std_logic_vector(3 downto 0); signal rx_allow : std_logic_vector(3 downto 0); +signal rx_allow_qtx : std_logic_vector(3 downto 0); + signal sd_q : std_logic_vector(3 downto 0); signal buf_med_dataready_out : std_logic_vector(3 downto 0); @@ -241,6 +244,7 @@ signal start_position_i : std_logic_vector(31 downto 0); signal send_reset_words_ext : std_logic_vector(3 downto 0); signal request_cnt_i : link_error_t; signal reset_rx_control : std_logic_vector(3 downto 0); +signal enable_correction_i : std_logic_vector(3 downto 0); attribute syn_keep : boolean; @@ -535,7 +539,6 @@ gen_logic : for i in 0 to 3 generate START_POSITION_IN => start_position_i(i*8+7 downto i*8), SEND_LINK_RESET_IN => send_reset_words_ext(i), TX_ALLOW_IN => tx_allow(i), - DEBUG_OUT => debug_txcontrol_i(i*32+31 downto i*32) ); @@ -554,7 +557,7 @@ gen_logic : for i in 0 to 3 generate RX_K_IN => rx_k(i), RX_CV_IN => link_error(i)(1), RX_DISP_ERR_IN => link_error(i)(0), - RX_ALLOW_IN => rx_allow(i), + RX_ALLOW_IN => rx_allow_qtx(i), -- media interface SYSCLK_IN => CLK, MED_DATA_OUT => buf_med_data_out(i*16+15 downto i*16), @@ -572,6 +575,7 @@ gen_logic : for i in 0 to 3 generate MAKE_TRBNET_RESET_OUT => make_trbnet_reset(i), -- Status signals PACKET_TIMEOUT_OUT => packet_timeout_i(i), + ENABLE_CORRECTION_IN => enable_correction_i(i), -- Debugging DEBUG_OUT => debug_rxcontrol_i(i*32+31 downto i*32) ); @@ -589,7 +593,7 @@ reset_rx_control(i) <= RESET or lane_rst(i) or link_error_q(i)(2) or link_error_ port map( SYSCLK => CLK, RESET => reset, - CLEAR => reset, + CLEAR => clear, SFP_MISSING_IN => '0', SFP_LOS_IN => sfp_los(i), SD_LINK_OK_IN => link_ok_q(i), @@ -620,20 +624,24 @@ reset_rx_control(i) <= RESET or lane_rst(i) or link_error_q(i)(2) or link_error_ CLK_TO_TX_SYNC: signal_sync generic map( DEPTH => 2, - WIDTH => 4 + WIDTH => 6 ) port map( - RESET => reset, + RESET => '0', D_IN(0) => tx_allow(i), D_IN(1) => lane_rst(i), D_IN(2) => quad_rst(i), D_IN(3) => CTRL_OP(i*16+15), + D_IN(4) => rx_allow(i), + D_IN(5) => CTRL_OP(i*16+8), CLK0 => CLK, CLK1 => CLK_25, D_OUT(0) => tx_allow_qtx(i), D_OUT(1) => lane_rst_qtx(i), D_OUT(2) => quad_rst_qtx(i), - D_OUT(3) => send_reset_words_ext(i) + D_OUT(3) => send_reset_words_ext(i), + D_OUT(4) => rx_allow_qtx(i), + D_OUT(5) => enable_correction_i(i) ); RX_TO_CLK_SYNC: signal_sync @@ -642,7 +650,7 @@ reset_rx_control(i) <= RESET or lane_rst(i) or link_error_q(i)(2) or link_error_ WIDTH => 9 ) port map( - RESET => reset, + RESET => '0', D_IN(7 downto 0) => link_error(i), D_IN(8) => link_ok(i), CLK0 => CLK_25, @@ -657,7 +665,7 @@ reset_rx_control(i) <= RESET or lane_rst(i) or link_error_q(i)(2) or link_error_ WIDTH => 1 ) port map( - RESET => reset, + RESET => '0', D_IN(0) => sd(i), CLK0 => CLK, CLK1 => CLK, @@ -678,7 +686,7 @@ reset_rx_control(i) <= RESET or lane_rst(i) or link_error_q(i)(2) or link_error_ STAT_OP(i*16+9) <= FSM_STAT_OP(i*16+9); STAT_OP(i*16+10) <= rx_led(i); STAT_OP(i*16+11) <= tx_led(i); - STAT_OP(i*16+12) <= packet_timeout_i(i); --FSM_STAT_OP(i*16+12); + STAT_OP(i*16+12) <= request_retransmit_i(i) when CTRL_OP(i*16+8) = '1' else (link_error(i)(1) and not send_reset_words(i) and tx_allow(i)); STAT_OP(i*16+13) <= make_trbnet_reset(i); STAT_OP(i*16+14) <= FSM_STAT_OP(i*16+14); STAT_OP(i*16+15) <= send_reset_words(i); diff --git a/media_interfaces/trb_net16_rx_checker.vhd b/media_interfaces/trb_net16_rx_checker.vhd index 4cefac7..44f2f3c 100644 --- a/media_interfaces/trb_net16_rx_checker.vhd +++ b/media_interfaces/trb_net16_rx_checker.vhd @@ -31,7 +31,7 @@ architecture behavioral of trb_net16_rx_checker is -- state declarations type STATES is (IDLE, CHK_PKT, RX_FAIL, WAIT_STX, DONE); -signal CURRENT_STATE, NEXT_STATE: STATES; +signal current_state, next_state: STATES; signal bsm_x : std_logic_vector(3 downto 0); signal bsm : std_logic_vector(3 downto 0); @@ -48,7 +48,7 @@ signal debug : std_logic_vector(15 downto 0); begin ---------------------------------------------------------------------- --- +-- ---------------------------------------------------------------------- ---------------------------------------------------------------------- @@ -59,13 +59,13 @@ STATE_MEM: process( SYSCLK_IN ) begin if( rising_edge(SYSCLK_IN) ) then if( RESET_IN = '1' ) then - CURRENT_STATE <= IDLE; + current_state <= IDLE; fifo_rst <= '0'; resume <= '0'; request <= '0'; bsm <= (others => '0'); else - CURRENT_STATE <= NEXT_STATE; + current_state <= next_state; fifo_rst <= fifo_rst_x; resume <= resume_x; request <= request_x; @@ -75,56 +75,56 @@ begin end process STATE_MEM; -- state transitions -STATE_TRANSFORM: process( CURRENT_STATE, PKT_TOC_IN, RX_IC_IN, STX_FND_IN, PKT_IN_TRANS_IN ) +STATE_TRANSFORM: process( current_state, PKT_TOC_IN, RX_IC_IN, STX_FND_IN, PKT_IN_TRANS_IN ) begin - NEXT_STATE <= IDLE; -- avoid latches + next_state <= IDLE; -- avoid latches fifo_rst_x <= '0'; resume_x <= '0'; request_x <= '0'; - case CURRENT_STATE is + case current_state is when IDLE => if ( PKT_TOC_IN = '1' ) then - NEXT_STATE <= RX_FAIL; + next_state <= RX_FAIL; fifo_rst_x <= '1'; elsif( RX_IC_IN = '1' ) then - NEXT_STATE <= CHK_PKT; + next_state <= CHK_PKT; else - NEXT_STATE <= IDLE; + next_state <= IDLE; end if; - when CHK_PKT => + when CHK_PKT => if( PKT_IN_TRANS_IN = '1' ) then - NEXT_STATE <= CHK_PKT; + next_state <= CHK_PKT; else - NEXT_STATE <= RX_FAIL; + next_state <= RX_FAIL; fifo_rst_x <= '1'; end if; when RX_FAIL => - NEXT_STATE <= WAIT_STX; + next_state <= WAIT_STX; fifo_rst_x <= '1'; request_x <= '1'; - when WAIT_STX => + when WAIT_STX => if( STX_FND_IN = '1' ) then - NEXT_STATE <= DONE; + next_state <= DONE; resume_x <= '1'; else - NEXT_STATE <= WAIT_STX; + next_state <= WAIT_STX; fifo_rst_x <= '1'; end if; when DONE => if( PKT_TOC_IN = '0' ) then - NEXT_STATE <= IDLE; + next_state <= IDLE; else - NEXT_STATE <= DONE; + next_state <= DONE; end if; when others => - NEXT_STATE <= IDLE; + next_state <= IDLE; end case; end process STATE_TRANSFORM; -- just for debugging -THE_DECODE_PROC: process( NEXT_STATE ) +THE_DECODE_PROC: process( next_state ) begin - case NEXT_STATE is + case next_state is when IDLE => bsm_x <= x"0"; when CHK_PKT => bsm_x <= x"1"; when RX_FAIL => bsm_x <= x"2"; diff --git a/media_interfaces/trb_net16_rx_comma_handler.vhd b/media_interfaces/trb_net16_rx_comma_handler.vhd index 6d5d4b4..25fbb65 100644 --- a/media_interfaces/trb_net16_rx_comma_handler.vhd +++ b/media_interfaces/trb_net16_rx_comma_handler.vhd @@ -31,6 +31,7 @@ port( -- reset handling SEND_RESET_WORDS_OUT : out std_logic; MAKE_TRBNET_RESET_OUT : out std_logic; + ENABLE_CORRECTION_IN : in std_logic; -- Debugging DEBUG_OUT : out std_logic_vector(15 downto 0) ); @@ -232,7 +233,7 @@ fifo_wr_x <= comma_toggle and data_valid_x and not fifo_inhibit; THE_FIFO_INHIBIT_PROC: process( CLK_IN ) begin if( rising_edge(CLK_IN) ) then - if ( (RESET_IN = '1') or (comma_stx = '1') ) then + if ( (RESET_IN = '1') or (comma_stx = '1') or ENABLE_CORRECTION_IN = '0') then fifo_inhibit <= '0'; elsif( (comma_locked = '1') and (comma_toggle = '1') and (comma_valid_x = '0') and (data_valid_x = '0') ) then fifo_inhibit <= '1'; @@ -246,7 +247,9 @@ end process THE_FIFO_INHIBIT_PROC; debug(15) <= comma_valid_x; debug(14) <= data_valid_x; debug(13) <= fifo_inhibit; -debug(12 downto 0) <= (others => '0'); +debug(12) <= c_reset; +debug(11) <= reset_word_cnt(4); +debug(10 downto 0) <= (others => '0'); ---------------------------------------------------------------------- -- Output signals diff --git a/media_interfaces/trb_net16_rx_control.vhd b/media_interfaces/trb_net16_rx_control.vhd index 06c31fe..efa5096 100644 --- a/media_interfaces/trb_net16_rx_control.vhd +++ b/media_interfaces/trb_net16_rx_control.vhd @@ -36,6 +36,7 @@ port( PACKET_TIMEOUT_OUT : out std_logic; COMMA_LOCKED_OUT : out std_logic; -- Debugging + ENABLE_CORRECTION_IN : in std_logic; DEBUG_OUT : out std_logic_vector(31 downto 0) ); end entity; @@ -70,6 +71,7 @@ port( -- reset handling SEND_RESET_WORDS_OUT : out std_logic; MAKE_TRBNET_RESET_OUT : out std_logic; + ENABLE_CORRECTION_IN : in std_logic; -- Debugging DEBUG_OUT : out std_logic_vector(15 downto 0) ); @@ -97,6 +99,7 @@ port( RX_DATA_CTR_VAL_IN : in std_logic_vector(7 downto 0); RX_DATA_CTR_OUT : out std_logic_vector(7 downto 0); PACKET_TIMEOUT_OUT : out std_logic; + ENABLE_CORRECTION_IN : in std_logic; -- Debug signals BSM_OUT : out std_logic_vector(3 downto 0); DBG_OUT : out std_logic_vector(15 downto 0) @@ -220,7 +223,7 @@ port map( -- FIFO interface FIFO_DATA_OUT => fifo_wr_data, FIFO_WR_OUT => fifo_wr_en, - FIFO_INHIBIT_OUT => rx_gone_wrong_x, -- BUG + FIFO_INHIBIT_OUT => rx_gone_wrong_x, -- Special comma actions LD_RX_POSITION_OUT => ld_rx_position_x, RX_POSITION_OUT => rx_position, @@ -231,6 +234,7 @@ port map( -- reset handling SEND_RESET_WORDS_OUT => send_reset_words, MAKE_TRBNET_RESET_OUT => make_trbnet_reset, + ENABLE_CORRECTION_IN => ENABLE_CORRECTION_IN, -- Debugging DEBUG_OUT => debug_rch ); @@ -311,6 +315,7 @@ port map( RX_DATA_CTR_VAL_IN => rx_position, RX_DATA_CTR_OUT => request_position, PACKET_TIMEOUT_OUT => packet_timeout, + ENABLE_CORRECTION_IN => ENABLE_CORRECTION_IN, -- Debug signals BSM_OUT => open, DBG_OUT => debug_rfp @@ -356,7 +361,10 @@ debug(31 downto 16) <= debug_rfp; debug(0) <= packet_timeout; debug(1) <= rx_gone_wrong; debug(2) <= pkt_in_transit; -debug(15 downto 3) <= debug_rch(15 downto 3); +debug(3) <= comma_locked; +debug(4) <= debug_rch(11); +debug(5) <= debug_rch(12); +debug(15 downto 4) <= debug_rch(15 downto 4); ---------------------------------------------------------------------- diff --git a/media_interfaces/trb_net16_rx_full_packets.vhd b/media_interfaces/trb_net16_rx_full_packets.vhd index aca3bbf..381a40d 100644 --- a/media_interfaces/trb_net16_rx_full_packets.vhd +++ b/media_interfaces/trb_net16_rx_full_packets.vhd @@ -28,6 +28,7 @@ port( RX_DATA_CTR_VAL_IN : in std_logic_vector(7 downto 0); RX_DATA_CTR_OUT : out std_logic_vector(7 downto 0); PACKET_TIMEOUT_OUT : out std_logic; + ENABLE_CORRECTION_IN : in std_logic; -- Debug signals BSM_OUT : out std_logic_vector(3 downto 0); DBG_OUT : out std_logic_vector(15 downto 0) @@ -358,7 +359,7 @@ begin end if; end process THE_TOC_PROC; -toc_done_x <= '1' when ( timeout_ctr(9 downto 2) = b"11_1111_11" ) else '0'; +toc_done_x <= '1' when ( timeout_ctr(9 downto 2) = b"11_1111_11" and ENABLE_CORRECTION_IN = '1') else '0'; ---------------------------------------------------------------------- -- Debug signals diff --git a/media_interfaces/trb_net16_tx_control.vhd b/media_interfaces/trb_net16_tx_control.vhd index d74e3c9..f452b46 100644 --- a/media_interfaces/trb_net16_tx_control.vhd +++ b/media_interfaces/trb_net16_tx_control.vhd @@ -284,7 +284,7 @@ THE_RAM_WR_PROC : process(TXCLK_IN) DEPTH => 2 ) port map( - RESET => RESET_IN, + RESET => '0', CLK0 => TXCLK_IN, CLK1 => TXCLK_IN, D_IN(0) => TX_ALLOW_IN, diff --git a/pinout/cts_fpga2.lpf b/pinout/cts_fpga2.lpf index 5b64695..65553ce 100644 --- a/pinout/cts_fpga2.lpf +++ b/pinout/cts_fpga2.lpf @@ -238,7 +238,7 @@ LOCATE COMP "RAM_TDO" SITE "E26"; LOCATE COMP "RAM_TMS" SITE "E21"; DEFINE PORT GROUP "RAM_group" "RAM*" ; -IOBUF GROUP "RAM_group" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=12; +IOBUF GROUP "RAM_group" IO_TYPE=LVCMOS25 PULLMODE=UP; ################################################################# diff --git a/special/handler_trigger_and_data.vhd b/special/handler_trigger_and_data.vhd index 7b31d85..6373e76 100644 --- a/special/handler_trigger_and_data.vhd +++ b/special/handler_trigger_and_data.vhd @@ -120,7 +120,7 @@ begin variable tmp_statusbits : std_logic_vector(31 downto 0); begin if rising_edge(CLOCK) then - if RESET = '1' or buf_lvl1_trg_release = '1' then + if RESET = '1' or buf_lvl1_trg_release = '1' or LVL1_VALID_TRIGGER_IN = '1' then fee_trg_statusbits <= (others => '0'); fee_trg_release <= (others => '0'); else diff --git a/trb_net16_api_base.vhd b/trb_net16_api_base.vhd index 3eeaa33..afaab69 100644 --- a/trb_net16_api_base.vhd +++ b/trb_net16_api_base.vhd @@ -19,7 +19,8 @@ entity trb_net16_api_base is SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES; APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_YES; ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; - BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF" + BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; + BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF" ); port( @@ -649,7 +650,8 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; end if; if INT_SLAVE_PACKET_NUM_IN = c_F1 then if ((INT_SLAVE_DATA_IN and ADDRESS_MASK) = (APL_MY_ADDRESS_IN and ADDRESS_MASK)) - or (and_all(not((not INT_SLAVE_DATA_IN) and (x"FF" & BROADCAST_BITMASK))) = '1') then + or (and_all(not((not INT_SLAVE_DATA_IN) and (x"FF" & BROADCAST_BITMASK))) = '1') + or (INT_SLAVE_DATA_IN = x"FE" & BROADCAST_SPECIAL_ADDR) then next_state_to_apl <= sa_MY_ADDR; slave_start <= '1'; else diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd index 8d8e7fc..f740cd5 100644 --- a/trb_net16_endpoint_hades_full.vhd +++ b/trb_net16_endpoint_hades_full.vhd @@ -27,6 +27,7 @@ entity trb_net16_endpoint_hades_full is APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO); ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; + BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF"; TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES; REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers @@ -297,8 +298,8 @@ begin end if; end process; - --MED_CTRL_OP_OUT(15) <= MED_STAT_OP_IN(15); - MED_CTRL_OP_OUT(15 downto 0) <= (others => '0'); + MED_CTRL_OP_OUT(15 downto 0) <= (8 => buf_REGIO_COMMON_CTRL_REG_OUT(64+27), + others => '0'); MED_STAT_OP <= MED_STAT_OP_IN; --Connections for data channel @@ -386,7 +387,8 @@ begin SECURE_MODE_TO_INT => API_SECURE_MODE_TO_INT(i), APL_WRITE_ALL_WORDS=> APL_WRITE_ALL_WORDS(i), ADDRESS_MASK => ADDRESS_MASK, - BROADCAST_BITMASK => BROADCAST_BITMASK + BROADCAST_BITMASK => BROADCAST_BITMASK, + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR ) port map ( -- Misc @@ -797,8 +799,7 @@ begin end if; buf_COMMON_STAT_REG_IN(47 downto 32) <= int_trigger_num; buf_COMMON_STAT_REG_IN(127 downto 64) <= stat_lvl1_handler; - buf_COMMON_STAT_REG_IN(131 downto 128) <= link_and_reset_status(3 downto 0); - buf_COMMON_STAT_REG_IN(136) <= link_error_i; + buf_COMMON_STAT_REG_IN(159 downto 128) <= link_and_reset_status(31 downto 0); end process; @@ -819,6 +820,19 @@ begin if make_trbnet_reset = '1' then link_and_reset_status(3 downto 0) <= link_and_reset_status(3 downto 0) + '1'; end if; + + if MED_STAT_OP_IN(12) = '1' then + link_and_reset_status(31 downto 24) <= link_and_reset_status(31 downto 24) + '1'; + end if; + + if MED_STAT_OP_IN(8) = '1' then + link_and_reset_status(23 downto 16) <= link_and_reset_status(23 downto 16) + '1'; + end if; + + if buf_REGIO_COMMON_CTRL_REG_OUT(5) = '1' then + link_and_reset_status <= (others => '0'); + end if; + end if; end process; @@ -927,7 +941,7 @@ begin begin if rising_edge(CLK) then last_reg_timing_trigger <= reg_timing_trigger; - trigger_timing_rising <= reg_timing_trigger and not last_reg_timing_trigger and buf_REGIO_COMMON_CTRL_REG_OUT(95); + trigger_timing_rising <= reg_timing_trigger and not last_reg_timing_trigger; -- and buf_REGIO_COMMON_CTRL_REG_OUT(95); last_LVL1_TRG_RECEIVED_OUT <= buf_LVL1_TRG_RECEIVED_OUT; LVL1_TRG_RECEIVED_OUT_rising <= buf_LVL1_TRG_RECEIVED_OUT and not last_LVL1_TRG_RECEIVED_OUT; diff --git a/trb_net16_endpoint_hades_full_handler.vhd b/trb_net16_endpoint_hades_full_handler.vhd index 482152b..cf1c6f6 100644 --- a/trb_net16_endpoint_hades_full_handler.vhd +++ b/trb_net16_endpoint_hades_full_handler.vhd @@ -17,6 +17,7 @@ entity trb_net16_endpoint_hades_full_handler is APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO); ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; + BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF"; REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers REGIO_INIT_CTRL_REGS : std_logic_vector(16*32-1 downto 0) := (others => '0'); @@ -220,6 +221,7 @@ begin APL_WRITE_ALL_WORDS => APL_WRITE_ALL_WORDS, ADDRESS_MASK => ADDRESS_MASK, BROADCAST_BITMASK => BROADCAST_BITMASK, + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, REGIO_INIT_CTRL_REGS => REGIO_INIT_CTRL_REGS, diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index 029559b..f4051df 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -22,6 +22,11 @@ entity trb_net16_hub_base is IBUF_SECURE_MODE : integer range 0 to 1 := c_NO; INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004"; INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0'); + INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := + x"00000000_00000000_00000000_00000000" & + x"00000000_00000000_00000000_00000000" & + x"00000000_00000000_000050FF_00000000" & + x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF"; COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; @@ -29,6 +34,7 @@ entity trb_net16_hub_base is HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; CLOCK_FREQUENCY : integer range 1 to 200 := 100; USE_ONEWIRE : integer range 0 to 2 := c_YES; + BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF"; --media interfaces MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 4; MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH; @@ -316,6 +322,11 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal lsm_data : std_logic_vector(31 downto 0); signal next_lsm_data : std_logic_vector(31 downto 0); signal last_lsm_read : std_logic; + signal next_last_lsm_read : std_logic; + + type counter8b_t is array (0 to 15) of unsigned(7 downto 0); + signal received_retransmit_requests : counter8b_t; + signal sent_retransmit_requests : counter8b_t; attribute syn_preserve : boolean; attribute syn_keep : boolean; @@ -374,6 +385,7 @@ begin begin if rising_edge(CLK) then MED_CTRL_OP(12+i*16 downto i*16) <= (others => '0'); + MED_CTRL_OP(8+i*16) <= HC_COMMON_CTRL_REGS(64+27); MED_CTRL_OP(13+i*16) <= local_reset_med(i); MED_CTRL_OP(14+i*16) <= HUB_CTRL_media_interfaces_off(i); if MII_IS_UPLINK(i) = 0 then @@ -591,7 +603,8 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; FIFO_TO_INT_DEPTH => HUB_CTRL_DEPTH, FIFO_TO_APL_DEPTH => HUB_CTRL_DEPTH, ADDRESS_MASK => HUB_CTRL_ADDRESS_MASK, - BROADCAST_BITMASK => HUB_CTRL_BROADCAST_BITMASK + BROADCAST_BITMASK => HUB_CTRL_BROADCAST_BITMASK, + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR ) port map( -- Misc @@ -933,12 +946,9 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; generic map( NUM_STAT_REGS => 6, NUM_CTRL_REGS => 4, - INIT_CTRL_REGS => x"00000000_00000000_00000000_00000000" & - x"00000000_00000000_00000000_00000000" & - x"00000000_00000000_000050FF_00000000" & - x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF", - USED_CTRL_REGS => (others => '1'), - USED_CTRL_BITMASK => (others => '1'), + INIT_CTRL_REGS => INIT_CTRL_REGS, + USED_CTRL_REGS => (others => '1'), + USED_CTRL_BITMASK => (others => '1'), USE_DAT_PORT => c_YES, INIT_ADDRESS => INIT_ADDRESS, INIT_UNIQUE_ID => INIT_UNIQUE_ID, @@ -1360,13 +1370,31 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); begin tmp := to_integer(unsigned(lsm_addr)); if rising_edge(CLK) then - last_lsm_read <= lsm_read; + next_last_lsm_read <= lsm_read; + last_lsm_read <= next_last_lsm_read; next_lsm_data(7 downto 0) <= MED_STAT_OP(tmp*16+7 downto tmp*16+0); - next_lsm_data(31 downto 8) <= (others => '0'); + next_lsm_data(15 downto 8) <= (others => '0'); + next_lsm_data(23 downto 16) <= received_retransmit_requests(tmp); + next_lsm_data(31 downto 24) <= sent_retransmit_requests(tmp); lsm_data <= next_lsm_data; end if; end process; + gen_retransmit_counters : for i in 0 to MII_NUMBER-1 generate + proc_retransmit_counters : process(CLK) + begin + if rising_edge(CLK) then + if MED_STAT_OP(i*16+12) = '1' then + sent_retransmit_requests(i) <= sent_retransmit_requests(i) + to_unsigned(1,1); + end if; + if MED_STAT_OP(i*16+8) = '1' then + received_retransmit_requests(i) <= received_retransmit_requests(i) + to_unsigned(1,1); + end if; + end if; + end process; + end generate; + + ------------------------------------ --STAT busy counters ------------------------------------ diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd index 484e42c..6ae6e06 100644 --- a/trb_net16_hub_func.vhd +++ b/trb_net16_hub_func.vhd @@ -95,6 +95,11 @@ package trb_net16_hub_func is IBUF_SECURE_MODE : integer range 0 to 1 := c_NO; INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004"; INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0'); + INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := + x"00000000_00000000_00000000_00000000" & + x"00000000_00000000_00000000_00000000" & + x"00000000_00000000_000050FF_00000000" & + x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF"; COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; @@ -102,6 +107,7 @@ package trb_net16_hub_func is HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; CLOCK_FREQUENCY : integer range 1 to 200 := 100; USE_ONEWIRE : integer range 0 to 2 := c_YES; + BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF"; --media interfaces MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 12; MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH; @@ -201,6 +207,7 @@ component trb_net16_hub_streaming_port is BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"7E"; CLOCK_FREQUENCY : integer range 1 to 200 := 100; USE_ONEWIRE : integer range 0 to 2 := c_YES; + BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF"; --media interfaces MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 12; MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH; diff --git a/trb_net16_hub_streaming_port.vhd b/trb_net16_hub_streaming_port.vhd index cafe0c5..29b43a8 100644 --- a/trb_net16_hub_streaming_port.vhd +++ b/trb_net16_hub_streaming_port.vhd @@ -28,6 +28,7 @@ entity trb_net16_hub_streaming_port is BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"7E"; CLOCK_FREQUENCY : integer range 1 to 200 := 100; USE_ONEWIRE : integer range 0 to 2 := c_YES; + BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF"; --media interfaces MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 12; MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH; @@ -232,6 +233,7 @@ begin HUB_CTRL_BROADCAST_BITMASK => BROADCAST_BITMASK, CLOCK_FREQUENCY => CLOCK_FREQUENCY, USE_ONEWIRE => USE_ONEWIRE, + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, MII_NUMBER => mii, MII_IBUF_DEPTH => MII_IBUF_DEPTH, MII_IS_UPLINK => MII_IS_UPLINK, diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd index 6edea80..f887c46 100644 --- a/trb_net16_regIO.vhd +++ b/trb_net16_regIO.vhd @@ -807,9 +807,7 @@ begin process(CLK) begin if rising_edge(CLK) then - if RESET = '1' then - buf_DAT_DATA_IN <= (others => '0'); - elsif DAT_DATAREADY_IN = '1' then + if DAT_DATAREADY_IN = '1' then buf_DAT_DATA_IN <= DAT_DATA_IN; end if; end if; diff --git a/trb_net_components.vhd b/trb_net_components.vhd index c7d92e1..6d4607a 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -139,7 +139,8 @@ end component trb_net16_med_scm_sfp_gbe; SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES; APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_NO; ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; - BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF" + BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; + BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF" ); port( @@ -343,6 +344,7 @@ end component trb_net16_med_scm_sfp_gbe; APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO); ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; + BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF"; TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES; REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers @@ -474,6 +476,7 @@ end component trb_net16_med_scm_sfp_gbe; APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO); ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; + BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF"; REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers REGIO_INIT_CTRL_REGS : std_logic_vector(16*32-1 downto 0) := (others => '0'); @@ -1590,7 +1593,7 @@ end component; CLK_25 : in std_logic; CLK_EN : in std_logic; RESET : in std_logic; - + CLEAR : in std_logic; --Internal Connection MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH*4-1 downto 0); MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH*4-1 downto 0); @@ -2345,6 +2348,7 @@ end component; MAKE_TRBNET_RESET_OUT : out std_logic; -- Status signals PACKET_TIMEOUT_OUT : out std_logic; + ENABLE_CORRECTION_IN : in std_logic; -- Debugging DEBUG_OUT : out std_logic_vector(31 downto 0) ); -- 2.43.0