From 34f41e7833a9e9316ffef24e631eb20436ac0073 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Thu, 12 Mar 2009 19:58:57 +0000 Subject: [PATCH] *** empty log message *** --- optical_link/flexi_PCS_channel_synch.vhd | 3 --- optical_link/flexi_PCS_synch.vhd | 3 --- optical_link/hub.vhd | 6 ++--- optical_link/hub_tb.vhd | 19 ++++++++-------- optical_link/simpleupcounter_16bit.vhd | 5 +---- optical_link/simpleupcounter_32bit.vhd | 5 +---- optical_link/simpleupcounter_8bit.vhd | 5 +---- optical_link/trb_hub_interface.vhd | 28 ++++++++++-------------- 8 files changed, 26 insertions(+), 48 deletions(-) diff --git a/optical_link/flexi_PCS_channel_synch.vhd b/optical_link/flexi_PCS_channel_synch.vhd index 60312dd..075520e 100644 --- a/optical_link/flexi_PCS_channel_synch.vhd +++ b/optical_link/flexi_PCS_channel_synch.vhd @@ -1,8 +1,5 @@ library IEEE; use IEEE.STD_LOGIC_UNSIGNED.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.all; -library ieee; library work; use ieee.std_logic_1164.all; use ieee.numeric_std.all; diff --git a/optical_link/flexi_PCS_synch.vhd b/optical_link/flexi_PCS_synch.vhd index a0ac212..cc29378 100644 --- a/optical_link/flexi_PCS_synch.vhd +++ b/optical_link/flexi_PCS_synch.vhd @@ -1,8 +1,5 @@ library IEEE; use IEEE.STD_LOGIC_UNSIGNED.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.all; -library ieee; library work; use ieee.std_logic_1164.all; use ieee.numeric_std.all; diff --git a/optical_link/hub.vhd b/optical_link/hub.vhd index d10832c..7287a5f 100644 --- a/optical_link/hub.vhd +++ b/optical_link/hub.vhd @@ -1,11 +1,9 @@ library IEEE; use IEEE.STD_LOGIC_UNSIGNED.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.all; -library ieee; -library work; use ieee.std_logic_1164.all; use ieee.numeric_std.all; + +library work; use work.all; use work.trb_net_std.all; use work.trb_net16_hub_func.all; diff --git a/optical_link/hub_tb.vhd b/optical_link/hub_tb.vhd index 1b35d87..3933fdd 100644 --- a/optical_link/hub_tb.vhd +++ b/optical_link/hub_tb.vhd @@ -1,7 +1,6 @@ library IEEE; use IEEE.STD_LOGIC_UNSIGNED.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.all; + library ieee; library work; use ieee.std_logic_1164.all; @@ -33,7 +32,7 @@ entity hub_tb is end hub_tb; architecture hub_tb of hub_tb is - + signal LVDS_CLK_200P_i : std_logic; signal LVDS_CLK_200N_i : std_logic; signal SERDES_200N_i : std_logic; @@ -81,7 +80,7 @@ component hub OPT_DATA_OUT : out std_logic_vector(16*HOW_MANY_CHANNELS-1 downto 0); OPT_DATA_VALID_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); OPT_DATA_VALID_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0) - + ); end component; @@ -105,12 +104,12 @@ begin -- of hub_tb SFP_INP_P => SFP_INP_P_i, SFP_OUT_N => SFP_OUT_N_i, SFP_OUT_P => SFP_OUT_P_i - FS_PE_11 => - OPT_DATA_IN => - OPT_DATA_OUT => - OPT_DATA_VALID_IN => - OPT_DATA_VALID_OUT => - + FS_PE_11 => + OPT_DATA_IN => + OPT_DATA_OUT => + OPT_DATA_VALID_IN => + OPT_DATA_VALID_OUT => + clock_gclk : process begin SERDES_200P_i <= '0'; diff --git a/optical_link/simpleupcounter_16bit.vhd b/optical_link/simpleupcounter_16bit.vhd index 4dd2e34..16e14af 100644 --- a/optical_link/simpleupcounter_16bit.vhd +++ b/optical_link/simpleupcounter_16bit.vhd @@ -3,10 +3,7 @@ use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --- Uncomment the following lines to use the declarations that are --- provided for instantiating Xilinx primitive components. ---library UNISIM; ---use UNISIM.VComponents.all; + entity simpleupcounter_16bit is Port ( QOUT : out std_logic_vector(15 downto 0); diff --git a/optical_link/simpleupcounter_32bit.vhd b/optical_link/simpleupcounter_32bit.vhd index 4bc7f93..7bf16a9 100644 --- a/optical_link/simpleupcounter_32bit.vhd +++ b/optical_link/simpleupcounter_32bit.vhd @@ -3,10 +3,7 @@ use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --- Uncomment the following lines to use the declarations that are --- provided for instantiating Xilinx primitive components. ---library UNISIM; ---use UNISIM.VComponents.all; + entity simpleupcounter_32bit is Port ( QOUT : out std_logic_vector(31 downto 0); diff --git a/optical_link/simpleupcounter_8bit.vhd b/optical_link/simpleupcounter_8bit.vhd index aa07751..e5fa035 100644 --- a/optical_link/simpleupcounter_8bit.vhd +++ b/optical_link/simpleupcounter_8bit.vhd @@ -3,10 +3,7 @@ use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --- Uncomment the following lines to use the declarations that are --- provided for instantiating Xilinx primitive components. ---library UNISIM; ---use UNISIM.VComponents.all; + entity simpleupcounter_8bit is Port ( QOUT : out std_logic_vector(7 downto 0); diff --git a/optical_link/trb_hub_interface.vhd b/optical_link/trb_hub_interface.vhd index 7f1d1b7..b340ad5 100644 --- a/optical_link/trb_hub_interface.vhd +++ b/optical_link/trb_hub_interface.vhd @@ -5,11 +5,7 @@ use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; --use work.support.all; -library UNISIM; -use UNISIM.VCOMPONENTS.all; -library UNISIM; -use UNISIM.VComponents.all; entity trb_hub_interface is port ( @@ -19,7 +15,7 @@ entity trb_hub_interface is INTERNAL_DATA_IN : in std_logic_vector(7 downto 0); INTERNAL_DATA_OUT : out std_logic_vector(7 downto 0); INTERNAL_ADDRESS : in std_logic_vector(15 downto 0); - INTERNAL_MODE : in std_logic; + INTERNAL_MODE : in std_logic; VALID_DATA_SENT : out std_logic; HUB_REGISTER_00 : in std_logic_vector(7 downto 0); HUB_REGISTER_01 : in std_logic_vector(7 downto 0); @@ -112,7 +108,7 @@ begin when x"0004" => saved_data_out <= HUB_REGISTER_04; when x"0005" => saved_data_out <= HUB_REGISTER_05; when x"0006" => saved_data_out <= HUB_REGISTER_06; - when x"0007" => saved_data_out <= HUB_REGISTER_07; + when x"0007" => saved_data_out <= HUB_REGISTER_07; when x"0008" => saved_data_out <= HUB_REGISTER_08; when x"0009" => saved_data_out <= HUB_REGISTER_09; when x"000a" => saved_data_out <= hub_register_0a_i; @@ -127,8 +123,8 @@ begin when x"0013" => saved_data_out <= HUB_REGISTER_13; when x"0014" => saved_data_out <= HUB_REGISTER_14; when x"0015" => saved_data_out <= HUB_REGISTER_15; - when x"0016" => saved_data_out <= HUB_REGISTER_16; - + when x"0016" => saved_data_out <= HUB_REGISTER_16; + when others => saved_data_out <= x"ff"; end case; elsif saved_mod = '0' then @@ -138,7 +134,7 @@ begin when x"000c" => hub_register_0c_i <= saved_data_in; when x"000d" => hub_register_0d_i <= saved_data_in; when x"000e" => hub_register_0e_i <= saved_data_in; - when x"000f" => hub_register_0f_i <= saved_data_in; + when x"000f" => hub_register_0f_i <= saved_data_in; when others => null; end case; end if; @@ -154,17 +150,17 @@ begin INTERNAL_DATA_OUT <= saved_data_out; data_ready <= '1'; VALID_CLOCKED : process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then + begin + if rising_edge(CLK) then + if RESET = '1' then VALID_current <= IDLE; - else + else VALID_current <= VALID_next; end if; end if; end process VALID_CLOCKED; SEND_VALID_FSM: process (VALID_current,data_ready,strobe_pulse) - begin + begin case (VALID_current) is when IDLE => VALID_DATA_SENT <= '0'; @@ -192,7 +188,7 @@ begin when VALID_5 => VALID_DATA_SENT <= '1'; VALID_next <= IDLE; - end case; + end case; end process SEND_VALID_FSM; - + end trb_hub_interface; -- 2.43.0