From 353fd001d1ed1e5004edd410255b5a8da7c56565 Mon Sep 17 00:00:00 2001 From: Andreas Neiser Date: Tue, 24 Feb 2015 10:40:45 +0100 Subject: [PATCH] relax clock constraints for slowcontrol stuff --- ADC/trb3_periph_adc_constraints.lpf | 3 +++ 1 file changed, 3 insertions(+) diff --git a/ADC/trb3_periph_adc_constraints.lpf b/ADC/trb3_periph_adc_constraints.lpf index 3aec3b1..6eb73dc 100644 --- a/ADC/trb3_periph_adc_constraints.lpf +++ b/ADC/trb3_periph_adc_constraints.lpf @@ -83,3 +83,6 @@ USE PRIMARY NET "CLK_PCLK_RIGHT_c"; #USE PRIMARY2EDGE NET "THE_ADC/clk_adcfast_i_0"; #USE PRIMARY2EDGE NET "THE_ADC/clk_adcfast_i_1"; + +MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "gen_reallogic_THE_ADC/adc_clk_right_c" 2 X; +MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "P_CLOCK_c" 2 X; -- 2.43.0