From 35fd80c0154aad49aaf3802391358165d0708e35 Mon Sep 17 00:00:00 2001 From: hadaq Date: Mon, 17 Oct 2011 21:02:15 +0000 Subject: [PATCH] Version String Local added --- libtrbnet/trbnet.c | 95 +++++++++++++++++++++++----------------------- 1 file changed, 48 insertions(+), 47 deletions(-) diff --git a/libtrbnet/trbnet.c b/libtrbnet/trbnet.c index 8b0e4dd..f35be10 100644 --- a/libtrbnet/trbnet.c +++ b/libtrbnet/trbnet.c @@ -1,4 +1,4 @@ -const char trbnet_version[] = "$Revision: 4.10 $"; +const char trbnet_version[] = "$Revision: 4.11 $ Local"; #include #include @@ -170,7 +170,7 @@ typedef struct { /* ------ Internal Functions for FPGA access ------------------------------ */ -#ifndef PEXOR /* Etrax-Board */ +#ifdef ETRAX /* Etrax-Board */ #define FIFO_TOGGLE_BIT 0x10000 @@ -448,7 +448,7 @@ static int trb_init_transfer(uint8_t channel) } /* Check for TX not Busy */ -#ifndef PEXOR +#ifdef ETRAX read32_from_FPGA(CHANNEL_N_SENDER_STATUS | ((channel * 2 + 1) << 4), &tmp); if (tmp != 0) { /* FIFO_TOGGLE_BIT-BUG Workaround */ @@ -462,7 +462,7 @@ static int trb_init_transfer(uint8_t channel) } /* Check receiver FIFO empty */ -#ifndef PEXOR +#ifdef ETRAX read32_from_FPGA(CHANNEL_N_RECEIVER_FIFO_STATUS | ((channel * 2 + 1) << 4), &tmp); if ((tmp & MASK_FIFO_EMPTY) == 0) { @@ -500,14 +500,15 @@ static int trb_fifo_read(uint8_t channel, unsigned int dsize) { -#ifndef PEXOR +#ifdef ETRAX static uint32_t dataBuffer = 0; uint32_t* tmp = &dataBuffer; uint32_t fifoBuffer = 0; unsigned int timeout = 0; -#else /* Pexor DMA */ +#else /* Pexor DMA */ uint32_t* tmp = dataBuffer; #endif + TRB_Package package = {0,0,0,0,0}; int headerType = 0; @@ -587,7 +588,7 @@ static int trb_fifo_read(uint8_t channel, fprintf(stderr, "FIFO_%03d: 0x%08x\n", fifoDebugCtr, *tmp); } -#ifndef PEXOR +#ifdef ETRAX fifo_flush(channel); #endif trb_errno = TRB_FIFO_INCOMPLETE_PACKAGE; @@ -605,7 +606,7 @@ static int trb_fifo_read(uint8_t channel, if (((*tmp & MASK_FIFO_TYPE) >> SHIFT_FIFO_TYPE) != (counter - 1) % 2) { /* Error: invalid sequence (not 0, 1, .), flush FIFO-BUFFER, exit */ -#ifndef PEXOR +#ifdef ETRAX fifo_flush(channel); #endif trb_errno = TRB_FIFO_SEQUENZ; @@ -656,13 +657,13 @@ static int trb_fifo_read(uint8_t channel, /* First package: headerType must be HDR or TRM */ if (packageCtr == 0) { if (!((headerType == HEADER_HDR) || (headerType == HEADER_TRM))) { -#ifndef PEXOR +#ifdef ETRAX fifo_flush(channel); #endif trb_errno = TRB_FIFO_INVALID_HEADER; return -1; } -#ifndef PEXOR +#ifdef ETRAX /* Check Header H0 */ if (((package.H0 & MASK_HEADER_REPLY) >> SHIFT_HEADER_REPLY != 0x01) || @@ -670,7 +671,7 @@ static int trb_fifo_read(uint8_t channel, != channel)) { /* Error Package inconsistencies, flush FIFO-BUFFER and exit */ -#ifndef PEXOR +#ifdef ETRAX fifo_flush(channel); #endif trb_errno = TRB_FIFO_HEADERS; @@ -684,14 +685,14 @@ static int trb_fifo_read(uint8_t channel, switch (mode) { case FIFO_MODE_TERM_ONLY: if (packageCtr > 0) { -#ifndef PEXOR +#ifdef ETRAX fifo_flush(channel); #endif trb_errno = TRB_INVALID_PKG_NUMBER; return -1; } if (headerType != HEADER_TRM) { -#ifndef PEXOR +#ifdef ETRAX fifo_flush(channel); #endif trb_errno = TRB_FIFO_INVALID_HEADER; @@ -703,7 +704,7 @@ static int trb_fifo_read(uint8_t channel, switch (headerType) { case HEADER_HDR: if ((packageCtr - endPointCtr * 2) != 0) { -#ifndef PEXOR +#ifdef ETRAX fifo_flush(channel); #endif trb_errno = TRB_FIFO_INVALID_HEADER; @@ -721,7 +722,7 @@ static int trb_fifo_read(uint8_t channel, case HEADER_DAT: if ((packageCtr - endPointCtr * 2) != 1) { -#ifndef PEXOR +#ifdef ETRAX fifo_flush(channel); #endif trb_errno = TRB_FIFO_INVALID_HEADER; @@ -743,7 +744,7 @@ static int trb_fifo_read(uint8_t channel, break; default: -#ifndef PEXOR +#ifdef ETRAX fifo_flush(channel); #endif trb_errno = TRB_FIFO_INVALID_HEADER; @@ -756,7 +757,7 @@ static int trb_fifo_read(uint8_t channel, switch (headerType) { case HEADER_HDR: if ((packageCtr - endPointCtr * 2) != 0) { -#ifndef PEXOR +#ifdef ETRAX fifo_flush(channel); #endif trb_errno = TRB_FIFO_INVALID_HEADER; @@ -774,7 +775,7 @@ static int trb_fifo_read(uint8_t channel, case HEADER_DAT: if ((packageCtr - endPointCtr * 2) != 1) { -#ifndef PEXOR +#ifdef ETRAX fifo_flush(channel); #endif trb_errno = TRB_FIFO_INVALID_HEADER; @@ -799,7 +800,7 @@ static int trb_fifo_read(uint8_t channel, break; default: -#ifndef PEXOR +#ifdef ETRAX fifo_flush(channel); #endif trb_errno = TRB_FIFO_INVALID_HEADER; @@ -848,7 +849,7 @@ static int trb_fifo_read(uint8_t channel, break; default: -#ifndef PEXOR +#ifdef ETRAX fifo_flush(channel); #endif trb_errno = TRB_FIFO_INVALID_HEADER; @@ -898,7 +899,7 @@ static int trb_fifo_read(uint8_t channel, break; default: -#ifndef PEXOR +#ifdef ETRAX fifo_flush(channel); #endif trb_errno = TRB_FIFO_INVALID_HEADER; @@ -914,7 +915,7 @@ static int trb_fifo_read(uint8_t channel, break; default: -#ifndef PEXOR +#ifdef ETRAX fifo_flush(channel); #endif trb_errno = TRB_FIFO_INVALID_HEADER; @@ -929,7 +930,7 @@ static int trb_fifo_read(uint8_t channel, switch (headerType) { case HEADER_HDR: if (packageCtr != 0) { -#ifndef PEXOR +#ifdef ETRAX fifo_flush(channel); #endif trb_errno = TRB_FIFO_INVALID_HEADER; @@ -958,7 +959,7 @@ static int trb_fifo_read(uint8_t channel, case HEADER_TRM: if ((packageCtr > 0) && (dataCtr != memLen)) { /* Error invalid length */ -#ifndef PEXOR +#ifdef ETRAX fifo_flush(channel); #endif trb_errno = TRB_HDR_DLEN; @@ -967,7 +968,7 @@ static int trb_fifo_read(uint8_t channel, break; default: -#ifndef PEXOR +#ifdef ETRAX fifo_flush(channel); #endif trb_errno = TRB_FIFO_INVALID_HEADER; @@ -985,7 +986,7 @@ static int trb_fifo_read(uint8_t channel, switch (headerType) { case HEADER_HDR: if ((packageCtr - endPointCtr * 3) != 0) { -#ifndef PEXOR +#ifdef ETRAX fifo_flush(channel); #endif trb_errno = TRB_FIFO_INVALID_HEADER; @@ -1027,7 +1028,7 @@ static int trb_fifo_read(uint8_t channel, break; default: -#ifndef PEXOR +#ifdef ETRAX fifo_flush(channel); #endif trb_errno = TRB_FIFO_INVALID_HEADER; @@ -1038,7 +1039,7 @@ static int trb_fifo_read(uint8_t channel, case FIFO_MODE_SET_ADDRESS: if (packageCtr > 2) { -#ifndef PEXOR +#ifdef ETRAX fifo_flush(channel); #endif trb_errno = TRB_INVALID_PKG_NUMBER; @@ -1059,7 +1060,7 @@ static int trb_fifo_read(uint8_t channel, break; default: -#ifndef PEXOR +#ifdef ETRAX fifo_flush(channel); #endif trb_errno = TRB_FIFO_INVALID_HEADER; @@ -1068,7 +1069,7 @@ static int trb_fifo_read(uint8_t channel, break; default: -#ifndef PEXOR +#ifdef ETRAX fifo_flush(channel); #endif trb_errno = TRB_FIFO_INVALID_MODE; @@ -1175,7 +1176,7 @@ static int lockPorts(int masterLock) sigprocmask(SIG_SETMASK, &blockSetOld, NULL); return -1; } -#ifndef PEXOR +#ifdef ETRAX /* Get FifoToggleBit-Status, needed by read32_from_FPGA ... */ fifoToggleBit = readPC() & FIFO_TOGGLE_BIT; #endif @@ -1255,7 +1256,7 @@ static int init_semaphore() /* ----- Global Functions ----------------------------------------------- */ -#ifndef PEXOR /* Etrax-Board */ +#ifdef ETRAX /* Etrax-Board */ /* Init FPGA Interface */ int init_ports() @@ -1412,7 +1413,7 @@ int trb_register_read(uint16_t trb_address, fprintf(stderr, "Init_Transfer done.\n"); } -#ifndef PEXOR +#ifdef ETRAX /* Build package and start transfer */ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address); write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000); @@ -1478,7 +1479,7 @@ int trb_registertime_read(uint16_t trb_address, fprintf(stderr, "Init_Transfer done.\n"); } -#ifndef PEXOR +#ifdef ETRAX /* Build package and start transfer */ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address); write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000); @@ -1556,7 +1557,7 @@ int trb_register_read_mem(uint16_t trb_address, fprintf(stderr, "Init_Transfer done.\n"); } -#ifndef PEXOR +#ifdef ETRAX /* Build package and start transfer */ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address); write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000); @@ -1644,7 +1645,7 @@ int trb_registertime_read_mem(uint16_t trb_address, fprintf(stderr, "Init_Transfer done.\n"); } -#ifndef PEXOR +#ifdef ETRAX /* Build package and start transfer */ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address); write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000); @@ -1721,7 +1722,7 @@ int trb_register_write(uint16_t trb_address, fprintf(stderr, "Init_Transfer done.\n"); } -#ifndef PEXOR +#ifdef ETRAX /* Build package */ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address); write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000); @@ -1770,7 +1771,7 @@ int trb_register_write_mem(uint16_t trb_address, uint16_t config; uint16_t ctr = 0; int status = -1; -#ifndef PEXOR +#ifdef ETRAX uint16_t i; #endif @@ -1799,7 +1800,7 @@ int trb_register_write_mem(uint16_t trb_address, fprintf(stderr, "Init_Transfer done.\n"); } -#ifndef PEXOR +#ifdef ETRAX /* Build package */ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address); write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000); @@ -1885,7 +1886,7 @@ int trb_read_uid(uint16_t trb_address, fprintf(stderr, "Init_Transfer done.\n"); } -#ifndef PEXOR +#ifdef ETRAX /* Build package and start transfer */ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address); write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000); @@ -1954,7 +1955,7 @@ int trb_set_address(uint64_t uid, fprintf(stderr, "Init_Transfer done.\n"); } -#ifndef PEXOR +#ifdef ETRAX /* Build package and start transfer */ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, 0xffff); /* always broadcast */ write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000); @@ -2030,7 +2031,7 @@ int trb_ipu_data_read(uint8_t type, fprintf(stderr, "Init_Transfer done.\n"); } -#ifndef PEXOR +#ifdef ETRAX /* Prepare IPU channel */ write32_to_FPGA(CHANNEL_1_SENDER_ERROR, (((uint32_t)trg_info << 24) | ((uint32_t)trg_random << 16) | @@ -2094,7 +2095,7 @@ int trb_send_trigger(uint8_t type, fprintf(stderr, "Init_Transfer done.\n"); } -#ifndef PEXOR +#ifdef ETRAX /* Prepare trigger channel */ write32_to_FPGA(CHANNEL_0_SENDER_ERROR, (((trg_info & 0xff) << 24) | ((uint32_t)trg_random << 16) | @@ -2175,7 +2176,7 @@ int trb_send_trigger_rich(uint8_t trg_input, fprintf(stderr, "Init_Transfer done.\n"); } -#ifndef PEXOR +#ifdef ETRAX /* Prepare slowcontrol channel */ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, 0x0000fffb); /* RICH Subnet only */ write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000); @@ -2209,7 +2210,7 @@ int trb_send_trigger_rich(uint8_t trg_input, return -1; } -#ifndef PEXOR +#ifdef ETRAX /* Prepare trigger channel */ write32_to_FPGA(CHANNEL_0_SENDER_ERROR, (((trg_info & 0xff) << 24) | ((uint32_t)trg_random << 16) | @@ -2262,7 +2263,7 @@ int fpga_register_read(uint32_t reg_address, uint32_t* value) int status = 0; trb_errno = TRB_NONE; -#ifndef PEXOR +#ifdef ETRAX reg_address &= 0xffff; #endif @@ -2285,7 +2286,7 @@ int fpga_register_write(uint32_t reg_address, uint32_t value) int status = 0; trb_errno = TRB_NONE; -#ifndef PEXOR +#ifdef ETRAX reg_address &= 0xffff; #endif -- 2.43.0