From 363f839785cf935f3a0caa7ed62464080230ace5 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 21 Jul 2009 08:33:50 +0000 Subject: [PATCH] *** empty log message *** --- design/tdc_readout_and_trb_interface.vhd | 193 ++++++++++------------- 1 file changed, 85 insertions(+), 108 deletions(-) diff --git a/design/tdc_readout_and_trb_interface.vhd b/design/tdc_readout_and_trb_interface.vhd index 4fecbc1..1d086ba 100644 --- a/design/tdc_readout_and_trb_interface.vhd +++ b/design/tdc_readout_and_trb_interface.vhd @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------- -- Attilio Tarantola --- Create Date: 18/08/2007 +-- Create Date: 18/08/2007 -- Description: it it the top level design of: --1) fifo_0 --2) tdc_readout: it builds the dataword @@ -25,7 +25,7 @@ use ecp2m.components.all; entity tdc_readout_and_trb_interface is -- generic (width : integer := 16; -- bus_number: std_logic_vector(3 downto 0)); - port ( + port ( CLK : in std_logic; RESET : in std_logic; @@ -35,7 +35,7 @@ entity tdc_readout_and_trb_interface is A_ADD : in std_logic_vector(8 downto 0); A_RESERV : in std_logic; --this is 11 bit of dataword A_AOD : in std_logic; --address or data - A_ACK : in std_logic; + A_ACK : in std_logic; A_DST : in std_logic; A_DRE : out std_logic; TOKEN_IN : in std_logic_vector(3 downto 0); @@ -43,7 +43,7 @@ entity tdc_readout_and_trb_interface is ------------------------------------------------------------------------------- -- tdc_readout_and_trb_interface -------------------------------------------------------------------------------- +------------------------------------------------------------------------------- DATA_TYPE_SELECT_IN : in std_logic_vector(19 downto 0); TOKEN_TO_TRB_OUT : out std_logic; REINIT_ROC1_IN : in std_logic; @@ -53,7 +53,7 @@ entity tdc_readout_and_trb_interface is DEBUG_REGISTER_0 : out std_logic_vector(7 downto 0); DEBUG_REGISTER_1 : out std_logic_vector(7 downto 0); DEBUG_REGISTER_2 : out std_logic_vector(7 downto 0); - + ------------------------------------------------------------------------------- -- trbnet interface ------------------------------------------------------------------------------- @@ -64,7 +64,7 @@ entity tdc_readout_and_trb_interface is LVL1_TRG_INFORMATION_IN : in std_logic_vector(7 downto 0); LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0) := x"00000000"; LVL1_TRG_RELEASE_OUT : out std_logic := '0'; - + --Data Port IPU_NUMBER_IN : in std_logic_vector (15 downto 0); IPU_INFORMATION_IN : in std_logic_vector (7 downto 0); @@ -86,20 +86,20 @@ architecture behavioral of tdc_readout_and_trb_interface is ---------------------------------------------------------------------- -- FSM_HEADER ---------------------------------------------------------------------- - + type state_type is (idle_state, wait_for_token, send_second_header_state, send_data_state, send_data_1_state,busy_header_state); - + signal current_state, next_state : state_type; - + ---------------------------------------------------------------------- -- FSM_FIFO_MULTIPLEXER ---------------------------------------------------------------------- type state_type_fsm_multiplexer is (idle_state_fsm_multiplexer, wait_for_complete_event_fsm_multiplexer, send_first_and_second_header_state_fsm_multiplexer, - + send_data_state_fsm_multiplexer, end_of_event_transfer_fsm_multiplexer, dummy_wait_1_fsm_multiplexer, @@ -107,9 +107,9 @@ architecture behavioral of tdc_readout_and_trb_interface is dummy_wait_4_fsm_multiplexer ); signal current_state_fsm_multiplexer, next_state_fsm_multiplexer : state_type_fsm_multiplexer; - + signal reg_fifo_data_in_i, next_fifo_data_in_i, fifo_data_in_i : std_logic_vector(31 downto 0); - signal reg_fifo_data_out_i, fifo_data_out_i : std_logic_vector(31 downto 0); + signal reg_fifo_data_out_i, fifo_data_out_i : std_logic_vector(31 downto 0); signal reg_fifo_write_enable_i, next_fifo_write_enable_i : std_logic; signal reg_lvl1_busy_i, next_lvl1_busy_i : std_logic; signal init_tdc_readout_i : std_logic_vector(3 downto 0); @@ -134,7 +134,7 @@ architecture behavioral of tdc_readout_and_trb_interface is signal pulse_init_tdc_readout : std_logic; signal next_debug_register_fsm_multiplexer : std_logic_vector(7 downto 0); - signal reg_debug_register_fsm_multiplexer : std_logic_vector(7 downto 0); + signal reg_debug_register_fsm_multiplexer : std_logic_vector(7 downto 0); signal fee_data_fifo_out_i : std_logic_vector(35 downto 0); signal header_data_fifo_out_i : std_logic_vector(51 downto 0); signal next_data_to_trb_net : std_logic_vector(31 downto 0); @@ -144,7 +144,7 @@ architecture behavioral of tdc_readout_and_trb_interface is signal reg_read_fee_data_fifo_i,next_read_fee_data_fifo_i, next_read_header_fifo_i, reg_read_header_fifo_i : std_logic; signal word_count_fee_data_fifo : std_logic_vector(13 downto 0); - signal word_count_header_fifo : std_logic_vector(9 downto 0); + signal word_count_header_fifo : std_logic_vector(9 downto 0); signal reg_lvl1_trg_received, pulse_ipu_start_readout, reg_ipu_read : std_logic; signal reg_lvl1_trg_type : std_logic_vector(3 downto 0); @@ -154,14 +154,14 @@ architecture behavioral of tdc_readout_and_trb_interface is signal reg_lvl1_error_pattern, next_lvl1_error_pattern : std_logic_vector (31 downto 0); -- signal reg_ipu_error_pattern, next_ipu_error_pattern : std_logic_vector (31 downto 0); - + signal reg_lvl1_trg_release, next_lvl1_trg_release : std_logic; signal reg_ipu_data, next_ipu_data : std_logic_vector (31 downto 0); signal reg_ipu_data_ready, next_ipu_data_ready : std_logic; signal reg_ipu_finished, next_ipu_finished : std_logic; signal how_many_complete_event_in_fifo_counter : std_logic_vector (31 downto 0); signal pulse_reg_lvl1_trg_received : std_logic; - signal reg_lvl1_trg_number : std_logic_vector(15 downto 0); + signal reg_lvl1_trg_number : std_logic_vector(15 downto 0); signal read_header_fifo,read_fee_data_fifo : std_logic; signal counter_word_read_from_trbnet : std_logic_vector(3 downto 0); signal clear_counter_word_read_from_trbnet : std_logic; @@ -169,9 +169,7 @@ architecture behavioral of tdc_readout_and_trb_interface is signal push_read_fee_data_i,push_read_header_data_i : std_logic; signal empty_flag_fee_data_fifo_i, empty_flag_header_data_fifo_i : std_logic; signal reg_empty_flag_fee_data_fifo_i : std_logic; - signal reg_empty_flag_header_data_fifo_i : std_logic; - signal reg_reg_empty_flag_header_data_fifo_i : std_logic; - signal reg_reg_reg_empty_flag_header_data_fifo_i : std_logic; + signal reg_reg_empty_flag_fee_data_fifo_i : std_logic; signal last_empty_flag_fee_data_fifo_i : std_logic; signal pulse_write_header_fifo_i, pulse_write_fee_data_fifo_i : std_logic; signal counter_pulse_write_header_fifo_i, counter_pulse_write_fee_data_fifo_i : std_logic_vector(15 downto 0); @@ -276,8 +274,8 @@ begin -- behavioral A_ADO_PULSE: edge_to_pulse port map ( - CLOCK => CLK, - ENABLE_CLK_IN =>'1', + CLOCK => CLK, + ENABLE_CLK_IN =>'1', SIGNAL_IN => A_AOD, PULSE_OUT => pulse_a_aod_i); @@ -316,7 +314,7 @@ begin -- behavioral SIGNAL_IN => write_fee_data_fifo_i, PULSE_OUT => pulse_write_fee_data_fifo_i); - + TDC_READOUT_INTERFACE : tdc_readout port map ( CLK => CLK, @@ -337,14 +335,14 @@ TDC_READOUT_INTERFACE : tdc_readout --generator after send --token FULL_FIFO_IN => '0', - DATA_TYPE_SELECT_IN => DATA_TYPE_SELECT_IN, + DATA_TYPE_SELECT_IN => DATA_TYPE_SELECT_IN, DEBUG_REGISTER_OUT => debug_register_tdc_readout_i); ------------------------------------------------------------------------------- -- OENP point test token back ------------------------------------------------------------------------------- --data transmission to trbnet terminated - TOKEN_TO_TRB_OUT <= reg_pseudo_token; + TOKEN_TO_TRB_OUT <= reg_pseudo_token; FEE_DATA_FIFO : fifo_8192depth_36width_dual_thresh_reg_out port map ( @@ -353,7 +351,7 @@ TDC_READOUT_INTERFACE : tdc_readout WrEn => write_fee_data_fifo_i, RdEn => read_fee_data_fifo, Reset => RESET, - AmEmptySetThresh => "0000000000000", + AmEmptySetThresh => "0000000000000", AmEmptyClrThresh => "0000000000000", Q => fee_data_fifo_out_i, WCNT => word_count_fee_data_fifo, @@ -389,7 +387,7 @@ TDC_READOUT_INTERFACE : tdc_readout end process; read_fee_data_fifo <= (IPU_READ_IN and reg_read_fee_data_fifo_i) or - pulse_not_empty_flag_fee_data_fifo_i; + pulse_not_empty_flag_fee_data_fifo_i; HEADER_FIFO: fifo_fall_through_512depth_52width_reg_out port map ( @@ -410,7 +408,7 @@ HEADER_FIFO: fifo_fall_through_512depth_52width_reg_out ------------------------------------------------------------------------------- -- reg_ipu_read is setted by TRBNET, -- reg_read_header_fifo_i is defined by the state machine -------------------------------------------------------------------------------- +------------------------------------------------------------------------------- read_header_fifo <= (IPU_READ_IN and reg_read_header_fifo_i) or push_read_header_data_i or pulse_not_empty_flag_header_data_fifo_i; @@ -418,12 +416,9 @@ read_header_fifo <= (IPU_READ_IN and reg_read_header_fifo_i) or ------------------------------------------------------------------------------- not_empty_flag_header_data_fifo_i <= not empty_flag_header_data_fifo_i; - process(CLK) + process(CLK, counter_pulse_not_empty_header) begin if rising_edge(CLK) then - reg_empty_flag_header_data_fifo_i <= empty_flag_header_data_fifo_i; - reg_reg_empty_flag_header_data_fifo_i <= reg_empty_flag_header_data_fifo_i; - reg_reg_reg_empty_flag_header_data_fifo_i <= reg_reg_empty_flag_header_data_fifo_i; if (counter_pulse_not_empty_header = x"0001") then pulse_not_empty_flag_header_data_fifo_i <= '0'; else @@ -447,36 +442,37 @@ end process; ------------------------------------------------------------------------------- -- I WANT THE FIRST DATAWORD TO APPEAR AT FIFO HEADER -- OUTPUT -------------------------------------------------------------------------------- +------------------------------------------------------------------------------- process (CLK, RESET, pulse_write_header_fifo_i,counter_pulse_write_header_fifo_i) begin if rising_edge(CLK) then - if (RESET = '1') then + if (RESET = '1') then push_read_header_data_i <= '0'; elsif (pulse_write_header_fifo_i = '1' and counter_pulse_write_header_fifo_i = X"0000") then push_read_header_data_i <= '1'; else - push_read_header_data_i <= '0'; + push_read_header_data_i <= '0'; end if; end if; end process; ----------------------------------------------------------------------------- -- register empty flag for fee data ------------------------------------------------------------------------------ +----------------------------------------------------------------------------- process (CLK, RESET) begin if rising_edge(CLK) then last_empty_flag_fee_data_fifo_i <= empty_flag_fee_data_fifo_i; reg_empty_flag_fee_data_fifo_i <= last_empty_flag_fee_data_fifo_i; + reg_reg_empty_flag_fee_data_fifo_i <= reg_empty_flag_fee_data_fifo_i; end if; end process; - + process (CLK, pulse_write_header_fifo_i) begin if rising_edge(CLK) then - if (RESET = '1') then + if (RESET = '1') then counter_pulse_write_header_fifo_i <= (others => '0'); elsif (pulse_write_header_fifo_i = '1') then counter_pulse_write_header_fifo_i <= counter_pulse_write_header_fifo_i + 1; @@ -486,20 +482,20 @@ end process; end if; end if; end process; - + ------------------------------------------------------------------------------- -- I WANT THE FIRST DATAWORD TO APPEAR AT FIFO DATA -- OUTPUT. this is important when I gather the first event -------------------------------------------------------------------------------- +------------------------------------------------------------------------------- process (CLK, RESET, pulse_write_fee_data_fifo_i, empty_flag_fee_data_fifo_i) begin if rising_edge(CLK) then - if (RESET = '1') then + if (RESET = '1') then push_read_fee_data_i <= '0'; elsif (counter_pulse_write_fee_data_fifo_i >= x"0001") then push_read_fee_data_i <= '0'; elsif (pulse_write_fee_data_fifo_i = '1' and counter_pulse_write_fee_data_fifo_i = X"0000") then - push_read_fee_data_i <= '1'; + push_read_fee_data_i <= '1'; else push_read_fee_data_i <= push_read_fee_data_i; end if; @@ -509,7 +505,7 @@ end process; process (CLK, pulse_write_fee_data_fifo_i) begin if rising_edge(CLK) then - if (RESET = '1') then + if (RESET = '1') then counter_pulse_write_fee_data_fifo_i <= (others => '0'); elsif (pulse_write_fee_data_fifo_i = '1') then counter_pulse_write_fee_data_fifo_i <= counter_pulse_write_fee_data_fifo_i + 1; @@ -527,13 +523,13 @@ end process; -- OUTPUT CONNECTIONS ------------------------------------------------------------------------------- LVL1_ERROR_PATTERN_OUT <= x"00000000"; - LVL1_TRG_RELEASE_OUT <= reg_empty_flag_fee_data_fifo_i and (not next_lvl1_busy_i); + LVL1_TRG_RELEASE_OUT <= reg_empty_flag_fee_data_fifo_i and (not next_lvl1_busy_i); IPU_DATA_OUT <= next_data_to_trb_net(31 downto 0); IPU_DATAREADY_OUT <= (fee_data_fifo_data_valid and next_ipu_data_ready) when (current_state_fsm_multiplexer=send_data_state_fsm_multiplexer) else reg_ipu_data_ready; - + IPU_READOUT_FINISHED_OUT <= reg_ipu_finished; IPU_LENGTH_OUT <= reg_first_header(51 downto 36); @@ -588,7 +584,7 @@ end process; process (CLK, RESET,token_tdc_readout_i, reg_pseudo_token) begin if rising_edge(CLK) then - if (RESET = '1' or reg_pseudo_token ='1') then + if (RESET = '1' or reg_pseudo_token ='1') then counter_token_back <= (others => '0'); elsif (token_tdc_readout_i(0) = '1') then counter_token_back <= counter_token_back + 1; @@ -597,10 +593,10 @@ end process; end if; end if; end process; - + -- process init_signals process (CLK) - begin + begin if rising_edge(CLK) then if RESET = '1' then current_state <= idle_state; @@ -624,12 +620,12 @@ end process; process(current_state, reg_lvl1_trg_received, token_tdc_readout_i, pulse_init_tdc_readout, INIT_TDC_READOUT_IN, almost_empty_flag_fee_data_fifo_i) begin - + next_write_header_fifo_i <= '0'; next_debug_register_fsm_header <= (others => '0'); next_lvl1_busy_i <= '0'; data_header_fifo_in_i <= reg_first_header; - + case current_state is when idle_state => @@ -637,7 +633,7 @@ end process; next_write_header_fifo_i <= '0'; data_header_fifo_in_i <= reg_first_header; next_lvl1_busy_i <= '0'; - if (INIT_TDC_READOUT_IN(0) = '1') then + if (INIT_TDC_READOUT_IN(0) = '1') then next_state <= wait_for_token; else next_state <= idle_state; @@ -662,7 +658,7 @@ end process; else next_state <= wait_for_token; end if; - + ------------------------------------------------------------------------------- -- SEND HEADER ------------------------------------------------------------------------------- @@ -686,7 +682,7 @@ end process; else next_state <= busy_header_state; end if; - + when others => next_debug_register_fsm_header <= x"00"; next_write_header_fifo_i <= '0'; @@ -697,7 +693,7 @@ end process; end process; ----------------------------------------------------------------------------- --- Syncronization and reset FSM_FIFO_MULTIPLEXER +-- Syncronization and reset FSM_FIFO_MULTIPLEXER ----------------------------------------------------------------------------- process (CLK, RESET) begin @@ -708,7 +704,7 @@ end process; reg_read_fee_data_fifo_i <= '0'; reg_read_header_fifo_i <= '0'; reg_lvl1_error_pattern <= (others => '0'); - reg_lvl1_trg_release <= '0'; + reg_lvl1_trg_release <= '0'; reg_ipu_data <= (others => '0'); reg_ipu_data_ready <= '0'; reg_ipu_finished <= '0'; @@ -722,14 +718,14 @@ end process; reg_lvl1_error_pattern <= next_lvl1_error_pattern; reg_lvl1_trg_release <= next_lvl1_trg_release; reg_ipu_data <= next_ipu_data; - reg_ipu_data_ready <= next_ipu_data_ready; + reg_ipu_data_ready <= next_ipu_data_ready; reg_ipu_finished <= next_ipu_finished; reg_pseudo_token <= next_pseudo_token; -- reg_ipu_error_pattern <= next_ipu_error_pattern; end if; end if; end process; - + ------------------------------------------------------------------------------- -- FSM_FIFO_MULTIPLEXER: -- this fsm multiplex data and header into TRB net entity. @@ -738,10 +734,10 @@ end process; how_many_complete_event_in_fifo_counter, counter_word_read_from_trbnet, INIT_TDC_READOUT_IN, word_count_header_fifo, fee_data_fifo_out_i, reg_ipu_read, - reg_empty_flag_fee_data_fifo_i,reg_flag_in_header,read_header_fifo, + reg_reg_empty_flag_fee_data_fifo_i,reg_flag_in_header,read_header_fifo, pulse_ipu_start_readout,counter_token_back, reg_ipu_start_readout_in, - header_data_fifo_out_i, reg_reg_reg_empty_flag_header_data_fifo_i ) - + header_data_fifo_out_i ) + begin next_debug_register_fsm_multiplexer <= (others => '0'); @@ -750,7 +746,7 @@ end process; next_read_header_fifo_i <= '0'; next_lvl1_error_pattern <= (others => '0'); - next_lvl1_trg_release <= '0'; + next_lvl1_trg_release <= '0'; next_ipu_data <= (others => '0'); next_ipu_data_ready <= '0'; next_ipu_finished <= '0'; @@ -758,12 +754,12 @@ end process; push_read_fee_data_1_i <= '0'; next_pseudo_token <= '0'; -- next_ipu_error_pattern <= (others => '0'); - + case current_state_fsm_multiplexer is when idle_state_fsm_multiplexer => next_debug_register_fsm_multiplexer <= x"00"; - next_read_fee_data_fifo_i <= '0'; + next_read_fee_data_fifo_i <= '0'; next_read_header_fifo_i <= '0'; next_ipu_data_ready <= '0'; next_data_to_trb_net <= header_data_fifo_out_i(31 downto 0); @@ -779,16 +775,16 @@ end process; -- at the beginning, after the token comes back). This check is important only -- if one event is written and the same event is read ------------------------------------------------------------------------------- - when wait_for_complete_event_fsm_multiplexer => + when wait_for_complete_event_fsm_multiplexer => next_debug_register_fsm_multiplexer <= x"01"; - next_read_fee_data_fifo_i <= '0'; + next_read_fee_data_fifo_i <= '0'; next_read_header_fifo_i <= '0'; next_ipu_data_ready <= '0'; next_data_to_trb_net <= header_data_fifo_out_i(31 downto 0); --here I wait only when the first token from the first event is back --in future I need to see there is one event at least in the header fifo --check if header is in the header fifo - if (reg_reg_reg_empty_flag_header_data_fifo_i = '0') then + if (empty_flag_header_data_fifo_i = '0') then --if (conv_integer(counter_token_back) >= 1) then next_state_fsm_multiplexer <= dummy_wait_4_fsm_multiplexer; else @@ -806,14 +802,15 @@ end process; -- FIRST HEADER and SECOND : Connect header_fifo to trbnet. -- The first and second headers can be sended. -- I check that the TRBNET read only ONE word than I switch the --- to the data fifo +-- to the data fifo ------------------------------------------------------------------------------- - when send_first_and_second_header_state_fsm_multiplexer => + when send_first_and_second_header_state_fsm_multiplexer => next_debug_register_fsm_multiplexer <= x"03"; next_read_fee_data_fifo_i <= '0'; next_read_header_fifo_i <= '1'; next_ipu_data_ready <= not IPU_READ_IN or not reg_ipu_data_ready; --trbnet can read next_data_to_trb_net <= header_data_fifo_out_i(31 downto 0); --header_fifo + if (read_header_fifo = '1') then --this read correspond to the header --read from trbnet --next_read_header_fifo_i <= '0'; @@ -825,18 +822,18 @@ end process; end if; --here register header flag - when dummy_wait_1_fsm_multiplexer => + when dummy_wait_1_fsm_multiplexer => next_debug_register_fsm_multiplexer <= x"04"; next_read_fee_data_fifo_i <= '0'; next_read_header_fifo_i <= '0'; next_ipu_data_ready <= '0'; --trbnet cannot read next_data_to_trb_net <= fee_data_fifo_out_i(31 downto 0); next_state_fsm_multiplexer <= send_data_state_fsm_multiplexer; - + ------------------------------------------------------------------------------- -- Connect fee_data_fifo to trbnet. -- I leave connected till the flag change to next event -------------------------------------------------------------------------------- +------------------------------------------------------------------------------- when send_data_state_fsm_multiplexer => next_debug_register_fsm_multiplexer <= x"05"; next_read_fee_data_fifo_i <= '1'; @@ -846,16 +843,15 @@ end process; --chenge state if event you read from the fifo is different from the --event you are sending or if the fifo does not contain anymore data. -- if ( (fee_data_fifo_out_i(35 downto 32) /= reg_flag_in_header ) or --- (reg_empty_flag_fee_data_fifo_i = '1') ) then - if ( reg_empty_flag_fee_data_fifo_i = '1' and IPU_READ_IN = '1' ) then - next_ipu_data_ready <= '0'; + if (reg_empty_flag_fee_data_fifo_i = '1') then + next_ipu_data_ready <= '0'; next_read_fee_data_fifo_i <= '0'; next_state_fsm_multiplexer <= end_of_event_transfer_fsm_multiplexer; else next_state_fsm_multiplexer <= send_data_state_fsm_multiplexer; end if; - - --stay if no tok back and fifo empty for + + --stay if no tok back and fifo empty for when end_of_event_transfer_fsm_multiplexer => next_debug_register_fsm_multiplexer <= x"07"; next_read_fee_data_fifo_i <= '0'; @@ -865,14 +861,14 @@ end process; next_ipu_finished <= '1'; --transmission terminated clear_counter_word_read_from_trbnet <= '1'; push_read_fee_data_1_i <= '1'; - + if (reg_ipu_start_readout_in = '0') then next_pseudo_token <= '1'; next_state_fsm_multiplexer <= idle_state_fsm_multiplexer; else next_state_fsm_multiplexer <= end_of_event_transfer_fsm_multiplexer; end if; - + when others => next_debug_register_fsm_multiplexer <= x"08"; next_data_to_trb_net <= header_data_fifo_out_i(31 downto 0); @@ -881,7 +877,7 @@ end process; end process; process (CLK) -begin +begin if rising_edge(CLK) then last_read_fee_data_fifo <= read_fee_data_fifo; if last_read_fee_data_fifo = '1' and last_empty_flag_fee_data_fifo_i = '0' then @@ -890,10 +886,10 @@ begin fee_data_fifo_data_valid <= '0'; end if; end if; - + end process; - + ------------------------------------------------------------------------------- -- EVENT FLAG GENERATOR: -- For each event I generate a flag (4 bits), which will be used to distinguish @@ -931,24 +927,6 @@ begin end if; end process; -------------------------------------------------------------------------------- --- registering input from TRBnet -------------------------------------------------------------------------------- --- process (CLK) --- begin --- if rising_edge(CLK) then --- if RESET = '1' then --- reg_LVL1_TRG_TYPE_IN <= (others => '0'); --4bit --- reg_LVL1_TRG_INFORMATION_IN <= (others => '0'); --8bit --- reg_LVL1_TRG_NUMBER_IN <= (others => '0'); --16bit --- else --- reg_LVL1_TRG_TYPE_IN <= LVL1_TRG_TYPE_IN; --- reg_LVL1_TRG_INFORMATION_IN <= LVL1_TRG_INFORMATION_IN; --- reg_LVL1_TRG_NUMBER_IN <= LVL1_TRG_NUMBER_IN; --- end if; --- end if; --- end process; - ------------------------------------------------------------------------------- -- Make headers 36 bit ------------------------------------------------------------------------------- @@ -956,14 +934,13 @@ first_header <= words_in_event_first_header & --(15 downto 0) flag_event_counter & --(3 downto 0) "0000" & --(3 downto 0) reg_lvl1_trg_type & --(3 downto 0) - reg_lvl1_trg_information & --(7 downto 0) + reg_lvl1_trg_code & --(7 downto 0) reg_lvl1_trg_number; --(15 downto 0) - ---number of dataword are counter in differet way if test data is enabled +--number of dataword are counted in differet way if test data is enabled words_in_event_first_header <= words_in_event_test_data when (DATA_TYPE_SELECT_IN(3 downto 0) = x"2") else words_in_event; - + --register header process (CLK) begin @@ -975,7 +952,7 @@ process (CLK) end if; end if; end process; - + DEBUG_REGISTER_0 <= x"0" & reg_debug_register_fsm_multiplexer(3 downto 0); ------------------------------------------------------------------------------- @@ -1037,16 +1014,16 @@ end process; -- PROCESS to count how many word the TRB net reads from the FIFO_HADER ------------------------------------------------------------------------------- process (CLK, RESET, clear_counter_word_read_from_trbnet, reg_ipu_read, current_state_fsm_multiplexer) -begin +begin if (rising_edge(CLK)) then if (RESET = '1' or clear_counter_word_read_from_trbnet = '1') then counter_word_read_from_trbnet <= (others => '0'); elsif (reg_ipu_read = '1' and current_state_fsm_multiplexer = send_first_and_second_header_state_fsm_multiplexer) then - counter_word_read_from_trbnet <= counter_word_read_from_trbnet + 1; + counter_word_read_from_trbnet <= counter_word_read_from_trbnet + 1; else - counter_word_read_from_trbnet <= counter_word_read_from_trbnet; - end if; + counter_word_read_from_trbnet <= counter_word_read_from_trbnet; + end if; end if; end process; @@ -1072,7 +1049,7 @@ end process; ------------------------------------------------------------------------------- --- AVERAGE NUMBER OF DATAWORDS PER EVENT ON THIS BUS. +-- AVERAGE NUMBER OF DATAWORDS PER EVENT ON THIS BUS. ------------------------------------------------------------------------------- end behavioral; -- 2.43.0