From 366c0ab0c8059e1faba71f4cea5893c5207ad55c Mon Sep 17 00:00:00 2001 From: Florian Marx Date: Wed, 21 Apr 2021 11:46:46 +0200 Subject: [PATCH] Updated the Shutdownlogic files --- shutdownlogic/code/shutdown_compare.vhd | 2 +- shutdownlogic/code/shutdown_individual.vhd | 5 ++--- shutdownlogic/code/shutdown_logic.vhd | 26 ++++++++++++++++++---- shutdownlogic/config.vhd | 2 +- shutdownlogic/config_compile_frankfurt.pl | 4 ++-- shutdownlogic/trb3sc_basic.prj | 2 +- 6 files changed, 29 insertions(+), 12 deletions(-) diff --git a/shutdownlogic/code/shutdown_compare.vhd b/shutdownlogic/code/shutdown_compare.vhd index 47794b8..ef32528 100644 --- a/shutdownlogic/code/shutdown_compare.vhd +++ b/shutdownlogic/code/shutdown_compare.vhd @@ -57,7 +57,7 @@ PROC_COMPARE: process begin wait until rising_edge(clk_in); if sum_signals >= max_signals then temp_out <= (others => '0'); - temp_out(0)<='1'; + temp_out(0) <= '1'; else temp_out <= (others => '0'); diff --git a/shutdownlogic/code/shutdown_individual.vhd b/shutdownlogic/code/shutdown_individual.vhd index 6b1028b..bba3cda 100644 --- a/shutdownlogic/code/shutdown_individual.vhd +++ b/shutdownlogic/code/shutdown_individual.vhd @@ -140,10 +140,9 @@ end process; -- -- end process; -- -PROC_MSPUSER: process begin -- generate a pulse every 10.000 pulses so its every 0.1ms +PROC_MSPUSER: process begin -- generate a pulse every 0.1 ms wait until rising_edge (clk_in); - if ms_timer=x"2710" then -- eqals 10.000 and 14 dual digits ORIGINAL CODE --- if ms_timer=x"0196" then -- eqals 150 ticks + if ms_timer=x"2710" then -- eqals 10.000 rising edges ms_pulse<='1'; ms_timer<=x"0000" ; else diff --git a/shutdownlogic/code/shutdown_logic.vhd b/shutdownlogic/code/shutdown_logic.vhd index 8e0af47..a7ba2ce 100644 --- a/shutdownlogic/code/shutdown_logic.vhd +++ b/shutdownlogic/code/shutdown_logic.vhd @@ -43,13 +43,19 @@ signal disableReg_compare: std_logic_vector(31 downto 0):=(others => '0'); -- registers for READOUT -signal current_count: Array32bit:=(others => (others => '0')); -- OUTPUT from indiv to bussystem to log the live values of every channel +signal current_count: Array32bit:=(others => (others => '0')); +-- OUTPUT from indiv to bussystem to log the live values of every channel signal individual_alerts: std_logic_vector(31 downto 0):=(others => '0'); -- ON / OFF Switch register 32 signal register_onoff :std_logic_vector(31 downto 0):=(others => '0'); +-- shutdown Pulse handling +signal signal_register: std_logic_vector(31 downto 0):=(others => '0'); +signal shutdown_signal: std_logic; +-- signal shutdown_signal:std_logic_vector(OUTPUTS-1 downto 0); + -- hand over the signals between entities signal in_2_indiv :std_logic_vector(INPUTS-1 downto 0); @@ -60,12 +66,19 @@ signal address_i : integer range 0 to 255; + + + + begin address_i <= to_integer(unsigned(BUS_RX.addr(7 downto 0))); --- OUTPUT <= comp_2_out; + + individual_alerts(INPUTS-1 downto 0) <= indiv_2_comp; in_2_indiv <= INPUT; +-- OUTPUT(0) <= shutdown_signal; + signal_register(0) <= shutdown_signal; -- comp_2_out(1) <= not comp_2_out(0); @@ -83,9 +96,12 @@ begin PROC_OFFSWITCH : process (comp_2_out) --Version 2 out of sync begin if register_onoff(0) = '1' then - OUTPUT <= comp_2_out; + shutdown_signal <= comp_2_out(0); +-- shutdown_signal <= comp_2_out; else - OUTPUT <= (others => '0'); + shutdown_signal <= '0'; +-- shutdown_signal <= (others => '0'); + end if; end process; @@ -124,6 +140,8 @@ PROC_REGS : process begin BUS_TX.data <= individual_alerts; elsif BUS_RX.addr(11 downto 8) = x"6" then BUS_TX.data <= register_onoff; + elsif BUS_RX.addr(11 downto 8) = x"7" then + BUS_TX.data <= signal_register; else BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; end if; diff --git a/shutdownlogic/config.vhd b/shutdownlogic/config.vhd index 5a676b7..d6d02f8 100644 --- a/shutdownlogic/config.vhd +++ b/shutdownlogic/config.vhd @@ -13,7 +13,7 @@ package config is constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N constant EVENT_MAX_SIZE : integer := 4096; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2 - + constant FPGA_TYPE : integer := 3; --Runs with 120 MHz instead of 100 MHz constant USE_120_MHZ : integer := c_NO; constant USE_200MHZOSCILLATOR : integer := c_YES; diff --git a/shutdownlogic/config_compile_frankfurt.pl b/shutdownlogic/config_compile_frankfurt.pl index 9de99d5..5f49246 100644 --- a/shutdownlogic/config_compile_frankfurt.pl +++ b/shutdownlogic/config_compile_frankfurt.pl @@ -1,8 +1,8 @@ TOPNAME => "trb3sc_basic", lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1702\@hadeb05.gsi.de", -lattice_path => '/d/jspc29/lattice/diamond/3.8_x64', -synplify_path => '/d/jspc29/lattice/synplify/L-2016.09-1/', +lattice_path => '/d/jspc29/lattice/diamond/3.11_x64', +synplify_path => '/d/jspc29/lattice/synplify/P-2019.09-SP1/', #synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options", # synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", diff --git a/shutdownlogic/trb3sc_basic.prj b/shutdownlogic/trb3sc_basic.prj index 241c751..fe04f7a 100644 --- a/shutdownlogic/trb3sc_basic.prj +++ b/shutdownlogic/trb3sc_basic.prj @@ -175,7 +175,7 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd" add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" -- 2.43.0