From 366ec89f8098cde678e6084bae468004a7866c85 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Mon, 19 Apr 2010 13:58:44 +0000 Subject: [PATCH] *** empty log message *** --- xilinx/virtex4/fifo/fifo_18x512_oreg.xco | 31 +++-- xilinx/virtex4/fifo/fifo_36x16k_oreg.xco | 19 ++- xilinx/virtex4/fifo/fifo_36x512_oreg.ngc | 3 + xilinx/virtex4/fifo/fifo_36x512_oreg.vhd | 155 +++++++++++++++++++++++ xilinx/virtex4/fifo/fifo_36x512_oreg.xco | 81 ++++++++++++ xilinx/virtex4/fifo/fifo_var_oreg.vhd | 28 +++- 6 files changed, 285 insertions(+), 32 deletions(-) create mode 100644 xilinx/virtex4/fifo/fifo_36x512_oreg.ngc create mode 100644 xilinx/virtex4/fifo/fifo_36x512_oreg.vhd create mode 100644 xilinx/virtex4/fifo/fifo_36x512_oreg.xco diff --git a/xilinx/virtex4/fifo/fifo_18x512_oreg.xco b/xilinx/virtex4/fifo/fifo_18x512_oreg.xco index a2f5b55..e411eb3 100644 --- a/xilinx/virtex4/fifo/fifo_18x512_oreg.xco +++ b/xilinx/virtex4/fifo/fifo_18x512_oreg.xco @@ -1,7 +1,7 @@ ############################################################## # -# Xilinx Core Generator version K.39 -# Date: Mon Apr 19 12:38:50 2010 +# Xilinx Core Generator version J.40 +# Date: Sun Apr 18 18:45:39 2010 # ############################################################## # @@ -24,23 +24,22 @@ SET flowvendor = Other SET formalverification = False SET foundationsym = False SET implementationfiletype = Ngc -SET package = ff1148 +SET package = ff668 SET removerpms = False SET simulationfiles = Behavioral -SET speedgrade = -10 +SET speedgrade = -11 SET verilogsim = False SET vhdlsim = True # END Project Options # BEGIN Select -SELECT Fifo_Generator family Xilinx,_Inc. 4.4 +SELECT Fifo_Generator family Xilinx,_Inc. 4.2 # END Select # BEGIN Parameters CSET almost_empty_flag=false CSET almost_full_flag=false CSET component_name=fifo_18x512_oreg CSET data_count=true -CSET data_count_width=10 -CSET disable_timing_violations=false +CSET data_count_width=9 CSET dout_reset_value=0 CSET empty_threshold_assert_value=2 CSET empty_threshold_negate_value=3 @@ -48,12 +47,12 @@ CSET enable_ecc=false CSET enable_int_clk=false CSET fifo_implementation=Common_Clock_Block_RAM CSET full_flags_reset_value=1 -CSET full_threshold_assert_value=1022 -CSET full_threshold_negate_value=1021 +CSET full_threshold_assert_value=510 +CSET full_threshold_negate_value=509 CSET input_data_width=18 -CSET input_depth=1024 +CSET input_depth=512 CSET output_data_width=18 -CSET output_depth=1024 +CSET output_depth=512 CSET overflow_flag=false CSET overflow_sense=Active_High CSET performance_options=Standard_FIFO @@ -61,13 +60,13 @@ CSET programmable_empty_type=No_Programmable_Empty_Threshold CSET programmable_full_type=Single_Programmable_Full_Threshold_Input_Port CSET read_clock_frequency=1 CSET read_data_count=false -CSET read_data_count_width=10 +CSET read_data_count_width=9 CSET reset_pin=true CSET reset_type=Asynchronous_Reset CSET underflow_flag=false CSET underflow_sense=Active_High -CSET use_dout_reset=true -CSET use_embedded_registers=false +CSET use_dout_reset=false +CSET use_embedded_registers=true CSET use_extra_logic=false CSET valid_flag=false CSET valid_sense=Active_High @@ -75,8 +74,8 @@ CSET write_acknowledge_flag=false CSET write_acknowledge_sense=Active_High CSET write_clock_frequency=1 CSET write_data_count=false -CSET write_data_count_width=10 +CSET write_data_count_width=9 # END Parameters GENERATE -# CRC: 98b1a0cf +# CRC: 5d90b917 diff --git a/xilinx/virtex4/fifo/fifo_36x16k_oreg.xco b/xilinx/virtex4/fifo/fifo_36x16k_oreg.xco index d96b915..8de1da4 100644 --- a/xilinx/virtex4/fifo/fifo_36x16k_oreg.xco +++ b/xilinx/virtex4/fifo/fifo_36x16k_oreg.xco @@ -1,7 +1,7 @@ ############################################################## # -# Xilinx Core Generator version K.39 -# Date: Mon Apr 19 12:37:12 2010 +# Xilinx Core Generator version J.40 +# Date: Fri Apr 16 21:01:46 2010 # ############################################################## # @@ -24,23 +24,22 @@ SET flowvendor = Other SET formalverification = False SET foundationsym = False SET implementationfiletype = Ngc -SET package = ff1148 +SET package = ff668 SET removerpms = False SET simulationfiles = Behavioral -SET speedgrade = -10 +SET speedgrade = -11 SET verilogsim = False SET vhdlsim = True # END Project Options # BEGIN Select -SELECT Fifo_Generator family Xilinx,_Inc. 4.4 +SELECT Fifo_Generator family Xilinx,_Inc. 4.2 # END Select # BEGIN Parameters CSET almost_empty_flag=false -CSET almost_full_flag=false +CSET almost_full_flag=true CSET component_name=fifo_36x16k_oreg CSET data_count=true CSET data_count_width=14 -CSET disable_timing_violations=false CSET dout_reset_value=0 CSET empty_threshold_assert_value=2 CSET empty_threshold_negate_value=3 @@ -66,8 +65,8 @@ CSET reset_pin=true CSET reset_type=Asynchronous_Reset CSET underflow_flag=false CSET underflow_sense=Active_High -CSET use_dout_reset=true -CSET use_embedded_registers=false +CSET use_dout_reset=false +CSET use_embedded_registers=true CSET use_extra_logic=false CSET valid_flag=false CSET valid_sense=Active_High @@ -78,5 +77,5 @@ CSET write_data_count=false CSET write_data_count_width=14 # END Parameters GENERATE -# CRC: e09a62f9 +# CRC: 4fce8c61 diff --git a/xilinx/virtex4/fifo/fifo_36x512_oreg.ngc b/xilinx/virtex4/fifo/fifo_36x512_oreg.ngc new file mode 100644 index 0000000..c8870bb --- /dev/null +++ b/xilinx/virtex4/fifo/fifo_36x512_oreg.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e +$0c441<,[o}e~g`n;"2*447&;:%>-*=d:-v+mgcix%hckheo-wiu)Xkn%mekaP37z657Yhzlm%bja<;0,357=4>3CE\XZ5dhl?70<768>0?;4@UURVP?bh}}6897>1e:6uh}27no<=4 ?>1d9:>LHW]]0{~biPelrw}Zrozlyc054?>378=?OIX\^1|ah_dosp|Ys`{oxdRo|sdpw8=<76;?057GAPTV9twi`Wlg{xtQ{hsgplZhboh~n054?>0f8=?OIX\^1|ah_gwohZrozlyc054?>368=?OIX\^1|ah_gwohZrozlycSl}|esv?8:;9KPRW]]0omyoPcnwmp9>=87;i744@UURVP?tcWmkmRm`uov?1GCJGLAMa8Idlhz_oydaac:OjjjtQm{ybcc=4N027?K77:=1E==8;;O3331=I992?7C??929M5421068J475<2D:=>:4N0370>H69<>0B1818J4433G;9<95A1337?K75:=1E=?=;;O3101=I9;??7C?=659M57133G;9495A13;0?K74<2D:?=:4N0120>H6;;>0B<=<4:L271286@>3768J450<2D:?5:4N01:7>H6<=1E=9>;;O3751=I9=8?7C?;359M51233G;?995A1547?K73?=1E=96;;O37=6=I9<>0B<;?4:L21425418J4043G;829M5<4<;O027>H5::1E>>=4N360?K42;2D9:>5A2618J7>43G82?6@<029M7458<;O147>H40:1E?4=4N520?K26:2D=?6@9939M36=I?990B:?<;O517>H0;:1E;9=4N670?K11;2D<;?5A839M=6=I1>90B478;OGWSJTL92Z?7]O]T`9SMKYE]ZCOTo5_IO]AQVHFEL<0_B[]CD68P\VBi2_XI_QNLHCPg>STM[U]E^GMLD18RFE>3_CN[RZVPD3g?]OKAGR&TIL/0/3#WQSE(9$:,L]LIH`8\ZEHZLUBBKA>0:Z\GJTBW@DMCRBFSU48\adXAml0TifPPsknR`ttafd:<6Vkm^ObnjtQm{ybcc??;Yfn[Hoig{\n~~g`nb9bhhit|Vof|ywm;`nnkvrXn|fg:6lncjws`>dfkb{S`o}kdp0?fjll2njxlQlotlw,5/c3mkmRm`uov+5,bbf|hUhcx`{(5+g?agsiVidycz'5(f8`drfWje~by&9)e9geqgXkfex%9&d:fbpdYdg|d$5'k;ecweZeh}g~7<3j4d`vb[firf}6:2i5kauc\gjsi|585h6jnt`]`kphs4:4o7io{a^alqkr;<7n0hlzn_bmvjq:26m1omyoPcnwmp909l2njxlQlotlw828a3mkmRm`uov?2nbb%?&7:fjj-77!>1oec&>1(58`lh/9;#<7iga(01*3>bnf!;?%:5kio*21,1bnf!89%:5kio*17,19'8;ekm,73.?2nbb%<9)69gmk.5? =0hd`'29+4?aoi ;3":6jfn)1*3>bnf!9;%:5kio*05,1bnf5;92:5kio>27;169gmk:6?7=0hd`319<4?aoi4835:6jfn=3=3>bnf58;2:5kio>15;1?08;ekm8759?2nbb1<;>69gmk:5=7=0hd`327<4?aoi4;=5;6jfn=0;:2=cag695384dhl?6;169gmk:4;7=0hd`335<:?aoi4:?1<394dhl?70813mce0>09;ekm81813mce0809;ekm83813mce0:09;ekm8=813mce0408;emvp-6.?2ndyy&>)99gkpr/99#37iazt)32-==cg|~#=?'7;emvp-74!11ocxz'15+;?air|!;>%55kotv+53/?3me~x%?8)99gkpr/91#37iazt)3:-2=cg|~#>$64dnww,76.02ndyy&=1(:8`jss ;8"46j`uu*17,>bh}}"9;$64dnww,7>.02ndyy&=9(58`jss :#37iazt)13-==cg|~#?<'7;emvp-55!11ocxz'32+;?air|!9?%55kotv+70/03me~x%:&7:flqq.2!>1ocxz'6(58`jss >#<7iazt):*3>bh}}"2%:5kotv?4;>18:flqq:69720hb{{<00=<>bh}}6:?364dnww842902ndyy2>5?:8`jss48<546j`uu>23;>99gkpr;::437iazt=07:==cg|~7>807;emvp941611ocxz326<;?air|583255kotv?6<803me~x1<18:flqq:48720hb{{<23=<>bh}}68>364dnww865902ndyy2<4?c8`jss4:?1<364dnww8639?2ndyy2<>69gkpr;<7=0hb{{<4<4?air|5<5;6j`uu>4:2=cg|~74394dnww8<8?3lnbj?`hd49fiur~991mekaP37z657Yhzlm9m6hffn]02}36:VeyijQiigm\c`hbzh~d~Rx;_3]{wqY6:11mekaPgdlfvdrhzV|?S?"/Cnpfc`h'1'8%<9gPiq07?cskd>1bbyQllj:8jbee}`fo46ayesdokrg0|ah_dosp|Ys`{oxd%?&159svjaXmdzuRzgrdqk,7/6<2zycjQjmqvz[qnumzb#?$?;;qplcZcjx}sTxe|jsi*7-42vugnUna}zv_ujqavn/? ;?7}|`g^gntqX|axne&7)048twi`Wlg{xtQ{hsgpl9>=87;i7}|`g^gntqX|axneQnsrgqp-6.9k1{~biPelrw}ZrozlycSl}|esv+5,7e3yxdkRkbpu{\pmtb{aUj~k}t)0*5g=wzfmTi`~{y^vkv`uoWhyxiz'3(3a?uthoVof|ywPtipfwmYf{zoyx%:&1c9svjaXmdzuRzgrdqk[dutm{~#9$?m;qplcZcjx}sTxe|jsi]bwvcu|!<"=o5rne\ahvsqV~c~h}g_`qpawr/? ;i7}|`g^gntqX|axneQnsrgqp->.9m1{~biPelrw}ZrozlycSl}|esv? ;i7}|`g^gntqX|axneQaefcwa-1.9k1{~biPelrw}ZrozlycSckhaug+<,7c3yxdkRkbpu{\pmtb{aUeijo{e=:94;?vugnUmyabPtipfwm.4!890|ah_gwohZrozlyc$9'>3:rqkbYa}efTxe|jsi*6-45vugnUmyabPtipfwm:56890|ah_gwohZrozlyc0>0>3:rqkbYa}efTxe|jsi>7:45018twi`Wog`Rzgrdqk8286=2zycjQiumn\pmtb{a636=0>3:rqkbYa}efTxe|jsi>;:4ga:rqkbYa}efTxe|jsi]bwvcu|!8"=l5rne\bpjkW}byi~fParqfvq.4!8k0|ah_gwohZrozlycSl}|esv+0,7f3yxdkRhzlm]wlwct`Vkxh|{(4+2e>vugnUmyabPtipfwmYf{zoyx%8&1`9svjaXn|fgSyf}erj\evubz}"<%vugnUmyabPtipfwmYimnki%<&1`9svjaXn|fgSyf}erj\j`af|l"8%$??;sf\`drfWje~by&<)028vaYci}kTob{at)6*55=ulVnjxlQlotlw,0/682xoSio{a^alqkr/> ;;7jPd`vb[firf}"<%<>4re]geqgXkfex%6&139q`Zbf|hUhcx`{<983:0=ulVoe:6|k_sqw7>tt|>1xndzjrs68wwus12ehh|ilnu6?sgkam<0{Qncj48swYddb;;7z|Pd`vb[firf}";%<>4ws]geqgXkfex%?&119tvZbf|hUhcx`{(3+24>quWmkmRm`uov+7,773~xThlzn_bmvjq.3!8:0{Qkauc\gjsi|!?"==5xr^fbpdYdg|d$;'>0:uq[agsiVidycz'7(33?rtXlh~jSnaznu*;-44<{UomyoPcnwmp9>=87?0{Qjn79tvZtt|tJK|952;306g33;38;nl94S07956c=83;8>o;;3;03fd><[8;1=>k50;306g33;38;nlo4d01:>5<628qX=?4>3681>455j<>86?>ma69'<3<6;k1}X:h50;395?06sZ;96<=8:38277d2<:0940<^131>v{>7;38q4>=82w/;n4:;c30=?6=>8086;?tH908^46=3c9Y<2<6s89i6pa>5g83>>o61;0;66g>a483>>i6;j0;66a>3983>>o6>10;6)9j:052?k1c2910e<88:18'3`<6?81e;i4>;:k223<72-=n6<9>;o5g>7=6=4+7d8234=i?m0876g>6583>!1b28=:7c9k:598m404290/;h4>709m3a<232c::?4?:%5f>4163g=o6;54i042>5<#?l0:;<5a7e84?>o6>90;6)9j:052?k1c2110e4>50;9j5<2=831d==l50;&4a?75m2d4;n33e?6=,>o1=?k4n6f95>=h9931<7*8e;31a>h0l3807b??8;29 2c=9;o0b:j53:9l551=83.5$6g957cn1965`11694?"0m3;9i6`8d;48?j77;3:1(:k513g8j2b=?21d==<50;&4a?75m2do1=?k4n6f9=>=h99:1<7*8e;31a>h0l3k07bhi:18'3`<6:l1e;i4m;:mea?6=,>o1=?k4n6f9g>=hnm0;6)9j:00f?k1c2m10ckm50;&4a?75m2d5<#?l0:>h5a7e8e?>ia13:1(:k513g8j2b=9910ck650;&4a?75m2d;:me3?6=,>o1=?k4n6f957=h0l3;876ai5;29 2c=9;o0b:j51598kc2=83.5$6g957cn1=;54og094?"0m3;9i6`8d;34?>ia93:1(:k513g8j2b=9110ck>50;&4a?75m2d4g<3f;:<7>5$6g957cn1=o54o02e>5<#?l0:>h5a7e82g>=h99o1<7*8e;31a>h0l3;o76a>0e83>!1b288n7c9k:0g8?j77k3:1(:k513g8j2b=9o10c<>::18'3`<6:l1e;i4=0:9lbd<72-=n6<77<3fom6=4+7d826`=i?m09>65`ed83>!1b288n7c9k:318?le5290/;h4j5:l4`?6<3`i:6=4+7d8f1>h0l3;07dm?:18'3`5<#?l0n96`8d;18?ldb290/;h4j5:l4`?2<3`ho6=4+7d8f1>h0l3?07dlm:18'3`5<#?l0n96`8d;58?ld>290/;h4j5:l4`?><3`h36=4+7d8f1>h0l3307dl8:18'3`5<#?l0n96`8d;`8?ld2290/;h4j5:l4`?e<3`h?6=4+7d8f1>h0l3n07dl<:18'3`5<#?l0n96`8d;d8?ld7290/;h4j5:l4`?7732cjj7>5$6g9a0=i?m0:=65fad83>!1b2l?0b:j51398mdb=83.45<3`kh6=4+7d8f1>h0l3;?76gnb;29 2c=m<1e;i4>5:9jed<72-=n6h;4n6f953=o1i85a7e82=>=nk10;6)9j:d78j2b=9h10en950;&4a?c23g=o65<#?l0n96`8d;3`?>od=3:1(:k5e49m3a<6l21bo94?:%5f>`3n1=h54ib194?"0m3o>7c9k:0d8?ldd290/;h4j5:l4`?4732ci=7>5$6g9a0=i?m09=65fa783>!1b2l?0b:j52398md3=83.75<3f326=4+7d8b6>h0l3:07b77:18'3`5<#?l0j>6`8d;08?j?1290/;h4n2:l4`?5<3f3>6=4+7d8b6>h0l3>07b7;:18'3`5<#?l0j>6`8d;48?j?5290/;h4n2:l4`?1<3f3:6=4+7d8b6>h0l3207o6<:182>5<7sA297)6?:918k2d=831vn<:50;394?6|@180(5>5159l56<722wij7>5b083>5}O0;1Q==4m{78b>a<02l02694<:c8`>=o4o9a94?=n9091<75f15;94?"0m3;?m6`8d;28?l7303:1(:k515c8j2b=921b=9950;&4a?73i2do1=9o4n6f97>=n9=?1<7*8e;37e>h0l3>07d?;4;29 2c=9=k0b:j55:9j515=83.7>5$6g951gn1;65f15394?"0m3;?m6`8d;:8?j72n3:17d?66;29?j7>03:17d?8b;29 2c=9>i0b:j50:9j52g=83.5$6g952en1>65f16:94?"0m3;o1=:m4n6f92>=n9>>1<7*8e;34g>h0l3=07d?83;29 2c=9>i0b:j58:9j5<4=831d=9>50;9l56`=831b4k4?::m2=5<72-=n6<7>;o5g>5=8d83>!1b283:7c9k:398k4>c290/;h4>909m3a<432e:4n4?:%5f>4?63g=o6954o0:a>5<#?l0:5<5a7e86?>i60h0;6)9j:0;2?k1c2?10c<66:18'3`<6181e;i48;:m2<=<72-=n6<7>;o5g>==5383>!1b28??7c9k:098m436290/;h4>559m3a<532c:9=4?:%5f>4333g=o6>54i06e>5<#?l0:995a7e87?>o62=i6=4+7d8211=i?m0376g>a483>>i6i:0;6)9j:0c7?k1c2910c;:m2e4<72-=n67=9g83>!1b28k?7c9k:598k4?b290/;h4>a59m3a<232e:5i4?:%5f>4g33g=o6;54o0;`>5<#?l0:m95a7e84?>i61k0;6)9j:0c7?k1c2110c<=l:188k45?2900e<7n:188m40?290/;h4>709m3a<732c:::4?:%5f>4163g=o6<54i045>5<#?l0:;<5a7e81?>o6><0;6)9j:052?k1c2:10e<8;:18'3`<6?81e;i4;;:k226<72-=n6<9>;o5g>0=6083>!1b28=:7c9k:698m407290/;h4>709m3a5;n3:1?6=3f;257>5;n3:3?6=3`;287>5;n33f?6=,>o1=?k4n6f94>=h99k1<7*8e;31a>h0l3;07b??9;29 2c=9;o0b:j52:9l55>=83.5$6g957cn1865`11494?"0m3;9i6`8d;78?j77<3:1(:k513g8j2b=>21d===50;&4a?75m2do1=?k4n6f9<>=h99;1<7*8e;31a>h0l3307b??0;29 2c=9;o0b:j5a:9lbc<72-=n6<g=h0l3i07bhk:18'3`<6:l1e;i4k;:meg?6=,>o1=?k4n6f9a>=hnk0;6)9j:00f?k1c2o10ck750;&4a?75m2do1=?k4n6f954=h0l3;976ai6;29 2c=9;o0b:j51298kc3=83.5$6g957cn1=854og194?"0m3;9i6`8d;35?>ia:3:1(:k513g8j2b=9>10ck?50;&4a?75m2do1=?k4n6f95<=i68o0;6)9j:00f?k1c28i07b??e;29 2c=9;o0b:j51e98k46c290/;h4>2d9m3a<6m21d==m50;&4a?75m2d76<3flj6=4+7d826`=i?m09=65`eg83>!1b288n7c9k:308?jcb290/;h4>2d9m3a<5;21bo?4?:%5f>`3n1<65fc083>!1b2l?0b:j51:9jg5<72-=n6h;4n6f96>=njo0;6)9j:d78j2b=;21bnh4?:%5f>`3n1865fbe83>!1b2l?0b:j55:9jfg<72-=n6h;4n6f92>=njh0;6)9j:d78j2b=?21bn44?:%5f>`3n1465fb983>!1b2l?0b:j59:9jf2<72-=n6h;4n6f9e>=nj?0;6)9j:d78j2b=j21bn84?:%5f>`3n1o65fb583>!1b2l?0b:j5d:9jf6<72-=n6h;4n6f9a>=nj;0;6)9j:d78j2b=n21bn=4?:%5f>`3n1==54i`d94?"0m3o>7c9k:038?lgb290/;h4j5:l4`?7532cjh7>5$6g9a0=i?m0:?65fab83>!1b2l?0b:j51598mdd=83.43<3`kj6=4+7d8f1>h0l3;=76gn9;29 2c=m<1e;i4>7:9je=<72-=n6h;4n6f95==o1i85a7e82f>=nk?0;6)9j:d78j2b=9j10en;50;&4a?c23g=o65<#?l0n96`8d;3f?>od;3:1(:k5e49m3a<6n21bnn4?:%5f>`3n1>=54ic394?"0m3o>7c9k:338?lg1290/;h4j5:l4`?4532cj97>5$6g9a0=i?m09?65`8e83>>o?m3:17d?75;29 2c=91<0b:j50:9j5=2=83.5$6g95=0n1>65f19094?"0m3;3:6`8d;18?l7?93:1(:k51948j2b=<21b=5>50;&4a?7?>2do1=584n6f92>=n9>o1<7*8e;3;2>h0l3=07d?8d;29 2c=91<0b:j58:9l=<<72-=n6l<4n6f94>=h110;6)9j:`08j2b=921d5:4?:%5f>d4n1>65`9783>!1b2h80b:j53:9l=0<72-=n6l<4n6f90>=h1=0;6)9j:`08j2b==21d5>4?:%5f>d4n1:65`9383>!1b2h80b:j57:9l=4<72-=n6l<4n6f9<>=hi=0;66g>5e83>!1b28?n7c9k:198m43d290/;h4>5d9m3a<632c:9o4?:%5f>43b3g=o6?54i07b>5<#?l0:9h5a7e80?>o6=00;6)9j:07f?k1c2=10e<;7:18'3`<6=l1e;i4:;:k212<72-=n6<;j;o5g>3=5483>!1b28?n7c9k:998m4>02900q~7?:181[?734l15=5+80860>{tm?0;6?uQc39>b?e53-2:6;l4}rg7>5<5sWi:70h5c09'<4<1l2wxi>4?:3y]g5=:n3i;7)6>:648yvc52909wSli;7}Yjl16j7lj;%:2>4?f:p``<72;qUno52f;`a?!>62;k0q~jk:181[df34l1nl5+80801>{tlj0;6?uQb89>b?d>3-2:69>4}rfa>5<5sWh370h5b99'<4<3j2wxhl4?:3y]f2=:n3h<7)6>:428yvb>2909wSl9;=6s|d983>7}Yj<16j7l:;%:2>0452f;`0?!>62{tl:0;6?uQb19>b?d73-2:6894}rf1>5<5sWkm70h5ag9'<4<202wxh<4?:3y]e`=:n3kn7)6>:4;8yvb72909wSok;m6s|cg83>7}Yij16j7ol;%:2>0d6234l1m45+8086a>{tkk0;6?uQa99>b?g?3-2:68h4}rab>5<5sWk<70h5a69'<4<182wxii4?:3y]g==:n3i37)6>:738yvcd2909wSm8;6s|ec83>7}Yk?16j7m9;%:2>3562??0q~k7:181[e434l1o>5+80852>{tm>0;6?uQbb9>b?dd3-2:6;94}rfe>5<5sWh:70h5b09'<4<102wxh94?:3y]e3=:n3k=7)6>:7;8yve>2909wSo:;j1v<9?:181[71?27m6<88;%:2>3c52z\223=:n3;=:6*71;4e?xu6>l0;6?uQ17789c<6><1/4<480:p53b=838pR<8;;5<5sW;=?63i:040?!>62>80q~?9b;296~X6>;16j7?92:&;5?143ty::l4?:3y]537<5o0::<5+80840>{t9?31<74?53-2:6:64}r3:0?6=:rT:5952f;3:0>"?93=27p}>a483>7}Y9h?01k4>a49'<4<6i2wxm>4?:3y]=<=:n3327)6>:0`8yvg62909wS77;7}Y1>16j778;%:2>4be:p=`<72;qU5852f;;6?!>62;:0q~7k:181[?334l1595+80815>{t1j0;6?uQ929>b??43-2:6?<4}r;a>5<5sW3970h5939'<4<5;2wx5l4?:3y]=4=:n33:7)6>:368yv75n3:1>vP>0c9>b?77j2.3=7<:;|q26a<72;qU==o4=g824d=#0809:6s|13a94?4|V8:270h511;8 =7=:>1v<7;%:2>7>52z\242=:n3;;;6*71;0:?xu6:00;6?uQ11489c<68?1/4<4=b:p571=838pR<>;;n5rs005>5<5sW;;?63i:020?!>62;n0q~?=5;296~X68;16j7??2:&;5?4b3ty:>94?:3y]557<5o0:<<5+8081b>{t9;91<7=4?:3y]ba=:n3lo7)6>:218yv76n3:1>vPic:?e>ce<,1;1?95rs03f>5<5sWli70h5fc9'<4<4>2wx=b?`?3-2:6>64}r32e?6=:rTm;63i:g58 =7=;01v{t9821<762:i0q~?>6;296~Xa;27m6k=4$9397a=z{8;>6=4={_d1?8`=n;1/4<4"?939m7p}>1283>7}Yn916j7h?;%:2>1752z\254=:n3;:=6*71;61?xu6;<0;6?uQ10289c<6991/4<4;3:p562=838pR<>i;5<5sW;;i63i:02f?!>62=?0q~?<2;296~X68m16j7??d:&;5?213ty:?<4?:3y]55e<5o0:{t9::1<7:5a8yv7403:1>vP>399>b?7402.3=7:k;|q27f<72;qU=>m4=g827f=#080?i6s|14d94?4|V8?m70h514d8 =7=51zJ;6>{i9;?1<7?tH908yk75>3:1=vF72:m571=83;pD5<4}o316sa13;94?7|@180qc?=a;295~N?:2we=?l50;3xL=451zJ;6>{i9;n1<7?tH908yk75m3:1=vF72:m57`=83;pD5<4}o304?6=9rB3>6sa12394?7|@180qc?<2;295~N?:2we=>=50;3xL=451zJ;6>{i9:?1<7?tH908yk74>3:1=vF72:m561=83;pD5<4}o306sa12;94?7|@180qc?l50;3xL=451zJ;6>{i9:n1<7?tH908yk74m3:1=vF72:m56`=83;pD5<4}o374?6=9rB3>6sa15394?7|@180qc?;2;295~N?:2we=9=50;3xL=451zJ;6>{i9=?1<7?tH908yk73>3:1=vF72:m511=83;pD5<4}o376sa15;94?7|@180qc?;a;295~N?:2we=9l50;3xL=451zJ;6>{i9=n1<7?tH908yk73m3:1=vF72:m51`=83;pD5<4}o364?6=9rB3>6sa14394?7|@180qc?:2;295~N?:2we=8=50;3xL=487>51zJ;6>{i93:1=vF72:m501=83;pD5<4}o366sa14;94?7|@180qc?:a;295~N?:2we=8l50;3xL=4o7>51zJ;6>{i96sa17394?7|@180qc?92;295~N?:2we=;=50;3xL=451zJ;6>{i9??1<7?tH908yk71>3:1=vF72:m531=83;pD5<4}o356sa17;94?7|@180qc?9a;295~N?:2we=;l50;3xL=451zJ;6>{i9?n1<7?tH908yk71m3:1=vF72:m53`=83;pD5<4}o344?6=9rB3>6sa16394?7|@180qc?82;295~N?:2we=:=50;3xL=451zJ;6>{i9>?1<7?tH908yk70>3:1=vF72:m521=83;pD5<4}o346sa16;94?7|@180qc?8a;295~N?:2we=:l50;3xL=451zJ;6>{i9>n1<7?tH908yk70m3:1=vF72:m52`=83;pD5<4}o3;4?6=9rB3>6sa19394?7|@180qc?72;295~N?:2wvqpNOCz3f0?c>mjihjnsO@Cy3yEFWstJK \ No newline at end of file diff --git a/xilinx/virtex4/fifo/fifo_36x512_oreg.vhd b/xilinx/virtex4/fifo/fifo_36x512_oreg.vhd new file mode 100644 index 0000000..4d6c58c --- /dev/null +++ b/xilinx/virtex4/fifo/fifo_36x512_oreg.vhd @@ -0,0 +1,155 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file fifo_36x512_oreg.vhd when simulating +-- the core, fifo_36x512_oreg. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY fifo_36x512_oreg IS + port ( + clk: IN std_logic; + din: IN std_logic_VECTOR(35 downto 0); + prog_full_thresh: IN std_logic_VECTOR(8 downto 0); + rd_en: IN std_logic; + rst: IN std_logic; + wr_en: IN std_logic; + data_count: OUT std_logic_VECTOR(8 downto 0); + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + prog_full: OUT std_logic); +END fifo_36x512_oreg; + +ARCHITECTURE fifo_36x512_oreg_a OF fifo_36x512_oreg IS +-- synthesis translate_off +component wrapped_fifo_36x512_oreg + port ( + clk: IN std_logic; + din: IN std_logic_VECTOR(35 downto 0); + prog_full_thresh: IN std_logic_VECTOR(8 downto 0); + rd_en: IN std_logic; + rst: IN std_logic; + wr_en: IN std_logic; + data_count: OUT std_logic_VECTOR(8 downto 0); + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + prog_full: OUT std_logic); +end component; + +-- Configuration specification + for all : wrapped_fifo_36x512_oreg use entity XilinxCoreLib.fifo_generator_v4_2(behavioral) + generic map( + c_has_int_clk => 0, + c_rd_freq => 1, + c_wr_response_latency => 1, + c_has_srst => 0, + c_has_rd_data_count => 0, + c_din_width => 36, + c_has_wr_data_count => 0, + c_full_flags_rst_val => 1, + c_implementation_type => 0, + c_family => "virtex4", + c_use_embedded_reg => 1, + c_has_wr_rst => 0, + c_wr_freq => 1, + c_use_dout_rst => 0, + c_underflow_low => 0, + c_has_meminit_file => 0, + c_has_overflow => 0, + c_preload_latency => 2, + c_dout_width => 36, + c_rd_depth => 512, + c_default_value => "BlankString", + c_mif_file_name => "BlankString", + c_has_underflow => 0, + c_has_rd_rst => 0, + c_has_almost_full => 0, + c_has_rst => 1, + c_data_count_width => 9, + c_has_wr_ack => 0, + c_use_ecc => 0, + c_wr_ack_low => 0, + c_common_clock => 1, + c_rd_pntr_width => 9, + c_use_fwft_data_count => 0, + c_has_almost_empty => 0, + c_rd_data_count_width => 9, + c_enable_rlocs => 0, + c_wr_pntr_width => 9, + c_overflow_low => 0, + c_prog_empty_type => 0, + c_optimization_mode => 0, + c_wr_data_count_width => 9, + c_preload_regs => 1, + c_dout_rst_val => "0", + c_has_data_count => 1, + c_prog_full_thresh_negate_val => 509, + c_wr_depth => 512, + c_prog_empty_thresh_negate_val => 3, + c_prog_empty_thresh_assert_val => 2, + c_has_valid => 0, + c_init_wr_pntr_val => 0, + c_prog_full_thresh_assert_val => 510, + c_use_fifo16_flags => 0, + c_has_backup => 0, + c_valid_low => 0, + c_prim_fifo_type => "512x36", + c_count_type => 0, + c_prog_full_type => 3, + c_memory_type => 1); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_fifo_36x512_oreg + port map ( + clk => clk, + din => din, + prog_full_thresh => prog_full_thresh, + rd_en => rd_en, + rst => rst, + wr_en => wr_en, + data_count => data_count, + dout => dout, + empty => empty, + full => full, + prog_full => prog_full); +-- synthesis translate_on + +END fifo_36x512_oreg_a; + diff --git a/xilinx/virtex4/fifo/fifo_36x512_oreg.xco b/xilinx/virtex4/fifo/fifo_36x512_oreg.xco new file mode 100644 index 0000000..6a2a80f --- /dev/null +++ b/xilinx/virtex4/fifo/fifo_36x512_oreg.xco @@ -0,0 +1,81 @@ +############################################################## +# +# Xilinx Core Generator version J.40 +# Date: Mon Apr 19 13:40:58 2010 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc4vlx40 +SET devicefamily = virtex4 +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = ff668 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -11 +SET verilogsim = False +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 4.2 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=fifo_36x512_oreg +CSET data_count=true +CSET data_count_width=9 +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=2 +CSET empty_threshold_negate_value=3 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET fifo_implementation=Common_Clock_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=510 +CSET full_threshold_negate_value=509 +CSET input_data_width=36 +CSET input_depth=512 +CSET output_data_width=36 +CSET output_depth=512 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=Standard_FIFO +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=Single_Programmable_Full_Threshold_Input_Port +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=9 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=false +CSET use_embedded_registers=true +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=9 +# END Parameters +GENERATE +# CRC: ffc72e01 + diff --git a/xilinx/virtex4/fifo/fifo_var_oreg.vhd b/xilinx/virtex4/fifo/fifo_var_oreg.vhd index d563da2..f24da79 100644 --- a/xilinx/virtex4/fifo/fifo_var_oreg.vhd +++ b/xilinx/virtex4/fifo/fifo_var_oreg.vhd @@ -47,13 +47,13 @@ end component; component fifo_36x512_oreg port ( clk : in std_logic; - din : in std_logic_vector(17 downto 0); + din : in std_logic_vector(35 downto 0); prog_full_thresh : in std_logic_vector(8 downto 0); rd_en : in std_logic; rst : in std_logic; wr_en : in std_logic; data_count : out std_logic_vector(8 downto 0); - dout : out std_logic_vector(17 downto 0); + dout : out std_logic_vector(35 downto 0); empty : out std_logic; full : out std_logic; prog_full : out std_logic @@ -95,10 +95,10 @@ end component; begin ---REPORT_EN: if ( ( (FIFO_DEPTH < 14 or FIFO_DEPTH >15) and FIFO_WIDTH = 36) or ( (FIFO_DEPTH < 9 or FIFO_DEPTH >9) and FIFO_WIDTH = 18) ) generate --- assert (FALSE) report "Selected data buffer type not implemented : depth - "&integer'image(FIFO_DEPTH)& ", width + 4 : " &integer'image(FIFO_WIDTH) severity error; ---end generate REPORT_EN; - +assert (FIFO_DEPTH >= 13 and FIFO_DEPTH <= 14 and FIFO_WIDTH = 36) + or (FIFO_DEPTH >= 9 and FIFO_DEPTH <= 9 and FIFO_WIDTH = 18) + or (FIFO_DEPTH >= 9 and FIFO_DEPTH <= 9 and FIFO_WIDTH = 36) + report "Selected data buffer size not implemented: depth - "&integer'image(FIFO_DEPTH)& ", width + 4 : " &integer'image(FIFO_WIDTH) severity error; @@ -137,6 +137,22 @@ begin ); end generate; + gen_36_512 : if FIFO_WIDTH = 36 and FIFO_DEPTH = 9 generate + THE_FIFO : fifo_36x512_oreg + port map( + din => Data, + clk => Clock, + wr_en => WrEn, + rd_en => RdEn, + rst => Reset, + prog_full_thresh => AmFullThresh, + dout => Q, + data_count => WCNT(8 downto 0), + empty => Empty, + full => Full, + prog_full => AlmostFull + ); + end generate; gen_18_512 : if FIFO_WIDTH = 18 and FIFO_DEPTH = 9 generate THE_FIFO : fifo_18x512_oreg -- 2.43.0