From 36e087ec334df11dd5f8c59e8c3c845ab507d451 Mon Sep 17 00:00:00 2001 From: hadaq Date: Thu, 30 Jul 2009 12:21:10 +0000 Subject: [PATCH] added gbe --- media_interfaces/ecp2m_sfp/serdes_gbe_2.jhd | 1 + media_interfaces/ecp2m_sfp/serdes_gbe_2.lpc | 140 + media_interfaces/ecp2m_sfp/serdes_gbe_2.pp | 95 + .../ecp2m_sfp/serdes_gbe_2.readme | 151 ++ media_interfaces/ecp2m_sfp/serdes_gbe_2.tft | 98 + media_interfaces/ecp2m_sfp/serdes_gbe_2.txt | 49 + media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd | 2188 ++++++++++++++++ media_interfaces/ecp2m_sfp/serdes_gbe_all.jhd | 1 + media_interfaces/ecp2m_sfp/serdes_gbe_all.lpc | 140 + media_interfaces/ecp2m_sfp/serdes_gbe_all.pp | 95 + .../ecp2m_sfp/serdes_gbe_all.readme | 337 +++ media_interfaces/ecp2m_sfp/serdes_gbe_all.tft | 98 + media_interfaces/ecp2m_sfp/serdes_gbe_all.txt | 91 + media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd | 2266 +++++++++++++++++ .../ecp2m_sfp/serdes_gbe_all_generate.log | 26 + .../trb_net16_med_ecp_sfp_gbe.vhd | 623 +++++ 16 files changed, 6399 insertions(+) create mode 100755 media_interfaces/ecp2m_sfp/serdes_gbe_2.jhd create mode 100755 media_interfaces/ecp2m_sfp/serdes_gbe_2.lpc create mode 100755 media_interfaces/ecp2m_sfp/serdes_gbe_2.pp create mode 100755 media_interfaces/ecp2m_sfp/serdes_gbe_2.readme create mode 100755 media_interfaces/ecp2m_sfp/serdes_gbe_2.tft create mode 100755 media_interfaces/ecp2m_sfp/serdes_gbe_2.txt create mode 100755 media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd create mode 100755 media_interfaces/ecp2m_sfp/serdes_gbe_all.jhd create mode 100755 media_interfaces/ecp2m_sfp/serdes_gbe_all.lpc create mode 100755 media_interfaces/ecp2m_sfp/serdes_gbe_all.pp create mode 100755 media_interfaces/ecp2m_sfp/serdes_gbe_all.readme create mode 100755 media_interfaces/ecp2m_sfp/serdes_gbe_all.tft create mode 100755 media_interfaces/ecp2m_sfp/serdes_gbe_all.txt create mode 100755 media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd create mode 100755 media_interfaces/ecp2m_sfp/serdes_gbe_all_generate.log create mode 100755 media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd diff --git a/media_interfaces/ecp2m_sfp/serdes_gbe_2.jhd b/media_interfaces/ecp2m_sfp/serdes_gbe_2.jhd new file mode 100755 index 0000000..4e8e2d6 --- /dev/null +++ b/media_interfaces/ecp2m_sfp/serdes_gbe_2.jhd @@ -0,0 +1 @@ +MODULE serdes_gbe_2 diff --git a/media_interfaces/ecp2m_sfp/serdes_gbe_2.lpc b/media_interfaces/ecp2m_sfp/serdes_gbe_2.lpc new file mode 100755 index 0000000..e9ecceb --- /dev/null +++ b/media_interfaces/ecp2m_sfp/serdes_gbe_2.lpc @@ -0,0 +1,140 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PCS +CoreRevision=7.0 +ModuleName=serdes_gbe_2 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=07/30/2009 +Time=11:43:53 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Protocol=Quad +mode=Gigabit Ethernet +Channel0=DISABLE +Channel1=DISABLE +Channel2=SINGLE +Channel3=DISABLE +Rate0=None +Rate1=None +Rate2=None +Rate3=None +TxRefClk=CORE_TXREFCLK +RxRefClk=CORE_RXREFCLK +ClkRate=2.0 +ClkMult=20X +CalClkRate=100.0 +DataWidth=16 +FPGAClkRate=100.0 +TxRefClkCM=REFCLK +RxRefClk0CM=REFCLK +RxRefClk1CM=REFCLK +RxRefClk2CM=REFCLK +RxRefClk3CM=REFCLK +ClkRateH=1.0 +ClkMultH=20XH +CalClkRateH=100.0 +DataWidthH=8 +FPGAClkRateH=100.0 +VCh0=0 +VCh1=0 +VCh2=0 +VCh3=0 +PreCh0=DISABLE +PreCh1=DISABLE +PreCh2=DISABLE +PreCh3=DISABLE +TxCh0=50 +TxCh1=50 +TxCh2=50 +TxCh3=50 +EqCh0=DISABLE +EqCh1=DISABLE +EqCh2=DISABLE +EqCh3=DISABLE +RxTermCh0=50 +RxTermCh1=50 +RxTermCh2=50 +RxTermCh3=50 +RxCoupCh0=AC +RxCoupCh1=AC +RxCoupCh2=DC +RxCoupCh3=AC +Loss=0 +CDRLoss=0 +TxTerm=50 +TxCoup=AC +TxPllLoss=0 +TxInvCh0=NORMAL +TxInvCh1=NORMAL +TxInvCh2=NORMAL +TxInvCh3=NORMAL +RxInvCh0=NORMAL +RxInvCh1=NORMAL +RxInvCh2=NORMAL +RxInvCh3=NORMAL +RxModeCh0=NORMAL +RxModeCh1=NORMAL +RxModeCh2=NORMAL +RxModeCh3=NORMAL +Plus=1100000101 +Minus=0011111010 +Mask=1111111111 +Align=AUTO +CTCCh0=NORMAL +CTCCh1=NORMAL +CTCCh2=NORMAL +CTCCh3=NORMAL +CC_MATCH1=0000000000 +CC_MATCH2=0000000000 +CC_MATCH3=0110111100 +CC_MATCH4=0001010000 +MinIPG=3 +High=9 +Low=7 +CC_MATCH_MODE=MATCH_3_4 +RxDataCh0=FALSE +RxDataCh1=FALSE +RxDataCh2=FALSE +RxDataCh3=FALSE +AlignerCh0=FALSE +AlignerCh1=FALSE +AlignerCh2=FALSE +AlignerCh3=FALSE +DetectCh0=FALSE +DetectCh1=FALSE +DetectCh2=FALSE +DetectCh3=FALSE +ELSMCh0=FALSE +ELSMCh1=FALSE +ELSMCh2=FALSE +ELSMCh3=FALSE +_teidleCh0=FALSE +_teidleCh1=FALSE +_teidleCh2=FALSE +_teidleCh3=FALSE +Ports0=FALSE +rdoPorts0=Serial Loopback +Ports1=TRUE +Ports2=TRUE +Ports3=FALSE +Ports3_1=FALSE +Ports4=FALSE diff --git a/media_interfaces/ecp2m_sfp/serdes_gbe_2.pp b/media_interfaces/ecp2m_sfp/serdes_gbe_2.pp new file mode 100755 index 0000000..d39d4c8 --- /dev/null +++ b/media_interfaces/ecp2m_sfp/serdes_gbe_2.pp @@ -0,0 +1,95 @@ +#define _device_name "LFE2M100E" +#define _protocol_mode "Quad Based Protocol Mode" +#define _protocol "GIGE" +#define _ch0_mode "DISABLE" +#define _ch1_mode "DISABLE" +#define _ch2_mode "SINGLE" +#define _ch3_mode "DISABLE" +#define _pll_txsrc "CORE_TXREFCLK" +#define _pll_rxsrc "CORE_RXREFCLK" +#define _datarange "MEDHIGH" +#define _refclk_mult "20X" +#define _refclk_rate 100.0 +#define _data_width "16" +#define _fpgaintclk_rate 100.0 +#define _ch0_tdrv_amp "0" +#define _ch1_tdrv_amp "0" +#define _ch2_tdrv_amp "0" +#define _ch3_tdrv_amp "0" +#define _ch0_tx_pre "DISABLE" +#define _ch1_tx_pre "DISABLE" +#define _ch2_tx_pre "DISABLE" +#define _ch3_tx_pre "DISABLE" +#define _ch0_rterm_tx "50" +#define _ch1_rterm_tx "50" +#define _ch2_rterm_tx "50" +#define _ch3_rterm_tx "50" +#define _ch0_rx_eq "DISABLE" +#define _ch1_rx_eq "DISABLE" +#define _ch2_rx_eq "DISABLE" +#define _ch3_rx_eq "DISABLE" +#define _ch0_rterm_rx "50" +#define _ch1_rterm_rx "50" +#define _ch2_rterm_rx "50" +#define _ch3_rterm_rx "50" +#define _ch0_rx_dcc "AC" +#define _ch1_rx_dcc "AC" +#define _ch2_rx_dcc "DC" +#define _ch3_rx_dcc "AC" +#define _los_threshold "0" +#define _pll_term "50" +#define _pll_dcc "AC" +#define _pll_lol_set "0" +#define _ch0_tx_sb "NORMAL" +#define _ch1_tx_sb "NORMAL" +#define _ch2_tx_sb "NORMAL" +#define _ch3_tx_sb "NORMAL" +#define _ch0_rx_sb "NORMAL" +#define _ch1_rx_sb "NORMAL" +#define _ch2_rx_sb "NORMAL" +#define _ch3_rx_sb "NORMAL" +#define _ch0_8b10b "NORMAL" +#define _ch1_8b10b "NORMAL" +#define _ch2_8b10b "NORMAL" +#define _ch3_8b10b "NORMAL" +#define _comma_a "1100000101" +#define _comma_b "0011111010" +#define _comma_m "1111111111" +#define _comma_align "AUTO" +#define _ch0_ctc_byp "NORMAL" +#define _ch1_ctc_byp "NORMAL" +#define _ch2_ctc_byp "NORMAL" +#define _ch3_ctc_byp "NORMAL" +#define _cc_match1 "0000000000" +#define _cc_match2 "0000000000" +#define _cc_match3 "0110111100" +#define _cc_match4 "0001010000" +#define _cc_match_mode "MATCH_3_4" +#define _cc_min_ipg "3" +#define _cchmark "9" +#define _cclmark "7" +#define _ch0_ird "FALSE" +#define _ch1_ird "FALSE" +#define _ch2_ird "FALSE" +#define _ch3_ird "FALSE" +#define _ch0_elsm "FALSE" +#define _ch1_elsm "FALSE" +#define _ch2_elsm "FALSE" +#define _ch3_elsm "FALSE" +#define _ch0_teidle "FALSE" +#define _ch1_teidle "FALSE" +#define _ch2_teidle "FALSE" +#define _ch3_teidle "FALSE" +#define _loopback "FALSE" +#define _lbtype "Serial Loopback" +#define _refck2core "TRUE" +#define _pllqclkports "FALSE" +#define _sci_ports "FALSE" +#define _sci_int_port "FALSE" +#define _errsports "TRUE" + +#define _circuit_name serdes_gbe_2 +#define _lang vhdl + +#include +#include diff --git a/media_interfaces/ecp2m_sfp/serdes_gbe_2.readme b/media_interfaces/ecp2m_sfp/serdes_gbe_2.readme new file mode 100755 index 0000000..2ef7bb2 --- /dev/null +++ b/media_interfaces/ecp2m_sfp/serdes_gbe_2.readme @@ -0,0 +1,151 @@ + + TOOL: orcapp + DATE: 19-MAR-2008 13:11:51 + TITLE: Lattice Semiconductor Corporation + MODULE: serdes_gbe_2 + DESIGN: serdes_gbe_2 + FILENAME: serdes_gbe_2.readme + PROJECT: Unknown + VERSION: 2.0 + This file is auto generated by the ispLEVER + + +NOTE: This readme file has been provided to instantiate the interface +netlist. Since this template contains synthesis attributes for precision that +are crucial to the design flow, we recommend that you use this +template in your FPGA design. +entity chip is +port ( + +-- Add your FPGA design top level I/Os here + + +-- ASIC side pins for PCSA. These pins must exist for the +-- PCS core. + refclkp : in std_logic; + refclkn : in std_logic; + hdinp0 : in std_logic; + hdinn0 : in std_logic; + hdinp1 : in std_logic; + hdinn1 : in std_logic; + hdinp2 : in std_logic; + hdinn2 : in std_logic; + hdinp3 : in std_logic; + hdinn3 : in std_logic; + + hdoutp0 : out std_logic; + hdoutn0 : out std_logic; + hdoutp1 : out std_logic; + hdoutn1 : out std_logic; + hdoutp2 : out std_logic; + hdoutn2 : out std_logic; + hdoutp3 : out std_logic; + hdoutn3 : out std_logic; + + +); +end chip; + +architecture chip_arch of chip is + +-- This defines all the high-speed ports. You may have to remove +-- some of them depending on your design. +attribute nopad : string; +attribute nopad of + refclkp, refclkn, + hdinp0, hdinn0, hdinp1, hdinn1, + hdinp2, hdinn2, hdinp3, hdinn3, + hdoutp0, hdoutn0, hdoutp1, hdoutn1, + hdoutp2, hdoutn2, hdoutp3, hdoutn3 : signal is "true"; + + COMPONENT serdes_gbe_2 + PORT( + core_txrefclk : IN std_logic; + core_rxrefclk : IN std_logic; + hdinp2 : IN std_logic; + hdinn2 : IN std_logic; + ff_rxiclk_ch2 : IN std_logic; + ff_txiclk_ch2 : IN std_logic; + ff_ebrd_clk_2 : IN std_logic; + ff_txdata_ch2 : IN std_logic_vector(15 downto 0); + ff_tx_k_cntrl_ch2 : IN std_logic_vector(1 downto 0); + ff_xmit_ch2 : IN std_logic_vector(1 downto 0); + ff_correct_disp_ch2 : IN std_logic_vector(1 downto 0); + ffc_rrst_ch2 : IN std_logic; + ffc_lane_tx_rst_ch2 : IN std_logic; + ffc_lane_rx_rst_ch2 : IN std_logic; + ffc_txpwdnb_ch2 : IN std_logic; + ffc_rxpwdnb_ch2 : IN std_logic; + ffc_macro_rst : IN std_logic; + ffc_quad_rst : IN std_logic; + ffc_trst : IN std_logic; + hdoutp2 : OUT std_logic; + hdoutn2 : OUT std_logic; + ff_rxdata_ch2 : OUT std_logic_vector(15 downto 0); + ff_rx_k_cntrl_ch2 : OUT std_logic_vector(1 downto 0); + ff_rxfullclk_ch2 : OUT std_logic; + ff_rxhalfclk_ch2 : OUT std_logic; + ff_disp_err_ch2 : OUT std_logic_vector(1 downto 0); + ff_cv_ch2 : OUT std_logic_vector(1 downto 0); + ff_rx_even_ch2 : OUT std_logic_vector(1 downto 0); + ffs_rlos_lo_ch2 : OUT std_logic; + ffs_ls_sync_status_ch2 : OUT std_logic; + ffs_cc_underrun_ch2 : OUT std_logic; + ffs_cc_overrun_ch2 : OUT std_logic; + ffs_txfbfifo_error_ch2 : OUT std_logic; + ffs_rxfbfifo_error_ch2 : OUT std_logic; + ffs_rlol_ch2 : OUT std_logic; + oob_out_ch2 : OUT std_logic; + ff_txfullclk : OUT std_logic; + ff_txhalfclk : OUT std_logic; + refck2core : OUT std_logic; + ffs_plol : OUT std_logic + ); + END COMPONENT; + + + + uut: serdes_gbe_2 PORT MAP( + core_txrefclk => core_txrefclk, + core_rxrefclk => core_rxrefclk, + hdinp2 => hdinp2, + hdinn2 => hdinn2, + hdoutp2 => hdoutp2, + hdoutn2 => hdoutn2, + ff_rxiclk_ch2 => ff_rxiclk_ch2, + ff_txiclk_ch2 => ff_txiclk_ch2, + ff_ebrd_clk_2 => ff_ebrd_clk_2, + ff_txdata_ch2 => ff_txdata_ch2, + ff_rxdata_ch2 => ff_rxdata_ch2, + ff_tx_k_cntrl_ch2 => ff_tx_k_cntrl_ch2, + ff_rx_k_cntrl_ch2 => ff_rx_k_cntrl_ch2, + ff_rxfullclk_ch2 => ff_rxfullclk_ch2, + ff_rxhalfclk_ch2 => ff_rxhalfclk_ch2, + ff_xmit_ch2 => ff_xmit_ch2, + ff_correct_disp_ch2 => ff_correct_disp_ch2, + ff_disp_err_ch2 => ff_disp_err_ch2, + ff_cv_ch2 => ff_cv_ch2, + ff_rx_even_ch2 => ff_rx_even_ch2, + ffc_rrst_ch2 => ffc_rrst_ch2, + ffc_lane_tx_rst_ch2 => ffc_lane_tx_rst_ch2, + ffc_lane_rx_rst_ch2 => ffc_lane_rx_rst_ch2, + ffc_txpwdnb_ch2 => ffc_txpwdnb_ch2, + ffc_rxpwdnb_ch2 => ffc_rxpwdnb_ch2, + ffs_rlos_lo_ch2 => ffs_rlos_lo_ch2, + ffs_ls_sync_status_ch2 => ffs_ls_sync_status_ch2, + ffs_cc_underrun_ch2 => ffs_cc_underrun_ch2, + ffs_cc_overrun_ch2 => ffs_cc_overrun_ch2, + ffs_txfbfifo_error_ch2 => ffs_txfbfifo_error_ch2, + ffs_rxfbfifo_error_ch2 => ffs_rxfbfifo_error_ch2, + ffs_rlol_ch2 => ffs_rlol_ch2, + oob_out_ch2 => oob_out_ch2, + ffc_macro_rst => ffc_macro_rst, + ffc_quad_rst => ffc_quad_rst, + ffc_trst => ffc_trst, + ff_txfullclk => ff_txfullclk, + ff_txhalfclk => ff_txhalfclk, + refck2core => refck2core, + ffs_plol => ffs_plol + ); + + diff --git a/media_interfaces/ecp2m_sfp/serdes_gbe_2.tft b/media_interfaces/ecp2m_sfp/serdes_gbe_2.tft new file mode 100755 index 0000000..8a55292 --- /dev/null +++ b/media_interfaces/ecp2m_sfp/serdes_gbe_2.tft @@ -0,0 +1,98 @@ +@set suppresnewline=on@ + +@comment --------------------------------------------------------------------- @ +@comment Template-drive TFI generator @ +@comment Template for TFI generation. @ +@comment --------------------------------------------------------------------- @ + +@set suppresnewline=off@ + TOOL: orcapp + DATE: 19-MAR-2008 13:11:51 + TITLE: %title% + MODULE: %module% + DESIGN: %module% + FILENAME: %filename% + PROJECT: %project% + VERSION: %ver% + This file is auto generated by the ispLEVER +@set suppresnewline=on@ + +@cr@ +@cr@ + +@set sigdelim=@ + +NOTE: This readme file has been provided to instantiate the interface@cr@ +netlist. Since this template contains synthesis attributes for precision that@cr@ +are crucial to the design flow, we recommend that you use this@cr@ +template in your FPGA design.@cr@ +entity chip is@cr@ +port (@cr@ +@cr@ +-- Add your FPGA design top level I/Os here@cr@ +@cr@ +@cr@ +-- ASIC side pins for PCSA. These pins must exist for the@cr@ +-- PCS core.@cr@ + refclkp : in std_logic;@cr@ + refclkn : in std_logic;@cr@ + hdinp0 : in std_logic;@cr@ + hdinn0 : in std_logic;@cr@ + hdinp1 : in std_logic;@cr@ + hdinn1 : in std_logic;@cr@ + hdinp2 : in std_logic;@cr@ + hdinn2 : in std_logic;@cr@ + hdinp3 : in std_logic;@cr@ + hdinn3 : in std_logic;@cr@ +@cr@ + hdoutp0 : out std_logic;@cr@ + hdoutn0 : out std_logic;@cr@ + hdoutp1 : out std_logic;@cr@ + hdoutn1 : out std_logic;@cr@ + hdoutp2 : out std_logic;@cr@ + hdoutn2 : out std_logic;@cr@ + hdoutp3 : out std_logic;@cr@ + hdoutn3 : out std_logic;@cr@ +@cr@ +@cr@ +);@cr@ +end chip;@cr@ +@cr@ +architecture chip_arch of chip is@cr@ +@cr@ +-- This defines all the high-speed ports. You may have to remove@cr@ +-- some of them depending on your design.@cr@ +attribute nopad : string;@cr@ +attribute nopad of@cr@ + refclkp, refclkn,@cr@ + hdinp0, hdinn0, hdinp1, hdinn1,@cr@ + hdinp2, hdinn2, hdinp3, hdinn3,@cr@ + hdoutp0, hdoutn0, hdoutp1, hdoutn1,@cr@ + hdoutp2, hdoutn2, hdoutp3, hdoutn3 : signal is "true";@cr@ + +@cr@ +@tab@COMPONENT %module% +@set sigdelim=@ +@cr@@tab@PORT( +@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@ +@ifhas oport=*@ @comment if the design has any output ports... @ + @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@ + @set sigdelim=;@ + @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@ +@endif@ +@ifnhas oport=*@ @comment we need an "else in this language! @ + @set sigdelim=;@ + @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@ +@endif@ +@cr@@tab@@tab@);@cr@ +@tab@END COMPONENT;@cr@@cr@ +@comment Now do a signal declaration for each port @ + +@cr@@cr@ +@comment do the component instantiation @ +@set sigdelim=,@ +@tab@uut: %module% PORT MAP( +@iterate@%port% +@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@ +@cr@@tab@);@cr@@cr@ +@set suppresnewline=off@ diff --git a/media_interfaces/ecp2m_sfp/serdes_gbe_2.txt b/media_interfaces/ecp2m_sfp/serdes_gbe_2.txt new file mode 100755 index 0000000..3a7cff7 --- /dev/null +++ b/media_interfaces/ecp2m_sfp/serdes_gbe_2.txt @@ -0,0 +1,49 @@ + +# This file is used by the simulation model as well as the ispLEVER bitstream +# generation process to automatically initialize the PCSC quad to the mode +# selected in the IPexpress. This file is expected to be modified by the +# end user to adjust the PCSC quad to the final design requirements. + +DEVICE_NAME "LFE2M100E" +PROTOCOL "GIGE" +CH0_MODE "DISABLE" +CH1_MODE "DISABLE" +CH2_MODE "SINGLE" +CH3_MODE "DISABLE" +PLL_SRC "CORE_TXREFCLK" +DATARANGE "MEDHIGH" +CH2_CDR_SRC "CORE_RXREFCLK" +CH2_DATA_WIDTH "16" +CH2_REFCK_MULT "20X" +#REFCLK_RATE 100.0 +#FPGAINTCLK_RATE 100.0 +CH2_TDRV_AMP "0" +CH2_TX_PRE "DISABLE" +CH2_RTERM_TX "50" +CH2_RX_EQ "DISABLE" +CH2_RTERM_RX "50" +CH2_RX_DCC "DC" +LOS_THRESHOLD "0" +PLL_TERM "50" +PLL_DCC "AC" +PLL_LOL_SET "0" +CH2_TX_SB "NORMAL" +CH2_RX_SB "NORMAL" +CH2_8B10B "NORMAL" +COMMA_A "1100000101" +COMMA_B "0011111010" +COMMA_M "1111111111" +CH2_COMMA_ALIGN "AUTO" +CH2_CTC_BYP "NORMAL" +CC_MATCH1 "0000000000" +CC_MATCH2 "0000000000" +CC_MATCH3 "0110111100" +CC_MATCH4 "0001010000" +CC_MATCH_MODE "MATCH_3_4" +CC_MIN_IPG "3" +CCHMARK "9" +CCLMARK "7" +OS_REFCK2CORE "1" +OS_PLLQCLKPORTS "0" +OS_INT_ALL "0" + diff --git a/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd b/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd new file mode 100755 index 0000000..4e5104a --- /dev/null +++ b/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd @@ -0,0 +1,2188 @@ + + +--synopsys translate_off + +library pcsc_work; +use pcsc_work.all; +library IEEE; +use IEEE.std_logic_1164.all; + +entity PCSC is +GENERIC( + CONFIG_FILE : String := "serdes_gbe_2.txt" + ); +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_RX_Q_CLK_0 : out std_logic; + FF_RX_Q_CLK_1 : out std_logic; + FF_RX_Q_CLK_2 : out std_logic; + FF_RX_Q_CLK_3 : out std_logic; + FF_TX_F_CLK : out std_logic; + FF_TX_H_CLK : out std_logic; + FF_TX_Q_CLK : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + OOB_OUT_0 : out std_logic; + OOB_OUT_1 : out std_logic; + OOB_OUT_2 : out std_logic; + OOB_OUT_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic +); + +end PCSC; + +architecture PCSC_arch of PCSC is + +component PCSC_sim +GENERIC( + CONFIG_FILE : String + ); +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_RX_Q_CLK_0 : out std_logic; + FF_RX_Q_CLK_1 : out std_logic; + FF_RX_Q_CLK_2 : out std_logic; + FF_RX_Q_CLK_3 : out std_logic; + FF_TX_F_CLK : out std_logic; + FF_TX_H_CLK : out std_logic; + FF_TX_Q_CLK : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + OOB_OUT_0 : out std_logic; + OOB_OUT_1 : out std_logic; + OOB_OUT_2 : out std_logic; + OOB_OUT_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic +); +end component; + +begin + +PCSC_sim_inst : PCSC_sim +generic map ( + CONFIG_FILE => CONFIG_FILE) +port map ( + HDINN0 => HDINN0, + HDINN1 => HDINN1, + HDINN2 => HDINN2, + HDINN3 => HDINN3, + HDINP0 => HDINP0, + HDINP1 => HDINP1, + HDINP2 => HDINP2, + HDINP3 => HDINP3, + REFCLKN => REFCLKN, + REFCLKP => REFCLKP, + CIN11 => CIN11, + CIN10 => CIN10, + CIN9 => CIN9, + CIN8 => CIN8, + CIN7 => CIN7, + CIN6 => CIN6, + CIN5 => CIN5, + CIN4 => CIN4, + CIN3 => CIN3, + CIN2 => CIN2, + CIN1 => CIN1, + CIN0 => CIN0, + CYAWSTN => CYAWSTN, + FF_EBRD_CLK_3 => FF_EBRD_CLK_3, + FF_EBRD_CLK_2 => FF_EBRD_CLK_2, + FF_EBRD_CLK_1 => FF_EBRD_CLK_1, + FF_EBRD_CLK_0 => FF_EBRD_CLK_0, + FF_RXI_CLK_3 => FF_RXI_CLK_3, + FF_RXI_CLK_2 => FF_RXI_CLK_2, + FF_RXI_CLK_1 => FF_RXI_CLK_1, + FF_RXI_CLK_0 => FF_RXI_CLK_0, + + FF_TX_D_0_0 => FF_TX_D_0_0, + FF_TX_D_0_1 => FF_TX_D_0_1, + FF_TX_D_0_2 => FF_TX_D_0_2, + FF_TX_D_0_3 => FF_TX_D_0_3, + FF_TX_D_0_4 => FF_TX_D_0_4, + FF_TX_D_0_5 => FF_TX_D_0_5, + FF_TX_D_0_6 => FF_TX_D_0_6, + FF_TX_D_0_7 => FF_TX_D_0_7, + FF_TX_D_0_8 => FF_TX_D_0_8, + FF_TX_D_0_9 => FF_TX_D_0_9, + FF_TX_D_0_10 => FF_TX_D_0_10, + FF_TX_D_0_11 => FF_TX_D_0_11, + FF_TX_D_0_12 => FF_TX_D_0_12, + FF_TX_D_0_13 => FF_TX_D_0_13, + FF_TX_D_0_14 => FF_TX_D_0_14, + FF_TX_D_0_15 => FF_TX_D_0_15, + FF_TX_D_0_16 => FF_TX_D_0_16, + FF_TX_D_0_17 => FF_TX_D_0_17, + FF_TX_D_0_18 => FF_TX_D_0_18, + FF_TX_D_0_19 => FF_TX_D_0_19, + FF_TX_D_0_20 => FF_TX_D_0_20, + FF_TX_D_0_21 => FF_TX_D_0_21, + FF_TX_D_0_22 => FF_TX_D_0_22, + FF_TX_D_0_23 => FF_TX_D_0_23, + FF_TX_D_1_0 => FF_TX_D_1_0, + FF_TX_D_1_1 => FF_TX_D_1_1, + FF_TX_D_1_2 => FF_TX_D_1_2, + FF_TX_D_1_3 => FF_TX_D_1_3, + FF_TX_D_1_4 => FF_TX_D_1_4, + FF_TX_D_1_5 => FF_TX_D_1_5, + FF_TX_D_1_6 => FF_TX_D_1_6, + FF_TX_D_1_7 => FF_TX_D_1_7, + FF_TX_D_1_8 => FF_TX_D_1_8, + FF_TX_D_1_9 => FF_TX_D_1_9, + FF_TX_D_1_10 => FF_TX_D_1_10, + FF_TX_D_1_11 => FF_TX_D_1_11, + FF_TX_D_1_12 => FF_TX_D_1_12, + FF_TX_D_1_13 => FF_TX_D_1_13, + FF_TX_D_1_14 => FF_TX_D_1_14, + FF_TX_D_1_15 => FF_TX_D_1_15, + FF_TX_D_1_16 => FF_TX_D_1_16, + FF_TX_D_1_17 => FF_TX_D_1_17, + FF_TX_D_1_18 => FF_TX_D_1_18, + FF_TX_D_1_19 => FF_TX_D_1_19, + FF_TX_D_1_20 => FF_TX_D_1_20, + FF_TX_D_1_21 => FF_TX_D_1_21, + FF_TX_D_1_22 => FF_TX_D_1_22, + FF_TX_D_1_23 => FF_TX_D_1_23, + FF_TX_D_2_0 => FF_TX_D_2_0, + FF_TX_D_2_1 => FF_TX_D_2_1, + FF_TX_D_2_2 => FF_TX_D_2_2, + FF_TX_D_2_3 => FF_TX_D_2_3, + FF_TX_D_2_4 => FF_TX_D_2_4, + FF_TX_D_2_5 => FF_TX_D_2_5, + FF_TX_D_2_6 => FF_TX_D_2_6, + FF_TX_D_2_7 => FF_TX_D_2_7, + FF_TX_D_2_8 => FF_TX_D_2_8, + FF_TX_D_2_9 => FF_TX_D_2_9, + FF_TX_D_2_10 => FF_TX_D_2_10, + FF_TX_D_2_11 => FF_TX_D_2_11, + FF_TX_D_2_12 => FF_TX_D_2_12, + FF_TX_D_2_13 => FF_TX_D_2_13, + FF_TX_D_2_14 => FF_TX_D_2_14, + FF_TX_D_2_15 => FF_TX_D_2_15, + FF_TX_D_2_16 => FF_TX_D_2_16, + FF_TX_D_2_17 => FF_TX_D_2_17, + FF_TX_D_2_18 => FF_TX_D_2_18, + FF_TX_D_2_19 => FF_TX_D_2_19, + FF_TX_D_2_20 => FF_TX_D_2_20, + FF_TX_D_2_21 => FF_TX_D_2_21, + FF_TX_D_2_22 => FF_TX_D_2_22, + FF_TX_D_2_23 => FF_TX_D_2_23, + FF_TX_D_3_0 => FF_TX_D_3_0, + FF_TX_D_3_1 => FF_TX_D_3_1, + FF_TX_D_3_2 => FF_TX_D_3_2, + FF_TX_D_3_3 => FF_TX_D_3_3, + FF_TX_D_3_4 => FF_TX_D_3_4, + FF_TX_D_3_5 => FF_TX_D_3_5, + FF_TX_D_3_6 => FF_TX_D_3_6, + FF_TX_D_3_7 => FF_TX_D_3_7, + FF_TX_D_3_8 => FF_TX_D_3_8, + FF_TX_D_3_9 => FF_TX_D_3_9, + FF_TX_D_3_10 => FF_TX_D_3_10, + FF_TX_D_3_11 => FF_TX_D_3_11, + FF_TX_D_3_12 => FF_TX_D_3_12, + FF_TX_D_3_13 => FF_TX_D_3_13, + FF_TX_D_3_14 => FF_TX_D_3_14, + FF_TX_D_3_15 => FF_TX_D_3_15, + FF_TX_D_3_16 => FF_TX_D_3_16, + FF_TX_D_3_17 => FF_TX_D_3_17, + FF_TX_D_3_18 => FF_TX_D_3_18, + FF_TX_D_3_19 => FF_TX_D_3_19, + FF_TX_D_3_20 => FF_TX_D_3_20, + FF_TX_D_3_21 => FF_TX_D_3_21, + FF_TX_D_3_22 => FF_TX_D_3_22, + FF_TX_D_3_23 => FF_TX_D_3_23, + FF_TXI_CLK_0 => FF_TXI_CLK_0, + FF_TXI_CLK_1 => FF_TXI_CLK_1, + FF_TXI_CLK_2 => FF_TXI_CLK_2, + FF_TXI_CLK_3 => FF_TXI_CLK_3, + FFC_CK_CORE_RX => FFC_CK_CORE_RX, + FFC_CK_CORE_TX => FFC_CK_CORE_TX, + FFC_EI_EN_0 => FFC_EI_EN_0, + FFC_EI_EN_1 => FFC_EI_EN_1, + FFC_EI_EN_2 => FFC_EI_EN_2, + FFC_EI_EN_3 => FFC_EI_EN_3, + FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0, + FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1, + FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2, + FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3, + FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0, + FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1, + FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2, + FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3, + FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0, + FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1, + FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2, + FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3, + FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0, + FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1, + FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2, + FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3, + FFC_MACRO_RST => FFC_MACRO_RST, + FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0, + FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1, + FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2, + FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3, + FFC_PCIE_CT_0 => FFC_PCIE_CT_0, + FFC_PCIE_CT_1 => FFC_PCIE_CT_1, + FFC_PCIE_CT_2 => FFC_PCIE_CT_2, + FFC_PCIE_CT_3 => FFC_PCIE_CT_3, + FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0, + FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1, + FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2, + FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3, + FFC_QUAD_RST => FFC_QUAD_RST, + FFC_RRST_0 => FFC_RRST_0, + FFC_RRST_1 => FFC_RRST_1, + FFC_RRST_2 => FFC_RRST_2, + FFC_RRST_3 => FFC_RRST_3, + FFC_RXPWDNB_0 => FFC_RXPWDNB_0, + FFC_RXPWDNB_1 => FFC_RXPWDNB_1, + FFC_RXPWDNB_2 => FFC_RXPWDNB_2, + FFC_RXPWDNB_3 => FFC_RXPWDNB_3, + FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, + FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, + FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, + FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, + FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0, + FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1, + FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2, + FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3, + FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0, + FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1, + FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2, + FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3, + FFC_TRST => FFC_TRST, + FFC_TXPWDNB_0 => FFC_TXPWDNB_0, + FFC_TXPWDNB_1 => FFC_TXPWDNB_1, + FFC_TXPWDNB_2 => FFC_TXPWDNB_2, + FFC_TXPWDNB_3 => FFC_TXPWDNB_3, + SCIADDR0 => SCIADDR0, + SCIADDR1 => SCIADDR1, + SCIADDR2 => SCIADDR2, + SCIADDR3 => SCIADDR3, + SCIADDR4 => SCIADDR4, + SCIADDR5 => SCIADDR5, + SCIENAUX => SCIENAUX, + SCIENCH0 => SCIENCH0, + SCIENCH1 => SCIENCH1, + SCIENCH2 => SCIENCH2, + SCIENCH3 => SCIENCH3, + SCIRD => SCIRD, + SCISELAUX => SCISELAUX, + SCISELCH0 => SCISELCH0, + SCISELCH1 => SCISELCH1, + SCISELCH2 => SCISELCH2, + SCISELCH3 => SCISELCH3, + SCIWDATA0 => SCIWDATA0, + SCIWDATA1 => SCIWDATA1, + SCIWDATA2 => SCIWDATA2, + SCIWDATA3 => SCIWDATA3, + SCIWDATA4 => SCIWDATA4, + SCIWDATA5 => SCIWDATA5, + SCIWDATA6 => SCIWDATA6, + SCIWDATA7 => SCIWDATA7, + SCIWSTN => SCIWSTN, + HDOUTN0 => HDOUTN0, + HDOUTN1 => HDOUTN1, + HDOUTN2 => HDOUTN2, + HDOUTN3 => HDOUTN3, + HDOUTP0 => HDOUTP0, + HDOUTP1 => HDOUTP1, + HDOUTP2 => HDOUTP2, + HDOUTP3 => HDOUTP3, + COUT19 => COUT19, + COUT18 => COUT18, + COUT17 => COUT17, + COUT16 => COUT16, + COUT15 => COUT15, + COUT14 => COUT14, + COUT13 => COUT13, + COUT12 => COUT12, + COUT11 => COUT11, + COUT10 => COUT10, + COUT9 => COUT9, + COUT8 => COUT8, + COUT7 => COUT7, + COUT6 => COUT6, + COUT5 => COUT5, + COUT4 => COUT4, + COUT3 => COUT3, + COUT2 => COUT2, + COUT1 => COUT1, + COUT0 => COUT0, + FF_RX_D_0_0 => FF_RX_D_0_0, + FF_RX_D_0_1 => FF_RX_D_0_1, + FF_RX_D_0_2 => FF_RX_D_0_2, + FF_RX_D_0_3 => FF_RX_D_0_3, + FF_RX_D_0_4 => FF_RX_D_0_4, + FF_RX_D_0_5 => FF_RX_D_0_5, + FF_RX_D_0_6 => FF_RX_D_0_6, + FF_RX_D_0_7 => FF_RX_D_0_7, + FF_RX_D_0_8 => FF_RX_D_0_8, + FF_RX_D_0_9 => FF_RX_D_0_9, + FF_RX_D_0_10 => FF_RX_D_0_10, + FF_RX_D_0_11 => FF_RX_D_0_11, + FF_RX_D_0_12 => FF_RX_D_0_12, + FF_RX_D_0_13 => FF_RX_D_0_13, + FF_RX_D_0_14 => FF_RX_D_0_14, + FF_RX_D_0_15 => FF_RX_D_0_15, + FF_RX_D_0_16 => FF_RX_D_0_16, + FF_RX_D_0_17 => FF_RX_D_0_17, + FF_RX_D_0_18 => FF_RX_D_0_18, + FF_RX_D_0_19 => FF_RX_D_0_19, + FF_RX_D_0_20 => FF_RX_D_0_20, + FF_RX_D_0_21 => FF_RX_D_0_21, + FF_RX_D_0_22 => FF_RX_D_0_22, + FF_RX_D_0_23 => FF_RX_D_0_23, + FF_RX_D_1_0 => FF_RX_D_1_0, + FF_RX_D_1_1 => FF_RX_D_1_1, + FF_RX_D_1_2 => FF_RX_D_1_2, + FF_RX_D_1_3 => FF_RX_D_1_3, + FF_RX_D_1_4 => FF_RX_D_1_4, + FF_RX_D_1_5 => FF_RX_D_1_5, + FF_RX_D_1_6 => FF_RX_D_1_6, + FF_RX_D_1_7 => FF_RX_D_1_7, + FF_RX_D_1_8 => FF_RX_D_1_8, + FF_RX_D_1_9 => FF_RX_D_1_9, + FF_RX_D_1_10 => FF_RX_D_1_10, + FF_RX_D_1_11 => FF_RX_D_1_11, + FF_RX_D_1_12 => FF_RX_D_1_12, + FF_RX_D_1_13 => FF_RX_D_1_13, + FF_RX_D_1_14 => FF_RX_D_1_14, + FF_RX_D_1_15 => FF_RX_D_1_15, + FF_RX_D_1_16 => FF_RX_D_1_16, + FF_RX_D_1_17 => FF_RX_D_1_17, + FF_RX_D_1_18 => FF_RX_D_1_18, + FF_RX_D_1_19 => FF_RX_D_1_19, + FF_RX_D_1_20 => FF_RX_D_1_20, + FF_RX_D_1_21 => FF_RX_D_1_21, + FF_RX_D_1_22 => FF_RX_D_1_22, + FF_RX_D_1_23 => FF_RX_D_1_23, + FF_RX_D_2_0 => FF_RX_D_2_0, + FF_RX_D_2_1 => FF_RX_D_2_1, + FF_RX_D_2_2 => FF_RX_D_2_2, + FF_RX_D_2_3 => FF_RX_D_2_3, + FF_RX_D_2_4 => FF_RX_D_2_4, + FF_RX_D_2_5 => FF_RX_D_2_5, + FF_RX_D_2_6 => FF_RX_D_2_6, + FF_RX_D_2_7 => FF_RX_D_2_7, + FF_RX_D_2_8 => FF_RX_D_2_8, + FF_RX_D_2_9 => FF_RX_D_2_9, + FF_RX_D_2_10 => FF_RX_D_2_10, + FF_RX_D_2_11 => FF_RX_D_2_11, + FF_RX_D_2_12 => FF_RX_D_2_12, + FF_RX_D_2_13 => FF_RX_D_2_13, + FF_RX_D_2_14 => FF_RX_D_2_14, + FF_RX_D_2_15 => FF_RX_D_2_15, + FF_RX_D_2_16 => FF_RX_D_2_16, + FF_RX_D_2_17 => FF_RX_D_2_17, + FF_RX_D_2_18 => FF_RX_D_2_18, + FF_RX_D_2_19 => FF_RX_D_2_19, + FF_RX_D_2_20 => FF_RX_D_2_20, + FF_RX_D_2_21 => FF_RX_D_2_21, + FF_RX_D_2_22 => FF_RX_D_2_22, + FF_RX_D_2_23 => FF_RX_D_2_23, + FF_RX_D_3_0 => FF_RX_D_3_0, + FF_RX_D_3_1 => FF_RX_D_3_1, + FF_RX_D_3_2 => FF_RX_D_3_2, + FF_RX_D_3_3 => FF_RX_D_3_3, + FF_RX_D_3_4 => FF_RX_D_3_4, + FF_RX_D_3_5 => FF_RX_D_3_5, + FF_RX_D_3_6 => FF_RX_D_3_6, + FF_RX_D_3_7 => FF_RX_D_3_7, + FF_RX_D_3_8 => FF_RX_D_3_8, + FF_RX_D_3_9 => FF_RX_D_3_9, + FF_RX_D_3_10 => FF_RX_D_3_10, + FF_RX_D_3_11 => FF_RX_D_3_11, + FF_RX_D_3_12 => FF_RX_D_3_12, + FF_RX_D_3_13 => FF_RX_D_3_13, + FF_RX_D_3_14 => FF_RX_D_3_14, + FF_RX_D_3_15 => FF_RX_D_3_15, + FF_RX_D_3_16 => FF_RX_D_3_16, + FF_RX_D_3_17 => FF_RX_D_3_17, + FF_RX_D_3_18 => FF_RX_D_3_18, + FF_RX_D_3_19 => FF_RX_D_3_19, + FF_RX_D_3_20 => FF_RX_D_3_20, + FF_RX_D_3_21 => FF_RX_D_3_21, + FF_RX_D_3_22 => FF_RX_D_3_22, + FF_RX_D_3_23 => FF_RX_D_3_23, + FF_RX_F_CLK_0 => FF_RX_F_CLK_0, + FF_RX_F_CLK_1 => FF_RX_F_CLK_1, + FF_RX_F_CLK_2 => FF_RX_F_CLK_2, + FF_RX_F_CLK_3 => FF_RX_F_CLK_3, + FF_RX_H_CLK_0 => FF_RX_H_CLK_0, + FF_RX_H_CLK_1 => FF_RX_H_CLK_1, + FF_RX_H_CLK_2 => FF_RX_H_CLK_2, + FF_RX_H_CLK_3 => FF_RX_H_CLK_3, + FF_RX_Q_CLK_0 => FF_RX_Q_CLK_0, + FF_RX_Q_CLK_1 => FF_RX_Q_CLK_1, + FF_RX_Q_CLK_2 => FF_RX_Q_CLK_2, + FF_RX_Q_CLK_3 => FF_RX_Q_CLK_3, + FF_TX_F_CLK => FF_TX_F_CLK, + FF_TX_H_CLK => FF_TX_H_CLK, + FF_TX_Q_CLK => FF_TX_Q_CLK, + FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0, + FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1, + FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2, + FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3, + FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0, + FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1, + FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2, + FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3, + FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0, + FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1, + FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2, + FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3, + FFS_PCIE_CON_0 => FFS_PCIE_CON_0, + FFS_PCIE_CON_1 => FFS_PCIE_CON_1, + FFS_PCIE_CON_2 => FFS_PCIE_CON_2, + FFS_PCIE_CON_3 => FFS_PCIE_CON_3, + FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, + FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, + FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, + FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, + FFS_RLOS_LO_0 => FFS_RLOS_LO_0, + FFS_RLOS_LO_1 => FFS_RLOS_LO_1, + FFS_RLOS_LO_2 => FFS_RLOS_LO_2, + FFS_RLOS_LO_3 => FFS_RLOS_LO_3, + FFS_PLOL => FFS_PLOL, + FFS_RLOL_0 => FFS_RLOL_0, + FFS_RLOL_1 => FFS_RLOL_1, + FFS_RLOL_2 => FFS_RLOL_2, + FFS_RLOL_3 => FFS_RLOL_3, + FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0, + FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1, + FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2, + FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3, + FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0, + FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1, + FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2, + FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3, + OOB_OUT_0 => OOB_OUT_0, + OOB_OUT_1 => OOB_OUT_1, + OOB_OUT_2 => OOB_OUT_2, + OOB_OUT_3 => OOB_OUT_3, + REFCK2CORE => REFCK2CORE, + SCIINT => SCIINT, + SCIRDATA0 => SCIRDATA0, + SCIRDATA1 => SCIRDATA1, + SCIRDATA2 => SCIRDATA2, + SCIRDATA3 => SCIRDATA3, + SCIRDATA4 => SCIRDATA4, + SCIRDATA5 => SCIRDATA5, + SCIRDATA6 => SCIRDATA6, + SCIRDATA7 => SCIRDATA7 + ); + +end PCSC_arch; + +--synopsys translate_on + +--synopsys translate_off +library ECP2; +use ECP2.components.all; +--synopsys translate_on + +library IEEE, STD; +use IEEE.std_logic_1164.all; +use STD.TEXTIO.all; + +entity serdes_gbe_2 is + GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_2.txt"); + port ( + core_txrefclk : in std_logic; + core_rxrefclk : in std_logic; + hdinp2, hdinn2 : in std_logic; + hdoutp2, hdoutn2 : out std_logic; + ff_rxiclk_ch2, ff_txiclk_ch2, ff_ebrd_clk_2 : in std_logic; + ff_txdata_ch2 : in std_logic_vector (15 downto 0); + ff_rxdata_ch2 : out std_logic_vector (15 downto 0); + ff_tx_k_cntrl_ch2 : in std_logic_vector (1 downto 0); + ff_rx_k_cntrl_ch2 : out std_logic_vector (1 downto 0); + ff_rxfullclk_ch2 : out std_logic; + ff_rxhalfclk_ch2 : out std_logic; + ff_xmit_ch2 : in std_logic_vector (1 downto 0); + ff_correct_disp_ch2 : in std_logic_vector (1 downto 0); + ff_disp_err_ch2, ff_cv_ch2 : out std_logic_vector (1 downto 0); + ff_rx_even_ch2 : out std_logic_vector (1 downto 0); + ffc_rrst_ch2 : in std_logic; + ffc_lane_tx_rst_ch2 : in std_logic; + ffc_lane_rx_rst_ch2 : in std_logic; + ffc_txpwdnb_ch2 : in std_logic; + ffc_rxpwdnb_ch2 : in std_logic; + ffs_rlos_lo_ch2 : out std_logic; + ffs_ls_sync_status_ch2 : out std_logic; + ffs_cc_underrun_ch2 : out std_logic; + ffs_cc_overrun_ch2 : out std_logic; + ffs_txfbfifo_error_ch2 : out std_logic; + ffs_rxfbfifo_error_ch2 : out std_logic; + ffs_rlol_ch2 : out std_logic; + oob_out_ch2 : out std_logic; + ffc_macro_rst : in std_logic; + ffc_quad_rst : in std_logic; + ffc_trst : in std_logic; + ff_txfullclk : out std_logic; + ff_txhalfclk : out std_logic; + refck2core : out std_logic; + ffs_plol : out std_logic); + +end serdes_gbe_2; + +architecture serdes_gbe_2_arch of serdes_gbe_2 is + +component VLO +port ( + Z : out std_logic); +end component; + +component VHI +port ( + Z : out std_logic); +end component; +component PCSC +--synopsys translate_off +GENERIC( + CONFIG_FILE : String + ); +--synopsys translate_on +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_RX_Q_CLK_0 : out std_logic; + FF_RX_Q_CLK_1 : out std_logic; + FF_RX_Q_CLK_2 : out std_logic; + FF_RX_Q_CLK_3 : out std_logic; + FF_TX_F_CLK : out std_logic; + FF_TX_H_CLK : out std_logic; + FF_TX_Q_CLK : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + OOB_OUT_0 : out std_logic; + OOB_OUT_1 : out std_logic; + OOB_OUT_2 : out std_logic; + OOB_OUT_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic +); +end component; + attribute IS_ASB: string; + attribute IS_ASB of PCSC_INST : label is "ep5m00/data/ep5m00.acd"; + attribute CONFIG_FILE: string; + attribute CONFIG_FILE of PCSC_INST : label is USER_CONFIG_FILE; + attribute black_box_pad_pin: string; + attribute black_box_pad_pin of PCSC : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; + +signal fpsc_vlo : std_logic := '0'; +signal cin : std_logic_vector (11 downto 0) := "000000000000"; +signal cout : std_logic_vector (19 downto 0); + +begin + +vlo_inst : VLO port map(Z => fpsc_vlo); + +-- pcs_quad instance +PCSC_INST : PCSC +--synopsys translate_off + generic map (CONFIG_FILE => USER_CONFIG_FILE) +--synopsys translate_on +port map ( + FFC_CK_CORE_TX => core_txrefclk, + FFC_CK_CORE_RX => core_rxrefclk, + REFCLKP => fpsc_vlo, + REFCLKN => fpsc_vlo, + HDINP0 => fpsc_vlo, + HDINN0 => fpsc_vlo, + HDOUTP0 => open, + HDOUTN0 => open, + SCISELCH0 => fpsc_vlo, + SCIENCH0 => fpsc_vlo, + FF_RXI_CLK_0 => fpsc_vlo, + FF_TXI_CLK_0 => fpsc_vlo, + FF_EBRD_CLK_0 => fpsc_vlo, + FF_RX_F_CLK_0 => open, + FF_RX_H_CLK_0 => open, + FF_RX_Q_CLK_0 => open, + FF_TX_D_0_0 => fpsc_vlo, + FF_TX_D_0_1 => fpsc_vlo, + FF_TX_D_0_2 => fpsc_vlo, + FF_TX_D_0_3 => fpsc_vlo, + FF_TX_D_0_4 => fpsc_vlo, + FF_TX_D_0_5 => fpsc_vlo, + FF_TX_D_0_6 => fpsc_vlo, + FF_TX_D_0_7 => fpsc_vlo, + FF_TX_D_0_8 => fpsc_vlo, + FF_TX_D_0_9 => fpsc_vlo, + FF_TX_D_0_10 => fpsc_vlo, + FF_TX_D_0_11 => fpsc_vlo, + FF_TX_D_0_12 => fpsc_vlo, + FF_TX_D_0_13 => fpsc_vlo, + FF_TX_D_0_14 => fpsc_vlo, + FF_TX_D_0_15 => fpsc_vlo, + FF_TX_D_0_16 => fpsc_vlo, + FF_TX_D_0_17 => fpsc_vlo, + FF_TX_D_0_18 => fpsc_vlo, + FF_TX_D_0_19 => fpsc_vlo, + FF_TX_D_0_20 => fpsc_vlo, + FF_TX_D_0_21 => fpsc_vlo, + FF_TX_D_0_22 => fpsc_vlo, + FF_TX_D_0_23 => fpsc_vlo, + FF_RX_D_0_0 => open, + FF_RX_D_0_1 => open, + FF_RX_D_0_2 => open, + FF_RX_D_0_3 => open, + FF_RX_D_0_4 => open, + FF_RX_D_0_5 => open, + FF_RX_D_0_6 => open, + FF_RX_D_0_7 => open, + FF_RX_D_0_8 => open, + FF_RX_D_0_9 => open, + FF_RX_D_0_10 => open, + FF_RX_D_0_11 => open, + FF_RX_D_0_12 => open, + FF_RX_D_0_13 => open, + FF_RX_D_0_14 => open, + FF_RX_D_0_15 => open, + FF_RX_D_0_16 => open, + FF_RX_D_0_17 => open, + FF_RX_D_0_18 => open, + FF_RX_D_0_19 => open, + FF_RX_D_0_20 => open, + FF_RX_D_0_21 => open, + FF_RX_D_0_22 => open, + FF_RX_D_0_23 => open, + FFC_RRST_0 => fpsc_vlo, + FFC_SIGNAL_DETECT_0 => fpsc_vlo, + FFC_SB_PFIFO_LP_0 => fpsc_vlo, + FFC_SB_INV_RX_0 => fpsc_vlo, + FFC_PFIFO_CLR_0 => fpsc_vlo, + FFC_PCIE_CT_0 => fpsc_vlo, + FFC_PCI_DET_EN_0 => fpsc_vlo, + FFC_FB_LOOPBACK_0 => fpsc_vlo, + FFC_ENABLE_CGALIGN_0 => fpsc_vlo, + FFC_EI_EN_0 => fpsc_vlo, + FFC_LANE_TX_RST_0 => fpsc_vlo, + FFC_LANE_RX_RST_0 => fpsc_vlo, + FFC_TXPWDNB_0 => fpsc_vlo, + FFC_RXPWDNB_0 => fpsc_vlo, + FFS_RLOS_LO_0 => open, + FFS_PCIE_DONE_0 => open, + FFS_PCIE_CON_0 => open, + FFS_LS_SYNC_STATUS_0 => open, + FFS_CC_UNDERRUN_0 => open, + FFS_CC_OVERRUN_0 => open, + FFS_RLOL_0 => open, + FFS_RXFBFIFO_ERROR_0 => open, + FFS_TXFBFIFO_ERROR_0 => open, + OOB_OUT_0 => open, + HDINP1 => fpsc_vlo, + HDINN1 => fpsc_vlo, + HDOUTP1 => open, + HDOUTN1 => open, + SCISELCH1 => fpsc_vlo, + SCIENCH1 => fpsc_vlo, + FF_RXI_CLK_1 => fpsc_vlo, + FF_TXI_CLK_1 => fpsc_vlo, + FF_EBRD_CLK_1 => fpsc_vlo, + FF_RX_F_CLK_1 => open, + FF_RX_H_CLK_1 => open, + FF_RX_Q_CLK_1 => open, + FF_TX_D_1_0 => fpsc_vlo, + FF_TX_D_1_1 => fpsc_vlo, + FF_TX_D_1_2 => fpsc_vlo, + FF_TX_D_1_3 => fpsc_vlo, + FF_TX_D_1_4 => fpsc_vlo, + FF_TX_D_1_5 => fpsc_vlo, + FF_TX_D_1_6 => fpsc_vlo, + FF_TX_D_1_7 => fpsc_vlo, + FF_TX_D_1_8 => fpsc_vlo, + FF_TX_D_1_9 => fpsc_vlo, + FF_TX_D_1_10 => fpsc_vlo, + FF_TX_D_1_11 => fpsc_vlo, + FF_TX_D_1_12 => fpsc_vlo, + FF_TX_D_1_13 => fpsc_vlo, + FF_TX_D_1_14 => fpsc_vlo, + FF_TX_D_1_15 => fpsc_vlo, + FF_TX_D_1_16 => fpsc_vlo, + FF_TX_D_1_17 => fpsc_vlo, + FF_TX_D_1_18 => fpsc_vlo, + FF_TX_D_1_19 => fpsc_vlo, + FF_TX_D_1_20 => fpsc_vlo, + FF_TX_D_1_21 => fpsc_vlo, + FF_TX_D_1_22 => fpsc_vlo, + FF_TX_D_1_23 => fpsc_vlo, + FF_RX_D_1_0 => open, + FF_RX_D_1_1 => open, + FF_RX_D_1_2 => open, + FF_RX_D_1_3 => open, + FF_RX_D_1_4 => open, + FF_RX_D_1_5 => open, + FF_RX_D_1_6 => open, + FF_RX_D_1_7 => open, + FF_RX_D_1_8 => open, + FF_RX_D_1_9 => open, + FF_RX_D_1_10 => open, + FF_RX_D_1_11 => open, + FF_RX_D_1_12 => open, + FF_RX_D_1_13 => open, + FF_RX_D_1_14 => open, + FF_RX_D_1_15 => open, + FF_RX_D_1_16 => open, + FF_RX_D_1_17 => open, + FF_RX_D_1_18 => open, + FF_RX_D_1_19 => open, + FF_RX_D_1_20 => open, + FF_RX_D_1_21 => open, + FF_RX_D_1_22 => open, + FF_RX_D_1_23 => open, + FFC_RRST_1 => fpsc_vlo, + FFC_SIGNAL_DETECT_1 => fpsc_vlo, + FFC_SB_PFIFO_LP_1 => fpsc_vlo, + FFC_SB_INV_RX_1 => fpsc_vlo, + FFC_PFIFO_CLR_1 => fpsc_vlo, + FFC_PCIE_CT_1 => fpsc_vlo, + FFC_PCI_DET_EN_1 => fpsc_vlo, + FFC_FB_LOOPBACK_1 => fpsc_vlo, + FFC_ENABLE_CGALIGN_1 => fpsc_vlo, + FFC_EI_EN_1 => fpsc_vlo, + FFC_LANE_TX_RST_1 => fpsc_vlo, + FFC_LANE_RX_RST_1 => fpsc_vlo, + FFC_TXPWDNB_1 => fpsc_vlo, + FFC_RXPWDNB_1 => fpsc_vlo, + FFS_RLOS_LO_1 => open, + FFS_PCIE_DONE_1 => open, + FFS_PCIE_CON_1 => open, + FFS_LS_SYNC_STATUS_1 => open, + FFS_CC_UNDERRUN_1 => open, + FFS_CC_OVERRUN_1 => open, + FFS_RLOL_1 => open, + FFS_RXFBFIFO_ERROR_1 => open, + FFS_TXFBFIFO_ERROR_1 => open, + OOB_OUT_1 => open, + HDINP2 => hdinp2, + HDINN2 => hdinn2, + HDOUTP2 => hdoutp2, + HDOUTN2 => hdoutn2, + SCISELCH2 => fpsc_vlo, + SCIENCH2 => fpsc_vlo, + FF_RXI_CLK_2 => ff_rxiclk_ch2, + FF_TXI_CLK_2 => ff_txiclk_ch2, + FF_EBRD_CLK_2 => ff_ebrd_clk_2, + FF_RX_F_CLK_2 => ff_rxfullclk_ch2, + FF_RX_H_CLK_2 => ff_rxhalfclk_ch2, + FF_RX_Q_CLK_2 => open, + FF_TX_D_2_0 => ff_txdata_ch2(0), + FF_TX_D_2_1 => ff_txdata_ch2(1), + FF_TX_D_2_2 => ff_txdata_ch2(2), + FF_TX_D_2_3 => ff_txdata_ch2(3), + FF_TX_D_2_4 => ff_txdata_ch2(4), + FF_TX_D_2_5 => ff_txdata_ch2(5), + FF_TX_D_2_6 => ff_txdata_ch2(6), + FF_TX_D_2_7 => ff_txdata_ch2(7), + FF_TX_D_2_8 => ff_tx_k_cntrl_ch2(0), + FF_TX_D_2_9 => fpsc_vlo, + FF_TX_D_2_10 => ff_xmit_ch2(0), + FF_TX_D_2_11 => ff_correct_disp_ch2(0), + FF_TX_D_2_12 => ff_txdata_ch2(8), + FF_TX_D_2_13 => ff_txdata_ch2(9), + FF_TX_D_2_14 => ff_txdata_ch2(10), + FF_TX_D_2_15 => ff_txdata_ch2(11), + FF_TX_D_2_16 => ff_txdata_ch2(12), + FF_TX_D_2_17 => ff_txdata_ch2(13), + FF_TX_D_2_18 => ff_txdata_ch2(14), + FF_TX_D_2_19 => ff_txdata_ch2(15), + FF_TX_D_2_20 => ff_tx_k_cntrl_ch2(1), + FF_TX_D_2_21 => fpsc_vlo, + FF_TX_D_2_22 => ff_xmit_ch2(1), + FF_TX_D_2_23 => ff_correct_disp_ch2(1), + FF_RX_D_2_0 => ff_rxdata_ch2(0), + FF_RX_D_2_1 => ff_rxdata_ch2(1), + FF_RX_D_2_2 => ff_rxdata_ch2(2), + FF_RX_D_2_3 => ff_rxdata_ch2(3), + FF_RX_D_2_4 => ff_rxdata_ch2(4), + FF_RX_D_2_5 => ff_rxdata_ch2(5), + FF_RX_D_2_6 => ff_rxdata_ch2(6), + FF_RX_D_2_7 => ff_rxdata_ch2(7), + FF_RX_D_2_8 => ff_rx_k_cntrl_ch2(0), + FF_RX_D_2_9 => ff_disp_err_ch2(0), + FF_RX_D_2_10 => ff_cv_ch2(0), + FF_RX_D_2_11 => ff_rx_even_ch2(0), + FF_RX_D_2_12 => ff_rxdata_ch2(8), + FF_RX_D_2_13 => ff_rxdata_ch2(9), + FF_RX_D_2_14 => ff_rxdata_ch2(10), + FF_RX_D_2_15 => ff_rxdata_ch2(11), + FF_RX_D_2_16 => ff_rxdata_ch2(12), + FF_RX_D_2_17 => ff_rxdata_ch2(13), + FF_RX_D_2_18 => ff_rxdata_ch2(14), + FF_RX_D_2_19 => ff_rxdata_ch2(15), + FF_RX_D_2_20 => ff_rx_k_cntrl_ch2(1), + FF_RX_D_2_21 => ff_disp_err_ch2(1), + FF_RX_D_2_22 => ff_cv_ch2(1), + FF_RX_D_2_23 => ff_rx_even_ch2(1), + FFC_RRST_2 => ffc_rrst_ch2, + FFC_SIGNAL_DETECT_2 => fpsc_vlo, + FFC_ENABLE_CGALIGN_2 => fpsc_vlo, + FFC_SB_PFIFO_LP_2 => fpsc_vlo, + FFC_PFIFO_CLR_2 => fpsc_vlo, + FFC_FB_LOOPBACK_2 => fpsc_vlo, + FFC_SB_INV_RX_2 => fpsc_vlo, + FFC_PCIE_CT_2 => fpsc_vlo, + FFC_PCI_DET_EN_2 => fpsc_vlo, + FFS_PCIE_DONE_2 => open, + FFS_PCIE_CON_2 => open, + FFC_EI_EN_2 => fpsc_vlo, + FFC_LANE_TX_RST_2 => ffc_lane_tx_rst_ch2, + FFC_LANE_RX_RST_2 => ffc_lane_rx_rst_ch2, + FFC_TXPWDNB_2 => ffc_txpwdnb_ch2, + FFC_RXPWDNB_2 => ffc_rxpwdnb_ch2, + FFS_RLOS_LO_2 => ffs_rlos_lo_ch2, + FFS_LS_SYNC_STATUS_2 => ffs_ls_sync_status_ch2, + FFS_CC_UNDERRUN_2 => ffs_cc_underrun_ch2, + FFS_CC_OVERRUN_2 => ffs_cc_overrun_ch2, + FFS_RXFBFIFO_ERROR_2 => ffs_rxfbfifo_error_ch2, + FFS_TXFBFIFO_ERROR_2 => ffs_txfbfifo_error_ch2, + FFS_RLOL_2 => ffs_rlol_ch2, + OOB_OUT_2 => oob_out_ch2, + HDINP3 => fpsc_vlo, + HDINN3 => fpsc_vlo, + HDOUTP3 => open, + HDOUTN3 => open, + SCISELCH3 => fpsc_vlo, + SCIENCH3 => fpsc_vlo, + FF_RXI_CLK_3 => fpsc_vlo, + FF_TXI_CLK_3 => fpsc_vlo, + FF_EBRD_CLK_3 => fpsc_vlo, + FF_RX_F_CLK_3 => open, + FF_RX_H_CLK_3 => open, + FF_RX_Q_CLK_3 => open, + FF_TX_D_3_0 => fpsc_vlo, + FF_TX_D_3_1 => fpsc_vlo, + FF_TX_D_3_2 => fpsc_vlo, + FF_TX_D_3_3 => fpsc_vlo, + FF_TX_D_3_4 => fpsc_vlo, + FF_TX_D_3_5 => fpsc_vlo, + FF_TX_D_3_6 => fpsc_vlo, + FF_TX_D_3_7 => fpsc_vlo, + FF_TX_D_3_8 => fpsc_vlo, + FF_TX_D_3_9 => fpsc_vlo, + FF_TX_D_3_10 => fpsc_vlo, + FF_TX_D_3_11 => fpsc_vlo, + FF_TX_D_3_12 => fpsc_vlo, + FF_TX_D_3_13 => fpsc_vlo, + FF_TX_D_3_14 => fpsc_vlo, + FF_TX_D_3_15 => fpsc_vlo, + FF_TX_D_3_16 => fpsc_vlo, + FF_TX_D_3_17 => fpsc_vlo, + FF_TX_D_3_18 => fpsc_vlo, + FF_TX_D_3_19 => fpsc_vlo, + FF_TX_D_3_20 => fpsc_vlo, + FF_TX_D_3_21 => fpsc_vlo, + FF_TX_D_3_22 => fpsc_vlo, + FF_TX_D_3_23 => fpsc_vlo, + FF_RX_D_3_0 => open, + FF_RX_D_3_1 => open, + FF_RX_D_3_2 => open, + FF_RX_D_3_3 => open, + FF_RX_D_3_4 => open, + FF_RX_D_3_5 => open, + FF_RX_D_3_6 => open, + FF_RX_D_3_7 => open, + FF_RX_D_3_8 => open, + FF_RX_D_3_9 => open, + FF_RX_D_3_10 => open, + FF_RX_D_3_11 => open, + FF_RX_D_3_12 => open, + FF_RX_D_3_13 => open, + FF_RX_D_3_14 => open, + FF_RX_D_3_15 => open, + FF_RX_D_3_16 => open, + FF_RX_D_3_17 => open, + FF_RX_D_3_18 => open, + FF_RX_D_3_19 => open, + FF_RX_D_3_20 => open, + FF_RX_D_3_21 => open, + FF_RX_D_3_22 => open, + FF_RX_D_3_23 => open, + FFC_RRST_3 => fpsc_vlo, + FFC_SIGNAL_DETECT_3 => fpsc_vlo, + FFC_SB_PFIFO_LP_3 => fpsc_vlo, + FFC_SB_INV_RX_3 => fpsc_vlo, + FFC_PFIFO_CLR_3 => fpsc_vlo, + FFC_PCIE_CT_3 => fpsc_vlo, + FFC_PCI_DET_EN_3 => fpsc_vlo, + FFC_FB_LOOPBACK_3 => fpsc_vlo, + FFC_ENABLE_CGALIGN_3 => fpsc_vlo, + FFC_EI_EN_3 => fpsc_vlo, + FFC_LANE_TX_RST_3 => fpsc_vlo, + FFC_LANE_RX_RST_3 => fpsc_vlo, + FFC_TXPWDNB_3 => fpsc_vlo, + FFC_RXPWDNB_3 => fpsc_vlo, + FFS_RLOS_LO_3 => open, + FFS_PCIE_DONE_3 => open, + FFS_PCIE_CON_3 => open, + FFS_LS_SYNC_STATUS_3 => open, + FFS_CC_UNDERRUN_3 => open, + FFS_CC_OVERRUN_3 => open, + FFS_RLOL_3 => open, + FFS_RXFBFIFO_ERROR_3 => open, + FFS_TXFBFIFO_ERROR_3 => open, + OOB_OUT_3 => open, + SCIWDATA0 => fpsc_vlo, + SCIWDATA1 => fpsc_vlo, + SCIWDATA2 => fpsc_vlo, + SCIWDATA3 => fpsc_vlo, + SCIWDATA4 => fpsc_vlo, + SCIWDATA5 => fpsc_vlo, + SCIWDATA6 => fpsc_vlo, + SCIWDATA7 => fpsc_vlo, + SCIADDR0 => fpsc_vlo, + SCIADDR1 => fpsc_vlo, + SCIADDR2 => fpsc_vlo, + SCIADDR3 => fpsc_vlo, + SCIADDR4 => fpsc_vlo, + SCIADDR5 => fpsc_vlo, + SCIRDATA0 => open, + SCIRDATA1 => open, + SCIRDATA2 => open, + SCIRDATA3 => open, + SCIRDATA4 => open, + SCIRDATA5 => open, + SCIRDATA6 => open, + SCIRDATA7 => open, + SCIENAUX => fpsc_vlo, + SCISELAUX => fpsc_vlo, + SCIRD => fpsc_vlo, + SCIWSTN => fpsc_vlo, + CYAWSTN => fpsc_vlo, + SCIINT => open, + FFC_MACRO_RST => ffc_macro_rst, + FFC_QUAD_RST => ffc_quad_rst, + FFC_TRST => ffc_trst, + FF_TX_F_CLK => ff_txfullclk, + FF_TX_H_CLK => ff_txhalfclk, + FF_TX_Q_CLK => open, + REFCK2CORE => refck2core, + CIN0 => cin(0), + CIN1 => cin(1), + CIN2 => cin(2), + CIN3 => cin(3), + CIN4 => cin(4), + CIN5 => cin(5), + CIN6 => cin(6), + CIN7 => cin(7), + CIN8 => cin(8), + CIN9 => cin(9), + CIN10 => cin(10), + CIN11 => cin(11), + COUT0 => cout(0), + COUT1 => cout(1), + COUT2 => cout(2), + COUT3 => cout(3), + COUT4 => cout(4), + COUT5 => cout(5), + COUT6 => cout(6), + COUT7 => cout(7), + COUT8 => cout(8), + COUT9 => cout(9), + COUT10 => cout(10), + COUT11 => cout(11), + COUT12 => cout(12), + COUT13 => cout(13), + COUT14 => cout(14), + COUT15 => cout(15), + COUT16 => cout(16), + COUT17 => cout(17), + COUT18 => cout(18), + COUT19 => cout(19), + FFS_PLOL => ffs_plol); + +--synopsys translate_off +file_read : PROCESS +VARIABLE open_status : file_open_status; +FILE config : text; +BEGIN + file_open (open_status, config, USER_CONFIG_FILE, read_mode); + IF (open_status = name_error) THEN + report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" + severity ERROR; + END IF; + wait; +END PROCESS; +--synopsys translate_on + +end serdes_gbe_2_arch ; diff --git a/media_interfaces/ecp2m_sfp/serdes_gbe_all.jhd b/media_interfaces/ecp2m_sfp/serdes_gbe_all.jhd new file mode 100755 index 0000000..4e8e2d6 --- /dev/null +++ b/media_interfaces/ecp2m_sfp/serdes_gbe_all.jhd @@ -0,0 +1 @@ +MODULE serdes_gbe_2 diff --git a/media_interfaces/ecp2m_sfp/serdes_gbe_all.lpc b/media_interfaces/ecp2m_sfp/serdes_gbe_all.lpc new file mode 100755 index 0000000..65d2a8a --- /dev/null +++ b/media_interfaces/ecp2m_sfp/serdes_gbe_all.lpc @@ -0,0 +1,140 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PCS +CoreRevision=7.0 +ModuleName=serdes_gbe_2 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=07/30/2009 +Time=14:05:48 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Protocol=Quad +mode=Gigabit Ethernet +Channel0=SINGLE +Channel1=SINGLE +Channel2=SINGLE +Channel3=SINGLE +Rate0=None +Rate1=None +Rate2=None +Rate3=None +TxRefClk=CORE_TXREFCLK +RxRefClk=CORE_RXREFCLK +ClkRate=2.0 +ClkMult=20X +CalClkRate=100.0 +DataWidth=16 +FPGAClkRate=100.0 +TxRefClkCM=REFCLK +RxRefClk0CM=REFCLK +RxRefClk1CM=REFCLK +RxRefClk2CM=REFCLK +RxRefClk3CM=REFCLK +ClkRateH=1.0 +ClkMultH=20XH +CalClkRateH=100.0 +DataWidthH=8 +FPGAClkRateH=100.0 +VCh0=0 +VCh1=0 +VCh2=0 +VCh3=0 +PreCh0=DISABLE +PreCh1=DISABLE +PreCh2=DISABLE +PreCh3=DISABLE +TxCh0=50 +TxCh1=50 +TxCh2=50 +TxCh3=50 +EqCh0=DISABLE +EqCh1=DISABLE +EqCh2=DISABLE +EqCh3=DISABLE +RxTermCh0=50 +RxTermCh1=50 +RxTermCh2=50 +RxTermCh3=50 +RxCoupCh0=DC +RxCoupCh1=DC +RxCoupCh2=DC +RxCoupCh3=DC +Loss=0 +CDRLoss=0 +TxTerm=50 +TxCoup=AC +TxPllLoss=0 +TxInvCh0=NORMAL +TxInvCh1=NORMAL +TxInvCh2=NORMAL +TxInvCh3=NORMAL +RxInvCh0=NORMAL +RxInvCh1=NORMAL +RxInvCh2=NORMAL +RxInvCh3=NORMAL +RxModeCh0=NORMAL +RxModeCh1=NORMAL +RxModeCh2=NORMAL +RxModeCh3=NORMAL +Plus=1100000101 +Minus=0011111010 +Mask=1111111111 +Align=AUTO +CTCCh0=NORMAL +CTCCh1=NORMAL +CTCCh2=NORMAL +CTCCh3=NORMAL +CC_MATCH1=0000000000 +CC_MATCH2=0000000000 +CC_MATCH3=0110111100 +CC_MATCH4=0001010000 +MinIPG=3 +High=9 +Low=7 +CC_MATCH_MODE=MATCH_3_4 +RxDataCh0=FALSE +RxDataCh1=FALSE +RxDataCh2=FALSE +RxDataCh3=FALSE +AlignerCh0=FALSE +AlignerCh1=FALSE +AlignerCh2=FALSE +AlignerCh3=FALSE +DetectCh0=FALSE +DetectCh1=FALSE +DetectCh2=FALSE +DetectCh3=FALSE +ELSMCh0=FALSE +ELSMCh1=FALSE +ELSMCh2=FALSE +ELSMCh3=FALSE +_teidleCh0=FALSE +_teidleCh1=FALSE +_teidleCh2=FALSE +_teidleCh3=FALSE +Ports0=FALSE +rdoPorts0=Serial Loopback +Ports1=TRUE +Ports2=TRUE +Ports3=FALSE +Ports3_1=FALSE +Ports4=FALSE diff --git a/media_interfaces/ecp2m_sfp/serdes_gbe_all.pp b/media_interfaces/ecp2m_sfp/serdes_gbe_all.pp new file mode 100755 index 0000000..ee77855 --- /dev/null +++ b/media_interfaces/ecp2m_sfp/serdes_gbe_all.pp @@ -0,0 +1,95 @@ +#define _device_name "LFE2M100E" +#define _protocol_mode "Quad Based Protocol Mode" +#define _protocol "GIGE" +#define _ch0_mode "SINGLE" +#define _ch1_mode "SINGLE" +#define _ch2_mode "SINGLE" +#define _ch3_mode "SINGLE" +#define _pll_txsrc "CORE_TXREFCLK" +#define _pll_rxsrc "CORE_RXREFCLK" +#define _datarange "MEDHIGH" +#define _refclk_mult "20X" +#define _refclk_rate 100.0 +#define _data_width "16" +#define _fpgaintclk_rate 100.0 +#define _ch0_tdrv_amp "0" +#define _ch1_tdrv_amp "0" +#define _ch2_tdrv_amp "0" +#define _ch3_tdrv_amp "0" +#define _ch0_tx_pre "DISABLE" +#define _ch1_tx_pre "DISABLE" +#define _ch2_tx_pre "DISABLE" +#define _ch3_tx_pre "DISABLE" +#define _ch0_rterm_tx "50" +#define _ch1_rterm_tx "50" +#define _ch2_rterm_tx "50" +#define _ch3_rterm_tx "50" +#define _ch0_rx_eq "DISABLE" +#define _ch1_rx_eq "DISABLE" +#define _ch2_rx_eq "DISABLE" +#define _ch3_rx_eq "DISABLE" +#define _ch0_rterm_rx "50" +#define _ch1_rterm_rx "50" +#define _ch2_rterm_rx "50" +#define _ch3_rterm_rx "50" +#define _ch0_rx_dcc "DC" +#define _ch1_rx_dcc "DC" +#define _ch2_rx_dcc "DC" +#define _ch3_rx_dcc "DC" +#define _los_threshold "0" +#define _pll_term "50" +#define _pll_dcc "AC" +#define _pll_lol_set "0" +#define _ch0_tx_sb "NORMAL" +#define _ch1_tx_sb "NORMAL" +#define _ch2_tx_sb "NORMAL" +#define _ch3_tx_sb "NORMAL" +#define _ch0_rx_sb "NORMAL" +#define _ch1_rx_sb "NORMAL" +#define _ch2_rx_sb "NORMAL" +#define _ch3_rx_sb "NORMAL" +#define _ch0_8b10b "NORMAL" +#define _ch1_8b10b "NORMAL" +#define _ch2_8b10b "NORMAL" +#define _ch3_8b10b "NORMAL" +#define _comma_a "1100000101" +#define _comma_b "0011111010" +#define _comma_m "1111111111" +#define _comma_align "AUTO" +#define _ch0_ctc_byp "NORMAL" +#define _ch1_ctc_byp "NORMAL" +#define _ch2_ctc_byp "NORMAL" +#define _ch3_ctc_byp "NORMAL" +#define _cc_match1 "0000000000" +#define _cc_match2 "0000000000" +#define _cc_match3 "0110111100" +#define _cc_match4 "0001010000" +#define _cc_match_mode "MATCH_3_4" +#define _cc_min_ipg "3" +#define _cchmark "9" +#define _cclmark "7" +#define _ch0_ird "FALSE" +#define _ch1_ird "FALSE" +#define _ch2_ird "FALSE" +#define _ch3_ird "FALSE" +#define _ch0_elsm "FALSE" +#define _ch1_elsm "FALSE" +#define _ch2_elsm "FALSE" +#define _ch3_elsm "FALSE" +#define _ch0_teidle "FALSE" +#define _ch1_teidle "FALSE" +#define _ch2_teidle "FALSE" +#define _ch3_teidle "FALSE" +#define _loopback "FALSE" +#define _lbtype "Serial Loopback" +#define _refck2core "TRUE" +#define _pllqclkports "FALSE" +#define _sci_ports "FALSE" +#define _sci_int_port "FALSE" +#define _errsports "TRUE" + +#define _circuit_name serdes_gbe_2 +#define _lang vhdl + +#include +#include diff --git a/media_interfaces/ecp2m_sfp/serdes_gbe_all.readme b/media_interfaces/ecp2m_sfp/serdes_gbe_all.readme new file mode 100755 index 0000000..79ef381 --- /dev/null +++ b/media_interfaces/ecp2m_sfp/serdes_gbe_all.readme @@ -0,0 +1,337 @@ + + TOOL: orcapp + DATE: 19-MAR-2008 13:11:51 + TITLE: Lattice Semiconductor Corporation + MODULE: serdes_gbe_2 + DESIGN: serdes_gbe_2 + FILENAME: serdes_gbe_2.readme + PROJECT: Unknown + VERSION: 2.0 + This file is auto generated by the ispLEVER + + +NOTE: This readme file has been provided to instantiate the interface +netlist. Since this template contains synthesis attributes for precision that +are crucial to the design flow, we recommend that you use this +template in your FPGA design. +entity chip is +port ( + +-- Add your FPGA design top level I/Os here + + +-- ASIC side pins for PCSA. These pins must exist for the +-- PCS core. + refclkp : in std_logic; + refclkn : in std_logic; + hdinp0 : in std_logic; + hdinn0 : in std_logic; + hdinp1 : in std_logic; + hdinn1 : in std_logic; + hdinp2 : in std_logic; + hdinn2 : in std_logic; + hdinp3 : in std_logic; + hdinn3 : in std_logic; + + hdoutp0 : out std_logic; + hdoutn0 : out std_logic; + hdoutp1 : out std_logic; + hdoutn1 : out std_logic; + hdoutp2 : out std_logic; + hdoutn2 : out std_logic; + hdoutp3 : out std_logic; + hdoutn3 : out std_logic; + + +); +end chip; + +architecture chip_arch of chip is + +-- This defines all the high-speed ports. You may have to remove +-- some of them depending on your design. +attribute nopad : string; +attribute nopad of + refclkp, refclkn, + hdinp0, hdinn0, hdinp1, hdinn1, + hdinp2, hdinn2, hdinp3, hdinn3, + hdoutp0, hdoutn0, hdoutp1, hdoutn1, + hdoutp2, hdoutn2, hdoutp3, hdoutn3 : signal is "true"; + + COMPONENT serdes_gbe_2 + PORT( + core_txrefclk : IN std_logic; + core_rxrefclk : IN std_logic; + hdinp0 : IN std_logic; + hdinn0 : IN std_logic; + ff_rxiclk_ch0 : IN std_logic; + ff_txiclk_ch0 : IN std_logic; + ff_ebrd_clk_0 : IN std_logic; + ff_txdata_ch0 : IN std_logic_vector(15 downto 0); + ff_tx_k_cntrl_ch0 : IN std_logic_vector(1 downto 0); + ff_xmit_ch0 : IN std_logic_vector(1 downto 0); + ff_correct_disp_ch0 : IN std_logic_vector(1 downto 0); + ffc_rrst_ch0 : IN std_logic; + ffc_lane_tx_rst_ch0 : IN std_logic; + ffc_lane_rx_rst_ch0 : IN std_logic; + ffc_txpwdnb_ch0 : IN std_logic; + ffc_rxpwdnb_ch0 : IN std_logic; + hdinp1 : IN std_logic; + hdinn1 : IN std_logic; + ff_rxiclk_ch1 : IN std_logic; + ff_txiclk_ch1 : IN std_logic; + ff_ebrd_clk_1 : IN std_logic; + ff_txdata_ch1 : IN std_logic_vector(15 downto 0); + ff_tx_k_cntrl_ch1 : IN std_logic_vector(1 downto 0); + ff_xmit_ch1 : IN std_logic_vector(1 downto 0); + ff_correct_disp_ch1 : IN std_logic_vector(1 downto 0); + ffc_rrst_ch1 : IN std_logic; + ffc_lane_tx_rst_ch1 : IN std_logic; + ffc_lane_rx_rst_ch1 : IN std_logic; + ffc_txpwdnb_ch1 : IN std_logic; + ffc_rxpwdnb_ch1 : IN std_logic; + hdinp2 : IN std_logic; + hdinn2 : IN std_logic; + ff_rxiclk_ch2 : IN std_logic; + ff_txiclk_ch2 : IN std_logic; + ff_ebrd_clk_2 : IN std_logic; + ff_txdata_ch2 : IN std_logic_vector(15 downto 0); + ff_tx_k_cntrl_ch2 : IN std_logic_vector(1 downto 0); + ff_xmit_ch2 : IN std_logic_vector(1 downto 0); + ff_correct_disp_ch2 : IN std_logic_vector(1 downto 0); + ffc_rrst_ch2 : IN std_logic; + ffc_lane_tx_rst_ch2 : IN std_logic; + ffc_lane_rx_rst_ch2 : IN std_logic; + ffc_txpwdnb_ch2 : IN std_logic; + ffc_rxpwdnb_ch2 : IN std_logic; + hdinp3 : IN std_logic; + hdinn3 : IN std_logic; + ff_rxiclk_ch3 : IN std_logic; + ff_txiclk_ch3 : IN std_logic; + ff_ebrd_clk_3 : IN std_logic; + ff_txdata_ch3 : IN std_logic_vector(15 downto 0); + ff_tx_k_cntrl_ch3 : IN std_logic_vector(1 downto 0); + ff_xmit_ch3 : IN std_logic_vector(1 downto 0); + ff_correct_disp_ch3 : IN std_logic_vector(1 downto 0); + ffc_rrst_ch3 : IN std_logic; + ffc_lane_tx_rst_ch3 : IN std_logic; + ffc_lane_rx_rst_ch3 : IN std_logic; + ffc_txpwdnb_ch3 : IN std_logic; + ffc_rxpwdnb_ch3 : IN std_logic; + ffc_macro_rst : IN std_logic; + ffc_quad_rst : IN std_logic; + ffc_trst : IN std_logic; + hdoutp0 : OUT std_logic; + hdoutn0 : OUT std_logic; + ff_rxdata_ch0 : OUT std_logic_vector(15 downto 0); + ff_rx_k_cntrl_ch0 : OUT std_logic_vector(1 downto 0); + ff_rxfullclk_ch0 : OUT std_logic; + ff_rxhalfclk_ch0 : OUT std_logic; + ff_disp_err_ch0 : OUT std_logic_vector(1 downto 0); + ff_cv_ch0 : OUT std_logic_vector(1 downto 0); + ff_rx_even_ch0 : OUT std_logic_vector(1 downto 0); + ffs_rlos_lo_ch0 : OUT std_logic; + ffs_ls_sync_status_ch0 : OUT std_logic; + ffs_cc_underrun_ch0 : OUT std_logic; + ffs_cc_overrun_ch0 : OUT std_logic; + ffs_txfbfifo_error_ch0 : OUT std_logic; + ffs_rxfbfifo_error_ch0 : OUT std_logic; + ffs_rlol_ch0 : OUT std_logic; + oob_out_ch0 : OUT std_logic; + hdoutp1 : OUT std_logic; + hdoutn1 : OUT std_logic; + ff_rxdata_ch1 : OUT std_logic_vector(15 downto 0); + ff_rx_k_cntrl_ch1 : OUT std_logic_vector(1 downto 0); + ff_rxfullclk_ch1 : OUT std_logic; + ff_rxhalfclk_ch1 : OUT std_logic; + ff_disp_err_ch1 : OUT std_logic_vector(1 downto 0); + ff_cv_ch1 : OUT std_logic_vector(1 downto 0); + ff_rx_even_ch1 : OUT std_logic_vector(1 downto 0); + ffs_rlos_lo_ch1 : OUT std_logic; + ffs_ls_sync_status_ch1 : OUT std_logic; + ffs_cc_underrun_ch1 : OUT std_logic; + ffs_cc_overrun_ch1 : OUT std_logic; + ffs_txfbfifo_error_ch1 : OUT std_logic; + ffs_rxfbfifo_error_ch1 : OUT std_logic; + ffs_rlol_ch1 : OUT std_logic; + oob_out_ch1 : OUT std_logic; + hdoutp2 : OUT std_logic; + hdoutn2 : OUT std_logic; + ff_rxdata_ch2 : OUT std_logic_vector(15 downto 0); + ff_rx_k_cntrl_ch2 : OUT std_logic_vector(1 downto 0); + ff_rxfullclk_ch2 : OUT std_logic; + ff_rxhalfclk_ch2 : OUT std_logic; + ff_disp_err_ch2 : OUT std_logic_vector(1 downto 0); + ff_cv_ch2 : OUT std_logic_vector(1 downto 0); + ff_rx_even_ch2 : OUT std_logic_vector(1 downto 0); + ffs_rlos_lo_ch2 : OUT std_logic; + ffs_ls_sync_status_ch2 : OUT std_logic; + ffs_cc_underrun_ch2 : OUT std_logic; + ffs_cc_overrun_ch2 : OUT std_logic; + ffs_txfbfifo_error_ch2 : OUT std_logic; + ffs_rxfbfifo_error_ch2 : OUT std_logic; + ffs_rlol_ch2 : OUT std_logic; + oob_out_ch2 : OUT std_logic; + hdoutp3 : OUT std_logic; + hdoutn3 : OUT std_logic; + ff_rxdata_ch3 : OUT std_logic_vector(15 downto 0); + ff_rx_k_cntrl_ch3 : OUT std_logic_vector(1 downto 0); + ff_rxfullclk_ch3 : OUT std_logic; + ff_rxhalfclk_ch3 : OUT std_logic; + ff_disp_err_ch3 : OUT std_logic_vector(1 downto 0); + ff_cv_ch3 : OUT std_logic_vector(1 downto 0); + ff_rx_even_ch3 : OUT std_logic_vector(1 downto 0); + ffs_rlos_lo_ch3 : OUT std_logic; + ffs_ls_sync_status_ch3 : OUT std_logic; + ffs_cc_underrun_ch3 : OUT std_logic; + ffs_cc_overrun_ch3 : OUT std_logic; + ffs_txfbfifo_error_ch3 : OUT std_logic; + ffs_rxfbfifo_error_ch3 : OUT std_logic; + ffs_rlol_ch3 : OUT std_logic; + oob_out_ch3 : OUT std_logic; + ff_txfullclk : OUT std_logic; + ff_txhalfclk : OUT std_logic; + refck2core : OUT std_logic; + ffs_plol : OUT std_logic + ); + END COMPONENT; + + + + uut: serdes_gbe_2 PORT MAP( + core_txrefclk => core_txrefclk, + core_rxrefclk => core_rxrefclk, + hdinp0 => hdinp0, + hdinn0 => hdinn0, + hdoutp0 => hdoutp0, + hdoutn0 => hdoutn0, + ff_rxiclk_ch0 => ff_rxiclk_ch0, + ff_txiclk_ch0 => ff_txiclk_ch0, + ff_ebrd_clk_0 => ff_ebrd_clk_0, + ff_txdata_ch0 => ff_txdata_ch0, + ff_rxdata_ch0 => ff_rxdata_ch0, + ff_tx_k_cntrl_ch0 => ff_tx_k_cntrl_ch0, + ff_rx_k_cntrl_ch0 => ff_rx_k_cntrl_ch0, + ff_rxfullclk_ch0 => ff_rxfullclk_ch0, + ff_rxhalfclk_ch0 => ff_rxhalfclk_ch0, + ff_xmit_ch0 => ff_xmit_ch0, + ff_correct_disp_ch0 => ff_correct_disp_ch0, + ff_disp_err_ch0 => ff_disp_err_ch0, + ff_cv_ch0 => ff_cv_ch0, + ff_rx_even_ch0 => ff_rx_even_ch0, + ffc_rrst_ch0 => ffc_rrst_ch0, + ffc_lane_tx_rst_ch0 => ffc_lane_tx_rst_ch0, + ffc_lane_rx_rst_ch0 => ffc_lane_rx_rst_ch0, + ffc_txpwdnb_ch0 => ffc_txpwdnb_ch0, + ffc_rxpwdnb_ch0 => ffc_rxpwdnb_ch0, + ffs_rlos_lo_ch0 => ffs_rlos_lo_ch0, + ffs_ls_sync_status_ch0 => ffs_ls_sync_status_ch0, + ffs_cc_underrun_ch0 => ffs_cc_underrun_ch0, + ffs_cc_overrun_ch0 => ffs_cc_overrun_ch0, + ffs_txfbfifo_error_ch0 => ffs_txfbfifo_error_ch0, + ffs_rxfbfifo_error_ch0 => ffs_rxfbfifo_error_ch0, + ffs_rlol_ch0 => ffs_rlol_ch0, + oob_out_ch0 => oob_out_ch0, + hdinp1 => hdinp1, + hdinn1 => hdinn1, + hdoutp1 => hdoutp1, + hdoutn1 => hdoutn1, + ff_rxiclk_ch1 => ff_rxiclk_ch1, + ff_txiclk_ch1 => ff_txiclk_ch1, + ff_ebrd_clk_1 => ff_ebrd_clk_1, + ff_txdata_ch1 => ff_txdata_ch1, + ff_rxdata_ch1 => ff_rxdata_ch1, + ff_tx_k_cntrl_ch1 => ff_tx_k_cntrl_ch1, + ff_rx_k_cntrl_ch1 => ff_rx_k_cntrl_ch1, + ff_rxfullclk_ch1 => ff_rxfullclk_ch1, + ff_rxhalfclk_ch1 => ff_rxhalfclk_ch1, + ff_xmit_ch1 => ff_xmit_ch1, + ff_correct_disp_ch1 => ff_correct_disp_ch1, + ff_disp_err_ch1 => ff_disp_err_ch1, + ff_cv_ch1 => ff_cv_ch1, + ff_rx_even_ch1 => ff_rx_even_ch1, + ffc_rrst_ch1 => ffc_rrst_ch1, + ffc_lane_tx_rst_ch1 => ffc_lane_tx_rst_ch1, + ffc_lane_rx_rst_ch1 => ffc_lane_rx_rst_ch1, + ffc_txpwdnb_ch1 => ffc_txpwdnb_ch1, + ffc_rxpwdnb_ch1 => ffc_rxpwdnb_ch1, + ffs_rlos_lo_ch1 => ffs_rlos_lo_ch1, + ffs_ls_sync_status_ch1 => ffs_ls_sync_status_ch1, + ffs_cc_underrun_ch1 => ffs_cc_underrun_ch1, + ffs_cc_overrun_ch1 => ffs_cc_overrun_ch1, + ffs_txfbfifo_error_ch1 => ffs_txfbfifo_error_ch1, + ffs_rxfbfifo_error_ch1 => ffs_rxfbfifo_error_ch1, + ffs_rlol_ch1 => ffs_rlol_ch1, + oob_out_ch1 => oob_out_ch1, + hdinp2 => hdinp2, + hdinn2 => hdinn2, + hdoutp2 => hdoutp2, + hdoutn2 => hdoutn2, + ff_rxiclk_ch2 => ff_rxiclk_ch2, + ff_txiclk_ch2 => ff_txiclk_ch2, + ff_ebrd_clk_2 => ff_ebrd_clk_2, + ff_txdata_ch2 => ff_txdata_ch2, + ff_rxdata_ch2 => ff_rxdata_ch2, + ff_tx_k_cntrl_ch2 => ff_tx_k_cntrl_ch2, + ff_rx_k_cntrl_ch2 => ff_rx_k_cntrl_ch2, + ff_rxfullclk_ch2 => ff_rxfullclk_ch2, + ff_rxhalfclk_ch2 => ff_rxhalfclk_ch2, + ff_xmit_ch2 => ff_xmit_ch2, + ff_correct_disp_ch2 => ff_correct_disp_ch2, + ff_disp_err_ch2 => ff_disp_err_ch2, + ff_cv_ch2 => ff_cv_ch2, + ff_rx_even_ch2 => ff_rx_even_ch2, + ffc_rrst_ch2 => ffc_rrst_ch2, + ffc_lane_tx_rst_ch2 => ffc_lane_tx_rst_ch2, + ffc_lane_rx_rst_ch2 => ffc_lane_rx_rst_ch2, + ffc_txpwdnb_ch2 => ffc_txpwdnb_ch2, + ffc_rxpwdnb_ch2 => ffc_rxpwdnb_ch2, + ffs_rlos_lo_ch2 => ffs_rlos_lo_ch2, + ffs_ls_sync_status_ch2 => ffs_ls_sync_status_ch2, + ffs_cc_underrun_ch2 => ffs_cc_underrun_ch2, + ffs_cc_overrun_ch2 => ffs_cc_overrun_ch2, + ffs_txfbfifo_error_ch2 => ffs_txfbfifo_error_ch2, + ffs_rxfbfifo_error_ch2 => ffs_rxfbfifo_error_ch2, + ffs_rlol_ch2 => ffs_rlol_ch2, + oob_out_ch2 => oob_out_ch2, + hdinp3 => hdinp3, + hdinn3 => hdinn3, + hdoutp3 => hdoutp3, + hdoutn3 => hdoutn3, + ff_rxiclk_ch3 => ff_rxiclk_ch3, + ff_txiclk_ch3 => ff_txiclk_ch3, + ff_ebrd_clk_3 => ff_ebrd_clk_3, + ff_txdata_ch3 => ff_txdata_ch3, + ff_rxdata_ch3 => ff_rxdata_ch3, + ff_tx_k_cntrl_ch3 => ff_tx_k_cntrl_ch3, + ff_rx_k_cntrl_ch3 => ff_rx_k_cntrl_ch3, + ff_rxfullclk_ch3 => ff_rxfullclk_ch3, + ff_rxhalfclk_ch3 => ff_rxhalfclk_ch3, + ff_xmit_ch3 => ff_xmit_ch3, + ff_correct_disp_ch3 => ff_correct_disp_ch3, + ff_disp_err_ch3 => ff_disp_err_ch3, + ff_cv_ch3 => ff_cv_ch3, + ff_rx_even_ch3 => ff_rx_even_ch3, + ffc_rrst_ch3 => ffc_rrst_ch3, + ffc_lane_tx_rst_ch3 => ffc_lane_tx_rst_ch3, + ffc_lane_rx_rst_ch3 => ffc_lane_rx_rst_ch3, + ffc_txpwdnb_ch3 => ffc_txpwdnb_ch3, + ffc_rxpwdnb_ch3 => ffc_rxpwdnb_ch3, + ffs_rlos_lo_ch3 => ffs_rlos_lo_ch3, + ffs_ls_sync_status_ch3 => ffs_ls_sync_status_ch3, + ffs_cc_underrun_ch3 => ffs_cc_underrun_ch3, + ffs_cc_overrun_ch3 => ffs_cc_overrun_ch3, + ffs_txfbfifo_error_ch3 => ffs_txfbfifo_error_ch3, + ffs_rxfbfifo_error_ch3 => ffs_rxfbfifo_error_ch3, + ffs_rlol_ch3 => ffs_rlol_ch3, + oob_out_ch3 => oob_out_ch3, + ffc_macro_rst => ffc_macro_rst, + ffc_quad_rst => ffc_quad_rst, + ffc_trst => ffc_trst, + ff_txfullclk => ff_txfullclk, + ff_txhalfclk => ff_txhalfclk, + refck2core => refck2core, + ffs_plol => ffs_plol + ); + + diff --git a/media_interfaces/ecp2m_sfp/serdes_gbe_all.tft b/media_interfaces/ecp2m_sfp/serdes_gbe_all.tft new file mode 100755 index 0000000..8a55292 --- /dev/null +++ b/media_interfaces/ecp2m_sfp/serdes_gbe_all.tft @@ -0,0 +1,98 @@ +@set suppresnewline=on@ + +@comment --------------------------------------------------------------------- @ +@comment Template-drive TFI generator @ +@comment Template for TFI generation. @ +@comment --------------------------------------------------------------------- @ + +@set suppresnewline=off@ + TOOL: orcapp + DATE: 19-MAR-2008 13:11:51 + TITLE: %title% + MODULE: %module% + DESIGN: %module% + FILENAME: %filename% + PROJECT: %project% + VERSION: %ver% + This file is auto generated by the ispLEVER +@set suppresnewline=on@ + +@cr@ +@cr@ + +@set sigdelim=@ + +NOTE: This readme file has been provided to instantiate the interface@cr@ +netlist. Since this template contains synthesis attributes for precision that@cr@ +are crucial to the design flow, we recommend that you use this@cr@ +template in your FPGA design.@cr@ +entity chip is@cr@ +port (@cr@ +@cr@ +-- Add your FPGA design top level I/Os here@cr@ +@cr@ +@cr@ +-- ASIC side pins for PCSA. These pins must exist for the@cr@ +-- PCS core.@cr@ + refclkp : in std_logic;@cr@ + refclkn : in std_logic;@cr@ + hdinp0 : in std_logic;@cr@ + hdinn0 : in std_logic;@cr@ + hdinp1 : in std_logic;@cr@ + hdinn1 : in std_logic;@cr@ + hdinp2 : in std_logic;@cr@ + hdinn2 : in std_logic;@cr@ + hdinp3 : in std_logic;@cr@ + hdinn3 : in std_logic;@cr@ +@cr@ + hdoutp0 : out std_logic;@cr@ + hdoutn0 : out std_logic;@cr@ + hdoutp1 : out std_logic;@cr@ + hdoutn1 : out std_logic;@cr@ + hdoutp2 : out std_logic;@cr@ + hdoutn2 : out std_logic;@cr@ + hdoutp3 : out std_logic;@cr@ + hdoutn3 : out std_logic;@cr@ +@cr@ +@cr@ +);@cr@ +end chip;@cr@ +@cr@ +architecture chip_arch of chip is@cr@ +@cr@ +-- This defines all the high-speed ports. You may have to remove@cr@ +-- some of them depending on your design.@cr@ +attribute nopad : string;@cr@ +attribute nopad of@cr@ + refclkp, refclkn,@cr@ + hdinp0, hdinn0, hdinp1, hdinn1,@cr@ + hdinp2, hdinn2, hdinp3, hdinn3,@cr@ + hdoutp0, hdoutn0, hdoutp1, hdoutn1,@cr@ + hdoutp2, hdoutn2, hdoutp3, hdoutn3 : signal is "true";@cr@ + +@cr@ +@tab@COMPONENT %module% +@set sigdelim=@ +@cr@@tab@PORT( +@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@ +@ifhas oport=*@ @comment if the design has any output ports... @ + @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@ + @set sigdelim=;@ + @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@ +@endif@ +@ifnhas oport=*@ @comment we need an "else in this language! @ + @set sigdelim=;@ + @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@ +@endif@ +@cr@@tab@@tab@);@cr@ +@tab@END COMPONENT;@cr@@cr@ +@comment Now do a signal declaration for each port @ + +@cr@@cr@ +@comment do the component instantiation @ +@set sigdelim=,@ +@tab@uut: %module% PORT MAP( +@iterate@%port% +@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@ +@cr@@tab@);@cr@@cr@ +@set suppresnewline=off@ diff --git a/media_interfaces/ecp2m_sfp/serdes_gbe_all.txt b/media_interfaces/ecp2m_sfp/serdes_gbe_all.txt new file mode 100755 index 0000000..0901b37 --- /dev/null +++ b/media_interfaces/ecp2m_sfp/serdes_gbe_all.txt @@ -0,0 +1,91 @@ + +# This file is used by the simulation model as well as the ispLEVER bitstream +# generation process to automatically initialize the PCSC quad to the mode +# selected in the IPexpress. This file is expected to be modified by the +# end user to adjust the PCSC quad to the final design requirements. + +DEVICE_NAME "LFE2M100E" +PROTOCOL "GIGE" +CH0_MODE "SINGLE" +CH1_MODE "SINGLE" +CH2_MODE "SINGLE" +CH3_MODE "SINGLE" +PLL_SRC "CORE_TXREFCLK" +DATARANGE "MEDHIGH" +CH0_CDR_SRC "CORE_RXREFCLK" +CH1_CDR_SRC "CORE_RXREFCLK" +CH2_CDR_SRC "CORE_RXREFCLK" +CH3_CDR_SRC "CORE_RXREFCLK" +CH0_DATA_WIDTH "16" +CH1_DATA_WIDTH "16" +CH2_DATA_WIDTH "16" +CH3_DATA_WIDTH "16" +CH0_REFCK_MULT "20X" +CH1_REFCK_MULT "20X" +CH2_REFCK_MULT "20X" +CH3_REFCK_MULT "20X" +#REFCLK_RATE 100.0 +#FPGAINTCLK_RATE 100.0 +CH0_TDRV_AMP "0" +CH1_TDRV_AMP "0" +CH2_TDRV_AMP "0" +CH3_TDRV_AMP "0" +CH0_TX_PRE "DISABLE" +CH1_TX_PRE "DISABLE" +CH2_TX_PRE "DISABLE" +CH3_TX_PRE "DISABLE" +CH0_RTERM_TX "50" +CH1_RTERM_TX "50" +CH2_RTERM_TX "50" +CH3_RTERM_TX "50" +CH0_RX_EQ "DISABLE" +CH1_RX_EQ "DISABLE" +CH2_RX_EQ "DISABLE" +CH3_RX_EQ "DISABLE" +CH0_RTERM_RX "50" +CH1_RTERM_RX "50" +CH2_RTERM_RX "50" +CH3_RTERM_RX "50" +CH0_RX_DCC "DC" +CH1_RX_DCC "DC" +CH2_RX_DCC "DC" +CH3_RX_DCC "DC" +LOS_THRESHOLD "0" +PLL_TERM "50" +PLL_DCC "AC" +PLL_LOL_SET "0" +CH0_TX_SB "NORMAL" +CH1_TX_SB "NORMAL" +CH2_TX_SB "NORMAL" +CH3_TX_SB "NORMAL" +CH0_RX_SB "NORMAL" +CH1_RX_SB "NORMAL" +CH2_RX_SB "NORMAL" +CH3_RX_SB "NORMAL" +CH0_8B10B "NORMAL" +CH1_8B10B "NORMAL" +CH2_8B10B "NORMAL" +CH3_8B10B "NORMAL" +COMMA_A "1100000101" +COMMA_B "0011111010" +COMMA_M "1111111111" +CH0_COMMA_ALIGN "AUTO" +CH1_COMMA_ALIGN "AUTO" +CH2_COMMA_ALIGN "AUTO" +CH3_COMMA_ALIGN "AUTO" +CH0_CTC_BYP "NORMAL" +CH1_CTC_BYP "NORMAL" +CH2_CTC_BYP "NORMAL" +CH3_CTC_BYP "NORMAL" +CC_MATCH1 "0000000000" +CC_MATCH2 "0000000000" +CC_MATCH3 "0110111100" +CC_MATCH4 "0001010000" +CC_MATCH_MODE "MATCH_3_4" +CC_MIN_IPG "3" +CCHMARK "9" +CCLMARK "7" +OS_REFCK2CORE "1" +OS_PLLQCLKPORTS "0" +OS_INT_ALL "0" + diff --git a/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd b/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd new file mode 100755 index 0000000..fbd4315 --- /dev/null +++ b/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd @@ -0,0 +1,2266 @@ + + +--synopsys translate_off + +library pcsc_work; +use pcsc_work.all; +library IEEE; +use IEEE.std_logic_1164.all; + +entity PCSC is +GENERIC( + CONFIG_FILE : String := "serdes_gbe_2.txt" + ); +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_RX_Q_CLK_0 : out std_logic; + FF_RX_Q_CLK_1 : out std_logic; + FF_RX_Q_CLK_2 : out std_logic; + FF_RX_Q_CLK_3 : out std_logic; + FF_TX_F_CLK : out std_logic; + FF_TX_H_CLK : out std_logic; + FF_TX_Q_CLK : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + OOB_OUT_0 : out std_logic; + OOB_OUT_1 : out std_logic; + OOB_OUT_2 : out std_logic; + OOB_OUT_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic +); + +end PCSC; + +architecture PCSC_arch of PCSC is + +component PCSC_sim +GENERIC( + CONFIG_FILE : String + ); +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_RX_Q_CLK_0 : out std_logic; + FF_RX_Q_CLK_1 : out std_logic; + FF_RX_Q_CLK_2 : out std_logic; + FF_RX_Q_CLK_3 : out std_logic; + FF_TX_F_CLK : out std_logic; + FF_TX_H_CLK : out std_logic; + FF_TX_Q_CLK : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + OOB_OUT_0 : out std_logic; + OOB_OUT_1 : out std_logic; + OOB_OUT_2 : out std_logic; + OOB_OUT_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic +); +end component; + +begin + +PCSC_sim_inst : PCSC_sim +generic map ( + CONFIG_FILE => CONFIG_FILE) +port map ( + HDINN0 => HDINN0, + HDINN1 => HDINN1, + HDINN2 => HDINN2, + HDINN3 => HDINN3, + HDINP0 => HDINP0, + HDINP1 => HDINP1, + HDINP2 => HDINP2, + HDINP3 => HDINP3, + REFCLKN => REFCLKN, + REFCLKP => REFCLKP, + CIN11 => CIN11, + CIN10 => CIN10, + CIN9 => CIN9, + CIN8 => CIN8, + CIN7 => CIN7, + CIN6 => CIN6, + CIN5 => CIN5, + CIN4 => CIN4, + CIN3 => CIN3, + CIN2 => CIN2, + CIN1 => CIN1, + CIN0 => CIN0, + CYAWSTN => CYAWSTN, + FF_EBRD_CLK_3 => FF_EBRD_CLK_3, + FF_EBRD_CLK_2 => FF_EBRD_CLK_2, + FF_EBRD_CLK_1 => FF_EBRD_CLK_1, + FF_EBRD_CLK_0 => FF_EBRD_CLK_0, + FF_RXI_CLK_3 => FF_RXI_CLK_3, + FF_RXI_CLK_2 => FF_RXI_CLK_2, + FF_RXI_CLK_1 => FF_RXI_CLK_1, + FF_RXI_CLK_0 => FF_RXI_CLK_0, + + FF_TX_D_0_0 => FF_TX_D_0_0, + FF_TX_D_0_1 => FF_TX_D_0_1, + FF_TX_D_0_2 => FF_TX_D_0_2, + FF_TX_D_0_3 => FF_TX_D_0_3, + FF_TX_D_0_4 => FF_TX_D_0_4, + FF_TX_D_0_5 => FF_TX_D_0_5, + FF_TX_D_0_6 => FF_TX_D_0_6, + FF_TX_D_0_7 => FF_TX_D_0_7, + FF_TX_D_0_8 => FF_TX_D_0_8, + FF_TX_D_0_9 => FF_TX_D_0_9, + FF_TX_D_0_10 => FF_TX_D_0_10, + FF_TX_D_0_11 => FF_TX_D_0_11, + FF_TX_D_0_12 => FF_TX_D_0_12, + FF_TX_D_0_13 => FF_TX_D_0_13, + FF_TX_D_0_14 => FF_TX_D_0_14, + FF_TX_D_0_15 => FF_TX_D_0_15, + FF_TX_D_0_16 => FF_TX_D_0_16, + FF_TX_D_0_17 => FF_TX_D_0_17, + FF_TX_D_0_18 => FF_TX_D_0_18, + FF_TX_D_0_19 => FF_TX_D_0_19, + FF_TX_D_0_20 => FF_TX_D_0_20, + FF_TX_D_0_21 => FF_TX_D_0_21, + FF_TX_D_0_22 => FF_TX_D_0_22, + FF_TX_D_0_23 => FF_TX_D_0_23, + FF_TX_D_1_0 => FF_TX_D_1_0, + FF_TX_D_1_1 => FF_TX_D_1_1, + FF_TX_D_1_2 => FF_TX_D_1_2, + FF_TX_D_1_3 => FF_TX_D_1_3, + FF_TX_D_1_4 => FF_TX_D_1_4, + FF_TX_D_1_5 => FF_TX_D_1_5, + FF_TX_D_1_6 => FF_TX_D_1_6, + FF_TX_D_1_7 => FF_TX_D_1_7, + FF_TX_D_1_8 => FF_TX_D_1_8, + FF_TX_D_1_9 => FF_TX_D_1_9, + FF_TX_D_1_10 => FF_TX_D_1_10, + FF_TX_D_1_11 => FF_TX_D_1_11, + FF_TX_D_1_12 => FF_TX_D_1_12, + FF_TX_D_1_13 => FF_TX_D_1_13, + FF_TX_D_1_14 => FF_TX_D_1_14, + FF_TX_D_1_15 => FF_TX_D_1_15, + FF_TX_D_1_16 => FF_TX_D_1_16, + FF_TX_D_1_17 => FF_TX_D_1_17, + FF_TX_D_1_18 => FF_TX_D_1_18, + FF_TX_D_1_19 => FF_TX_D_1_19, + FF_TX_D_1_20 => FF_TX_D_1_20, + FF_TX_D_1_21 => FF_TX_D_1_21, + FF_TX_D_1_22 => FF_TX_D_1_22, + FF_TX_D_1_23 => FF_TX_D_1_23, + FF_TX_D_2_0 => FF_TX_D_2_0, + FF_TX_D_2_1 => FF_TX_D_2_1, + FF_TX_D_2_2 => FF_TX_D_2_2, + FF_TX_D_2_3 => FF_TX_D_2_3, + FF_TX_D_2_4 => FF_TX_D_2_4, + FF_TX_D_2_5 => FF_TX_D_2_5, + FF_TX_D_2_6 => FF_TX_D_2_6, + FF_TX_D_2_7 => FF_TX_D_2_7, + FF_TX_D_2_8 => FF_TX_D_2_8, + FF_TX_D_2_9 => FF_TX_D_2_9, + FF_TX_D_2_10 => FF_TX_D_2_10, + FF_TX_D_2_11 => FF_TX_D_2_11, + FF_TX_D_2_12 => FF_TX_D_2_12, + FF_TX_D_2_13 => FF_TX_D_2_13, + FF_TX_D_2_14 => FF_TX_D_2_14, + FF_TX_D_2_15 => FF_TX_D_2_15, + FF_TX_D_2_16 => FF_TX_D_2_16, + FF_TX_D_2_17 => FF_TX_D_2_17, + FF_TX_D_2_18 => FF_TX_D_2_18, + FF_TX_D_2_19 => FF_TX_D_2_19, + FF_TX_D_2_20 => FF_TX_D_2_20, + FF_TX_D_2_21 => FF_TX_D_2_21, + FF_TX_D_2_22 => FF_TX_D_2_22, + FF_TX_D_2_23 => FF_TX_D_2_23, + FF_TX_D_3_0 => FF_TX_D_3_0, + FF_TX_D_3_1 => FF_TX_D_3_1, + FF_TX_D_3_2 => FF_TX_D_3_2, + FF_TX_D_3_3 => FF_TX_D_3_3, + FF_TX_D_3_4 => FF_TX_D_3_4, + FF_TX_D_3_5 => FF_TX_D_3_5, + FF_TX_D_3_6 => FF_TX_D_3_6, + FF_TX_D_3_7 => FF_TX_D_3_7, + FF_TX_D_3_8 => FF_TX_D_3_8, + FF_TX_D_3_9 => FF_TX_D_3_9, + FF_TX_D_3_10 => FF_TX_D_3_10, + FF_TX_D_3_11 => FF_TX_D_3_11, + FF_TX_D_3_12 => FF_TX_D_3_12, + FF_TX_D_3_13 => FF_TX_D_3_13, + FF_TX_D_3_14 => FF_TX_D_3_14, + FF_TX_D_3_15 => FF_TX_D_3_15, + FF_TX_D_3_16 => FF_TX_D_3_16, + FF_TX_D_3_17 => FF_TX_D_3_17, + FF_TX_D_3_18 => FF_TX_D_3_18, + FF_TX_D_3_19 => FF_TX_D_3_19, + FF_TX_D_3_20 => FF_TX_D_3_20, + FF_TX_D_3_21 => FF_TX_D_3_21, + FF_TX_D_3_22 => FF_TX_D_3_22, + FF_TX_D_3_23 => FF_TX_D_3_23, + FF_TXI_CLK_0 => FF_TXI_CLK_0, + FF_TXI_CLK_1 => FF_TXI_CLK_1, + FF_TXI_CLK_2 => FF_TXI_CLK_2, + FF_TXI_CLK_3 => FF_TXI_CLK_3, + FFC_CK_CORE_RX => FFC_CK_CORE_RX, + FFC_CK_CORE_TX => FFC_CK_CORE_TX, + FFC_EI_EN_0 => FFC_EI_EN_0, + FFC_EI_EN_1 => FFC_EI_EN_1, + FFC_EI_EN_2 => FFC_EI_EN_2, + FFC_EI_EN_3 => FFC_EI_EN_3, + FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0, + FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1, + FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2, + FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3, + FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0, + FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1, + FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2, + FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3, + FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0, + FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1, + FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2, + FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3, + FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0, + FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1, + FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2, + FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3, + FFC_MACRO_RST => FFC_MACRO_RST, + FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0, + FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1, + FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2, + FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3, + FFC_PCIE_CT_0 => FFC_PCIE_CT_0, + FFC_PCIE_CT_1 => FFC_PCIE_CT_1, + FFC_PCIE_CT_2 => FFC_PCIE_CT_2, + FFC_PCIE_CT_3 => FFC_PCIE_CT_3, + FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0, + FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1, + FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2, + FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3, + FFC_QUAD_RST => FFC_QUAD_RST, + FFC_RRST_0 => FFC_RRST_0, + FFC_RRST_1 => FFC_RRST_1, + FFC_RRST_2 => FFC_RRST_2, + FFC_RRST_3 => FFC_RRST_3, + FFC_RXPWDNB_0 => FFC_RXPWDNB_0, + FFC_RXPWDNB_1 => FFC_RXPWDNB_1, + FFC_RXPWDNB_2 => FFC_RXPWDNB_2, + FFC_RXPWDNB_3 => FFC_RXPWDNB_3, + FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, + FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, + FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, + FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, + FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0, + FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1, + FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2, + FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3, + FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0, + FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1, + FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2, + FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3, + FFC_TRST => FFC_TRST, + FFC_TXPWDNB_0 => FFC_TXPWDNB_0, + FFC_TXPWDNB_1 => FFC_TXPWDNB_1, + FFC_TXPWDNB_2 => FFC_TXPWDNB_2, + FFC_TXPWDNB_3 => FFC_TXPWDNB_3, + SCIADDR0 => SCIADDR0, + SCIADDR1 => SCIADDR1, + SCIADDR2 => SCIADDR2, + SCIADDR3 => SCIADDR3, + SCIADDR4 => SCIADDR4, + SCIADDR5 => SCIADDR5, + SCIENAUX => SCIENAUX, + SCIENCH0 => SCIENCH0, + SCIENCH1 => SCIENCH1, + SCIENCH2 => SCIENCH2, + SCIENCH3 => SCIENCH3, + SCIRD => SCIRD, + SCISELAUX => SCISELAUX, + SCISELCH0 => SCISELCH0, + SCISELCH1 => SCISELCH1, + SCISELCH2 => SCISELCH2, + SCISELCH3 => SCISELCH3, + SCIWDATA0 => SCIWDATA0, + SCIWDATA1 => SCIWDATA1, + SCIWDATA2 => SCIWDATA2, + SCIWDATA3 => SCIWDATA3, + SCIWDATA4 => SCIWDATA4, + SCIWDATA5 => SCIWDATA5, + SCIWDATA6 => SCIWDATA6, + SCIWDATA7 => SCIWDATA7, + SCIWSTN => SCIWSTN, + HDOUTN0 => HDOUTN0, + HDOUTN1 => HDOUTN1, + HDOUTN2 => HDOUTN2, + HDOUTN3 => HDOUTN3, + HDOUTP0 => HDOUTP0, + HDOUTP1 => HDOUTP1, + HDOUTP2 => HDOUTP2, + HDOUTP3 => HDOUTP3, + COUT19 => COUT19, + COUT18 => COUT18, + COUT17 => COUT17, + COUT16 => COUT16, + COUT15 => COUT15, + COUT14 => COUT14, + COUT13 => COUT13, + COUT12 => COUT12, + COUT11 => COUT11, + COUT10 => COUT10, + COUT9 => COUT9, + COUT8 => COUT8, + COUT7 => COUT7, + COUT6 => COUT6, + COUT5 => COUT5, + COUT4 => COUT4, + COUT3 => COUT3, + COUT2 => COUT2, + COUT1 => COUT1, + COUT0 => COUT0, + FF_RX_D_0_0 => FF_RX_D_0_0, + FF_RX_D_0_1 => FF_RX_D_0_1, + FF_RX_D_0_2 => FF_RX_D_0_2, + FF_RX_D_0_3 => FF_RX_D_0_3, + FF_RX_D_0_4 => FF_RX_D_0_4, + FF_RX_D_0_5 => FF_RX_D_0_5, + FF_RX_D_0_6 => FF_RX_D_0_6, + FF_RX_D_0_7 => FF_RX_D_0_7, + FF_RX_D_0_8 => FF_RX_D_0_8, + FF_RX_D_0_9 => FF_RX_D_0_9, + FF_RX_D_0_10 => FF_RX_D_0_10, + FF_RX_D_0_11 => FF_RX_D_0_11, + FF_RX_D_0_12 => FF_RX_D_0_12, + FF_RX_D_0_13 => FF_RX_D_0_13, + FF_RX_D_0_14 => FF_RX_D_0_14, + FF_RX_D_0_15 => FF_RX_D_0_15, + FF_RX_D_0_16 => FF_RX_D_0_16, + FF_RX_D_0_17 => FF_RX_D_0_17, + FF_RX_D_0_18 => FF_RX_D_0_18, + FF_RX_D_0_19 => FF_RX_D_0_19, + FF_RX_D_0_20 => FF_RX_D_0_20, + FF_RX_D_0_21 => FF_RX_D_0_21, + FF_RX_D_0_22 => FF_RX_D_0_22, + FF_RX_D_0_23 => FF_RX_D_0_23, + FF_RX_D_1_0 => FF_RX_D_1_0, + FF_RX_D_1_1 => FF_RX_D_1_1, + FF_RX_D_1_2 => FF_RX_D_1_2, + FF_RX_D_1_3 => FF_RX_D_1_3, + FF_RX_D_1_4 => FF_RX_D_1_4, + FF_RX_D_1_5 => FF_RX_D_1_5, + FF_RX_D_1_6 => FF_RX_D_1_6, + FF_RX_D_1_7 => FF_RX_D_1_7, + FF_RX_D_1_8 => FF_RX_D_1_8, + FF_RX_D_1_9 => FF_RX_D_1_9, + FF_RX_D_1_10 => FF_RX_D_1_10, + FF_RX_D_1_11 => FF_RX_D_1_11, + FF_RX_D_1_12 => FF_RX_D_1_12, + FF_RX_D_1_13 => FF_RX_D_1_13, + FF_RX_D_1_14 => FF_RX_D_1_14, + FF_RX_D_1_15 => FF_RX_D_1_15, + FF_RX_D_1_16 => FF_RX_D_1_16, + FF_RX_D_1_17 => FF_RX_D_1_17, + FF_RX_D_1_18 => FF_RX_D_1_18, + FF_RX_D_1_19 => FF_RX_D_1_19, + FF_RX_D_1_20 => FF_RX_D_1_20, + FF_RX_D_1_21 => FF_RX_D_1_21, + FF_RX_D_1_22 => FF_RX_D_1_22, + FF_RX_D_1_23 => FF_RX_D_1_23, + FF_RX_D_2_0 => FF_RX_D_2_0, + FF_RX_D_2_1 => FF_RX_D_2_1, + FF_RX_D_2_2 => FF_RX_D_2_2, + FF_RX_D_2_3 => FF_RX_D_2_3, + FF_RX_D_2_4 => FF_RX_D_2_4, + FF_RX_D_2_5 => FF_RX_D_2_5, + FF_RX_D_2_6 => FF_RX_D_2_6, + FF_RX_D_2_7 => FF_RX_D_2_7, + FF_RX_D_2_8 => FF_RX_D_2_8, + FF_RX_D_2_9 => FF_RX_D_2_9, + FF_RX_D_2_10 => FF_RX_D_2_10, + FF_RX_D_2_11 => FF_RX_D_2_11, + FF_RX_D_2_12 => FF_RX_D_2_12, + FF_RX_D_2_13 => FF_RX_D_2_13, + FF_RX_D_2_14 => FF_RX_D_2_14, + FF_RX_D_2_15 => FF_RX_D_2_15, + FF_RX_D_2_16 => FF_RX_D_2_16, + FF_RX_D_2_17 => FF_RX_D_2_17, + FF_RX_D_2_18 => FF_RX_D_2_18, + FF_RX_D_2_19 => FF_RX_D_2_19, + FF_RX_D_2_20 => FF_RX_D_2_20, + FF_RX_D_2_21 => FF_RX_D_2_21, + FF_RX_D_2_22 => FF_RX_D_2_22, + FF_RX_D_2_23 => FF_RX_D_2_23, + FF_RX_D_3_0 => FF_RX_D_3_0, + FF_RX_D_3_1 => FF_RX_D_3_1, + FF_RX_D_3_2 => FF_RX_D_3_2, + FF_RX_D_3_3 => FF_RX_D_3_3, + FF_RX_D_3_4 => FF_RX_D_3_4, + FF_RX_D_3_5 => FF_RX_D_3_5, + FF_RX_D_3_6 => FF_RX_D_3_6, + FF_RX_D_3_7 => FF_RX_D_3_7, + FF_RX_D_3_8 => FF_RX_D_3_8, + FF_RX_D_3_9 => FF_RX_D_3_9, + FF_RX_D_3_10 => FF_RX_D_3_10, + FF_RX_D_3_11 => FF_RX_D_3_11, + FF_RX_D_3_12 => FF_RX_D_3_12, + FF_RX_D_3_13 => FF_RX_D_3_13, + FF_RX_D_3_14 => FF_RX_D_3_14, + FF_RX_D_3_15 => FF_RX_D_3_15, + FF_RX_D_3_16 => FF_RX_D_3_16, + FF_RX_D_3_17 => FF_RX_D_3_17, + FF_RX_D_3_18 => FF_RX_D_3_18, + FF_RX_D_3_19 => FF_RX_D_3_19, + FF_RX_D_3_20 => FF_RX_D_3_20, + FF_RX_D_3_21 => FF_RX_D_3_21, + FF_RX_D_3_22 => FF_RX_D_3_22, + FF_RX_D_3_23 => FF_RX_D_3_23, + FF_RX_F_CLK_0 => FF_RX_F_CLK_0, + FF_RX_F_CLK_1 => FF_RX_F_CLK_1, + FF_RX_F_CLK_2 => FF_RX_F_CLK_2, + FF_RX_F_CLK_3 => FF_RX_F_CLK_3, + FF_RX_H_CLK_0 => FF_RX_H_CLK_0, + FF_RX_H_CLK_1 => FF_RX_H_CLK_1, + FF_RX_H_CLK_2 => FF_RX_H_CLK_2, + FF_RX_H_CLK_3 => FF_RX_H_CLK_3, + FF_RX_Q_CLK_0 => FF_RX_Q_CLK_0, + FF_RX_Q_CLK_1 => FF_RX_Q_CLK_1, + FF_RX_Q_CLK_2 => FF_RX_Q_CLK_2, + FF_RX_Q_CLK_3 => FF_RX_Q_CLK_3, + FF_TX_F_CLK => FF_TX_F_CLK, + FF_TX_H_CLK => FF_TX_H_CLK, + FF_TX_Q_CLK => FF_TX_Q_CLK, + FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0, + FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1, + FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2, + FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3, + FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0, + FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1, + FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2, + FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3, + FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0, + FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1, + FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2, + FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3, + FFS_PCIE_CON_0 => FFS_PCIE_CON_0, + FFS_PCIE_CON_1 => FFS_PCIE_CON_1, + FFS_PCIE_CON_2 => FFS_PCIE_CON_2, + FFS_PCIE_CON_3 => FFS_PCIE_CON_3, + FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, + FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, + FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, + FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, + FFS_RLOS_LO_0 => FFS_RLOS_LO_0, + FFS_RLOS_LO_1 => FFS_RLOS_LO_1, + FFS_RLOS_LO_2 => FFS_RLOS_LO_2, + FFS_RLOS_LO_3 => FFS_RLOS_LO_3, + FFS_PLOL => FFS_PLOL, + FFS_RLOL_0 => FFS_RLOL_0, + FFS_RLOL_1 => FFS_RLOL_1, + FFS_RLOL_2 => FFS_RLOL_2, + FFS_RLOL_3 => FFS_RLOL_3, + FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0, + FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1, + FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2, + FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3, + FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0, + FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1, + FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2, + FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3, + OOB_OUT_0 => OOB_OUT_0, + OOB_OUT_1 => OOB_OUT_1, + OOB_OUT_2 => OOB_OUT_2, + OOB_OUT_3 => OOB_OUT_3, + REFCK2CORE => REFCK2CORE, + SCIINT => SCIINT, + SCIRDATA0 => SCIRDATA0, + SCIRDATA1 => SCIRDATA1, + SCIRDATA2 => SCIRDATA2, + SCIRDATA3 => SCIRDATA3, + SCIRDATA4 => SCIRDATA4, + SCIRDATA5 => SCIRDATA5, + SCIRDATA6 => SCIRDATA6, + SCIRDATA7 => SCIRDATA7 + ); + +end PCSC_arch; + +--synopsys translate_on + +--synopsys translate_off +library ECP2; +use ECP2.components.all; +--synopsys translate_on + +library IEEE, STD; +use IEEE.std_logic_1164.all; +use STD.TEXTIO.all; + +entity serdes_gbe_2 is + GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_2.txt"); + port ( + core_txrefclk : in std_logic; + core_rxrefclk : in std_logic; + hdinp0, hdinn0 : in std_logic; + hdoutp0, hdoutn0 : out std_logic; + ff_rxiclk_ch0, ff_txiclk_ch0, ff_ebrd_clk_0 : in std_logic; + ff_txdata_ch0 : in std_logic_vector (15 downto 0); + ff_rxdata_ch0 : out std_logic_vector (15 downto 0); + ff_tx_k_cntrl_ch0 : in std_logic_vector (1 downto 0); + ff_rx_k_cntrl_ch0 : out std_logic_vector (1 downto 0); + ff_rxfullclk_ch0 : out std_logic; + ff_rxhalfclk_ch0 : out std_logic; + ff_xmit_ch0 : in std_logic_vector (1 downto 0); + ff_correct_disp_ch0 : in std_logic_vector (1 downto 0); + ff_disp_err_ch0, ff_cv_ch0 : out std_logic_vector (1 downto 0); + ff_rx_even_ch0 : out std_logic_vector (1 downto 0); + ffc_rrst_ch0 : in std_logic; + ffc_lane_tx_rst_ch0 : in std_logic; + ffc_lane_rx_rst_ch0 : in std_logic; + ffc_txpwdnb_ch0 : in std_logic; + ffc_rxpwdnb_ch0 : in std_logic; + ffs_rlos_lo_ch0 : out std_logic; + ffs_ls_sync_status_ch0 : out std_logic; + ffs_cc_underrun_ch0 : out std_logic; + ffs_cc_overrun_ch0 : out std_logic; + ffs_txfbfifo_error_ch0 : out std_logic; + ffs_rxfbfifo_error_ch0 : out std_logic; + ffs_rlol_ch0 : out std_logic; + oob_out_ch0 : out std_logic; + hdinp1, hdinn1 : in std_logic; + hdoutp1, hdoutn1 : out std_logic; + ff_rxiclk_ch1, ff_txiclk_ch1, ff_ebrd_clk_1 : in std_logic; + ff_txdata_ch1 : in std_logic_vector (15 downto 0); + ff_rxdata_ch1 : out std_logic_vector (15 downto 0); + ff_tx_k_cntrl_ch1 : in std_logic_vector (1 downto 0); + ff_rx_k_cntrl_ch1 : out std_logic_vector (1 downto 0); + ff_rxfullclk_ch1 : out std_logic; + ff_rxhalfclk_ch1 : out std_logic; + ff_xmit_ch1 : in std_logic_vector (1 downto 0); + ff_correct_disp_ch1 : in std_logic_vector (1 downto 0); + ff_disp_err_ch1, ff_cv_ch1 : out std_logic_vector (1 downto 0); + ff_rx_even_ch1 : out std_logic_vector (1 downto 0); + ffc_rrst_ch1 : in std_logic; + ffc_lane_tx_rst_ch1 : in std_logic; + ffc_lane_rx_rst_ch1 : in std_logic; + ffc_txpwdnb_ch1 : in std_logic; + ffc_rxpwdnb_ch1 : in std_logic; + ffs_rlos_lo_ch1 : out std_logic; + ffs_ls_sync_status_ch1 : out std_logic; + ffs_cc_underrun_ch1 : out std_logic; + ffs_cc_overrun_ch1 : out std_logic; + ffs_txfbfifo_error_ch1 : out std_logic; + ffs_rxfbfifo_error_ch1 : out std_logic; + ffs_rlol_ch1 : out std_logic; + oob_out_ch1 : out std_logic; + hdinp2, hdinn2 : in std_logic; + hdoutp2, hdoutn2 : out std_logic; + ff_rxiclk_ch2, ff_txiclk_ch2, ff_ebrd_clk_2 : in std_logic; + ff_txdata_ch2 : in std_logic_vector (15 downto 0); + ff_rxdata_ch2 : out std_logic_vector (15 downto 0); + ff_tx_k_cntrl_ch2 : in std_logic_vector (1 downto 0); + ff_rx_k_cntrl_ch2 : out std_logic_vector (1 downto 0); + ff_rxfullclk_ch2 : out std_logic; + ff_rxhalfclk_ch2 : out std_logic; + ff_xmit_ch2 : in std_logic_vector (1 downto 0); + ff_correct_disp_ch2 : in std_logic_vector (1 downto 0); + ff_disp_err_ch2, ff_cv_ch2 : out std_logic_vector (1 downto 0); + ff_rx_even_ch2 : out std_logic_vector (1 downto 0); + ffc_rrst_ch2 : in std_logic; + ffc_lane_tx_rst_ch2 : in std_logic; + ffc_lane_rx_rst_ch2 : in std_logic; + ffc_txpwdnb_ch2 : in std_logic; + ffc_rxpwdnb_ch2 : in std_logic; + ffs_rlos_lo_ch2 : out std_logic; + ffs_ls_sync_status_ch2 : out std_logic; + ffs_cc_underrun_ch2 : out std_logic; + ffs_cc_overrun_ch2 : out std_logic; + ffs_txfbfifo_error_ch2 : out std_logic; + ffs_rxfbfifo_error_ch2 : out std_logic; + ffs_rlol_ch2 : out std_logic; + oob_out_ch2 : out std_logic; + hdinp3, hdinn3 : in std_logic; + hdoutp3, hdoutn3 : out std_logic; + ff_rxiclk_ch3, ff_txiclk_ch3, ff_ebrd_clk_3 : in std_logic; + ff_txdata_ch3 : in std_logic_vector (15 downto 0); + ff_rxdata_ch3 : out std_logic_vector (15 downto 0); + ff_tx_k_cntrl_ch3 : in std_logic_vector (1 downto 0); + ff_rx_k_cntrl_ch3 : out std_logic_vector (1 downto 0); + ff_rxfullclk_ch3 : out std_logic; + ff_rxhalfclk_ch3 : out std_logic; + ff_xmit_ch3 : in std_logic_vector (1 downto 0); + ff_correct_disp_ch3 : in std_logic_vector (1 downto 0); + ff_disp_err_ch3, ff_cv_ch3 : out std_logic_vector (1 downto 0); + ff_rx_even_ch3 : out std_logic_vector (1 downto 0); + ffc_rrst_ch3 : in std_logic; + ffc_lane_tx_rst_ch3 : in std_logic; + ffc_lane_rx_rst_ch3 : in std_logic; + ffc_txpwdnb_ch3 : in std_logic; + ffc_rxpwdnb_ch3 : in std_logic; + ffs_rlos_lo_ch3 : out std_logic; + ffs_ls_sync_status_ch3 : out std_logic; + ffs_cc_underrun_ch3 : out std_logic; + ffs_cc_overrun_ch3 : out std_logic; + ffs_txfbfifo_error_ch3 : out std_logic; + ffs_rxfbfifo_error_ch3 : out std_logic; + ffs_rlol_ch3 : out std_logic; + oob_out_ch3 : out std_logic; + ffc_macro_rst : in std_logic; + ffc_quad_rst : in std_logic; + ffc_trst : in std_logic; + ff_txfullclk : out std_logic; + ff_txhalfclk : out std_logic; + refck2core : out std_logic; + ffs_plol : out std_logic); + +end serdes_gbe_2; + +architecture serdes_gbe_2_arch of serdes_gbe_2 is + +component VLO +port ( + Z : out std_logic); +end component; + +component VHI +port ( + Z : out std_logic); +end component; +component PCSC +--synopsys translate_off +GENERIC( + CONFIG_FILE : String + ); +--synopsys translate_on +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_RX_Q_CLK_0 : out std_logic; + FF_RX_Q_CLK_1 : out std_logic; + FF_RX_Q_CLK_2 : out std_logic; + FF_RX_Q_CLK_3 : out std_logic; + FF_TX_F_CLK : out std_logic; + FF_TX_H_CLK : out std_logic; + FF_TX_Q_CLK : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + OOB_OUT_0 : out std_logic; + OOB_OUT_1 : out std_logic; + OOB_OUT_2 : out std_logic; + OOB_OUT_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic +); +end component; + attribute IS_ASB: string; + attribute IS_ASB of PCSC_INST : label is "ep5m00/data/ep5m00.acd"; + attribute CONFIG_FILE: string; + attribute CONFIG_FILE of PCSC_INST : label is USER_CONFIG_FILE; + attribute black_box_pad_pin: string; + attribute black_box_pad_pin of PCSC : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; + +signal fpsc_vlo : std_logic := '0'; +signal cin : std_logic_vector (11 downto 0) := "000000000000"; +signal cout : std_logic_vector (19 downto 0); + +begin + +vlo_inst : VLO port map(Z => fpsc_vlo); + +-- pcs_quad instance +PCSC_INST : PCSC +--synopsys translate_off + generic map (CONFIG_FILE => USER_CONFIG_FILE) +--synopsys translate_on +port map ( + FFC_CK_CORE_TX => core_txrefclk, + FFC_CK_CORE_RX => core_rxrefclk, + REFCLKP => fpsc_vlo, + REFCLKN => fpsc_vlo, + HDINP0 => hdinp0, + HDINN0 => hdinn0, + HDOUTP0 => hdoutp0, + HDOUTN0 => hdoutn0, + SCISELCH0 => fpsc_vlo, + SCIENCH0 => fpsc_vlo, + FF_RXI_CLK_0 => ff_rxiclk_ch0, + FF_TXI_CLK_0 => ff_txiclk_ch0, + FF_EBRD_CLK_0 => ff_ebrd_clk_0, + FF_RX_F_CLK_0 => ff_rxfullclk_ch0, + FF_RX_H_CLK_0 => ff_rxhalfclk_ch0, + FF_RX_Q_CLK_0 => open, + FF_TX_D_0_0 => ff_txdata_ch0(0), + FF_TX_D_0_1 => ff_txdata_ch0(1), + FF_TX_D_0_2 => ff_txdata_ch0(2), + FF_TX_D_0_3 => ff_txdata_ch0(3), + FF_TX_D_0_4 => ff_txdata_ch0(4), + FF_TX_D_0_5 => ff_txdata_ch0(5), + FF_TX_D_0_6 => ff_txdata_ch0(6), + FF_TX_D_0_7 => ff_txdata_ch0(7), + FF_TX_D_0_8 => ff_tx_k_cntrl_ch0(0), + FF_TX_D_0_9 => fpsc_vlo, + FF_TX_D_0_10 => ff_xmit_ch0(0), + FF_TX_D_0_11 => ff_correct_disp_ch0(0), + FF_TX_D_0_12 => ff_txdata_ch0(8), + FF_TX_D_0_13 => ff_txdata_ch0(9), + FF_TX_D_0_14 => ff_txdata_ch0(10), + FF_TX_D_0_15 => ff_txdata_ch0(11), + FF_TX_D_0_16 => ff_txdata_ch0(12), + FF_TX_D_0_17 => ff_txdata_ch0(13), + FF_TX_D_0_18 => ff_txdata_ch0(14), + FF_TX_D_0_19 => ff_txdata_ch0(15), + FF_TX_D_0_20 => ff_tx_k_cntrl_ch0(1), + FF_TX_D_0_21 => fpsc_vlo, + FF_TX_D_0_22 => ff_xmit_ch0(1), + FF_TX_D_0_23 => ff_correct_disp_ch0(1), + FF_RX_D_0_0 => ff_rxdata_ch0(0), + FF_RX_D_0_1 => ff_rxdata_ch0(1), + FF_RX_D_0_2 => ff_rxdata_ch0(2), + FF_RX_D_0_3 => ff_rxdata_ch0(3), + FF_RX_D_0_4 => ff_rxdata_ch0(4), + FF_RX_D_0_5 => ff_rxdata_ch0(5), + FF_RX_D_0_6 => ff_rxdata_ch0(6), + FF_RX_D_0_7 => ff_rxdata_ch0(7), + FF_RX_D_0_8 => ff_rx_k_cntrl_ch0(0), + FF_RX_D_0_9 => ff_disp_err_ch0(0), + FF_RX_D_0_10 => ff_cv_ch0(0), + FF_RX_D_0_11 => ff_rx_even_ch0(0), + FF_RX_D_0_12 => ff_rxdata_ch0(8), + FF_RX_D_0_13 => ff_rxdata_ch0(9), + FF_RX_D_0_14 => ff_rxdata_ch0(10), + FF_RX_D_0_15 => ff_rxdata_ch0(11), + FF_RX_D_0_16 => ff_rxdata_ch0(12), + FF_RX_D_0_17 => ff_rxdata_ch0(13), + FF_RX_D_0_18 => ff_rxdata_ch0(14), + FF_RX_D_0_19 => ff_rxdata_ch0(15), + FF_RX_D_0_20 => ff_rx_k_cntrl_ch0(1), + FF_RX_D_0_21 => ff_disp_err_ch0(1), + FF_RX_D_0_22 => ff_cv_ch0(1), + FF_RX_D_0_23 => ff_rx_even_ch0(1), + FFC_RRST_0 => ffc_rrst_ch0, + FFC_SIGNAL_DETECT_0 => fpsc_vlo, + FFC_ENABLE_CGALIGN_0 => fpsc_vlo, + FFC_SB_PFIFO_LP_0 => fpsc_vlo, + FFC_PFIFO_CLR_0 => fpsc_vlo, + FFC_FB_LOOPBACK_0 => fpsc_vlo, + FFC_SB_INV_RX_0 => fpsc_vlo, + FFC_PCIE_CT_0 => fpsc_vlo, + FFC_PCI_DET_EN_0 => fpsc_vlo, + FFS_PCIE_DONE_0 => open, + FFS_PCIE_CON_0 => open, + FFC_EI_EN_0 => fpsc_vlo, + FFC_LANE_TX_RST_0 => ffc_lane_tx_rst_ch0, + FFC_LANE_RX_RST_0 => ffc_lane_rx_rst_ch0, + FFC_TXPWDNB_0 => ffc_txpwdnb_ch0, + FFC_RXPWDNB_0 => ffc_rxpwdnb_ch0, + FFS_RLOS_LO_0 => ffs_rlos_lo_ch0, + FFS_LS_SYNC_STATUS_0 => ffs_ls_sync_status_ch0, + FFS_CC_UNDERRUN_0 => ffs_cc_underrun_ch0, + FFS_CC_OVERRUN_0 => ffs_cc_overrun_ch0, + FFS_RXFBFIFO_ERROR_0 => ffs_rxfbfifo_error_ch0, + FFS_TXFBFIFO_ERROR_0 => ffs_txfbfifo_error_ch0, + FFS_RLOL_0 => ffs_rlol_ch0, + OOB_OUT_0 => oob_out_ch0, + HDINP1 => hdinp1, + HDINN1 => hdinn1, + HDOUTP1 => hdoutp1, + HDOUTN1 => hdoutn1, + SCISELCH1 => fpsc_vlo, + SCIENCH1 => fpsc_vlo, + FF_RXI_CLK_1 => ff_rxiclk_ch1, + FF_TXI_CLK_1 => ff_txiclk_ch1, + FF_EBRD_CLK_1 => ff_ebrd_clk_1, + FF_RX_F_CLK_1 => ff_rxfullclk_ch1, + FF_RX_H_CLK_1 => ff_rxhalfclk_ch1, + FF_RX_Q_CLK_1 => open, + FF_TX_D_1_0 => ff_txdata_ch1(0), + FF_TX_D_1_1 => ff_txdata_ch1(1), + FF_TX_D_1_2 => ff_txdata_ch1(2), + FF_TX_D_1_3 => ff_txdata_ch1(3), + FF_TX_D_1_4 => ff_txdata_ch1(4), + FF_TX_D_1_5 => ff_txdata_ch1(5), + FF_TX_D_1_6 => ff_txdata_ch1(6), + FF_TX_D_1_7 => ff_txdata_ch1(7), + FF_TX_D_1_8 => ff_tx_k_cntrl_ch1(0), + FF_TX_D_1_9 => fpsc_vlo, + FF_TX_D_1_10 => ff_xmit_ch1(0), + FF_TX_D_1_11 => ff_correct_disp_ch1(0), + FF_TX_D_1_12 => ff_txdata_ch1(8), + FF_TX_D_1_13 => ff_txdata_ch1(9), + FF_TX_D_1_14 => ff_txdata_ch1(10), + FF_TX_D_1_15 => ff_txdata_ch1(11), + FF_TX_D_1_16 => ff_txdata_ch1(12), + FF_TX_D_1_17 => ff_txdata_ch1(13), + FF_TX_D_1_18 => ff_txdata_ch1(14), + FF_TX_D_1_19 => ff_txdata_ch1(15), + FF_TX_D_1_20 => ff_tx_k_cntrl_ch1(1), + FF_TX_D_1_21 => fpsc_vlo, + FF_TX_D_1_22 => ff_xmit_ch1(1), + FF_TX_D_1_23 => ff_correct_disp_ch1(1), + FF_RX_D_1_0 => ff_rxdata_ch1(0), + FF_RX_D_1_1 => ff_rxdata_ch1(1), + FF_RX_D_1_2 => ff_rxdata_ch1(2), + FF_RX_D_1_3 => ff_rxdata_ch1(3), + FF_RX_D_1_4 => ff_rxdata_ch1(4), + FF_RX_D_1_5 => ff_rxdata_ch1(5), + FF_RX_D_1_6 => ff_rxdata_ch1(6), + FF_RX_D_1_7 => ff_rxdata_ch1(7), + FF_RX_D_1_8 => ff_rx_k_cntrl_ch1(0), + FF_RX_D_1_9 => ff_disp_err_ch1(0), + FF_RX_D_1_10 => ff_cv_ch1(0), + FF_RX_D_1_11 => ff_rx_even_ch1(0), + FF_RX_D_1_12 => ff_rxdata_ch1(8), + FF_RX_D_1_13 => ff_rxdata_ch1(9), + FF_RX_D_1_14 => ff_rxdata_ch1(10), + FF_RX_D_1_15 => ff_rxdata_ch1(11), + FF_RX_D_1_16 => ff_rxdata_ch1(12), + FF_RX_D_1_17 => ff_rxdata_ch1(13), + FF_RX_D_1_18 => ff_rxdata_ch1(14), + FF_RX_D_1_19 => ff_rxdata_ch1(15), + FF_RX_D_1_20 => ff_rx_k_cntrl_ch1(1), + FF_RX_D_1_21 => ff_disp_err_ch1(1), + FF_RX_D_1_22 => ff_cv_ch1(1), + FF_RX_D_1_23 => ff_rx_even_ch1(1), + FFC_RRST_1 => ffc_rrst_ch1, + FFC_SIGNAL_DETECT_1 => fpsc_vlo, + FFC_ENABLE_CGALIGN_1 => fpsc_vlo, + FFC_SB_PFIFO_LP_1 => fpsc_vlo, + FFC_PFIFO_CLR_1 => fpsc_vlo, + FFC_FB_LOOPBACK_1 => fpsc_vlo, + FFC_SB_INV_RX_1 => fpsc_vlo, + FFC_PCIE_CT_1 => fpsc_vlo, + FFC_PCI_DET_EN_1 => fpsc_vlo, + FFS_PCIE_DONE_1 => open, + FFS_PCIE_CON_1 => open, + FFC_EI_EN_1 => fpsc_vlo, + FFC_LANE_TX_RST_1 => ffc_lane_tx_rst_ch1, + FFC_LANE_RX_RST_1 => ffc_lane_rx_rst_ch1, + FFC_TXPWDNB_1 => ffc_txpwdnb_ch1, + FFC_RXPWDNB_1 => ffc_rxpwdnb_ch1, + FFS_RLOS_LO_1 => ffs_rlos_lo_ch1, + FFS_LS_SYNC_STATUS_1 => ffs_ls_sync_status_ch1, + FFS_CC_UNDERRUN_1 => ffs_cc_underrun_ch1, + FFS_CC_OVERRUN_1 => ffs_cc_overrun_ch1, + FFS_RXFBFIFO_ERROR_1 => ffs_rxfbfifo_error_ch1, + FFS_TXFBFIFO_ERROR_1 => ffs_txfbfifo_error_ch1, + FFS_RLOL_1 => ffs_rlol_ch1, + OOB_OUT_1 => oob_out_ch1, + HDINP2 => hdinp2, + HDINN2 => hdinn2, + HDOUTP2 => hdoutp2, + HDOUTN2 => hdoutn2, + SCISELCH2 => fpsc_vlo, + SCIENCH2 => fpsc_vlo, + FF_RXI_CLK_2 => ff_rxiclk_ch2, + FF_TXI_CLK_2 => ff_txiclk_ch2, + FF_EBRD_CLK_2 => ff_ebrd_clk_2, + FF_RX_F_CLK_2 => ff_rxfullclk_ch2, + FF_RX_H_CLK_2 => ff_rxhalfclk_ch2, + FF_RX_Q_CLK_2 => open, + FF_TX_D_2_0 => ff_txdata_ch2(0), + FF_TX_D_2_1 => ff_txdata_ch2(1), + FF_TX_D_2_2 => ff_txdata_ch2(2), + FF_TX_D_2_3 => ff_txdata_ch2(3), + FF_TX_D_2_4 => ff_txdata_ch2(4), + FF_TX_D_2_5 => ff_txdata_ch2(5), + FF_TX_D_2_6 => ff_txdata_ch2(6), + FF_TX_D_2_7 => ff_txdata_ch2(7), + FF_TX_D_2_8 => ff_tx_k_cntrl_ch2(0), + FF_TX_D_2_9 => fpsc_vlo, + FF_TX_D_2_10 => ff_xmit_ch2(0), + FF_TX_D_2_11 => ff_correct_disp_ch2(0), + FF_TX_D_2_12 => ff_txdata_ch2(8), + FF_TX_D_2_13 => ff_txdata_ch2(9), + FF_TX_D_2_14 => ff_txdata_ch2(10), + FF_TX_D_2_15 => ff_txdata_ch2(11), + FF_TX_D_2_16 => ff_txdata_ch2(12), + FF_TX_D_2_17 => ff_txdata_ch2(13), + FF_TX_D_2_18 => ff_txdata_ch2(14), + FF_TX_D_2_19 => ff_txdata_ch2(15), + FF_TX_D_2_20 => ff_tx_k_cntrl_ch2(1), + FF_TX_D_2_21 => fpsc_vlo, + FF_TX_D_2_22 => ff_xmit_ch2(1), + FF_TX_D_2_23 => ff_correct_disp_ch2(1), + FF_RX_D_2_0 => ff_rxdata_ch2(0), + FF_RX_D_2_1 => ff_rxdata_ch2(1), + FF_RX_D_2_2 => ff_rxdata_ch2(2), + FF_RX_D_2_3 => ff_rxdata_ch2(3), + FF_RX_D_2_4 => ff_rxdata_ch2(4), + FF_RX_D_2_5 => ff_rxdata_ch2(5), + FF_RX_D_2_6 => ff_rxdata_ch2(6), + FF_RX_D_2_7 => ff_rxdata_ch2(7), + FF_RX_D_2_8 => ff_rx_k_cntrl_ch2(0), + FF_RX_D_2_9 => ff_disp_err_ch2(0), + FF_RX_D_2_10 => ff_cv_ch2(0), + FF_RX_D_2_11 => ff_rx_even_ch2(0), + FF_RX_D_2_12 => ff_rxdata_ch2(8), + FF_RX_D_2_13 => ff_rxdata_ch2(9), + FF_RX_D_2_14 => ff_rxdata_ch2(10), + FF_RX_D_2_15 => ff_rxdata_ch2(11), + FF_RX_D_2_16 => ff_rxdata_ch2(12), + FF_RX_D_2_17 => ff_rxdata_ch2(13), + FF_RX_D_2_18 => ff_rxdata_ch2(14), + FF_RX_D_2_19 => ff_rxdata_ch2(15), + FF_RX_D_2_20 => ff_rx_k_cntrl_ch2(1), + FF_RX_D_2_21 => ff_disp_err_ch2(1), + FF_RX_D_2_22 => ff_cv_ch2(1), + FF_RX_D_2_23 => ff_rx_even_ch2(1), + FFC_RRST_2 => ffc_rrst_ch2, + FFC_SIGNAL_DETECT_2 => fpsc_vlo, + FFC_ENABLE_CGALIGN_2 => fpsc_vlo, + FFC_SB_PFIFO_LP_2 => fpsc_vlo, + FFC_PFIFO_CLR_2 => fpsc_vlo, + FFC_FB_LOOPBACK_2 => fpsc_vlo, + FFC_SB_INV_RX_2 => fpsc_vlo, + FFC_PCIE_CT_2 => fpsc_vlo, + FFC_PCI_DET_EN_2 => fpsc_vlo, + FFS_PCIE_DONE_2 => open, + FFS_PCIE_CON_2 => open, + FFC_EI_EN_2 => fpsc_vlo, + FFC_LANE_TX_RST_2 => ffc_lane_tx_rst_ch2, + FFC_LANE_RX_RST_2 => ffc_lane_rx_rst_ch2, + FFC_TXPWDNB_2 => ffc_txpwdnb_ch2, + FFC_RXPWDNB_2 => ffc_rxpwdnb_ch2, + FFS_RLOS_LO_2 => ffs_rlos_lo_ch2, + FFS_LS_SYNC_STATUS_2 => ffs_ls_sync_status_ch2, + FFS_CC_UNDERRUN_2 => ffs_cc_underrun_ch2, + FFS_CC_OVERRUN_2 => ffs_cc_overrun_ch2, + FFS_RXFBFIFO_ERROR_2 => ffs_rxfbfifo_error_ch2, + FFS_TXFBFIFO_ERROR_2 => ffs_txfbfifo_error_ch2, + FFS_RLOL_2 => ffs_rlol_ch2, + OOB_OUT_2 => oob_out_ch2, + HDINP3 => hdinp3, + HDINN3 => hdinn3, + HDOUTP3 => hdoutp3, + HDOUTN3 => hdoutn3, + SCISELCH3 => fpsc_vlo, + SCIENCH3 => fpsc_vlo, + FF_RXI_CLK_3 => ff_rxiclk_ch3, + FF_TXI_CLK_3 => ff_txiclk_ch3, + FF_EBRD_CLK_3 => ff_ebrd_clk_3, + FF_RX_F_CLK_3 => ff_rxfullclk_ch3, + FF_RX_H_CLK_3 => ff_rxhalfclk_ch3, + FF_RX_Q_CLK_3 => open, + FF_TX_D_3_0 => ff_txdata_ch3(0), + FF_TX_D_3_1 => ff_txdata_ch3(1), + FF_TX_D_3_2 => ff_txdata_ch3(2), + FF_TX_D_3_3 => ff_txdata_ch3(3), + FF_TX_D_3_4 => ff_txdata_ch3(4), + FF_TX_D_3_5 => ff_txdata_ch3(5), + FF_TX_D_3_6 => ff_txdata_ch3(6), + FF_TX_D_3_7 => ff_txdata_ch3(7), + FF_TX_D_3_8 => ff_tx_k_cntrl_ch3(0), + FF_TX_D_3_9 => fpsc_vlo, + FF_TX_D_3_10 => ff_xmit_ch3(0), + FF_TX_D_3_11 => ff_correct_disp_ch3(0), + FF_TX_D_3_12 => ff_txdata_ch3(8), + FF_TX_D_3_13 => ff_txdata_ch3(9), + FF_TX_D_3_14 => ff_txdata_ch3(10), + FF_TX_D_3_15 => ff_txdata_ch3(11), + FF_TX_D_3_16 => ff_txdata_ch3(12), + FF_TX_D_3_17 => ff_txdata_ch3(13), + FF_TX_D_3_18 => ff_txdata_ch3(14), + FF_TX_D_3_19 => ff_txdata_ch3(15), + FF_TX_D_3_20 => ff_tx_k_cntrl_ch3(1), + FF_TX_D_3_21 => fpsc_vlo, + FF_TX_D_3_22 => ff_xmit_ch3(1), + FF_TX_D_3_23 => ff_correct_disp_ch3(1), + FF_RX_D_3_0 => ff_rxdata_ch3(0), + FF_RX_D_3_1 => ff_rxdata_ch3(1), + FF_RX_D_3_2 => ff_rxdata_ch3(2), + FF_RX_D_3_3 => ff_rxdata_ch3(3), + FF_RX_D_3_4 => ff_rxdata_ch3(4), + FF_RX_D_3_5 => ff_rxdata_ch3(5), + FF_RX_D_3_6 => ff_rxdata_ch3(6), + FF_RX_D_3_7 => ff_rxdata_ch3(7), + FF_RX_D_3_8 => ff_rx_k_cntrl_ch3(0), + FF_RX_D_3_9 => ff_disp_err_ch3(0), + FF_RX_D_3_10 => ff_cv_ch3(0), + FF_RX_D_3_11 => ff_rx_even_ch3(0), + FF_RX_D_3_12 => ff_rxdata_ch3(8), + FF_RX_D_3_13 => ff_rxdata_ch3(9), + FF_RX_D_3_14 => ff_rxdata_ch3(10), + FF_RX_D_3_15 => ff_rxdata_ch3(11), + FF_RX_D_3_16 => ff_rxdata_ch3(12), + FF_RX_D_3_17 => ff_rxdata_ch3(13), + FF_RX_D_3_18 => ff_rxdata_ch3(14), + FF_RX_D_3_19 => ff_rxdata_ch3(15), + FF_RX_D_3_20 => ff_rx_k_cntrl_ch3(1), + FF_RX_D_3_21 => ff_disp_err_ch3(1), + FF_RX_D_3_22 => ff_cv_ch3(1), + FF_RX_D_3_23 => ff_rx_even_ch3(1), + FFC_RRST_3 => ffc_rrst_ch3, + FFC_SIGNAL_DETECT_3 => fpsc_vlo, + FFC_ENABLE_CGALIGN_3 => fpsc_vlo, + FFC_SB_PFIFO_LP_3 => fpsc_vlo, + FFC_PFIFO_CLR_3 => fpsc_vlo, + FFC_FB_LOOPBACK_3 => fpsc_vlo, + FFC_SB_INV_RX_3 => fpsc_vlo, + FFC_PCIE_CT_3 => fpsc_vlo, + FFC_PCI_DET_EN_3 => fpsc_vlo, + FFS_PCIE_DONE_3 => open, + FFS_PCIE_CON_3 => open, + FFC_EI_EN_3 => fpsc_vlo, + FFC_LANE_TX_RST_3 => ffc_lane_tx_rst_ch3, + FFC_LANE_RX_RST_3 => ffc_lane_rx_rst_ch3, + FFC_TXPWDNB_3 => ffc_txpwdnb_ch3, + FFC_RXPWDNB_3 => ffc_rxpwdnb_ch3, + FFS_RLOS_LO_3 => ffs_rlos_lo_ch3, + FFS_LS_SYNC_STATUS_3 => ffs_ls_sync_status_ch3, + FFS_CC_UNDERRUN_3 => ffs_cc_underrun_ch3, + FFS_CC_OVERRUN_3 => ffs_cc_overrun_ch3, + FFS_RXFBFIFO_ERROR_3 => ffs_rxfbfifo_error_ch3, + FFS_TXFBFIFO_ERROR_3 => ffs_txfbfifo_error_ch3, + FFS_RLOL_3 => ffs_rlol_ch3, + OOB_OUT_3 => oob_out_ch3, + SCIWDATA0 => fpsc_vlo, + SCIWDATA1 => fpsc_vlo, + SCIWDATA2 => fpsc_vlo, + SCIWDATA3 => fpsc_vlo, + SCIWDATA4 => fpsc_vlo, + SCIWDATA5 => fpsc_vlo, + SCIWDATA6 => fpsc_vlo, + SCIWDATA7 => fpsc_vlo, + SCIADDR0 => fpsc_vlo, + SCIADDR1 => fpsc_vlo, + SCIADDR2 => fpsc_vlo, + SCIADDR3 => fpsc_vlo, + SCIADDR4 => fpsc_vlo, + SCIADDR5 => fpsc_vlo, + SCIRDATA0 => open, + SCIRDATA1 => open, + SCIRDATA2 => open, + SCIRDATA3 => open, + SCIRDATA4 => open, + SCIRDATA5 => open, + SCIRDATA6 => open, + SCIRDATA7 => open, + SCIENAUX => fpsc_vlo, + SCISELAUX => fpsc_vlo, + SCIRD => fpsc_vlo, + SCIWSTN => fpsc_vlo, + CYAWSTN => fpsc_vlo, + SCIINT => open, + FFC_MACRO_RST => ffc_macro_rst, + FFC_QUAD_RST => ffc_quad_rst, + FFC_TRST => ffc_trst, + FF_TX_F_CLK => ff_txfullclk, + FF_TX_H_CLK => ff_txhalfclk, + FF_TX_Q_CLK => open, + REFCK2CORE => refck2core, + CIN0 => cin(0), + CIN1 => cin(1), + CIN2 => cin(2), + CIN3 => cin(3), + CIN4 => cin(4), + CIN5 => cin(5), + CIN6 => cin(6), + CIN7 => cin(7), + CIN8 => cin(8), + CIN9 => cin(9), + CIN10 => cin(10), + CIN11 => cin(11), + COUT0 => cout(0), + COUT1 => cout(1), + COUT2 => cout(2), + COUT3 => cout(3), + COUT4 => cout(4), + COUT5 => cout(5), + COUT6 => cout(6), + COUT7 => cout(7), + COUT8 => cout(8), + COUT9 => cout(9), + COUT10 => cout(10), + COUT11 => cout(11), + COUT12 => cout(12), + COUT13 => cout(13), + COUT14 => cout(14), + COUT15 => cout(15), + COUT16 => cout(16), + COUT17 => cout(17), + COUT18 => cout(18), + COUT19 => cout(19), + FFS_PLOL => ffs_plol); + +--synopsys translate_off +file_read : PROCESS +VARIABLE open_status : file_open_status; +FILE config : text; +BEGIN + file_open (open_status, config, USER_CONFIG_FILE, read_mode); + IF (open_status = name_error) THEN + report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" + severity ERROR; + END IF; + wait; +END PROCESS; +--synopsys translate_on + +end serdes_gbe_2_arch ; diff --git a/media_interfaces/ecp2m_sfp/serdes_gbe_all_generate.log b/media_interfaces/ecp2m_sfp/serdes_gbe_all_generate.log new file mode 100755 index 0000000..117610b --- /dev/null +++ b/media_interfaces/ecp2m_sfp/serdes_gbe_all_generate.log @@ -0,0 +1,26 @@ +Starting process: + + Module Name: serdes_gbe_2 + Core Name: PCS + LPC file : serdes_gbe_2.lpc + Parameter File : serdes_gbe_2.pp + Command line: X:/Programme/ispTOOLS_72/ispfpga/bin/nt/orcapp.exe -Fmaco serdes_gbe_2.pp + Return Value: + + + Module PCS has been generated in i:/vhdl_pro/adcmv2/lever successfully! + +X:/Programme/ispTOOLS_72/ispcpld/bin/hdl2jhd.exe -tfi -mod serdes_gbe_2 -ext readme -out serdes_gbe_2 -tpl serdes_gbe_2.tft serdes_gbe_2.vhd + +Done successfully! +File: serdes_gbe_all.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd b/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd new file mode 100755 index 0000000..b5d7341 --- /dev/null +++ b/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd @@ -0,0 +1,623 @@ +--Media interface for Lattice ECP2M using PCS at 2GHz + +--Still missing: link reset features, fifo full error handling + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; + +entity trb_net16_med_ecp_sfp is + generic( + SERDES_NUM : integer range 0 to 3 := 2; + EXT_CLOCK : integer range 0 to 1 := c_NO + ); + port( + CLK : in std_logic; -- SerDes clock + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; + --Internal Connection + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_READ_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + REFCLK2CORE_OUT : out std_logic; + --SFP Connection + SD_RXD_P_IN : in std_logic; + SD_RXD_N_IN : in std_logic; + SD_TXD_P_OUT : out std_logic; + SD_TXD_N_OUT : out std_logic; + SD_REFCLK_P_IN : in std_logic; + SD_REFCLK_N_IN : in std_logic; + SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic; -- SFP disable + -- Status and control port + STAT_OP : out std_logic_vector (15 downto 0); + CTRL_OP : in std_logic_vector (15 downto 0); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) + ); +end entity; + +architecture med_ecp_sfp of trb_net16_med_ecp_sfp is + + + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of med_ecp_sfp : architecture is "media_interface_group"; + attribute syn_sharing : string; + attribute syn_sharing of med_ecp_sfp : architecture is "off"; + +-- component serdes_sfp_2 +-- port( +-- core_txrefclk : in std_logic; +-- core_rxrefclk : in std_logic; +-- hdinp2 : in std_logic; +-- hdinn2 : in std_logic; +-- ff_rxiclk_ch2 : in std_logic; +-- ff_txiclk_ch2 : in std_logic; +-- ff_ebrd_clk_2 : in std_logic; +-- ff_txdata_ch2 : in std_logic_vector(15 downto 0); +-- ff_tx_k_cntrl_ch2 : in std_logic_vector(1 downto 0); +-- ff_force_disp_ch2 : in std_logic_vector(1 downto 0); +-- ff_disp_sel_ch2 : in std_logic_vector(1 downto 0); +-- ff_correct_disp_ch2 : in std_logic_vector(1 downto 0); +-- ffc_rrst_ch2 : in std_logic; +-- ffc_lane_tx_rst_ch2 : in std_logic; +-- ffc_lane_rx_rst_ch2 : in std_logic; +-- ffc_txpwdnb_ch2 : in std_logic; +-- ffc_rxpwdnb_ch2 : in std_logic; +-- ffc_macro_rst : in std_logic; +-- ffc_quad_rst : in std_logic; +-- ffc_trst : in std_logic; +-- hdoutp2 : out std_logic; +-- hdoutn2 : out std_logic; +-- ff_rxdata_ch2 : out std_logic_vector(15 downto 0); +-- ff_rx_k_cntrl_ch2 : out std_logic_vector(1 downto 0); +-- ff_rxfullclk_ch2 : out std_logic; +-- ff_rxhalfclk_ch2 : out std_logic; +-- ff_disp_err_ch2 : out std_logic_vector(1 downto 0); +-- ff_cv_ch2 : out std_logic_vector(1 downto 0); +-- ffs_rlos_lo_ch2 : out std_logic; +-- ffs_ls_sync_status_ch2 : out std_logic; +-- ffs_cc_underrun_ch2 : out std_logic; +-- ffs_cc_overrun_ch2 : out std_logic; +-- ffs_txfbfifo_error_ch2 : out std_logic; +-- ffs_rxfbfifo_error_ch2 : out std_logic; +-- ffs_rlol_ch2 : out std_logic; +-- oob_out_ch2 : out std_logic; +-- ff_txfullclk : out std_logic; +-- ff_txhalfclk : out std_logic; +-- refck2core : out std_logic; +-- ffs_plol : out std_logic +-- ); +-- end component; + + component serdes_gbe_2 + port( + core_txrefclk : IN std_logic; + core_rxrefclk : IN std_logic; + hdinp2 : IN std_logic; + hdinn2 : IN std_logic; + ff_rxiclk_ch2 : IN std_logic; + ff_txiclk_ch2 : IN std_logic; + ff_ebrd_clk_2 : IN std_logic; + ff_txdata_ch2 : IN std_logic_vector(15 downto 0); + ff_tx_k_cntrl_ch2 : IN std_logic_vector(1 downto 0); + ff_xmit_ch2 : IN std_logic_vector(1 downto 0); + ff_correct_disp_ch2 : IN std_logic_vector(1 downto 0); + ffc_rrst_ch2 : IN std_logic; + ffc_lane_tx_rst_ch2 : IN std_logic; + ffc_lane_rx_rst_ch2 : IN std_logic; + ffc_txpwdnb_ch2 : IN std_logic; + ffc_rxpwdnb_ch2 : IN std_logic; + ffc_macro_rst : IN std_logic; + ffc_quad_rst : IN std_logic; + ffc_trst : IN std_logic; + hdoutp2 : OUT std_logic; + hdoutn2 : OUT std_logic; + ff_rxdata_ch2 : OUT std_logic_vector(15 downto 0); + ff_rx_k_cntrl_ch2 : OUT std_logic_vector(1 downto 0); + ff_rxfullclk_ch2 : OUT std_logic; + ff_rxhalfclk_ch2 : OUT std_logic; + ff_disp_err_ch2 : OUT std_logic_vector(1 downto 0); + ff_cv_ch2 : OUT std_logic_vector(1 downto 0); + ff_rx_even_ch2 : OUT std_logic_vector(1 downto 0); + ffs_rlos_lo_ch2 : OUT std_logic; + ffs_ls_sync_status_ch2 : OUT std_logic; + ffs_cc_underrun_ch2 : OUT std_logic; + ffs_cc_overrun_ch2 : OUT std_logic; + ffs_txfbfifo_error_ch2 : OUT std_logic; + ffs_rxfbfifo_error_ch2 : OUT std_logic; + ffs_rlol_ch2 : OUT std_logic; + oob_out_ch2 : OUT std_logic; + ff_txfullclk : OUT std_logic; + ff_txhalfclk : OUT std_logic; + refck2core : OUT std_logic; + ffs_plol : OUT std_logic + ); + end component; + + + + signal refck2core : std_logic; +-- signal clock : std_logic; + --reset signals + signal ffc_quad_rst : std_logic; + signal ffc_lane_tx_rst : std_logic; + signal ffc_lane_rx_rst : std_logic; + --serdes connections + signal tx_data : std_logic_vector(15 downto 0); + signal tx_k : std_logic_vector(1 downto 0); + signal rx_data : std_logic_vector(15 downto 0); -- delayed signals + signal rx_k : std_logic_vector(1 downto 0); -- delayed signals + signal comb_rx_data : std_logic_vector(15 downto 0); -- original signals from SFP + signal comb_rx_k : std_logic_vector(1 downto 0); -- original signals from SFP + signal link_ok : std_logic_vector(0 downto 0); + signal link_error : std_logic_vector(8 downto 0); +-- signal ff_rxhalfclk : std_logic; + signal ff_txhalfclk : std_logic; + signal ff_txfullclk : std_logic; + --rx fifo signals + signal fifo_rx_rd_en : std_logic; + signal fifo_rx_wr_en : std_logic; + signal fifo_rx_reset : std_logic; + signal fifo_rx_din : std_logic_vector(17 downto 0); + signal fifo_rx_dout : std_logic_vector(17 downto 0); + signal fifo_rx_full : std_logic; + signal fifo_rx_empty : std_logic; + --tx fifo signals + signal fifo_tx_rd_en : std_logic; + signal fifo_tx_wr_en : std_logic; + signal fifo_tx_reset : std_logic; + signal fifo_tx_din : std_logic_vector(17 downto 0); + signal fifo_tx_dout : std_logic_vector(17 downto 0); + signal fifo_tx_full : std_logic; + signal fifo_tx_empty : std_logic; + --rx path + signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal buf_med_dataready_out : std_logic; + signal buf_med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal last_rx : std_logic_vector(8 downto 0); + signal last_fifo_rx_empty : std_logic; + --tx path + signal last_fifo_tx_empty : std_logic; + --link status + signal link_led : std_logic; + signal rx_k_q : std_logic_vector(1 downto 0); + + signal info_led : std_logic; + + signal quad_rst : std_logic; + signal lane_rst : std_logic; + signal tx_allow : std_logic; + signal rx_allow : std_logic; + + signal rx_allow_q : std_logic; -- clock domain changed signal + signal tx_allow_q : std_logic; + signal swap_bytes : std_logic; + signal buf_stat_debug : std_logic_vector(31 downto 0); + + -- status inputs from SFP + signal sfp_prsnt_n : std_logic; -- synchronized input signals + signal sfp_los : std_logic; -- synchronized input signals + + signal buf_STAT_OP : std_logic_vector(15 downto 0); + + signal led_counter : std_logic_vector(17 downto 0); + signal rx_led : std_logic; + signal tx_led : std_logic; + attribute syn_keep : boolean; + attribute syn_keep of led_counter : signal is true; + + signal reset_i : std_logic; + signal pwr_up : std_logic; +begin + +-------------------------------------------------------------------------- +-- Internal Lane Resets +-------------------------------------------------------------------------- + + PROC_RESET : process(SYSCLK) + begin + if rising_edge(SYSCLK) then + reset_i <= RESET or CTRL_OP(14); + pwr_up <= '1'; --not CTRL_OP(i*16+14); + end if; + end process; + +-------------------------------------------------------------------------- +-- Synchronizer stages +-------------------------------------------------------------------------- + +-- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP) +THE_SFP_STATUS_SYNC: signal_sync + generic map( + DEPTH => 3, + WIDTH => 2 + ) + port map( + RESET => reset_i, + D_IN(0) => sd_prsnt_n_in, + D_IN(1) => sd_los_in, + CLK0 => sysclk, + CLK1 => sysclk, + D_OUT(0) => sfp_prsnt_n, + D_OUT(1) => sfp_los + ); + +-- Komma delimiter transfer for training phase +THE_RX_K_SYNC: signal_sync + generic map( + DEPTH => 3, + WIDTH => 2 + ) + port map( + RESET => reset_i, + D_IN => comb_rx_k, + CLK0 => ff_txhalfclk, -- CHANGED + CLK1 => sysclk, + D_OUT => rx_k_q + ); + +-- delay line for RX_K and RX_DATA (directly from SFP to fabric logic) +THE_RX_DATA_DELAY: signal_sync + generic map( + DEPTH => 2, + WIDTH => 16 + ) + port map( + RESET => reset_i, + D_IN => comb_rx_data, + CLK0 => ff_txhalfclk, -- CHANGED + CLK1 => ff_txhalfclk, -- CHANGED + D_OUT => rx_data + ); + +THE_RX_K_DELAY: signal_sync + generic map( + DEPTH => 2, + WIDTH => 2 + ) + port map( + RESET => reset_i, + D_IN => comb_rx_k, + CLK0 => ff_txhalfclk, -- CHANGED + CLK1 => ff_txhalfclk, -- CHANGED + D_OUT => rx_k + ); + + +-- Transfer for ALLOW signals +THE_RX_ALLOW_SYNC: signal_sync -- really needed?!? + generic map( + DEPTH => 2, + WIDTH => 2 + ) + port map( + RESET => reset_i, + D_IN(0) => rx_allow, + D_IN(1) => tx_allow, + CLK0 => sysclk, + CLK1 => sysclk, + D_OUT(0) => rx_allow_q, + D_OUT(1) => tx_allow_q + ); + +-------------------------------------------------------------------------- +-- Main control state machine, startup control for SFP +-------------------------------------------------------------------------- + +THE_SFP_LSM: trb_net16_lsm_sfp + port map( + SYSCLK => sysclk, + RESET => reset_i, + CLEAR => clear, + SFP_MISSING_IN => sfp_prsnt_n, + SFP_LOS_IN => sfp_los, + SD_LINK_OK_IN => link_ok(0), + SD_LOS_IN => link_error(8), + SD_TXCLK_BAD_IN => link_error(5), + SD_RXCLK_BAD_IN => link_error(4), + SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope + SD_ALIGNMENT_IN => rx_k_q, + SD_CV_IN => link_error(7 downto 6), + FULL_RESET_OUT => quad_rst, + LANE_RESET_OUT => lane_rst, + TX_ALLOW_OUT => tx_allow, + RX_ALLOW_OUT => rx_allow, + SWAP_BYTES_OUT => swap_bytes, + STAT_OP => buf_stat_op, + CTRL_OP => ctrl_op, + STAT_DEBUG => buf_stat_debug + ); + +sd_txdis_out <= quad_rst; + +-------------------------------------------------------------------------- +-------------------------------------------------------------------------- + +ffc_quad_rst <= quad_rst; +ffc_lane_tx_rst <= lane_rst; +ffc_lane_rx_rst <= lane_rst; + +-- SerDes clock output to FPGA fabric +refclk2core_out <= refck2core; + +-- Instantiation of serdes module + gen_serdes_2 : if SERDES_NUM = 2 generate + THE_SERDES: serdes_gbe_2 + port map( + core_txrefclk => clk, + core_rxrefclk => clk, + hdinp2 => sd_rxd_p_in, + hdinn2 => sd_rxd_n_in, + ff_rxiclk_ch2 => ff_txhalfclk, -- CHANGED + ff_txiclk_ch2 => ff_txhalfclk, + ff_ebrd_clk_2 => ff_txfullclk, -- CHANGED + ff_txdata_ch2 => tx_data, + ff_tx_k_cntrl_ch2 => tx_k, + ff_xmit_ch2 => "00", -- UNKNOWN + ff_correct_disp_ch2 => "00", + ffc_rrst_ch2 => '0', + ffc_lane_tx_rst_ch2 => ffc_lane_tx_rst, + ffc_lane_rx_rst_ch2 => ffc_lane_tx_rst, + ffc_txpwdnb_ch2 => '1', + ffc_rxpwdnb_ch2 => '1', + ffc_macro_rst => '0', + ffc_quad_rst => ffc_quad_rst, + ffc_trst => '0', + hdoutp2 => sd_txd_p_out, + hdoutn2 => sd_txd_n_out, + ff_rxdata_ch2 => comb_rx_data, + ff_rx_k_cntrl_ch2 => comb_rx_k, + ff_rxfullclk_ch2 => open, + ff_rxhalfclk_ch2 => open, --ff_rxhalfclk, + ff_disp_err_ch2 => open, + ff_cv_ch2 => link_error(7 downto 6), + ff_rx_even_ch2 => open, -- UNKNOWN + ffs_rlos_lo_ch2 => link_error(8), + ffs_ls_sync_status_ch2 => link_ok(0), + ffs_cc_underrun_ch2 => link_error(0), + ffs_cc_overrun_ch2 => link_error(1), + ffs_txfbfifo_error_ch2 => link_error(2), + ffs_rxfbfifo_error_ch2 => link_error(3), + ffs_rlol_ch2 => link_error(4), + oob_out_ch2 => open, + ff_txfullclk => ff_txfullclk, -- CHANGED + ff_txhalfclk => ff_txhalfclk, + refck2core => refck2core, + ffs_plol => link_error(5) + ); +-- THE_SERDES: serdes_sfp_2 +-- port map( +-- core_txrefclk => clk, +-- core_rxrefclk => clk, +-- hdinp2 => sd_rxd_p_in, +-- hdinn2 => sd_rxd_n_in, +-- ff_rxiclk_ch2 => ff_rxhalfclk, +-- ff_txiclk_ch2 => ff_txhalfclk, +-- ff_ebrd_clk_2 => ff_rxhalfclk, -- not used, just for completeness +-- ff_txdata_ch2 => tx_data, +-- ff_tx_k_cntrl_ch2 => tx_k, +---- ff_force_disp_ch2 => "00", +---- ff_disp_sel_ch2 => "00", +-- ff_correct_disp_ch2 => "00", +-- ffc_rrst_ch2 => '0', +-- ffc_lane_tx_rst_ch2 => ffc_lane_tx_rst, +-- ffc_lane_rx_rst_ch2 => ffc_lane_rx_rst, +-- ffc_txpwdnb_ch2 => '1', +-- ffc_rxpwdnb_ch2 => '1', +-- ffc_macro_rst => '0', +-- ffc_quad_rst => ffc_quad_rst, +-- ffc_trst => '0', +-- hdoutp2 => sd_txd_p_out, +-- hdoutn2 => sd_txd_n_out, +-- ff_rxdata_ch2 => comb_rx_data, --rx_data, +-- ff_rx_k_cntrl_ch2 => comb_rx_k, --rx_k, +-- ff_rxfullclk_ch2 => open, +-- ff_rxhalfclk_ch2 => ff_rxhalfclk, +-- ff_disp_err_ch2 => open, +-- ff_cv_ch2 => link_error(7 downto 6), +-- ffs_rlos_lo_ch2 => link_error(8), +-- ffs_ls_sync_status_ch2 => link_ok(0), +-- ffs_cc_underrun_ch2 => link_error(0), +-- ffs_cc_overrun_ch2 => link_error(1), +-- ffs_txfbfifo_error_ch2 => link_error(2), +-- ffs_rxfbfifo_error_ch2 => link_error(3), +-- ffs_rlol_ch2 => link_error(4), +-- oob_out_ch2 => open, +-- ff_txfullclk => open, +-- ff_txhalfclk => ff_txhalfclk, +-- refck2core => refck2core, +-- ffs_plol => link_error(5) +-- ); + end generate; + +------------------------------------------------------------------------- +-- RX Fifo & Data output +------------------------------------------------------------------------- +THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport +generic map( + USE_STATUS_FLAGS => c_NO + ) +port map( read_clock_in => sysclk, + write_clock_in => ff_txhalfclk, -- CHANGED + read_enable_in => fifo_rx_rd_en, + write_enable_in => fifo_rx_wr_en, + fifo_gsr_in => fifo_rx_reset, + write_data_in => fifo_rx_din, + read_data_out => fifo_rx_dout, + full_out => fifo_rx_full, + empty_out => fifo_rx_empty + ); + +fifo_rx_reset <= reset_i or not rx_allow_q; +fifo_rx_rd_en <= '1'; + +-- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path +THE_BYTE_SWAP_PROC: process( ff_txhalfclk ) -- CHANGED +begin + if( rising_edge(ff_txhalfclk) ) then -- CHANGED + last_rx <= rx_k(1) & rx_data(15 downto 8); + if( swap_bytes = '0' ) then + fifo_rx_din <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0); + fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok(0); + else + fifo_rx_din <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0); + fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok(0); + end if; + end if; +end process THE_BYTE_SWAP_PROC; + +buf_med_data_out <= fifo_rx_dout(15 downto 0); +buf_med_dataready_out <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q; +buf_med_packet_num_out <= rx_counter; +med_read_out <= tx_allow_q; + +THE_SYNC_PROC: process( sysclk ) +begin + if( rising_edge(sysclk) ) then + if reset_i = '1' then + med_dataready_out <= '0'; + else + med_dataready_out <= buf_med_dataready_out; + med_data_out <= buf_med_data_out; + med_packet_num_out <= buf_med_packet_num_out; + end if; + end if; +end process THE_SYNC_PROC; + +--rx packet counter +--------------------- +THE_RX_PACKETS_PROC: process( sysclk ) +begin + if( rising_edge(sysclk) ) then + last_fifo_rx_empty <= fifo_rx_empty; + if reset_i = '1' or rx_allow_q = '0' then + rx_counter <= c_H0; + else + if( buf_med_dataready_out = '1' ) then + if( rx_counter = c_max_word_number ) then + rx_counter <= (others => '0'); + else + rx_counter <= rx_counter + 1; + end if; + end if; + end if; + end if; +end process; + +--TX Fifo & Data output to Serdes +--------------------- +THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport +generic map( + USE_STATUS_FLAGS => c_NO + ) +port map( read_clock_in => ff_txhalfclk, + write_clock_in => sysclk, + read_enable_in => fifo_tx_rd_en, + write_enable_in => fifo_tx_wr_en, + fifo_gsr_in => fifo_tx_reset, + write_data_in => fifo_tx_din, + read_data_out => fifo_tx_dout, + full_out => fifo_tx_full, + empty_out => fifo_tx_empty + ); + +fifo_tx_reset <= reset_i or not tx_allow_q; +fifo_tx_din <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in; +fifo_tx_wr_en <= med_dataready_in and tx_allow_q; +fifo_tx_rd_en <= tx_allow; + + +THE_SERDES_INPUT_PROC: process( ff_txhalfclk ) +begin + if( rising_edge(ff_txhalfclk) ) then + last_fifo_tx_empty <= fifo_tx_empty; + if( (last_fifo_tx_empty = '1') or (tx_allow = '0') ) then + tx_data <= x"c5bc"; + tx_k <= "01"; +-- elsif send_resync = '1' then +-- tx_data <= x"7F7F"; +-- tx_k <= "00"; + else + tx_data <= fifo_tx_dout(15 downto 0); + tx_k <= "00"; + end if; + end if; +end process THE_SERDES_INPUT_PROC; + +-- + + +--Generate LED signals +---------------------- +process(sysclk) + begin + if rising_edge(sysclk) then + led_counter <= led_counter + 1; + + if buf_med_dataready_out = '1' then + rx_led <= '1'; + elsif led_counter = 0 then + rx_led <= '0'; + end if; + + if tx_k(0) = '0' then -- tx_k clock domain crossing! + tx_led <= '1'; + elsif led_counter = 0 then + tx_led <= '0'; + end if; + + end if; + end process; + +stat_op(15 downto 12) <= buf_stat_op(15 downto 12); +stat_op(11) <= tx_led; --tx led +stat_op(10) <= rx_led; --rx led +stat_op(9 downto 0) <= buf_stat_op(9 downto 0); + +-- Debug output +stat_debug(15 downto 0) <= rx_data; +stat_debug(17 downto 16) <= rx_k; +stat_debug(19 downto 18) <= (others => '0'); +stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0); +stat_debug(41 downto 24) <= (others => '0'); +stat_debug(42) <= ff_txhalfclk; -- CHANGED +stat_debug(43) <= ff_txhalfclk; -- CHANGED +stat_debug(59 downto 44) <= (others => '0'); +stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0); --link_error(3 downto 0); + +--stat_debug(3 downto 0) <= buf_stat_debug(3 downto 0); -- state_bits +--stat_debug(4) <= buf_stat_debug(4); -- alignme +--stat_debug(5) <= sfp_prsnt_n; +--stat_debug(6) <= tx_k(0); +--stat_debug(7) <= tx_k(1); +--stat_debug(8) <= rx_k_q(0); +--stat_debug(9) <= rx_k_q(1); +--stat_debug(18 downto 10) <= link_error; +--stat_debug(19) <= '0'; +--stat_debug(20) <= link_ok(0); +--stat_debug(38 downto 21) <= fifo_rx_din; +--stat_debug(39) <= swap_bytes; +--stat_debug(40) <= buf_stat_debug(7); -- sfp_missing_in +--stat_debug(41) <= buf_stat_debug(8); -- sfp_los_in +--stat_debug(42) <= buf_stat_debug(6); -- resync +--stat_debug(59 downto 43) <= (others => '0'); +--stat_debug(63 downto 60) <= link_error(3 downto 0); + +end architecture; \ No newline at end of file -- 2.43.0