From 36e98aacae4c4a8f07565efedcb3f5fbf6938051 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Fri, 19 Aug 2022 08:19:25 +0200 Subject: [PATCH] seems to work now --- gbe_trb_ecp3/media/gbe_med_fifo.vhd | 77 ++++++++++++++++++----- gbe_trb_ecp3/media/serdes_gbe_4ch_ds.lpc | 6 +- gbe_trb_ecp3/media/serdes_gbe_4ch_ds.vhd | 78 +++++++++++++----------- trb_net16_endpoint_standalone_sctrl.vhd | 37 +++++------ 4 files changed, 122 insertions(+), 76 deletions(-) diff --git a/gbe_trb_ecp3/media/gbe_med_fifo.vhd b/gbe_trb_ecp3/media/gbe_med_fifo.vhd index 58888e8..54571bd 100644 --- a/gbe_trb_ecp3/media/gbe_med_fifo.vhd +++ b/gbe_trb_ecp3/media/gbe_med_fifo.vhd @@ -66,6 +66,7 @@ entity gbe_med_fifo is MASTER_CLK_OUT : out std_logic; -- recovered RX clock from slave port, if any TX_CLK_AVAIL_OUT : out std_logic; -- slave port has valid RX recovered clock SYNC_TX_PLL_IN : in std_logic; + WAP_REQUESTED_IN : in std_logic_vector(3 downto 0); -- TESTTESTTEST -- DLM DLM_INJECT_IN : in std_logic_vector(3 downto 0) := (others => '0'); DLM_DATA_IN : in std_logic_vector(4 * 8 - 1 downto 0) := (others => '0'); @@ -73,6 +74,7 @@ entity gbe_med_fifo is DLM_DATA_OUT : out std_logic_vector(4 * 8 - 1 downto 0); DLM_CLK_OUT : out std_logic_vector(3 downto 0); -- Debug + WAP_OUT : out std_logic_vector(15 downto 0); STATUS_OUT : out std_logic_vector(4 * 8 - 1 downto 0); DEBUG_OUT : out std_logic_vector(127 downto 0) ); @@ -202,7 +204,6 @@ architecture gbe_med_fifo_arch of gbe_med_fifo is signal sd_rx_kcntl_dst : std_logic_vector(3 downto 0); signal sd_rx_clk : std_logic_vector(3 downto 0); - signal sd_tx_clk : std_logic_vector(3 downto 0); signal xmit : std_logic_vector(3 downto 0); signal sd_rx_disp_error : std_logic_vector(3 downto 0); signal sd_rx_cv_error : std_logic_vector(3 downto 0); @@ -289,7 +290,17 @@ architecture gbe_med_fifo_arch of gbe_med_fifo is -- attribute HGROUP of gbe_med_fifo_arch : architecture is "gbe_med_fifo_group"; -- attribute BBOX of ddmtd_arch : architecture is "2,2"; - signal quad_mode : integer range 0 to 100; + signal sci_ch_i : std_logic_vector(4 downto 0); + signal sci_addr_i : std_logic_vector(5 downto 0); + signal sci_data_in_i : std_logic_vector(7 downto 0); + signal sci_data_out_i : std_logic_vector(7 downto 0); + signal sci_read_i : std_logic; + signal sci_write_i : std_logic; + signal wa_position_i : std_logic_vector(15 downto 0) := x"ffff"; + signal wap_requested_i : std_logic_vector(15 downto 0); + signal is_wap_zero : std_logic_vector(3 downto 0); + + signal quad_mode : integer range 0 to 100; begin @@ -331,6 +342,14 @@ begin link_rx_ready(3) when (LINK_MODE(3) = c_IS_SLAVE) else '0'; +------------------------------------------------- +-- WAP request (for testing) +------------------------------------------------- + wap_requested_i(0*4+3 downto 0*4) <= WAP_REQUESTED_IN when (LINK_MODE(0) = c_IS_MASTER) else x"0"; + wap_requested_i(1*4+3 downto 1*4) <= WAP_REQUESTED_IN when (LINK_MODE(1) = c_IS_MASTER) else x"0"; + wap_requested_i(2*4+3 downto 2*4) <= WAP_REQUESTED_IN when (LINK_MODE(2) = c_IS_MASTER) else x"0"; + wap_requested_i(3*4+3 downto 3*4) <= WAP_REQUESTED_IN when (LINK_MODE(3) = c_IS_MASTER) else x"0"; + ------------------------------------------------- -- SerDes quad ------------------------------------------------- @@ -342,7 +361,7 @@ begin hdoutp_ch0 => SD_TXD_P_OUT(0), hdoutn_ch0 => SD_TXD_N_OUT(0), rxiclk_ch0 => sd_rx_clk(0), - txiclk_ch0 => MASTER_CLK_IN, --sd_tx_clk(0), -- CLK_125 + txiclk_ch0 => MASTER_CLK_IN, -- CLK_125 rx_full_clk_ch0 => sd_rx_clk(0), rx_half_clk_ch0 => open, tx_full_clk_ch0 => open, @@ -372,7 +391,7 @@ begin hdoutp_ch1 => SD_TXD_P_OUT(1), hdoutn_ch1 => SD_TXD_N_OUT(1), rxiclk_ch1 => sd_rx_clk(1), - txiclk_ch1 => MASTER_CLK_IN, --sd_tx_clk(1), -- CLK_125, + txiclk_ch1 => MASTER_CLK_IN, -- CLK_125, rx_full_clk_ch1 => sd_rx_clk(1), rx_half_clk_ch1 => open, tx_full_clk_ch1 => open, @@ -402,7 +421,7 @@ begin hdoutp_ch2 => SD_TXD_P_OUT(2), hdoutn_ch2 => SD_TXD_N_OUT(2), rxiclk_ch2 => sd_rx_clk(2), - txiclk_ch2 => MASTER_CLK_IN, --sd_tx_clk(2), -- CLK_125, + txiclk_ch2 => MASTER_CLK_IN, -- CLK_125, rx_full_clk_ch2 => sd_rx_clk(2), rx_half_clk_ch2 => open, tx_full_clk_ch2 => open, @@ -432,7 +451,7 @@ begin hdoutp_ch3 => SD_TXD_P_OUT(3), hdoutn_ch3 => SD_TXD_N_OUT(3), rxiclk_ch3 => sd_rx_clk(3), - txiclk_ch3 => MASTER_CLK_IN, --sd_tx_clk(3), -- CLK_125, + txiclk_ch3 => MASTER_CLK_IN, -- CLK_125, rx_full_clk_ch3 => sd_rx_clk(3), rx_half_clk_ch3 => open, tx_full_clk_ch3 => open, @@ -462,17 +481,40 @@ begin tx_pll_lol_qd_s => tx_plol_lol, rst_qd_c => CLEAR, -- ONLY ONCE serdes_rst_qd_c => '0', - tx_sync_qd_c => SYNC_TX_PLL_IN --'0' + tx_sync_qd_c => SYNC_TX_PLL_IN, --'0' + -- SCI interface + SCI_WRDATA => sci_data_in_i, + SCI_RDDATA => sci_data_out_i, + SCI_ADDR => sci_addr_i, + SCI_SEL_QUAD => sci_ch_i(4), + SCI_SEL_CH0 => sci_ch_i(0), + SCI_SEL_CH1 => sci_ch_i(1), + SCI_SEL_CH2 => sci_ch_i(2), + SCI_SEL_CH3 => sci_ch_i(3), + SCI_RD => sci_read_i, + SCI_WRN => sci_write_i ); TX_PLOL_LOL_OUT <= tx_plol_lol; - -- workaround for clock domain problem --- sd_tx_clk(0) <= MASTER_CLK_IN; --- sd_tx_clk(1) <= MASTER_CLK_IN; --- sd_tx_clk(2) <= MASTER_CLK_IN; --- sd_tx_clk(3) <= MASTER_CLK_IN; - + -- SCI reader for WAP position + THE_SCI_READER : entity work.gbe_sci_reader + port map( + CLK => CLK_125, + RESET => CLEAR, -- needed for link establishment + --SCI + SCI_WRDATA => sci_data_in_i, + SCI_RDDATA => sci_data_out_i, + SCI_ADDR => sci_addr_i, + SCI_SEL => sci_ch_i, + SCI_RD => sci_read_i, + SCI_WR => sci_write_i, + -- WAP + WA_POS_OUT => wa_position_i + ); + + WAP_OUT <= wa_position_i; + -- in case we have no uplink port... NO_LOCAL_GEN: if (quad_mode < 8) generate MAC_RX_DATA_OUT <= (others => '0'); @@ -516,8 +558,8 @@ begin DEBUG_OUT((i + 1) * 32 - 2) <= '0'; DEBUG_OUT((i + 1) * 32 - 3) <= '0'; DEBUG_OUT((i + 1) * 32 - 4) <= '0'; - DEBUG_OUT((i + 1) * 32 - 5) <= '0'; - DEBUG_OUT((i + 1) * 32 - 6) <= '0'; + DEBUG_OUT((i + 1) * 32 - 5) <= is_wap_zero(i); + DEBUG_OUT((i + 1) * 32 - 6) <= sci_read_i; DEBUG_OUT((i + 1) * 32 - 7) <= tx_clk_avail_i; DEBUG_OUT((i + 1) * 32 - 8) <= link_active(i); DEBUG_OUT((i + 1) * 32 - 9) <= mac_ready_conf(i); @@ -558,7 +600,7 @@ begin CV_IN => sd_rx_cv_error(i), LSM_IN => lsm_status(i), LOS_IN => rx_los_low(i), - WAP_ZERO_IN => '1', -- not needed here + WAP_ZERO_IN => is_wap_zero(i), --'1', -- not needed here -- outputs WAP_REQ_OUT => open, -- not needed here RX_SERDES_RST_OUT => rx_serdes_rst(i), -- CLK_REF based @@ -567,6 +609,9 @@ begin STATE_OUT => open ); + -- BUG, WAP_REQUESTED_IN to be replaced by wap_requested_i() + is_wap_zero(i) <= '1' when (wa_position_i(i * 4 + 3 downto i * 4) = WAP_REQUESTED_IN) else '0'; + -- reset signals for RX SerDes need to be sync'ed to real RX clock for ECP5 SYNC_RST_SIGS: entity work.signal_sync generic map( WIDTH => 2 ) diff --git a/gbe_trb_ecp3/media/serdes_gbe_4ch_ds.lpc b/gbe_trb_ecp3/media/serdes_gbe_4ch_ds.lpc index be4479f..dc76923 100644 --- a/gbe_trb_ecp3/media/serdes_gbe_4ch_ds.lpc +++ b/gbe_trb_ecp3/media/serdes_gbe_4ch_ds.lpc @@ -16,8 +16,8 @@ CoreRevision=8.2 ModuleName=serdes_gbe_4ch_ds SourceFormat=VHDL ParameterFileVersion=1.0 -Date=07/01/2022 -Time=17:42:19 +Date=08/18/2022 +Time=21:03:42 [Parameters] Verilog=0 @@ -242,7 +242,7 @@ _rx_los_port0=Internal _rx_los_port1=Internal _rx_los_port2=Internal _rx_los_port3=Internal -_sci_ports=DISABLED +_sci_ports=ENABLED _sci_int_port=DISABLED _refck2core=DISABLED Regen=auto diff --git a/gbe_trb_ecp3/media/serdes_gbe_4ch_ds.vhd b/gbe_trb_ecp3/media/serdes_gbe_4ch_ds.vhd index 5585dd1..ae8bac5 100644 --- a/gbe_trb_ecp3/media/serdes_gbe_4ch_ds.vhd +++ b/gbe_trb_ecp3/media/serdes_gbe_4ch_ds.vhd @@ -1537,6 +1537,7 @@ entity serdes_gbe_4ch_ds is -- CH0 -- hdinp_ch0, hdinn_ch0 : in std_logic; hdoutp_ch0, hdoutn_ch0 : out std_logic; + sci_sel_ch0 : in std_logic; rxiclk_ch0 : in std_logic; txiclk_ch0 : in std_logic; rx_full_clk_ch0 : out std_logic; @@ -1565,6 +1566,7 @@ entity serdes_gbe_4ch_ds is -- CH1 -- hdinp_ch1, hdinn_ch1 : in std_logic; hdoutp_ch1, hdoutn_ch1 : out std_logic; + sci_sel_ch1 : in std_logic; rxiclk_ch1 : in std_logic; txiclk_ch1 : in std_logic; rx_full_clk_ch1 : out std_logic; @@ -1593,6 +1595,7 @@ entity serdes_gbe_4ch_ds is -- CH2 -- hdinp_ch2, hdinn_ch2 : in std_logic; hdoutp_ch2, hdoutn_ch2 : out std_logic; + sci_sel_ch2 : in std_logic; rxiclk_ch2 : in std_logic; txiclk_ch2 : in std_logic; rx_full_clk_ch2 : out std_logic; @@ -1621,6 +1624,7 @@ entity serdes_gbe_4ch_ds is -- CH3 -- hdinp_ch3, hdinn_ch3 : in std_logic; hdoutp_ch3, hdoutn_ch3 : out std_logic; + sci_sel_ch3 : in std_logic; rxiclk_ch3 : in std_logic; txiclk_ch3 : in std_logic; rx_full_clk_ch3 : out std_logic; @@ -1647,6 +1651,12 @@ entity serdes_gbe_4ch_ds is lsm_status_ch3_s : out std_logic; rx_cdr_lol_ch3_s : out std_logic; ---- Miscillaneous ports + sci_wrdata : in std_logic_vector (7 downto 0); + sci_addr : in std_logic_vector (5 downto 0); + sci_rddata : out std_logic_vector (7 downto 0); + sci_sel_quad : in std_logic; + sci_rd : in std_logic; + sci_wrn : in std_logic; fpga_txrefclk : in std_logic; tx_serdes_rst_c : in std_logic; tx_pll_lol_qd_s : out std_logic; @@ -2290,8 +2300,8 @@ port map ( PCIE_POWERDOWN_0_1 => fpsc_vlo, PCIE_RXVALID_0 => open, PCIE_PHYSTATUS_0 => open, - SCISELCH0 => fpsc_vlo, - SCIENCH0 => fpsc_vlo, + SCISELCH0 => sci_sel_ch0, + SCIENCH0 => fpsc_vhi, FF_RXI_CLK_0 => rxiclk_ch0, FF_TXI_CLK_0 => txiclk_ch0, FF_EBRD_CLK_0 => fpsc_vlo, @@ -2396,8 +2406,8 @@ port map ( PCIE_POWERDOWN_1_1 => fpsc_vlo, PCIE_RXVALID_1 => open, PCIE_PHYSTATUS_1 => open, - SCISELCH1 => fpsc_vlo, - SCIENCH1 => fpsc_vlo, + SCISELCH1 => sci_sel_ch1, + SCIENCH1 => fpsc_vhi, FF_RXI_CLK_1 => rxiclk_ch1, FF_TXI_CLK_1 => txiclk_ch1, FF_EBRD_CLK_1 => fpsc_vlo, @@ -2502,8 +2512,8 @@ port map ( PCIE_POWERDOWN_2_1 => fpsc_vlo, PCIE_RXVALID_2 => open, PCIE_PHYSTATUS_2 => open, - SCISELCH2 => fpsc_vlo, - SCIENCH2 => fpsc_vlo, + SCISELCH2 => sci_sel_ch2, + SCIENCH2 => fpsc_vhi, FF_RXI_CLK_2 => rxiclk_ch2, FF_TXI_CLK_2 => txiclk_ch2, FF_EBRD_CLK_2 => fpsc_vlo, @@ -2608,8 +2618,8 @@ port map ( PCIE_POWERDOWN_3_1 => fpsc_vlo, PCIE_RXVALID_3 => open, PCIE_PHYSTATUS_3 => open, - SCISELCH3 => fpsc_vlo, - SCIENCH3 => fpsc_vlo, + SCISELCH3 => sci_sel_ch3, + SCIENCH3 => fpsc_vhi, FF_RXI_CLK_3 => rxiclk_ch3, FF_TXI_CLK_3 => txiclk_ch3, FF_EBRD_CLK_3 => fpsc_vlo, @@ -2703,32 +2713,32 @@ port map ( FFC_RATE_MODE_RX_3 => fpsc_vlo, ----- Auxilliary ---- - SCIWDATA7 => fpsc_vlo, - SCIWDATA6 => fpsc_vlo, - SCIWDATA5 => fpsc_vlo, - SCIWDATA4 => fpsc_vlo, - SCIWDATA3 => fpsc_vlo, - SCIWDATA2 => fpsc_vlo, - SCIWDATA1 => fpsc_vlo, - SCIWDATA0 => fpsc_vlo, - SCIADDR5 => fpsc_vlo, - SCIADDR4 => fpsc_vlo, - SCIADDR3 => fpsc_vlo, - SCIADDR2 => fpsc_vlo, - SCIADDR1 => fpsc_vlo, - SCIADDR0 => fpsc_vlo, - SCIRDATA7 => open, - SCIRDATA6 => open, - SCIRDATA5 => open, - SCIRDATA4 => open, - SCIRDATA3 => open, - SCIRDATA2 => open, - SCIRDATA1 => open, - SCIRDATA0 => open, - SCIENAUX => fpsc_vlo, - SCISELAUX => fpsc_vlo, - SCIRD => fpsc_vlo, - SCIWSTN => fpsc_vlo, + SCIWDATA7 => sci_wrdata(7), + SCIWDATA6 => sci_wrdata(6), + SCIWDATA5 => sci_wrdata(5), + SCIWDATA4 => sci_wrdata(4), + SCIWDATA3 => sci_wrdata(3), + SCIWDATA2 => sci_wrdata(2), + SCIWDATA1 => sci_wrdata(1), + SCIWDATA0 => sci_wrdata(0), + SCIADDR5 => sci_addr(5), + SCIADDR4 => sci_addr(4), + SCIADDR3 => sci_addr(3), + SCIADDR2 => sci_addr(2), + SCIADDR1 => sci_addr(1), + SCIADDR0 => sci_addr(0), + SCIRDATA7 => sci_rddata(7), + SCIRDATA6 => sci_rddata(6), + SCIRDATA5 => sci_rddata(5), + SCIRDATA4 => sci_rddata(4), + SCIRDATA3 => sci_rddata(3), + SCIRDATA2 => sci_rddata(2), + SCIRDATA1 => sci_rddata(1), + SCIRDATA0 => sci_rddata(0), + SCIENAUX => fpsc_vhi, + SCISELAUX => sci_sel_quad, + SCIRD => sci_rd, + SCIWSTN => sci_wrn, CYAWSTN => fpsc_vlo, SCIINT => open, FFC_CK_CORE_TX => fpga_txrefclk, diff --git a/trb_net16_endpoint_standalone_sctrl.vhd b/trb_net16_endpoint_standalone_sctrl.vhd index 6fbe930..39404ca 100644 --- a/trb_net16_endpoint_standalone_sctrl.vhd +++ b/trb_net16_endpoint_standalone_sctrl.vhd @@ -74,7 +74,6 @@ architecture arch of trb_net16_endpoint_standalone_sctrl is signal buf_IDRAM_DATA_OUT : std_logic_vector(15 downto 0); signal buf_IDRAM_ADDR_IN : std_logic_vector(2 downto 0); signal buf_IDRAM_WR_IN : std_logic; - signal buf_stat_onewire : std_logic_vector(31 downto 0); signal buf_COMMON_STAT_REG_IN : std_logic_vector(std_COMSTATREG*32-1 downto 0); signal buf_COMMON_CTRL_REG_OUT : std_logic_vector(std_COMCTRLREG*32-1 downto 0); @@ -264,7 +263,7 @@ begin WRITE_OUT=> buf_IDRAM_WR_IN, TEMP_OUT => temperature_i, ID_OUT => unique_id_i - ); + ); end generate; gen_1wire : if REGIO_USE_1WIRE_INTERFACE = c_YES generate @@ -272,7 +271,7 @@ begin generic map( USE_TEMPERATURE_READOUT => c_YES, CLK_PERIOD => 10 - ) + ) port map( CLK => CLK, RESET => RESET, @@ -285,8 +284,8 @@ begin WRITE_OUT=> buf_IDRAM_WR_IN, TEMP_OUT => temperature_i, ID_OUT => unique_id_i, - STAT => buf_stat_onewire - ); + STAT => open + ); end generate; gen_i2c : if REGIO_USE_1WIRE_INTERFACE = c_I2C generate @@ -294,7 +293,7 @@ begin generic map( USE_TEMPERATURE_READOUT => c_YES, CLK_PERIOD => 10 - ) + ) port map( CLK => CLK, RESET => RESET, @@ -308,8 +307,8 @@ begin WRITE_OUT => buf_IDRAM_WR_IN, TEMP_OUT => temperature_i, ID_OUT => unique_id_i, - STAT => buf_stat_onewire - ); + STAT => open + ); end generate; gen_i2c_tc : if REGIO_USE_1WIRE_INTERFACE = c_I2C_TC generate @@ -317,7 +316,7 @@ begin generic map( USE_TEMPERATURE_READOUT => c_YES, CLK_PERIOD => 10 - ) + ) port map( CLK => CLK, RESET => RESET, @@ -331,26 +330,18 @@ begin WRITE_OUT => buf_IDRAM_WR_IN, TEMP_OUT => temperature_i, ID_OUT => unique_id_i, - STAT => buf_stat_onewire - ); + STAT => open + ); end generate; ------------------------------------------------- -- Common Status Register ------------------------------------------------- --- proc_gen_common_stat_regs : process(REGIO_COMMON_STAT_REG_IN, temperature_i, buf_stat_onewire) --- begin --- buf_COMMON_STAT_REG_IN <= REGIO_COMMON_STAT_REG_IN; --- buf_COMMON_STAT_REG_IN(31 downto 20) <= temperature_i; --- buf_COMMON_STAT_REG_IN(131 downto 128) <= std_logic_vector(link_and_reset_status(3 downto 0)); --- buf_COMMON_STAT_REG_IN(319 downto 288) <= buf_stat_onewire; --- end process; - - proc_gen_common_stat_regs : process(REGIO_COMMON_STAT_REG_IN, temperature_i, buf_stat_onewire) + proc_gen_common_stat_regs : process(REGIO_COMMON_STAT_REG_IN, temperature_i) begin - buf_COMMON_STAT_REG_IN <= (others => '0'); - buf_COMMON_STAT_REG_IN(31 downto 20) <= temperature_i; - buf_COMMON_STAT_REG_IN(159 downto 32) <= REGIO_COMMON_STAT_REG_IN(159 downto 32); + buf_COMMON_STAT_REG_IN(19 downto 0) <= (others => '0'); + buf_COMMON_STAT_REG_IN(31 downto 20) <= temperature_i; + buf_COMMON_STAT_REG_IN(std_COMSTATREG*32-1 downto 32) <= REGIO_COMMON_STAT_REG_IN(std_COMSTATREG*32-1 downto 32); end process; -- 2.43.0