From 37b46a4e37e9a037ac75874632a74f7e2a49d911 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Tue, 25 Oct 2022 14:26:50 +0200 Subject: [PATCH] ECP3 works well now, link seems stable --- gbe_hub/trb3sc_gbe_hub.prj | 2 +- gbe_hub/trb3sc_gbe_hub.vhd | 8 ++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/gbe_hub/trb3sc_gbe_hub.prj b/gbe_hub/trb3sc_gbe_hub.prj index 66bbec5..790bfda 100644 --- a/gbe_hub/trb3sc_gbe_hub.prj +++ b/gbe_hub/trb3sc_gbe_hub.prj @@ -190,7 +190,7 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/base/remover.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/cores/fifo_inserter.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/cores/fifo_remover.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/parser.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/parser.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/rx_rb.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/tx_fifo.vhd" diff --git a/gbe_hub/trb3sc_gbe_hub.vhd b/gbe_hub/trb3sc_gbe_hub.vhd index 5697415..3ed1dc7 100644 --- a/gbe_hub/trb3sc_gbe_hub.vhd +++ b/gbe_hub/trb3sc_gbe_hub.vhd @@ -128,6 +128,7 @@ architecture trb3sc_arch of trb3sc_gbe_hub is signal tx_pll_lol_d_i : std_logic; signal tx_clk_avail_i : std_logic; signal tx_pcs_rst_i : std_logic; + signal rst_qd_c_i : std_logic; signal link_tx_ready_i : std_logic; signal status_raw : std_logic_vector(4 * 32 - 1 downto 0); @@ -415,6 +416,7 @@ begin -- 8 : fifo_eof -- 7..0: data +-- DBG(15 downto 0) <= debug_pcsd(15 downto 0); DBG(31 downto 0) <= debug_pcsd(31 downto 0); -- DBG(31 downto 16) <= debug_pcsc(111 downto 96); DBG(32) <= '0'; @@ -669,6 +671,7 @@ begin SD_TXDIS_OUT(3) => open, -- SerDes control TX_PLOL_LOL_OUT => tx_pll_lol_a_i, + RST_QD_C_IN => rst_qd_c_i, TX_PCS_RST_IN => tx_pcs_rst_i, RX_LINK_READY_OUT => open, TX_LINK_READY_IN => link_tx_ready_i, @@ -778,6 +781,7 @@ begin SD_TXDIS_OUT(3) => HUB_TXDIS(8), --open, -- SerDes control TX_PLOL_LOL_OUT => tx_pll_lol_b_i, + RST_QD_C_IN => rst_qd_c_i, TX_PCS_RST_IN => tx_pcs_rst_i, RX_LINK_READY_OUT => open, TX_LINK_READY_IN => link_tx_ready_i, @@ -885,6 +889,7 @@ begin SD_TXDIS_OUT(3) => HUB_TXDIS(2), -- SerDes control TX_PLOL_LOL_OUT => tx_pll_lol_c_i, + RST_QD_C_IN => rst_qd_c_i, TX_PCS_RST_IN => tx_pcs_rst_i, RX_LINK_READY_OUT => open, TX_LINK_READY_IN => link_tx_ready_i, @@ -965,6 +970,7 @@ begin MAC_RX_ERROR_OUT => sniffer_error, -- SerDes control TX_PLOL_LOL_OUT => tx_pll_lol_d_i, + RST_QD_C_IN => rst_qd_c_i, TX_PCS_RST_IN => tx_pcs_rst_i, RX_LINK_READY_OUT => open, TX_LINK_READY_IN => link_tx_ready_i, @@ -1007,6 +1013,8 @@ begin global_reset_i <= not tx_clk_avail_i; -- keep everything in reset until we get some clock + rst_qd_c_i <= clear_i; + --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- -- 2.43.0