From 38c8e566b696aa0d98b41ea16b5c06f8ba08405d Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Thu, 14 Apr 2022 14:51:43 +0200 Subject: [PATCH] DDMTD continued --- special/ddmtd.vhd | 62 +++++++++++++++++++++++++++++++++++++------- special/deglitch.vhd | 4 +-- 2 files changed, 54 insertions(+), 12 deletions(-) diff --git a/special/ddmtd.vhd b/special/ddmtd.vhd index 1f1d35e..c5c3add 100644 --- a/special/ddmtd.vhd +++ b/special/ddmtd.vhd @@ -13,9 +13,10 @@ port( PING_OUT : out std_logic; -- stretched TX_K signal PONG_OUT : out std_logic; -- stretched RX_K signal START_PING_OUT : out std_logic; -- rising edge of stretched TX_K signal - START_PONG_OUT : out std_logic; -- rising edge of stretched RX_K signal - TOGGLE_OUT : out std_logic; - BEAT_OUT : out std_logic + START_PONG_OUT : out std_logic; -- rising edge of stretched RX_K signal + DELAY_VALUE_OUT : out std_logic_vector(15 downto 0); + DELAY_VALID_OUT : out std_logic; + TOGGLE_OUT : out std_logic -- for checking by scope ); end entity ddmtd; @@ -23,12 +24,16 @@ architecture ddmtd_arch of ddmtd is signal ping_q : std_logic_vector(2 downto 0); signal pong_q : std_logic_vector(2 downto 0); - signal beat_xor_x : std_logic; - signal beat_xor_q : std_logic; signal toggle_q : std_logic; signal start_ping_i : std_logic; signal start_pong_i : std_logic; + signal delay_ce : std_logic; + signal delay_rst : std_logic; + signal delay_ctr : unsigned(9 downto 0); + signal delay_store : std_logic; + signal delay_valid : std_logic; + signal delay_data : std_logic_vector(15 downto 0); attribute HGROUP : string; -- attribute BBOX : string; @@ -48,7 +53,6 @@ begin ping_q <= ping_q(1 downto 0) & PING_IN; pong_q <= pong_q(1 downto 0) & PONG_IN; -- register stages - beat_xor_q <= beat_xor_x; end if; end process THE_SAMPLER_PROC; @@ -70,8 +74,46 @@ port map( START_OUT => start_pong_i ); --- XOR of both stretched signals -beat_xor_x <= ping_q(1) xor pong_q(1); +-- delay counter +THE_DELAY_CTR_PROC: process( AUXCLK, RESET ) +begin + if ( RESET = '1' ) then + delay_ctr <= (others => '0'); + elsif( rising_edge(AUXCLK) ) then + if ( delay_rst = '1' ) then + delay_ctr <= (others => '0'); + elsif( delay_ce = '1' ) then + delay_ctr <= delay_ctr + 1; + end if; + end if; +end process THE_DELAY_CTR_PROC; + +delay_rst <= start_pong_i; +delay_store <= start_pong_i; + +THE_DELAY_CE_PROC: process( AUXCLK, RESET ) +begin + if ( RESET = '1' ) then + delay_ce <= '0'; + elsif( rising_edge(AUXCLK) ) then + if ( (start_ping_i = '1') and (start_pong_i = '0') ) then + delay_ce <= '1'; + elsif( (start_pong_i = '1') ) then + delay_ce <= '0'; + end if; + end if; +end process THE_DELAY_CE_PROC; + +THE_DELAY_STORE_PROC: process( AUXCLK, RESET ) +begin + if ( RESET = '1' ) then + delay_data <= (others => '0'); + elsif( rising_edge(AUXCLK) ) then + if( delay_store = '1' ) then + delay_data <= b"000000" & std_logic_vector(delay_ctr); + end if; + end if; +end process THE_DELAY_STORE_PROC; -- toggle bit for clock check THE_TOGGLE_PROC: process( AUXCLK, RESET ) @@ -87,8 +129,8 @@ PING_OUT <= ping_q(1); PONG_OUT <= pong_q(1); START_PING_OUT <= start_ping_i; START_PONG_OUT <= start_pong_i; - +DELAY_VALUE_OUT <= delay_data; +DELAY_VALID_OUT <= delay_valid; TOGGLE_OUT <= toggle_q; -BEAT_OUT <= beat_xor_q; end architecture; diff --git a/special/deglitch.vhd b/special/deglitch.vhd index d2ba61b..3931f05 100644 --- a/special/deglitch.vhd +++ b/special/deglitch.vhd @@ -54,8 +54,8 @@ begin end if; end process THE_UP_DOWN_COUNTER_PROC; -ctr_up_x <= '1' when ( (SIGNAL_IN = '1') and (deglitch_q(7) = '0') ) else '0'; -ctr_down_x <= '1' when ( (SIGNAL_IN = '0') and (deglitch_q(7) = '1') ) else '0'; +ctr_up_x <= '1' when ( (SIGNAL_IN = '1') and (deglitch_q(7) = '0') and (counter < 8) ) else '0'; +ctr_down_x <= '1' when ( (SIGNAL_IN = '0') and (deglitch_q(7) = '1') and (counter > 0) ) else '0'; --start_x <= '1' when ( counter = x"4" ) else '0'; start_x <= '1' when ( (counter = x"3") and (ctr_up_x = '1') ) else '0'; -- 2.43.0