From 392d9f925be625a978762070db957f2394ffaab9 Mon Sep 17 00:00:00 2001 From: Andreas Neiser Date: Fri, 27 Feb 2015 14:23:11 +0100 Subject: [PATCH] statebits also to ADC clock domain --- ADC/source/adc_processor_cfd.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ADC/source/adc_processor_cfd.vhd b/ADC/source/adc_processor_cfd.vhd index dc8d58e..00a5876 100644 --- a/ADC/source/adc_processor_cfd.vhd +++ b/ADC/source/adc_processor_cfd.vhd @@ -107,7 +107,7 @@ begin READOUT_TX.data_write <= RDO_write_main when rising_edge(CLK_SYS); READOUT_TX.data <= RDO_data_main when rising_edge(CLK_SYS); readout_reset <= CONTROL(12) when rising_edge(CLK_SYS); - statebits <= std_logic_vector(to_unsigned(state_t'pos(state), 8)); + statebits <= std_logic_vector(to_unsigned(state_t'pos(state), 8)) when rising_edge(CLK_ADC); proc_readout : process variable channelselect : integer range 0 to 3; -- 2.43.0