From 3cc07e0796cb2048040c79a20871b3a1a1eb78be Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 24 Feb 2014 12:08:15 +0100 Subject: [PATCH] added logic for trigger output to central hub --- trb3_gbe/trb3_central.prj | 2 +- trb3_gbe/trb3_central.vhd | 58 +++++++++++++++++++++++++++++++++++---- 2 files changed, 54 insertions(+), 6 deletions(-) diff --git a/trb3_gbe/trb3_central.prj b/trb3_gbe/trb3_central.prj index e40bf6b..f46e1a0 100644 --- a/trb3_gbe/trb3_central.prj +++ b/trb3_gbe/trb3_central.prj @@ -223,7 +223,7 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4_onboard.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4.vhd" - +add_file -vhdl -lib work "../base/code/input_to_trigger_logic.vhd" add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd" add_file -vhdl -lib work "./trb3_central.vhd" diff --git a/trb3_gbe/trb3_central.vhd b/trb3_gbe/trb3_central.vhd index 4ff8eda..7588e4f 100644 --- a/trb3_gbe/trb3_central.vhd +++ b/trb3_gbe/trb3_central.vhd @@ -29,6 +29,7 @@ entity trb3_central is TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out -- TRIGGER_EXT : in std_logic_vector(4 downto 2); --additional trigger from RJ45 TRIGGER_OUT : out std_logic; --trigger to second input of fan-out + TRIGGER_OUT2 : out std_logic; --trigger output on RJ45 --Serdes CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 2/0, 200 MHz, only in case of problems CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 1/0, off, 125 MHz possible @@ -259,6 +260,15 @@ signal select_tc_write : std_logic; signal select_tc_read : std_logic; signal select_tc_ack : std_logic; +signal trig_outputs : std_logic_vector(4 downto 0); +signal trig_inputs : std_logic_vector(15 downto 0); +signal trig_din : std_logic_vector(31 downto 0); +signal trig_dout : std_logic_vector(31 downto 0); +signal trig_write : std_logic := '0'; +signal trig_read : std_logic := '0'; +signal trig_ack : std_logic := '0'; +signal trig_nack : std_logic := '0'; +signal trig_addr : std_logic_vector(15 downto 0) := (others => '0'); signal debug : std_logic_vector(63 downto 0); @@ -742,9 +752,9 @@ end generate; --------------------------------------------------------------------------- THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 6, - PORT_ADDRESSES => (0 => x"d000", 1 => x"8100", 2 => x"8300", 3 => x"b000", 4 => x"b200", 5 => x"d300", others => x"0000"), - PORT_ADDR_MASK => (0 => 9, 1 => 8, 2 => 8, 3 => 9, 4 => 9, 5 => '0', others => 0) + PORT_NUMBER => 7, + PORT_ADDRESSES => (0 => x"d000", 1 => x"8100", 2 => x"8300", 3 => x"b000", 4 => x"b200", 5 => x"d300", 6 => x"cf00", others => x"0000"), + PORT_ADDR_MASK => (0 => 9, 1 => 8, 2 => 8, 3 => 9, 4 => 9, 5 => 0, 6 => 6, others => 0) ) port map( CLK => clk_sys_i, @@ -837,6 +847,17 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler BUS_NO_MORE_DATA_IN(5) => '0', BUS_UNKNOWN_ADDR_IN(5) => '0', + --Trigger logic registers + BUS_READ_ENABLE_OUT(6) => trig_read, + BUS_WRITE_ENABLE_OUT(6) => trig_write, + BUS_DATA_OUT(6*32+31 downto 6*32) => trig_din, + BUS_ADDR_OUT(6*16+15 downto 6*16) => trig_addr, + BUS_TIMEOUT_OUT(6) => open, + BUS_DATA_IN(6*32+31 downto 6*32) => trig_dout, + BUS_DATAREADY_IN(6) => trig_ack, + BUS_WRITE_ACK_IN(6) => trig_ack, + BUS_NO_MORE_DATA_IN(6) => '0', + BUS_UNKNOWN_ADDR_IN(6) => trig_nack, STAT_DEBUG => open ); @@ -869,15 +890,42 @@ THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload SPI_SDI_IN => FLASH_DOUT ); +--------------------------------------------------------------------------- +-- Trigger logic +--------------------------------------------------------------------------- + THE_TRIG_LOGIC : input_to_trigger_logic + generic map( + INPUTS => 16, + OUTPUTS => 5 + ) + port map( + CLK => clk_sys_i, + + INPUT => trig_inputs, + OUTPUT => trig_outputs, + + DATA_IN => trig_din, + DATA_OUT => trig_dout, + WRITE_IN => trig_write, + READ_IN => trig_read, + ACK_OUT => trig_ack, + NACK_OUT => trig_nack, + ADDR_IN => trig_addr + ); + +TRIGGER_OUT2 <= trig_outputs(0); +trig_inputs <= FPGA4_COMM(10 downto 7) & FPGA3_COMM(10 downto 7) & FPGA2_COMM(10 downto 7) & FPGA1_COMM(10 downto 7); + + --------------------------------------------------------------------------- -- Clock and Trigger Configuration --------------------------------------------------------------------------- process begin - wait until rising_edge(clk_100_i); + wait until rising_edge(clk_sys_i); if reset_i = '1' then - select_tc <= x"00000000"; --always internal trigger source + select_tc <= x"00000000"; --always external trigger source elsif select_tc_write = '1' then select_tc <= select_tc_data_in; end if; -- 2.43.0