From 3d341ab15323ff18da3ac7c0ee1f42c051dadc04 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 13 Jun 2022 10:19:18 +0200 Subject: [PATCH] update template project with latest files, move to 3.12 --- template/config.vhd | 2 +- template/config_compile_frankfurt.pl | 4 ++-- template/trb5sc_template.prj | 4 +++- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/template/config.vhd b/template/config.vhd index 4757bc0..2825860 100644 --- a/template/config.vhd +++ b/template/config.vhd @@ -12,7 +12,7 @@ package config is --set to 0 for backplane serdes, set to 1 for SFP serdes - constant SERDES_NUM : integer := 0; + constant SERDES_NUM : integer := 1; --TDC settings constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5 diff --git a/template/config_compile_frankfurt.pl b/template/config_compile_frankfurt.pl index a681cf6..9dc053b 100644 --- a/template/config_compile_frankfurt.pl +++ b/template/config_compile_frankfurt.pl @@ -7,8 +7,8 @@ Speedgrade => '8', TOPNAME => "trb5sc_template", lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1702\@jspc29", -lattice_path => '/d/jspc29/lattice/diamond/3.10_x64', -synplify_path => '/d/jspc29/lattice/synplify/O-2018.09-SP1/', +lattice_path => '/d/jspc29/lattice/diamond/3.12', +synplify_path => '/d/jspc29/lattice/synplify/R-2020.09-SP1/', nodelist_file => '../nodelist_frankfurt.txt', pinout_file => 'trb5sc_tdc', diff --git a/template/trb5sc_template.prj b/template/trb5sc_template.prj index af55465..49c2652 100644 --- a/template/trb5sc_template.prj +++ b/template/trb5sc_template.prj @@ -66,7 +66,7 @@ add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd" add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd" add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" -add_file -vhdl -lib work "../../dirich/code/sedcheck.vhd" +add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd" #Fifos @@ -153,6 +153,7 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync ########################################## add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd" add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" @@ -195,6 +196,7 @@ add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" -- 2.43.0