From 3d58674ac32c8e5e196c213b51e70f662662b825 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Wed, 29 Jun 2022 17:50:28 +0200 Subject: [PATCH] GBE template (WIP) --- gbe_template/README | 7 + gbe_template/compile.pl | 1 + gbe_template/config.vhd | 126 ++++++++++ gbe_template/config_compile_frankfurt.pl | 25 ++ gbe_template/config_compile_gsi.pl | 26 ++ gbe_template/nodelist_frankfurt.txt | 13 + gbe_template/par.p2t | 69 ++++++ gbe_template/trb5sc_gbe_template.lpf | 39 +++ gbe_template/trb5sc_gbe_template.prj | 301 +++++++++++++++++++++++ gbe_template/trb5sc_gbe_template.vhd | 297 ++++++++++++++++++++++ 10 files changed, 904 insertions(+) create mode 100644 gbe_template/README create mode 120000 gbe_template/compile.pl create mode 100644 gbe_template/config.vhd create mode 100644 gbe_template/config_compile_frankfurt.pl create mode 100644 gbe_template/config_compile_gsi.pl create mode 100644 gbe_template/nodelist_frankfurt.txt create mode 100644 gbe_template/par.p2t create mode 100644 gbe_template/trb5sc_gbe_template.lpf create mode 100644 gbe_template/trb5sc_gbe_template.prj create mode 100644 gbe_template/trb5sc_gbe_template.vhd diff --git a/gbe_template/README b/gbe_template/README new file mode 100644 index 0000000..eb6db9c --- /dev/null +++ b/gbe_template/README @@ -0,0 +1,7 @@ +The tdc repository branch has to be set to sep17. + +Run + +$ git checkout sep17 + +in tdc repository folder. diff --git a/gbe_template/compile.pl b/gbe_template/compile.pl new file mode 120000 index 0000000..933ff60 --- /dev/null +++ b/gbe_template/compile.pl @@ -0,0 +1 @@ +../../trb3/scripts/compile.pl \ No newline at end of file diff --git a/gbe_template/config.vhd b/gbe_template/config.vhd new file mode 100644 index 0000000..c91c178 --- /dev/null +++ b/gbe_template/config.vhd @@ -0,0 +1,126 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + + +--set to 0 for backplane serdes, set to 1 for SFP serdes + constant SERDES_NUM : integer := 1; + +--TDC settings + constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5 + constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons + constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 + -- 0: single edge only, + -- 1: same channel, + -- 2: alternating channels, + -- 3: same channel with stretcher + constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size + -- mode: 0, 1, 2, 3, 7 + -- size: 32, 64, 96, 128, dyn + constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC + -- 0: Single fine time as the sum of the two transitions + -- 1: Double fine time, individual transitions + -- 13: Debug - fine time + (if 0x3ff full chain) + -- 14: Debug - single fine time and the ROM addresses for the two transitions + -- 15: Debug - complete carry chain dump + + constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F570"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector; + + constant INCLUDE_UART : integer := c_YES; --300 slices + constant INCLUDE_SPI : integer := c_YES; --300 slices + constant INCLUDE_LCD : integer := c_NO; --800 slices + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; --400 slices @32->2 + constant INCLUDE_STATISTICS : integer := c_NO; --1300 slices, 1 RAM @32 + constant TRIG_GEN_INPUT_NUM : integer := 32; + constant TRIG_GEN_OUTPUT_NUM : integer := 4; + constant MONITOR_INPUT_NUM : integer := 32; + + constant FPGA_SIZE : string := "85KUM"; + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + + type data_t is array (0 to 1023) of std_logic_vector(7 downto 0); + constant LCD_DATA : data_t := (others => x"00"); + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"A5000000"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := std_logic_vector(to_unsigned(132-SERDES_NUM*3,8)); --81 (SFP) or 84 (Backplane) + + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1 + + t(7 downto 0) := std_logic_vector(to_unsigned(1,8)); + t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4)); + t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); + t(15) := '1'; --TDC + t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2)); + + t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := "0";--std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/gbe_template/config_compile_frankfurt.pl b/gbe_template/config_compile_frankfurt.pl new file mode 100644 index 0000000..9dc053b --- /dev/null +++ b/gbe_template/config_compile_frankfurt.pl @@ -0,0 +1,25 @@ +Familyname => 'ECP5UM', +Devicename => 'LFE5UM-85F', +Package => 'CABGA756', +Speedgrade => '8', + + +TOPNAME => "trb5sc_template", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@jspc29", +lattice_path => '/d/jspc29/lattice/diamond/3.12', +synplify_path => '/d/jspc29/lattice/synplify/R-2020.09-SP1/', + +nodelist_file => '../nodelist_frankfurt.txt', +pinout_file => 'trb5sc_tdc', +par_options => '../par.p2t', + + +#Include only necessary lpf files +include_TDC => 1, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used diff --git a/gbe_template/config_compile_gsi.pl b/gbe_template/config_compile_gsi.pl new file mode 100644 index 0000000..958ee69 --- /dev/null +++ b/gbe_template/config_compile_gsi.pl @@ -0,0 +1,26 @@ +Familyname => 'ECP5UM', +Devicename => 'LFE5UM-85F', +Package => 'CABGA756', +Speedgrade => '8', + +TOPNAME => "trb5sc_gbe_template", +lm_license_file_for_synplify => "27000\@lxcad04.gsi.de", +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/opt/lattice/diamond/3.12', +synplify_path => '/opt/synplicity/P-2019.09-SP1', +#synplify_command => "/opt/lattice/diamond/3.4_x64/bin/lin64/synpwrap -fg -options", +#synplify_command => "/opt/synplicity/P-2019.09-SP1/bin/synplify_premier_dp", +synplify_command => "/opt/synplicity/R-2020.09-SP1/bin/synplify_premier_dp", + +nodelist_file => "../nodelist_hades68.txt", +pinout_file => 'trb5sc_tdc', +par_options => '../par.p2t', + +#Include only necessary lpf files +include_TDC => 0, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used diff --git a/gbe_template/nodelist_frankfurt.txt b/gbe_template/nodelist_frankfurt.txt new file mode 100644 index 0000000..2e858da --- /dev/null +++ b/gbe_template/nodelist_frankfurt.txt @@ -0,0 +1,13 @@ +// nodes file for parallel place&route + +[jspc37] +SYSTEM = linux +CORENUM = 7 +ENV = /d/jspc29/lattice/310_settings.sh +WORKDIR = /d/jspc22/trb/git/trb5sc/template/workdir + +[jspc57] +SYSTEM = linux +CORENUM = 3 +ENV = /d/jspc29/lattice/310_settings.sh +WORKDIR = /d/jspc22/trb/git/trb5sc/template/workdir diff --git a/gbe_template/par.p2t b/gbe_template/par.p2t new file mode 100644 index 0000000..e168739 --- /dev/null +++ b/gbe_template/par.p2t @@ -0,0 +1,69 @@ +-w +#-y +-l 5 +#-m nodelist.txt # Controlled by the compile.pl script. +#-n 1 # Controlled by the compile.pl script. +-s 10 +-t 11 +-c 2 +-e 2 +-i 10 +#-exp parPlcInLimit=0 +#-exp parPlcInNeighborSize=1 +#General PAR Command Line Options +# -w With this option, any files generated will overwrite existing files +# (e.g., any .par, .pad files). +# -y Adds the Delay Summary Report in the .par file and creates the delay +# file (in .dly format) at the end of the par run. +# +#PAR Placement Command Line Options +# -l Specifies the effort level of the design from 1 (simplest designs) +# to 5 (most complex designs). +# -m Multi-tasking option. Controlled by the compile.pl script. +# -n Sets the number of iterations performed at the effort level +# specified by the -l option. Controlled by the compile.pl script. +# -s Save the number of best results for this run. +# -t Start placement at the specified cost table. Default is 1. +# +#PAR Routing Command Line Options +# -c Run number of cost-based cleanup passes of the router. +# -e Run number of delay-based cleanup passes of the router on +# completely-routed designs only. +# -i Run a maximum number of passes, stopping earlier only if the routing +# goes to 100 percent completion and all constraints are met. +# +#PAR Explorer Command Line Options +# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is +# compatible with all Lattice FPGA device families; however, most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families. +# parCDR Enable the congestion-driven router (CDR) algorithm. +# Congestion-driven options like parCDR and parCDP can improve +# performance given a design with multiple congestion “hotspots.” The +# Layer > Congestion option of the Design Planner Floorplan View can +# help visualize routing congestion. Large congested areas may prevent +# the options from finding a successful solution. +# CDR is compatible with all Lattice FPGA device families however most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families. +# paruseNBR NBR Router or Negotiation-based routing option. Supports all +# FPGA device families except LatticeXP and MachXO. +# When turned on, an alternate routing engine from the traditional +# Rip-up-based routing selection (RBR) is used. This involves an +# iterative routing algorithm that routes connections to achieve +# minimum delay cost. It does so by computing the demand on each +# routing resource and applying cost values per node. It will +# complete when an optimal solution is arrived at or the number of +# iterations is reached. +# parPathBased Path-based placement option. Path-based timing driven +# placement will yield better performance and more +# predictable results in many cases. +# parHold Additional hold time correction option. This option +# forces the router to automatically insert extra wires to compensate for the +# hold time violation. +# parHoldLimit This option allows you to set a limit on the number of +# hold time violations to be processed by the auto hold time correction option +# parHold. +# parPlcInLimit Cannot find in the online help +# parPlcInNeighborSize Cannot find in the online help +-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1 diff --git a/gbe_template/trb5sc_gbe_template.lpf b/gbe_template/trb5sc_gbe_template.lpf new file mode 100644 index 0000000..a3207b4 --- /dev/null +++ b/gbe_template/trb5sc_gbe_template.lpf @@ -0,0 +1,39 @@ +COMMERCIAL ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# + +FREQUENCY PORT "CLK_200" 200.000 MHz; +FREQUENCY PORT "CLK_125" 125.000 MHz; +FREQUENCY PORT "CLK_EXT" 200.000 MHz; + +FREQUENCY NET "GBE/physical/CLK_125_RX_OUT" 125.000 MHz; +FREQUENCY NET "GBE/physical/gbe_serdes/tx_pclk" 125.000 MHz; +FREQUENCY NET "clk_sys" 100.000 MHz; +FREQUENCY NET "CLK_125_c" 125.000 MHz; + +BLOCK PATH TO PORT "LED*"; +BLOCK PATH TO PORT "PROGRAMN"; +BLOCK PATH TO PORT "TEST*"; +BLOCK PATH TO PORT "HDR*"; + +#FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +#FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +# FREQUENCY NET "med_stat_debug[11]" 200 MHz; +#FREQUENCY NET "med2int_0.clk_full" 200 MHz; +# FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz; +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns; +#MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; +#MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; +#MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns; +#MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns; +#GSR_NET NET "clear_i"; +# LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ; +#REGION "MEDIA" "R81C44D" 13 25; +#LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ; + diff --git a/gbe_template/trb5sc_gbe_template.prj b/gbe_template/trb5sc_gbe_template.prj new file mode 100644 index 0000000..9809111 --- /dev/null +++ b/gbe_template/trb5sc_gbe_template.prj @@ -0,0 +1,301 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology ECP5UM +set_option -part LFE5UM_85F +set_option -package BG756C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb5sc_template" +set_option -resource_sharing false + +# map options +set_option -frequency 120 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +set_option -forcegsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true +set_option -multi_file_compilation_unit 1 + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb5sc_gbe_template.edf" +set_option log_file "workdir/trb5sc_project.srf" +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + +add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd" + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +#add_file -vhdl -lib work "tdc_release/tdc_version.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd" + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" + + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" + + +######################################### +#channel 0, backplane +#add_file -vhdl -lib work "../../dirich/cores/serdes_sync_0.vhd" +#add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v" + +#channel 1, SFP +#add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd" +#add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v" +########################################## + + +######################################### +#channel 0, backplane +#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd" + +#channel 1, SFP +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd" +########################################## + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd" +add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" + + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + +add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd" + + +#add_file -vhdl -lib work "tdc_release/tdc_components.vhd" +#add_file -vhdl -lib work "tdc_release/bit_sync.vhd" +#add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd" +#add_file -vhdl -lib work "tdc_release/Channel_200.vhd" +#add_file -vhdl -lib work "tdc_release/Channel.vhd" +#add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd" +#add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd" +#add_file -vhdl -lib work "tdc_release/hit_mux.vhd" +#add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd" +#add_file -vhdl -lib work "tdc_release/Readout_record.vhd" +#add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd" +#add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp5.vhd" +#add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd" +#add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd" +#add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd" +#add_file -vhdl -lib work "tdc_release/Stretcher.vhd" +#add_file -vhdl -lib work "tdc_release/TDC_record.vhd" +#add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd" +#add_file -vhdl -lib work "tdc_release/up_counter.vhd" + +#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/TDC/Adder_288/Adder_288.vhd" +#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd" +#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_OutReg/FIFO_DC_36x128_OutReg.vhd" +#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x64_OutReg/FIFO_DC_36x64_OutReg.vhd" +#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x32_OutReg/FIFO_DC_36x32_OutReg.vhd" +#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x128_OutReg/FIFO_36x128_OutReg.vhd" +#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x64_OutReg/FIFO_36x64_OutReg.vhd" +#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_36x32_OutReg.vhd" +#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out50/pll_in125_out50.vhd" +#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd" + +#GbE +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_wrapper_single.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_med_interface_single.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd" +add_file -verilog -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/serdes_gbe_softlogic.v" +# Choose your SerDes location here +#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch0/serdes_gbe.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch1/serdes_gbe.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch0/serdes_gbe.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch1/serdes_gbe.vhd" + +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32x8.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x72.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx16x8_mb2.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2048x8x16.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_65536x18x9.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/slv_mac_memory.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ip_mem.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af_cnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9_af_cnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2kx9x18_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4kx18x9_wcnt.vhd" + +add_file -vhdl -lib work "./trb5sc_gbe_template.vhd" +#add_file -fpga_constraint "./synplify.fdc" + + + diff --git a/gbe_template/trb5sc_gbe_template.vhd b/gbe_template/trb5sc_gbe_template.vhd new file mode 100644 index 0000000..088a646 --- /dev/null +++ b/gbe_template/trb5sc_gbe_template.vhd @@ -0,0 +1,297 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.med_sync_define.all; + +entity trb5sc_template is + port( + CLK_200 : in std_logic; + CLK_125 : in std_logic; + CLK_EXT : in std_logic; + -- + TRIG_IN_BACKPL : in std_logic; --Reference Time + TRIG_IN_RJ45 : in std_logic; --Reference Time + IN_SELECT_EXT_CLOCK : in std_logic; + -- + SPARE : out std_logic_vector(1 downto 0); -- trigger output 2+3 + BACK_GPIO : inout std_logic_vector(3 downto 0); --0: Serdes out, 1: Serdes in, 2,3: trigger output 0+1 + -- + SFP_TX_DIS : out std_logic; + SFP_LOS : in std_logic; + SFP_MOD_0 : in std_logic; + --AddOn +-- FE_GPIO : inout std_logic_vector(11 downto 0); +-- FE_CLK : out std_logic_vector( 2 downto 1); +-- FE_DIFF : inout std_logic_vector(63 downto 0); + INP : in std_logic_vector(63 downto 0); + -- + CS : out std_logic_vector(4 downto 1); + MISO : in std_logic_vector(4 downto 1); + MOSI : out std_logic; + SCK : out std_logic; + --ADC + ADC_SCLK : out std_logic; + ADC_NCS : out std_logic; + ADC_MOSI : out std_logic; + ADC_MISO : in std_logic; + --Flash, Reload + FLASH_SCLK : out std_logic; + FLASH_NCS : out std_logic; + FLASH_MOSI : out std_logic; + FLASH_MISO : in std_logic; + FLASH_HOLD : out std_logic; + FLASH_WP : out std_logic; + PROGRAMN : out std_logic; + --I2C + I2C_SDA : inout std_logic; + I2C_SCL : inout std_logic; + TMP_ALERT : in std_logic; + --LED + LED : out std_logic_vector(8 downto 1); + LED_SFP_YELLOW : out std_logic; + LED_SFP_GREEN : out std_logic; + LED_SFP_RED : out std_logic; + LED_RJ_GREEN : out std_logic_vector(1 downto 0); + LED_RJ_RED : out std_logic_vector(1 downto 0); + LED_EXT_CLOCK : out std_logic; + --Other Connectors + TEST : inout std_logic_vector(14 downto 1); + HDR_IO : inout std_logic_vector(15 downto 0) + ); + + + attribute syn_useioff : boolean; + attribute syn_useioff of FLASH_NCS : signal is true; + attribute syn_useioff of FLASH_SCLK : signal is true; + attribute syn_useioff of FLASH_MOSI : signal is true; + attribute syn_useioff of FLASH_MISO : signal is true; + + +end entity; + +architecture arch of trb5sc_template is + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys : std_logic; + signal clk_full : std_logic; + signal clk_full_osc : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + + signal sd_led_green : std_logic; + signal sd_led_red : std_logic; + signal sd_led_yellow : std_logic; + + signal uuid_i : std_logic_vector(63 downto 0); + + signal gsc_init_data : std_logic_vector(15 downto 0); + signal gsc_reply_data : std_logic_vector(15 downto 0); + signal gsc_init_read : std_logic; + signal gsc_reply_read : std_logic; + signal gsc_init_dataready : std_logic; + signal gsc_reply_dataready : std_logic; + signal gsc_init_packet_num : std_logic_vector(2 downto 0); + signal gsc_reply_packet_num : std_logic_vector(2 downto 0); + signal gsc_busy : std_logic; + + signal reboot_from_gbe : std_logic; + signal reset_via_gbe : std_logic; + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + signal debug : std_logic_vector(127 downto 0); + + signal status : std_logic_vector(15 downto 0); + + signal flash_ncs_i : std_logic; + + +begin + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- + THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + CLOCK_IN => CLK_200, + GLOBAL_RESET_IN => '0', + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + REF_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + RAW_CLK_OUT => clk_full_osc, + DEBUG_OUT => open + ); + +------------------------------------------------------------------------------- +-- UUID handling, needed as MAC for GbE +------------------------------------------------------------------------------- + THE_UUID_STUFF: trb_net_i2cwire + generic map( + USE_TEMPERATURE_READOUT => 1, + CLK_PERIOD => 10 + ) + port map( + CLK => clk_sys, + RESET => clear_i, + READOUT_ENABLE_IN => '1', + --connection to I2C interface + SCL_INOUT => I2C_SCL, + SDA_INOUT => I2C_SDA, + --connection to id ram, according to memory map in TrbNetRegIO + DATA_OUT => open, + ADDR_OUT => open, + WRITE_OUT => open, + TEMP_OUT => open, + ID_OUT => uuid_i, + STAT => open + ); + +--------------------------------------------------------------------------- +-- GbE +--------------------------------------------------------------------------- + GBE : entity work.gbe_wrapper_single + generic map( + DO_SIMULATION => 0, + INCLUDE_DEBUG => 0, + USE_INTERNAL_TRBNET_DUMMY => 0, + USE_EXTERNAL_TRBNET_DUMMY => 0, + RX_PATH_ENABLE => 1, + FIXED_SIZE_MODE => 1, + INCREMENTAL_MODE => 1, + FIXED_SIZE => 100, + FIXED_DELAY_MODE => 1, + UP_DOWN_MODE => 0, + UP_DOWN_LIMIT => 100, + FIXED_DELAY => 100, + + NUMBER_OF_GBE_LINKS => 1, + LINKS_ACTIVE => "0001", + + LINK_HAS_READOUT => "0000", + LINK_HAS_SLOWCTRL => "0001", + LINK_HAS_DHCP => "0001", + LINK_HAS_ARP => "0001", + LINK_HAS_PING => "0001", + LINK_HAS_FWD => "0000" + ) + port map( + CLK_SYS_IN => clk_sys, + CLK_125_IN => CLK_125, + RESET => reset_i, + GSR_N => GSR_N, + -- Trigger + TRIGGER_IN => '0', + -- SFP + SD_PRSNT_N_IN => SFP_MOD_0, + SD_LOS_IN => SFP_LOS, + SD_TXDIS_OUT => SFP_TX_DIS, + -- trigger channel + -- only for LINK_HAS_READOUT + CTS_NUMBER_IN => (others => '0'), + CTS_CODE_IN => (others => '0'), + CTS_INFORMATION_IN => (others => '0'), + CTS_READOUT_TYPE_IN => (others => '0'), + CTS_START_READOUT_IN => '0', + CTS_DATA_OUT => open, + CTS_DATAREADY_OUT => open, + CTS_READOUT_FINISHED_OUT => open, + CTS_READ_IN => '1', + CTS_LENGTH_OUT => open, + CTS_ERROR_PATTERN_OUT => open, + -- data channel + -- only for LINK_HAS_READOUT + FEE_DATA_IN => (others => '0'), + FEE_DATAREADY_IN => '0', + FEE_READ_OUT => open, + FEE_STATUS_BITS_IN => (others => '0'), + FEE_BUSY_IN => '0', + -- unique adresses + MC_UNIQUE_ID_IN => uuid_i, + MY_TRBNET_ADDRESS_IN => x"d00f", + ISSUE_REBOOT_OUT => reboot_from_gbe, + -- slow control by GbE + GSC_CLK_IN => clk_sys, + GSC_INIT_DATAREADY_OUT => open, + GSC_INIT_DATA_OUT => open, + GSC_INIT_PACKET_NUM_OUT => open, + GSC_INIT_READ_IN => '0', + GSC_REPLY_DATAREADY_IN => '0', + GSC_REPLY_DATA_IN => (others => '0'), + GSC_REPLY_PACKET_NUM_IN => (others => '0'), + GSC_REPLY_READ_OUT => open, + GSC_BUSY_IN => '0', + -- readout + BUS_IP_RX => open, + BUS_IP_TX => open, + BUS_REG_RX => open, + BUS_REG_TX => open, + -- Forwarder + FWD_DST_MAC_IN => (others => '0'), + FWD_DST_IP_IN => (others => '0'), + FWD_DST_UDP_IN => (others => '0'), + FWD_DATA_IN => (others => '0'), + FWD_DATA_VALID_IN => '0', + FWD_SOP_IN => '0', + FWD_EOP_IN => '0', + FWD_READY_OUT => open, + FWD_FULL_OUT => open, + -- reset + MAKE_RESET_OUT => reset_via_gbe, -- reset by GbE + -- debug and status + STATUS_OUT => status, --open, + DEBUG_OUT => debug --open + ); + +--------------------------------------------------------------------------- +-- I/Os +--------------------------------------------------------------------------- + --HDR_IO(15 downto 0) <= (others => '0'); + HDR_IO <= debug(15 downto 0); + + TEST(13 downto 2) <= (others => '0'); + TEST(1) <= reset_via_gbe; -- to keep things in place + TEST(14) <= flash_ncs_i; + FLASH_NCS <= flash_ncs_i; + + flash_ncs_i <= '1'; + + FLASH_SCLK <= '0'; + FLASH_MOSI <= '0'; + FLASH_HOLD <= '0'; + FLASH_WP <= '1'; + PROGRAMN <= '1'; + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + LED_SFP_GREEN <= not (status(0) and status(1) and status(2)); --'0'; + LED_SFP_YELLOW <= not '0'; + LED_SFP_RED <= not (status(3) or status(4)); --'0'; + LED(8) <= not status(8); --'0'; + LED(7) <= not '0'; + LED(6) <= not '0'; + LED(5) <= not '0'; + LED(4) <= not '0'; + LED(3) <= not status(2); --'0'; -- AN_COMPLETE + LED(2) <= not status(1); --'0'; -- LRR + LED(1) <= not status(0); --'0'; -- LTR + LED_RJ_GREEN <= "00"; + LED_RJ_RED <= "11"; + LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK; + +end architecture; + + + -- 2.43.0