From 3d6dfdc8dd655976ba7cf5af744fea680ac89156 Mon Sep 17 00:00:00 2001
From: Michael Boehmer <mboehmer@ph.tum.de>
Date: Mon, 25 Jul 2022 08:43:28 +0200
Subject: [PATCH] READOUT taken out. not working yet.

---
 gbe_trb/base/gbe_logic_wrapper.vhd            |  188 +--
 gbe_trb/base/gbe_wrapper_fifo.vhd             |  335 +----
 gbe_trb/base/trb_net16_gbe_main_control.vhd   |  231 +---
 .../base/trb_net16_gbe_protocol_selector.vhd  |  199 +--
 gbe_trb/base/tx_fifo.vhd                      |   10 +
 ...net16_gbe_response_constructor_Forward.vhd |    2 +
 ...b_net16_gbe_response_constructor_SCTRL.vhd | 1096 +++++++----------
 trb_net16_addresses.vhd                       |   26 +-
 trb_net16_endpoint_standalone_sctrl.vhd       |   25 +-
 trb_net16_regIO.vhd                           |    6 +-
 10 files changed, 637 insertions(+), 1481 deletions(-)

diff --git a/gbe_trb/base/gbe_logic_wrapper.vhd b/gbe_trb/base/gbe_logic_wrapper.vhd
index 988af77..9b4952d 100644
--- a/gbe_trb/base/gbe_logic_wrapper.vhd
+++ b/gbe_trb/base/gbe_logic_wrapper.vhd
@@ -12,13 +12,11 @@ use work.trb_net_gbe_protocols.all;
 
 entity gbe_logic_wrapper is
   generic(
-    INCLUDE_READOUT           : std_logic                   := '0';
     INCLUDE_SLOWCTRL          : std_logic                   := '0';
     INCLUDE_DHCP              : std_logic                   := '0';
     INCLUDE_ARP               : std_logic                   := '0';
     INCLUDE_PING              : std_logic                   := '0';
     INCLUDE_FWD               : std_logic                   := '0';
-    READOUT_BUFFER_SIZE       : integer range 1 to 4        := 1;
     SLOWCTRL_BUFFER_SIZE      : integer range 1 to 4        := 1
   );
   port(
@@ -32,7 +30,6 @@ entity gbe_logic_wrapper is
     ISSUE_REBOOT_OUT         : out std_logic;
     -- connection to MAC (link handling)
     MAC_READY_CONF_IN        : in  std_logic;
-    MAC_RECONF_OUT           : out std_logic;
     MAC_AN_READY_IN          : in  std_logic;
     -- TSMAC RX stuff
     MAC_RX_DATA_IN           : in  std_logic_vector(7 downto 0);
@@ -43,24 +40,6 @@ entity gbe_logic_wrapper is
     FT_TX_DATA_OUT           : out std_logic_vector(8 downto 0);
     FT_TX_WR_OUT             : out std_logic;
     FT_TX_FIFOFULL_IN        : in  std_logic;
-    -- CTS interface
-    CTS_NUMBER_IN            : in  std_logic_vector(15 downto 0);
-    CTS_CODE_IN              : in  std_logic_vector(7 downto 0);
-    CTS_INFORMATION_IN       : in  std_logic_vector(7 downto 0);
-    CTS_READOUT_TYPE_IN      : in  std_logic_vector(3 downto 0);
-    CTS_START_READOUT_IN     : in  std_logic;
-    CTS_DATA_OUT             : out std_logic_vector(31 downto 0);
-    CTS_DATAREADY_OUT        : out std_logic;
-    CTS_READOUT_FINISHED_OUT : out std_logic;
-    CTS_READ_IN              : in  std_logic;
-    CTS_LENGTH_OUT           : out std_logic_vector(15 downto 0);
-    CTS_ERROR_PATTERN_OUT    : out std_logic_vector(31 downto 0);
-    -- Data payload interface
-    FEE_DATA_IN              : in  std_logic_vector(15 downto 0);
-    FEE_DATAREADY_IN         : in  std_logic;
-    FEE_READ_OUT             : out std_logic;
-    FEE_STATUS_BITS_IN       : in  std_logic_vector(31 downto 0);
-    FEE_BUSY_IN              : in  std_logic;
     -- SlowControl
     GSC_CLK_IN               : in  std_logic;
     GSC_INIT_DATAREADY_OUT   : out std_logic;
@@ -72,36 +51,10 @@ entity gbe_logic_wrapper is
     GSC_REPLY_PACKET_NUM_IN  : in  std_logic_vector(2 downto 0);
     GSC_REPLY_READ_OUT       : out std_logic;
     GSC_BUSY_IN              : in  std_logic;
-    -- IP configuration
-    SLV_ADDR_IN              : in  std_logic_vector(7 downto 0);
-    SLV_READ_IN              : in  std_logic;
-    SLV_WRITE_IN             : in  std_logic;
-    SLV_BUSY_OUT             : out std_logic;
-    SLV_ACK_OUT              : out std_logic;
-    SLV_DATA_IN              : in  std_logic_vector(31 downto 0);
-    SLV_DATA_OUT             : out std_logic_vector(31 downto 0);
-    -- configuration of gbe core
-    CFG_GBE_ENABLE_IN        : in  std_logic;
-    CFG_IPU_ENABLE_IN        : in  std_logic;
-    CFG_MULT_ENABLE_IN       : in  std_logic;
+    --
+    CFG_MAX_REPLY_SIZE_IN    : in  std_logic_vector(31 downto 0);
     CFG_MAX_FRAME_IN         : in  std_logic_vector(15 downto 0);
     CFG_ALLOW_RX_IN          : in  std_logic;
-    CFG_SOFT_RESET_IN        : in  std_logic;
-    CFG_SUBEVENT_ID_IN       : in  std_logic_vector(31 downto 0);
-    CFG_SUBEVENT_DEC_IN      : in  std_logic_vector(31 downto 0);
-    CFG_QUEUE_DEC_IN         : in  std_logic_vector(31 downto 0);
-    CFG_READOUT_CTR_IN       : in  std_logic_vector(23 downto 0);
-    CFG_READOUT_CTR_VALID_IN : in  std_logic;
-    CFG_INSERT_TTYPE_IN      : in  std_logic;
-    CFG_MAX_SUB_IN           : in  std_logic_vector(15 downto 0);
-    CFG_MAX_QUEUE_IN         : in  std_logic_vector(15 downto 0);
-    CFG_MAX_SUBS_IN_QUEUE_IN : in  std_logic_vector(15 downto 0);
-    CFG_MAX_SINGLE_SUB_IN    : in  std_logic_vector(15 downto 0);
-    CFG_ADDITIONAL_HDR_IN    : in  std_logic;
-    CFG_MAX_REPLY_SIZE_IN    : in  std_logic_vector(31 downto 0);
-    CFG_AUTO_THROTTLE_IN     : in  std_logic;
-    CFG_THROTTLE_PAUSE_IN    : in  std_logic_vector(15 downto 0);
-
     -- Forwarder
     FWD_DST_MAC_IN           : in  std_logic_vector(47 downto 0);
     FWD_DST_IP_IN            : in  std_logic_vector(31 downto 0);
@@ -112,7 +65,7 @@ entity gbe_logic_wrapper is
     FWD_EOP_IN               : in  std_logic;
     FWD_READY_OUT            : out std_logic;
     FWD_FULL_OUT             : out std_logic;
-
+    -- Monitor
     MONITOR_RX_BYTES_OUT     : out std_logic_vector(31 downto 0);
     MONITOR_RX_FRAMES_OUT    : out std_logic_vector(31 downto 0);
     MONITOR_TX_BYTES_OUT     : out std_logic_vector(31 downto 0);
@@ -120,6 +73,7 @@ entity gbe_logic_wrapper is
     MONITOR_TX_PACKETS_OUT   : out std_logic_vector(31 downto 0);
     MONITOR_DROPPED_OUT      : out std_logic_vector(31 downto 0);
     MONITOR_GEN_DBG_OUT      : out std_logic_vector(2 * c_MAX_PROTOCOLS * 32 - 1 downto 0);
+    --
     MAKE_RESET_OUT           : out std_logic;
     DEBUG_OUT                : out std_logic_vector(31 downto 0)
   );
@@ -195,42 +149,32 @@ architecture RTL of gbe_logic_wrapper is
   signal ft_tx_empty        : std_logic;
   signal ft_start_of_packet : std_logic;
 
-  signal gbe_cts_number           : std_logic_vector(15 downto 0);
-  signal gbe_cts_code             : std_logic_vector(7 downto 0);
-  signal gbe_cts_information      : std_logic_vector(7 downto 0);
-  signal gbe_cts_start_readout    : std_logic;
-  signal gbe_cts_readout_type     : std_logic_vector(3 downto 0);
-  signal gbe_cts_readout_finished : std_logic;
-  signal gbe_cts_status_bits      : std_logic_vector(31 downto 0);
-  signal gbe_fee_data             : std_logic_vector(15 downto 0);
-  signal gbe_fee_dataready        : std_logic;
-  signal gbe_fee_read             : std_logic;
-  signal gbe_fee_status_bits      : std_logic_vector(31 downto 0);
-  signal gbe_fee_busy             : std_logic;
-
-  signal fr_ip_proto              : std_logic_vector(7 downto 0);
-  signal mc_ip_proto              : std_logic_vector(7 downto 0);
-  signal mc_ident                 : std_logic_vector(15 downto 0);
-
-  signal dbg_select_rec           : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
-  signal dbg_select_sent          : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
-  signal dbg_select_rec_bytes     : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
-  signal dbg_select_sent_bytes    : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
-  signal dbg_select_drop_in       : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
-  signal dbg_select_drop_out      : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
-  signal dbg_select_gen           : std_logic_vector(2 * c_MAX_PROTOCOLS * 32 - 1 downto 0);
-
-  signal global_reset, rst_n, ff  : std_logic;
-  signal link_ok, dhcp_done       : std_logic;
-
-  signal dum_busy, dum_read, dum_dataready : std_logic;
-  signal dum_data                          : std_logic_vector(15 downto 0);
-
-  signal monitor_tx_packets                                                       : std_logic_vector(31 downto 0);
-  signal monitor_rx_bytes, monitor_rx_frames, monitor_tx_bytes, monitor_tx_frames : std_logic_vector(31 downto 0);
-
-  signal dbg_hist, dbg_hist2    : hist_array;
+  signal fr_ip_proto            : std_logic_vector(7 downto 0);
+  signal mc_ip_proto            : std_logic_vector(7 downto 0);
+  signal mc_ident               : std_logic_vector(15 downto 0);
+
+  signal dbg_select_rec         : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+  signal dbg_select_sent        : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+  signal dbg_select_rec_bytes   : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+  signal dbg_select_sent_bytes  : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+  signal dbg_select_drop_in     : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+  signal dbg_select_drop_out    : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+  signal dbg_select_gen         : std_logic_vector(2 * c_MAX_PROTOCOLS * 32 - 1 downto 0);
+
+  signal global_reset           : std_logic;
+  signal rst_n                  : std_logic;
+  signal ff                     : std_logic;
+  signal link_ok                : std_logic;
+  signal dhcp_done              : std_logic;
+
+  signal monitor_tx_packets     : std_logic_vector(31 downto 0);
+  signal monitor_rx_bytes       : std_logic_vector(31 downto 0);
+  signal monitor_rx_frames      : std_logic_vector(31 downto 0);
+  signal monitor_tx_bytes       : std_logic_vector(31 downto 0);
+  signal monitor_tx_frames      : std_logic_vector(31 downto 0);
   signal monitor_dropped        : std_logic_vector(31 downto 0);
+
+  signal dbg_hist, dbg_hist2    : hist_array; -- TO BE CHECKED
   signal make_reset             : std_logic;
   signal frame_pause            : std_logic_vector(31 downto 0);
 
@@ -259,13 +203,11 @@ begin
     generic map(
       RX_PATH_ENABLE       => 1,
       DO_SIMULATION        => 0,
-      INCLUDE_READOUT      => INCLUDE_READOUT,
       INCLUDE_SLOWCTRL     => INCLUDE_SLOWCTRL,
       INCLUDE_DHCP         => INCLUDE_DHCP,
       INCLUDE_ARP          => INCLUDE_ARP,
       INCLUDE_PING         => INCLUDE_PING,
       INCLUDE_FWD          => INCLUDE_FWD,
-      READOUT_BUFFER_SIZE  => READOUT_BUFFER_SIZE,
       SLOWCTRL_BUFFER_SIZE => SLOWCTRL_BUFFER_SIZE
     )
     port map(
@@ -310,6 +252,7 @@ begin
       TC_TRANSMIT_DONE_IN           => mc_transmit_done,
       -- signals to/from sgmii/gbe pcs_an_complete
       PCS_AN_COMPLETE_IN            => MAC_AN_READY_IN,
+      MAC_READY_CONF_IN             => MAC_READY_CONF_IN,
       -- signals to/from hub
       GSC_CLK_IN                    => GSC_CLK_IN,
       GSC_INIT_DATAREADY_OUT        => GSC_INIT_DATAREADY_OUT,
@@ -321,54 +264,12 @@ begin
       GSC_REPLY_PACKET_NUM_IN       => GSC_REPLY_PACKET_NUM_IN,
       GSC_REPLY_READ_OUT            => GSC_REPLY_READ_OUT,
       GSC_BUSY_IN                   => GSC_BUSY_IN,
-      MAKE_RESET_OUT                => make_reset,
+      CFG_MAX_REPLY_SIZE_IN         => CFG_MAX_REPLY_SIZE_IN,
       --
       RESET_TRBNET_IN               => '0',
       RESET_SCTRL_IN                => '0',
-      -- CTS interface
-      CTS_NUMBER_IN                 => CTS_NUMBER_IN,
-      CTS_CODE_IN                   => CTS_CODE_IN,
-      CTS_INFORMATION_IN            => CTS_INFORMATION_IN,
-      CTS_READOUT_TYPE_IN           => CTS_READOUT_TYPE_IN,
-      CTS_START_READOUT_IN          => CTS_START_READOUT_IN,
-      CTS_DATA_OUT                  => CTS_DATA_OUT,
-      CTS_DATAREADY_OUT             => CTS_DATAREADY_OUT,
-      CTS_READOUT_FINISHED_OUT      => CTS_READOUT_FINISHED_OUT,
-      CTS_READ_IN                   => CTS_READ_IN,
-      CTS_LENGTH_OUT                => CTS_LENGTH_OUT,
-      CTS_ERROR_PATTERN_OUT         => CTS_ERROR_PATTERN_OUT,
-      -- Data payload interface
-      FEE_DATA_IN                   => FEE_DATA_IN,
-      FEE_DATAREADY_IN              => FEE_DATAREADY_IN,
-      FEE_READ_OUT                  => FEE_READ_OUT,
-      FEE_STATUS_BITS_IN            => FEE_STATUS_BITS_IN,
-      FEE_BUSY_IN                   => FEE_BUSY_IN,
-      -- ip configurator
-      SLV_ADDR_IN                   => SLV_ADDR_IN,
-      SLV_READ_IN                   => SLV_READ_IN,
-      SLV_WRITE_IN                  => SLV_WRITE_IN,
-      SLV_BUSY_OUT                  => SLV_BUSY_OUT,
-      SLV_ACK_OUT                   => SLV_ACK_OUT,
-      SLV_DATA_IN                   => SLV_DATA_IN,
-      SLV_DATA_OUT                  => SLV_DATA_OUT,
-      CFG_GBE_ENABLE_IN             => CFG_GBE_ENABLE_IN,
-      CFG_IPU_ENABLE_IN             => CFG_IPU_ENABLE_IN,
-      CFG_MULT_ENABLE_IN            => CFG_MULT_ENABLE_IN,
-      CFG_SUBEVENT_ID_IN            => CFG_SUBEVENT_ID_IN,
-      CFG_SUBEVENT_DEC_IN           => CFG_SUBEVENT_DEC_IN,
-      CFG_QUEUE_DEC_IN              => CFG_QUEUE_DEC_IN,
-      CFG_READOUT_CTR_IN            => CFG_READOUT_CTR_IN,
-      CFG_READOUT_CTR_VALID_IN      => CFG_READOUT_CTR_VALID_IN,
-      CFG_INSERT_TTYPE_IN           => CFG_INSERT_TTYPE_IN,
-      CFG_MAX_SUB_IN                => CFG_MAX_SUB_IN,
-      CFG_MAX_QUEUE_IN              => CFG_MAX_QUEUE_IN,
-      CFG_MAX_SUBS_IN_QUEUE_IN      => CFG_MAX_SUBS_IN_QUEUE_IN,
-      CFG_MAX_SINGLE_SUB_IN         => CFG_MAX_SINGLE_SUB_IN,
-      CFG_ADDITIONAL_HDR_IN         => CFG_ADDITIONAL_HDR_IN,
-      CFG_MAX_REPLY_SIZE_IN         => CFG_MAX_REPLY_SIZE_IN,
-      CFG_AUTO_THROTTLE_IN          => '0', --CFG_AUTO_THROTTLE_IN,
-      CFG_THROTTLE_PAUSE_IN         => (others => '0'), --CFG_THROTTLE_PAUSE_IN,
-
+      MAKE_RESET_OUT                => make_reset,
+      --
       FWD_DST_MAC_IN                => FWD_DST_MAC_IN,
       FWD_DST_IP_IN                 => FWD_DST_IP_IN,
       FWD_DST_UDP_IN                => FWD_DST_UDP_IN,
@@ -378,22 +279,10 @@ begin
       FWD_EOP_IN                    => FWD_EOP_IN,
       FWD_READY_OUT                 => FWD_READY_OUT,
       FWD_FULL_OUT                  => FWD_FULL_OUT,
-
-      TSM_HADDR_OUT                 => open, --mac_haddr,
-      TSM_HDATA_OUT                 => open, --mac_hdataout,
-      TSM_HCS_N_OUT                 => open, --mac_hcs,
-      TSM_HWRITE_N_OUT              => open, --mac_hwrite,
-      TSM_HREAD_N_OUT               => open, --mac_hread,
-      TSM_HREADY_N_IN               => '0', --mac_hready,
-      TSM_HDATA_EN_N_IN             => '1', --mac_hdata_en,
-      TSM_RX_STAT_VEC_IN            => (others => '0'), --mac_rx_stat_vec,
-      TSM_RX_STAT_EN_IN             => '0', --mac_rx_stat_en,
-
+      --
       DEBUG_OUT(31 downto 0)        => DEBUG_OUT, 
       DEBUG_OUT(63 downto 32)       => open, 
-      
-      MAC_READY_CONF_IN             => MAC_READY_CONF_IN,
-      MAC_RECONF_OUT                => MAC_RECONF_OUT,
+      --
       MONITOR_SELECT_REC_OUT        => dbg_select_rec,
       MONITOR_SELECT_REC_BYTES_OUT  => dbg_select_rec_bytes,
       MONITOR_SELECT_SENT_BYTES_OUT => dbg_select_sent_bytes,
@@ -483,7 +372,8 @@ begin
       MONITOR_TX_FRAMES_OUT   => monitor_tx_frames
     );
     
-  frame_pause <= x"0000" & CFG_THROTTLE_PAUSE_IN;
+--  frame_pause <= x"0000" & CFG_THROTTLE_PAUSE_IN; -- TAKE CARE!!!
+  frame_pause <= x"0000" & x"0000"; -- TAKE CARE!!!
 
   RECEIVE_CONTROLLER : trb_net16_gbe_receive_control
     port map(
@@ -561,10 +451,6 @@ begin
       MONITOR_DROPPED_OUT     => monitor_dropped
     );
 
---  DEBUG_OUT(0) <= fr_rd_en;
---  DEBUG_OUT(1) <= fr_frame_valid;
---  DEBUG_OUT(2) <= fr_get_frame;
-    
   MONITOR_RX_FRAMES_OUT  <= monitor_rx_frames;
   MONITOR_RX_BYTES_OUT   <= monitor_rx_bytes;
   MONITOR_TX_FRAMES_OUT  <= monitor_tx_frames;
diff --git a/gbe_trb/base/gbe_wrapper_fifo.vhd b/gbe_trb/base/gbe_wrapper_fifo.vhd
index 7ec7ce6..7bd606d 100644
--- a/gbe_trb/base/gbe_wrapper_fifo.vhd
+++ b/gbe_trb/base/gbe_wrapper_fifo.vhd
@@ -10,16 +10,13 @@ use work.trb_net_components.all;
 use work.trb_net_gbe_components.all;
 use work.trb_net_gbe_protocols.all;
 
-
 entity gbe_wrapper_fifo is
   generic(
-    LINK_HAS_READOUT          : std_logic                    := '1';
-    LINK_HAS_PING             : std_logic                    := '1';
-    LINK_HAS_ARP              : std_logic                    := '1';
-    LINK_HAS_DHCP             : std_logic                    := '1';
-    LINK_HAS_READOUT          : std_logic                    := '1';
-    LINK_HAS_SLOWCTRL         : std_logic                    := '1';
-    LINK_HAS_FWD              : std_logic                    := '1'
+    LINK_HAS_PING      : std_logic := '1';
+    LINK_HAS_ARP       : std_logic := '1';
+    LINK_HAS_DHCP      : std_logic := '1';
+    LINK_HAS_SLOWCTRL  : std_logic := '1';
+    LINK_HAS_FWD       : std_logic := '1'
   );
   port(
     CLK_125_IN                : in  std_logic;
@@ -42,26 +39,6 @@ entity gbe_wrapper_fifo is
     --
     PCS_AN_READY_IN           : in  std_logic;
     LINK_ACTIVE_IN            : in  std_logic;
-    --                        
-    TRIGGER_IN                : in  std_logic; -- for debug purpose only
-    -- CTS interface          
-    CTS_NUMBER_IN             : in  std_logic_vector(15 downto 0) := (others => '0');
-    CTS_CODE_IN               : in  std_logic_vector(7 downto 0)  := (others => '0');
-    CTS_INFORMATION_IN        : in  std_logic_vector(7 downto 0)  := (others => '0');
-    CTS_READOUT_TYPE_IN       : in  std_logic_vector(3 downto 0)  := (others => '0');
-    CTS_START_READOUT_IN      : in  std_logic                     := '0';
-    CTS_DATA_OUT              : out std_logic_vector(31 downto 0);
-    CTS_DATAREADY_OUT         : out std_logic;
-    CTS_READOUT_FINISHED_OUT  : out std_logic;
-    CTS_READ_IN               : in  std_logic                     := '0';
-    CTS_LENGTH_OUT            : out std_logic_vector(15 downto 0);
-    CTS_ERROR_PATTERN_OUT     : out std_logic_vector(31 downto 0);
-    -- Data payload interface 
-    FEE_DATA_IN               : in  std_logic_vector(15 downto 0) := (others => '0');
-    FEE_DATAREADY_IN          : in  std_logic                     := '0';
-    FEE_READ_OUT              : out std_logic;
-    FEE_STATUS_BITS_IN        : in  std_logic_vector(31 downto 0) := (others => '0');
-    FEE_BUSY_IN               : in  std_logic                     := '0';
     -- SlowControl            
     MY_TRBNET_ADDRESS_IN      : in  std_logic_vector(15 downto 0);
     ISSUE_REBOOT_OUT          : out std_logic;
@@ -76,12 +53,6 @@ entity gbe_wrapper_fifo is
     GSC_REPLY_PACKET_NUM_IN   : in  std_logic_vector(2 downto 0);
     GSC_REPLY_READ_OUT        : out std_logic;
     GSC_BUSY_IN               : in  std_logic;
-    -- IP configuration       
-    BUS_IP_RX                 : in  CTRLBUS_RX;
-    BUS_IP_TX                 : out CTRLBUS_TX;
-    -- Registers config
-    BUS_REG_RX                : in  CTRLBUS_RX;
-    BUS_REG_TX                : out CTRLBUS_TX;
     -- Forwarder
     FWD_DST_MAC_IN            : in  std_logic_vector(47 downto 0) := (others => '0');
     FWD_DST_IP_IN             : in  std_logic_vector(31 downto 0) := (others => '0');
@@ -102,45 +73,7 @@ end entity gbe_wrapper_fifo;
 
 architecture RTL of gbe_wrapper_fifo is
 
-  signal cfg_gbe_enable             : std_logic;
-  signal cfg_ipu_enable             : std_logic;
-  signal cfg_mult_enable            : std_logic;
-  signal cfg_subevent_id            : std_logic_vector(31 downto 0);
-  signal cfg_subevent_dec           : std_logic_vector(31 downto 0);
-  signal cfg_queue_dec              : std_logic_vector(31 downto 0);
-  signal cfg_readout_ctr            : std_logic_vector(23 downto 0);
-  signal cfg_readout_ctr_valid      : std_logic;
-  signal cfg_insert_ttype           : std_logic;
-  signal cfg_max_sub                : std_logic_vector(15 downto 0);
-  signal cfg_max_queue              : std_logic_vector(15 downto 0);
-  signal cfg_max_subs_in_queue      : std_logic_vector(15 downto 0);
-  signal cfg_max_single_sub         : std_logic_vector(15 downto 0);
-  signal cfg_additional_hdr         : std_logic;
-  signal cfg_soft_rst               : std_logic;
-  signal cfg_allow_rx               : std_logic;
-  signal cfg_max_frame              : std_logic_vector(15 downto 0);
-
-  signal dbg_hist, dbg_hist2        : hist_array;
-
-  signal mac_0                      : std_logic_vector(47 downto 0);
-  signal cfg_max_reply              : std_logic_vector(31 downto 0);
-
-  signal mlt_cts_number             : std_logic_vector(15 downto 0);
-  signal mlt_cts_code               : std_logic_vector(7 downto 0);
-  signal mlt_cts_information        : std_logic_vector(7 downto 0);
-  signal mlt_cts_readout_type       : std_logic_vector(3 downto 0);
-  signal mlt_cts_start_readout      : std_logic_vector(0 downto 0);
-  signal mlt_cts_data               : std_logic_vector(31 downto 0);
-  signal mlt_cts_dataready          : std_logic_vector(0 downto 0);
-  signal mlt_cts_readout_finished   : std_logic_vector(0 downto 0);
-  signal mlt_cts_read               : std_logic_vector(0 downto 0);
-  signal mlt_cts_length             : std_logic_vector(15 downto 0);
-  signal mlt_cts_error_pattern      : std_logic_vector(31 downto 0);
-  signal mlt_fee_data               : std_logic_vector(15 downto 0);
-  signal mlt_fee_dataready          : std_logic_vector(0 downto 0);
-  signal mlt_fee_read               : std_logic_vector(0 downto 0);
-  signal mlt_fee_status             : std_logic_vector(31 downto 0);
-  signal mlt_fee_busy               : std_logic_vector(0 downto 0);
+  signal mac                        : std_logic_vector(47 downto 0);
 
   signal mlt_gsc_clk                : std_logic;
   signal mlt_gsc_init_dataready     : std_logic;
@@ -153,43 +86,18 @@ architecture RTL of gbe_wrapper_fifo is
   signal mlt_gsc_reply_read         : std_logic;
   signal mlt_gsc_busy               : std_logic;
 
-  signal local_cts_number           : std_logic_vector(15 downto 0);
-  signal local_cts_code             : std_logic_vector(7 downto 0);
-  signal local_cts_information      : std_logic_vector(7 downto 0);
-  signal local_cts_readout_type     : std_logic_vector(3 downto 0);
-  signal local_cts_start_readout    : std_logic;
-  signal local_cts_readout_finished : std_logic;
-  signal local_cts_status_bits      : std_logic_vector(31 downto 0);
-  signal local_fee_data             : std_logic_vector(15 downto 0);
-  signal local_fee_dataready        : std_logic;
-  signal local_fee_read             : std_logic;
-  signal local_fee_status_bits      : std_logic_vector(31 downto 0);
-  signal local_fee_busy             : std_logic;
   signal dhcp_done                  : std_logic;
-  signal all_links_ready            : std_logic;
+
   signal monitor_rx_frames          : std_logic_vector(31 downto 0);
   signal monitor_rx_bytes           : std_logic_vector(31 downto 0);
   signal monitor_tx_frames          : std_logic_vector(31 downto 0);
   signal monitor_tx_bytes           : std_logic_vector(31 downto 0);
   signal monitor_tx_packets         : std_logic_vector(31 downto 0);
   signal monitor_dropped            : std_logic_vector(31 downto 0);
-  signal sum_rx_frames              : std_logic_vector(31 downto 0);
-  signal sum_rx_bytes               : std_logic_vector(31 downto 0);
-  signal sum_tx_frames              : std_logic_vector(31 downto 0);
-  signal sum_tx_bytes               : std_logic_vector(31 downto 0);
-  signal sum_tx_packets             : std_logic_vector(31 downto 0);
-  signal sum_dropped                : std_logic_vector(31 downto 0);
-
-  signal busip0                     : CTRLBUS_TX;
 
-  signal dummy_event                : std_logic_vector(15 downto 0);
-  signal dummy_mode                 : std_logic;
-  signal make_reset0                : std_logic := '0';
+  signal make_reset                 : std_logic := '0';
   signal monitor_gen_dbg            : std_logic_vector(c_MAX_PROTOCOLS * 64 - 1 downto 0);
 
-  signal cfg_autothrottle           : std_logic;
-  signal cfg_throttle_pause         : std_logic_vector(15 downto 0);
-  
   signal issue_reboot               : std_logic;
   signal my_ip                      : std_logic_vector(127 downto 0);
   signal debug                      : std_logic_vector(127 downto 0);
@@ -239,11 +147,9 @@ begin
   -- debug(63 downto 0) are media interface
 --  DEBUG_OUT <= monitor_gen_dbg(95 downto 64);
 
-  mac_0 <= MC_UNIQUE_ID_IN(15 downto 8) & MC_UNIQUE_ID_IN(23 downto 16) & MC_UNIQUE_ID_IN(31 downto 24) & x"0" & MC_UNIQUE_ID_IN(35 downto 32) & x"7ada";
-
-  all_links_ready <= '1' when dhcp_done = '1' else '0';
+  mac <= MC_UNIQUE_ID_IN(15 downto 8) & MC_UNIQUE_ID_IN(23 downto 16) & MC_UNIQUE_ID_IN(31 downto 24) & x"0" & MC_UNIQUE_ID_IN(35 downto 32) & x"7ada";
 
-  MAKE_RESET_OUT <= '1' when  make_reset0 = '1' else '0';
+  MAKE_RESET_OUT <= '1' when  make_reset = '1' else '0';
   
   ISSUE_REBOOT_OUT <= '0' when issue_reboot = '0' else '1';
 
@@ -252,26 +158,23 @@ begin
   
   gbe_inst : entity work.gbe_logic_wrapper
   generic map(
-    INCLUDE_READOUT          => LINK_HAS_READOUT,
     INCLUDE_SLOWCTRL         => LINK_HAS_SLOWCTRL,
     INCLUDE_DHCP             => LINK_HAS_DHCP,
     INCLUDE_ARP              => LINK_HAS_ARP,
     INCLUDE_PING             => LINK_HAS_PING,
     INCLUDE_FWD              => LINK_HAS_FWD,
-    READOUT_BUFFER_SIZE      => 4,
     SLOWCTRL_BUFFER_SIZE     => 2
   )
   port map(
     CLK_125_IN               => CLK_125_IN,
     RESET                    => RESET,
     GSR_N                    => GSR_N,
-    MY_MAC_IN                => mac_0,
+    MY_MAC_IN                => mac,
     DHCP_DONE_OUT            => dhcp_done,
     MY_IP_OUT                => my_ip(31 downto 0),
     MY_TRBNET_ADDRESS_IN     => MY_TRBNET_ADDRESS_IN,
     ISSUE_REBOOT_OUT         => issue_reboot,
     MAC_READY_CONF_IN        => LINK_ACTIVE_IN,
-    MAC_RECONF_OUT           => open,
     MAC_AN_READY_IN          => PCS_AN_READY_IN,
     -- MAC RX stuff    
     MAC_RX_DATA_IN           => MAC_RX_DATA_IN,
@@ -282,23 +185,7 @@ begin
     FT_TX_DATA_OUT           => ft_tx_data,
     FT_TX_WR_OUT             => ft_tx_wr,
     FT_TX_FIFOFULL_IN        => ft_tx_fifofull,
-    --
-    CTS_NUMBER_IN            => mlt_cts_number,
-    CTS_CODE_IN              => mlt_cts_code,
-    CTS_INFORMATION_IN       => mlt_cts_information,
-    CTS_READOUT_TYPE_IN      => mlt_cts_readout_type,
-    CTS_START_READOUT_IN     => mlt_cts_start_readout(0),
-    CTS_DATA_OUT             => mlt_cts_data,
-    CTS_DATAREADY_OUT        => mlt_cts_dataready(0),
-    CTS_READOUT_FINISHED_OUT => mlt_cts_readout_finished(0),
-    CTS_READ_IN              => mlt_cts_read(0),
-    CTS_LENGTH_OUT           => mlt_cts_length,
-    CTS_ERROR_PATTERN_OUT    => mlt_cts_error_pattern,
-    FEE_DATA_IN              => mlt_fee_data,
-    FEE_DATAREADY_IN         => mlt_fee_dataready(0),
-    FEE_READ_OUT             => mlt_fee_read(0),
-    FEE_STATUS_BITS_IN       => mlt_fee_status,
-    FEE_BUSY_IN              => mlt_fee_busy(0),
+    -- SCTRL
     GSC_CLK_IN               => mlt_gsc_clk,
     GSC_INIT_DATAREADY_OUT   => mlt_gsc_init_dataready,
     GSC_INIT_DATA_OUT        => mlt_gsc_init_data,
@@ -309,33 +196,11 @@ begin
     GSC_REPLY_PACKET_NUM_IN  => mlt_gsc_reply_packet,
     GSC_REPLY_READ_OUT       => mlt_gsc_reply_read,
     GSC_BUSY_IN              => mlt_gsc_busy,
-    SLV_ADDR_IN              => BUS_IP_RX.addr(7 downto 0),
-    SLV_READ_IN              => BUS_IP_RX.read,
-    SLV_WRITE_IN             => BUS_IP_RX.write,
-    SLV_BUSY_OUT             => busip0.nack,
-    SLV_ACK_OUT              => busip0.ack,
-    SLV_DATA_IN              => BUS_IP_RX.data,
-    SLV_DATA_OUT             => busip0.data,
-    CFG_GBE_ENABLE_IN        => cfg_gbe_enable,
-    CFG_IPU_ENABLE_IN        => cfg_ipu_enable,
-    CFG_MULT_ENABLE_IN       => cfg_mult_enable,
-    CFG_MAX_FRAME_IN         => cfg_max_frame,
-    CFG_ALLOW_RX_IN          => cfg_allow_rx,
-    CFG_SOFT_RESET_IN        => cfg_soft_rst,
-    CFG_SUBEVENT_ID_IN       => cfg_subevent_id,
-    CFG_SUBEVENT_DEC_IN      => cfg_subevent_dec,
-    CFG_QUEUE_DEC_IN         => cfg_queue_dec,
-    CFG_READOUT_CTR_IN       => cfg_readout_ctr,
-    CFG_READOUT_CTR_VALID_IN => cfg_readout_ctr_valid,
-    CFG_INSERT_TTYPE_IN      => cfg_insert_ttype,
-    CFG_MAX_SUB_IN           => cfg_max_sub,
-    CFG_MAX_QUEUE_IN         => cfg_max_queue,
-    CFG_MAX_SUBS_IN_QUEUE_IN => cfg_max_subs_in_queue,
-    CFG_MAX_SINGLE_SUB_IN    => cfg_max_single_sub,
-    CFG_ADDITIONAL_HDR_IN    => cfg_additional_hdr,
-    CFG_MAX_REPLY_SIZE_IN    => cfg_max_reply,
-    CFG_AUTO_THROTTLE_IN     => cfg_autothrottle,
-    CFG_THROTTLE_PAUSE_IN    => cfg_throttle_pause,
+    -- 
+    CFG_MAX_REPLY_SIZE_IN    => x"0000_fa00",
+    CFG_MAX_FRAME_IN         => x"0578",
+    CFG_ALLOW_RX_IN          => '1',
+    -- Forwarder
     FWD_DST_MAC_IN           => FWD_DST_MAC_IN,
     FWD_DST_IP_IN            => FWD_DST_IP_IN,
     FWD_DST_UDP_IN           => FWD_DST_UDP_IN,
@@ -345,6 +210,7 @@ begin
     FWD_EOP_IN               => FWD_EOP_IN,
     FWD_READY_OUT            => FWD_READY_OUT,
     FWD_FULL_OUT             => FWD_FULL_OUT,
+    -- Monitor
     MONITOR_RX_FRAMES_OUT    => monitor_rx_frames,
     MONITOR_RX_BYTES_OUT     => monitor_rx_bytes,
     MONITOR_TX_FRAMES_OUT    => monitor_tx_frames,
@@ -352,153 +218,38 @@ begin
     MONITOR_TX_PACKETS_OUT   => monitor_tx_packets,
     MONITOR_DROPPED_OUT      => monitor_dropped,
     MONITOR_GEN_DBG_OUT      => monitor_gen_dbg,
-    MAKE_RESET_OUT           => make_reset0,
+    -- 
+    MAKE_RESET_OUT           => make_reset,
     DEBUG_OUT                => DEBUG_OUT --open
   );
 
-  BUS_IP_TX.ack  <= busip0.ack  when rising_edge(CLK_125_IN);
-  BUS_IP_TX.nack <= busip0.nack when rising_edge(CLK_125_IN);
-  BUS_IP_TX.data <= busip0.data when rising_edge(CLK_125_IN);
-
-  ipu_mult : entity work.gbe_ipu_multiplexer
-    generic map(
-      DO_SIMULATION       => 0,
-      INCLUDE_DEBUG       => 0,
-      LINK_HAS_READOUT    => "000" & LINK_HAS_READOUT,
-      NUMBER_OF_GBE_LINKS => 1
-    )
-    port map(
-      CLK_SYS_IN                  => CLK_125_IN,
-      RESET                       => RESET,
-      CTS_NUMBER_IN               => CTS_NUMBER_IN,
-      CTS_CODE_IN                 => CTS_CODE_IN,
-      CTS_INFORMATION_IN          => CTS_INFORMATION_IN,
-      CTS_READOUT_TYPE_IN         => CTS_READOUT_TYPE_IN,
-      CTS_START_READOUT_IN        => CTS_START_READOUT_IN,
-      CTS_DATA_OUT                => CTS_DATA_OUT,
-      CTS_DATAREADY_OUT           => CTS_DATAREADY_OUT,
-      CTS_READOUT_FINISHED_OUT    => CTS_READOUT_FINISHED_OUT,
-      CTS_READ_IN                 => CTS_READ_IN,
-      CTS_LENGTH_OUT              => CTS_LENGTH_OUT,
-      CTS_ERROR_PATTERN_OUT       => CTS_ERROR_PATTERN_OUT,
-      FEE_DATA_IN                 => FEE_DATA_IN,
-      FEE_DATAREADY_IN            => FEE_DATAREADY_IN,
-      FEE_READ_OUT                => FEE_READ_OUT,
-      FEE_STATUS_BITS_IN          => FEE_STATUS_BITS_IN,
-      FEE_BUSY_IN                 => FEE_BUSY_IN,
-      MLT_CTS_NUMBER_OUT          => mlt_cts_number,
-      MLT_CTS_CODE_OUT            => mlt_cts_code,
-      MLT_CTS_INFORMATION_OUT     => mlt_cts_information,
-      MLT_CTS_READOUT_TYPE_OUT    => mlt_cts_readout_type,
-      MLT_CTS_START_READOUT_OUT   => mlt_cts_start_readout,
-      MLT_CTS_DATA_IN             => mlt_cts_data,
-      MLT_CTS_DATAREADY_IN        => mlt_cts_dataready,
-      MLT_CTS_READOUT_FINISHED_IN => mlt_cts_readout_finished,
-      MLT_CTS_READ_OUT            => mlt_cts_read,
-      MLT_CTS_LENGTH_IN           => mlt_cts_length,
-      MLT_CTS_ERROR_PATTERN_IN    => mlt_cts_error_pattern,
-      MLT_FEE_DATA_OUT            => mlt_fee_data,
-      MLT_FEE_DATAREADY_OUT       => mlt_fee_dataready,
-      MLT_FEE_READ_IN             => mlt_fee_read,
-      MLT_FEE_STATUS_BITS_OUT     => mlt_fee_status,
-      MLT_FEE_BUSY_OUT            => mlt_fee_busy,
-      DEBUG_OUT                   => open
-    );
-
-  SETUP : gbe_setup
-  port map(
-    CLK                          => CLK_125_IN,
-    RESET                        => RESET,
-    -- interface to regio bus
-    BUS_ADDR_IN                  => BUS_REG_RX.addr(7 downto 0),
-    BUS_DATA_IN                  => BUS_REG_RX.data,
-    BUS_DATA_OUT                 => BUS_REG_TX.data,
-    BUS_WRITE_EN_IN              => BUS_REG_RX.write,
-    BUS_READ_EN_IN               => BUS_REG_RX.read,
-    BUS_ACK_OUT                  => BUS_REG_TX.ack,
-    -- output to gbe_buf
-    GBE_SUBEVENT_ID_OUT          => cfg_subevent_id,
-    GBE_SUBEVENT_DEC_OUT         => cfg_subevent_dec,
-    GBE_QUEUE_DEC_OUT            => cfg_queue_dec,
-    GBE_MAX_FRAME_OUT            => cfg_max_frame,
-    GBE_USE_GBE_OUT              => cfg_gbe_enable,
-    GBE_USE_TRBNET_OUT           => cfg_ipu_enable,
-    GBE_USE_MULTIEVENTS_OUT      => cfg_mult_enable,
-    GBE_READOUT_CTR_OUT          => cfg_readout_ctr,
-    GBE_READOUT_CTR_VALID_OUT    => cfg_readout_ctr_valid,
-    GBE_ALLOW_RX_OUT             => cfg_allow_rx,
-    GBE_ADDITIONAL_HDR_OUT       => cfg_additional_hdr,
-    GBE_INSERT_TTYPE_OUT         => cfg_insert_ttype,
-    GBE_SOFT_RESET_OUT           => cfg_soft_rst,
-    GBE_MAX_REPLY_OUT            => cfg_max_reply,
-    GBE_MAX_SUB_OUT              => cfg_max_sub,
-    GBE_MAX_QUEUE_OUT            => cfg_max_queue,
-    GBE_MAX_SUBS_IN_QUEUE_OUT    => cfg_max_subs_in_queue,
-    GBE_MAX_SINGLE_SUB_OUT       => cfg_max_single_sub,
-    GBE_AUTOTHROTTLE_OUT         => cfg_autothrottle,
-    GBE_THROTTLE_PAUSE_OUT       => cfg_throttle_pause,
-    MONITOR_RX_BYTES_IN          => sum_rx_bytes,
-    MONITOR_RX_FRAMES_IN         => sum_rx_frames,
-    MONITOR_TX_BYTES_IN          => sum_tx_bytes,
-    MONITOR_TX_FRAMES_IN         => sum_tx_frames,
-    MONITOR_TX_PACKETS_IN        => sum_tx_packets,
-    MONITOR_DROPPED_IN           => sum_dropped,
-    MONITOR_SELECT_REC_IN        => (others => '0'),
-    MONITOR_SELECT_REC_BYTES_IN  => (others => '0'),
-    MONITOR_SELECT_SENT_BYTES_IN => (others => '0'),
-    MONITOR_SELECT_SENT_IN       => (others => '0'),
-    MONITOR_SELECT_DROP_IN_IN    => (others => '0'),
-    MONITOR_SELECT_DROP_OUT_IN   => (others => '0'),
-    MONITOR_SELECT_GEN_DBG_IN    => monitor_gen_dbg,
-    MONITOR_IP_IN                => my_ip,
-    DUMMY_EVENT_SIZE_OUT         => dummy_event,
-    DUMMY_TRIGGERED_MODE_OUT     => dummy_mode,
-    DATA_HIST_IN                 => (others => (others => '0')),
-    SCTRL_HIST_IN                => (others => (others => '0'))
-  );
+  -- sum_rx_*  ???
+  -- sum_tx_*  ???
 
   NOSCTRL_MAP_GEN : if (LINK_HAS_SLOWCTRL = '0') generate
-    GSC_INIT_DATAREADY_OUT  <= '0';
-    GSC_INIT_DATA_OUT       <= (others => '0');
-    GSC_INIT_PACKET_NUM_OUT <= (others => '0');
-    GSC_REPLY_READ_OUT      <= '1';
-    mlt_gsc_clk             <= (others => '0');
-    mlt_gsc_init_read       <= (others => '0');
-    mlt_gsc_reply_dataready <= (others => '0');
-    mlt_gsc_reply_data      <= (others => '0');
-    mlt_gsc_reply_packet    <= (others => '0');
-    mlt_gsc_busy            <= (others => '0');
+    mlt_gsc_clk              <= '0';
+    GSC_INIT_DATAREADY_OUT   <= '0';
+    GSC_INIT_DATA_OUT        <= (others => '0');
+    GSC_INIT_PACKET_NUM_OUT  <= (others => '0');
+    GSC_REPLY_READ_OUT       <= '1';
+    mlt_gsc_init_read        <= '0';
+    mlt_gsc_reply_dataready  <= '0';
+    mlt_gsc_reply_data       <= (others => '0');
+    mlt_gsc_reply_packet     <= (others => '0');
+    mlt_gsc_busy             <= '0';
   end generate NOSCTRL_MAP_GEN;
 
-  SCTRL_MAP_GEN : if (LINK_HAS_SLOWCTRL /= '0') generate
-    ACTIVE_MAP_GEN : if (LINK_HAS_SLOWCTRL = '1') generate
-      mlt_gsc_clk              <= GSC_CLK_IN;
-      GSC_INIT_DATAREADY_OUT   <= mlt_gsc_init_dataready;
-      GSC_INIT_DATA_OUT        <= mlt_gsc_init_data;
-      GSC_INIT_PACKET_NUM_OUT  <= mlt_gsc_init_packet;
-      mlt_gsc_init_read        <= GSC_INIT_READ_IN;
-      mlt_gsc_reply_dataready  <= GSC_REPLY_DATAREADY_IN;
-      mlt_gsc_reply_data       <= GSC_REPLY_DATA_IN;
-      mlt_gsc_reply_packet     <= GSC_REPLY_PACKET_NUM_IN;
-      GSC_REPLY_READ_OUT       <= mlt_gsc_reply_read;
-      mlt_gsc_busy             <= GSC_BUSY_IN;
-    end generate ACTIVE_MAP_GEN;
-
-    INACTIVE_MAP_GEN : if (LINK_HAS_SLOWCTRL = '0') generate
-      mlt_gsc_clk              <= '0';
-      mlt_gsc_init_read        <= '0';
-      mlt_gsc_reply_dataready  <= '0';
-      mlt_gsc_reply_data       <= (others => '0');
-      mlt_gsc_reply_packet     <= (others => '0');
-      mlt_gsc_busy             <= '0';
-    end generate INACTIVE_MAP_GEN;
+  SCTRL_MAP_GEN : if (LINK_HAS_SLOWCTRL = '1') generate
+    mlt_gsc_clk              <= GSC_CLK_IN;
+    GSC_INIT_DATAREADY_OUT   <= mlt_gsc_init_dataready;
+    GSC_INIT_DATA_OUT        <= mlt_gsc_init_data;
+    GSC_INIT_PACKET_NUM_OUT  <= mlt_gsc_init_packet;
+    GSC_REPLY_READ_OUT       <= mlt_gsc_reply_read;
+    mlt_gsc_init_read        <= GSC_INIT_READ_IN;
+    mlt_gsc_reply_dataready  <= GSC_REPLY_DATAREADY_IN;
+    mlt_gsc_reply_data       <= GSC_REPLY_DATA_IN;
+    mlt_gsc_reply_packet     <= GSC_REPLY_PACKET_NUM_IN;
+    mlt_gsc_busy             <= GSC_BUSY_IN;
   end generate SCTRL_MAP_GEN;
 
-  sum_rx_bytes   <= monitor_rx_bytes;
-  sum_rx_frames  <= monitor_rx_frames;
-  sum_tx_bytes   <= monitor_tx_bytes;
-  sum_tx_frames  <= monitor_tx_frames;
-  sum_tx_packets <= monitor_tx_packets;
-  sum_dropped    <= monitor_dropped;
-
 end architecture RTL;
diff --git a/gbe_trb/base/trb_net16_gbe_main_control.vhd b/gbe_trb/base/trb_net16_gbe_main_control.vhd
index 3f3c6ab..33977a5 100644
--- a/gbe_trb/base/trb_net16_gbe_main_control.vhd
+++ b/gbe_trb/base/trb_net16_gbe_main_control.vhd
@@ -22,14 +22,12 @@ entity trb_net16_gbe_main_control is
     RX_PATH_ENABLE       : integer range 0 to 1 := 1;
     DO_SIMULATION        : integer range 0 to 1 := 0;
     --
-    INCLUDE_READOUT      : std_logic            := '0';
     INCLUDE_SLOWCTRL     : std_logic            := '0';
     INCLUDE_DHCP         : std_logic            := '0';
     INCLUDE_ARP          : std_logic            := '0';
     INCLUDE_PING         : std_logic            := '0';
     INCLUDE_FWD          : std_logic            := '0';
     --
-    READOUT_BUFFER_SIZE  : integer range 1 to 4;
     SLOWCTRL_BUFFER_SIZE : integer range 1 to 4
   );
   port(
@@ -37,7 +35,7 @@ entity trb_net16_gbe_main_control is
     CLK_125                       : in  std_logic;
     RESET                         : in  std_logic;
     --
-    MC_LINK_OK_OUT                : out std_logic;
+    MC_LINK_OK_OUT                : out std_logic; -- ??? is that really needed???
     MC_RESET_LINK_IN              : in  std_logic;
     MC_IDLE_TOO_LONG_OUT          : out std_logic;
     MC_DHCP_DONE_OUT              : out std_logic;
@@ -77,6 +75,7 @@ entity trb_net16_gbe_main_control is
     TC_TRANSMIT_DONE_IN           : in  std_logic;
     -- signals to/from sgmii/gbe pcs_an_complete
     PCS_AN_COMPLETE_IN            : in  std_logic;
+    MAC_READY_CONF_IN             : in  std_logic;
     -- signals to/from hub
     GSC_CLK_IN                    : in  std_logic;
     GSC_INIT_DATAREADY_OUT        : out std_logic;
@@ -88,54 +87,10 @@ entity trb_net16_gbe_main_control is
     GSC_REPLY_PACKET_NUM_IN       : in  std_logic_vector(2 downto 0);
     GSC_REPLY_READ_OUT            : out std_logic;
     GSC_BUSY_IN                   : in  std_logic;
+    CFG_MAX_REPLY_SIZE_IN         : in  std_logic_vector(31 downto 0);
     --
     RESET_TRBNET_IN               : in  std_logic;
     RESET_SCTRL_IN                : in  std_logic;
-    -- signal for data readout
-    -- CTS interface
-    CTS_NUMBER_IN                 : in  std_logic_vector(15 downto 0);
-    CTS_CODE_IN                   : in  std_logic_vector(7 downto 0);
-    CTS_INFORMATION_IN            : in  std_logic_vector(7 downto 0);
-    CTS_READOUT_TYPE_IN           : in  std_logic_vector(3 downto 0);
-    CTS_START_READOUT_IN          : in  std_logic;
-    CTS_DATA_OUT                  : out std_logic_vector(31 downto 0);
-    CTS_DATAREADY_OUT             : out std_logic;
-    CTS_READOUT_FINISHED_OUT      : out std_logic;
-    CTS_READ_IN                   : in  std_logic;
-    CTS_LENGTH_OUT                : out std_logic_vector(15 downto 0);
-    CTS_ERROR_PATTERN_OUT         : out std_logic_vector(31 downto 0);
-    -- Data payload interface
-    FEE_DATA_IN                   : in  std_logic_vector(15 downto 0);
-    FEE_DATAREADY_IN              : in  std_logic;
-    FEE_READ_OUT                  : out std_logic;
-    FEE_STATUS_BITS_IN            : in  std_logic_vector(31 downto 0);
-    FEE_BUSY_IN                   : in  std_logic;
-    -- ip configurator
-    SLV_ADDR_IN                   : in  std_logic_vector(7 downto 0);
-    SLV_READ_IN                   : in  std_logic;
-    SLV_WRITE_IN                  : in  std_logic;
-    SLV_BUSY_OUT                  : out std_logic;
-    SLV_ACK_OUT                   : out std_logic;
-    SLV_DATA_IN                   : in  std_logic_vector(31 downto 0);
-    SLV_DATA_OUT                  : out std_logic_vector(31 downto 0);
-    --
-    CFG_GBE_ENABLE_IN             : in  std_logic;
-    CFG_IPU_ENABLE_IN             : in  std_logic;
-    CFG_MULT_ENABLE_IN            : in  std_logic;
-    CFG_SUBEVENT_ID_IN            : in  std_logic_vector(31 downto 0);
-    CFG_SUBEVENT_DEC_IN           : in  std_logic_vector(31 downto 0);
-    CFG_QUEUE_DEC_IN              : in  std_logic_vector(31 downto 0);
-    CFG_READOUT_CTR_IN            : in  std_logic_vector(23 downto 0);
-    CFG_READOUT_CTR_VALID_IN      : in  std_logic;
-    CFG_INSERT_TTYPE_IN           : in  std_logic;
-    CFG_MAX_SUB_IN                : in  std_logic_vector(15 downto 0);
-    CFG_MAX_QUEUE_IN              : in  std_logic_vector(15 downto 0);
-    CFG_MAX_SUBS_IN_QUEUE_IN      : in  std_logic_vector(15 downto 0);
-    CFG_MAX_SINGLE_SUB_IN         : in  std_logic_vector(15 downto 0);
-    CFG_ADDITIONAL_HDR_IN         : in  std_logic;
-    CFG_MAX_REPLY_SIZE_IN         : in  std_logic_vector(31 downto 0);
-    CFG_AUTO_THROTTLE_IN          : in  std_logic;
-    CFG_THROTTLE_PAUSE_IN         : in  std_logic_vector(15 downto 0);
     MAKE_RESET_OUT                : out std_logic;
     -- Forwarder
     FWD_DST_MAC_IN                : in  std_logic_vector(47 downto 0);
@@ -147,19 +102,6 @@ entity trb_net16_gbe_main_control is
     FWD_EOP_IN                    : in  std_logic;
     FWD_READY_OUT                 : out std_logic;
     FWD_FULL_OUT                  : out std_logic;
-    -- signal to/from Host interface of TriSpeed MAC
-    TSM_HADDR_OUT                 : out std_logic_vector(7 downto 0);
-    TSM_HDATA_OUT                 : out std_logic_vector(7 downto 0);
-    TSM_HCS_N_OUT                 : out std_logic;
-    TSM_HWRITE_N_OUT              : out std_logic;
-    TSM_HREAD_N_OUT               : out std_logic;
-    TSM_HREADY_N_IN               : in  std_logic;
-    TSM_HDATA_EN_N_IN             : in  std_logic;
-    TSM_RX_STAT_VEC_IN            : in  std_logic_vector(31 downto 0);
-    TSM_RX_STAT_EN_IN             : in  std_logic;
-    --
-    MAC_READY_CONF_IN             : in  std_logic;
-    MAC_RECONF_OUT                : out std_logic;
     --
     MONITOR_SELECT_REC_OUT        : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
     MONITOR_SELECT_REC_BYTES_OUT  : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
@@ -183,20 +125,12 @@ architecture trb_net16_gbe_main_control of trb_net16_gbe_main_control is
 
   attribute syn_encoding : string;
 
-  signal tsm_ready           : std_logic;
-  signal tsm_reconf          : std_logic;
-  signal tsm_haddr           : std_logic_vector(7 downto 0);
-  signal tsm_hdata           : std_logic_vector(7 downto 0);
-  signal tsm_hcs_n           : std_logic;
-  signal tsm_hwrite_n        : std_logic;
-  signal tsm_hread_n         : std_logic;
-
   type link_states is (INACTIVE, ACTIVE, ENABLE_MAC, TIMEOUT, FINALIZE, WAIT_FOR_BOOT, GET_ADDRESS);
   signal link_current_state, link_next_state : link_states;
   attribute syn_encoding of link_current_state : signal is "onehot";
 
-  signal link_down_ctr       : std_logic_vector(15 downto 0);
-  signal link_down_ctr_lock  : std_logic;
+--  signal link_down_ctr       : std_logic_vector(15 downto 0);
+--  signal link_down_ctr_lock  : std_logic;
   signal link_ok             : std_logic;
   signal link_ok_timeout_ctr : std_logic_vector(15 downto 0);
 
@@ -214,9 +148,9 @@ architecture trb_net16_gbe_main_control of trb_net16_gbe_main_control is
   signal ps_response_ready   : std_logic;
   signal ps_busy             : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
   signal rc_rd_en            : std_logic;
-  signal first_byte          : std_logic;
-  signal first_byte_q        : std_logic;
-  signal first_byte_qq       : std_logic;
+--  signal first_byte          : std_logic;
+--  signal first_byte_q        : std_logic;
+--  signal first_byte_qq       : std_logic;
   signal proto_select        : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
   signal loaded_bytes_ctr    : std_Logic_vector(15 downto 0);
 
@@ -235,14 +169,17 @@ architecture trb_net16_gbe_main_control of trb_net16_gbe_main_control is
   signal redirect_current_state, redirect_next_state : redirect_states;
   attribute syn_encoding of redirect_current_state : signal is "onehot";
 
-  signal disable_redirect, ps_wr_en_q, ps_wr_en_qq : std_logic;
+  signal disable_redirect    : std_logic;
+  signal ps_wr_en_q          : std_logic;
+  signal ps_wr_en_qq         : std_logic;
 
   type stats_states is (IDLE, LOAD_VECTOR, CLEANUP);
   signal stats_current_state, stats_next_state : stats_states;
 
-  signal stat_rdy, stat_ack : std_logic;
-  signal rx_stat_en_q       : std_logic;
-  signal rx_stat_vec_q      : std_logic_vector(31 downto 0);
+  signal stat_rdy            : std_logic;
+  signal stat_ack            : std_logic;
+  signal rx_stat_en_q        : std_logic;
+  signal rx_stat_vec_q       : std_logic_vector(31 downto 0);
 
   type array_of_ctrs is array (15 downto 0) of std_logic_vector(31 downto 0);
   signal arr       : array_of_ctrs;
@@ -250,43 +187,38 @@ architecture trb_net16_gbe_main_control of trb_net16_gbe_main_control is
   signal stat_data : std_logic_vector(31 downto 0);
   signal stat_addr : std_logic_vector(7 downto 0);
 
-  signal nothing_sent     : std_logic;
-  signal nothing_sent_ctr : std_logic_vector(31 downto 0);
+  signal dbg_ps              : std_Logic_vector(63 downto 0);
 
-  signal dbg_ps : std_Logic_vector(63 downto 0);
-
-  signal tc_data : std_logic_vector(8 downto 0);
+  signal tc_data             : std_logic_vector(8 downto 0);
 
   attribute syn_preserve : boolean;
   attribute syn_keep : boolean;
-  attribute syn_keep of nothing_sent, link_state, state, redirect_state, dhcp_done : signal is true;
-  attribute syn_preserve of nothing_sent, link_state, state, redirect_state, dhcp_done : signal is true;
+  attribute syn_keep of link_state, state, redirect_state, dhcp_done : signal is true;
+  attribute syn_preserve of link_state, state, redirect_state, dhcp_done : signal is true;
 
-  signal mc_busy        : std_logic;
-  signal incl_dhcp      : std_logic;
-  signal flow_state     : std_logic_vector(3 downto 0);
-  signal selector_debug : std_logic_vector(63 downto 0);
+  signal mc_busy             : std_logic;
+  signal incl_dhcp           : std_logic;
+  signal flow_state          : std_logic_vector(3 downto 0);
+  signal selector_debug      : std_logic_vector(63 downto 0);
 
 begin
   protocol_selector : entity work.trb_net16_gbe_protocol_selector
     generic map(
       RX_PATH_ENABLE       => RX_PATH_ENABLE,
       DO_SIMULATION        => DO_SIMULATION,
-      INCLUDE_READOUT      => INCLUDE_READOUT,
       INCLUDE_SLOWCTRL     => INCLUDE_SLOWCTRL,
       INCLUDE_DHCP         => INCLUDE_DHCP,
       INCLUDE_ARP          => INCLUDE_ARP,
       INCLUDE_PING         => INCLUDE_PING,
       INCLUDE_FWD          => INCLUDE_FWD,
-      READOUT_BUFFER_SIZE  => READOUT_BUFFER_SIZE,
       SLOWCTRL_BUFFER_SIZE => SLOWCTRL_BUFFER_SIZE
     )
     port map(
       CLK                           => CLK,
       RESET                         => RESET,
       RESET_FOR_DHCP                => MC_RESET_LINK_IN,
-      PS_DATA_IN                    => rc_data_local, -- RC_DATA_IN,
-      PS_WR_EN_IN                   => ps_wr_en_qq, --ps_wr_en,
+      PS_DATA_IN                    => rc_data_local,
+      PS_WR_EN_IN                   => ps_wr_en_qq,
       PS_PROTO_SELECT_IN            => proto_select,
       PS_BUSY_OUT                   => ps_busy,
       PS_FRAME_SIZE_IN              => RC_FRAME_SIZE_IN,
@@ -329,49 +261,7 @@ begin
       MY_TRBNET_ADDRESS_IN          => MY_TRBNET_ADDRESS_IN,
       ISSUE_REBOOT_OUT              => ISSUE_REBOOT_OUT,
 
-      -- CTS interface
-      CTS_NUMBER_IN                 => CTS_NUMBER_IN,
-      CTS_CODE_IN                   => CTS_CODE_IN,
-      CTS_INFORMATION_IN            => CTS_INFORMATION_IN,
-      CTS_READOUT_TYPE_IN           => CTS_READOUT_TYPE_IN,
-      CTS_START_READOUT_IN          => CTS_START_READOUT_IN,
-      CTS_DATA_OUT                  => CTS_DATA_OUT,
-      CTS_DATAREADY_OUT             => CTS_DATAREADY_OUT,
-      CTS_READOUT_FINISHED_OUT      => CTS_READOUT_FINISHED_OUT,
-      CTS_READ_IN                   => CTS_READ_IN,
-      CTS_LENGTH_OUT                => CTS_LENGTH_OUT,
-      CTS_ERROR_PATTERN_OUT         => CTS_ERROR_PATTERN_OUT,
-      -- Data payload interface
-      FEE_DATA_IN                   => FEE_DATA_IN,
-      FEE_DATAREADY_IN              => FEE_DATAREADY_IN,
-      FEE_READ_OUT                  => FEE_READ_OUT,
-      FEE_STATUS_BITS_IN            => FEE_STATUS_BITS_IN,
-      FEE_BUSY_IN                   => FEE_BUSY_IN,
-      -- ip configurator
-      SLV_ADDR_IN                   => SLV_ADDR_IN,
-      SLV_READ_IN                   => SLV_READ_IN,
-      SLV_WRITE_IN                  => SLV_WRITE_IN,
-      SLV_BUSY_OUT                  => SLV_BUSY_OUT,
-      SLV_ACK_OUT                   => SLV_ACK_OUT,
-      SLV_DATA_IN                   => SLV_DATA_IN,
-      SLV_DATA_OUT                  => SLV_DATA_OUT,
-      CFG_GBE_ENABLE_IN             => CFG_GBE_ENABLE_IN,
-      CFG_IPU_ENABLE_IN             => CFG_IPU_ENABLE_IN,
-      CFG_MULT_ENABLE_IN            => CFG_MULT_ENABLE_IN,
-      CFG_SUBEVENT_ID_IN            => CFG_SUBEVENT_ID_IN,
-      CFG_SUBEVENT_DEC_IN           => CFG_SUBEVENT_DEC_IN,
-      CFG_QUEUE_DEC_IN              => CFG_QUEUE_DEC_IN,
-      CFG_READOUT_CTR_IN            => CFG_READOUT_CTR_IN,
-      CFG_READOUT_CTR_VALID_IN      => CFG_READOUT_CTR_VALID_IN,
-      CFG_INSERT_TTYPE_IN           => CFG_INSERT_TTYPE_IN,
-      CFG_MAX_SUB_IN                => CFG_MAX_SUB_IN,
-      CFG_MAX_QUEUE_IN              => CFG_MAX_QUEUE_IN,
-      CFG_MAX_SUBS_IN_QUEUE_IN      => CFG_MAX_SUBS_IN_QUEUE_IN,
-      CFG_MAX_SINGLE_SUB_IN         => CFG_MAX_SINGLE_SUB_IN,
-      CFG_ADDITIONAL_HDR_IN         => CFG_ADDITIONAL_HDR_IN,
       CFG_MAX_REPLY_SIZE_IN         => CFG_MAX_REPLY_SIZE_IN,
-      CFG_AUTO_THROTTLE_IN          => CFG_AUTO_THROTTLE_IN,
-      CFG_THROTTLE_PAUSE_IN         => CFG_THROTTLE_PAUSE_IN,
 
       FWD_DST_MAC_IN                => FWD_DST_MAC_IN,
       FWD_DST_IP_IN                 => FWD_DST_IP_IN,
@@ -555,19 +445,19 @@ begin
     end if;
   end process LOADED_BYTES_CTR_PROC;
 
-  FIRST_BYTE_PROC : process(CLK)
-  begin
-    if rising_edge(CLK) then
-      first_byte_q  <= first_byte;
-      first_byte_qq <= first_byte_q;
-
-      if (redirect_current_state = IDLE) then
-        first_byte <= '1';
-      else
-        first_byte <= '0';
-      end if;
-    end if;
-  end process FIRST_BYTE_PROC;
+--  FIRST_BYTE_PROC : process(CLK)
+--  begin
+--    if rising_edge(CLK) then
+--      first_byte_q  <= first_byte;
+--      first_byte_qq <= first_byte_q;
+--
+--      if (redirect_current_state = IDLE) then
+--        first_byte <= '1';
+--      else
+--        first_byte <= '0';
+--      end if;
+--    end if;
+--  end process FIRST_BYTE_PROC;
 
   --*********************
   --	DATA FLOW CONTROL
@@ -676,6 +566,7 @@ begin
     incl_dhcp <= '0';
   end generate noincl_dhcp_gen;
 
+  -- to be reworked. link_ok_timer is not needed anymore!
   LINK_STATE_MACHINE : process(link_current_state, dhcp_done, wait_ctr, PCS_AN_COMPLETE_IN, incl_dhcp, MAC_READY_CONF_IN, link_ok_timeout_ctr)
   begin
     link_state <= x"0";
@@ -792,43 +683,31 @@ begin
     end if;
   end process WAIT_CTR_PROC;
 
-  MC_LINK_OK_OUT <= link_ok;          -- or nothing_sent;
+  MC_LINK_OK_OUT <= link_ok;
 
   -- END OF LINK STATE CONTROL
   --*************
 
-  process(CLK)
-  begin
-    if rising_edge(CLK) then
-      if link_current_state = INACTIVE and PCS_AN_COMPLETE_IN = '1' then
-        tsm_reconf <= '1';
-      else
-        tsm_reconf <= '0';
-      end if;
-    end if;
-  end process;
-  MAC_RECONF_OUT <= tsm_reconf;
-
-  TSM_HADDR_OUT    <= tsm_haddr;
-  TSM_HCS_N_OUT    <= tsm_hcs_n;
-  TSM_HDATA_OUT    <= tsm_hdata;
-  TSM_HREAD_N_OUT  <= tsm_hread_n;
-  TSM_HWRITE_N_OUT <= tsm_hwrite_n;
-
-  -- END OF TRI SPEED MAC CONTROLLER
-  --***************
-
 --  process(CLK)
 --  begin
 --    if rising_edge(CLK) then
---      DEBUG_OUT(3 downto 0)   <= redirect_state;
---      DEBUG_OUT(7 downto 4)   <= flow_state;
---      DEBUG_OUT(11 downto 8)  <= link_state;
---      DEBUG_OUT(31 downto 12) <= (others => '0');
---
---      DEBUG_OUT(63 downto 32) <= selector_debug(31 downto 0);
+--      if link_current_state = INACTIVE and PCS_AN_COMPLETE_IN = '1' then
+--        tsm_reconf <= '1';
+--      else
+--        tsm_reconf <= '0';
+--      end if;
 --    end if;
 --  end process;
+--  MAC_RECONF_OUT <= tsm_reconf;
+
+--  TSM_HADDR_OUT    <= tsm_haddr;
+--  TSM_HCS_N_OUT    <= tsm_hcs_n;
+--  TSM_HDATA_OUT    <= tsm_hdata;
+--  TSM_HREAD_N_OUT  <= tsm_hread_n;
+--  TSM_HWRITE_N_OUT <= tsm_hwrite_n;
+
+  -- END OF TRI SPEED MAC CONTROLLER
+  --***************
 
   DEBUG_OUT <= selector_debug;
 
diff --git a/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd b/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd
index ac5aebe..bdb443e 100644
--- a/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd
+++ b/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd
@@ -16,25 +16,21 @@ use work.trb_net_gbe_protocols.all;
 -- 
 -- 
 
-
 entity trb_net16_gbe_protocol_selector is
   generic(
     RX_PATH_ENABLE       : integer range 0 to 1 := 1;
     DO_SIMULATION        : integer range 0 to 1 := 0;
-    INCLUDE_READOUT      : std_logic            := '0';
     INCLUDE_SLOWCTRL     : std_logic            := '0';
     INCLUDE_DHCP         : std_logic            := '0';
     INCLUDE_ARP          : std_logic            := '0';
     INCLUDE_PING         : std_logic            := '0';
     INCLUDE_FWD          : std_logic            := '0';
-    READOUT_BUFFER_SIZE  : integer range 1 to 4;
     SLOWCTRL_BUFFER_SIZE : integer range 1 to 4
   );
   port(
     CLK                           : in  std_logic; -- system clock
     RESET                         : in  std_logic;
     RESET_FOR_DHCP                : in  std_logic;
-
     -- signals to/from main controller
     PS_DATA_IN                    : in  std_logic_vector(8 downto 0);
     PS_WR_EN_IN                   : in  std_logic;
@@ -48,8 +44,7 @@ entity trb_net16_gbe_protocol_selector is
     PS_DEST_IP_ADDRESS_IN         : in  std_logic_vector(31 downto 0);
     PS_SRC_UDP_PORT_IN            : in  std_logic_vector(15 downto 0);
     PS_DEST_UDP_PORT_IN           : in  std_logic_vector(15 downto 0);
-
-    -- singals to/from transmit controller with constructed response
+    -- signals to/from transmit controller with constructed response
     TC_DATA_OUT                   : out std_logic_vector(8 downto 0);
     TC_RD_EN_IN                   : in  std_logic;
     TC_FRAME_SIZE_OUT             : out std_logic_vector(15 downto 0);
@@ -63,7 +58,6 @@ entity trb_net16_gbe_protocol_selector is
     TC_SRC_IP_OUT                 : out std_logic_vector(31 downto 0);
     TC_SRC_UDP_OUT                : out std_logic_vector(15 downto 0);
     MC_BUSY_IN                    : in  std_logic;
-
     -- misc signals for response constructors
     MY_MAC_IN                     : in  std_logic_vector(47 downto 0);
     MY_IP_OUT                     : out std_logic_vector(31 downto 0);
@@ -79,56 +73,10 @@ entity trb_net16_gbe_protocol_selector is
     GSC_REPLY_PACKET_NUM_IN       : in  std_logic_vector(2 downto 0);
     GSC_REPLY_READ_OUT            : out std_logic;
     GSC_BUSY_IN                   : in  std_logic;
+    CFG_MAX_REPLY_SIZE_IN         : in  std_logic_vector(31 downto 0);    -- USED IN SCTRL
     MAKE_RESET_OUT                : out std_logic;
-
     MY_TRBNET_ADDRESS_IN          : in  std_logic_vector(15 downto 0);
     ISSUE_REBOOT_OUT              : out std_logic;
-    
-    -- signal for data readout
-    -- CTS interface
-    CTS_NUMBER_IN                 : in  std_logic_vector(15 downto 0);
-    CTS_CODE_IN                   : in  std_logic_vector(7 downto 0);
-    CTS_INFORMATION_IN            : in  std_logic_vector(7 downto 0);
-    CTS_READOUT_TYPE_IN           : in  std_logic_vector(3 downto 0);
-    CTS_START_READOUT_IN          : in  std_logic;
-    CTS_DATA_OUT                  : out std_logic_vector(31 downto 0);
-    CTS_DATAREADY_OUT             : out std_logic;
-    CTS_READOUT_FINISHED_OUT      : out std_logic;
-    CTS_READ_IN                   : in  std_logic;
-    CTS_LENGTH_OUT                : out std_logic_vector(15 downto 0);
-    CTS_ERROR_PATTERN_OUT         : out std_logic_vector(31 downto 0);
-    -- Data payload interface
-    FEE_DATA_IN                   : in  std_logic_vector(15 downto 0);
-    FEE_DATAREADY_IN              : in  std_logic;
-    FEE_READ_OUT                  : out std_logic;
-    FEE_STATUS_BITS_IN            : in  std_logic_vector(31 downto 0);
-    FEE_BUSY_IN                   : in  std_logic;
-    -- ip configurator
-    SLV_ADDR_IN                   : in  std_logic_vector(7 downto 0);
-    SLV_READ_IN                   : in  std_logic;
-    SLV_WRITE_IN                  : in  std_logic;
-    SLV_BUSY_OUT                  : out std_logic;
-    SLV_ACK_OUT                   : out std_logic;
-    SLV_DATA_IN                   : in  std_logic_vector(31 downto 0);
-    SLV_DATA_OUT                  : out std_logic_vector(31 downto 0);
-    CFG_GBE_ENABLE_IN             : in  std_logic;
-    CFG_IPU_ENABLE_IN             : in  std_logic;
-    CFG_MULT_ENABLE_IN            : in  std_logic;
-    CFG_SUBEVENT_ID_IN            : in  std_logic_vector(31 downto 0);
-    CFG_SUBEVENT_DEC_IN           : in  std_logic_vector(31 downto 0);
-    CFG_QUEUE_DEC_IN              : in  std_logic_vector(31 downto 0);
-    CFG_READOUT_CTR_IN            : in  std_logic_vector(23 downto 0);
-    CFG_READOUT_CTR_VALID_IN      : in  std_logic;
-    CFG_INSERT_TTYPE_IN           : in  std_logic;
-    CFG_MAX_SUB_IN                : in  std_logic_vector(15 downto 0);
-    CFG_MAX_QUEUE_IN              : in  std_logic_vector(15 downto 0);
-    CFG_MAX_SUBS_IN_QUEUE_IN      : in  std_logic_vector(15 downto 0);
-    CFG_MAX_SINGLE_SUB_IN         : in  std_logic_vector(15 downto 0);
-    CFG_ADDITIONAL_HDR_IN         : in  std_logic;
-    CFG_MAX_REPLY_SIZE_IN         : in  std_logic_vector(31 downto 0);
-    CFG_AUTO_THROTTLE_IN          : in  std_logic;
-    CFG_THROTTLE_PAUSE_IN         : in  std_logic_vector(15 downto 0);
-
     -- Forwarder
     FWD_DST_MAC_IN                : in  std_logic_vector(47 downto 0);
     FWD_DST_IP_IN                 : in  std_logic_vector(31 downto 0);
@@ -139,7 +87,6 @@ entity trb_net16_gbe_protocol_selector is
     FWD_EOP_IN                    : in  std_logic;
     FWD_READY_OUT                 : out std_logic;
     FWD_FULL_OUT                  : out std_logic;
-
     -- input for statistics from outside	
     STAT_DATA_IN                  : in  std_logic_vector(31 downto 0);
     STAT_ADDR_IN                  : in  std_logic_vector(7 downto 0);
@@ -257,9 +204,9 @@ begin
         STAT_ADDR_OUT          => stat_addr(1 * 8 - 1 downto 0 * 8),
         STAT_DATA_RDY_OUT      => stat_rdy(0),
         STAT_DATA_ACK_IN       => stat_ack(0),
-        RECEIVED_FRAMES_OUT    => open, --RECEIVED_FRAMES_OUT(1 * 16 - 1 downto 0 * 16),
-        SENT_FRAMES_OUT        => open, --SENT_FRAMES_OUT(1 * 16 - 1 downto 0 * 16),
-        DEBUG_OUT              => MONITOR_SELECT_GEN_DBG_OUT(1 * 64 - 1 downto 0 * 64) --PROTOS_DEBUG_OUT(1 * 32 - 1 downto 0 * 32)
+        RECEIVED_FRAMES_OUT    => open,
+        SENT_FRAMES_OUT        => open,
+        DEBUG_OUT              => MONITOR_SELECT_GEN_DBG_OUT(1 * 64 - 1 downto 0 * 64)
       -- END OF INTERFACE 
       );
   end generate arp_gen;
@@ -311,14 +258,14 @@ begin
         STAT_ADDR_OUT          => stat_addr(2 * 8 - 1 downto 1 * 8),
         STAT_DATA_RDY_OUT      => stat_rdy(1),
         STAT_DATA_ACK_IN       => stat_ack(1),
-        RECEIVED_FRAMES_OUT    => open, --RECEIVED_FRAMES_OUT(2 * 16 - 1 downto 1 * 16),
-        SENT_FRAMES_OUT        => open, --SENT_FRAMES_OUT(2 * 16 - 1 downto 1 * 16),
+        RECEIVED_FRAMES_OUT    => open,
+        SENT_FRAMES_OUT        => open,
         -- END OF INTERFACE
 
         MY_IP_OUT              => my_ip,
         DHCP_START_IN          => DHCP_START_IN,
         DHCP_DONE_OUT          => DHCP_DONE_OUT,
-        DEBUG_OUT              => MONITOR_SELECT_GEN_DBG_OUT(2 * 64 - 1 downto 1 * 64) --PROTOS_DEBUG_OUT(1 * 32 - 1 downto 0 * 32)
+        DEBUG_OUT              => MONITOR_SELECT_GEN_DBG_OUT(2 * 64 - 1 downto 1 * 64)
       );
   end generate dhcp_gen;
 
@@ -434,7 +381,6 @@ begin
         GSC_REPLY_PACKET_NUM_IN       => GSC_REPLY_PACKET_NUM_IN,
         GSC_REPLY_READ_OUT            => GSC_REPLY_READ_OUT,
         GSC_BUSY_IN                   => GSC_BUSY_IN,
-        CFG_ADDITIONAL_HDR_IN         => CFG_ADDITIONAL_HDR_IN,
         CFG_MAX_REPLY_SIZE_IN         => CFG_MAX_REPLY_SIZE_IN,
         MAKE_RESET_OUT                => MAKE_RESET_OUT,
         MONITOR_SELECT_REC_OUT        => MONITOR_SELECT_REC_OUT(3 * 32 - 1 downto 2 * 32),
@@ -457,113 +403,11 @@ begin
 
   end generate no_sctrl_gen;
 
-  trbnet_gen : if INCLUDE_READOUT = '1' generate
-    TrbNetData : trb_net16_gbe_response_constructor_TrbNetData
-      generic map(
-        RX_PATH_ENABLE      => RX_PATH_ENABLE,
-        DO_SIMULATION       => DO_SIMULATION,
-        READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE
-      )
-      port map(
-        CLK                           => CLK,
-        RESET                         => RESET,
-
-        -- INTERFACE	
-        MY_MAC_IN                     => MY_MAC_IN,
-        MY_IP_IN                      => my_ip,
-        PS_DATA_IN                    => PS_DATA_IN,
-        PS_WR_EN_IN                   => PS_WR_EN_IN,
-        PS_ACTIVATE_IN                => PS_PROTO_SELECT_IN(3),
-        PS_RESPONSE_READY_OUT         => resp_ready(3),
-        PS_BUSY_OUT                   => busy(3),
-        PS_SELECTED_IN                => selected(3),
-        PS_SRC_MAC_ADDRESS_IN         => PS_SRC_MAC_ADDRESS_IN,
-        PS_DEST_MAC_ADDRESS_IN        => PS_DEST_MAC_ADDRESS_IN,
-        PS_SRC_IP_ADDRESS_IN          => PS_SRC_IP_ADDRESS_IN,
-        PS_DEST_IP_ADDRESS_IN         => PS_DEST_IP_ADDRESS_IN,
-        PS_SRC_UDP_PORT_IN            => PS_SRC_UDP_PORT_IN,
-        PS_DEST_UDP_PORT_IN           => PS_DEST_UDP_PORT_IN,
-        TC_RD_EN_IN                   => TC_RD_EN_IN,
-        TC_DATA_OUT                   => tc_data(4 * 9 - 1 downto 3 * 9),
-        TC_FRAME_SIZE_OUT             => tc_size(4 * 16 - 1 downto 3 * 16),
-        TC_FRAME_TYPE_OUT             => tc_type(4 * 16 - 1 downto 3 * 16),
-        TC_IP_PROTOCOL_OUT            => tc_ip_proto(4 * 8 - 1 downto 3 * 8),
-        TC_IDENT_OUT                  => tc_ident(4 * 16 - 1 downto 3 * 16),
-        TC_DEST_MAC_OUT               => tc_mac(4 * 48 - 1 downto 3 * 48),
-        TC_DEST_IP_OUT                => tc_ip(4 * 32 - 1 downto 3 * 32),
-        TC_DEST_UDP_OUT               => tc_udp(4 * 16 - 1 downto 3 * 16),
-        TC_SRC_MAC_OUT                => tc_src_mac(4 * 48 - 1 downto 3 * 48),
-        TC_SRC_IP_OUT                 => tc_src_ip(4 * 32 - 1 downto 3 * 32),
-        TC_SRC_UDP_OUT                => tc_src_udp(4 * 16 - 1 downto 3 * 16),
-        STAT_DATA_OUT                 => stat_data(4 * 32 - 1 downto 3 * 32),
-        STAT_ADDR_OUT                 => stat_addr(4 * 8 - 1 downto 3 * 8),
-        STAT_DATA_RDY_OUT             => stat_rdy(3),
-        STAT_DATA_ACK_IN              => stat_ack(3),
-        DEBUG_OUT                     => MONITOR_SELECT_GEN_DBG_OUT(4 * 64 - 1 downto 3 * 64),
-        -- END OF INTERFACE
-
-        -- CTS interface
-        CTS_NUMBER_IN                 => CTS_NUMBER_IN,
-        CTS_CODE_IN                   => CTS_CODE_IN,
-        CTS_INFORMATION_IN            => CTS_INFORMATION_IN,
-        CTS_READOUT_TYPE_IN           => CTS_READOUT_TYPE_IN,
-        CTS_START_READOUT_IN          => CTS_START_READOUT_IN,
-        CTS_DATA_OUT                  => CTS_DATA_OUT,
-        CTS_DATAREADY_OUT             => CTS_DATAREADY_OUT,
-        CTS_READOUT_FINISHED_OUT      => CTS_READOUT_FINISHED_OUT,
-        CTS_READ_IN                   => CTS_READ_IN,
-        CTS_LENGTH_OUT                => CTS_LENGTH_OUT,
-        CTS_ERROR_PATTERN_OUT         => CTS_ERROR_PATTERN_OUT,
-        -- Data payload interface
-        FEE_DATA_IN                   => FEE_DATA_IN,
-        FEE_DATAREADY_IN              => FEE_DATAREADY_IN,
-        FEE_READ_OUT                  => FEE_READ_OUT,
-        FEE_STATUS_BITS_IN            => FEE_STATUS_BITS_IN,
-        FEE_BUSY_IN                   => FEE_BUSY_IN,
-        -- ip configurator
-        SLV_ADDR_IN                   => SLV_ADDR_IN,
-        SLV_READ_IN                   => SLV_READ_IN,
-        SLV_WRITE_IN                  => SLV_WRITE_IN,
-        SLV_BUSY_OUT                  => SLV_BUSY_OUT,
-        SLV_ACK_OUT                   => SLV_ACK_OUT,
-        SLV_DATA_IN                   => SLV_DATA_IN,
-        SLV_DATA_OUT                  => SLV_DATA_OUT,
-        CFG_GBE_ENABLE_IN             => CFG_GBE_ENABLE_IN,
-        CFG_IPU_ENABLE_IN             => CFG_IPU_ENABLE_IN,
-        CFG_MULT_ENABLE_IN            => CFG_MULT_ENABLE_IN,
-        CFG_SUBEVENT_ID_IN            => CFG_SUBEVENT_ID_IN,
-        CFG_SUBEVENT_DEC_IN           => CFG_SUBEVENT_DEC_IN,
-        CFG_QUEUE_DEC_IN              => CFG_QUEUE_DEC_IN,
-        CFG_READOUT_CTR_IN            => CFG_READOUT_CTR_IN,
-        CFG_READOUT_CTR_VALID_IN      => CFG_READOUT_CTR_VALID_IN,
-        CFG_INSERT_TTYPE_IN           => CFG_INSERT_TTYPE_IN,
-        CFG_MAX_SUB_IN                => CFG_MAX_SUB_IN,
-        CFG_MAX_QUEUE_IN              => CFG_MAX_QUEUE_IN,
-        CFG_MAX_SUBS_IN_QUEUE_IN      => CFG_MAX_SUBS_IN_QUEUE_IN,
-        CFG_MAX_SINGLE_SUB_IN         => CFG_MAX_SINGLE_SUB_IN,
-        CFG_AUTO_THROTTLE_IN          => CFG_AUTO_THROTTLE_IN,
-        CFG_THROTTLE_PAUSE_IN         => CFG_THROTTLE_PAUSE_IN,
-        MONITOR_SELECT_REC_OUT        => MONITOR_SELECT_REC_OUT(4 * 32 - 1 downto 3 * 32),
-        MONITOR_SELECT_REC_BYTES_OUT  => MONITOR_SELECT_REC_BYTES_OUT(4 * 32 - 1 downto 3 * 32),
-        MONITOR_SELECT_SENT_BYTES_OUT => MONITOR_SELECT_SENT_BYTES_OUT(4 * 32 - 1 downto 3 * 32),
-        MONITOR_SELECT_SENT_OUT       => MONITOR_SELECT_SENT_OUT(4 * 32 - 1 downto 3 * 32),
-        MONITOR_SELECT_DROP_OUT_OUT   => MONITOR_SELECT_DROP_OUT_OUT(4 * 32 - 1 downto 3 * 32),
-        MONITOR_SELECT_DROP_IN_OUT    => open,
-        DATA_HIST_OUT                 => DATA_HIST_OUT
-      );
-  end generate trbnet_gen;
-
-  no_readout_gen : if INCLUDE_READOUT = '0' generate
-    resp_ready(3)            <= '0';
-    busy(3)                  <= '0';
-    CTS_DATA_OUT             <= (others => '0');
-    CTS_DATAREADY_OUT        <= '0';
-    CTS_READOUT_FINISHED_OUT <= '0';
-    CTS_LENGTH_OUT           <= (others => '0');
-    CTS_ERROR_PATTERN_OUT    <= (others => '0');
-    FEE_READ_OUT             <= '0';
-  end generate no_readout_gen;
-
+  ---------------------------------------------------------------------------------------
+  -- once upon a time, this was "READOUT"
+  resp_ready(3)            <= '0';
+  busy(3)                  <= '0';
+  ---------------------------------------------------------------------------------------
 
   fwd_gen : if INCLUDE_FWD = '1' generate
 
@@ -633,11 +477,7 @@ begin
     if RESET = '1' then
       select_current_state <= IDLE;
     elsif rising_edge(CLK) then
-      --		if (RESET = '1') then
-      --			select_current_state <= IDLE;
-      --		else
       select_current_state <= select_next_state;
-    --		end if;
     end if;
   end process SELECT_MACHINE_PROC;
 
@@ -678,7 +518,7 @@ begin
 
       when PROCESS_REQUEST =>
         select_state <= x"4";
-        if (busy(index) = '0') then --if (MC_BUSY_IN = '0') then
+        if (busy(index) = '0') then
           select_next_state <= CLEANUP;
         else
           select_next_state <= PROCESS_REQUEST;
@@ -747,17 +587,6 @@ begin
     end if;
   end process SELECTOR_PROC;
 
---  process(CLK)
---  begin
---    if rising_edge(CLK) then
---      DEBUG_OUT(3 downto 0)   <= select_state;
---      DEBUG_OUT(11 downto 4)  <= std_logic_vector(to_unsigned(index, 8));
---      DEBUG_OUT(19 downto 12) <= "00" & resp_ready; -- 4:0
---      DEBUG_OUT(27 downto 20) <= "00" & busy; -- 4:0
---      DEBUG_OUT(63 downto 28) <= (others => '0');
---    end if;
---  end process;
-
 end trb_net16_gbe_protocol_selector;
 
 
diff --git a/gbe_trb/base/tx_fifo.vhd b/gbe_trb/base/tx_fifo.vhd
index adcd0b9..5d7bf39 100644
--- a/gbe_trb/base/tx_fifo.vhd
+++ b/gbe_trb/base/tx_fifo.vhd
@@ -4,6 +4,16 @@ use ieee.numeric_std.all;
 
 library work;
 
+-- BUG: if no frame is stored in FIFO, and filling the FIFO triggers FIFOFULL,
+--      the frame must be written completely but dropped.
+
+-- BUG: use dynamic ALMOSTFULL to accommodate for pipelining inside the data
+--      multiplexer of hub.
+
+-- OPTIMIZE: we can start transfering data to the MAC once 16bytes (or similar)
+--           have been written.
+--           The MAC needs a preread and then a continous data stream.
+
 entity tx_fifo is
   port(
     CLK               : in  std_logic;
diff --git a/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd b/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd
index dbc79b9..47036ee 100644
--- a/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd
+++ b/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd
@@ -17,6 +17,8 @@ use work.trb_net_gbe_components.all;
 -- WARNING: data latency was wrong by one cycle (first byte not sent, last byte duplicated), and
 --          size was calculated wrong (one off). Works now FOR ME. To be tested carefully!
 
+-- BUG: If a frame written triggers FIFOFULL, it must be discarded. Maximum frame payload is 4096bytes.
+
 entity trb_net16_gbe_response_constructor_Forward is
   port (
     CLK                     : in  std_logic;  -- system clock
diff --git a/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd b/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd
index 3c7306c..cdfd969 100644
--- a/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd
+++ b/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd
@@ -14,82 +14,78 @@ use work.trb_net_gbe_protocols.all;
 
 entity trb_net16_gbe_response_constructor_SCTRL is
 generic ( STAT_ADDRESS_BASE : integer := 0;
-	SLOWCTRL_BUFFER_SIZE : integer range 1 to 4 := 1
+  SLOWCTRL_BUFFER_SIZE : integer range 1 to 4 := 1
 );
-	port (
-		CLK			: in	std_logic;  -- system clock
-		RESET			: in	std_logic;
-		
-	-- INTERFACE	
-		MY_MAC_IN				: in std_logic_vector(47 downto 0);
-		MY_IP_IN				: in std_logic_vector(31 downto 0);
-		PS_DATA_IN		: in	std_logic_vector(8 downto 0);
-		PS_WR_EN_IN		: in	std_logic;
-		PS_ACTIVATE_IN		: in	std_logic;
-		PS_RESPONSE_READY_OUT	: out	std_logic;
-		PS_BUSY_OUT		: out	std_logic;
-		PS_SELECTED_IN		: in	std_logic;
-		PS_SRC_MAC_ADDRESS_IN	: in	std_logic_vector(47 downto 0);
-		PS_DEST_MAC_ADDRESS_IN  : in	std_logic_vector(47 downto 0);
-		PS_SRC_IP_ADDRESS_IN	: in	std_logic_vector(31 downto 0);
-		PS_DEST_IP_ADDRESS_IN	: in	std_logic_vector(31 downto 0);
-		PS_SRC_UDP_PORT_IN	: in	std_logic_vector(15 downto 0);
-		PS_DEST_UDP_PORT_IN	: in	std_logic_vector(15 downto 0);
-			
-		TC_RD_EN_IN		: in	std_logic;
-		TC_DATA_OUT		: out	std_logic_vector(8 downto 0);
-		TC_FRAME_SIZE_OUT	: out	std_logic_vector(15 downto 0);
-		TC_FRAME_TYPE_OUT	: out	std_logic_vector(15 downto 0);
-		TC_IP_PROTOCOL_OUT	: out	std_logic_vector(7 downto 0);	
-		TC_IDENT_OUT        : out	std_logic_vector(15 downto 0);	
-		TC_DEST_MAC_OUT		: out	std_logic_vector(47 downto 0);
-		TC_DEST_IP_OUT		: out	std_logic_vector(31 downto 0);
-		TC_DEST_UDP_OUT		: out	std_logic_vector(15 downto 0);
-		TC_SRC_MAC_OUT		: out	std_logic_vector(47 downto 0);
-		TC_SRC_IP_OUT		: out	std_logic_vector(31 downto 0);
-		TC_SRC_UDP_OUT		: out	std_logic_vector(15 downto 0);
-		
-		STAT_DATA_OUT : out std_logic_vector(31 downto 0);
-		STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
-		STAT_DATA_RDY_OUT : out std_logic;
-		STAT_DATA_ACK_IN  : in std_logic;
-		
-		DEBUG_OUT		  : out std_logic_vector(63 downto 0);
-	-- END OF INTERFACE
-	
-	-- protocol specific ports
-		GSC_CLK_IN               : in std_logic;
-		GSC_INIT_DATAREADY_OUT   : out std_logic;
-		GSC_INIT_DATA_OUT        : out std_logic_vector(15 downto 0);
-		GSC_INIT_PACKET_NUM_OUT  : out std_logic_vector(2 downto 0);
-		GSC_INIT_READ_IN         : in std_logic;
-		GSC_REPLY_DATAREADY_IN   : in std_logic;
-		GSC_REPLY_DATA_IN        : in std_logic_vector(15 downto 0);
-		GSC_REPLY_PACKET_NUM_IN  : in std_logic_vector(2 downto 0);
-		GSC_REPLY_READ_OUT       : out std_logic;
-		GSC_BUSY_IN              : in std_logic;
-		MAKE_RESET_OUT           : out std_logic;
-		CFG_ADDITIONAL_HDR_IN    : in std_logic;
-		CFG_MAX_REPLY_SIZE_IN    : in std_logic_vector(31 downto 0);
-	-- end of protocol specific ports
-	
-		MONITOR_SELECT_REC_OUT	      : out	std_logic_vector(31 downto 0);
-		MONITOR_SELECT_REC_BYTES_OUT  : out	std_logic_vector(31 downto 0);
-		MONITOR_SELECT_SENT_BYTES_OUT : out	std_logic_vector(31 downto 0);
-		MONITOR_SELECT_SENT_OUT	      : out	std_logic_vector(31 downto 0);
-		
-		DATA_HIST_OUT : out hist_array
-	);
+  port (
+    CLK                           : in  std_logic;  -- system clock
+    RESET                         : in  std_logic;
+                                  
+  -- INTERFACE                    
+    MY_MAC_IN                     : in  std_logic_vector(47 downto 0);
+    MY_IP_IN                      : in  std_logic_vector(31 downto 0);
+    PS_DATA_IN                    : in  std_logic_vector(8 downto 0);
+    PS_WR_EN_IN                   : in  std_logic;
+    PS_ACTIVATE_IN                : in  std_logic;
+    PS_RESPONSE_READY_OUT         : out std_logic;
+    PS_BUSY_OUT                   : out std_logic;
+    PS_SELECTED_IN                : in  std_logic;
+    PS_SRC_MAC_ADDRESS_IN         : in  std_logic_vector(47 downto 0);
+    PS_DEST_MAC_ADDRESS_IN        : in  std_logic_vector(47 downto 0);
+    PS_SRC_IP_ADDRESS_IN          : in  std_logic_vector(31 downto 0);
+    PS_DEST_IP_ADDRESS_IN         : in  std_logic_vector(31 downto 0);
+    PS_SRC_UDP_PORT_IN            : in  std_logic_vector(15 downto 0);
+    PS_DEST_UDP_PORT_IN           : in  std_logic_vector(15 downto 0);
+                                  
+    TC_RD_EN_IN                   : in  std_logic;
+    TC_DATA_OUT                   : out std_logic_vector(8 downto 0);
+    TC_FRAME_SIZE_OUT             : out std_logic_vector(15 downto 0);
+    TC_FRAME_TYPE_OUT             : out std_logic_vector(15 downto 0);
+    TC_IP_PROTOCOL_OUT            : out std_logic_vector(7 downto 0);	
+    TC_IDENT_OUT                  : out std_logic_vector(15 downto 0);	
+    TC_DEST_MAC_OUT               : out std_logic_vector(47 downto 0);
+    TC_DEST_IP_OUT                : out std_logic_vector(31 downto 0);
+    TC_DEST_UDP_OUT               : out std_logic_vector(15 downto 0);
+    TC_SRC_MAC_OUT                : out std_logic_vector(47 downto 0);
+    TC_SRC_IP_OUT                 : out std_logic_vector(31 downto 0);
+    TC_SRC_UDP_OUT                : out std_logic_vector(15 downto 0);
+                                  
+    STAT_DATA_OUT                 : out std_logic_vector(31 downto 0);
+    STAT_ADDR_OUT                 : out std_logic_vector(7 downto 0);
+    STAT_DATA_RDY_OUT             : out std_logic;
+    STAT_DATA_ACK_IN              : in  std_logic;
+                                  
+    DEBUG_OUT                     : out std_logic_vector(63 downto 0);
+  -- END OF INTERFACE
+
+  -- protocol specific ports
+    GSC_CLK_IN                    : in  std_logic;
+    GSC_INIT_DATAREADY_OUT        : out std_logic;
+    GSC_INIT_DATA_OUT             : out std_logic_vector(15 downto 0);
+    GSC_INIT_PACKET_NUM_OUT       : out std_logic_vector(2 downto 0);
+    GSC_INIT_READ_IN              : in  std_logic;
+    GSC_REPLY_DATAREADY_IN        : in  std_logic;
+    GSC_REPLY_DATA_IN             : in  std_logic_vector(15 downto 0);
+    GSC_REPLY_PACKET_NUM_IN       : in  std_logic_vector(2 downto 0);
+    GSC_REPLY_READ_OUT            : out std_logic;
+    GSC_BUSY_IN                   : in  std_logic;
+    MAKE_RESET_OUT                : out std_logic;
+    CFG_MAX_REPLY_SIZE_IN         : in  std_logic_vector(31 downto 0);
+  -- end of protocol specific ports
+
+    MONITOR_SELECT_REC_OUT	      : out	std_logic_vector(31 downto 0);
+    MONITOR_SELECT_REC_BYTES_OUT  : out	std_logic_vector(31 downto 0);
+    MONITOR_SELECT_SENT_BYTES_OUT : out	std_logic_vector(31 downto 0);
+    MONITOR_SELECT_SENT_OUT	      : out	std_logic_vector(31 downto 0);
+
+    DATA_HIST_OUT                 : out hist_array
+  );
 end entity trb_net16_gbe_response_constructor_SCTRL;
 
 architecture RTL of trb_net16_gbe_response_constructor_SCTRL is
 
 attribute syn_encoding	: string;
 
---type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, LOAD_FRAME, WAIT_FOR_TC, DIVIDE, WAIT_FOR_LOAD, CLEANUP);
 type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, LOAD_FRAME, WAIT_FOR_LOAD, CLEANUP);
---type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_A_WORD, WAIT_ONE, WAIT_TWO, WAIT_FOR_RESPONSE, SAVE_RESPONSE, LOAD_FRAME, WAIT_FOR_TC, DIVIDE, WAIT_FOR_LOAD, CLEANUP);
---type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, LOAD_FRAME, WAIT_FOR_TC, DIVIDE, WAIT_FOR_LOAD, CLEANUP);
 signal dissect_current_state, dissect_next_state : dissect_states;
 attribute syn_encoding of dissect_current_state: signal is "onehot";
 
@@ -100,12 +96,11 @@ attribute syn_encoding of stats_current_state : signal is "onehot";
 signal saved_target_ip          : std_logic_vector(31 downto 0);
 signal data_ctr                 : integer range 0 to 30;
 
-
 signal stat_data_temp           : std_logic_vector(31 downto 0);
 signal rec_frames               : std_logic_vector(15 downto 0);
 
 signal rx_fifo_q                : std_logic_vector(17 downto 0);
-signal rx_fifo_qq                : std_logic_vector(17 downto 0);
+signal rx_fifo_qq               : std_logic_vector(17 downto 0);
 signal rx_fifo_wr, rx_fifo_rd   : std_logic;
 signal tx_eod, rx_eod           : std_logic;
 
@@ -114,7 +109,7 @@ signal tx_fifo_wr, tx_fifo_rd   : std_logic;
 signal tx_fifo_reset            : std_logic;
 signal gsc_reply_read           : std_logic;
 signal gsc_init_dataready       : std_logic;
-signal gsc_init_dataready_q       : std_logic;
+signal gsc_init_dataready_q     : std_logic;
 
 signal tx_data_ctr              : std_logic_vector(15 downto 0);
 signal tx_loaded_ctr            : std_logic_vector(15 downto 0);
@@ -133,15 +128,15 @@ signal reset_detected           : std_logic := '0';
 signal make_reset               : std_logic := '0';
 
 
-signal fifo_rd_q               : std_logic;
+signal fifo_rd_q                : std_logic;
 
-signal too_much_data           : std_logic;
+signal too_much_data            : std_logic;
 
-signal rx_fifo_data            : std_logic_vector(8 downto 0);
-signal tx_fifo_data            : std_logic_vector(17 downto 0);
+signal rx_fifo_data             : std_logic_vector(8 downto 0);
+signal tx_fifo_data             : std_logic_vector(17 downto 0);
 
-signal tc_wr                   : std_logic;
-signal state                   : std_logic_vector(3 downto 0);
+signal tc_wr                    : std_logic;
+signal state                    : std_logic_vector(3 downto 0);
 signal saved_hdr_1              : std_logic_vector(7 downto 0) := x"ab";
 signal saved_hdr_2              : std_logic_vector(7 downto 0) := x"cd";
 signal saved_hdr_ctr            : std_logic_vector(3 downto 0);
@@ -164,146 +159,73 @@ MAKE_RESET_OUT <= make_reset;
 
 receive_fifo : entity work.fifo_2kx9x18_wcnt
   PORT map(
-    Reset            => RESET,
-	RPReset          => RESET,
-    WrClock          => CLK,
-	RdClock          => CLK,
-    Data             => rx_fifo_data,
-    WrEn             => rx_fifo_wr,
-    RdEn             => rx_fifo_rd,
-    Q                => rx_fifo_q,
-    Full             => rx_full,
-    Empty            => rx_empty,
-    WCNT => rx_cnt(11 downto 0)
+    Reset    => RESET,
+    RPReset  => RESET,
+    WrClock  => CLK,
+    RdClock  => CLK,
+    Data     => rx_fifo_data,
+    WrEn     => rx_fifo_wr,
+    RdEn     => rx_fifo_rd,
+    Q        => rx_fifo_q,
+    Full     => rx_full,
+    Empty    => rx_empty,
+    WCNT     => rx_cnt(11 downto 0)
   );
 
 --TODO: change to synchronous
-rx_fifo_rd              <= '1' when (gsc_init_dataready = '1' and dissect_current_state = LOAD_TO_HUB) or 
-								(gsc_init_dataready = '1' and dissect_current_state = WAIT_FOR_HUB and GSC_INIT_READ_IN = '1') or
-								(dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1')
-								else '0';  -- preload first word
-								
+rx_fifo_rd <= '1' when (gsc_init_dataready = '1' and dissect_current_state = LOAD_TO_HUB) or 
+                       (gsc_init_dataready = '1' and dissect_current_state = WAIT_FOR_HUB and GSC_INIT_READ_IN = '1') or
+                       (dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1')
+              else '0';  -- preload first word
+              
 RX_FIFO_WR_SYNC : process(CLK)
 begin
-	if rising_edge(CLK) then
-	
-		if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' and (saved_hdr_ctr = "0100" or saved_hdr_ctr = "1000")) then
-			rx_fifo_wr <= '1';
-		else
-			rx_fifo_wr <= '0';
-		end if;
-		
-		rx_fifo_data <= PS_DATA_IN;
-	end if;
+  if rising_edge(CLK) then
+
+    if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' and (saved_hdr_ctr = "0100" or saved_hdr_ctr = "1000")) then
+      rx_fifo_wr <= '1';
+    else
+      rx_fifo_wr <= '0';
+    end if;
+  
+    rx_fifo_data <= PS_DATA_IN;
+  end if;
 end process RX_FIFO_WR_SYNC;
 
 SAVED_HDR_CTR_PROC : process(CLK)
 begin
-	if rising_edge(CLK) then
-		if (dissect_current_state = IDLE and PS_WR_EN_IN = '0' and PS_ACTIVATE_IN = '0') then
-			saved_hdr_ctr <= "0001";
-		elsif (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' and saved_hdr_ctr /= "1000") then
-			saved_hdr_ctr(3 downto 0) <= saved_hdr_ctr(2 downto 0) & '0';
-		else
-			saved_hdr_ctr <= saved_hdr_ctr;
-		end if;
-	end if;
+  if rising_edge(CLK) then
+    if (dissect_current_state = IDLE and PS_WR_EN_IN = '0' and PS_ACTIVATE_IN = '0') then
+      saved_hdr_ctr <= "0001";
+    elsif (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' and saved_hdr_ctr /= "1000") then
+      saved_hdr_ctr(3 downto 0) <= saved_hdr_ctr(2 downto 0) & '0';
+    else
+      saved_hdr_ctr <= saved_hdr_ctr;
+    end if;
+  end if;
 end process SAVED_HDR_CTR_PROC;
 
 SAVED_HDR_PROC : process(CLK)
 begin
-	if rising_edge(CLK) then
-		if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
-			if (saved_hdr_ctr = "0001") then
-				saved_hdr_1 <= PS_DATA_IN(7 downto 0);
-				saved_hdr_2 <= saved_hdr_2;
-			elsif (saved_hdr_ctr = "0010") then
-				saved_hdr_2 <= PS_DATA_IN(7 downto 0);
-				saved_hdr_1 <= saved_hdr_1;
-			else
-				saved_hdr_1 <= saved_hdr_1;
-				saved_hdr_2 <= saved_hdr_2;
-			end if;
-		else
-			saved_hdr_1 <= saved_hdr_1;
-			saved_hdr_2 <= saved_hdr_2;
-		end if;
-	end if;
+  if rising_edge(CLK) then
+    if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
+      if (saved_hdr_ctr = "0001") then
+        saved_hdr_1 <= PS_DATA_IN(7 downto 0);
+        saved_hdr_2 <= saved_hdr_2;
+      elsif (saved_hdr_ctr = "0010") then
+        saved_hdr_2 <= PS_DATA_IN(7 downto 0);
+        saved_hdr_1 <= saved_hdr_1;
+      else
+        saved_hdr_1 <= saved_hdr_1;
+        saved_hdr_2 <= saved_hdr_2;
+      end if;
+    else
+      saved_hdr_1 <= saved_hdr_1;
+      saved_hdr_2 <= saved_hdr_2;
+    end if;
+  end if;
 end process SAVED_HDR_PROC;
 
---RX_FIFO_RD_SYNC : process(CLK)
---begin
---	if rising_edge(CLK) then
---	
---		if (dissect_current_state = LOAD_A_WORD) then
---			rx_fifo_rd <= '1';
---		else
---			rx_fifo_rd <= '0';
---		end if;
---		
-----		if (dissect_current_state = WAIT_ONE) then
-----			gsc_init_dataready <= '1';
-----		elsif (dissect_current_state = WAIT_FOR_HUB and GSC_INIT_READ_IN = '0') then
-----			gsc_init_dataready <= '1';
-----		else
-----			gsc_init_dataready <= '0';
-----		end if;
---
-----		if (dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1') then  -- preload the first byte
-----			rx_fifo_rd <= '1';
-----		elsif (dissect_current_state = LOAD_TO_HUB) then
-----			rx_fifo_rd <= '1';
-----		elsif (dissect_current_state = WAIT_FOR_HUB and GSC_INIT_READ_IN = '1') then
-----			rx_fifo_rd <= '1';
-----		else
-----			rx_fifo_rd <= '0';
-----		end if;
-----		
-----		if (dissect_current_state = WAIT_FOR_HUB) then
-----			gsc_init_dataready <= '1';
-----		elsif (dissect_current_state = LOAD_TO_HUB and GSC_INIT_READ_IN = '1') then
-----			gsc_init_dataready <= '1';
-----		else
-----			gsc_init_dataready <= '0';
-----		end if;
-----		
-----		if (dissect_current_state = WAIT_FOR_HUB) then
-----			packet_num <= "100";
-----		elsif (dissect_current_state = LOAD_TO_HUB) then
-----			if (gsc_init_dataready = '1' and packet_num = "100") then
-----				packet_num <= "000";
-----			elsif (gsc_init_dataready = '1' and packet_num /= "100") then
-----				packet_num <= packet_num + "1";
-----			else
-----				packet_num <= packet_num;
-----			end if;
-----		else
-----			packet_num <= packet_num;
-----		end if;
---
---		if (dissect_current_state = READ_FRAME) then
---			packet_num <= "011";
---		elsif (dissect_current_state = LOAD_A_WORD) then
---			if (packet_num = "100") then
---				packet_num <= "000";
---			else
---				packet_num <= packet_num + "1";
---			end if;
---		else
---			packet_num <= packet_num;
---		end if;
---	
---		GSC_INIT_DATA_OUT(7 downto 0)  <= rx_fifo_q(16 downto 9);
---		GSC_INIT_DATA_OUT(15 downto 8) <= rx_fifo_q(7 downto 0);
---		
---		--GSC_INIT_DATAREADY_OUT  <= gsc_init_dataready;
---		
-----		GSC_INIT_PACKET_NUM_OUT <= packet_num;
---	
---	end if;
---end process RX_FIFO_RD_SYNC;
---
---GSC_INIT_DATAREADY_OUT <= '1' when dissect_current_state = WAIT_FOR_HUB else '0';
 
 ----TODO: add a register
 GSC_INIT_DATA_OUT(7 downto 0)  <= rx_fifo_q(16 downto 9);
@@ -313,546 +235,428 @@ GSC_INIT_DATA_OUT(15 downto 8) <= rx_fifo_q(7 downto 0);
 GSC_INIT_PACKET_NUM_OUT <= packet_num;
 GSC_INIT_DATAREADY_OUT  <= gsc_init_dataready;
 gsc_init_dataready <= '1' when (GSC_INIT_READ_IN = '1' and dissect_current_state = LOAD_TO_HUB) or  --TODO Ob das so richtig ist, ohne auf fifo_rd zu schauen?
-							   (dissect_current_state = WAIT_FOR_HUB) else '0';
+                               (dissect_current_state = WAIT_FOR_HUB) 
+                      else '0';
 
 PACKET_NUM_PROC : process(CLK)
 begin
-	if rising_edge(CLK) then
-		if (dissect_current_state = IDLE) then
-			packet_num <= "100";
-		elsif (GSC_INIT_READ_IN = '1' and rx_fifo_rd = '1' and packet_num = "100" and dissect_current_state /= READ_FRAME) then  --BUG zählt schon hoch beim fifo_rd weil read schon 1 ist. read geht aber nur auf 1 wenn dataready auf 1 ist
-			packet_num <= "000";
-		elsif (rx_fifo_rd = '1' and packet_num /= "100") then
-			packet_num <= packet_num + "1";
-		end if;
-	end if;
+  if rising_edge(CLK) then
+    if (dissect_current_state = IDLE) then
+      packet_num <= "100";
+    elsif (GSC_INIT_READ_IN = '1' and rx_fifo_rd = '1' and packet_num = "100" and dissect_current_state /= READ_FRAME) then  --BUG zählt schon hoch beim fifo_rd weil read schon 1 ist. read geht aber nur auf 1 wenn dataready auf 1 ist
+      packet_num <= "000";
+    elsif (rx_fifo_rd = '1' and packet_num /= "100") then
+      packet_num <= packet_num + "1";
+    end if;
+  end if;
 end process PACKET_NUM_PROC;
 
 tf_4k_gen : if SLOWCTRL_BUFFER_SIZE = 1 generate
-	transmit_fifo : entity work.fifo_4kx18x9_wcnt
-	  PORT map(
-	    Reset             => tx_fifo_reset,
-		RPReset           => tx_fifo_reset,
-	    WrClock           => CLK,
-		RdClock           => CLK,
-		Data              => tx_fifo_data,
-	    WrEn              => tx_fifo_wr,
-	    RdEn              => tx_fifo_rd,
-	    Q                 => tx_fifo_q,
-	    Full              => tx_full,
-	    Empty             => tx_empty,
-	    WCNT => tx_cnt(11 downto 0)
-	  );
+  transmit_fifo : entity work.fifo_4kx18x9_wcnt
+  PORT map(
+    Reset    => tx_fifo_reset,
+    RPReset  => tx_fifo_reset,
+    WrClock  => CLK,
+    RdClock  => CLK,
+    Data     => tx_fifo_data,
+    WrEn     => tx_fifo_wr,
+    RdEn     => tx_fifo_rd,
+    Q        => tx_fifo_q,
+    Full     => tx_full,
+    Empty    => tx_empty,
+    WCNT     => tx_cnt(11 downto 0)
+  );
 end generate tf_4k_gen;
 
 tf_65k_gen : if SLOWCTRL_BUFFER_SIZE = 2 generate
-	transmit_fifo : entity work.fifo_64kx18x9_wcnt
-	  PORT map(
-	    Reset             => tx_fifo_reset,
-		RPReset           => tx_fifo_reset,
-	    WrClock           => CLK,
-		RdClock           => CLK,
-		Data              => tx_fifo_data,
-	    WrEn              => tx_fifo_wr,
-	    RdEn              => tx_fifo_rd,
-	    Q                 => tx_fifo_q,
-	    Full              => tx_full,
-	    Empty             => tx_empty,
-	    WCNT => tx_cnt
-	  );
+  transmit_fifo : entity work.fifo_64kx18x9_wcnt
+  PORT map(
+    Reset    => tx_fifo_reset,
+    RPReset  => tx_fifo_reset,
+    WrClock  => CLK,
+    RdClock  => CLK,
+    Data     => tx_fifo_data,
+    WrEn     => tx_fifo_wr,
+    RdEn     => tx_fifo_rd,
+    Q        => tx_fifo_q,
+    Full     => tx_full,
+    Empty    => tx_empty,
+    WCNT     => tx_cnt
+  );
 end generate tf_65k_gen;
 
 TX_FIFO_WR_SYNC : process(CLK)
 begin
-	if rising_edge(CLK) then
-		if (GSC_REPLY_DATAREADY_IN = '1' and gsc_reply_read = '1') then
-			tx_fifo_wr <= '1';
-		elsif (saved_hdr_ctr = "0010") then
-			tx_fifo_wr <= '1';
-		else
-			tx_fifo_wr <= '0';
-		end if;
-		
-		if (saved_hdr_ctr = "010") then
-			tx_fifo_data <= '0' & PS_DATA_IN(7 downto 0) & '0' & x"02";
-		else
-			tx_fifo_data(7 downto 0)  <= GSC_REPLY_DATA_IN(15 downto 8);
-			tx_fifo_data(8)           <= '0';
-			tx_fifo_data(16 downto 9) <= GSC_REPLY_DATA_IN(7 downto 0);
-			tx_fifo_data(17)          <= '0';
-		end if;
-	end if;
+  if rising_edge(CLK) then
+    if (GSC_REPLY_DATAREADY_IN = '1' and gsc_reply_read = '1') then
+      tx_fifo_wr <= '1';
+    elsif (saved_hdr_ctr = "0010") then
+      tx_fifo_wr <= '1';
+    else
+      tx_fifo_wr <= '0';
+    end if;
+  
+    if (saved_hdr_ctr = "010") then
+      tx_fifo_data <= '0' & PS_DATA_IN(7 downto 0) & '0' & x"02";
+    else
+      tx_fifo_data(7 downto 0)  <= GSC_REPLY_DATA_IN(15 downto 8);
+      tx_fifo_data(8)           <= '0';
+      tx_fifo_data(16 downto 9) <= GSC_REPLY_DATA_IN(7 downto 0);
+      tx_fifo_data(17)          <= '0';
+    end if;
+  end if;
 end process TX_FIFO_WR_SYNC;
 
---TX_FIFO_RD_SYNC : process(CLK)
---begin
---	if rising_edge(CLK) then
---		if (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1' and tx_frame_loaded /= g_MAX_FRAME_SIZE) then
---			tx_fifo_rd <= '1';
---		else
---			tx_fifo_rd <= '0';
---		end if;
---	end if;
---end process TX_FIFO_RD_SYNC;
 tx_fifo_rd <= '1' when TC_RD_EN_IN = '1' and PS_SELECTED_IN = '1' else '0';
-		
+
 TX_FIFO_SYNC_PROC : process(CLK)
 begin
-	if rising_edge(CLK) then
-		if (RESET = '1') or (too_much_data = '1' and dissect_current_state = CLEANUP) then
-			tx_fifo_reset <= '1';
-		else
-			tx_fifo_reset <= '0';
-		end if;
-	end if;
+  if rising_edge(CLK) then
+    if (RESET = '1') or (too_much_data = '1' and dissect_current_state = CLEANUP) then
+      tx_fifo_reset <= '1';
+    else
+      tx_fifo_reset <= '0';
+    end if;
+  end if;
 end process TX_FIFO_SYNC_PROC;
 
 TC_DATA_PROC : process(CLK)
 begin
-	if rising_edge(CLK) then
-
-		TC_DATA_OUT(7 downto 0) <= tx_fifo_q(7 downto 0);
-		
-		--if (tx_loaded_ctr = tx_data_ctr + x"1" or tx_frame_loaded = g_MAX_FRAME_SIZE - x"1") then
-		if (tx_loaded_ctr = tx_data_ctr) then
-			TC_DATA_OUT(8) <= '1';
-		else
-			TC_DATA_OUT(8) <= '0';
-		end if;
-	end if;
+  if rising_edge(CLK) then
+
+    TC_DATA_OUT(7 downto 0) <= tx_fifo_q(7 downto 0);
+  
+    if (tx_loaded_ctr = tx_data_ctr) then
+      TC_DATA_OUT(8) <= '1';
+    else
+      TC_DATA_OUT(8) <= '0';
+    end if;
+  end if;
 end process TC_DATA_PROC;
 
 GSC_REPLY_READ_PROC : process(CLK)
 begin
-	if rising_edge(CLK) then
-		if (dissect_current_state = WAIT_FOR_RESPONSE or dissect_current_state = SAVE_RESPONSE) then
-			gsc_reply_read <= '1';
-		else
-			gsc_reply_read <= '0';
-		end if;
-	end if;
+  if rising_edge(CLK) then
+    if (dissect_current_state = WAIT_FOR_RESPONSE or dissect_current_state = SAVE_RESPONSE) then
+      gsc_reply_read <= '1';
+    else
+      gsc_reply_read <= '0';
+    end if;
+  end if;
 end process GSC_REPLY_READ_PROC;
 GSC_REPLY_READ_OUT      <= gsc_reply_read;
 
 -- counter of data received from TRBNet hub
 TX_DATA_CTR_PROC : process(CLK)
 begin
-	if rising_edge(CLK) then
-		if (dissect_current_state = IDLE) then
-			tx_data_ctr <= (others => '0');
-		elsif (tx_fifo_wr = '1') then
-			tx_data_ctr <= tx_data_ctr + x"2";
-		end if;
-	end if;
+  if rising_edge(CLK) then
+    if (dissect_current_state = IDLE) then
+      tx_data_ctr <= (others => '0');
+    elsif (tx_fifo_wr = '1') then
+      tx_data_ctr <= tx_data_ctr + x"2";
+    end if;
+  end if;
 end process TX_DATA_CTR_PROC;
 
 TOO_MUCH_DATA_PROC : process(CLK)
 begin
-	if rising_edge(CLK) then
-		if (dissect_current_state = IDLE) then
-			too_much_data <= '0';
-		elsif (dissect_current_state = SAVE_RESPONSE) and (tx_data_ctr = CFG_MAX_REPLY_SIZE_IN(15 downto 0)) then
-			too_much_data <= '1';
-		else
-			too_much_data <= too_much_data;
-		end if;
-	end if;
+  if rising_edge(CLK) then
+    if (dissect_current_state = IDLE) then
+      too_much_data <= '0';
+    elsif (dissect_current_state = SAVE_RESPONSE) and (tx_data_ctr = CFG_MAX_REPLY_SIZE_IN(15 downto 0)) then
+      too_much_data <= '1';
+    else
+      too_much_data <= too_much_data;
+    end if;
+  end if;
 end process TOO_MUCH_DATA_PROC;
 
 -- total counter of data transported to frame constructor
 TX_LOADED_CTR_PROC : process(CLK)
 begin
-	if rising_edge(CLK) then
-		if (dissect_current_state = IDLE) then
-			tx_loaded_ctr <= x"0000";
-		elsif (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1') then
-			tx_loaded_ctr <= tx_loaded_ctr + x"1";
-		else
-			tx_loaded_ctr <= tx_loaded_ctr;
-		end if;
-	end if;
+  if rising_edge(CLK) then
+    if (dissect_current_state = IDLE) then
+      tx_loaded_ctr <= x"0000";
+    elsif (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1') then
+      tx_loaded_ctr <= tx_loaded_ctr + x"1";
+    else
+      tx_loaded_ctr <= tx_loaded_ctr;
+    end if;
+  end if;
 end process TX_LOADED_CTR_PROC;
-						
+
 PS_RESPONSE_SYNC : process(CLK)
 begin
-	if rising_edge(CLK) then
-		if (too_much_data = '0') then
-			if (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP) then
-				PS_RESPONSE_READY_OUT <= '1';
-			else
-				PS_RESPONSE_READY_OUT <= '0';
-			end if;
-		end if;
-		
-		if (dissect_current_state = IDLE or dissect_current_state = WAIT_FOR_RESPONSE) then
-			PS_BUSY_OUT <= '0';
-		else
-			PS_BUSY_OUT <= '1';
-		end if;
-	end if;	
+  if rising_edge(CLK) then
+    if (too_much_data = '0') then
+      if (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP) then
+        PS_RESPONSE_READY_OUT <= '1';
+      else
+        PS_RESPONSE_READY_OUT <= '0';
+      end if;
+    end if;
+  
+    if (dissect_current_state = IDLE or dissect_current_state = WAIT_FOR_RESPONSE) then
+      PS_BUSY_OUT <= '0';
+    else
+      PS_BUSY_OUT <= '1';
+    end if;
+  end if;	
 end process PS_RESPONSE_SYNC;
 
-TC_FRAME_TYPE_OUT  <= x"0008";
-TC_DEST_MAC_OUT    <= PS_SRC_MAC_ADDRESS_IN;
-TC_DEST_IP_OUT     <= PS_SRC_IP_ADDRESS_IN;
-TC_DEST_UDP_OUT(7 downto 0)    <= PS_SRC_UDP_PORT_IN(15 downto 8);
-TC_DEST_UDP_OUT(15 downto 8)   <= PS_SRC_UDP_PORT_IN(7 downto 0);
-TC_SRC_MAC_OUT     <= MY_MAC_IN;
-TC_SRC_IP_OUT      <= MY_IP_IN;
-TC_SRC_UDP_OUT     <= x"9065"; --x"a861";
-TC_IP_PROTOCOL_OUT <= x"11";
-TC_IDENT_OUT       <= x"3" & reply_ctr(11 downto 0);
+TC_FRAME_TYPE_OUT            <= x"0008";
+TC_DEST_MAC_OUT              <= PS_SRC_MAC_ADDRESS_IN;
+TC_DEST_IP_OUT               <= PS_SRC_IP_ADDRESS_IN;
+TC_DEST_UDP_OUT(7 downto 0)  <= PS_SRC_UDP_PORT_IN(15 downto 8);
+TC_DEST_UDP_OUT(15 downto 8) <= PS_SRC_UDP_PORT_IN(7 downto 0);
+TC_SRC_MAC_OUT               <= MY_MAC_IN;
+TC_SRC_IP_OUT                <= MY_IP_IN;
+TC_SRC_UDP_OUT               <= x"9065"; --x"a861";
+TC_IP_PROTOCOL_OUT           <= x"11";
+TC_IDENT_OUT                 <= x"3" & reply_ctr(11 downto 0);
 
 TC_FRAME_SIZE_OUT   <= tx_data_ctr;
 
 DISSECT_MACHINE_PROC : process(RESET, CLK)
 begin
-	if RESET = '1' then
-		dissect_current_state <= IDLE;
-	elsif rising_edge(CLK) then
---		if (RESET = '1') then
---			if (g_SIMULATE = 0) then
---				dissect_current_state <= IDLE;
---			else
---				dissect_current_state <= WAIT_FOR_RESPONSE;
---			end if;
---		else
-			dissect_current_state <= dissect_next_state;
---		end if;
-	end if;
+  if RESET = '1' then
+    dissect_current_state <= IDLE;
+  elsif rising_edge(CLK) then
+    dissect_current_state <= dissect_next_state;
+  end if;
 end process DISSECT_MACHINE_PROC;
 
 DISSECT_MACHINE : process(dissect_current_state, reset_detected, too_much_data, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, PS_SELECTED_IN, GSC_INIT_READ_IN, GSC_REPLY_DATAREADY_IN, tx_loaded_ctr, tx_data_ctr, rx_fifo_q, GSC_BUSY_IN)
 begin
-	state <= x"0";
-	
-	case dissect_current_state is
-	
-		when IDLE =>
-			state <= x"1";
-			if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
-				dissect_next_state <= READ_FRAME;
-			else
-				dissect_next_state <= IDLE;
-			end if;
-		
-		when READ_FRAME =>
-			state <= x"2";
-			if (PS_DATA_IN(8) = '1' and (GSC_INIT_READ_IN = '0')) then
-				dissect_next_state <= WAIT_FOR_HUB;
-			elsif (PS_DATA_IN(8) = '1' and (GSC_INIT_READ_IN = '1')) then
-				dissect_next_state <= LOAD_TO_HUB;
-			else
-				dissect_next_state <= READ_FRAME;
-			end if;
-			
-		when WAIT_FOR_HUB =>
-			state <= x"3";
-			if (GSC_INIT_READ_IN = '1') then
-				dissect_next_state <= LOAD_TO_HUB;
-			else
-				dissect_next_state <= WAIT_FOR_HUB;
-			end if;						
-		
-		when LOAD_TO_HUB =>
-			state <= x"4";
---			if (rx_fifo_q(17) = '1') then
-			if ((rx_fifo_q(17) = '1') and (GSC_INIT_READ_IN = '1')) then
-				if (reset_detected = '1') then
-					dissect_next_state <= CLEANUP;
-				else
-					dissect_next_state <= WAIT_FOR_RESPONSE;
-				end if;
-			else
-				dissect_next_state <= LOAD_TO_HUB;
-			end if;	
-			
-		when WAIT_FOR_RESPONSE =>
-			state <= x"5";
-			if (GSC_REPLY_DATAREADY_IN = '1') then
-				dissect_next_state <= SAVE_RESPONSE;
-			else
-				dissect_next_state <= WAIT_FOR_RESPONSE;
-			end if;
-			
-		when SAVE_RESPONSE =>
-			state <= x"6";
-			if (GSC_REPLY_DATAREADY_IN = '0' and GSC_BUSY_IN = '0') then
-				if (too_much_data = '0') then
-					dissect_next_state <= WAIT_FOR_LOAD;
-				else
-					dissect_next_state <= CLEANUP;
-				end if;
-			else
-				dissect_next_state <= SAVE_RESPONSE;
-			end if;			
-			
-		when WAIT_FOR_LOAD =>
-			state <= x"7";
-			if (PS_SELECTED_IN = '1') then
-				dissect_next_state <= LOAD_FRAME;
-			else
-				dissect_next_state <= WAIT_FOR_LOAD;
-			end if;
-			
-		when LOAD_FRAME =>
-			state <= x"8";
-			if (tx_loaded_ctr = tx_data_ctr) then
-				dissect_next_state <= CLEANUP;
-			else
-				dissect_next_state <= LOAD_FRAME;
-			end if;
-		
-		when CLEANUP =>
-			state <= x"9";
-			dissect_next_state <= IDLE;
-			
-		when others => dissect_next_state <= IDLE;
-	
-	end case;
+  state <= x"0";
+
+  case dissect_current_state is
+
+    when IDLE =>
+      state <= x"1";
+      if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
+        dissect_next_state <= READ_FRAME;
+      else
+        dissect_next_state <= IDLE;
+      end if;
+  
+    when READ_FRAME =>
+      state <= x"2";
+      if (PS_DATA_IN(8) = '1' and (GSC_INIT_READ_IN = '0')) then
+        dissect_next_state <= WAIT_FOR_HUB;
+      elsif (PS_DATA_IN(8) = '1' and (GSC_INIT_READ_IN = '1')) then
+        dissect_next_state <= LOAD_TO_HUB;
+      else
+        dissect_next_state <= READ_FRAME;
+      end if;
+    
+    when WAIT_FOR_HUB =>
+      state <= x"3";
+      if (GSC_INIT_READ_IN = '1') then
+        dissect_next_state <= LOAD_TO_HUB;
+      else
+        dissect_next_state <= WAIT_FOR_HUB;
+      end if;						
+  
+    when LOAD_TO_HUB =>
+      state <= x"4";
+      if ((rx_fifo_q(17) = '1') and (GSC_INIT_READ_IN = '1')) then
+        if (reset_detected = '1') then
+          dissect_next_state <= CLEANUP;
+        else
+          dissect_next_state <= WAIT_FOR_RESPONSE;
+        end if;
+      else
+        dissect_next_state <= LOAD_TO_HUB;
+      end if;	
+     
+    when WAIT_FOR_RESPONSE =>
+      state <= x"5";
+      if (GSC_REPLY_DATAREADY_IN = '1') then
+        dissect_next_state <= SAVE_RESPONSE;
+      else
+        dissect_next_state <= WAIT_FOR_RESPONSE;
+      end if;
+    
+    when SAVE_RESPONSE =>
+      state <= x"6";
+      if (GSC_REPLY_DATAREADY_IN = '0' and GSC_BUSY_IN = '0') then
+        if (too_much_data = '0') then
+          dissect_next_state <= WAIT_FOR_LOAD;
+        else
+          dissect_next_state <= CLEANUP;
+        end if;
+      else
+        dissect_next_state <= SAVE_RESPONSE;
+      end if;			
+
+    when WAIT_FOR_LOAD =>
+      state <= x"7";
+      if (PS_SELECTED_IN = '1') then
+        dissect_next_state <= LOAD_FRAME;
+      else
+        dissect_next_state <= WAIT_FOR_LOAD;
+      end if;
+
+    when LOAD_FRAME =>
+      state <= x"8";
+      if (tx_loaded_ctr = tx_data_ctr) then
+        dissect_next_state <= CLEANUP;
+      else
+        dissect_next_state <= LOAD_FRAME;
+      end if;
+
+    when CLEANUP =>
+      state <= x"9";
+      dissect_next_state <= IDLE;
+
+    when others => dissect_next_state <= IDLE;
+
+  end case;
 end process DISSECT_MACHINE;
 
 -- reset request packet detection
- RESET_DETECTED_PROC : process(CLK)
- begin
-	 if rising_edge(CLK) then
-		 if (dissect_current_state = IDLE) then
-			 reset_detected <= '0';
-		 elsif (PS_DATA_IN(7 downto 0) = x"80" and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' and saved_hdr_ctr = "0100") then
-			 reset_detected <= '1';
-		else
-			reset_detected <= reset_detected;
-		 end if;
-	 end if;
- end process RESET_DETECTED_PROC;
+RESET_DETECTED_PROC : process(CLK)
+begin
+  if rising_edge(CLK) then
+    if (dissect_current_state = IDLE) then
+      reset_detected <= '0';
+    elsif (PS_DATA_IN(7 downto 0) = x"80" and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' and saved_hdr_ctr = "0100") then
+      reset_detected <= '1';
+  else
+    reset_detected <= reset_detected;
+    end if;
+  end if;
+end process RESET_DETECTED_PROC;
  
- MAKE_RESET_PROC : process(CLK)
- begin
-	 if rising_edge(CLK) then
-		 if (dissect_current_state = IDLE) then
-			 make_reset <= '0';
-		 elsif (dissect_current_state = CLEANUP and reset_detected = '1') then
-			 make_reset <= '1';
-		else
-			make_reset <= make_reset;
-		 end if;
-	 end if;
- end process MAKE_RESET_PROC;
+MAKE_RESET_PROC : process(CLK)
+begin
+  if rising_edge(CLK) then
+    if (dissect_current_state = IDLE) then
+      make_reset <= '0';
+    elsif (dissect_current_state = CLEANUP and reset_detected = '1') then
+      make_reset <= '1';
+  else
+    make_reset <= make_reset;
+    end if;
+  end if;
+end process MAKE_RESET_PROC;
 
 
 -- monitoring
 
 hist_ctrs_gen : for i in 0 to 31 generate
 
-	process(CLK)
-	begin
-		if rising_edge(CLK) then
-			if (RESET = '1') then
-				reset_all_hist(i) <= '1';
-			elsif (hist_inst(i) = x"ffff_ffff") then
-				reset_all_hist(i) <= '1';
-			else
-				reset_all_hist(i) <= '0';
-			end if;				
-		end if;
-	end process;
-
-	process(CLK)
-	begin
-		if rising_edge(CLK) then
-			if (reset_all_hist /= x"0000_0000") then
-				hist_inst(i) <= (others => '0');
-			elsif (dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr and i = to_integer(unsigned(tx_data_ctr(15 downto 11)))) then
-				hist_inst(i) <= hist_inst(i) + x"1"; 
-			else
-				hist_inst(i) <= hist_inst(i);
-			end if;
-		end if;
-	end process;
-	
+  process(CLK)
+  begin
+    if rising_edge(CLK) then
+      if (RESET = '1') then
+        reset_all_hist(i) <= '1';
+      elsif (hist_inst(i) = x"ffff_ffff") then
+        reset_all_hist(i) <= '1';
+      else
+        reset_all_hist(i) <= '0';
+      end if;				
+    end if;
+  end process;
+
+  process(CLK)
+  begin
+    if rising_edge(CLK) then
+      if (reset_all_hist /= x"0000_0000") then
+        hist_inst(i) <= (others => '0');
+      elsif (dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr and i = to_integer(unsigned(tx_data_ctr(15 downto 11)))) then
+        hist_inst(i) <= hist_inst(i) + x"1"; 
+      else
+        hist_inst(i) <= hist_inst(i);
+      end if;
+    end if;
+  end process;
+
 end generate hist_ctrs_gen;
 
 DATA_HIST_OUT <= hist_inst;
 
-
 process(CLK)
 begin
-	if rising_edge(CLK) then
-		DEBUG_OUT(0) <= rx_full;
-		DEBUG_OUT(1) <= rx_empty;
-		DEBUG_OUT(2) <= tx_full;
-		DEBUG_OUT(3) <= tx_empty;
-		DEBUG_OUT(7 downto 4) <= state;
-		DEBUG_OUT(23 downto 8) <= rx_cnt;
-		DEBUG_OUT(39 downto 24) <= tx_cnt;
-		DEBUG_OUT(63 downto 40) <= (others => '0');
-	end if;
+  if rising_edge(CLK) then
+    DEBUG_OUT(0) <= rx_full;
+    DEBUG_OUT(1) <= rx_empty;
+    DEBUG_OUT(2) <= tx_full;
+    DEBUG_OUT(3) <= tx_empty;
+    DEBUG_OUT(7 downto 4) <= state;
+    DEBUG_OUT(23 downto 8) <= rx_cnt;
+    DEBUG_OUT(39 downto 24) <= tx_cnt;
+    DEBUG_OUT(63 downto 40) <= (others => '0');
+  end if;
 end process;
 
 process(CLK)
 begin
-	if rising_edge(CLK) then
-		if (RESET = '1') then
-			mon_rec_frames <= (others => '0');
-		elsif (dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1') then
-			mon_rec_frames <= mon_rec_frames + x"1";
-		else
-			mon_rec_frames <= mon_rec_frames;
-		end if;
-	end if;
+  if rising_edge(CLK) then
+    if (RESET = '1') then
+      mon_rec_frames <= (others => '0');
+    elsif (dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1') then
+      mon_rec_frames <= mon_rec_frames + x"1";
+    else
+      mon_rec_frames <= mon_rec_frames;
+    end if;
+  end if;
 end process;
 MONITOR_SELECT_REC_OUT <= mon_rec_frames;
 
 process(CLK)
 begin
-	if rising_edge(CLK) then
-		if (RESET = '1') then
-			mon_rec_bytes <= (others => '0');
-		elsif (rx_fifo_wr = '1') then
-			mon_rec_bytes <= mon_rec_bytes + x"1";
-		else
-			mon_rec_bytes <= mon_rec_bytes;
-		end if;
-	end if;
+  if rising_edge(CLK) then
+    if (RESET = '1') then
+      mon_rec_bytes <= (others => '0');
+    elsif (rx_fifo_wr = '1') then
+      mon_rec_bytes <= mon_rec_bytes + x"1";
+    else
+      mon_rec_bytes <= mon_rec_bytes;
+    end if;
+  end if;
 end process;
 MONITOR_SELECT_REC_BYTES_OUT <= mon_rec_bytes;
 
 process(CLK)
 begin
-	if rising_edge(CLK) then
-		if (RESET = '1') then
-			mon_sent_frames <= (others => '0');
-		elsif (dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr) then
-			mon_sent_frames <= mon_sent_frames + x"1";
-		else
-			mon_sent_frames <= mon_sent_frames;
-		end if;
-	end if;
+  if rising_edge(CLK) then
+    if (RESET = '1') then
+      mon_sent_frames <= (others => '0');
+    elsif (dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr) then
+      mon_sent_frames <= mon_sent_frames + x"1";
+    else
+      mon_sent_frames <= mon_sent_frames;
+    end if;
+  end if;
 end process;
 MONITOR_SELECT_SENT_OUT <= mon_sent_frames;
 
 process(CLK)
 begin
-	if rising_edge(CLK) then
-		if (RESET = '1') then
-			mon_sent_bytes <= (others => '0');
-		elsif (tx_fifo_rd = '1') then
-			mon_sent_bytes <= mon_sent_bytes + x"1";
-		else
-			mon_sent_bytes <= mon_sent_bytes;
-		end if;
-	end if;
+  if rising_edge(CLK) then
+    if (RESET = '1') then
+      mon_sent_bytes <= (others => '0');
+    elsif (tx_fifo_rd = '1') then
+      mon_sent_bytes <= mon_sent_bytes + x"1";
+    else
+      mon_sent_bytes <= mon_sent_bytes;
+    end if;
+  end if;
 end process;
 MONITOR_SELECT_SENT_BYTES_OUT <= mon_sent_bytes;
 
--- statistics
---REC_FRAMES_PROC : process(CLK)
---begin
---	if rising_edge(CLK) then
---		if (RESET = '1') then
---			rec_frames <= (others => '0');
---		elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
---			rec_frames <= rec_frames + x"1";
---		end if;
---	end if;
---end process REC_FRAMES_PROC;
---
 -- needed for identification
 REPLY_CTR_PROC : process(CLK)
 begin
-	if rising_edge(CLK) then
-		if (RESET = '1') then
-			reply_ctr <= (others => '0');
-		elsif (dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr) then
-			reply_ctr <= reply_ctr + x"1";
-		end if;
-	end if;
+  if rising_edge(CLK) then
+    if (RESET = '1') then
+      reply_ctr <= (others => '0');
+    elsif (dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr) then
+      reply_ctr <= reply_ctr + x"1";
+    end if;
+  end if;
 end process REPLY_CTR_PROC;
---
---
---STATS_MACHINE_PROC : process(CLK)
---begin
---	if rising_edge(CLK) then
---		if (RESET = '1') then
---			stats_current_state <= IDLE;
---		else
---			stats_current_state <= stats_next_state;
---		end if;
---	end if;
---end process STATS_MACHINE_PROC;
---
---STATS_MACHINE : process(stats_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, dissect_current_state, tx_loaded_ctr, tx_data_ctr)
---begin
---
---	case (stats_current_state) is
---	
---		when IDLE =>
---			if ((dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') or (dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr)) then
---				stats_next_state <= LOAD_RECEIVED;
---			else
---				stats_next_state <= IDLE;
---			end if;
---		
---		when LOAD_RECEIVED =>
---			if (STAT_DATA_ACK_IN = '1') then
---				stats_next_state <= LOAD_REPLY;
---			else
---				stats_next_state <= LOAD_RECEIVED;
---			end if;
---			
---		when LOAD_REPLY =>
---			if (STAT_DATA_ACK_IN = '1') then
---				stats_next_state <= CLEANUP;
---			else
---				stats_next_state <= LOAD_REPLY;
---			end if;		
---		
---		when CLEANUP =>
---			stats_next_state <= IDLE;
---	
---	end case;
---
---end process STATS_MACHINE;
---
---SELECTOR : process(CLK)
---begin
---	if rising_edge(CLK) then
---		case(stats_current_state) is
---			
---			when LOAD_RECEIVED =>
---				stat_data_temp <= x"0502" & rec_frames;
---				STAT_ADDR_OUT  <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8));
---			
---			when LOAD_REPLY =>
---				stat_data_temp <= x"0503" & reply_ctr;
---				STAT_ADDR_OUT  <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8));
---				
---			when others =>
---				stat_data_temp <= (others => '0');
---				STAT_ADDR_OUT  <= (others => '0');
---		
---		end case;
---	end if;	
---end process SELECTOR;
---
---STAT_DATA_OUT(7 downto 0)   <= stat_data_temp(31 downto 24);
---STAT_DATA_OUT(15 downto 8)  <= stat_data_temp(23 downto 16);
---STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8);
---STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0);
---
---STAT_SYNC : process(CLK)
---begin
---	if rising_edge(CLK) then
---		if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then
---			STAT_DATA_RDY_OUT <= '1';
---		else
---			STAT_DATA_RDY_OUT <= '0';
---		end if;
---	end if;
---end process STAT_SYNC;
-----STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0';
---
----- end of statistics
-
 
 end architecture RTL;
diff --git a/trb_net16_addresses.vhd b/trb_net16_addresses.vhd
index 348524e..f1d22b4 100644
--- a/trb_net16_addresses.vhd
+++ b/trb_net16_addresses.vhd
@@ -74,16 +74,16 @@ architecture trb_net16_addresses_arch of trb_net16_addresses is
       );
   end component;
 
-signal ram_read_addr : std_logic_vector(3 downto 0);
-signal ram_read_dout : std_logic_vector(15 downto 0);
-signal matching_counter : std_logic_vector(2 downto 0);
-signal ram_read_addr1 : std_logic_vector(3 downto 0);
-signal ram_read_addr2 : std_logic_vector(3 downto 0);
-signal last_ram_read_addr2 : std_logic_vector(3 downto 0);
+signal ram_read_addr          : std_logic_vector(3 downto 0);
+signal ram_read_dout          : std_logic_vector(15 downto 0);
+signal matching_counter       : std_logic_vector(2 downto 0);
+signal ram_read_addr1         : std_logic_vector(3 downto 0);
+signal ram_read_addr2         : std_logic_vector(3 downto 0);
+signal last_ram_read_addr2    : std_logic_vector(3 downto 0);
 signal buf_API_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0);
-signal buf_API_READ_OUT : std_logic;
-signal buf_API_SEND_OUT : std_logic;
-signal recv_set_address : std_logic;
+signal buf_API_READ_OUT       : std_logic;
+signal buf_API_SEND_OUT       : std_logic;
+signal recv_set_address       : std_logic;
 
 signal next_state, state : std_logic_vector(c_NUM_WIDTH-1 downto 0);
 
@@ -286,10 +286,10 @@ begin
       dout2   => ram_read_dout
       );
 
-API_READ_OUT <= buf_API_READ_OUT;
-API_SEND_OUT <= delayed_buf_API_SEND_OUT;
+API_READ_OUT       <= buf_API_READ_OUT;
+API_SEND_OUT       <= delayed_buf_API_SEND_OUT;
 API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT;
-ADDRESS_OUT <= buf_ADDRESS_OUT;
+ADDRESS_OUT        <= buf_ADDRESS_OUT;
 
 
 
@@ -307,4 +307,4 @@ STAT_DEBUG(15 downto 12) <= "0000"; --added by regio!
 --   STAT_ADDR_DEBUG(14) <= ADR_SEND_OUT;
 --   STAT_ADDR_DEBUG(15) <= ADR_DATAREADY_OUT;      --dataready out of addresses
 
-end architecture;
\ No newline at end of file
+end architecture;
diff --git a/trb_net16_endpoint_standalone_sctrl.vhd b/trb_net16_endpoint_standalone_sctrl.vhd
index bedd0b3..3a80ed7 100644
--- a/trb_net16_endpoint_standalone_sctrl.vhd
+++ b/trb_net16_endpoint_standalone_sctrl.vhd
@@ -21,14 +21,12 @@ entity trb_net16_endpoint_standalone_sctrl is
     REGIO_INIT_ENDPOINT_ID       : std_logic_vector(15 downto 0) := x"0001";
     REGIO_USE_VAR_ENDPOINT_ID    : integer range c_NO to c_YES   := c_NO;
     REGIO_USE_1WIRE_INTERFACE    : integer range 0 to 5 := c_YES
-    );
-
+  );
   port(
     --  Misc
     CLK                          : in  std_logic;
     RESET                        : in  std_logic;
     CLK_EN                       : in  std_logic := '1';
-    
     --Port to GbE
     GSC_INIT_DATAREADY_IN        : in  std_logic;
     GSC_INIT_DATA_IN             : in  std_logic_vector(15 downto 0);
@@ -40,14 +38,12 @@ entity trb_net16_endpoint_standalone_sctrl is
     GSC_REPLY_READ_IN            : in  std_logic;    
     GSC_BUSY_OUT                 : out std_logic;
     GBE_MAKE_RESET_IN            : in  std_logic; --for monitoring only
-    
     --Slow Control Port
     --common registers 0x00-0x2F
     REGIO_COMMON_STAT_REG_IN     : in  std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
     REGIO_COMMON_CTRL_REG_OUT    : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
     REGIO_COMMON_STAT_STROBE_OUT : out std_logic_vector(std_COMSTATREG-1 downto 0);
     REGIO_COMMON_CTRL_STROBE_OUT : out std_logic_vector(std_COMCTRLREG-1 downto 0);
-
     --internal data port
     BUS_RX                       : out CTRLBUS_RX;
     BUS_TX                       : in  CTRLBUS_TX;
@@ -55,12 +51,10 @@ entity trb_net16_endpoint_standalone_sctrl is
     BUS_MASTER_IN                : out CTRLBUS_TX;
     BUS_MASTER_OUT               : in  CTRLBUS_RX := (data => (others => '0'), addr => (others => '0'), write => '0', read => '0', timeout => '0');
     BUS_MASTER_ACTIVE            : in  std_logic := '0';
-
     --Sensors & ID
     ONEWIRE_INOUT                : inout std_logic;
     I2C_SCL                      : inout std_logic;
     I2C_SDA                      : inout std_logic;
-
     TIMERS_OUT                   : out TIMERS; --clock ticks, temperature, unique id
     MY_ADDRESS_OUT               : out std_logic_vector(15 downto 0)
   );
@@ -187,9 +181,9 @@ begin
       )
     port map(
     --  Misc
-      CLK      => CLK,
-      RESET    => RESET,
-      CLK_EN   => '1',
+      CLK                    => CLK,
+      RESET                  => RESET,
+      CLK_EN                 => '1',
     -- Port to API
       API_DATA_OUT           => buf_APL_DATA_IN,
       API_PACKET_NUM_OUT     => buf_APL_PACKET_NUM_IN,
@@ -243,12 +237,13 @@ begin
       STAT_ADDR_DEBUG        => open
       );
       
-  REGIO_COMMON_STAT_STROBE_OUT   <= buf_COMMON_STAT_REG_STROBE;
-  REGIO_COMMON_CTRL_STROBE_OUT   <= buf_COMMON_CTRL_REG_STROBE;      
-  REGIO_COMMON_CTRL_REG_OUT      <= buf_COMMON_CTRL_REG_OUT;
+  REGIO_COMMON_STAT_STROBE_OUT <= buf_COMMON_STAT_REG_STROBE;
+  REGIO_COMMON_CTRL_STROBE_OUT <= buf_COMMON_CTRL_REG_STROBE;      
+  REGIO_COMMON_CTRL_REG_OUT    <= buf_COMMON_CTRL_REG_OUT;
       
-  TIMERS_OUT.temperature  <= temperature_i;
-  TIMERS_OUT.uid          <= unique_id_i;        
+  TIMERS_OUT.temperature       <= temperature_i;
+  TIMERS_OUT.uid               <= unique_id_i;
+  TIMERS_OUT.network_address   <= my_address_i;
 
   BUS_RX <= regio_rx when BUS_MASTER_ACTIVE = '0' else BUS_MASTER_OUT;
   BUS_MASTER_IN <= BUS_TX;  
diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd
index 1655fbd..23e3d6e 100644
--- a/trb_net16_regIO.vhd
+++ b/trb_net16_regIO.vhd
@@ -213,9 +213,9 @@ begin
 
   the_addresses : trb_net16_addresses
     generic map(
-      INIT_ADDRESS   => INIT_ADDRESS,
-      INIT_UNIQUE_ID => INIT_UNIQUE_ID,
-      INIT_BOARD_INFO=> INIT_BOARD_INFO,
+      INIT_ADDRESS     => INIT_ADDRESS,
+      INIT_UNIQUE_ID   => INIT_UNIQUE_ID,
+      INIT_BOARD_INFO  => INIT_BOARD_INFO,
       INIT_ENDPOINT_ID => INIT_ENDPOINT_ID
       )
     port map(
-- 
2.43.0