From 3da98f056e2207f1083b02b069e61a4accf394d0 Mon Sep 17 00:00:00 2001 From: Michael Traxler Date: Thu, 31 Jan 2019 01:55:28 +0100 Subject: [PATCH] added some general words about a DiRICH-System, mt --- trb3/DiRich.tex | 65 ++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 64 insertions(+), 1 deletion(-) diff --git a/trb3/DiRich.tex b/trb3/DiRich.tex index f0bf6ff..2128af1 100644 --- a/trb3/DiRich.tex +++ b/trb3/DiRich.tex @@ -1,7 +1,70 @@ - \begin{figure} +\begin{figure} \begin{center} \includegraphics[width=0.7\textwidth]{figures/dirichcombiner_connections.png} \caption[DiRich Combiner Front Panel]{Connections and LEDs on the DiRich combiner front-panel} \label{fig:dirichcombinerfrontpanel} \end{center} \end{figure} + +The DiRICH system is a variant of the TRB3-system. + +The system consists of a DiRICH-modulem which combines a galvanic isolation at +the input, an amplifier (gain ~30), a discriminator, TDC and an fill +DAQ-system ``TRBNet'' all on the centra FPGA (ECP5UM-80) on board. The +thresholds are produced by two peripheral MachXO3-FPGAs, which are controlled +by the central FPGA. +All inputs and outpts (including power) are on the front connector. + +Therefore the DiRICH is used on a backplane, which routes all the signals and +power to the right place. + +Currently we have backplanes for the CBM/HADES-RICH based on MAPMTs H12700 and +for the PANDA-Barrel-DIRC (MCP-PMT). +\begin{itemize*} +\item The backplane for the MAPMTs is available for 3x2 MAPTS and 2x2 MAPMTs. +\item The backplane for the MCP-PMTs are available for 2x2 MCP-PMTs. +\end{itemize*} + +For a working system one needs the connection to the outside world, which was +implemented via two modules at the sides of the backplanes. +One is the ``DiRICH-Concentrator1'', which utilizes up to 12 SERDES links to the +DiRICH-modules for data transfer. Additionally, it receives the reference-time +via a RJ45 connector (in the firmware +\begin{lstlisting} + dirich_combiner_20180327.bit +\end{lstlisting} +it is the RJ45 connector near the edge of the PCB) and the optional external +clock (if enables in the firmware). + +The ``DiRICH-Power1'' has the power-connector. We have two options for the +power supply. For the best performance (low noise) we use pre regulated supply +lines, for 1.1V (DiRich core and DiRich amplifiers), 1.2V (for the concentrator FPGA +core), 2.5V and 3.3V. The disadvantage of this method of powering the system +is the effort you have to supply the quite large current on 1.1V and to take +care that the voltage drop on the cables is not too large. +If equipped with the DC/DC converters it takes a single 32V input and provides +all the needed voltages on board. +The DiRICH-Power1 additionally has an input connector for the HV for the +MAPMTs (not for the MCP-PMTs backplane, which assumes that the HV goes via +cables to the MCP-PMT). The DiRICH-Power1 also serves as reference-time and +clock fanout board. + +Overvoltage: +You are not allowed to increase the input voltages above 5.5V at any rail. +There is not really a way to have an overvoltage anywhere (e.g. 1.1V if the +input is at 2V), as all voltages (except 3.3V) are regulated on the DiRICH, +and the common 3.3V is regulated on the ``DiRich-Power1''. +The only thing which will happen is that you produce more heat. +The minimum overvoltage in front of the LDOs has to be 60mV for +each voltage, so that the regulators really work as expected. + +After you connected the TRBNet optical link to the hub of a TRB3/sc the +DiRICH-system is a part of the TRBNet as any other TRB3/sc. + +To check the input voltages and currents, there is a tool available: examples +\begin{itemize*} +\item a DiRICH: ~/trbsoft/daqtools/tools/trb3scadc.pl 0x1593 1 +\item a Concentrator for voltages: ~/trbsoft/daqtools/tools/trb3scadc.pl + 0xf3dc 2 +\item the current flowing: ~/trbsoft/daqtools/tools/trb3scadc.pl 0xf3dc 4 +\end{itemize*} -- 2.43.0