From 3dc3beeb8bd3b162a77d9725f26c54abd9db6aed Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 30 Jul 2014 18:53:15 +0200 Subject: [PATCH] added record for trigger and readout ports --- trb_net16_endpoint_hades_full_handler.vhd | 6 +- trb_net_std.vhd | 70 +++++++++++++++++------ 2 files changed, 58 insertions(+), 18 deletions(-) diff --git a/trb_net16_endpoint_hades_full_handler.vhd b/trb_net16_endpoint_hades_full_handler.vhd index 7f3844c..f795e68 100644 --- a/trb_net16_endpoint_hades_full_handler.vhd +++ b/trb_net16_endpoint_hades_full_handler.vhd @@ -194,6 +194,7 @@ architecture trb_net16_endpoint_hades_full_handler_arch of trb_net16_endpoint_ha signal time_since_last_trg_i : std_logic_vector (31 downto 0); signal time_ticks_i : std_logic_vector ( 1 downto 0); + signal buf_fee_data_almost_full_out : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); signal stat_handler_i : std_logic_vector (127 downto 0); signal stat_data_buffer_level : std_logic_vector (DATA_INTERFACE_NUMBER*32-1 downto 0); signal stat_header_buffer_level: std_logic_vector (31 downto 0); @@ -574,7 +575,7 @@ stat_handler_registers(2) <= stat_handler_i(95 downto 64); FEE_DATA_IN => FEE_DATA_IN, FEE_DATA_WRITE_IN => FEE_DATA_WRITE_IN, FEE_DATA_FINISHED_IN => FEE_DATA_FINISHED_IN, - FEE_DATA_ALMOST_FULL_OUT => FEE_DATA_ALMOST_FULL_OUT, + FEE_DATA_ALMOST_FULL_OUT => buf_fee_data_almost_full_out, TMG_TRG_ERROR_IN => tmg_trg_error_i, MAX_EVENT_SIZE_IN => max_event_size, @@ -602,7 +603,8 @@ stat_handler_registers(2) <= stat_handler_i(95 downto 64); STAT_DEBUG_DATA_HANDLER_OUT <= debug_data_handler_i; tmg_trg_error_i <= int_lvl1_missing_tmg_trg or int_lvl1_spurious_trg or int_lvl1_timeout_detected or int_multiple_trg or int_spike_detected or int_lvl1_long_trg; - + FEE_DATA_ALMOST_FULL_OUT <= (others => or_all(buf_fee_data_almost_full_out)); + --------------------------------------------------------------------------- -- Connect Status Registers --------------------------------------------------------------------------- diff --git a/trb_net_std.vhd b/trb_net_std.vhd index 3e230a4..d62e1dc 100644 --- a/trb_net_std.vhd +++ b/trb_net_std.vhd @@ -149,13 +149,65 @@ package trb_net_std is --constant VERSION_NUMBER_TIME : std_logic_vector(31 downto 0) := conv_std_logic_vector(1234567890,32); + type CTRLBUS_TX is record + data : std_logic_vector(31 downto 0); + ack : std_logic; + wack,rack : std_logic; --for the old-fashioned guys + unknown : std_logic; + nack : std_logic; + end record; + + type CTRLBUS_RX is record + data : std_logic_vector(31 downto 0); + addr : std_logic_vector(15 downto 0); + write : std_logic; + read : std_logic; + timeout : std_logic; + end record; + + + type READOUT_RX is record + data_valid : std_logic; + valid_timing_trg : std_logic; + valid_notiming_trg : std_logic; + invalid_trg : std_logic; + -- + trg_type : std_logic_vector( 3 downto 0); + trg_number : std_logic_vector(15 downto 0); + trg_code : std_logic_vector( 7 downto 0); + trg_information : std_logic_vector(23 downto 0); + trg_int_number : std_logic_vector(15 downto 0); + -- + trg_multiple : std_logic; + trg_timeout : std_logic; + trg_spurious : std_logic; + trg_missing : std_logic; + trg_spike : std_logic; + -- + buffer_almost_full : std_logic; + end record; + + + type READOUT_TX is record + busy_release : std_logic; + statusbits : std_logic_vector(31 downto 0); + data : std_logic_vector(31 downto 0); + data_write : std_logic; + data_finished : std_logic; + end record; + + + type std_logic_vector_array_36 is array (integer range <>) of std_logic_vector(35 downto 0); type std_logic_vector_array_32 is array (integer range <>) of std_logic_vector(31 downto 0); type std_logic_vector_array_24 is array (integer range <>) of std_logic_vector(23 downto 0); type std_logic_vector_array_11 is array (integer range <>) of std_logic_vector(10 downto 0); type std_logic_vector_array_8 is array (integer range <>) of std_logic_vector(7 downto 0); + type int_array_t is array(integer range <>) of integer; - + type ctrlbus_tx_array_t is array (integer range <>) of CTRLBUS_TX; + type ctrlbus_rx_array_t is array (integer range <>) of CTRLBUS_RX; + type readout_tx_array_t is array (integer range <>) of READOUT_TX; --function declarations function and_all (arg : std_logic_vector) @@ -185,21 +237,7 @@ package trb_net_std is end package trb_net_std; package body trb_net_std is - - type CTRLBUS_TX is record - data : std_logic_vector(31 downto 0); - ack : std_logic; - unknown : std_logic; - nack : std_logic; - end record; - - type CTRLBUS_RX is record - data : std_logic_vector(31 downto 0); - addr : std_logic_vector(15 downto 0); - write : std_logic; - read : std_logic; - timeout : std_logic; - end record; + function and_all (arg : std_logic_vector) return std_logic is -- 2.43.0