From 3de952ebf71a779008f74a6863c2ac8351ef9e6f Mon Sep 17 00:00:00 2001 From: Peter Lemmens Date: Tue, 20 Jan 2015 16:08:26 +0100 Subject: [PATCH] Trb med_xxxx signals reconnected. SYSCLK of med_ecp3_sfp_4_sync_down.vhd connected to rxup_full_clk instead of clk_100_osc. Preferences in ldf file debugged and simplified. Some 100 timing errors remain (setup) mostly rx_full_clk, some clk_200_osc. --- Cu_trb3_soda_client.ldf | 331 ------------------------ Cu_trb3_soda_client.lpf | 198 --------------- Cu_trb3_soda_client.xcf | 223 ----------------- code/med_ecp3_sfp_4_sync_down.vhd | 61 +++-- code/med_ecp3_sfp_sync_up.vhd | 25 +- code/soda_components.vhd | 4 +- code/soda_hub.vhd | 2 +- code/trb3_periph_sodahub.vhd | 28 ++- soda_hub.ldf | 2 +- soda_hub.lpf | 8 +- soda_hub_probe.rvl | 400 ++++++++---------------------- trb3_soda_hub.xcf | 6 +- 12 files changed, 187 insertions(+), 1101 deletions(-) delete mode 100644 Cu_trb3_soda_client.ldf delete mode 100644 Cu_trb3_soda_client.lpf delete mode 100644 Cu_trb3_soda_client.xcf diff --git a/Cu_trb3_soda_client.ldf b/Cu_trb3_soda_client.ldf deleted file mode 100644 index 7763b36..0000000 --- a/Cu_trb3_soda_client.ldf +++ /dev/null @@ -1,331 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Cu_trb3_soda_client.lpf b/Cu_trb3_soda_client.lpf deleted file mode 100644 index 0e626da..0000000 --- a/Cu_trb3_soda_client.lpf +++ /dev/null @@ -1,198 +0,0 @@ -rvl_alias "reveal_ist_125" "the_sync_link/rx_full_clk"; -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -BLOCK RD_DURING_WR_PATHS ; -################################################################# -# Basic Settings -################################################################# -# SYSCONFIG MCCLK_FREQ = 2.5; -# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; -# FREQUENCY PORT "CLK_PCLK_LEFT" 200.000000 MHz ; -# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; -################################################################# -# Clock I/O -################################################################# -#LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ; -#LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ; -#LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18"; -#LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";s -LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ; -#LOCATE COMP "CLK_GPLL_LEFT" SITE "U25"; -DEFINE PORT GROUP "CLK_group" "CLK*" ; -IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ; -################################################################# -# Trigger I/O -################################################################# -#Trigger from fan-out -#LOCATE COMP "TRIGGER_LEFT" SITE "V3"; -#LOCATE COMP "TRIGGER_RIGHT" SITE "N24"; -#IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ; -#IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ; -################################################################# -# To central FPGA -################################################################# -LOCATE COMP "FPGA5_COMM_0" SITE "AD4"; -LOCATE COMP "FPGA5_COMM_1" SITE "AE3"; -LOCATE COMP "FPGA5_COMM_2" SITE "AA7"; -LOCATE COMP "FPGA5_COMM_3" SITE "AB7"; -LOCATE COMP "FPGA5_COMM_4" SITE "AD3"; -LOCATE COMP "FPGA5_COMM_5" SITE "AC4"; -LOCATE COMP "FPGA5_COMM_6" SITE "AE2"; -LOCATE COMP "FPGA5_COMM_7" SITE "AF3"; -LOCATE COMP "FPGA5_COMM_8" SITE "AE4"; -LOCATE COMP "FPGA5_COMM_9" SITE "AF4"; -LOCATE COMP "FPGA5_COMM_10" SITE "V10"; -LOCATE COMP "FPGA5_COMM_11" SITE "W10"; -DEFINE PORT GROUP "FPGA_group" "FPGA*" ; -IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; -LOCATE COMP "TEST_LINE[0]" SITE "A5" ; -LOCATE COMP "TEST_LINE[1]" SITE "A6" ; -LOCATE COMP "TEST_LINE[2]" SITE "G8" ; -LOCATE COMP "TEST_LINE[3]" SITE "F9" ; -LOCATE COMP "TEST_LINE[4]" SITE "D9" ; -LOCATE COMP "TEST_LINE[5]" SITE "D10" ; -LOCATE COMP "TEST_LINE[6]" SITE "F10" ; -LOCATE COMP "TEST_LINE[7]" SITE "E10" ; -LOCATE COMP "TEST_LINE[8]" SITE "A8" ; -LOCATE COMP "TEST_LINE[9]" SITE "B8" ; -LOCATE COMP "TEST_LINE[10]" SITE "G10" ; -LOCATE COMP "TEST_LINE[11]" SITE "G9" ; -LOCATE COMP "TEST_LINE[12]" SITE "C9" ; -LOCATE COMP "TEST_LINE[13]" SITE "C10" ; -LOCATE COMP "TEST_LINE[14]" SITE "H10" ; -LOCATE COMP "TEST_LINE[15]" SITE "H11" ; -DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; -IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ; -################################################################# -# Connection to AddOn -################################################################# -LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0 #1 -LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1 #3 -LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2 #5 -LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3 #7 -#LOCATE COMP "SFP_MOD1_1" SITE "R1"; #DQLL0_4 #9 -#LOCATE COMP "SFP_MOD2_1" SITE "R2"; #DQLL0_5 #11 -#LOCATE COMP "SFP_RATESEL_1" SITE "N3"; #DQSLL0_T #13 -LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C #15 -LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6 #17 -#LOCATE COMP "SFP_TXFAULT_1" SITE "P6"; #DQLL0_7 #19 -LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8 #21 -LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9 #23 -LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0 #25 -LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1 #27 -#LOCATE COMP "SFP_MOD1_2" SITE "AB1"; #DQLL2_2 #29 -#LOCATE COMP "SFP_MOD2_2" SITE "AC1"; #DQLL2_3 #31 -#LOCATE COMP "SFP_RATESEL_2" SITE "AA1"; #DQLL2_4 #33 -LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5 #35 -LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2 -#LOCATE COMP "SFP_TXFAULT_2" SITE "W6"; #DQLL2_C #39 #should be DQSLL2 -LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0 #2 -LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1 #4 -LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2 #6 -LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3 #8 -#LOCATE COMP "SFP_MOD1_3" SITE "AB3"; #DQLL3_4 #10 -#LOCATE COMP "SFP_MOD2_3" SITE "AB4"; #DQLL3_5 #12 -#LOCATE COMP "SFP_RATESEL_3" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3 -LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3 -LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6 #18 -#LOCATE COMP "SFP_TXFAULT_3" SITE "AA4"; #DQLL3_7 #20 -LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8 #22 -LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9 #24 -LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0 #26 -LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1 #28 -#LOCATE COMP "SFP_MOD1_4" SITE "T1"; #DQLL1_2 #30 -#LOCATE COMP "SFP_MOD2_4" SITE "U1"; #DQLL1_3 #32 -#LOCATE COMP "SFP_RATESEL_4" SITE "P4"; #DQLL1_4 #34 -LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5 #36 -LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T #38 -#LOCATE COMP "SFP_TXFAULT_4" SITE "R4"; #DQSLL1_C #40 -LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0 #169 -LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1 #171 -LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2 #173 -LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3 #175 -#LOCATE COMP "SFP_MOD1_5" SITE "AA26"; #DQLR1_4 #177 -#LOCATE COMP "SFP_MOD2_5" SITE "AB26"; #DQLR1_5 #179 -#LOCATE COMP "SFP_RATESEL_5" SITE "W21"; #DQSLR1_T #181 -LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C #183 -LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6 #185 -#LOCATE COMP "SFP_TXFAULT_5" SITE "AA23"; #DQLR1_7 #187 -LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0 #170 -LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1 #172 -LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2 #174 -LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3 #176 -#LOCATE COMP "SFP_MOD1_6" SITE "T26"; #DQLR2_4 #178 -#LOCATE COMP "SFP_MOD2_6" SITE "U26"; #DQLR2_5 #180 -#LOCATE COMP "SFP_RATESEL_6" SITE "V21"; #DQSLR2_T #182 -LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C #184 -LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6 #186 -#LOCATE COMP "SFP_TXFAULT_6" SITE "V24"; #DQLR2_7 #188 -DEFINE PORT GROUP "SFP_group" "SFP*" ; -IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; -################################################################# -# Additional Lines to AddOn -################################################################# -#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3 -#all lines are input only -#line 4/5 go to PLL input -#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194 -#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196 -#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198 -#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200 -#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69 -#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71 -################################################################# -# Flash ROM and Reboot -################################################################# -LOCATE COMP "FLASH_CLK" SITE "B12" ; -LOCATE COMP "FLASH_CS" SITE "E11" ; -LOCATE COMP "FLASH_DIN" SITE "E12" ; -LOCATE COMP "FLASH_DOUT" SITE "A12" ; -DEFINE PORT GROUP "FLASH_group" "FLASH*" ; -IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ; -LOCATE COMP "PROGRAMN" SITE "B11" ; -IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; -################################################################# -# Misc -################################################################# -LOCATE COMP "TEMPSENS" SITE "A13" ; -IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; -#coding of FPGA number -LOCATE COMP "CODE_LINE[1]" SITE "AA20" ; -LOCATE COMP "CODE_LINE[0]" SITE "Y21" ; -IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ; -IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ; -#terminated differential pair to pads -LOCATE COMP "SUPPL" SITE "C14" ; -#IOBUF PORT "SUPPL" IO_TYPE=LVDS25; -################################################################# -# LED -################################################################# -LOCATE COMP "LED_GREEN" SITE "F12" ; -LOCATE COMP "LED_ORANGE" SITE "G13" ; -LOCATE COMP "LED_RED" SITE "A15" ; -LOCATE COMP "LED_YELLOW" SITE "A16" ; -DEFINE PORT GROUP "LED_group" "LED*" ; -IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ; -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -BLOCK RD_DURING_WR_PATHS ; -################################################################# -#GSR_NET NET "GSR_N"; -################################################################# -# Locate Serdes and media interfaces -################################################################# -LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; -LOCATE COMP "THE_SYNC_LINK/THE_SERDES/PCSD_INST" SITE "PCSA" ; - -MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ; -MULTICYCLE TO CELL "THE_SYNC_LINK/SCI_DATA_OUT*" 20.000000 ns ; -MULTICYCLE TO CELL "THE_SYNC_LINK/sci*" 20.000000 ns ; -MULTICYCLE FROM CELL "THE_SYNC_LINK/sci*" 20.000000 ns ; -#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; - -BLOCK JTAGPATHS ; -## IOBUF ALLPORTS ; -USE PRIMARY NET "clk_200_osc" ; -USE PRIMARY NET "clk_100_osc" ; -FREQUENCY NET "clk_200_osc" 200.000000 MHz ; -FREQUENCY NET "clk_100_osc" 100.000000 MHz ; diff --git a/Cu_trb3_soda_client.xcf b/Cu_trb3_soda_client.xcf deleted file mode 100644 index ff49071..0000000 --- a/Cu_trb3_soda_client.xcf +++ /dev/null @@ -1,223 +0,0 @@ - - - - - - JTAG - - - 1 - Lattice - LatticeECP3 - LFE3-150EA - 0x01015043 - All - LFE3-150EA - - 8 - 11111111 - 1 - 0 - - /local/lemmens/lattice/soda/trb3_central_gbe_20130626.bit - 09/24/13 10:52:51 - Bypass - - - - - 2 - Lattice - LatticeECP3 - LFE3-150EA - 0x01015043 - All - LFE3-150EA - - 8 - 11111111 - 1 - 0 - - /local/lemmens/lattice/soda/CU_trb3_periph_soda_client_20141112.bit - 11/12/14 10:02:17 - Fast Program - - - - - 3 - Lattice - LatticeECP3 - LFE3-150EA - 0x01015043 - All - LFE3-150EA - - 8 - 11111111 - 1 - 0 - - /home/gsi/bitfiles/trb3_periph_sodasource_20130903.bit - 09/03/13 16:32:30 - N/A - Bypass - - - - - 4 - Lattice - LatticeECP3 - LFE3-150EA - 0x01015043 - All - LFE3-150EA - - 8 - 11111111 - 1 - 0 - - Bypass - - - - - 5 - Lattice - LatticeECP3 - LFE3-150EA - 0x01015043 - All - LFE3-150EA - - 8 - 11111111 - 1 - 0 - - /local/lemmens/lattice/soda/trb3_periph_sodasource_20140915.bit - 09/11/14 08:56:37 - Fast Program - - - - - 6 - Lattice - ispCLOCK - ispPAC-CLK5410D - 0x00190043 - 64-pin QFNS - ispPAC-CLK5410D-XXSN64C - - 8 - 11111111 - 1 - 0 - - /local/lemmens/lattice/trb3/base/clockmanager/CM1_125twice.jed - 04/10/13 09:35:41 - 0x1C57 - Erase,Program,Verify - - - - - 7 - Lattice - ispCLOCK - ispPAC-CLK5410D - 0x00190043 - 64-pin QFNS - ispPAC-CLK5410D-XXSN64C - - 8 - 11111111 - 1 - 0 - - Bypass - - - - - SEQUENTIAL - ENTIRED CHAIN - No Override - TLR - TLR - - - - USB - EzUSB-0 - - diff --git a/code/med_ecp3_sfp_4_sync_down.vhd b/code/med_ecp3_sfp_4_sync_down.vhd index c13f970..e72c1b5 100644 --- a/code/med_ecp3_sfp_4_sync_down.vhd +++ b/code/med_ecp3_sfp_4_sync_down.vhd @@ -65,8 +65,10 @@ entity med_ecp3_sfp_4_sync_down is SCI_ACK : out std_logic := '0'; SCI_NACK : out std_logic := '0'; -- Status and control port - STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0); - CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0'); +-- STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0); +-- CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0'); + STAT_OP : out std_logic_vector (63 downto 0); + CTRL_OP : in std_logic_vector (63 downto 0) := (others => '0'); STAT_DEBUG : out std_logic_vector (63 downto 0); CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') ); @@ -335,11 +337,11 @@ THE_SERDES : entity work.serdes_4_sync_downstream sci_rd => sci_read_i, sci_wrn => sci_write_i, - fpga_txrefclk => clk_200_txdata, --clk_200_osc, --clk_200_i(0), + fpga_txrefclk => clk_200_txdata, tx_serdes_rst_c => '0', --tx_serdes_rst(0), -- resets tx_pll PL 1906 tx_pll_lol_qd_s => tx_pll_lol_quad, tx_sync_qd_c => '0', -- unused; signal to synchronise channels/serdesses for multi-channel protocols - rst_qd_c => rst_down_quad, -- jemig wat is Oscar toch gasfjkl[glk + rst_qd_c => rst_down_quad, serdes_rst_qd_c => serdes_rst_down_quad ); @@ -363,7 +365,7 @@ generated_logic : for i in 0 to 3 generate THE_RX_FSM : rx_reset_fsm port map( RST_N => rst_n(i), - RX_REFCLK => rx_full_clk(i), --clk_200_osc, -- want de rx_refclk is clk_200_osc !!! en moet er altijd zijn + RX_REFCLK => rx_full_clk(i), TX_PLL_LOL_QD_S => tx_pll_lol(i), RX_SERDES_RST_CH_C => rx_serdes_rst(i), RX_CDR_LOL_CH_S => rx_cdr_lol(i), @@ -376,7 +378,7 @@ generated_logic : for i in 0 to 3 generate THE_TX_FSM : tx_reset_fsm port map( RST_N => rst_n(i), - TX_REFCLK => clk_200_txdata, --clk_200_osc, + TX_REFCLK => clk_200_txdata, TX_PLL_LOL_QD_S => tx_pll_lol(i), RST_QD_C => rst_qd(i), TX_PCS_RST_CH_C => tx_pcs_rst(i), @@ -456,7 +458,7 @@ generated_logic : for i in 0 to 3 generate SEND_DLM => TX_DLM(i), SEND_DLM_WORD => TX_DLM_WORD(i), - SEND_LINK_RESET_IN => CTRL_OP(i)(15), + SEND_LINK_RESET_IN => CTRL_OP(i*16 + 15), --CTRL_OP(i)(15), TX_ALLOW_IN => tx_allow(i), RX_ALLOW_IN => rx_allow(i), LINK_PHASE_OUT => link_phase_S(i), --PL! @@ -503,7 +505,8 @@ generated_logic : for i in 0 to 3 generate ); internal_make_link_reset_out(i) <= make_link_reset_i(i) when (IS_SYNC_SLAVE=c_YES) else '0'; - sd_los_i(i) <= SD_LOS_IN(i) when rising_edge(SYSCLK); -- PL! +-- sd_los_i(i) <= SD_LOS_IN(i) when rising_edge(SYSCLK); --PL! 200115 + sd_los_i(i) <= SD_LOS_IN(i) when rising_edge(clk_200_txdata); end generate; @@ -514,7 +517,7 @@ end generate; PROC_SCI_CTRL: process variable cnt : integer range 0 to 4 := 0; begin -wait until rising_edge(SYSCLK); +wait until rising_edge(SYSCLK); SCI_ACK <= '0'; case sci_state is when IDLE => @@ -643,19 +646,33 @@ end process; -- internal_make_link_reset_out(i) <= make_link_reset_i(i) when (IS_SYNC_SLAVE=c_YES) else '0'; -- sd_los_i(i) <= SD_LOS_IN(i) when rising_edge(SYSCLK); -- PL! - STAT_OP(i)(15) <= send_link_reset_i(i) when rising_edge(SYSCLK); - STAT_OP(i)(14) <= '0'; - STAT_OP(i)(13) <= internal_make_link_reset_out(i) when rising_edge(SYSCLK); --make trbnet reset - STAT_OP(i)(12) <= '0'; - STAT_OP(i)(11) <= '0'; - STAT_OP(i)(10) <= rx_allow(i); - STAT_OP(i)(9) <= tx_allow(i); - STAT_OP(i)(8) <= got_link_ready_i(i); - STAT_OP(i)(7) <= send_link_reset_i(i); - STAT_OP(i)(6) <= make_link_reset_i(i); - STAT_OP(i)(5) <= request_retr_i(i); - STAT_OP(i)(4) <= start_retr_i(i); - STAT_OP(i)(3 downto 0) <= x"0" when rx_allow_q(i) = '1' and tx_allow_q(i) = '1' else x"7"; + STAT_OP(i*16 + 15) <= send_link_reset_i(i) when rising_edge(SYSCLK); + STAT_OP(i*16 + 14) <= '0'; + STAT_OP(i*16 + 13) <= internal_make_link_reset_out(i) when rising_edge(SYSCLK); --make trbnet reset + STAT_OP(i*16 + 12) <= '0'; + STAT_OP(i*16 + 11) <= '0'; + STAT_OP(i*16 + 10) <= rx_allow(i); + STAT_OP(i*16 + 9) <= tx_allow(i); + STAT_OP(i*16 + 8) <= got_link_ready_i(i); + STAT_OP(i*16 + 7) <= send_link_reset_i(i); + STAT_OP(i*16 + 6) <= make_link_reset_i(i); + STAT_OP(i*16 + 5) <= request_retr_i(i); + STAT_OP(i*16 + 4) <= start_retr_i(i); + STAT_OP(i*16 + 3 downto i*16) <= x"0" when rx_allow_q(i) = '1' and tx_allow_q(i) = '1' else x"7"; + -- STAT_OP(i)(15) <= send_link_reset_i(i) when rising_edge(SYSCLK); +-- STAT_OP(i)(14) <= '0'; +-- STAT_OP(i)(13) <= internal_make_link_reset_out(i) when rising_edge(SYSCLK); --make trbnet reset +-- STAT_OP(i)(12) <= '0'; +-- STAT_OP(i)(11) <= '0'; +-- STAT_OP(i)(10) <= rx_allow(i); +-- STAT_OP(i)(9) <= tx_allow(i); +-- STAT_OP(i)(8) <= got_link_ready_i(i); +-- STAT_OP(i)(7) <= send_link_reset_i(i); +-- STAT_OP(i)(6) <= make_link_reset_i(i); +-- STAT_OP(i)(5) <= request_retr_i(i); +-- STAT_OP(i)(4) <= start_retr_i(i); +-- STAT_OP(i)(3 downto 0) <= x"0" when rx_allow_q(i) = '1' and tx_allow_q(i) = '1' else x"7"; + end generate; end med_ecp3_sfp_4_sync_down_arch; diff --git a/code/med_ecp3_sfp_sync_up.vhd b/code/med_ecp3_sfp_sync_up.vhd index 462d6e5..42f0654 100644 --- a/code/med_ecp3_sfp_sync_up.vhd +++ b/code/med_ecp3_sfp_sync_up.vhd @@ -355,10 +355,10 @@ THE_TX : soda_tx_control CLK_100 => rx_half_clk, --SYSCLK, RESET_IN => rst, --CLEAR, PL! - TX_DATA_IN => (others => '0'), --MED_DATA_IN, - TX_PACKET_NUMBER_IN => (others => '0'), --MED_PACKET_NUM_IN, - TX_WRITE_IN => '0', --MED_DATAREADY_IN, - TX_READ_OUT => open, --MED_READ_OUT, + TX_DATA_IN => MED_DATA_IN, + TX_PACKET_NUMBER_IN => MED_PACKET_NUM_IN, + TX_WRITE_IN => MED_DATAREADY_IN, + TX_READ_OUT => MED_READ_OUT, TX_DATA_OUT => tx_data, TX_K_OUT => tx_k, @@ -388,14 +388,14 @@ LINK_PHASE_OUT <= link_phase_S; --PL! ------------------------------------------------- THE_RX_CONTROL : rx_control port map( - CLK_200 => rx_full_clk, --clk_200_i, PL! - CLK_100 => rx_half_clk, --SYSCLK, - RESET_IN => rst, --CLEAR, PL! + CLK_200 => rx_full_clk, + CLK_100 => rx_half_clk, + RESET_IN => rst, - RX_DATA_OUT => open, --MED_DATA_OUT, - RX_PACKET_NUMBER_OUT => open, --MED_PACKET_NUM_OUT, - RX_WRITE_OUT => open, --MED_DATAREADY_OUT, - RX_READ_IN => '0', --MED_READ_IN, + RX_DATA_OUT => MED_DATA_OUT, + RX_PACKET_NUMBER_OUT => MED_PACKET_NUM_OUT, + RX_WRITE_OUT => MED_DATAREADY_OUT, + RX_READ_IN => MED_READ_IN, RX_DATA_IN => rx_data, RX_K_IN => rx_k, @@ -536,7 +536,8 @@ debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0); STAT_DEBUG <= debug_reg; internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = c_YES else '0'; -sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK); -- PL! +--sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK); -- PL! +sd_los_i <= SD_LOS_IN when rising_edge(rx_full_clk); -- PL! 200115 STAT_OP(15) <= send_link_reset_i when rising_edge(SYSCLK); STAT_OP(14) <= '0'; diff --git a/code/soda_components.vhd b/code/soda_components.vhd index 4ce848f..a926589 100644 --- a/code/soda_components.vhd +++ b/code/soda_components.vhd @@ -463,8 +463,8 @@ package soda_components is SCI_ACK : out std_logic := '0'; SCI_NACK : out std_logic := '0'; -- Status and control port - STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0); - CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0'); + STAT_OP : out std_logic_vector (63 downto 0); + CTRL_OP : in std_logic_vector (63 downto 0) := (others => '0'); STAT_DEBUG : out std_logic_vector (63 downto 0); CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') ); diff --git a/code/soda_hub.vhd b/code/soda_hub.vhd index aacf361..00f8069 100644 --- a/code/soda_hub.vhd +++ b/code/soda_hub.vhd @@ -177,7 +177,7 @@ begin SODACLK => SODACLK, RESET => RESET, --Internal Connection - LINK_PHASE_IN => UPLINK_PHASE_IN, --link_phase_S, PL! 17092014 vergeten ??? of niet nodig ? + LINK_PHASE_IN => UPLINK_PHASE_IN, --link_phase_S, PL! 17092014 vergeten ??? of niet nodig ? SODA_CMD_STROBE_IN => TXsoda_cmd_valid_S(i), START_OF_SUPERBURST => TXstart_of_superburst_S(i), SUPER_BURST_NR_IN => TXsuper_burst_nr_S(i)(30 downto 0), diff --git a/code/trb3_periph_sodahub.vhd b/code/trb3_periph_sodahub.vhd index 82572c8..598cd45 100644 --- a/code/trb3_periph_sodahub.vhd +++ b/code/trb3_periph_sodahub.vhd @@ -534,7 +534,7 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up port map( OSC_CLK => clk_200_osc, TX_DATACLK => rxup_full_clk, - SYSCLK => clk_100_osc, -- rx_half_clk is selectively used inside med_ecp3_sfp_4_sync_down.vhd + SYSCLK => rxup_half_clk, --clk_100_osc, RESET => downlink_reset, CLEAR => downlink_clear, --------------------------------------------------------------------------------------------------------------------------------------------------------- @@ -675,15 +675,23 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up SCI_NACK => sci2_nack, --Status and control port - STAT_OP(0) => med_stat_op(1*16+15 downto 1*16), - STAT_OP(1) => med_stat_op(6*16+15 downto 6*16), - STAT_OP(2) => med_stat_op(2*16+15 downto 2*16), - STAT_OP(3) => med_stat_op(4*16+15 downto 4*16), - - CTRL_OP(0) => med_ctrl_op(1*16+15 downto 1*16), - CTRL_OP(1) => med_ctrl_op(6*16+15 downto 6*16), - CTRL_OP(2) => med_ctrl_op(2*16+15 downto 2*16), - CTRL_OP(3) => med_ctrl_op(4*16+15 downto 4*16), +-- STAT_OP(0) => med_stat_op(1*16+15 downto 1*16), +-- STAT_OP(1) => med_stat_op(6*16+15 downto 6*16), +-- STAT_OP(2) => med_stat_op(2*16+15 downto 2*16), +-- STAT_OP(3) => med_stat_op(4*16+15 downto 4*16), + STAT_OP(15 downto 0) => med_stat_op(1*16+15 downto 1*16), + STAT_OP(31 downto 16) => med_stat_op(6*16+15 downto 6*16), + STAT_OP(47 downto 32) => med_stat_op(2*16+15 downto 2*16), + STAT_OP(63 downto 48) => med_stat_op(4*16+15 downto 4*16), + +-- CTRL_OP(0) => med_ctrl_op(1*16+15 downto 1*16), +-- CTRL_OP(1) => med_ctrl_op(6*16+15 downto 6*16), +-- CTRL_OP(2) => med_ctrl_op(2*16+15 downto 2*16), +-- CTRL_OP(3) => med_ctrl_op(4*16+15 downto 4*16), + CTRL_OP(15 downto 0) => med_ctrl_op(1*16+15 downto 1*16), + CTRL_OP(31 downto 16) => med_ctrl_op(6*16+15 downto 6*16), + CTRL_OP(47 downto 32) => med_ctrl_op(2*16+15 downto 2*16), + CTRL_OP(63 downto 48) => med_ctrl_op(4*16+15 downto 4*16), STAT_DEBUG => open, CTRL_DEBUG => (others => '0') diff --git a/soda_hub.ldf b/soda_hub.ldf index cf522c4..b032d1a 100644 --- a/soda_hub.ldf +++ b/soda_hub.ldf @@ -4,7 +4,7 @@