From 3e7b52afc35f70f8c13684f3002b1cb8deb47dc7 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Mon, 28 Mar 2022 13:40:03 +0200 Subject: [PATCH] TDC implemented in FE, SCI reader allows quick switch --- backplanemaster/trb3sc_master.vhd | 4 +- tdctemplate/config_16_sfp_kel.vhd | 4 +- tdctemplate/config_compile_gsi.pl | 2 +- tdctemplate/trb3sc_tdctemplate.vhd | 148 +++++++++++++---------------- 4 files changed, 69 insertions(+), 89 deletions(-) diff --git a/backplanemaster/trb3sc_master.vhd b/backplanemaster/trb3sc_master.vhd index d8c8b1d..6812a00 100644 --- a/backplanemaster/trb3sc_master.vhd +++ b/backplanemaster/trb3sc_master.vhd @@ -262,8 +262,8 @@ THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_all_RS TX_DLM_WORD_IN => send_dlm_word_i, RX_RST_OUT => send_rst_i, RX_RST_WORD_OUT => send_rst_word_i, - TX_RST_IN => '0', - TX_RST_WORD_IN => x"00", + TX_RST_IN => send_rst_i, --'0', + TX_RST_WORD_IN => send_rst_word_i, --x"00", -- sync operation WORD_SYNC_IN => word_sync_i, WORD_SYNC_OUT => word_sync_i, diff --git a/tdctemplate/config_16_sfp_kel.vhd b/tdctemplate/config_16_sfp_kel.vhd index 0b80273..f5c7902 100644 --- a/tdctemplate/config_16_sfp_kel.vhd +++ b/tdctemplate/config_16_sfp_kel.vhd @@ -27,8 +27,8 @@ package config is --TDC settings constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement - constant NUM_TDC_CHANNELS : integer range 1 to 65 := 17; -- number of tdc channels per module - constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 4; --the nearest power of two, for convenience reasons + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 5; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 2; --the nearest power of two, for convenience reasons constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 -- 0: single edge only, -- 1: same channel, diff --git a/tdctemplate/config_compile_gsi.pl b/tdctemplate/config_compile_gsi.pl index 80de18f..7ef1463 100644 --- a/tdctemplate/config_compile_gsi.pl +++ b/tdctemplate/config_compile_gsi.pl @@ -9,7 +9,7 @@ nodelist_file => 'nodelist.txt', pinout_file => 'trb3sc_padiwa', par_options => '../par.p2t', -include_TDC => 0, +include_TDC => 1, include_GBE => 0, firefox_open => 0, diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd index f823109..d946f74 100644 --- a/tdctemplate/trb3sc_tdctemplate.vhd +++ b/tdctemplate/trb3sc_tdctemplate.vhd @@ -221,70 +221,58 @@ end generate; --------------------------------------------------------------------------- THE_MEDIA_INTERFACE : entity med_ecp3_sfp_sync_all_RS generic map( - IS_MODE => (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_SLAVE) + IS_MODE => (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_SLAVE) ) port map( -- Clocks and reset - CLK_REF_FULL => link_clock, - SYSCLK => clk_sys, - CLEAR => init_quad, - RESET => reset_i, + CLK_REF_FULL => link_clock, + SYSCLK => clk_sys, + CLEAR => init_quad, + RESET => reset_i, -- Media Interface TX/RX - MEDIA_MED2INT(0) => open, - MEDIA_MED2INT(1) => open, - MEDIA_MED2INT(2) => open, - MEDIA_MED2INT(3) => med2int(0), - MEDIA_INT2MED(0) => open, - MEDIA_INT2MED(1) => open, - MEDIA_INT2MED(2) => open, - MEDIA_INT2MED(3) => int2med(0), + MEDIA_MED2INT(0 to 2) => open, + MEDIA_MED2INT(3) => med2int(0), + MEDIA_INT2MED(0 to 2) => open, + MEDIA_INT2MED(3) => int2med(0), -- Sync operation - RX_DLM_OUT(0) => open, - RX_DLM_OUT(1) => open, - RX_DLM_OUT(2) => open, - RX_DLM_OUT(3) => rx_dlm_i, + RX_DLM_OUT(2 downto 2) => open, + RX_DLM_OUT(3) => rx_dlm_i, RX_DLM_WORD_OUT(23 downto 0) => open, RX_DLM_WORD_OUT(31 downto 24) => send_dlm_word_i, - TX_DLM_IN => rx_dlm_i, - TX_DLM_WORD_IN => send_dlm_word_i, - RX_RST_OUT => send_rst_i, - RX_RST_WORD_OUT => send_rst_word_i, - TX_RST_IN => '0', - TX_RST_WORD_IN => x"00", + TX_DLM_IN => rx_dlm_i, + TX_DLM_WORD_IN => send_dlm_word_i, + RX_RST_OUT => send_rst_i, + RX_RST_WORD_OUT => send_rst_word_i, + TX_RST_IN => send_rst_i, --'0', + TX_RST_WORD_IN => send_rst_word_i, --x"00", -- sync operation - WORD_SYNC_IN => word_sync_i, - WORD_SYNC_OUT => word_sync_i, - MASTER_CLK_IN => master_clk_i, - MASTER_CLK_OUT => master_clk_i, - LINK_TX_NULL_IN => global_reset_i, - LINK_RX_NULL_OUT => global_reset_i, - TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i, - TX_CLK_AVAIL_OUT => tx_clk_avail_i, - TX_PCS_RST_IN => tx_pcs_rst_i, - SYNC_TX_PLL_IN => sync_tx_quad_i, - LINK_TX_READY_IN => link_tx_ready_i, - DESTROY_LINK_IN => (others => '0'), - WAP_REQUESTED_IN => x"0", + WORD_SYNC_IN => word_sync_i, + WORD_SYNC_OUT => word_sync_i, + MASTER_CLK_IN => master_clk_i, + MASTER_CLK_OUT => master_clk_i, + LINK_TX_NULL_IN => global_reset_i, + LINK_RX_NULL_OUT => global_reset_i, + TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i, + TX_CLK_AVAIL_OUT => tx_clk_avail_i, + TX_PCS_RST_IN => tx_pcs_rst_i, + SYNC_TX_PLL_IN => sync_tx_quad_i, + LINK_TX_READY_IN => link_tx_ready_i, + DESTROY_LINK_IN => (others => '0'), + WAP_REQUESTED_IN => x"0", --SFP Connection - SD_PRSNT_N_IN(0) => '1', - SD_LOS_IN(0) => '1', - SD_TXDIS_OUT(0) => open, - SD_PRSNT_N_IN(1) => '1', - SD_LOS_IN(1) => '1', - SD_TXDIS_OUT(1) => open, - SD_PRSNT_N_IN(2) => '1', - SD_LOS_IN(2) => '1', - SD_TXDIS_OUT(2) => open, - SD_PRSNT_N_IN(3) => SFP_MOD0(1), - SD_LOS_IN(3) => SFP_LOS(1), - SD_TXDIS_OUT(3) => SFP_TX_DIS(1), + SD_PRSNT_N_IN(2 downto 0) => (others => '1'), + SD_LOS_IN(2 downto 0) => (others => '1'), + SD_TXDIS_OUT(2 downto 0) => open, + SD_PRSNT_N_IN(3) => SFP_MOD0(1), + SD_LOS_IN(3) => SFP_LOS(1), + SD_TXDIS_OUT(3) => SFP_TX_DIS(1), --Control Interface - BUS_RX => bussci_rx, - BUS_TX => bussci_tx, + BUS_RX => bussci_rx, + BUS_TX => bussci_tx, -- Status and control port - STAT_DEBUG => open, - CTRL_DEBUG => open, - DEBUG_OUT => debug_i + STAT_DEBUG => open, + CTRL_DEBUG => open, + DEBUG_OUT => debug_i ); THE_MAIN_TX_RST: main_tx_reset_RS @@ -551,13 +539,6 @@ end generate; LED_SFP_GREEN <= not med2int(0).stat_op(9) & '1'; --SFP Link Status LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) & '1'; --SFP RX/TX - --- THE_TOGGLE_PROC: process( clk_sys ) --- begin --- if( rising_edge(clk_sys) ) then --- toggler <= not toggler; --- end if; --- end process THE_TOGGLE_PROC; --------------------------------------------------------------------------- -- Test Circuits @@ -574,29 +555,29 @@ end generate; ------------------------------------------------------------------------------- -- TDC ------------------------------------------------------------------------------- --- THE_TDC : TDC_record --- generic map ( --- CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module --- STATUS_REG_NR => 21, -- Number of status regs --- DEBUG => c_YES, --- SIMULATION => c_NO) --- port map ( --- RESET => reset_i, --- CLK_TDC => clk_full_osc, --- CLK_READOUT => clk_sys, -- Clock for the readout --- REFERENCE_TIME => TRIG_LEFT, -- Reference time input --- HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals --- HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC --- -- Trigger signals from handler --- BUSRDO_RX => readout_rx, --- BUSRDO_TX => readout_tx(0), --- -- Slow control bus --- BUS_RX => bustdc_rx, --- BUS_TX => bustdc_tx, --- -- Dubug signals --- INFO_IN => timer, --- LOGIC_ANALYSER_OUT => logic_analyser_i --- ); + THE_TDC : TDC_record + generic map ( + CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module + STATUS_REG_NR => 21, -- Number of status regs + DEBUG => c_YES, + SIMULATION => c_NO) + port map ( + RESET => reset_i, + CLK_TDC => clk_full_osc, + CLK_READOUT => clk_sys, -- Clock for the readout + REFERENCE_TIME => TRIG_LEFT, -- Reference time input + HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals + HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC + -- Trigger signals from handler + BUSRDO_RX => readout_rx, + BUSRDO_TX => readout_tx(0), + -- Slow control bus + BUS_RX => bustdc_rx, + BUS_TX => bustdc_tx, + -- Dubug signals + INFO_IN => timer, + LOGIC_ANALYSER_OUT => logic_analyser_i + ); gen_normal_pins : if PINOUT = 1 or PINOUT = 2 or PINOUT = 3 generate @@ -614,7 +595,6 @@ gen_normal_pins : if PINOUT = 1 or PINOUT = 2 or PINOUT = 3 generate end generate Gen_Hit_In_Signals; end generate; - gen_montrg_inputs_normal : if TRIG_GEN_FAST_CHANNELS = c_NO generate monitor_inputs_i <= trig_gen_out_i & inputs(MONITOR_INPUT_NUM-TRIG_GEN_OUTPUT_NUM -1 downto 0); trigger_inputs_i <= inputs(TRIG_GEN_INPUT_NUM-1 downto 0); -- 2.43.0