From 3f88d1464bcceb962690db000515775bca76f237 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Mon, 2 Feb 2009 17:14:01 +0000 Subject: [PATCH] *** empty log message *** --- etrax_interface.vhd | 91 +++++++++++++++------------- special/trb_net_bridge_etrax_apl.vhd | 15 ++--- 2 files changed, 58 insertions(+), 48 deletions(-) diff --git a/etrax_interface.vhd b/etrax_interface.vhd index 3ace9bc..e54f9e0 100644 --- a/etrax_interface.vhd +++ b/etrax_interface.vhd @@ -37,23 +37,23 @@ architecture etrax_interface of etrax_interface is component signal_sync is generic( - WIDTH : integer := 2; -- + WIDTH : integer := 2; DEPTH : integer := 1 ); port( - RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register - CLK0 : in std_logic; --clock for first FF - CLK1 : in std_logic; --Clock for other FF - D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input - D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output + RESET : in std_logic; + CLK0 : in std_logic; + CLK1 : in std_logic; + D_IN : in std_logic_vector(WIDTH-1 downto 0); + D_OUT : out std_logic_vector(WIDTH-1 downto 0) ); end component; - type ETRAX_RW_STATE_MACHINE is (IDLE, SAVE_ADDRESS_1, SAVE_ADDRESS_2, SAVE_DATA_1 ,SAVE_DATA_2 , SEND_DATA_1, SEND_ZERO, SEND_DATA_2, WAIT_FOR_DATA, SAVING_EXTERNAL_DATA, SEND_VALID, SEND_EXTERNAL_TRIGGER ); + type ETRAX_RW_STATE_MACHINE is (IDLE, SAVE_DATA_1 ,SAVE_DATA_2 , SEND_DATA_1, SEND_ZERO, SEND_DATA_2, WAIT_FOR_DATA, SAVING_EXTERNAL_DATA, SEND_VALID, SEND_EXTERNAL_TRIGGER ); --SAVE_ADDRESS_1, SAVE_ADDRESS_2, signal ETRAX_RW_STATE_currentstate,ETRAX_RW_STATE_nextstate : ETRAX_RW_STATE_MACHINE; signal etrax_trigger_pulse : std_logic; - signal saved_rw_mode : std_logic_vector(15 downto 0); +-- signal saved_rw_mode : std_logic_vector(15 downto 0); signal saved_address : std_logic_vector (15 downto 0); signal saved_data : std_logic_vector(31 downto 0); signal saved_data_fpga : std_logic_vector(31 downto 0); @@ -116,9 +116,10 @@ begin ETRAX_BUS_BUSY <= '0' when ETRAX_RW_STATE_currentstate = IDLE else '1'; ETRAX_IS_READY_TO_READ <= etrax_is_ready_to_read_i; - read_cycle <= saved_rw_mode(15); - write_cycle <= not saved_rw_mode(15); - +-- read_cycle <= saved_rw_mode(15); +-- write_cycle <= not saved_rw_mode(15); + read_cycle <= saved_address(15); + write_cycle <= not saved_address(15); ETRAX_FPGA_COMUNICATION_CLOCK : process (CLK) begin @@ -129,11 +130,10 @@ begin ETRAX_RW_STATE_currentstate <= ETRAX_RW_STATE_nextstate; end if; end if; - end process ETRAX_FPGA_COMUNICATION_CLOCK; + end process; - ETRAX_FPGA_COMUNICATION: process (ETRAX_RW_STATE_currentstate,etrax_trigger_pulse, - saved_rw_mode(15), read_cycle, write_cycle, - INTERNAL_DATAREADY_IN, saved_address) + ETRAX_FPGA_COMUNICATION: process (ETRAX_RW_STATE_currentstate,etrax_trigger_pulse, --saved_rw_mode(15) + read_cycle, write_cycle, INTERNAL_DATAREADY_IN, saved_address) begin communication_state <= x"1"; ETRAX_RW_STATE_nextstate <= ETRAX_RW_STATE_currentstate; @@ -141,27 +141,32 @@ begin when IDLE => communication_state <= x"1"; if etrax_trigger_pulse = '1' then - ETRAX_RW_STATE_nextstate <= SAVE_ADDRESS_1; - end if; - - when SAVE_ADDRESS_1 => - communication_state <= x"2"; - if etrax_trigger_pulse = '1' then - ETRAX_RW_STATE_nextstate <= SAVE_ADDRESS_2; - end if; - - when SAVE_ADDRESS_2 => - communication_state <= x"3"; - if etrax_trigger_pulse = '1' then - if read_cycle = '1' then - ETRAX_RW_STATE_nextstate <= SEND_EXTERNAL_TRIGGER; - else +-- ETRAX_RW_STATE_nextstate <= SAVE_ADDRESS_1; +-- end if; +-- +-- when SAVE_ADDRESS_1 => +-- communication_state <= x"2"; +-- if etrax_trigger_pulse = '1' then +-- ETRAX_RW_STATE_nextstate <= SAVE_ADDRESS_2; +-- end if; +-- +-- when SAVE_ADDRESS_2 => +-- communication_state <= x"3"; +-- if etrax_trigger_pulse = '1' then +-- if read_cycle = '1' then +-- ETRAX_RW_STATE_nextstate <= SEND_EXTERNAL_TRIGGER; +-- else ETRAX_RW_STATE_nextstate <= SAVE_DATA_1; end if; - end if; +-- end if; when SAVE_DATA_1 => communication_state <= x"4"; +--new start + if read_cycle = '1' then + ETRAX_RW_STATE_nextstate <= SEND_EXTERNAL_TRIGGER; + end if; +--new end if etrax_trigger_pulse = '1' then ETRAX_RW_STATE_nextstate <= SAVE_DATA_2; end if; @@ -179,7 +184,7 @@ begin communication_state <= x"6"; if write_cycle = '1' then ETRAX_RW_STATE_nextstate <= SEND_VALID; - elsif INTERNAL_DATAREADY_IN = '1' or saved_address(15 downto 8) = 0 then + elsif INTERNAL_DATAREADY_IN = '1' or saved_address(14 downto 8) = 0 then --(15 downto 8) ETRAX_RW_STATE_nextstate <= SAVING_EXTERNAL_DATA; end if; @@ -216,13 +221,17 @@ begin begin if rising_edge(CLK) then if internal_reset_i = '1' then - saved_rw_mode <= (others => '0'); +-- saved_rw_mode <= (others => '0'); saved_address <= (others => '0'); saved_data <= (others => '0'); +-- elsif ETRAX_RW_STATE_currentstate = IDLE and etrax_trigger_pulse = '1' then +-- saved_rw_mode <= ETRAX_DATA_BUS_C(15 downto 0); +-- elsif ETRAX_RW_STATE_currentstate = SAVE_ADDRESS_2 and etrax_trigger_pulse = '1' then +-- saved_address(15 downto 0) <= ETRAX_DATA_BUS_C(15 downto 0); +--new start elsif ETRAX_RW_STATE_currentstate = IDLE and etrax_trigger_pulse = '1' then - saved_rw_mode <= ETRAX_DATA_BUS_C(15 downto 0); - elsif ETRAX_RW_STATE_currentstate = SAVE_ADDRESS_2 and etrax_trigger_pulse = '1' then saved_address(15 downto 0) <= ETRAX_DATA_BUS_C(15 downto 0); +--new end elsif ETRAX_RW_STATE_currentstate = SAVE_DATA_1 and etrax_trigger_pulse = '1' then saved_data(31 downto 16) <= ETRAX_DATA_BUS_C(15 downto 0); elsif ETRAX_RW_STATE_currentstate = SAVE_DATA_2 and etrax_trigger_pulse = '1' then @@ -232,11 +241,11 @@ begin end process REGISTER_ETRAX_BUS; - INTERNAL_ADDRESS_OUT <= saved_address; + INTERNAL_ADDRESS_OUT <= '0' & saved_address(14 downto 0); INTERNAL_DATA_OUT <= saved_data; - INTERNAL_WRITE_OUT <= '1' when write_cycle = '1' and saved_address(15 downto 8) /= 0 and ETRAX_RW_STATE_currentstate = SEND_EXTERNAL_TRIGGER else '0'; - INTERNAL_READ_OUT <= '1' when read_cycle = '1' and saved_address(15 downto 8) /= 0 and ETRAX_RW_STATE_currentstate = SEND_EXTERNAL_TRIGGER else '0'; + INTERNAL_WRITE_OUT <= '1' when write_cycle = '1' and saved_address(14 downto 8) /= 0 and ETRAX_RW_STATE_currentstate = SEND_EXTERNAL_TRIGGER else '0'; --(15 downto 8) + INTERNAL_READ_OUT <= '1' when read_cycle = '1' and saved_address(14 downto 8) /= 0 and ETRAX_RW_STATE_currentstate = SEND_EXTERNAL_TRIGGER else '0'; --(15 downto 8) FPGA_REGISTER_OUT <= buf_FPGA_REGISTER_OUT; @@ -269,8 +278,8 @@ begin ctrl_num := conv_integer(saved_address(3 downto 0)); -- case saved_rw_mode(14 downto 0) is -- when "000000000000000" => - if saved_rw_mode(15) = '1' then - if saved_address(15 downto 8) = 0 then + if read_cycle = '1' then + if saved_address(14 downto 8) = 0 then if saved_address(7 downto 4) = 0 then --status regs saved_data_fpga <= FPGA_REGISTER_IN((stat_num)*32+31 downto stat_num*32); elsif saved_address(4) = '1' then @@ -281,7 +290,7 @@ begin elsif INTERNAL_DATAREADY_IN = '1' then saved_data_fpga <= INTERNAL_DATA_IN; end if; - elsif saved_rw_mode(15) = '0' and ETRAX_RW_STATE_currentstate = WAIT_FOR_DATA then + elsif write_cycle = '1' and ETRAX_RW_STATE_currentstate = WAIT_FOR_DATA then buf_FPGA_REGISTER_OUT((ctrl_num+1)*32-1 downto (ctrl_num)*32) <= saved_data; end if; -- when others => diff --git a/special/trb_net_bridge_etrax_apl.vhd b/special/trb_net_bridge_etrax_apl.vhd index 3bae89a..b607d6e 100644 --- a/special/trb_net_bridge_etrax_apl.vhd +++ b/special/trb_net_bridge_etrax_apl.vhd @@ -39,7 +39,7 @@ entity trb_net_bridge_etrax_apl is ); end entity; ---address range is 000 to FFF +--address range is 100 to FFF -- (c is channel number * 2 + 1 if active part) --sending data. sending is released when 1c0 is written @@ -75,8 +75,9 @@ architecture trb_net_bridge_etrax_apl_arch of trb_net_bridge_etrax_apl is signal fifo_pci_to_net_full : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); signal fifo_pci_to_net_empty : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0); signal next_APL_SEND_OUT : std_logic_vector(2**c_MUX_WIDTH-1 downto 0); - signal fifo_pci_to_net_data_count : std_logic_vector(10*2**c_MUX_WIDTH-1 downto 0); - signal fifo_net_to_pci_data_count : std_logic_vector(10*2**c_MUX_WIDTH-1 downto 0); + type data_count_t is array(0 to 2**c_MUX_WIDTH-1) of std_logic_vector(9 downto 0); + signal fifo_pci_to_net_data_count : data_count_t; + signal fifo_net_to_pci_data_count : data_count_t; signal sender_control : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0); signal sender_target : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0); signal sender_error : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0); @@ -165,12 +166,12 @@ begin next_CPU_DATA_OUT <= sender_error(channel_address*32+31 downto channel_address*32); when x"14" => next_CPU_DATA_OUT <= x"000" & "00" & fifo_pci_to_net_empty(channel_address) & fifo_pci_to_net_full(channel_address) - & "000000" & fifo_pci_to_net_data_count(channel_address*10+9 downto channel_address*10); + & "000000" & fifo_pci_to_net_data_count(channel_address)(9 downto 0); when x"1F" => next_CPU_DATA_OUT <= sender_status(channel_address*32+31 downto channel_address*32); when x"24" => next_CPU_DATA_OUT <= x"000" & "00" & fifo_net_to_pci_empty(channel_address) & fifo_net_to_pci_full(channel_address) - & "000000" & fifo_net_to_pci_data_count(channel_address*10+9 downto channel_address*10); + & "000000" & fifo_net_to_pci_data_count(channel_address)(9 downto 0); when x"30" => next_CPU_DATA_OUT <= api_status(channel_address*32+31 downto channel_address*32); when others => @@ -273,7 +274,7 @@ begin PACKET_NUM_IN => fifo_net_to_pci_din(18*i+17 downto 18*i+16), DATA_OUT => fifo_net_to_pci_dout(32*i+15 downto 32*i), PACKET_NUM_OUT => fifo_net_to_pci_dout(32*i+17 downto 32*i+16), - DATA_COUNT_OUT => fifo_net_to_pci_data_count(10*i+9 downto 10*i), + DATA_COUNT_OUT => fifo_net_to_pci_data_count(i)(9 downto 0), full_out => fifo_net_to_pci_full(i), empty_out => fifo_net_to_pci_empty(i) ); @@ -294,7 +295,7 @@ begin PACKET_NUM_IN => reg_CPU_DATA_IN(17 downto 16), DATA_OUT => fifo_pci_to_net_dout(18*i+15 downto 18*i), PACKET_NUM_OUT => fifo_pci_to_net_dout(18*i+17 downto 18*i+16), - DATA_COUNT_OUT => fifo_pci_to_net_data_count(10*i+9 downto 10*i), + DATA_COUNT_OUT => fifo_pci_to_net_data_count(i)(9 downto 0), full_out => fifo_pci_to_net_full(i), empty_out => fifo_pci_to_net_empty(i) ); -- 2.43.0