From 3f91984ed6f3e5198eb8a6749653b51f7952ca60 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Wed, 26 Jan 2022 17:14:29 +0100 Subject: [PATCH] unknown --- cts/trb3sc_cts.vhd | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd index 745ecad..5e9612d 100644 --- a/cts/trb3sc_cts.vhd +++ b/cts/trb3sc_cts.vhd @@ -258,6 +258,8 @@ architecture trb3sc_arch of trb3sc_cts is signal rx_index_i : std_logic_vector(3 downto 0); signal phaser_data : std_logic_vector(31 downto 0); signal phaser_update : std_logic; + signal coarse_counter : unsigned(15 downto 0); + signal coarse_delay : std_logic_vector(15 downto 0); -- attribute syn_keep : boolean; -- attribute syn_preserve : boolean; @@ -436,10 +438,26 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate RESET => reset_i, SIGNAL_A_IN => word_sync_i, SIGNAL_B_IN => rx_index_i(3), - LOW_CNT_OUT => phaser_data(15 downto 0), + LOW_CNT_OUT => open, HI_CNT_OUT => phaser_data(31 downto 16), UPDATE_OUT => phaser_update ); + + THE_COARSE_COUNTER_PROC: process( clk_full_osc ) + begin + if( rising_edge(clk_full_osc) ) then + if( tx_dlm_i = '1' ) then + coarse_counter <= (others => '0'); + else + coarse_counter <= coarse_counter + 1; + end if; + if( rx_dlm_i = '1' ) then + coarse_delay <= std_logic_vector(coarse_counter); + end if; + end if; + end process THE_COARSE_COUNTER_PROC; + + phaser_data(15 downto 0) <= coarse_delay; -------------------------------------------------------------------- -------------------------------------------------------------------- -- 2.43.0