From 3fc27f6626a14454904d971f56951cca175c1702 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Thu, 24 Mar 2022 13:07:30 +0100 Subject: [PATCH] added CLEAR for initial reset --- .../med_ecp3_sfp_sync_all_125M_RS.vhd | 20 +- media_interfaces/sync/med_sync_control_RS.vhd | 24 +- media_interfaces/sync/med_sync_define_RS.vhd | 36 +- media_interfaces/sync/sci_reader_RS.vhd | 6 +- media_interfaces/sync/tx_control_RS.vhd | 370 +++++++++--------- 5 files changed, 221 insertions(+), 235 deletions(-) diff --git a/media_interfaces/med_ecp3_sfp_sync_all_125M_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_125M_RS.vhd index a6bae19..7870338 100644 --- a/media_interfaces/med_ecp3_sfp_sync_all_125M_RS.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_all_125M_RS.vhd @@ -11,13 +11,13 @@ use work.med_sync_define_RS.all; entity med_ecp3_sfp_sync_all_125M_RS is generic( - IS_MODE : int_array_t(0 to 3) := (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED); - IS_WAP_ZERO : integer := 1 + IS_MODE : int_array_t(0 to 3) := (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED) ); port( -- Clocks and reset CLK_REF_FULL : in std_logic; -- TRBnet reference clock SYSCLK : in std_logic; -- FPGA fabric clock + CLEAR : in std_logic; RESET : in std_logic; -- synchronous reset -- Media Interface TX/RX MEDIA_MED2INT : out med2int_array_t(0 to 3); @@ -386,7 +386,7 @@ begin fpga_txrefclk => MASTER_CLK_IN, -- reference TX clock tx_serdes_rst_c => '0', tx_pll_lol_qd_s => TX_PLL_LOL_OUT, - rst_qd_c => QUAD_RST_IN, + rst_qd_c => CLEAR, --QUAD_RST_IN, serdes_rst_qd_c => '0', -- was wrong tx_sync_qd_c => SYNC_TX_PLL_IN ); @@ -401,7 +401,6 @@ gen_control : for i in 0 to 3 generate gen_used_control : if (IS_MODE(i) = c_IS_SLAVE) or (IS_MODE(i) = c_IS_MASTER) generate THE_MED_CONTROL : entity work.med_sync_control_RS generic map( - IS_WAP_ZERO => IS_WAP_ZERO, IS_MODE => IS_MODE(i) ) port map( @@ -411,6 +410,7 @@ gen_control : for i in 0 to 3 generate CLK_RXHALF => clk_rx_half(i), CLK_TXI => clk_tx_full(i), CLK_REF => CLK_REF_FULL, + CLEAR => CLEAR, RESET => RESET, -- Media Interface MEDIA_MED2INT => MEDIA_MED2INT(i), @@ -470,6 +470,11 @@ gen_control : for i in 0 to 3 generate MEDIA_MED2INT(i).dataready <= '0'; MEDIA_MED2INT(i).tx_read <= '1'; MEDIA_MED2INT(i).stat_op <= x"0007"; + cv_cnt(i) <= (others => '0'); + word_sync_i(i) <= '0'; + RX_DLM_WORD_OUT(i*8+7 downto i*8) <= (others => '0'); + rx_rst_i(i) <= '0'; + rx_rst_word_i(i*8+7 downto i*8) <= (others => '0'); end generate; end generate; @@ -484,7 +489,7 @@ end generate; THE_SCI_READER : entity work.sci_reader_RS port map( CLK => SYSCLK, - RESET => RESET, + RESET => CLEAR, --'0', -- need for link establishment --SCI SCI_WRDATA => sci_data_in_i, SCI_RDDATA => sci_data_out_i, @@ -508,8 +513,7 @@ end generate; MEDIA_STATUS_REG_IN(207 downto 200) => cv_cnt_sys(1), MEDIA_STATUS_REG_IN(215 downto 208) => cv_cnt_sys(2), MEDIA_STATUS_REG_IN(223 downto 216) => cv_cnt_sys(3), - MEDIA_STATUS_REG_IN(255 downto 224) => (others => '0'), - DEBUG_OUT => open + MEDIA_STATUS_REG_IN(255 downto 224) => (others => '0') ); cv_cnt_sys <= cv_cnt when rising_edge(SYSCLK); @@ -521,7 +525,7 @@ end generate; -- SerDes #3 is used for debugging -- DEBUG_OUT <= debug_i(0*32+31 downto 0*32); -- all SerDes debug - DEBUG_OUT(31 downto 24) <= debug_i(3*32+7 downto 3*32); + DEBUG_OUT(31 downto 24) <= stat_fsm_reset_i(3*32+7 downto 3*32);--debug_i(3*32+7 downto 3*32); DEBUG_OUT(23 downto 16) <= debug_i(2*32+7 downto 2*32); DEBUG_OUT(15 downto 8) <= debug_i(1*32+7 downto 1*32); DEBUG_OUT(7 downto 0) <= debug_i(0*32+7 downto 0*32); diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd index 2b1fae4..21345e3 100644 --- a/media_interfaces/sync/med_sync_control_RS.vhd +++ b/media_interfaces/sync/med_sync_control_RS.vhd @@ -4,12 +4,10 @@ USE IEEE.numeric_std.all; library work; use work.trb_net_std.all; ---use work.trb_net_components.all; use work.med_sync_define_RS.all; entity med_sync_control_RS is generic( - IS_WAP_ZERO : integer := 1; -- should be 1 for synchronous operation IS_MODE : integer := c_IS_UNUSED ); port( @@ -19,6 +17,7 @@ entity med_sync_control_RS is CLK_RXHALF : in std_logic; -- used for media interface CLK_TXI : in std_logic; -- TX clock, from SerDes TX channel CLK_REF : in std_logic; -- SerDes reference clock + CLEAR : in std_logic; RESET : in std_logic; -- Media Interface MEDIA_MED2INT : out MED2INT; -- Media Interface OUT @@ -104,11 +103,6 @@ architecture med_sync_control_arch of med_sync_control_RS is signal link_rx_null_i : std_logic; signal link_rx_null_qref : std_logic; --- attribute syn_keep : boolean; --- attribute syn_preserve : boolean; --- attribute syn_keep of rx_lsm_state : signal is true; --- attribute syn_preserve of rx_lsm_state : signal is true; - begin ------------------------------------------------- @@ -126,7 +120,7 @@ begin ------------------------------------------------- THE_MAIN_RX_RST: main_rx_reset_RS port map( - CLEAR => '0', + CLEAR => CLEAR, --'0', -- DO NOT USE CLK_REF => CLK_REF, CDR_LOL_IN => RX_CDR_LOL_IN, CV_IN => RX_CV_IN, @@ -165,7 +159,7 @@ begin port map( CLK_RXI => CLK_RXI, CLK_SYS => CLK_SYS, - RESET => '0', --reset_i, + RESET => CLEAR, --'0', -- DO NOT USE -- RX_DATA_OUT => media_med2int_i.data, RX_PACKET_NUMBER_OUT => media_med2int_i.packet_num, @@ -207,7 +201,7 @@ begin port map( CLK_TXI => CLK_TXI, CLK_SYS => CLK_SYS, - RESET => '0', --reset_i, + CLEAR => CLEAR, --'0', -- DO NOT USE -- Media Interface TX_DATA_IN => MEDIA_INT2MED.data, TX_PACKET_NUMBER_IN => MEDIA_INT2MED.packet_num, @@ -249,7 +243,6 @@ begin ------------------------------------------------- led_ok <= link_full_done_i when rising_edge(CLK_SYS); led_rx <= (media_med2int_i.dataready or led_rx) and not timer(20) when rising_edge(CLK_SYS); --- led_tx <= (MEDIA_INT2MED.dataready or led_tx or sd_los_q) and not timer(20) when rising_edge(CLK_SYS); led_tx <= (MEDIA_INT2MED.dataready or led_tx or SFP_LOS_IN) and not timer(20) when rising_edge(CLK_SYS); ROC_TIMER_PROC: process( CLK_SYS, RESET ) @@ -327,15 +320,6 @@ begin LINK_RX_NULL_OUT <= link_rx_null_qref; -- TEST_LINE signals --- DEBUG_OUT(31 downto 12) <= (others => '0'); --- DEBUG_OUT(11) <= link_full_done_qsys; --- DEBUG_OUT(10) <= link_half_done_qsys; --- DEBUG_OUT(9) <= '0'; --- DEBUG_OUT(8) <= link_rx_ready_qsys; --- DEBUG_OUT(7) <= link_tx_ready_qsys; --- DEBUG_OUT(6 downto 2) <= (others => '0'); --- DEBUG_OUT(1 downto 0) <= debug_rx_control_i(1 downto 0); --- DEBUG_OUT <= (others => '0'); DEBUG_OUT(31 downto 8) <= (others => '0'); -- these signals will be used outside! DEBUG_OUT(7 downto 4) <= (others => '0'); diff --git a/media_interfaces/sync/med_sync_define_RS.vhd b/media_interfaces/sync/med_sync_define_RS.vhd index 4ed1ccf..8aefe48 100644 --- a/media_interfaces/sync/med_sync_define_RS.vhd +++ b/media_interfaces/sync/med_sync_define_RS.vhd @@ -29,12 +29,10 @@ component main_rx_reset_RS is port ( CLEAR : in std_logic; CLK_REF : in std_logic; - PLL_LOL_IN : in std_logic; CDR_LOL_IN : in std_logic; CV_IN : in std_logic; LSM_IN : in std_logic; LOS_IN : in std_logic; - SD_LOS_IN : in std_logic; WAP_ZERO_IN : in std_logic; -- outputs WAP_REQ_OUT : out std_logic; @@ -45,6 +43,22 @@ component main_rx_reset_RS is ); end component; +component main_tx_reset_RS is + port( + CLEAR : in std_logic; -- async reset, active high + CLK_REF : in std_logic; -- usually RX_REFCLK, not TX_REFCLK! + TX_PLL_LOL_QD_A_IN : in std_logic; -- QUAD A + TX_PLL_LOL_QD_B_IN : in std_logic; -- QUAD B + TX_PLL_LOL_QD_C_IN : in std_logic; -- QUAD C + TX_PLL_LOL_QD_D_IN : in std_logic; -- QUAD D + TX_CLOCK_AVAIL_IN : in std_logic; -- recovered RX clock available (if needed) + TX_PCS_RST_CH_C_OUT : out std_logic; -- PCS reset + SYNC_TX_QUAD_OUT : out std_logic; -- sync all QUADs to TX bit 0 + LINK_TX_READY_OUT : out std_logic; -- TX lane can use used now + STATE_OUT : out std_logic_vector(3 downto 0) + ); +end component; + component signal_sync is generic( WIDTH : integer := 1; -- @@ -75,22 +89,6 @@ component lattice_ecp3_fifo_18x16_dualport_oreg ); end component; -component main_tx_reset_RS is - port( - CLEAR : in std_logic; -- async reset, active high - CLK_REF : in std_logic; -- usually RX_REFCLK, not TX_REFCLK! - TX_PLL_LOL_QD_A_IN : in std_logic; -- QUAD A - TX_PLL_LOL_QD_B_IN : in std_logic; -- QUAD B - TX_PLL_LOL_QD_C_IN : in std_logic; -- QUAD C - TX_PLL_LOL_QD_D_IN : in std_logic; -- QUAD D - TX_CLOCK_AVAIL_IN : in std_logic; -- recovered RX clock available (if needed) - TX_PCS_RST_CH_C_OUT : out std_logic; -- PCS reset - SYNC_TX_QUAD_OUT : out std_logic; -- sync all QUADs to TX bit 0 - LINK_TX_READY_OUT : out std_logic; -- TX lane can use used now - STATE_OUT : out std_logic_vector(3 downto 0) - ); -end component; - component rx_control_RS is port( CLK_RXI : in std_logic; @@ -127,7 +125,7 @@ component tx_control_RS is port( CLK_TXI : in std_logic; CLK_SYS : in std_logic; - RESET : in std_logic; -- async/sync reset + CLEAR : in std_logic; -- Media Interface TX_DATA_IN : in std_logic_vector(15 downto 0); -- media interface TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0); -- media interface diff --git a/media_interfaces/sync/sci_reader_RS.vhd b/media_interfaces/sync/sci_reader_RS.vhd index 08e67ac..f5fca7d 100644 --- a/media_interfaces/sync/sci_reader_RS.vhd +++ b/media_interfaces/sync/sci_reader_RS.vhd @@ -27,8 +27,7 @@ entity sci_reader_RS is --Slowcontrol BUS_RX : in CTRLBUS_RX; BUS_TX : out CTRLBUS_TX; - MEDIA_STATUS_REG_IN : in std_logic_vector(255 downto 0) := (others => '0'); - DEBUG_OUT : out std_logic_vector(31 downto 0) + MEDIA_STATUS_REG_IN : in std_logic_vector(255 downto 0) := (others => '0') ); end entity; @@ -141,5 +140,6 @@ begin end process PROC_SCI_CTRL; WA_POS_OUT <= wa_position; - + WA_ACK_OUT <= '0'; + end architecture; diff --git a/media_interfaces/sync/tx_control_RS.vhd b/media_interfaces/sync/tx_control_RS.vhd index 61bfbb5..f553dfa 100644 --- a/media_interfaces/sync/tx_control_RS.vhd +++ b/media_interfaces/sync/tx_control_RS.vhd @@ -16,7 +16,7 @@ entity tx_control_RS is port( CLK_TXI : in std_logic; CLK_SYS : in std_logic; - RESET : in std_logic; -- async/sync reset + CLEAR : in std_logic; -- Media Interface TX_DATA_IN : in std_logic_vector(15 downto 0); -- media interface TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0); -- media interface @@ -173,12 +173,12 @@ begin AlmostFull => ct_fifo_afull ); - THE_RD_PROC : process(CLK_SYS) - begin - if rising_edge(CLK_SYS) then - buf_tx_read_out <= link_active_qsys and not ct_fifo_afull ; - end if; - end process; + THE_RD_PROC: process( CLK_SYS ) + begin + if rising_edge(CLK_SYS) then + buf_tx_read_out <= link_active_qsys and not ct_fifo_afull ; + end if; + end process; ct_fifo_reset <= not link_active_qtx; TX_READ_OUT <= buf_tx_read_out; @@ -195,64 +195,64 @@ begin ---------------------------------------------------------------------- -- RAM ---------------------------------------------------------------------- - THE_RAM_WR_PROC : process(CLK_TXI) - begin - if( rising_edge(CLK_TXI) ) then - ram_write <= last_ct_fifo_read and not last_ct_fifo_empty; - end if; - end process; + THE_RAM_WR_PROC: process( CLK_TXI ) + begin + if( rising_edge(CLK_TXI) ) then + ram_write <= last_ct_fifo_read and not last_ct_fifo_empty; + end if; + end process THE_RAM_WR_PROC; --RAM - THE_RAM_PROC : process(CLK_TXI) - begin - if( rising_edge(CLK_TXI) ) then - if( ram_write = '1' ) then - ram((to_integer(ram_write_addr))) <= tx_data_200; - end if; - next_ram_dout <= ram(to_integer(ram_read_addr)); - ram_dout <= next_ram_dout; + THE_RAM_PROC: process( CLK_TXI ) + begin + if( rising_edge(CLK_TXI) ) then + if( ram_write = '1' ) then + ram((to_integer(ram_write_addr))) <= tx_data_200; end if; - end process; + next_ram_dout <= ram(to_integer(ram_read_addr)); + ram_dout <= next_ram_dout; + end if; + end process THE_RAM_PROC; --RAM read pointer - THE_READ_CNT : process(CLK_TXI) - begin - if( rising_edge(CLK_TXI) ) then - if( link_active_qtx = '0' ) then - ram_read_addr <= (others => '0'); - elsif( ram_read = '1' ) then - ram_read_addr <= ram_read_addr + to_unsigned(1,1); - end if; + THE_READ_CNT: process( CLK_TXI ) + begin + if( rising_edge(CLK_TXI) ) then + if( link_active_qtx = '0' ) then + ram_read_addr <= (others => '0'); + elsif( ram_read = '1' ) then + ram_read_addr <= ram_read_addr + to_unsigned(1,1); end if; - end process; + end if; + end process THE_READ_CNT; --RAM write pointer - THE_WRITE_CNT : process(CLK_TXI) - begin - if( rising_edge(CLK_TXI) ) then - if( link_active_qtx = '0' ) then - ram_write_addr <= (others => '0'); - elsif( ram_write = '1' ) then - ram_write_addr <= ram_write_addr + to_unsigned(1,1); - end if; + THE_WRITE_CNT: process( CLK_TXI ) + begin + if( rising_edge(CLK_TXI) ) then + if( link_active_qtx = '0' ) then + ram_write_addr <= (others => '0'); + elsif( ram_write = '1' ) then + ram_write_addr <= ram_write_addr + to_unsigned(1,1); end if; - end process; + end if; + end process THE_WRITE_CNT; --RAM fill level counter - THE_FILL_CNT : process(CLK_TXI) - begin - if( rising_edge(CLK_TXI) ) then - if( link_active_qtx = '0' ) then - ram_fill_level <= (others => '0'); - else - ram_fill_level <= last_ram_write_addr - ram_read_addr; - end if; + THE_FILL_CNT: process( CLK_TXI ) + begin + if( rising_edge(CLK_TXI) ) then + if( link_active_qtx = '0' ) then + ram_fill_level <= (others => '0'); + else + ram_fill_level <= last_ram_write_addr - ram_read_addr; end if; - end process; + end if; + end process THE_FILL_CNT; --RAM empty - ram_empty <= '1' when (last_ram_write_addr = ram_read_addr) or RESET = '1' else '0'; - ram_afull <= '1' when ram_fill_level >= 4 else '0'; + ram_empty <= '1' when ((last_ram_write_addr = ram_read_addr) or (CLEAR = '1')) else '0'; + ram_afull <= '1' when (ram_fill_level >= 4) else '0'; last_ram_write_addr <= ram_write_addr when rising_edge(CLK_TXI); @@ -260,141 +260,141 @@ begin -- TX control state machine ---------------------------------------------------------------------- - THE_DATA_CONTROL_FSM : process(CLK_TXI, RESET) - begin - if( RESET = '1' ) then - current_state <= IDLE; - tx_k_i <= '1'; - tx_data_i <= K_NULL; - word_sync_i <= '0'; - else - if( rising_edge(CLK_TXI) ) then - tx_k_i <= '0'; - word_sync_i <= '0'; - debug_sending_dlm <= '0'; - debug_sending_rst <= '0'; + THE_DATA_CONTROL_FSM: process( CLK_TXI, CLEAR, link_active_qtx ) + begin + if( CLEAR = '1' ) then + current_state <= IDLE; + tx_k_i <= '1'; + tx_data_i <= K_NULL; + word_sync_i <= '0'; + else + if( rising_edge(CLK_TXI) ) then + tx_k_i <= '0'; + word_sync_i <= '0'; + debug_sending_dlm <= '0'; + debug_sending_rst <= '0'; - case current_state is - when IDLE => - tx_k_i <= '1'; - tx_data_i <= K_NULL; - if( (link_tx_ready_qtx = '1') and (link_tx_null_qtx = '0') ) then - current_state <= SEND_IDLE_L; - else - current_state <= IDLE; - end if; + case current_state is + when IDLE => + tx_k_i <= '1'; + tx_data_i <= K_NULL; + if( (link_tx_ready_qtx = '1') and (link_tx_null_qtx = '0') ) then + current_state <= SEND_IDLE_L; + else + current_state <= IDLE; + end if; - when SEND_IDLE_L => - tx_data_i <= K_IDLE; - tx_k_i <= '1'; - if( WORD_SYNC_IN = '1' )then - current_state <= SEND_IDLE_H; - else - current_state <= SEND_IDLE_L; - end if; - - when SEND_IDLE_H => - word_sync_i <= '1'; - if( send_steady_idle_int = '1' ) then - tx_data_i <= D_IDLE1; - else - tx_data_i <= D_IDLE0; - end if; - - when SEND_DATA_L => - tx_data_i <= ram_dout(7 downto 0); - load_sop <= ram_dout(16); - load_eop <= ram_dout(17); - current_state <= SEND_DATA_H; - - when SEND_DATA_H => - word_sync_i <= '1'; - tx_data_i <= ram_dout(15 downto 8); - - when SEND_DLM_L => - tx_data_i <= K_DLM; - tx_k_i <= '1'; - current_state <= SEND_DLM_H; - debug_sending_dlm <= '1'; - - when SEND_DLM_H => - word_sync_i <= '1'; - tx_data_i <= send_dlm_word_i; - - when SEND_RST_L => - tx_data_i <= K_RST; - tx_k_i <= '1'; - current_state <= SEND_RST_H; - debug_sending_rst <= '1'; - - when SEND_RST_H => - word_sync_i <= '1'; - tx_data_i <= send_rst_word_i; - - when others => + when SEND_IDLE_L => + tx_data_i <= K_IDLE; + tx_k_i <= '1'; + if( WORD_SYNC_IN = '1' )then + current_state <= SEND_IDLE_H; + else current_state <= SEND_IDLE_L; - end case; - - if( (current_state = SEND_IDLE_H) or (current_state = SEND_DATA_H) or - (current_state = SEND_DLM_H) or (current_state = SEND_RST_H) ) then - if ( (link_tx_ready_qtx = '0') or (link_tx_null_qtx = '1') ) then - current_state <= IDLE; - elsif( send_dlm_i = '1' ) then - current_state <= SEND_DLM_L; - elsif( send_rst_i = '1' ) then - current_state <= SEND_RST_L; - elsif( ram_empty = '0' ) then - current_state <= SEND_DATA_L; + end if; + + when SEND_IDLE_H => + word_sync_i <= '1'; + if( send_steady_idle_int = '1' ) then + tx_data_i <= D_IDLE1; else - current_state <= SEND_IDLE_L; + tx_data_i <= D_IDLE0; end if; + when SEND_DATA_L => + tx_data_i <= ram_dout(7 downto 0); + load_sop <= ram_dout(16); + load_eop <= ram_dout(17); + current_state <= SEND_DATA_H; + + when SEND_DATA_H => + word_sync_i <= '1'; + tx_data_i <= ram_dout(15 downto 8); + + when SEND_DLM_L => + tx_data_i <= K_DLM; + tx_k_i <= '1'; + current_state <= SEND_DLM_H; + debug_sending_dlm <= '1'; + + when SEND_DLM_H => + word_sync_i <= '1'; + tx_data_i <= send_dlm_word_i; + + when SEND_RST_L => + tx_data_i <= K_RST; + tx_k_i <= '1'; + current_state <= SEND_RST_H; + debug_sending_rst <= '1'; + + when SEND_RST_H => + word_sync_i <= '1'; + tx_data_i <= send_rst_word_i; + + when others => + current_state <= SEND_IDLE_L; + + end case; + + if( (current_state = SEND_IDLE_H) or (current_state = SEND_DATA_H) or + (current_state = SEND_DLM_H) or (current_state = SEND_RST_H) ) then + if ( (link_tx_ready_qtx = '0') or (link_tx_null_qtx = '1') ) then + current_state <= IDLE; + elsif( send_dlm_i = '1' ) then + current_state <= SEND_DLM_L; + elsif( send_rst_i = '1' ) then + current_state <= SEND_RST_L; + elsif( ram_empty = '0' ) then + current_state <= SEND_DATA_L; + else + current_state <= SEND_IDLE_L; end if; - end if; - end if; - --async because of oreg. - if ((current_state = SEND_IDLE_H) or (current_state = SEND_DATA_H) or (current_state = SEND_DLM_H) or (current_state = SEND_RST_H)) - and (ram_empty = '0') and (link_active_qtx = '1') and (send_dlm_i = '0') and (send_rst_i = '0') then - ram_read <= '1'; - else - ram_read <= '0'; - end if; - if RESET = '1' then - ram_read <= '0'; + end if; end if; + end if; - end process; + --async because of oreg. + if ((current_state = SEND_IDLE_H) or (current_state = SEND_DATA_H) or (current_state = SEND_DLM_H) or (current_state = SEND_RST_H)) + and (ram_empty = '0') and (link_active_qtx = '1') and (send_dlm_i = '0') and (send_rst_i = '0') then + ram_read <= '1'; + else + ram_read <= '0'; + end if; + if (CLEAR = '1') then + ram_read <= '0'; + end if; + end process THE_DATA_CONTROL_FSM; ---------------------------------------------------------------------- -- ---------------------------------------------------------------------- -send_dlm_i <= SEND_DLM_IN when rising_edge(CLK_TXI); -send_dlm_word_i <= SEND_DLM_WORD_IN when rising_edge(CLK_TXI); + send_dlm_i <= SEND_DLM_IN when rising_edge(CLK_TXI); + send_dlm_word_i <= SEND_DLM_WORD_IN when rising_edge(CLK_TXI); -- Send RST message -- UNTESTED - THE_STORE_RST_PROC: process( CLK_TXI, RESET ) - begin - if( RESET = '1' ) then + THE_STORE_RST_PROC: process( CLK_TXI, CLEAR ) + begin + if( CLEAR = '1' ) then + send_rst_i <= '0'; + send_rst_word_i <= (others => '0'); + elsif( rising_edge(CLK_TXI) ) then + if ( link_active_qtx = '0' ) then send_rst_i <= '0'; send_rst_word_i <= (others => '0'); - elsif( rising_edge(CLK_TXI) ) then - if ( link_active_qtx = '0' ) then - send_rst_i <= '0'; - send_rst_word_i <= (others => '0'); - elsif( SEND_RST_IN = '1' ) then - send_rst_i <= '1'; - send_rst_word_i <= SEND_RST_WORD_IN; - elsif( current_state = SEND_RST_L ) then - send_rst_i <= '0'; - elsif( current_state = SEND_RST_H ) then - send_rst_word_i <= (others => '0'); - end if; + elsif( SEND_RST_IN = '1' ) then + send_rst_i <= '1'; + send_rst_word_i <= SEND_RST_WORD_IN; + elsif( current_state = SEND_RST_L ) then + send_rst_i <= '0'; + elsif( current_state = SEND_RST_H ) then + send_rst_word_i <= (others => '0'); end if; - end process THE_STORE_RST_PROC; + end if; + end process THE_STORE_RST_PROC; ---------------------------------------------------------------------- -- Debug @@ -407,27 +407,27 @@ send_dlm_word_i <= SEND_DLM_WORD_IN when rising_edge(CLK_TXI); DEBUG_OUT(4) <= '0'; --toggle_idle when rising_edge(CLK_TXI); DEBUG_OUT(3 downto 0) <= state_bits when rising_edge(CLK_TXI); - process(CLK_SYS) - begin - if rising_edge(CLK_SYS) then --- STAT_REG_OUT <= (others => '0'); - STAT_REG_OUT(3 downto 0) <= state_bits; - STAT_REG_OUT(7 downto 4) <= (others => '0'); - STAT_REG_OUT(15 downto 8) <= std_logic_vector(ram_read_addr); - STAT_REG_OUT(17) <= ram_empty; - STAT_REG_OUT(18) <= link_active_qsys; - STAT_REG_OUT(19) <= '0'; - STAT_REG_OUT(21 downto 20) <= (others => '0'); - STAT_REG_OUT(22) <= load_eop; - STAT_REG_OUT(23) <= send_dlm_i; - STAT_REG_OUT(26 downto 24) <= (others => '0'); - STAT_REG_OUT(27) <= ct_fifo_afull; - STAT_REG_OUT(28) <= ct_fifo_read; - STAT_REG_OUT(29) <= ct_fifo_write; - STAT_REG_OUT(30) <= RESET; - STAT_REG_OUT(31) <= '0'; - end if; - end process; + THE_STAT_PROC: process( CLK_SYS ) + begin + if rising_edge(CLK_SYS) then +-- STAT_REG_OUT <= (others => '0'); + STAT_REG_OUT(3 downto 0) <= state_bits; + STAT_REG_OUT(7 downto 4) <= (others => '0'); + STAT_REG_OUT(15 downto 8) <= std_logic_vector(ram_read_addr); + STAT_REG_OUT(17) <= ram_empty; + STAT_REG_OUT(18) <= link_active_qsys; + STAT_REG_OUT(19) <= '0'; + STAT_REG_OUT(21 downto 20) <= (others => '0'); + STAT_REG_OUT(22) <= load_eop; + STAT_REG_OUT(23) <= send_dlm_i; + STAT_REG_OUT(26 downto 24) <= (others => '0'); + STAT_REG_OUT(27) <= ct_fifo_afull; + STAT_REG_OUT(28) <= ct_fifo_read; + STAT_REG_OUT(29) <= ct_fifo_write; + STAT_REG_OUT(30) <= CLEAR; + STAT_REG_OUT(31) <= '0'; + end if; + end process THE_STAT_PROC; state_bits <= x"0" when current_state = IDLE else x"1" when current_state = SEND_IDLE_L else -- 2.43.0