From 40049a8744728f8c7123047f0e35dcc1f29d2ca9 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Thu, 11 Oct 2007 14:23:02 +0000 Subject: [PATCH] some changes to 16bit files, Jan --- trb_net16_apimbuf.vhd | 152 ++++++----- trb_net16_base_api.vhd | 29 +- trb_net16_io_multiplexer.vhd | 68 +++-- trb_net16_obuf.vhd | 1 - ...et16_trigger_receiver_apimbuf_endpoint.vhd | 87 +++--- trb_net16_trigger_receiver_endpoint.vhd | 66 +++-- xilinx/trb_net_fifo_arch.vhd | 253 ++++++++++-------- 7 files changed, 383 insertions(+), 273 deletions(-) diff --git a/trb_net16_apimbuf.vhd b/trb_net16_apimbuf.vhd index c2bd86c..6f44801 100644 --- a/trb_net16_apimbuf.vhd +++ b/trb_net16_apimbuf.vhd @@ -13,10 +13,10 @@ entity trb_net16_apimbuf is generic ( API_TYPE : integer range 0 to 1 := 1; INIT_DEPTH : integer range 0 to 7 := 0; - REPLY_DEPTH : integer range 0 to 7 := 2; - FIFO_TO_INT_DEPTH : integer range 0 to 7 := 2; - FIFO_TO_APL_DEPTH : integer range 0 to 7 := 2; - FIFO_TERM_BUFFER_DEPTH : integer := 0 + REPLY_DEPTH : integer range 0 to 7 := 1; + FIFO_TO_INT_DEPTH : integer range 0 to 7 := 1; + FIFO_TO_APL_DEPTH : integer range 0 to 7 := 1; + FIFO_TERM_BUFFER_DEPTH : integer := 0; MULT_WIDTH : integer range 1 to 5 := 3; DAT_CHANNEL : integer range 0 to 2**(MULT_WIDTH-1) := 0; DATA_WIDTH : integer range 16 to 16 := 16; @@ -248,24 +248,24 @@ component trb_net16_io_multiplexer is CLK_EN : in std_logic; -- Media direction port MED_DATAREADY_IN: in std_logic; - MED_DATA_IN: in std_logic_vector (BUS_WIDTH-1 downto 0); + MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0); -- highest bits are mult. MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0); MED_READ_OUT: out std_logic; MED_DATAREADY_OUT: out std_logic; - MED_DATA_OUT: out std_logic_vector (BUS_WIDTH-1 downto 0); + MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0); MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); MED_READ_IN: in std_logic; -- Internal direction port INT_DATAREADY_OUT: out std_logic_vector (2**MULT_WIDTH-1 downto 0); - INT_DATA_OUT: out std_logic_vector ((BUS_WIDTH)*(2**MULT_WIDTH)-1 downto 0); + INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MULT_WIDTH)-1 downto 0); INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MULT_WIDTH)-1 downto 0); INT_READ_IN: in std_logic_vector (2**MULT_WIDTH-1 downto 0); INT_DATAREADY_IN: in std_logic_vector (2**MULT_WIDTH-1 downto 0); - INT_DATA_IN: in std_logic_vector ((BUS_WIDTH)*(2**MULT_WIDTH)-1 downto 0); + INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MULT_WIDTH)-1 downto 0); INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MULT_WIDTH)-1 downto 0); INT_READ_OUT: out std_logic_vector (2**MULT_WIDTH-1 downto 0); @@ -317,36 +317,52 @@ signal MED_REPLY_PACKET_NUM_IN : std_logic_vector (1 downto 0); signal MED_REPLY_READ_OUT : std_logic; signal m_DATAREADY_OUT : std_logic_vector (2**MULT_WIDTH-1 downto 0); -signal m_DATA_OUT : std_logic_vector (BUS_WIDTH*2**MULT_WIDTH-1 downto 0); +signal m_DATA_OUT : std_logic_vector (DATA_WIDTH*2**MULT_WIDTH-1 downto 0); signal m_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH*2**MULT_WIDTH-1 downto 0); signal m_READ_IN : std_logic_vector (2**MULT_WIDTH-1 downto 0); signal m_DATAREADY_IN : std_logic_vector (2**MULT_WIDTH-1 downto 0); -signal m_DATA_IN : std_logic_vector (BUS_WIDTH**MULT_WIDTH-1 downto 0); +signal m_DATA_IN : std_logic_vector (DATA_WIDTH*2**MULT_WIDTH-1 downto 0); signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MULT_WIDTH-1 downto 0); signal m_READ_OUT : std_logic_vector (2**MULT_WIDTH-1 downto 0); begin --Connections for data channel - m_DATAREADY_OUT(DAT_CHANNEL*2) <= MED_DAT_INIT_DATAREADY_OUT; - m_DATAREADY_OUT(DAT_CHANNEL*2+1) <= MED_DAT_REPLY_DATAREADY_OUT; - m_DATA_OUT((DAT_CHANNEL*2+1)*BUS_WIDTH-1 downto DAT_CHANNEL*BUS_WIDTH*2) <= MED_DAT_INIT_DATA_OUT; - m_DATA_OUT((DAT_CHANNEL*2+2)*BUS_WIDTH-1 downto (DAT_CHANNEL*2+1)*BUS_WIDTH) <= MED_DAT_REPLY_DATA_OUT; - m_PACKET_NUM_OUT(DAT_CHANNEL*NUM_WIDTH*2+1 downto DAT_CHANNEL*NUM_WIDTH*2) <= MED_DAT_INIT_PACKET_NUM_OUT; - m_PACKET_NUM_OUT(DAT_CHANNEL*NUM_WIDTH*3+1 downto DAT_CHANNEL*NUM_WIDTH*3) <= MED_DAT_REPLY_PACKET_NUM_OUT; - MED_DAT_INIT_READ_IN <= m_READ_IN(DAT_CHANNEL*2); - MED_DAT_REPLY_READ_IN <= m_READ_IN(DAT_CHANNEL*2+1); - - MED_DAT_INIT_DATAREADY_IN <= m_DATAREADY_IN(DAT_CHANNEL*2); - MED_DAT_REPLY_DATAREADY_IN <= m_DATAREADY_IN(DAT_CHANNEL*2+1); - MED_DAT_INIT_DATA_IN <= m_DATA_IN((DAT_CHANNEL*2+1)*BUS_WIDTH-1 downto DAT_CHANNEL*BUS_WIDTH*2); - MED_DAT_REPLY_DATA_IN <= m_DATA_IN((DAT_CHANNEL*2+2)*BUS_WIDTH-1 downto (DAT_CHANNEL*2+1)*BUS_WIDTH); - MED_DAT_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(DAT_CHANNEL*NUM_WIDTH*2+1 downto DAT_CHANNEL*NUM_WIDTH*2); - MED_DAT_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(DAT_CHANNEL*NUM_WIDTH*3+1 downto DAT_CHANNEL*NUM_WIDTH*3); - m_READ_OUT(DAT_CHANNEL*2) <= MED_DAT_INIT_READ_OUT; - m_READ_OUT(DAT_CHANNEL*2+1) <= MED_DAT_REPLY_READ_OUT; - + genmuxcon : for i in 0 to 2**(MULT_WIDTH-1)-1 generate + gendat: if i = DAT_CHANNEL generate + m_DATAREADY_OUT(i*2) <= MED_INIT_DATAREADY_OUT; + m_DATAREADY_OUT(i*2+1) <= MED_REPLY_DATAREADY_OUT; + m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_INIT_DATA_OUT; + m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_REPLY_DATA_OUT; + m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_INIT_PACKET_NUM_OUT; + m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_REPLY_PACKET_NUM_OUT; + MED_INIT_READ_IN <= m_READ_IN(i*2); + MED_REPLY_READ_IN <= m_READ_IN(i*2+1); + MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2); + MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1); + MED_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2); + MED_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH); + MED_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2); + MED_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2); + m_READ_OUT(i*2) <= MED_INIT_READ_OUT; + m_READ_OUT(i*2+1) <= MED_REPLY_READ_OUT; + end generate; + genelse: if i /= DAT_CHANNEL generate + m_DATAREADY_OUT(i*2) <= '0'; + m_DATAREADY_OUT(i*2+1) <= '0'; + m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= (others => '0'); + m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= (others => '0'); + m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= (others => '0'); + m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= (others => '0'); + + m_READ_OUT(i*2) <= '0'; + m_READ_OUT(i*2+1) <= '0'; + end generate; + end generate; + + + gen_actapi: if API_TYPE = 1 generate DAT_ACTIVE_API: trb_net16_base_api generic map ( @@ -381,26 +397,26 @@ begin APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, APL_SEQNR_OUT => APL_SEQNR_OUT, -- Internal direction port - INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT_INIT_DATAREADY, - INT_MASTER_DATA_OUT => apl_to_buf_DAT_INIT_DATA, - INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT_INIT_PACKET_NUM, - INT_MASTER_READ_IN => apl_to_buf_DAT_INIT_READ, - INT_MASTER_DATAREADY_IN => buf_to_apl_DAT_INIT_DATAREADY, - INT_MASTER_DATA_IN => buf_to_apl_DAT_INIT_DATA, - INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT_INIT_PACKET_NUM, - INT_MASTER_READ_OUT => buf_to_apl_DAT_INIT_READ, + INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY, + INT_MASTER_DATA_OUT => apl_to_buf_INIT_DATA, + INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM, + INT_MASTER_READ_IN => apl_to_buf_INIT_READ, + INT_MASTER_DATAREADY_IN => buf_to_apl_INIT_DATAREADY, + INT_MASTER_DATA_IN => buf_to_apl_INIT_DATA, + INT_MASTER_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM, + INT_MASTER_READ_OUT => buf_to_apl_INIT_READ, INT_SLAVE_HEADER_IN => '0', - INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT_REPLY_DATAREADY, - INT_SLAVE_DATA_OUT => apl_to_buf_DAT_REPLY_DATA, - INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT_REPLY_PACKET_NUM, - INT_SLAVE_READ_IN => apl_to_buf_DAT_REPLY_READ, - INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT_REPLY_DATAREADY, - INT_SLAVE_DATA_IN => buf_to_apl_DAT_REPLY_DATA, - INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT_REPLY_PACKET_NUM, - INT_SLAVE_READ_OUT => buf_to_apl_DAT_REPLY_READ, + INT_SLAVE_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY, + INT_SLAVE_DATA_OUT => apl_to_buf_REPLY_DATA, + INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM, + INT_SLAVE_READ_IN => apl_to_buf_REPLY_READ, + INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY, + INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA, + INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM, + INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ, -- Status and control port - STAT_FIFO_TO_INT => DAT_api_stat_fifo_to_int, - STAT_FIFO_TO_APL => DAT_api_stat_fifo_to_apl + STAT_FIFO_TO_INT => api_stat_fifo_to_int, + STAT_FIFO_TO_APL => api_stat_fifo_to_apl ); end generate; @@ -438,26 +454,26 @@ begin APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, APL_SEQNR_OUT => APL_SEQNR_OUT, -- Internal direction port - INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT_REPLY_DATAREADY, - INT_MASTER_DATA_OUT => apl_to_buf_DAT_REPLY_DATA, - INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT_REPLY_PACKET_NUM, - INT_MASTER_READ_IN => apl_to_buf_DAT_REPLY_READ, - INT_MASTER_DATAREADY_IN => buf_to_apl_DAT_REPLY_DATAREADY, - INT_MASTER_DATA_IN => buf_to_apl_DAT_REPLY_DATA, - INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT_REPLY_PACKET_NUM, - INT_MASTER_READ_OUT => buf_to_apl_DAT_REPLY_READ, + INT_MASTER_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY, + INT_MASTER_DATA_OUT => apl_to_buf_REPLY_DATA, + INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM, + INT_MASTER_READ_IN => apl_to_buf_REPLY_READ, + INT_MASTER_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY, + INT_MASTER_DATA_IN => buf_to_apl_REPLY_DATA, + INT_MASTER_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM, + INT_MASTER_READ_OUT => buf_to_apl_REPLY_READ, INT_SLAVE_HEADER_IN => '0', - INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT_INIT_DATAREADY, - INT_SLAVE_DATA_OUT => apl_to_buf_DAT_INIT_DATA, - INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT_INIT_PACKET_NUM, - INT_SLAVE_READ_IN => apl_to_buf_DAT_INIT_READ, - INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT_INIT_DATAREADY, - INT_SLAVE_DATA_IN => buf_to_apl_DAT_INIT_DATA, - INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT_INIT_PACKET_NUM, - INT_SLAVE_READ_OUT => buf_to_apl_DAT_INIT_READ, + INT_SLAVE_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY, + INT_SLAVE_DATA_OUT => apl_to_buf_INIT_DATA, + INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_INIT_PACKET_NUM, + INT_SLAVE_READ_IN => apl_to_buf_INIT_READ, + INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY, + INT_SLAVE_DATA_IN => buf_to_apl_INIT_DATA, + INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM, + INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ, -- Status and control port - STAT_FIFO_TO_INT => DAT_api_stat_fifo_to_int, - STAT_FIFO_TO_APL => DAT_api_stat_fifo_to_apl + STAT_FIFO_TO_INT => api_stat_fifo_to_int, + STAT_FIFO_TO_APL => api_stat_fifo_to_apl ); end generate; @@ -474,8 +490,8 @@ STAT_api_control_signals(31 downto 13) <= (others => '0'); IOBUF: trb_net16_iobuf - generic map (INIT_DEPTH => DAT_INIT_DEPTH, - REPLY_DEPTH => DAT_REPLY_DEPTH) + generic map (INIT_DEPTH => INIT_DEPTH, + REPLY_DEPTH => REPLY_DEPTH) port map ( -- Misc @@ -540,8 +556,8 @@ IOBUF: trb_net16_iobuf ); MPLEX: trb_net16_io_multiplexer - generic map (BUS_WIDTH => 16, - MULT_WIDTH => 1) + generic map (BUS_WIDTH => DATA_WIDTH, + MULT_WIDTH => MULT_WIDTH) port map ( CLK => CLK, RESET => RESET , diff --git a/trb_net16_base_api.vhd b/trb_net16_base_api.vhd index b937d86..5280c0e 100644 --- a/trb_net16_base_api.vhd +++ b/trb_net16_base_api.vhd @@ -589,13 +589,24 @@ begin elsif current_state = SHUTDOWN then next_state <= SHUTDOWN; if sbuf_free = '1' then - fifo_to_int_read <= '1'; - next_INT_MASTER_DATAREADY_OUT <= '1'; - -- we are done - --implicit: fill with padding words - if master_counter = "00" and fifo_to_int_empty = '1' then - next_state <= SEND_TRAILER; - out_select <= TRM; +-- next_INT_MASTER_DATAREADY_OUT <= '1'; +-- -- we are done +-- --implicit: fill with padding words +-- if master_counter = "00" and fifo_to_int_empty = '1' then +-- next_state <= SEND_TRAILER; +-- out_select <= TRM; + if fifo_to_int_empty = '0' then + -- data words have to be prepared + fifo_to_int_read <= '1'; + next_INT_MASTER_DATAREADY_OUT <= '1'; + else + -- we are done + --implicit: fill with padding words + if master_counter = "00" then + next_state <= SEND_TRAILER; + out_select <= TRM; + end if; + next_INT_MASTER_DATAREADY_OUT <= '1'; end if; end if; ------------------------------------------------------------------------------- @@ -645,8 +656,8 @@ begin next_slave_running <= '1'; end if; end if; - if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT= "11" - and (APL_READ_IN = '1' and reg_APL_DATAREADY_OUT = '1') then --fifo_to_apl_read = '1' + if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT= "11" and (APL_READ_IN = '1' and reg_APL_DATAREADY_OUT = '1') + then --fifo_to_apl_read = '1' next_state <= IDLE; if API_TYPE = 1 then next_sequence_counter <= sequence_counter +1; diff --git a/trb_net16_io_multiplexer.vhd b/trb_net16_io_multiplexer.vhd index 06f067d..2d616b5 100644 --- a/trb_net16_io_multiplexer.vhd +++ b/trb_net16_io_multiplexer.vhd @@ -8,9 +8,13 @@ use work.trb_net_std.all; entity trb_net16_io_multiplexer is - generic (BUS_WIDTH : integer := 16; - MULT_WIDTH : integer range 1 to 5 := 3); - + generic ( + BUS_WIDTH : integer := 16; + NUM_WIDTH : integer := 2; + MULT_WIDTH : integer range 1 to 5 := 3; + SECURE_MODE : integer range 0 to 1 := 0 --use sbufs or not? + ); + port( -- Misc CLK : in std_logic; @@ -117,23 +121,43 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is ------------------------------------------------------------------------------ G1: for i in 0 to 2**MULT_WIDTH-1 generate - DEMUX_SBUF: trb_net16_sbuf - generic map (DATA_WIDTH => BUS_WIDTH+2, VERSION => 0) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - COMB_DATAREADY_IN => next_demux_dr(i), - COMB_next_READ_OUT => demux_next_READ(i), - COMB_READ_IN => current_demux_READ(i), - COMB_DATA_IN => MED_DATA_IN, - COMB_PACKET_NUM_IN => MED_PACKET_NUM_IN, - SYN_DATAREADY_OUT => INT_DATAREADY_OUT(i), - SYN_DATA_OUT => INT_DATA_OUT ((BUS_WIDTH)*(i+1)-1 downto (BUS_WIDTH)*(i)), - SYN_PACKET_NUM_OUT => INT_PACKET_NUM_OUT(2*(i+1)-1 downto 2*i), - SYN_READ_IN => INT_READ_IN(i) - ); + gensbuf: if SECURE_MODE = 1 generate + DEMUX_SBUF: trb_net16_sbuf + generic map (DATA_WIDTH => BUS_WIDTH, NUM_WIDTH => NUM_WIDTH, VERSION => 0) + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + COMB_DATAREADY_IN => next_demux_dr(i), + COMB_next_READ_OUT => demux_next_READ(i), + COMB_READ_IN => current_demux_READ(i), + COMB_DATA_IN => MED_DATA_IN, + COMB_PACKET_NUM_IN => MED_PACKET_NUM_IN, + SYN_DATAREADY_OUT => INT_DATAREADY_OUT(i), + SYN_DATA_OUT => INT_DATA_OUT ((BUS_WIDTH)*(i+1)-1 downto (BUS_WIDTH)*(i)), + SYN_PACKET_NUM_OUT => INT_PACKET_NUM_OUT(2*(i+1)-1 downto 2*i), + SYN_READ_IN => INT_READ_IN(i) + ); + end generate; + if SECURE_MODE = 0 generate + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + INT_DATA_OUT ((BUS_WIDTH)*(i+1)-1 downto (BUS_WIDTH)*(i)) <= (others => '0'); + INT_PACKET_NUM_OUT(2*(i+1)-1 downto 2*i) <= (others => '0'); + INT_DATAREADY_OUT(i) <= '0'; + else + INT_DATA_OUT ((BUS_WIDTH)*(i+1)-1 downto (BUS_WIDTH)*(i)) <= MED_DATA_IN; + INT_PACKET_NUM_OUT(2*(i+1)-1 downto 2*i) <= MED_PACKET_NUM_IN; + INT_DATAREADY_OUT(i) <= next_demux_dr(i); + end if; + end if; + end process; + end generate; end generate; + --current_demux_READ <= INT_READ_IN; + demux_next_READ <= (others => '1'); MED_READ_OUT <= current_MED_READ_OUT; @@ -269,7 +293,7 @@ ARBITER: trb_net_priority_arbiter MUX_SBUF: trb_net16_sbuf - generic map (DATA_WIDTH => BUS_WIDTH+2, VERSION => 0) + generic map (DATA_WIDTH => BUS_WIDTH, NUM_WIDTH => NUM_WIDTH, VERSION => 0) port map ( CLK => CLK, RESET => RESET, @@ -285,7 +309,7 @@ ARBITER: trb_net_priority_arbiter SYN_READ_IN => MED_READ_IN ); - genmux : if MULT_WIDTH /= 3 generate + genmux : if MULT_WIDTH /= 95 generate process (current_INT_READ_OUT, INT_DATA_IN, INT_PACKET_NUM_IN) variable var_mux_buffer : STD_LOGIC_VECTOR (BUS_WIDTH+2-1 downto 0); begin @@ -306,7 +330,7 @@ ARBITER: trb_net_priority_arbiter end process; end generate; - genmux3: if MULT_WIDTH = 3 generate + genmux3: if MULT_WIDTH = 95 generate process (current_INT_READ_OUT, INT_DATA_IN, INT_PACKET_NUM_IN) variable var_mux_buffer : STD_LOGIC_VECTOR (BUS_WIDTH+2-1 downto 0); begin diff --git a/trb_net16_obuf.vhd b/trb_net16_obuf.vhd index 4ffd41f..60595c1 100644 --- a/trb_net16_obuf.vhd +++ b/trb_net16_obuf.vhd @@ -193,7 +193,6 @@ begin next_DATA_COUNT <= CURRENT_DATA_COUNT; next_SEND_ACK_IN <= send_ACK; --BUGBUG: next_SEND_ACK_IN should be a counter (2 may arrive) -- -> no real problem due to same speed of transmission - comb_dataready <= '0'; if (reg_INT_READ_OUT = '1' and INT_DATAREADY_IN = '1') then diff --git a/trb_net16_trigger_receiver_apimbuf_endpoint.vhd b/trb_net16_trigger_receiver_apimbuf_endpoint.vhd index b8a5005..57e9ade 100644 --- a/trb_net16_trigger_receiver_apimbuf_endpoint.vhd +++ b/trb_net16_trigger_receiver_apimbuf_endpoint.vhd @@ -404,43 +404,56 @@ signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MULT_WIDTH-1 downto 0); signal m_READ_OUT : std_logic_vector (2**MULT_WIDTH-1 downto 0); begin - --Connections for data channel - m_DATAREADY_OUT(DAT_CHANNEL*2) <= MED_DAT_INIT_DATAREADY_OUT; - m_DATAREADY_OUT(DAT_CHANNEL*2+1) <= MED_DAT_REPLY_DATAREADY_OUT; - m_DATA_OUT((DAT_CHANNEL*2+1)*BUS_WIDTH-1 downto DAT_CHANNEL*BUS_WIDTH*2) <= MED_DAT_INIT_DATA_OUT; - m_DATA_OUT((DAT_CHANNEL*2+2)*BUS_WIDTH-1 downto (DAT_CHANNEL*2+1)*BUS_WIDTH) <= MED_DAT_REPLY_DATA_OUT; - m_PACKET_NUM_OUT(DAT_CHANNEL*4+1 downto DAT_CHANNEL*4) <= MED_DAT_INIT_PACKET_NUM_OUT; - m_PACKET_NUM_OUT(DAT_CHANNEL*4+3 downto DAT_CHANNEL*4+2) <= MED_DAT_REPLY_PACKET_NUM_OUT; - MED_DAT_INIT_READ_IN <= m_READ_IN(DAT_CHANNEL*2); - MED_DAT_REPLY_READ_IN <= m_READ_IN(DAT_CHANNEL*2+1); - - MED_DAT_INIT_DATAREADY_IN <= m_DATAREADY_IN(DAT_CHANNEL*2); - MED_DAT_REPLY_DATAREADY_IN <= m_DATAREADY_IN(DAT_CHANNEL*2+1); - MED_DAT_INIT_DATA_IN <= m_DATA_IN((DAT_CHANNEL*2+1)*BUS_WIDTH-1 downto DAT_CHANNEL*BUS_WIDTH*2); - MED_DAT_REPLY_DATA_IN <= m_DATA_IN((DAT_CHANNEL*2+2)*BUS_WIDTH-1 downto (DAT_CHANNEL*2+1)*BUS_WIDTH); - MED_DAT_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(DAT_CHANNEL*4+1 downto DAT_CHANNEL*4); - MED_DAT_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(DAT_CHANNEL*4+3 downto DAT_CHANNEL*4+2); - m_READ_OUT(DAT_CHANNEL*2) <= MED_DAT_INIT_READ_OUT; - m_READ_OUT(DAT_CHANNEL*2+1) <= MED_DAT_REPLY_READ_OUT; - - --Connections for trigger channel - m_DATAREADY_OUT(TRG_CHANNEL*2) <= MED_TRG_INIT_DATAREADY_OUT; - m_DATAREADY_OUT(TRG_CHANNEL*2+1) <= MED_TRG_REPLY_DATAREADY_OUT; - m_DATA_OUT((TRG_CHANNEL*2+1)*BUS_WIDTH-1 downto TRG_CHANNEL*BUS_WIDTH*2) <= MED_TRG_INIT_DATA_OUT; - m_DATA_OUT((TRG_CHANNEL*2+2)*BUS_WIDTH-1 downto (TRG_CHANNEL*2+1)*BUS_WIDTH) <= MED_TRG_REPLY_DATA_OUT; - m_PACKET_NUM_OUT(TRG_CHANNEL*4+1 downto TRG_CHANNEL*4) <= MED_TRG_INIT_PACKET_NUM_OUT; - m_PACKET_NUM_OUT(TRG_CHANNEL*4+3 downto TRG_CHANNEL*4+2) <= MED_TRG_REPLY_PACKET_NUM_OUT; - MED_TRG_INIT_READ_IN <= m_READ_IN(TRG_CHANNEL*2); - MED_TRG_REPLY_READ_IN <= m_READ_IN(TRG_CHANNEL*2+1); - - MED_TRG_INIT_DATAREADY_IN <= m_DATAREADY_IN(TRG_CHANNEL*2); - MED_TRG_REPLY_DATAREADY_IN <= m_DATAREADY_IN(TRG_CHANNEL*2+1); - MED_TRG_INIT_DATA_IN <= m_DATA_IN((TRG_CHANNEL*2+1)*BUS_WIDTH-1 downto TRG_CHANNEL*BUS_WIDTH*2); - MED_TRG_REPLY_DATA_IN <= m_DATA_IN((TRG_CHANNEL*2+2)*BUS_WIDTH-1 downto (TRG_CHANNEL*2+1)*BUS_WIDTH); - MED_TRG_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(TRG_CHANNEL*4+1 downto TRG_CHANNEL*4); - MED_TRG_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(TRG_CHANNEL*4+3 downto TRG_CHANNEL*4+2); - m_READ_OUT(TRG_CHANNEL*2) <= MED_TRG_INIT_READ_OUT; - m_READ_OUT(TRG_CHANNEL*2+1) <= MED_TRG_REPLY_READ_OUT; + + --Connections for data and trigger channel + genmuxcon : for i in 0 to 2**(MULT_WIDTH-1)-1 generate + gendat: if i = DAT_CHANNEL generate + m_DATAREADY_OUT(i*2) <= MED_DAT_INIT_DATAREADY_OUT; + m_DATAREADY_OUT(i*2+1) <= MED_DAT_REPLY_DATAREADY_OUT; + m_DATA_OUT((i*2+1)*BUS_WIDTH-1 downto i*BUS_WIDTH*2) <= MED_DAT_INIT_DATA_OUT; + m_DATA_OUT((i*2+2)*BUS_WIDTH-1 downto (i*2+1)*BUS_WIDTH) <= MED_DAT_REPLY_DATA_OUT; + m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_DAT_INIT_PACKET_NUM_OUT; + m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_DAT_REPLY_PACKET_NUM_OUT; + MED_DAT_INIT_READ_IN <= m_READ_IN(i*2); + MED_DAT_REPLY_READ_IN <= m_READ_IN(i*2+1); + MED_DAT_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2); + MED_DAT_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1); + MED_DAT_INIT_DATA_IN <= m_DATA_IN((i*2+1)*BUS_WIDTH-1 downto i*BUS_WIDTH*2); + MED_DAT_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*BUS_WIDTH-1 downto (i*2+1)*BUS_WIDTH); + MED_DAT_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2); + MED_DAT_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2); + m_READ_OUT(i*2) <= MED_DAT_INIT_READ_OUT; + m_READ_OUT(i*2+1) <= MED_DAT_REPLY_READ_OUT; + end generate; + gentrg: if i = TRG_CHANNEL generate + m_DATAREADY_OUT(i*2) <= MED_TRG_INIT_DATAREADY_OUT; + m_DATAREADY_OUT(i*2+1) <= MED_TRG_REPLY_DATAREADY_OUT; + m_DATA_OUT((i*2+1)*BUS_WIDTH-1 downto i*BUS_WIDTH*2) <= MED_TRG_INIT_DATA_OUT; + m_DATA_OUT((i*2+2)*BUS_WIDTH-1 downto (i*2+1)*BUS_WIDTH) <= MED_TRG_REPLY_DATA_OUT; + m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_TRG_INIT_PACKET_NUM_OUT; + m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_TRG_REPLY_PACKET_NUM_OUT; + MED_TRG_INIT_READ_IN <= m_READ_IN(i*2); + MED_TRG_REPLY_READ_IN <= m_READ_IN(i*2+1); + MED_TRG_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2); + MED_TRG_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1); + MED_TRG_INIT_DATA_IN <= m_DATA_IN((i*2+1)*BUS_WIDTH-1 downto i*BUS_WIDTH*2); + MED_TRG_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*BUS_WIDTH-1 downto (i*2+1)*BUS_WIDTH); + MED_TRG_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2); + MED_TRG_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2); + m_READ_OUT(i*2) <= MED_TRG_INIT_READ_OUT; + m_READ_OUT(i*2+1) <= MED_TRG_REPLY_READ_OUT; + end generate; + genelse: if i /= DAT_CHANNEL and i /= TRG_CHANNEL generate + m_DATAREADY_OUT(i*2) <= '0'; + m_DATAREADY_OUT(i*2+1) <= '0'; + m_DATA_OUT((i*2+1)*BUS_WIDTH-1 downto i*BUS_WIDTH*2) <= (others => '0'); + m_DATA_OUT((i*2+2)*BUS_WIDTH-1 downto (i*2+1)*BUS_WIDTH) <= (others => '0'); + m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= (others => '0'); + m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= (others => '0'); + m_READ_OUT(i*2) <= '0'; + m_READ_OUT(i*2+1) <= '0'; + end generate; + end generate; gen_actapi: if API_TYPE = 1 generate DAT_ACTIVE_API: trb_net16_base_api diff --git a/trb_net16_trigger_receiver_endpoint.vhd b/trb_net16_trigger_receiver_endpoint.vhd index 38d5436..15cbc75 100644 --- a/trb_net16_trigger_receiver_endpoint.vhd +++ b/trb_net16_trigger_receiver_endpoint.vhd @@ -239,37 +239,51 @@ architecture trb_net16_trigger_receiver_endpoint_arch of trb_net16_trigger_recei signal MED_REPLY_PACKET_NUM_IN : std_logic_vector (1 downto 0); signal MED_REPLY_READ_OUT : std_logic; - signal m_DATAREADY_OUT : std_logic_vector (1 downto 0); - signal m_DATA_OUT : std_logic_vector (2**MULT_WIDTH*BUS_WIDTH-1 downto 0); - signal m_PACKET_NUM_OUT: std_logic_vector (2**MULT_WIDTH*NUM_WIDTH-1 downto 0); - signal m_READ_IN : std_logic_vector (1 downto 0); - - signal m_DATAREADY_IN : std_logic_vector (1 downto 0); - signal m_DATA_IN : std_logic_vector (2**MULT_WIDTH*BUS_WIDTH-1 downto 0); - signal m_PACKET_NUM_IN : std_logic_vector (2**MULT_WIDTH*NUM_WIDTH-1 downto 0); - signal m_READ_OUT : std_logic_vector (1 downto 0); +signal m_DATAREADY_OUT : std_logic_vector (2**MULT_WIDTH-1 downto 0); +signal m_DATA_OUT : std_logic_vector (BUS_WIDTH*2**MULT_WIDTH-1 downto 0); +signal m_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH*2**MULT_WIDTH-1 downto 0); +signal m_READ_IN : std_logic_vector (2**MULT_WIDTH-1 downto 0); + +signal m_DATAREADY_IN : std_logic_vector (2**MULT_WIDTH-1 downto 0); +signal m_DATA_IN : std_logic_vector (BUS_WIDTH**MULT_WIDTH-1 downto 0); +signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MULT_WIDTH-1 downto 0); +signal m_READ_OUT : std_logic_vector (2**MULT_WIDTH-1 downto 0); begin ------------------------------------------------- --Connection between multiplexer and iobuf ------------------------------------------------- - m_DATAREADY_OUT(TRG_CHANNEL*2) <= MED_INIT_DATAREADY_OUT; - m_DATAREADY_OUT(TRG_CHANNEL*2+1) <= MED_REPLY_DATAREADY_OUT; - m_DATA_OUT(BUS_WIDTH*(TRG_CHANNEL+1)-1 downto BUS_WIDTH*TRG_CHANNEL) <= MED_INIT_DATA_OUT; - m_DATA_OUT(BUS_WIDTH*(TRG_CHANNEL+2)-1 downto BUS_WIDTH*(TRG_CHANNEL+1)) <= MED_REPLY_DATA_OUT; - m_PACKET_NUM_OUT((TRG_CHANNEL+1)*2-1 downto TRG_CHANNEL*2) <= MED_INIT_PACKET_NUM_OUT; - m_PACKET_NUM_OUT((TRG_CHANNEL+2)*2-1 downto (TRG_CHANNEL+1)*2) <= MED_REPLY_PACKET_NUM_OUT; - MED_INIT_READ_IN <= m_READ_IN(TRG_CHANNEL*2); - MED_REPLY_READ_IN <= m_READ_IN(TRG_CHANNEL*2+1); - - MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(TRG_CHANNEL*2); - MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(TRG_CHANNEL*2+1); - MED_INIT_DATA_IN <= m_DATA_IN(BUS_WIDTH*(TRG_CHANNEL+1)-1 downto BUS_WIDTH*TRG_CHANNEL); - MED_REPLY_DATA_IN <= m_DATA_IN(BUS_WIDTH*(TRG_CHANNEL+2)-1 downto BUS_WIDTH*(TRG_CHANNEL+1)); - MED_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN((TRG_CHANNEL+1)*2-1 downto TRG_CHANNEL*2); - MED_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN((TRG_CHANNEL+2)*2-1 downto (TRG_CHANNEL+1)*2); - m_READ_OUT(TRG_CHANNEL*2) <= MED_INIT_READ_OUT; - m_READ_OUT(TRG_CHANNEL*2+1) <= MED_REPLY_READ_OUT; + --Connections for data and trigger channel + genmuxcon : for i in 0 to 2**(MULT_WIDTH-1)-1 generate + gentrg: if i = TRG_CHANNEL generate + m_DATAREADY_OUT(i*2) <= MED_INIT_DATAREADY_OUT; + m_DATAREADY_OUT(i*2+1) <= MED_REPLY_DATAREADY_OUT; + m_DATA_OUT((i*2+1)*BUS_WIDTH-1 downto i*BUS_WIDTH*2) <= MED_INIT_DATA_OUT; + m_DATA_OUT((i*2+2)*BUS_WIDTH-1 downto (i*2+1)*BUS_WIDTH) <= MED_REPLY_DATA_OUT; + m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_INIT_PACKET_NUM_OUT; + m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_REPLY_PACKET_NUM_OUT; + MED_INIT_READ_IN <= m_READ_IN(i*2); + MED_REPLY_READ_IN <= m_READ_IN(i*2+1); + MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2); + MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1); + MED_INIT_DATA_IN <= m_DATA_IN((i*2+1)*BUS_WIDTH-1 downto i*BUS_WIDTH*2); + MED_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*BUS_WIDTH-1 downto (i*2+1)*BUS_WIDTH); + MED_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2); + MED_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2); + m_READ_OUT(i*2) <= MED_INIT_READ_OUT; + m_READ_OUT(i*2+1) <= MED_REPLY_READ_OUT; + end generate; + genelse: if i /= TRG_CHANNEL generate + m_DATAREADY_OUT(i*2) <= '0'; + m_DATAREADY_OUT(i*2+1) <= '0'; + m_DATA_OUT((i*2+1)*BUS_WIDTH-1 downto i*BUS_WIDTH*2) <= (others => '0'); + m_DATA_OUT((i*2+2)*BUS_WIDTH-1 downto (i*2+1)*BUS_WIDTH) <= (others => '0'); + m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= (others => '0'); + m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= (others => '0'); + m_READ_OUT(i*2) <= '0'; + m_READ_OUT(i*2+1) <= '0'; + end generate; + end generate; IOBUF: trb_net16_iobuf port map ( diff --git a/xilinx/trb_net_fifo_arch.vhd b/xilinx/trb_net_fifo_arch.vhd index dc4f70a..5e82f3c 100644 --- a/xilinx/trb_net_fifo_arch.vhd +++ b/xilinx/trb_net_fifo_arch.vhd @@ -12,7 +12,18 @@ use work.trb_net_std.all; architecture arch_trb_net_fifo of trb_net_fifo is - + component trb_net16_bram_fifo is + port (clock_in: IN std_logic; + read_enable_in: IN std_logic; + write_enable_in: IN std_logic; + write_data_in: IN std_logic_vector(17 downto 0); + fifo_gsr_in: IN std_logic; + read_data_out: OUT std_logic_vector(17 downto 0); + full_out: OUT std_logic; + empty_out: OUT std_logic; + fifocount_out: OUT std_logic_vector(3 downto 0)); + end component; + component shift_lut_x16 generic ( ADDRESS_WIDTH : integer := 0 @@ -35,131 +46,153 @@ architecture arch_trb_net_fifo of trb_net_fifo is signal current_FULL, next_FULL : std_logic; signal current_EMPTY, next_EMPTY : std_logic; signal do_shift, do_shift_internal : std_logic; + signal fifocount : std_logic_vector(3 downto 0); begin - FULL_OUT <= current_FULL; - EMPTY_OUT <= current_EMPTY; - do_shift <= do_shift_internal and CLK_EN; - + gen_shiftreg : if DEPTH < 4 or WIDTH /= 18 generate --- generate the shift registers + FULL_OUT <= current_FULL; + EMPTY_OUT <= current_EMPTY; + do_shift <= do_shift_internal and CLK_EN; - inst_SRLC256E_MACRO : for i in 0 to (WIDTH - 1) generate - U1 : shift_lut_x16 - generic map ( - ADDRESS_WIDTH => DEPTH - 3 - ) - port map ( - D => DATA_IN(i), - CE => do_shift, - CLK => CLK, - A => real_ADDRESS_SRL(DEPTH downto 0), - Q => next_DOUT(i)); - end generate; - - reg_counter: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - current_ADDRESS_SRL <= (others => '0'); - elsif CLK_EN = '1' then - current_ADDRESS_SRL <= next_ADDRESS_SRL; - else - current_ADDRESS_SRL <= current_ADDRESS_SRL; + + -- generate the shift registers + + inst_SRLC256E_MACRO : for i in 0 to (WIDTH - 1) generate + U1 : shift_lut_x16 + generic map ( + ADDRESS_WIDTH => DEPTH - 3 + ) + port map ( + D => DATA_IN(i), + CE => do_shift, + CLK => CLK, + A => real_ADDRESS_SRL(DEPTH downto 0), + Q => next_DOUT(i)); + end generate; + + reg_counter: process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + current_ADDRESS_SRL <= (others => '0'); + elsif CLK_EN = '1' then + current_ADDRESS_SRL <= next_ADDRESS_SRL; + else + current_ADDRESS_SRL <= current_ADDRESS_SRL; + end if; end if; - end if; - end process; - --- adress logic - comb_counter: process(WRITE_ENABLE_IN, READ_ENABLE_IN, current_ADDRESS_SRL, - current_EMPTY, current_FULL) - begin --- no activity - if WRITE_ENABLE_IN = '0' and READ_ENABLE_IN = '0' then - do_shift_internal <= '0'; - next_ADDRESS_SRL <= current_ADDRESS_SRL; - real_ADDRESS_SRL <= current_ADDRESS_SRL - 1; --- read from FIFO - elsif WRITE_ENABLE_IN = '0' and READ_ENABLE_IN = '1' and current_EMPTY = '0' then - do_shift_internal <= '0'; - next_ADDRESS_SRL <= current_ADDRESS_SRL - 1; - real_ADDRESS_SRL <= current_ADDRESS_SRL - 2; --- write into FIFO - elsif WRITE_ENABLE_IN = '1' and READ_ENABLE_IN = '0' and current_FULL = '0' then - do_shift_internal <= '1'; - next_ADDRESS_SRL <= current_ADDRESS_SRL + 1; - real_ADDRESS_SRL <= current_ADDRESS_SRL - 1; --- read and write can be done in all cases - elsif WRITE_ENABLE_IN = '1' and READ_ENABLE_IN = '1' then - do_shift_internal <= '1'; - next_ADDRESS_SRL <= current_ADDRESS_SRL; - real_ADDRESS_SRL <= current_ADDRESS_SRL - 2; - else - do_shift_internal <= '0'; + end process; + + -- adress logic + comb_counter: process(WRITE_ENABLE_IN, READ_ENABLE_IN, current_ADDRESS_SRL, + current_EMPTY, current_FULL) + begin + do_shift_internal <= WRITE_ENABLE_IN and not current_FULL; next_ADDRESS_SRL <= current_ADDRESS_SRL; real_ADDRESS_SRL <= current_ADDRESS_SRL - 1; + + -- no activity + if WRITE_ENABLE_IN = '0' and READ_ENABLE_IN = '0' then + next_ADDRESS_SRL <= current_ADDRESS_SRL; + real_ADDRESS_SRL <= current_ADDRESS_SRL - 1; + -- read from FIFO + elsif WRITE_ENABLE_IN = '0' and READ_ENABLE_IN = '1' then + if current_EMPTY = '0' then + next_ADDRESS_SRL <= current_ADDRESS_SRL - 1; + real_ADDRESS_SRL <= current_ADDRESS_SRL - 2; + end if; + -- write into FIFO + elsif WRITE_ENABLE_IN = '1' and READ_ENABLE_IN = '0' then + if current_FULL = '0' then + next_ADDRESS_SRL <= current_ADDRESS_SRL + 1; + real_ADDRESS_SRL <= current_ADDRESS_SRL - 1; + end if; + -- read and write can be done in all cases + elsif WRITE_ENABLE_IN = '1' and READ_ENABLE_IN = '1' then + next_ADDRESS_SRL <= current_ADDRESS_SRL; + real_ADDRESS_SRL <= current_ADDRESS_SRL - 2; end if; end process; - --- registered read from FIFO - reg_output: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - current_DOUT <= (others => '0'); - elsif CLK_EN = '1' then - if current_EMPTY = '1' or real_ADDRESS_SRL(DEPTH+1) = '1' then - current_DOUT <= DATA_IN; + + + -- registered read from FIFO + reg_output: process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + current_DOUT <= (others => '0'); + elsif CLK_EN = '1' then + if current_EMPTY = '1' or real_ADDRESS_SRL(DEPTH+1) = '1' then + current_DOUT <= DATA_IN; + else + current_DOUT <= next_DOUT; + end if; else - current_DOUT <= next_DOUT; + current_DOUT <= current_DOUT; end if; - else - current_DOUT <= current_DOUT; - end if; - end if; - end process; + end if; + end process; + + -- Comparator Block + next_FULL <= next_ADDRESS_SRL(DEPTH+1); + -- Empty flag is generated when reading from the last location + next_EMPTY <= '1' when (next_ADDRESS_SRL(DEPTH+1 downto 0) = 0) else '0'; + + reg_empty: process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + current_EMPTY <= '1'; + current_FULL <= '0'; + elsif CLK_EN = '1' then + current_EMPTY <= next_EMPTY; + current_FULL <= next_FULL; + else + current_EMPTY <= current_EMPTY; + current_FULL <= current_FULL; + end if; + end if; + end process; + + FULL_OUT <= current_FULL; + EMPTY_OUT <= current_EMPTY; + DATA_OUT <= current_DOUT; + + + -- generate the real depth which is at least 3 + -- 0 -> 2 + -- 1 -> 4 + -- 2 -> 8 + -- 3 -> 16 + CHECK_DEPTH1: if DEPTH>=3 generate + DEPTH_OUT <= std_logic_vector(to_unsigned(DEPTH,8)); + end generate CHECK_DEPTH1; + CHECK_DEPTH2: if DEPTH<3 generate + DEPTH_OUT <= x"03"; + end generate CHECK_DEPTH2; + end generate; --- Comparator Block - next_FULL <= next_ADDRESS_SRL(DEPTH+1); - -- Empty flag is generated when reading from the last location - next_EMPTY <= not or_all(next_ADDRESS_SRL(DEPTH+1 downto 0)); - reg_empty: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - current_EMPTY <= '1'; - current_FULL <= '0'; - elsif CLK_EN = '1' then - current_EMPTY <= next_EMPTY; - current_FULL <= next_FULL; - else - current_EMPTY <= current_EMPTY; - current_FULL <= current_FULL; - - end if; - end if; - end process; - FULL_OUT <= current_FULL; - EMPTY_OUT <= current_EMPTY; - DATA_OUT <= current_DOUT; + gen_BRAM : if DEPTH > 3 and WIDTH = 18 generate + bram_fifo:trb_net16_bram_fifo + port map ( + clock_in => CLK, + read_enable_in => READ_ENABLE_IN, + write_enable_in => WRITE_ENABLE_IN, + write_data_in => DATA_IN, + fifo_gsr_in => RESET, + read_data_out => DATA_OUT, + full_out => FULL_OUT, + empty_out => EMPTY_OUT, + fifocount_out => fifocount + ); + DEPTH_OUT <= (others => '1'); + end generate; - - -- generate the real depth which is at least 3 - -- 0 -> 2 - -- 1 -> 4 - -- 2 -> 8 - -- 3 -> 16 - CHECK_DEPTH1: if DEPTH>=3 generate - DEPTH_OUT <= std_logic_vector(to_unsigned(DEPTH,8)); - end generate CHECK_DEPTH1; - CHECK_DEPTH2: if DEPTH<3 generate - DEPTH_OUT <= x"03"; - end generate CHECK_DEPTH2; - -end arch_trb_net_fifo; +end arch_trb_net_fifo; -- 2.43.0