From 400511d040e19544ff732c713fb9d93d7c7ae1de Mon Sep 17 00:00:00 2001 From: Thomas Gessler Date: Mon, 28 Sep 2020 17:45:58 +0200 Subject: [PATCH] Adapt to single-MGT scheme --- endpoint_test/endpoint_test.xpr | 38 +- endpoint_test/src/endpoint_test.vhd | 118 +- hub_test/constrs/debug.xdc | 132 +- hub_test/constrs/debug_serdes.xdc | 28 +- hub_test/constrs/hub_test.xdc | 25 +- hub_test/hub_test.xpr | 58 +- hub_test/ip/clk_wiz_1/clk_wiz_1.xci | 710 ----- hub_test/ip/clk_wiz_1/clk_wiz_1.xml | 4497 --------------------------- hub_test/src/hub_test.vhd | 380 ++- 9 files changed, 383 insertions(+), 5603 deletions(-) delete mode 100644 hub_test/ip/clk_wiz_1/clk_wiz_1.xci delete mode 100644 hub_test/ip/clk_wiz_1/clk_wiz_1.xml diff --git a/endpoint_test/endpoint_test.xpr b/endpoint_test/endpoint_test.xpr index 37a721b..8bd4fee 100644 --- a/endpoint_test/endpoint_test.xpr +++ b/endpoint_test/endpoint_test.xpr @@ -115,42 +115,28 @@ - + - - - - - - - - - - - - - - - + - + - + @@ -193,7 +179,7 @@ - + @@ -205,7 +191,7 @@ - + @@ -367,12 +353,6 @@ - - - - - - @@ -529,6 +509,12 @@ + + + + + + diff --git a/endpoint_test/src/endpoint_test.vhd b/endpoint_test/src/endpoint_test.vhd index f90789a..1daf5fd 100644 --- a/endpoint_test/src/endpoint_test.vhd +++ b/endpoint_test/src/endpoint_test.vhd @@ -13,10 +13,10 @@ entity endpoint_test is MGTREFCLK_P : in std_logic; MGTREFCLK_N : in std_logic; - RXN : in std_logic_vector(3 downto 0); - RXP : in std_logic_vector(3 downto 0); - TXN : out std_logic_vector(3 downto 0); - TXP : out std_logic_vector(3 downto 0); + RXN : in std_logic; + RXP : in std_logic; + TXN : out std_logic; + TXP : out std_logic; CLK_200_P : in std_logic; CLK_200_N : in std_logic; @@ -49,6 +49,8 @@ architecture behavioral of endpoint_test is signal sysclk_locked : std_logic; signal mgtrefclk : std_logic; + signal mgtrefclk_hrow : std_logic; + signal mgtrefclk_bufg : std_logic; signal initial_clear_timer : unsigned(27 downto 0) := (others => '0'); signal initial_clear_n : std_logic := '0'; @@ -66,8 +68,6 @@ architecture behavioral of endpoint_test is signal med2int_i : MED2INT; signal int2med_i : INT2MED; - signal med2int_unused : med2int_array_t(0 to 2); - signal int2med_unused : int2med_array_t(0 to 2); signal ctrlbus_rx_i : CTRLBUS_RX; signal bustools_rx : CTRLBUS_RX; @@ -83,9 +83,9 @@ architecture behavioral of endpoint_test is signal readout_tx_i : READOUT_TX; - signal txpmaresetdone : std_logic_vector(3 downto 0); + signal txpmaresetdone : std_logic; signal userclk_tx_reset : std_logic; - signal txoutclk : std_logic_vector(3 downto 0); + signal txoutclk : std_logic; signal usrclk_active_meta : std_logic := '0'; signal usrclk_active : std_logic := '0'; @@ -99,9 +99,6 @@ architecture behavioral of endpoint_test is signal usrclk_mmcm_fb : std_logic; signal usrclk : std_logic; signal usrclk_double : std_logic; - - signal usrclk_vector : std_logic_vector(3 downto 0); - signal usrclk_double_vector : std_logic_vector(3 downto 0); begin MPOD_RESET_N <= "1111"; @@ -116,12 +113,28 @@ begin ); THE_MGTREFCLK0_X0Y3 : IBUFDS_GTE3 + generic map ( + REFCLK_EN_TX_PATH => '0', + REFCLK_HROW_CK_SEL => "00", + REFCLK_ICNTL_RX => "00" + ) port map ( I => MGTREFCLK_P, IB => MGTREFCLK_N, CEB => '0', O => mgtrefclk, - ODIV2 => open + ODIV2 => mgtrefclk_hrow + ); + + BUFG_GT_MGTREFCLK0_X0Y3 : BUFG_GT + port map ( + O => mgtrefclk_bufg, + CE => '1', + CEMASK => '0', + CLR => '0', + CLRMASK => '0', + DIV => "000", + I => mgtrefclk_hrow ); THE_VIO : vio_0 @@ -164,52 +177,47 @@ begin DEBUG_OUT => open ); - usrclk_vector <= usrclk & usrclk & usrclk & usrclk; - usrclk_double_vector <= usrclk_double & usrclk_double & usrclk_double - & usrclk_double; - THE_MEDIA_INTERFACE : entity work.med_xcku_sfp_sync_4 + THE_UPLINK : entity work.med_xcku_sfp_sync generic map ( - IS_SYNC_SLAVE => (c_YES, c_NO, c_NO, c_NO), - IS_USED => (c_YES, c_NO, c_NO, c_NO) + IS_SYNC_SLAVE => c_YES, + LINE_RATE_KBPS => 2000000, + REFCLK_FREQ_HZ => 100000000 ) port map ( - SYSCLK => sysclk_100, - CLK_200 => sysclk_200, - GTREFCLK => mgtrefclk, - RXOUTCLK => open, - TXOUTCLK => txoutclk, - RXUSRCLK => usrclk_vector, - RXUSRCLK_DOUBLE => usrclk_double_vector, - TXUSRCLK => usrclk_vector, - TXUSRCLK_DOUBLE => usrclk_double_vector, - RXUSRCLK_ACTIVE => usrclk_active, - TXUSRCLK_ACTIVE => usrclk_active, - RXPMARESETDONE => open, - TXPMARESETDONE => txpmaresetdone, - RESET => reset, - CLEAR => clear, - RXN => RXN, - RXP => RXP, - TXN => TXN, - TXP => TXP, - MEDIA_MED2INT(0) => med2int_i, - MEDIA_MED2INT(1 to 3) => med2int_unused, - MEDIA_INT2MED(0) => int2med_i, - MEDIA_INT2MED(1 to 3) => int2med_unused, - RX_DLM => open, - RX_DLM_WORD => open, - TX_DLM => open, - TX_DLM_WORD => open, - SD_LOS_IN => "0000", - SD_TXDIS_OUT => open, - BUS_RX => bussci_rx, - BUS_TX => bussci_tx, - STAT_DEBUG => open, - CTRL_DEBUG => open + SYSCLK => sysclk_100, + CLK_100 => sysclk_100, + GTREFCLK => mgtrefclk, + GTREFCLK_BUFG => mgtrefclk_bufg, + RXOUTCLK => open, + TXOUTCLK => txoutclk, + RXUSRCLK => usrclk, + RXUSRCLK_DOUBLE => usrclk_double, + TXUSRCLK => usrclk, + TXUSRCLK_DOUBLE => usrclk_double, + RXUSRCLK_ACTIVE => usrclk_active, + TXUSRCLK_ACTIVE => usrclk_active, + RXPMARESETDONE => open, + TXPMARESETDONE => txpmaresetdone, + RESET => reset, + CLEAR => clear, + RXN => RXN, + RXP => RXP, + TXN => TXN, + TXP => TXP, + MEDIA_MED2INT => med2int_i, + MEDIA_INT2MED => int2med_i, + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => '0', + TX_DLM_WORD => x"00", + SD_LOS_IN => '0', + SD_TXDIS_OUT => open, + STAT_DEBUG => open, + CTRL_DEBUG => (others => '0') ); - userclk_tx_reset <= not txpmaresetdone(0); + userclk_tx_reset <= not txpmaresetdone; bufg_gt_usrclk_inst : BUFG_GT port map ( @@ -219,7 +227,7 @@ begin CLR => userclk_tx_reset, CLRMASK => '0', DIV => "000", - I => txoutclk(0) + I => txoutclk ); -- Indicate active helper block functionality when the BUFG_GT divider is @@ -365,15 +373,19 @@ begin begin if rising_edge(sysclk_100) then bustools_tx.data <= (others => '0'); + bussci_tx.data <= (others => '0'); bustc_tx.data <= (others => '0'); bustools_tx.unknown <= bustools_rx.read or bustools_rx.write; + bussci_tx.unknown <= bussci_rx.read or bussci_rx.write; bustc_tx.unknown <= bustc_rx.read or bustc_rx.write; bustools_tx.ack <= '0'; + bussci_tx.ack <= '0'; bustc_tx.ack <= '0'; bustools_tx.nack <= '0'; + bussci_tx.nack <= '0'; bustc_tx.nack <= '0'; end if; end process TERMINATE_UNUSED; diff --git a/hub_test/constrs/debug.xdc b/hub_test/constrs/debug.xdc index b7902be..0e3b5ec 100644 --- a/hub_test/constrs/debug.xdc +++ b/hub_test/constrs/debug.xdc @@ -23,44 +23,48 @@ set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property port_width 1 [get_debug_ports u_ila_0/clk] connect_debug_port u_ila_0/clk [get_nets [list THE_SYSCLK/inst/clk_out1]] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] -set_property port_width 1 [get_debug_ports u_ila_0/probe0] -connect_debug_port u_ila_0/probe0 [get_nets [list {hub_data_active[4]}]] +set_property port_width 72 [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {hub_data_seqnmbr[0]} {hub_data_seqnmbr[1]} {hub_data_seqnmbr[2]} {hub_data_seqnmbr[3]} {hub_data_seqnmbr[4]} {hub_data_seqnmbr[5]} {hub_data_seqnmbr[6]} {hub_data_seqnmbr[7]} {hub_data_seqnmbr[8]} {hub_data_seqnmbr[9]} {hub_data_seqnmbr[10]} {hub_data_seqnmbr[11]} {hub_data_seqnmbr[12]} {hub_data_seqnmbr[13]} {hub_data_seqnmbr[14]} {hub_data_seqnmbr[15]} {hub_data_seqnmbr[16]} {hub_data_seqnmbr[17]} {hub_data_seqnmbr[18]} {hub_data_seqnmbr[19]} {hub_data_seqnmbr[20]} {hub_data_seqnmbr[21]} {hub_data_seqnmbr[22]} {hub_data_seqnmbr[23]} {hub_data_seqnmbr[24]} {hub_data_seqnmbr[25]} {hub_data_seqnmbr[26]} {hub_data_seqnmbr[27]} {hub_data_seqnmbr[28]} {hub_data_seqnmbr[29]} {hub_data_seqnmbr[30]} {hub_data_seqnmbr[31]} {hub_data_seqnmbr[32]} {hub_data_seqnmbr[33]} {hub_data_seqnmbr[34]} {hub_data_seqnmbr[35]} {hub_data_seqnmbr[36]} {hub_data_seqnmbr[37]} {hub_data_seqnmbr[38]} {hub_data_seqnmbr[39]} {hub_data_seqnmbr[40]} {hub_data_seqnmbr[41]} {hub_data_seqnmbr[42]} {hub_data_seqnmbr[43]} {hub_data_seqnmbr[44]} {hub_data_seqnmbr[45]} {hub_data_seqnmbr[46]} {hub_data_seqnmbr[47]} {hub_data_seqnmbr[48]} {hub_data_seqnmbr[49]} {hub_data_seqnmbr[50]} {hub_data_seqnmbr[51]} {hub_data_seqnmbr[52]} {hub_data_seqnmbr[53]} {hub_data_seqnmbr[54]} {hub_data_seqnmbr[55]} {hub_data_seqnmbr[56]} {hub_data_seqnmbr[57]} {hub_data_seqnmbr[58]} {hub_data_seqnmbr[59]} {hub_data_seqnmbr[60]} {hub_data_seqnmbr[61]} {hub_data_seqnmbr[62]} {hub_data_seqnmbr[63]} {hub_data_seqnmbr[64]} {hub_data_seqnmbr[65]} {hub_data_seqnmbr[66]} {hub_data_seqnmbr[67]} {hub_data_seqnmbr[68]} {hub_data_seqnmbr[69]} {hub_data_seqnmbr[70]} {hub_data_seqnmbr[71]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] -set_property port_width 16 [get_debug_ports u_ila_0/probe1] -connect_debug_port u_ila_0/probe1 [get_nets [list {hub_data_address_sender[64]} {hub_data_address_sender[65]} {hub_data_address_sender[66]} {hub_data_address_sender[67]} {hub_data_address_sender[68]} {hub_data_address_sender[69]} {hub_data_address_sender[70]} {hub_data_address_sender[71]} {hub_data_address_sender[72]} {hub_data_address_sender[73]} {hub_data_address_sender[74]} {hub_data_address_sender[75]} {hub_data_address_sender[76]} {hub_data_address_sender[77]} {hub_data_address_sender[78]} {hub_data_address_sender[79]}]] +set_property port_width 36 [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list {trb_data_tkeep[0]} {trb_data_tkeep[1]} {trb_data_tkeep[2]} {trb_data_tkeep[3]} {trb_data_tkeep[4]} {trb_data_tkeep[5]} {trb_data_tkeep[6]} {trb_data_tkeep[7]} {trb_data_tkeep[8]} {trb_data_tkeep[9]} {trb_data_tkeep[10]} {trb_data_tkeep[11]} {trb_data_tkeep[12]} {trb_data_tkeep[13]} {trb_data_tkeep[14]} {trb_data_tkeep[15]} {trb_data_tkeep[16]} {trb_data_tkeep[17]} {trb_data_tkeep[18]} {trb_data_tkeep[19]} {trb_data_tkeep[20]} {trb_data_tkeep[21]} {trb_data_tkeep[22]} {trb_data_tkeep[23]} {trb_data_tkeep[24]} {trb_data_tkeep[25]} {trb_data_tkeep[26]} {trb_data_tkeep[27]} {trb_data_tkeep[28]} {trb_data_tkeep[29]} {trb_data_tkeep[30]} {trb_data_tkeep[31]} {trb_data_tkeep[32]} {trb_data_tkeep[33]} {trb_data_tkeep[34]} {trb_data_tkeep[35]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] -set_property port_width 16 [get_debug_ports u_ila_0/probe2] -connect_debug_port u_ila_0/probe2 [get_nets [list {hub_data_length[64]} {hub_data_length[65]} {hub_data_length[66]} {hub_data_length[67]} {hub_data_length[68]} {hub_data_length[69]} {hub_data_length[70]} {hub_data_length[71]} {hub_data_length[72]} {hub_data_length[73]} {hub_data_length[74]} {hub_data_length[75]} {hub_data_length[76]} {hub_data_length[77]} {hub_data_length[78]} {hub_data_length[79]}]] +set_property port_width 144 [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list {hub_data_length[0]} {hub_data_length[1]} {hub_data_length[2]} {hub_data_length[3]} {hub_data_length[4]} {hub_data_length[5]} {hub_data_length[6]} {hub_data_length[7]} {hub_data_length[8]} {hub_data_length[9]} {hub_data_length[10]} {hub_data_length[11]} {hub_data_length[12]} {hub_data_length[13]} {hub_data_length[14]} {hub_data_length[15]} {hub_data_length[16]} {hub_data_length[17]} {hub_data_length[18]} {hub_data_length[19]} {hub_data_length[20]} {hub_data_length[21]} {hub_data_length[22]} {hub_data_length[23]} {hub_data_length[24]} {hub_data_length[25]} {hub_data_length[26]} {hub_data_length[27]} {hub_data_length[28]} {hub_data_length[29]} {hub_data_length[30]} {hub_data_length[31]} {hub_data_length[32]} {hub_data_length[33]} {hub_data_length[34]} {hub_data_length[35]} {hub_data_length[36]} {hub_data_length[37]} {hub_data_length[38]} {hub_data_length[39]} {hub_data_length[40]} {hub_data_length[41]} {hub_data_length[42]} {hub_data_length[43]} {hub_data_length[44]} {hub_data_length[45]} {hub_data_length[46]} {hub_data_length[47]} {hub_data_length[48]} {hub_data_length[49]} {hub_data_length[50]} {hub_data_length[51]} {hub_data_length[52]} {hub_data_length[53]} {hub_data_length[54]} {hub_data_length[55]} {hub_data_length[56]} {hub_data_length[57]} {hub_data_length[58]} {hub_data_length[59]} {hub_data_length[60]} {hub_data_length[61]} {hub_data_length[62]} {hub_data_length[63]} {hub_data_length[64]} {hub_data_length[65]} {hub_data_length[66]} {hub_data_length[67]} {hub_data_length[68]} {hub_data_length[69]} {hub_data_length[70]} {hub_data_length[71]} {hub_data_length[72]} {hub_data_length[73]} {hub_data_length[74]} {hub_data_length[75]} {hub_data_length[76]} {hub_data_length[77]} {hub_data_length[78]} {hub_data_length[79]} {hub_data_length[80]} {hub_data_length[81]} {hub_data_length[82]} {hub_data_length[83]} {hub_data_length[84]} {hub_data_length[85]} {hub_data_length[86]} {hub_data_length[87]} {hub_data_length[88]} {hub_data_length[89]} {hub_data_length[90]} {hub_data_length[91]} {hub_data_length[92]} {hub_data_length[93]} {hub_data_length[94]} {hub_data_length[95]} {hub_data_length[96]} {hub_data_length[97]} {hub_data_length[98]} {hub_data_length[99]} {hub_data_length[100]} {hub_data_length[101]} {hub_data_length[102]} {hub_data_length[103]} {hub_data_length[104]} {hub_data_length[105]} {hub_data_length[106]} {hub_data_length[107]} {hub_data_length[108]} {hub_data_length[109]} {hub_data_length[110]} {hub_data_length[111]} {hub_data_length[112]} {hub_data_length[113]} {hub_data_length[114]} {hub_data_length[115]} {hub_data_length[116]} {hub_data_length[117]} {hub_data_length[118]} {hub_data_length[119]} {hub_data_length[120]} {hub_data_length[121]} {hub_data_length[122]} {hub_data_length[123]} {hub_data_length[124]} {hub_data_length[125]} {hub_data_length[126]} {hub_data_length[127]} {hub_data_length[128]} {hub_data_length[129]} {hub_data_length[130]} {hub_data_length[131]} {hub_data_length[132]} {hub_data_length[133]} {hub_data_length[134]} {hub_data_length[135]} {hub_data_length[136]} {hub_data_length[137]} {hub_data_length[138]} {hub_data_length[139]} {hub_data_length[140]} {hub_data_length[141]} {hub_data_length[142]} {hub_data_length[143]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] -set_property port_width 1 [get_debug_ports u_ila_0/probe3] -connect_debug_port u_ila_0/probe3 [get_nets [list {trb_data_tready[4]}]] +set_property port_width 144 [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {hub_data_address_sender[0]} {hub_data_address_sender[1]} {hub_data_address_sender[2]} {hub_data_address_sender[3]} {hub_data_address_sender[4]} {hub_data_address_sender[5]} {hub_data_address_sender[6]} {hub_data_address_sender[7]} {hub_data_address_sender[8]} {hub_data_address_sender[9]} {hub_data_address_sender[10]} {hub_data_address_sender[11]} {hub_data_address_sender[12]} {hub_data_address_sender[13]} {hub_data_address_sender[14]} {hub_data_address_sender[15]} {hub_data_address_sender[16]} {hub_data_address_sender[17]} {hub_data_address_sender[18]} {hub_data_address_sender[19]} {hub_data_address_sender[20]} {hub_data_address_sender[21]} {hub_data_address_sender[22]} {hub_data_address_sender[23]} {hub_data_address_sender[24]} {hub_data_address_sender[25]} {hub_data_address_sender[26]} {hub_data_address_sender[27]} {hub_data_address_sender[28]} {hub_data_address_sender[29]} {hub_data_address_sender[30]} {hub_data_address_sender[31]} {hub_data_address_sender[32]} {hub_data_address_sender[33]} {hub_data_address_sender[34]} {hub_data_address_sender[35]} {hub_data_address_sender[36]} {hub_data_address_sender[37]} {hub_data_address_sender[38]} {hub_data_address_sender[39]} {hub_data_address_sender[40]} {hub_data_address_sender[41]} {hub_data_address_sender[42]} {hub_data_address_sender[43]} {hub_data_address_sender[44]} {hub_data_address_sender[45]} {hub_data_address_sender[46]} {hub_data_address_sender[47]} {hub_data_address_sender[48]} {hub_data_address_sender[49]} {hub_data_address_sender[50]} {hub_data_address_sender[51]} {hub_data_address_sender[52]} {hub_data_address_sender[53]} {hub_data_address_sender[54]} {hub_data_address_sender[55]} {hub_data_address_sender[56]} {hub_data_address_sender[57]} {hub_data_address_sender[58]} {hub_data_address_sender[59]} {hub_data_address_sender[60]} {hub_data_address_sender[61]} {hub_data_address_sender[62]} {hub_data_address_sender[63]} {hub_data_address_sender[64]} {hub_data_address_sender[65]} {hub_data_address_sender[66]} {hub_data_address_sender[67]} {hub_data_address_sender[68]} {hub_data_address_sender[69]} {hub_data_address_sender[70]} {hub_data_address_sender[71]} {hub_data_address_sender[72]} {hub_data_address_sender[73]} {hub_data_address_sender[74]} {hub_data_address_sender[75]} {hub_data_address_sender[76]} {hub_data_address_sender[77]} {hub_data_address_sender[78]} {hub_data_address_sender[79]} {hub_data_address_sender[80]} {hub_data_address_sender[81]} {hub_data_address_sender[82]} {hub_data_address_sender[83]} {hub_data_address_sender[84]} {hub_data_address_sender[85]} {hub_data_address_sender[86]} {hub_data_address_sender[87]} {hub_data_address_sender[88]} {hub_data_address_sender[89]} {hub_data_address_sender[90]} {hub_data_address_sender[91]} {hub_data_address_sender[92]} {hub_data_address_sender[93]} {hub_data_address_sender[94]} {hub_data_address_sender[95]} {hub_data_address_sender[96]} {hub_data_address_sender[97]} {hub_data_address_sender[98]} {hub_data_address_sender[99]} {hub_data_address_sender[100]} {hub_data_address_sender[101]} {hub_data_address_sender[102]} {hub_data_address_sender[103]} {hub_data_address_sender[104]} {hub_data_address_sender[105]} {hub_data_address_sender[106]} {hub_data_address_sender[107]} {hub_data_address_sender[108]} {hub_data_address_sender[109]} {hub_data_address_sender[110]} {hub_data_address_sender[111]} {hub_data_address_sender[112]} {hub_data_address_sender[113]} {hub_data_address_sender[114]} {hub_data_address_sender[115]} {hub_data_address_sender[116]} {hub_data_address_sender[117]} {hub_data_address_sender[118]} {hub_data_address_sender[119]} {hub_data_address_sender[120]} {hub_data_address_sender[121]} {hub_data_address_sender[122]} {hub_data_address_sender[123]} {hub_data_address_sender[124]} {hub_data_address_sender[125]} {hub_data_address_sender[126]} {hub_data_address_sender[127]} {hub_data_address_sender[128]} {hub_data_address_sender[129]} {hub_data_address_sender[130]} {hub_data_address_sender[131]} {hub_data_address_sender[132]} {hub_data_address_sender[133]} {hub_data_address_sender[134]} {hub_data_address_sender[135]} {hub_data_address_sender[136]} {hub_data_address_sender[137]} {hub_data_address_sender[138]} {hub_data_address_sender[139]} {hub_data_address_sender[140]} {hub_data_address_sender[141]} {hub_data_address_sender[142]} {hub_data_address_sender[143]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] -set_property port_width 32 [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list {hub_data_out[128]} {hub_data_out[129]} {hub_data_out[130]} {hub_data_out[131]} {hub_data_out[132]} {hub_data_out[133]} {hub_data_out[134]} {hub_data_out[135]} {hub_data_out[136]} {hub_data_out[137]} {hub_data_out[138]} {hub_data_out[139]} {hub_data_out[140]} {hub_data_out[141]} {hub_data_out[142]} {hub_data_out[143]} {hub_data_out[144]} {hub_data_out[145]} {hub_data_out[146]} {hub_data_out[147]} {hub_data_out[148]} {hub_data_out[149]} {hub_data_out[150]} {hub_data_out[151]} {hub_data_out[152]} {hub_data_out[153]} {hub_data_out[154]} {hub_data_out[155]} {hub_data_out[156]} {hub_data_out[157]} {hub_data_out[158]} {hub_data_out[159]}]] +set_property port_width 288 [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {trb_data_tdata[0]} {trb_data_tdata[1]} {trb_data_tdata[2]} {trb_data_tdata[3]} {trb_data_tdata[4]} {trb_data_tdata[5]} {trb_data_tdata[6]} {trb_data_tdata[7]} {trb_data_tdata[8]} {trb_data_tdata[9]} {trb_data_tdata[10]} {trb_data_tdata[11]} {trb_data_tdata[12]} {trb_data_tdata[13]} {trb_data_tdata[14]} {trb_data_tdata[15]} {trb_data_tdata[16]} {trb_data_tdata[17]} {trb_data_tdata[18]} {trb_data_tdata[19]} {trb_data_tdata[20]} {trb_data_tdata[21]} {trb_data_tdata[22]} {trb_data_tdata[23]} {trb_data_tdata[24]} {trb_data_tdata[25]} {trb_data_tdata[26]} {trb_data_tdata[27]} {trb_data_tdata[28]} {trb_data_tdata[29]} {trb_data_tdata[30]} {trb_data_tdata[31]} {trb_data_tdata[32]} {trb_data_tdata[33]} {trb_data_tdata[34]} {trb_data_tdata[35]} {trb_data_tdata[36]} {trb_data_tdata[37]} {trb_data_tdata[38]} {trb_data_tdata[39]} {trb_data_tdata[40]} {trb_data_tdata[41]} {trb_data_tdata[42]} {trb_data_tdata[43]} {trb_data_tdata[44]} {trb_data_tdata[45]} {trb_data_tdata[46]} {trb_data_tdata[47]} {trb_data_tdata[48]} {trb_data_tdata[49]} {trb_data_tdata[50]} {trb_data_tdata[51]} {trb_data_tdata[52]} {trb_data_tdata[53]} {trb_data_tdata[54]} {trb_data_tdata[55]} {trb_data_tdata[56]} {trb_data_tdata[57]} {trb_data_tdata[58]} {trb_data_tdata[59]} {trb_data_tdata[60]} {trb_data_tdata[61]} {trb_data_tdata[62]} {trb_data_tdata[63]} {trb_data_tdata[64]} {trb_data_tdata[65]} {trb_data_tdata[66]} {trb_data_tdata[67]} {trb_data_tdata[68]} {trb_data_tdata[69]} {trb_data_tdata[70]} {trb_data_tdata[71]} {trb_data_tdata[72]} {trb_data_tdata[73]} {trb_data_tdata[74]} {trb_data_tdata[75]} {trb_data_tdata[76]} {trb_data_tdata[77]} {trb_data_tdata[78]} {trb_data_tdata[79]} {trb_data_tdata[80]} {trb_data_tdata[81]} {trb_data_tdata[82]} {trb_data_tdata[83]} {trb_data_tdata[84]} {trb_data_tdata[85]} {trb_data_tdata[86]} {trb_data_tdata[87]} {trb_data_tdata[88]} {trb_data_tdata[89]} {trb_data_tdata[90]} {trb_data_tdata[91]} {trb_data_tdata[92]} {trb_data_tdata[93]} {trb_data_tdata[94]} {trb_data_tdata[95]} {trb_data_tdata[96]} {trb_data_tdata[97]} {trb_data_tdata[98]} {trb_data_tdata[99]} {trb_data_tdata[100]} {trb_data_tdata[101]} {trb_data_tdata[102]} {trb_data_tdata[103]} {trb_data_tdata[104]} {trb_data_tdata[105]} {trb_data_tdata[106]} {trb_data_tdata[107]} {trb_data_tdata[108]} {trb_data_tdata[109]} {trb_data_tdata[110]} {trb_data_tdata[111]} {trb_data_tdata[112]} {trb_data_tdata[113]} {trb_data_tdata[114]} {trb_data_tdata[115]} {trb_data_tdata[116]} {trb_data_tdata[117]} {trb_data_tdata[118]} {trb_data_tdata[119]} {trb_data_tdata[120]} {trb_data_tdata[121]} {trb_data_tdata[122]} {trb_data_tdata[123]} {trb_data_tdata[124]} {trb_data_tdata[125]} {trb_data_tdata[126]} {trb_data_tdata[127]} {trb_data_tdata[128]} {trb_data_tdata[129]} {trb_data_tdata[130]} {trb_data_tdata[131]} {trb_data_tdata[132]} {trb_data_tdata[133]} {trb_data_tdata[134]} {trb_data_tdata[135]} {trb_data_tdata[136]} {trb_data_tdata[137]} {trb_data_tdata[138]} {trb_data_tdata[139]} {trb_data_tdata[140]} {trb_data_tdata[141]} {trb_data_tdata[142]} {trb_data_tdata[143]} {trb_data_tdata[144]} {trb_data_tdata[145]} {trb_data_tdata[146]} {trb_data_tdata[147]} {trb_data_tdata[148]} {trb_data_tdata[149]} {trb_data_tdata[150]} {trb_data_tdata[151]} {trb_data_tdata[152]} {trb_data_tdata[153]} {trb_data_tdata[154]} {trb_data_tdata[155]} {trb_data_tdata[156]} {trb_data_tdata[157]} {trb_data_tdata[158]} {trb_data_tdata[159]} {trb_data_tdata[160]} {trb_data_tdata[161]} {trb_data_tdata[162]} {trb_data_tdata[163]} {trb_data_tdata[164]} {trb_data_tdata[165]} {trb_data_tdata[166]} {trb_data_tdata[167]} {trb_data_tdata[168]} {trb_data_tdata[169]} {trb_data_tdata[170]} {trb_data_tdata[171]} {trb_data_tdata[172]} {trb_data_tdata[173]} {trb_data_tdata[174]} {trb_data_tdata[175]} {trb_data_tdata[176]} {trb_data_tdata[177]} {trb_data_tdata[178]} {trb_data_tdata[179]} {trb_data_tdata[180]} {trb_data_tdata[181]} {trb_data_tdata[182]} {trb_data_tdata[183]} {trb_data_tdata[184]} {trb_data_tdata[185]} {trb_data_tdata[186]} {trb_data_tdata[187]} {trb_data_tdata[188]} {trb_data_tdata[189]} {trb_data_tdata[190]} {trb_data_tdata[191]} {trb_data_tdata[192]} {trb_data_tdata[193]} {trb_data_tdata[194]} {trb_data_tdata[195]} {trb_data_tdata[196]} {trb_data_tdata[197]} {trb_data_tdata[198]} {trb_data_tdata[199]} {trb_data_tdata[200]} {trb_data_tdata[201]} {trb_data_tdata[202]} {trb_data_tdata[203]} {trb_data_tdata[204]} {trb_data_tdata[205]} {trb_data_tdata[206]} {trb_data_tdata[207]} {trb_data_tdata[208]} {trb_data_tdata[209]} {trb_data_tdata[210]} {trb_data_tdata[211]} {trb_data_tdata[212]} {trb_data_tdata[213]} {trb_data_tdata[214]} {trb_data_tdata[215]} {trb_data_tdata[216]} {trb_data_tdata[217]} {trb_data_tdata[218]} {trb_data_tdata[219]} {trb_data_tdata[220]} {trb_data_tdata[221]} {trb_data_tdata[222]} {trb_data_tdata[223]} {trb_data_tdata[224]} {trb_data_tdata[225]} {trb_data_tdata[226]} {trb_data_tdata[227]} {trb_data_tdata[228]} {trb_data_tdata[229]} {trb_data_tdata[230]} {trb_data_tdata[231]} {trb_data_tdata[232]} {trb_data_tdata[233]} {trb_data_tdata[234]} {trb_data_tdata[235]} {trb_data_tdata[236]} {trb_data_tdata[237]} {trb_data_tdata[238]} {trb_data_tdata[239]} {trb_data_tdata[240]} {trb_data_tdata[241]} {trb_data_tdata[242]} {trb_data_tdata[243]} {trb_data_tdata[244]} {trb_data_tdata[245]} {trb_data_tdata[246]} {trb_data_tdata[247]} {trb_data_tdata[248]} {trb_data_tdata[249]} {trb_data_tdata[250]} {trb_data_tdata[251]} {trb_data_tdata[252]} {trb_data_tdata[253]} {trb_data_tdata[254]} {trb_data_tdata[255]} {trb_data_tdata[256]} {trb_data_tdata[257]} {trb_data_tdata[258]} {trb_data_tdata[259]} {trb_data_tdata[260]} {trb_data_tdata[261]} {trb_data_tdata[262]} {trb_data_tdata[263]} {trb_data_tdata[264]} {trb_data_tdata[265]} {trb_data_tdata[266]} {trb_data_tdata[267]} {trb_data_tdata[268]} {trb_data_tdata[269]} {trb_data_tdata[270]} {trb_data_tdata[271]} {trb_data_tdata[272]} {trb_data_tdata[273]} {trb_data_tdata[274]} {trb_data_tdata[275]} {trb_data_tdata[276]} {trb_data_tdata[277]} {trb_data_tdata[278]} {trb_data_tdata[279]} {trb_data_tdata[280]} {trb_data_tdata[281]} {trb_data_tdata[282]} {trb_data_tdata[283]} {trb_data_tdata[284]} {trb_data_tdata[285]} {trb_data_tdata[286]} {trb_data_tdata[287]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] -set_property port_width 1 [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list {hub_data_ready[4]}]] +set_property port_width 9 [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list {hub_data_ready[0]} {hub_data_ready[1]} {hub_data_ready[2]} {hub_data_ready[3]} {hub_data_ready[4]} {hub_data_ready[5]} {hub_data_ready[6]} {hub_data_ready[7]} {hub_data_ready[8]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] -set_property port_width 1 [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list {trb_data_tlast[4]}]] +set_property port_width 9 [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list {hub_data_active[0]} {hub_data_active[1]} {hub_data_active[2]} {hub_data_active[3]} {hub_data_active[4]} {hub_data_active[5]} {hub_data_active[6]} {hub_data_active[7]} {hub_data_active[8]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] -set_property port_width 1 [get_debug_ports u_ila_0/probe7] -connect_debug_port u_ila_0/probe7 [get_nets [list {trb_data_tvalid[4]}]] +set_property port_width 288 [get_debug_ports u_ila_0/probe7] +connect_debug_port u_ila_0/probe7 [get_nets [list {hub_data_out[0]} {hub_data_out[1]} {hub_data_out[2]} {hub_data_out[3]} {hub_data_out[4]} {hub_data_out[5]} {hub_data_out[6]} {hub_data_out[7]} {hub_data_out[8]} {hub_data_out[9]} {hub_data_out[10]} {hub_data_out[11]} {hub_data_out[12]} {hub_data_out[13]} {hub_data_out[14]} {hub_data_out[15]} {hub_data_out[16]} {hub_data_out[17]} {hub_data_out[18]} {hub_data_out[19]} {hub_data_out[20]} {hub_data_out[21]} {hub_data_out[22]} {hub_data_out[23]} {hub_data_out[24]} {hub_data_out[25]} {hub_data_out[26]} {hub_data_out[27]} {hub_data_out[28]} {hub_data_out[29]} {hub_data_out[30]} {hub_data_out[31]} {hub_data_out[32]} {hub_data_out[33]} {hub_data_out[34]} {hub_data_out[35]} {hub_data_out[36]} {hub_data_out[37]} {hub_data_out[38]} {hub_data_out[39]} {hub_data_out[40]} {hub_data_out[41]} {hub_data_out[42]} {hub_data_out[43]} {hub_data_out[44]} {hub_data_out[45]} {hub_data_out[46]} {hub_data_out[47]} {hub_data_out[48]} {hub_data_out[49]} {hub_data_out[50]} {hub_data_out[51]} {hub_data_out[52]} {hub_data_out[53]} {hub_data_out[54]} {hub_data_out[55]} {hub_data_out[56]} {hub_data_out[57]} {hub_data_out[58]} {hub_data_out[59]} {hub_data_out[60]} {hub_data_out[61]} {hub_data_out[62]} {hub_data_out[63]} {hub_data_out[64]} {hub_data_out[65]} {hub_data_out[66]} {hub_data_out[67]} {hub_data_out[68]} {hub_data_out[69]} {hub_data_out[70]} {hub_data_out[71]} {hub_data_out[72]} {hub_data_out[73]} {hub_data_out[74]} {hub_data_out[75]} {hub_data_out[76]} {hub_data_out[77]} {hub_data_out[78]} {hub_data_out[79]} {hub_data_out[80]} {hub_data_out[81]} {hub_data_out[82]} {hub_data_out[83]} {hub_data_out[84]} {hub_data_out[85]} {hub_data_out[86]} {hub_data_out[87]} {hub_data_out[88]} {hub_data_out[89]} {hub_data_out[90]} {hub_data_out[91]} {hub_data_out[92]} {hub_data_out[93]} {hub_data_out[94]} {hub_data_out[95]} {hub_data_out[96]} {hub_data_out[97]} {hub_data_out[98]} {hub_data_out[99]} {hub_data_out[100]} {hub_data_out[101]} {hub_data_out[102]} {hub_data_out[103]} {hub_data_out[104]} {hub_data_out[105]} {hub_data_out[106]} {hub_data_out[107]} {hub_data_out[108]} {hub_data_out[109]} {hub_data_out[110]} {hub_data_out[111]} {hub_data_out[112]} {hub_data_out[113]} {hub_data_out[114]} {hub_data_out[115]} {hub_data_out[116]} {hub_data_out[117]} {hub_data_out[118]} {hub_data_out[119]} {hub_data_out[120]} {hub_data_out[121]} {hub_data_out[122]} {hub_data_out[123]} {hub_data_out[124]} {hub_data_out[125]} {hub_data_out[126]} {hub_data_out[127]} {hub_data_out[128]} {hub_data_out[129]} {hub_data_out[130]} {hub_data_out[131]} {hub_data_out[132]} {hub_data_out[133]} {hub_data_out[134]} {hub_data_out[135]} {hub_data_out[136]} {hub_data_out[137]} {hub_data_out[138]} {hub_data_out[139]} {hub_data_out[140]} {hub_data_out[141]} {hub_data_out[142]} {hub_data_out[143]} {hub_data_out[144]} {hub_data_out[145]} {hub_data_out[146]} {hub_data_out[147]} {hub_data_out[148]} {hub_data_out[149]} {hub_data_out[150]} {hub_data_out[151]} {hub_data_out[152]} {hub_data_out[153]} {hub_data_out[154]} {hub_data_out[155]} {hub_data_out[156]} {hub_data_out[157]} {hub_data_out[158]} {hub_data_out[159]} {hub_data_out[160]} {hub_data_out[161]} {hub_data_out[162]} {hub_data_out[163]} {hub_data_out[164]} {hub_data_out[165]} {hub_data_out[166]} {hub_data_out[167]} {hub_data_out[168]} {hub_data_out[169]} {hub_data_out[170]} {hub_data_out[171]} {hub_data_out[172]} {hub_data_out[173]} {hub_data_out[174]} {hub_data_out[175]} {hub_data_out[176]} {hub_data_out[177]} {hub_data_out[178]} {hub_data_out[179]} {hub_data_out[180]} {hub_data_out[181]} {hub_data_out[182]} {hub_data_out[183]} {hub_data_out[184]} {hub_data_out[185]} {hub_data_out[186]} {hub_data_out[187]} {hub_data_out[188]} {hub_data_out[189]} {hub_data_out[190]} {hub_data_out[191]} {hub_data_out[192]} {hub_data_out[193]} {hub_data_out[194]} {hub_data_out[195]} {hub_data_out[196]} {hub_data_out[197]} {hub_data_out[198]} {hub_data_out[199]} {hub_data_out[200]} {hub_data_out[201]} {hub_data_out[202]} {hub_data_out[203]} {hub_data_out[204]} {hub_data_out[205]} {hub_data_out[206]} {hub_data_out[207]} {hub_data_out[208]} {hub_data_out[209]} {hub_data_out[210]} {hub_data_out[211]} {hub_data_out[212]} {hub_data_out[213]} {hub_data_out[214]} {hub_data_out[215]} {hub_data_out[216]} {hub_data_out[217]} {hub_data_out[218]} {hub_data_out[219]} {hub_data_out[220]} {hub_data_out[221]} {hub_data_out[222]} {hub_data_out[223]} {hub_data_out[224]} {hub_data_out[225]} {hub_data_out[226]} {hub_data_out[227]} {hub_data_out[228]} {hub_data_out[229]} {hub_data_out[230]} {hub_data_out[231]} {hub_data_out[232]} {hub_data_out[233]} {hub_data_out[234]} {hub_data_out[235]} {hub_data_out[236]} {hub_data_out[237]} {hub_data_out[238]} {hub_data_out[239]} {hub_data_out[240]} {hub_data_out[241]} {hub_data_out[242]} {hub_data_out[243]} {hub_data_out[244]} {hub_data_out[245]} {hub_data_out[246]} {hub_data_out[247]} {hub_data_out[248]} {hub_data_out[249]} {hub_data_out[250]} {hub_data_out[251]} {hub_data_out[252]} {hub_data_out[253]} {hub_data_out[254]} {hub_data_out[255]} {hub_data_out[256]} {hub_data_out[257]} {hub_data_out[258]} {hub_data_out[259]} {hub_data_out[260]} {hub_data_out[261]} {hub_data_out[262]} {hub_data_out[263]} {hub_data_out[264]} {hub_data_out[265]} {hub_data_out[266]} {hub_data_out[267]} {hub_data_out[268]} {hub_data_out[269]} {hub_data_out[270]} {hub_data_out[271]} {hub_data_out[272]} {hub_data_out[273]} {hub_data_out[274]} {hub_data_out[275]} {hub_data_out[276]} {hub_data_out[277]} {hub_data_out[278]} {hub_data_out[279]} {hub_data_out[280]} {hub_data_out[281]} {hub_data_out[282]} {hub_data_out[283]} {hub_data_out[284]} {hub_data_out[285]} {hub_data_out[286]} {hub_data_out[287]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] -set_property port_width 32 [get_debug_ports u_ila_0/probe8] -connect_debug_port u_ila_0/probe8 [get_nets [list {trb_data_tdata[128]} {trb_data_tdata[129]} {trb_data_tdata[130]} {trb_data_tdata[131]} {trb_data_tdata[132]} {trb_data_tdata[133]} {trb_data_tdata[134]} {trb_data_tdata[135]} {trb_data_tdata[136]} {trb_data_tdata[137]} {trb_data_tdata[138]} {trb_data_tdata[139]} {trb_data_tdata[140]} {trb_data_tdata[141]} {trb_data_tdata[142]} {trb_data_tdata[143]} {trb_data_tdata[144]} {trb_data_tdata[145]} {trb_data_tdata[146]} {trb_data_tdata[147]} {trb_data_tdata[148]} {trb_data_tdata[149]} {trb_data_tdata[150]} {trb_data_tdata[151]} {trb_data_tdata[152]} {trb_data_tdata[153]} {trb_data_tdata[154]} {trb_data_tdata[155]} {trb_data_tdata[156]} {trb_data_tdata[157]} {trb_data_tdata[158]} {trb_data_tdata[159]}]] +set_property port_width 9 [get_debug_ports u_ila_0/probe8] +connect_debug_port u_ila_0/probe8 [get_nets [list {trb_data_tvalid[0]} {trb_data_tvalid[1]} {trb_data_tvalid[2]} {trb_data_tvalid[3]} {trb_data_tvalid[4]} {trb_data_tvalid[5]} {trb_data_tvalid[6]} {trb_data_tvalid[7]} {trb_data_tvalid[8]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] -set_property port_width 8 [get_debug_ports u_ila_0/probe9] -connect_debug_port u_ila_0/probe9 [get_nets [list {hub_data_seqnmbr[32]} {hub_data_seqnmbr[33]} {hub_data_seqnmbr[34]} {hub_data_seqnmbr[35]} {hub_data_seqnmbr[36]} {hub_data_seqnmbr[37]} {hub_data_seqnmbr[38]} {hub_data_seqnmbr[39]}]] +set_property port_width 9 [get_debug_ports u_ila_0/probe9] +connect_debug_port u_ila_0/probe9 [get_nets [list {trb_data_tlast[0]} {trb_data_tlast[1]} {trb_data_tlast[2]} {trb_data_tlast[3]} {trb_data_tlast[4]} {trb_data_tlast[5]} {trb_data_tlast[6]} {trb_data_tlast[7]} {trb_data_tlast[8]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] +set_property port_width 9 [get_debug_ports u_ila_0/probe10] +connect_debug_port u_ila_0/probe10 [get_nets [list {trb_data_tready[0]} {trb_data_tready[1]} {trb_data_tready[2]} {trb_data_tready[3]} {trb_data_tready[4]} {trb_data_tready[5]} {trb_data_tready[6]} {trb_data_tready[7]} {trb_data_tready[8]}]] create_debug_core u_ila_1 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1] set_property ALL_PROBE_SAME_MU_CNT 16 [get_debug_cores u_ila_1] @@ -73,68 +77,104 @@ set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1] set_property port_width 1 [get_debug_ports u_ila_1/clk] connect_debug_port u_ila_1/clk [get_nets [list THE_SYSCLK/inst/clk_out2]] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0] -set_property port_width 16 [get_debug_ports u_ila_1/probe0] -connect_debug_port u_ila_1/probe0 [get_nets [list {THE_MEDIA_4_PCSB/THE_SERDES/TXDATA[0]} {THE_MEDIA_4_PCSB/THE_SERDES/TXDATA[1]} {THE_MEDIA_4_PCSB/THE_SERDES/TXDATA[2]} {THE_MEDIA_4_PCSB/THE_SERDES/TXDATA[3]} {THE_MEDIA_4_PCSB/THE_SERDES/TXDATA[4]} {THE_MEDIA_4_PCSB/THE_SERDES/TXDATA[5]} {THE_MEDIA_4_PCSB/THE_SERDES/TXDATA[6]} {THE_MEDIA_4_PCSB/THE_SERDES/TXDATA[7]} {THE_MEDIA_4_PCSB/THE_SERDES/TXDATA[8]} {THE_MEDIA_4_PCSB/THE_SERDES/TXDATA[9]} {THE_MEDIA_4_PCSB/THE_SERDES/TXDATA[10]} {THE_MEDIA_4_PCSB/THE_SERDES/TXDATA[11]} {THE_MEDIA_4_PCSB/THE_SERDES/TXDATA[12]} {THE_MEDIA_4_PCSB/THE_SERDES/TXDATA[13]} {THE_MEDIA_4_PCSB/THE_SERDES/TXDATA[14]} {THE_MEDIA_4_PCSB/THE_SERDES/TXDATA[15]}]] +set_property port_width 2 [get_debug_ports u_ila_1/probe0] +connect_debug_port u_ila_1/probe0 [get_nets [list {med2int_i[9][stat_op][13]} {med2int_i[9][stat_op][15]}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1] -set_property port_width 2 [get_debug_ports u_ila_1/probe1] -connect_debug_port u_ila_1/probe1 [get_nets [list {THE_MEDIA_4_PCSB/THE_SERDES/TXCHARISK[0]} {THE_MEDIA_4_PCSB/THE_SERDES/TXCHARISK[1]}]] +set_property port_width 8 [get_debug_ports u_ila_1/probe1] +connect_debug_port u_ila_1/probe1 [get_nets [list {THE_UPLINK/THE_SERDES/TXDATA[0]} {THE_UPLINK/THE_SERDES/TXDATA[1]} {THE_UPLINK/THE_SERDES/TXDATA[2]} {THE_UPLINK/THE_SERDES/TXDATA[3]} {THE_UPLINK/THE_SERDES/TXDATA[4]} {THE_UPLINK/THE_SERDES/TXDATA[5]} {THE_UPLINK/THE_SERDES/TXDATA[6]} {THE_UPLINK/THE_SERDES/TXDATA[7]}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2] -set_property port_width 2 [get_debug_ports u_ila_1/probe2] -connect_debug_port u_ila_1/probe2 [get_nets [list {THE_MEDIA_4_PCSB/THE_SERDES/TXCHARDISPMODE[0]} {THE_MEDIA_4_PCSB/THE_SERDES/TXCHARDISPMODE[1]}]] +set_property port_width 8 [get_debug_ports u_ila_1/probe2] +connect_debug_port u_ila_1/probe2 [get_nets [list {THE_UPLINK/THE_SERDES/RXDATA[0]} {THE_UPLINK/THE_SERDES/RXDATA[1]} {THE_UPLINK/THE_SERDES/RXDATA[2]} {THE_UPLINK/THE_SERDES/RXDATA[3]} {THE_UPLINK/THE_SERDES/RXDATA[4]} {THE_UPLINK/THE_SERDES/RXDATA[5]} {THE_UPLINK/THE_SERDES/RXDATA[6]} {THE_UPLINK/THE_SERDES/RXDATA[7]}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3] -set_property port_width 2 [get_debug_ports u_ila_1/probe3] -connect_debug_port u_ila_1/probe3 [get_nets [list {THE_MEDIA_4_PCSB/THE_SERDES/TXCHARDISPVAL[0]} {THE_MEDIA_4_PCSB/THE_SERDES/TXCHARDISPVAL[1]}]] +set_property port_width 8 [get_debug_ports u_ila_1/probe3] +connect_debug_port u_ila_1/probe3 [get_nets [list {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/RXDATA[0]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/RXDATA[1]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/RXDATA[2]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/RXDATA[3]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/RXDATA[4]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/RXDATA[5]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/RXDATA[6]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/RXDATA[7]}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4] -set_property port_width 2 [get_debug_ports u_ila_1/probe4] -connect_debug_port u_ila_1/probe4 [get_nets [list {med2int_i[9][stat_op][13]} {med2int_i[9][stat_op][15]}]] +set_property port_width 8 [get_debug_ports u_ila_1/probe4] +connect_debug_port u_ila_1/probe4 [get_nets [list {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/TXDATA[0]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/TXDATA[1]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/TXDATA[2]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/TXDATA[3]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/TXDATA[4]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/TXDATA[5]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/TXDATA[6]} {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/TXDATA[7]}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5] -set_property port_width 2 [get_debug_ports u_ila_1/probe5] -connect_debug_port u_ila_1/probe5 [get_nets [list {THE_MEDIA_4_PCSB/THE_SERDES/RXCHARISK[0]} {THE_MEDIA_4_PCSB/THE_SERDES/RXCHARISK[1]}]] +set_property port_width 1 [get_debug_ports u_ila_1/probe5] +connect_debug_port u_ila_1/probe5 [get_nets [list clear]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6] -set_property port_width 2 [get_debug_ports u_ila_1/probe6] -connect_debug_port u_ila_1/probe6 [get_nets [list {THE_MEDIA_4_PCSB/THE_SERDES/RXCHARISCOMMA[0]} {THE_MEDIA_4_PCSB/THE_SERDES/RXCHARISCOMMA[1]}]] +set_property port_width 1 [get_debug_ports u_ila_1/probe6] +connect_debug_port u_ila_1/probe6 [get_nets [list initial_clear_n]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe7] -set_property port_width 16 [get_debug_ports u_ila_1/probe7] -connect_debug_port u_ila_1/probe7 [get_nets [list {THE_MEDIA_4_PCSB/THE_SERDES/RXDATA[0]} {THE_MEDIA_4_PCSB/THE_SERDES/RXDATA[1]} {THE_MEDIA_4_PCSB/THE_SERDES/RXDATA[2]} {THE_MEDIA_4_PCSB/THE_SERDES/RXDATA[3]} {THE_MEDIA_4_PCSB/THE_SERDES/RXDATA[4]} {THE_MEDIA_4_PCSB/THE_SERDES/RXDATA[5]} {THE_MEDIA_4_PCSB/THE_SERDES/RXDATA[6]} {THE_MEDIA_4_PCSB/THE_SERDES/RXDATA[7]} {THE_MEDIA_4_PCSB/THE_SERDES/RXDATA[8]} {THE_MEDIA_4_PCSB/THE_SERDES/RXDATA[9]} {THE_MEDIA_4_PCSB/THE_SERDES/RXDATA[10]} {THE_MEDIA_4_PCSB/THE_SERDES/RXDATA[11]} {THE_MEDIA_4_PCSB/THE_SERDES/RXDATA[12]} {THE_MEDIA_4_PCSB/THE_SERDES/RXDATA[13]} {THE_MEDIA_4_PCSB/THE_SERDES/RXDATA[14]} {THE_MEDIA_4_PCSB/THE_SERDES/RXDATA[15]}]] +set_property port_width 1 [get_debug_ports u_ila_1/probe7] +connect_debug_port u_ila_1/probe7 [get_nets [list reset]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe8] -set_property port_width 2 [get_debug_ports u_ila_1/probe8] -connect_debug_port u_ila_1/probe8 [get_nets [list {THE_MEDIA_4_PCSB/THE_SERDES/RXDISPERR[0]} {THE_MEDIA_4_PCSB/THE_SERDES/RXDISPERR[1]}]] +set_property port_width 1 [get_debug_ports u_ila_1/probe8] +connect_debug_port u_ila_1/probe8 [get_nets [list {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/RXCHARISCOMMA}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe9] -set_property port_width 2 [get_debug_ports u_ila_1/probe9] -connect_debug_port u_ila_1/probe9 [get_nets [list {THE_MEDIA_4_PCSB/THE_SERDES/RXNOTINTABLE[0]} {THE_MEDIA_4_PCSB/THE_SERDES/RXNOTINTABLE[1]}]] +set_property port_width 1 [get_debug_ports u_ila_1/probe9] +connect_debug_port u_ila_1/probe9 [get_nets [list THE_UPLINK/THE_SERDES/RXCHARISCOMMA]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe10] set_property port_width 1 [get_debug_ports u_ila_1/probe10] -connect_debug_port u_ila_1/probe10 [get_nets [list clear]] +connect_debug_port u_ila_1/probe10 [get_nets [list THE_UPLINK/THE_SERDES/RXCHARISK]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe11] set_property port_width 1 [get_debug_ports u_ila_1/probe11] -connect_debug_port u_ila_1/probe11 [get_nets [list initial_clear_n]] +connect_debug_port u_ila_1/probe11 [get_nets [list {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/RXCHARISK}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe12] set_property port_width 1 [get_debug_ports u_ila_1/probe12] -connect_debug_port u_ila_1/probe12 [get_nets [list reset]] +connect_debug_port u_ila_1/probe12 [get_nets [list THE_UPLINK/THE_SERDES/RXDISPERR]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe13] set_property port_width 1 [get_debug_ports u_ila_1/probe13] -connect_debug_port u_ila_1/probe13 [get_nets [list send_reset_detect]] +connect_debug_port u_ila_1/probe13 [get_nets [list {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/RXDISPERR}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe14] set_property port_width 1 [get_debug_ports u_ila_1/probe14] -connect_debug_port u_ila_1/probe14 [get_nets [list sysclk_locked]] +connect_debug_port u_ila_1/probe14 [get_nets [list {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/RXNOTINTABLE}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe15] set_property port_width 1 [get_debug_ports u_ila_1/probe15] -connect_debug_port u_ila_1/probe15 [get_nets [list trb_reset]] +connect_debug_port u_ila_1/probe15 [get_nets [list THE_UPLINK/THE_SERDES/RXNOTINTABLE]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe16] +set_property port_width 1 [get_debug_ports u_ila_1/probe16] +connect_debug_port u_ila_1/probe16 [get_nets [list send_reset_detect]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe17] +set_property port_width 1 [get_debug_ports u_ila_1/probe17] +connect_debug_port u_ila_1/probe17 [get_nets [list sysclk_locked]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe18] +set_property port_width 1 [get_debug_ports u_ila_1/probe18] +connect_debug_port u_ila_1/probe18 [get_nets [list trb_reset]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe19] +set_property port_width 1 [get_debug_ports u_ila_1/probe19] +connect_debug_port u_ila_1/probe19 [get_nets [list {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/TXCHARDISPMODE}]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe20] +set_property port_width 1 [get_debug_ports u_ila_1/probe20] +connect_debug_port u_ila_1/probe20 [get_nets [list THE_UPLINK/THE_SERDES/TXCHARDISPMODE]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe21] +set_property port_width 1 [get_debug_ports u_ila_1/probe21] +connect_debug_port u_ila_1/probe21 [get_nets [list THE_UPLINK/THE_SERDES/TXCHARDISPVAL]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe22] +set_property port_width 1 [get_debug_ports u_ila_1/probe22] +connect_debug_port u_ila_1/probe22 [get_nets [list {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/TXCHARDISPVAL}]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe23] +set_property port_width 1 [get_debug_ports u_ila_1/probe23] +connect_debug_port u_ila_1/probe23 [get_nets [list {generate_downlinks[4].THE_DOWNLINK/THE_SERDES/TXCHARISK}]] +create_debug_port u_ila_1 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe24] +set_property port_width 1 [get_debug_ports u_ila_1/probe24] +connect_debug_port u_ila_1/probe24 [get_nets [list THE_UPLINK/THE_SERDES/TXCHARISK]] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] diff --git a/hub_test/constrs/debug_serdes.xdc b/hub_test/constrs/debug_serdes.xdc index b9a595e..fcdd62f 100644 --- a/hub_test/constrs/debug_serdes.xdc +++ b/hub_test/constrs/debug_serdes.xdc @@ -1,19 +1,19 @@ set_property KEEP true [get_nets {TXDATA[*]}] -set_property KEEP true [get_nets {TXCHARISK[*]}] -set_property KEEP true [get_nets {TXCHARDISPMODE[*]}] -set_property KEEP true [get_nets {TXCHARDISPVAL[*]}] +set_property KEEP true [get_nets {TXCHARISK}] +set_property KEEP true [get_nets {TXCHARDISPMODE}] +set_property KEEP true [get_nets {TXCHARDISPVAL}] set_property KEEP true [get_nets {RXDATA[*]}] -set_property KEEP true [get_nets {RXCHARISK[*]}] -set_property KEEP true [get_nets {RXCHARISCOMMA[*]}] -set_property KEEP true [get_nets {RXNOTINTABLE[*]}] -set_property KEEP true [get_nets {RXDISPERR[*]}] +set_property KEEP true [get_nets {RXCHARISK}] +set_property KEEP true [get_nets {RXCHARISCOMMA}] +set_property KEEP true [get_nets {RXNOTINTABLE}] +set_property KEEP true [get_nets {RXDISPERR}] set_property MARK_DEBUG true [get_nets {TXDATA[*]}] -set_property MARK_DEBUG true [get_nets {TXCHARISK[*]}] -set_property MARK_DEBUG true [get_nets {TXCHARDISPMODE[*]}] -set_property MARK_DEBUG true [get_nets {TXCHARDISPVAL[*]}] +set_property MARK_DEBUG true [get_nets {TXCHARISK}] +set_property MARK_DEBUG true [get_nets {TXCHARDISPMODE}] +set_property MARK_DEBUG true [get_nets {TXCHARDISPVAL}] set_property MARK_DEBUG true [get_nets {RXDATA[*]}] -set_property MARK_DEBUG true [get_nets {RXCHARISK[*]}] -set_property MARK_DEBUG true [get_nets {RXCHARISCOMMA[*]}] -set_property MARK_DEBUG true [get_nets {RXNOTINTABLE[*]}] -set_property MARK_DEBUG true [get_nets {RXDISPERR[*]}] +set_property MARK_DEBUG true [get_nets {RXCHARISK}] +set_property MARK_DEBUG true [get_nets {RXCHARISCOMMA}] +set_property MARK_DEBUG true [get_nets {RXNOTINTABLE}] +set_property MARK_DEBUG true [get_nets {RXDISPERR}] diff --git a/hub_test/constrs/hub_test.xdc b/hub_test/constrs/hub_test.xdc index 6fbbe4f..e775545 100644 --- a/hub_test/constrs/hub_test.xdc +++ b/hub_test/constrs/hub_test.xdc @@ -4,10 +4,10 @@ create_clock -period 5.000 -name CLK_200_P [get_ports CLK_200_P] set_property PACKAGE_PIN AR21 [get_ports SI5345_IN0_P] set_property IOSTANDARD LVDS [get_ports SI5345_IN0_P] -create_clock -period 10.000 -name SI5345_IN0_P [get_ports SI5345_IN0_P] set_property PACKAGE_PIN AY37 [get_ports SI5345_OUT7_P] set_property IOSTANDARD LVDS [get_ports SI5345_OUT7_P] +create_clock -period 10.000 -name SI5345_OUT7_P [get_ports SI5345_OUT7_P] set_property PACKAGE_PIN K10 [get_ports MPOD_RX1_RESET_N] set_property IOSTANDARD LVTTL [get_ports MPOD_RX1_RESET_N] @@ -59,19 +59,16 @@ set_property IOSTANDARD LVDS [get_ports TRG_OUT_2_P] set_property PACKAGE_PIN AT29 [get_ports TRG_OUT_3_P] set_property IOSTANDARD LVDS [get_ports TRG_OUT_3_P] -set_property LOC GTHE3_CHANNEL_X0Y8 [get_cells -hierarchical -filter {NAME =~ *THE_MEDIA_4_PCSB*gen_channel_container[2].*gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] -set_property LOC GTHE3_CHANNEL_X0Y9 [get_cells -hierarchical -filter {NAME =~ *THE_MEDIA_4_PCSB*gen_channel_container[2].*gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST}] -set_property LOC GTHE3_CHANNEL_X0Y10 [get_cells -hierarchical -filter {NAME =~ *THE_MEDIA_4_PCSB*gen_channel_container[2].*gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST}] -set_property LOC GTHE3_CHANNEL_X0Y11 [get_cells -hierarchical -filter {NAME =~ *THE_MEDIA_4_PCSB*gen_channel_container[2].*gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST}] +set_property LOC GTHE3_CHANNEL_X0Y9 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[4].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] +set_property LOC GTHE3_CHANNEL_X0Y10 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[5].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] +set_property LOC GTHE3_CHANNEL_X0Y11 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[6].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] -set_property LOC GTHE3_CHANNEL_X0Y12 [get_cells -hierarchical -filter {NAME =~ *THE_MEDIA_4_PCSC*gen_channel_container[2].*gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] -set_property LOC GTHE3_CHANNEL_X0Y13 [get_cells -hierarchical -filter {NAME =~ *THE_MEDIA_4_PCSC*gen_channel_container[2].*gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST}] -set_property LOC GTHE3_CHANNEL_X0Y14 [get_cells -hierarchical -filter {NAME =~ *THE_MEDIA_4_PCSC*gen_channel_container[2].*gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST}] -set_property LOC GTHE3_CHANNEL_X0Y15 [get_cells -hierarchical -filter {NAME =~ *THE_MEDIA_4_PCSC*gen_channel_container[2].*gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST}] +set_property LOC GTHE3_CHANNEL_X0Y12 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[2].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] +set_property LOC GTHE3_CHANNEL_X0Y13 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[3].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] +set_property LOC GTHE3_CHANNEL_X0Y14 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[0].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] +set_property LOC GTHE3_CHANNEL_X0Y15 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[1].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] -set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ *THE_MEDIA_4_PCSD*gen_channel_container[2].*gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] -set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ *THE_MEDIA_4_PCSD*gen_channel_container[2].*gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST}] -set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *THE_MEDIA_4_PCSD*gen_channel_container[2].*gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST}] -set_property LOC GTHE3_CHANNEL_X0Y19 [get_cells -hierarchical -filter {NAME =~ *THE_MEDIA_4_PCSD*gen_channel_container[2].*gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST}] +set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[8].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] +set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[7].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] -set_false_path -from [get_pins {design_1_wrapper_i/design_1_i/axi_gpio_mpod_los/U0/gpio_core_1/Dual.gpio_Data_Out_reg[*]/C}] -to [get_pins {THE_MEDIA_4_PCS?/gen_control[*].gen_used_control.THE_MED_CONTROL/THE_RX_FSM/sync_sfp_sigs/gen_others.gen_flipflops[*].sync_q_reg[*]_srl2/D}] +set_property LOC GTHE3_CHANNEL_X0Y8 [get_cells -hierarchical -filter {NAME =~ THE_UPLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}] diff --git a/hub_test/hub_test.xpr b/hub_test/hub_test.xpr index 6280768..1206c03 100644 --- a/hub_test/hub_test.xpr +++ b/hub_test/hub_test.xpr @@ -67,49 +67,42 @@ - - - - - - - - + - + - + - + - + - + @@ -137,27 +130,6 @@ - - - - - - - - - - - - - - - - - - - - - @@ -212,13 +184,7 @@ - - - - - - - + @@ -248,7 +214,7 @@ - + @@ -488,12 +454,6 @@ - - - - - - @@ -567,7 +527,7 @@ - + diff --git a/hub_test/ip/clk_wiz_1/clk_wiz_1.xci b/hub_test/ip/clk_wiz_1/clk_wiz_1.xci deleted file mode 100644 index 55b9afc..0000000 --- a/hub_test/ip/clk_wiz_1/clk_wiz_1.xci +++ /dev/null @@ -1,710 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - clk_wiz_1 - - - false - 100000000 - false - 100000000 - false - 100000000 - false - 100000000 - - - - 100000000 - 0 - 0 - 0.000 - 1 - LEVEL_HIGH - - - - 100000000 - 0 - 0 - 0.000 - 0 - 0 - - 100000000 - 0 - 0 - 0.000 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 0 - MMCM - cddcdone - cddcreq - 0000 - 0000 - clkfb_in_n - clkfb_in - clkfb_in_p - SINGLE - clkfb_out_n - clkfb_out - clkfb_out_p - clkfb_stopped - 50.0 - 100.0 - 0000 - 0000 - 100.00000 - 0000 - 0000 - 100.000 - BUFG - 50.0 - false - 100.00000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - VCO - clk_in_sel - clk_out1 - clk_out2 - clk_out3 - clk_out4 - clk_out5 - clk_out6 - clk_out7 - CLK_VALID - NA - daddr - dclk - den - din - 0000 - 1 - 1.0 - 1.0 - 1.0 - 1.0 - 1.0 - 1.0 - dout - drdy - dwe - 93.000 - 1.000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - FDBK_AUTO - 0000 - 0000 - 0 - Input Clock Freq (MHz) Input Jitter (UI) - __primary_________200.000____________0.010 - no_secondary_input_clock - input_clk_stopped - 0 - Units_MHz - No_Jitter - locked - 0000 - 0000 - 0000 - false - false - false - false - false - false - false - false - OPTIMIZED - 5.000 - 0.000 - FALSE - 5.000 - 10.0 - 10.000 - 0.500 - 0.000 - FALSE - 1 - 0.500 - 0.000 - FALSE - 1 - 0.500 - 0.000 - FALSE - 1 - 0.500 - 0.000 - FALSE - FALSE - 1 - 0.500 - 0.000 - FALSE - 1 - 0.500 - 0.000 - FALSE - 1 - 0.500 - 0.000 - FALSE - FALSE - AUTO - 1 - None - 0.010 - 0.010 - FALSE - 64.000 - 2.000 - 1 - Output Output Phase Duty Cycle Pk-to-Pk Phase - Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - clk_out1__100.00000______0.000______50.0______112.316_____89.971 - no_CLK_OUT2_output - no_CLK_OUT3_output - no_CLK_OUT4_output - no_CLK_OUT5_output - no_CLK_OUT6_output - no_CLK_OUT7_output - 0 - 0 - 128.000 - 1.000 - WAVEFORM - UNKNOWN - false - false - false - false - false - OPTIMIZED - 1 - 0.000 - 1.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - CLKFBOUT - SYSTEM_SYNCHRONOUS - 1 - No notes - 0.010 - power_down - 0000 - 1 - clk_in1 - MMCM - AUTO - 200.000 - 0.010 - 10.000 - Differential_clock_capable_pin - psclk - psdone - psen - psincdec - 100.0 - 0 - reset - 100.000 - 0.010 - 10.000 - clk_in2 - Single_ended_clock_capable_pin - CENTER_HIGH - 4000 - 0.004 - STATUS - 11 - 32 - 100.0 - 100.0 - 100.0 - 100.0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 1 - 0 - 1 - 0 - 0 - 0 - 1440.000 - 600.000 - clk_wiz_1 - MMCM - false - empty - cddcdone - cddcreq - clkfb_in_n - clkfb_in - clkfb_in_p - SINGLE - clkfb_out_n - clkfb_out - clkfb_out_p - clkfb_stopped - 50.0 - 0.010 - 100.0 - 0.010 - Buffer - 112.316 - false - 89.971 - 50.000 - 100.000 - 0.000 - 1 - true - Buffer - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - Buffer - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - Buffer - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - Buffer - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - Buffer - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - Buffer - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - 600.000 - Custom - Custom - clk_in_sel - clk_out1 - false - clk_out2 - false - clk_out3 - false - clk_out4 - false - clk_out5 - false - clk_out6 - false - clk_out7 - false - CLK_VALID - auto - clk_wiz_1 - daddr - dclk - den - Custom - Custom - din - dout - drdy - dwe - false - false - false - false - false - false - false - false - false - FDBK_AUTO - input_clk_stopped - frequency - Enable_AXI - Units_MHz - Units_UI - UI - No_Jitter - locked - OPTIMIZED - 5.000 - 0.000 - false - 5.000 - 10.0 - 10.000 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - false - 1 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - false - AUTO - 1 - None - 0.010 - 0.010 - false - 1 - false - false - WAVEFORM - false - UNKNOWN - OPTIMIZED - 4 - 0.000 - 10.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - CLKFBOUT - SYSTEM_SYNCHRONOUS - 1 - None - 0.010 - power_down - 1 - clk_in1 - MMCM - mmcm_adv - 200.000 - 0.010 - 10.000 - Differential_clock_capable_pin - psclk - psdone - psen - psincdec - 100.0 - REL_PRIMARY - Custom - reset - ACTIVE_HIGH - 100.000 - 0.010 - 10.000 - clk_in2 - Single_ended_clock_capable_pin - CENTER_HIGH - 250 - 0.004 - STATUS - empty - 100.0 - 100.0 - 100.0 - 100.0 - false - false - false - false - false - false - false - true - false - false - true - false - false - false - true - false - true - false - false - false - kintexu - - - xcku115 - flvf1924 - VHDL - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 5 - TRUE - . - - . - 2020.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/hub_test/ip/clk_wiz_1/clk_wiz_1.xml b/hub_test/ip/clk_wiz_1/clk_wiz_1.xml deleted file mode 100644 index 535ff64..0000000 --- a/hub_test/ip/clk_wiz_1/clk_wiz_1.xml +++ /dev/null @@ -1,4497 +0,0 @@ - - - xilinx.com - customized_ip - clk_wiz_1 - 1.0 - - - s_axi_lite - S_AXI_LITE - - - - - - - ARADDR - - - s_axi_araddr - - - - - ARREADY - - - s_axi_arready - - - - - ARVALID - - - s_axi_arvalid - - - - - AWADDR - - - s_axi_awaddr - - - - - AWREADY - - - s_axi_awready - - - - - AWVALID - - - s_axi_awvalid - - - - - BREADY - - - s_axi_bready - - - - - BRESP - - - s_axi_bresp - - - - - BVALID - - - s_axi_bvalid - - - - - RDATA - - - s_axi_rdata - - - - - RREADY - - - s_axi_rready - - - - - RRESP - - - s_axi_rresp - - - - - RVALID - - - s_axi_rvalid - - - - - WDATA - - - s_axi_wdata - - - - - WREADY - - - s_axi_wready - - - - - WSTRB - - - s_axi_wstrb - - - - - WVALID - - - s_axi_wvalid - - - - - - DATA_WIDTH - 1 - - - none - - - - - PROTOCOL - AXI4LITE - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 1 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 0 - - - none - - - - - HAS_LOCK - 0 - - - none - - - - - HAS_PROT - 0 - - - none - - - - - HAS_CACHE - 0 - - - none - - - - - HAS_QOS - 0 - - - none - - - - - HAS_REGION - 0 - - - none - - - - - HAS_WSTRB - 0 - - - none - - - - - HAS_BRESP - 0 - - - none - - - - - HAS_RRESP - 0 - - - none - - - - - SUPPORTS_NARROW_BURST - 0 - - - none - - - - - NUM_READ_OUTSTANDING - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - MAX_BURST_LENGTH - 1 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - s_axi_aclk - s_axi_aclk - - - - - - - CLK - - - s_axi_aclk - - - - - - ASSOCIATED_BUSIF - s_axi_lite - - - ASSOCIATED_RESET - s_axi_aresetn - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - ref_clk - ref_clk - - - - - - - CLK - - - ref_clk - - - - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - s_axi_resetn - S_AXI_RESETN - - - - - - - RST - - - s_axi_aresetn - - - - - - ASSOCIATED_RESET - aresetn - - - POLARITY - ACTIVE_LOW - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - intr - Intr - - - - - - - INTERRUPT - - - ip2intc_irpt - - - - - - SENSITIVITY - LEVEL_HIGH - - - none - - - - - PortWidth - 1 - - - none - - - - - - - - false - - - - - - CLK_IN1_D - CLK_IN1_D - Differential Clock input - - - - - - - CLK_N - - - clk_in1_n - - - - - CLK_P - - - clk_in1_p - - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN1_BOARD_INTERFACE - - - - required - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - true - - - - - - CLK_IN2_D - CLK_IN2_D - Differential Clock input - - - - - - - CLK_N - - - clk_in2_n - - - - - CLK_P - - - clk_in2_p - - - - - - BOARD.ASSOCIATED_PARAM - CLK_IN2_BOARD_INTERFACE - - - - required - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLKFB_IN_D - CLKFB_IN_D - Differential Feedback Clock input - - - - - - - CLK_N - - - clkfb_in_n - - - - - CLK_P - - - clkfb_in_p - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - CLKFB_OUT_D - CLKFB_OUT_D - Differential Feeback Clock Output - - - - - - - CLK_N - - - clkfb_out_n - - - - - CLK_P - - - clkfb_out_p - - - - - - CAN_DEBUG - false - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - - - - false - - - - - - reset - reset - - - - - - - RST - - - reset - - - - - - POLARITY - ACTIVE_HIGH - - - BOARD.ASSOCIATED_PARAM - RESET_BOARD_INTERFACE - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - resetn - resetn - - - - - - - RST - - - resetn - - - - - - POLARITY - ACTIVE_LOW - - - BOARD.ASSOCIATED_PARAM - RESET_BOARD_INTERFACE - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - clock_CLK_OUT1 - - - - - - - CLK_OUT1 - - - clk_out1 - - - - - - FREQ_HZ - 100000000 - - - none - - - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - - - xilinx_elaborateports - Elaborate Ports - :vivado.xilinx.com:elaborate.ports - - - outputProductCRC - 9:10d1178b - - - - - - - s_axi_aclk - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_aresetn - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_awaddr - - in - - 10 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_awvalid - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_awready - - out - - - std_logic - xilinx_elaborateports - - - - - - - false - - - - - - s_axi_wdata - - in - - 31 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_wstrb - - in - - 3 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_wvalid - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_wready - - out - - - std_logic - xilinx_elaborateports - - - - - - - false - - - - - - s_axi_bresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - - - - false - - - - - - s_axi_bvalid - - out - - - std_logic - xilinx_elaborateports - - - - - - - false - - - - - - s_axi_bready - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_araddr - - in - - 10 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_arvalid - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - s_axi_arready - - out - - - std_logic - xilinx_elaborateports - - - - - - - false - - - - - - s_axi_rdata - - out - - 31 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - - - - false - - - - - - s_axi_rresp - - out - - 1 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - - - - false - - - - - - s_axi_rvalid - - out - - - std_logic - xilinx_elaborateports - - - - - - - false - - - - - - s_axi_rready - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clk_in1_p - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - true - - - - - - clk_in1_n - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - true - - - - - - clk_in2_p - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clk_in2_n - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clkfb_in_p - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clkfb_in_n - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clkfb_out_p - - out - - - std_logic - xilinx_elaborateports - - - - - - - false - - - - - - clkfb_out_n - - out - - - std_logic - xilinx_elaborateports - - - - - - - false - - - - - - reset - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - true - - - - - - resetn - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - ref_clk - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clk_stop - - out - - 3 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clk_glitch - - out - - 3 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - interrupt - - out - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clk_oor - - out - - 3 - 0 - - - - std_logic_vector - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - user_clk0 - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - user_clk1 - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - user_clk2 - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - user_clk3 - - in - - - std_logic - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - clk_out1 - - out - - - std_logic - xilinx_elaborateports - - - - - - locked - - out - - - std_logic - xilinx_elaborateports - - - - - - - - C_CLKOUT2_USED - 0 - - - C_USER_CLK_FREQ0 - 100.0 - - - C_AUTO_PRIMITIVE - MMCM - - - C_USER_CLK_FREQ1 - 100.0 - - - C_USER_CLK_FREQ2 - 100.0 - - - C_USER_CLK_FREQ3 - 100.0 - - - C_ENABLE_CLOCK_MONITOR - 0 - - - C_ENABLE_USER_CLOCK0 - 0 - - - C_ENABLE_USER_CLOCK1 - 0 - - - C_ENABLE_USER_CLOCK2 - 0 - - - C_ENABLE_USER_CLOCK3 - 0 - - - C_Enable_PLL0 - 0 - - - C_Enable_PLL1 - 0 - - - C_REF_CLK_FREQ - 100.0 - - - C_PRECISION - 1 - - - C_CLKOUT3_USED - 0 - - - C_CLKOUT4_USED - 0 - - - C_CLKOUT5_USED - 0 - - - C_CLKOUT6_USED - 0 - - - C_CLKOUT7_USED - 0 - - - C_USE_CLKOUT1_BAR - 0 - - - C_USE_CLKOUT2_BAR - 0 - - - C_USE_CLKOUT3_BAR - 0 - - - C_USE_CLKOUT4_BAR - 0 - - - c_component_name - clk_wiz_1 - - - C_PLATFORM - UNKNOWN - - - C_USE_FREQ_SYNTH - 1 - - - C_USE_PHASE_ALIGNMENT - 1 - - - C_PRIM_IN_JITTER - 0.010 - - - C_SECONDARY_IN_JITTER - 0.010 - - - C_JITTER_SEL - No_Jitter - - - C_USE_MIN_POWER - 0 - - - C_USE_MIN_O_JITTER - 0 - - - C_USE_MAX_I_JITTER - 0 - - - C_USE_DYN_PHASE_SHIFT - 0 - - - C_USE_INCLK_SWITCHOVER - 0 - - - C_USE_DYN_RECONFIG - 0 - - - C_USE_SPREAD_SPECTRUM - 0 - - - C_USE_FAST_SIMULATION - 0 - - - C_PRIMTYPE_SEL - AUTO - - - C_USE_CLK_VALID - 0 - - - C_PRIM_IN_FREQ - 200.000 - - - C_PRIM_IN_TIMEPERIOD - 10.000 - - - C_IN_FREQ_UNITS - Units_MHz - - - C_SECONDARY_IN_FREQ - 100.000 - - - C_SECONDARY_IN_TIMEPERIOD - 10.000 - - - C_FEEDBACK_SOURCE - FDBK_AUTO - - - C_PRIM_SOURCE - Differential_clock_capable_pin - - - C_PHASESHIFT_MODE - WAVEFORM - - - C_SECONDARY_SOURCE - Single_ended_clock_capable_pin - - - C_CLKFB_IN_SIGNALING - SINGLE - - - C_USE_RESET - 1 - - - C_RESET_LOW - 0 - - - C_USE_LOCKED - 1 - - - C_USE_INCLK_STOPPED - 0 - - - C_USE_CLKFB_STOPPED - 0 - - - C_USE_POWER_DOWN - 0 - - - C_USE_STATUS - 0 - - - C_USE_FREEZE - 0 - - - C_NUM_OUT_CLKS - 1 - - - C_CLKOUT1_DRIVES - BUFG - - - C_CLKOUT2_DRIVES - BUFG - - - C_CLKOUT3_DRIVES - BUFG - - - C_CLKOUT4_DRIVES - BUFG - - - C_CLKOUT5_DRIVES - BUFG - - - C_CLKOUT6_DRIVES - BUFG - - - C_CLKOUT7_DRIVES - BUFG - - - C_INCLK_SUM_ROW0 - Input Clock Freq (MHz) Input Jitter (UI) - - - C_INCLK_SUM_ROW1 - __primary_________200.000____________0.010 - - - C_INCLK_SUM_ROW2 - no_secondary_input_clock - - - C_OUTCLK_SUM_ROW0A - C Outclk Sum Row0a - Output Output Phase Duty Cycle Pk-to-Pk Phase - - - C_OUTCLK_SUM_ROW0B - Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - - - C_OUTCLK_SUM_ROW1 - clk_out1__100.00000______0.000______50.0______112.316_____89.971 - - - C_OUTCLK_SUM_ROW2 - no_CLK_OUT2_output - - - C_OUTCLK_SUM_ROW3 - no_CLK_OUT3_output - - - C_OUTCLK_SUM_ROW4 - no_CLK_OUT4_output - - - C_OUTCLK_SUM_ROW5 - no_CLK_OUT5_output - - - C_OUTCLK_SUM_ROW6 - no_CLK_OUT6_output - - - C_OUTCLK_SUM_ROW7 - no_CLK_OUT7_output - - - C_CLKOUT1_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT2_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT3_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT4_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT5_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT6_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT7_REQUESTED_OUT_FREQ - 100.000 - - - C_CLKOUT1_REQUESTED_PHASE - 0.000 - - - C_CLKOUT2_REQUESTED_PHASE - 0.000 - - - C_CLKOUT3_REQUESTED_PHASE - 0.000 - - - C_CLKOUT4_REQUESTED_PHASE - 0.000 - - - C_CLKOUT5_REQUESTED_PHASE - 0.000 - - - C_CLKOUT6_REQUESTED_PHASE - 0.000 - - - C_CLKOUT7_REQUESTED_PHASE - 0.000 - - - C_CLKOUT1_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT2_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT3_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT4_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT5_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT6_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT7_REQUESTED_DUTY_CYCLE - 50.000 - - - C_CLKOUT1_OUT_FREQ - 100.00000 - - - C_CLKOUT2_OUT_FREQ - 100.000 - - - C_CLKOUT3_OUT_FREQ - 100.000 - - - C_CLKOUT4_OUT_FREQ - 100.000 - - - C_CLKOUT5_OUT_FREQ - 100.000 - - - C_CLKOUT6_OUT_FREQ - 100.000 - - - C_CLKOUT7_OUT_FREQ - 100.000 - - - C_CLKOUT1_PHASE - 0.000 - - - C_CLKOUT2_PHASE - 0.000 - - - C_CLKOUT3_PHASE - 0.000 - - - C_CLKOUT4_PHASE - 0.000 - - - C_CLKOUT5_PHASE - 0.000 - - - C_CLKOUT6_PHASE - 0.000 - - - C_CLKOUT7_PHASE - 0.000 - - - C_CLKOUT1_DUTY_CYCLE - 50.0 - - - C_CLKOUT2_DUTY_CYCLE - 50.000 - - - C_CLKOUT3_DUTY_CYCLE - 50.000 - - - C_CLKOUT4_DUTY_CYCLE - 50.000 - - - C_CLKOUT5_DUTY_CYCLE - 50.000 - - - C_CLKOUT6_DUTY_CYCLE - 50.000 - - - C_CLKOUT7_DUTY_CYCLE - 50.000 - - - C_USE_SAFE_CLOCK_STARTUP - 0 - - - C_USE_CLOCK_SEQUENCING - 0 - - - C_CLKOUT1_SEQUENCE_NUMBER - 1 - - - C_CLKOUT2_SEQUENCE_NUMBER - 1 - - - C_CLKOUT3_SEQUENCE_NUMBER - 1 - - - C_CLKOUT4_SEQUENCE_NUMBER - 1 - - - C_CLKOUT5_SEQUENCE_NUMBER - 1 - - - C_CLKOUT6_SEQUENCE_NUMBER - 1 - - - C_CLKOUT7_SEQUENCE_NUMBER - 1 - - - C_MMCM_NOTES - None - - - C_MMCM_BANDWIDTH - OPTIMIZED - - - C_MMCM_CLKFBOUT_MULT_F - 5.000 - - - C_MMCM_CLKIN1_PERIOD - 5.000 - - - C_MMCM_CLKIN2_PERIOD - 10.0 - - - C_MMCM_CLKOUT4_CASCADE - FALSE - - - C_MMCM_CLOCK_HOLD - FALSE - - - C_MMCM_COMPENSATION - AUTO - - - C_MMCM_DIVCLK_DIVIDE - 1 - - - C_MMCM_REF_JITTER1 - 0.010 - - - C_MMCM_REF_JITTER2 - 0.010 - - - C_MMCM_STARTUP_WAIT - FALSE - - - C_MMCM_CLKOUT0_DIVIDE_F - 10.000 - - - C_MMCM_CLKOUT1_DIVIDE - 1 - - - C_MMCM_CLKOUT2_DIVIDE - 1 - - - C_MMCM_CLKOUT3_DIVIDE - 1 - - - C_MMCM_CLKOUT4_DIVIDE - 1 - - - C_MMCM_CLKOUT5_DIVIDE - 1 - - - C_MMCM_CLKOUT6_DIVIDE - 1 - - - C_MMCM_CLKOUT0_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT1_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT2_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT3_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT4_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT5_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKOUT6_DUTY_CYCLE - 0.500 - - - C_MMCM_CLKFBOUT_PHASE - 0.000 - - - C_MMCM_CLKOUT0_PHASE - 0.000 - - - C_MMCM_CLKOUT1_PHASE - 0.000 - - - C_MMCM_CLKOUT2_PHASE - 0.000 - - - C_MMCM_CLKOUT3_PHASE - 0.000 - - - C_MMCM_CLKOUT4_PHASE - 0.000 - - - C_MMCM_CLKOUT5_PHASE - 0.000 - - - C_MMCM_CLKOUT6_PHASE - 0.000 - - - C_MMCM_CLKFBOUT_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT0_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT1_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT2_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT3_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT4_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT5_USE_FINE_PS - FALSE - - - C_MMCM_CLKOUT6_USE_FINE_PS - FALSE - - - C_PLL_NOTES - No notes - - - C_PLL_BANDWIDTH - OPTIMIZED - - - C_PLL_CLK_FEEDBACK - CLKFBOUT - - - C_PLL_CLKFBOUT_MULT - 1 - - - C_PLL_CLKIN_PERIOD - 1.000 - - - C_PLL_COMPENSATION - SYSTEM_SYNCHRONOUS - - - C_PLL_DIVCLK_DIVIDE - 1 - - - C_PLL_REF_JITTER - 0.010 - - - C_PLL_CLKOUT0_DIVIDE - 1 - - - C_PLL_CLKOUT1_DIVIDE - 1 - - - C_PLL_CLKOUT2_DIVIDE - 1 - - - C_PLL_CLKOUT3_DIVIDE - 1 - - - C_PLL_CLKOUT4_DIVIDE - 1 - - - C_PLL_CLKOUT5_DIVIDE - 1 - - - C_PLL_CLKOUT0_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT1_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT2_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT3_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT4_DUTY_CYCLE - 0.500 - - - C_PLL_CLKOUT5_DUTY_CYCLE - 0.500 - - - C_PLL_CLKFBOUT_PHASE - 0.000 - - - C_PLL_CLKOUT0_PHASE - 0.000 - - - C_PLL_CLKOUT1_PHASE - 0.000 - - - C_PLL_CLKOUT2_PHASE - 0.000 - - - C_PLL_CLKOUT3_PHASE - 0.000 - - - C_PLL_CLKOUT4_PHASE - 0.000 - - - C_PLL_CLKOUT5_PHASE - 0.000 - - - C_CLOCK_MGR_TYPE - NA - - - C_OVERRIDE_MMCM - 0 - - - C_OVERRIDE_PLL - 0 - - - C_PRIMARY_PORT - clk_in1 - - - C_SECONDARY_PORT - clk_in2 - - - C_CLK_OUT1_PORT - clk_out1 - - - C_CLK_OUT2_PORT - clk_out2 - - - C_CLK_OUT3_PORT - clk_out3 - - - C_CLK_OUT4_PORT - clk_out4 - - - C_CLK_OUT5_PORT - clk_out5 - - - C_CLK_OUT6_PORT - clk_out6 - - - C_CLK_OUT7_PORT - clk_out7 - - - C_RESET_PORT - reset - - - C_LOCKED_PORT - locked - - - C_CLKFB_IN_PORT - clkfb_in - - - C_CLKFB_IN_P_PORT - clkfb_in_p - - - C_CLKFB_IN_N_PORT - clkfb_in_n - - - C_CLKFB_OUT_PORT - clkfb_out - - - C_CLKFB_OUT_P_PORT - clkfb_out_p - - - C_CLKFB_OUT_N_PORT - clkfb_out_n - - - C_POWER_DOWN_PORT - power_down - - - C_DADDR_PORT - daddr - - - C_DCLK_PORT - dclk - - - C_DRDY_PORT - drdy - - - C_DWE_PORT - dwe - - - C_DIN_PORT - din - - - C_DOUT_PORT - dout - - - C_DEN_PORT - den - - - C_PSCLK_PORT - psclk - - - C_PSEN_PORT - psen - - - C_PSINCDEC_PORT - psincdec - - - C_PSDONE_PORT - psdone - - - C_CLK_VALID_PORT - CLK_VALID - - - C_STATUS_PORT - STATUS - - - C_CLK_IN_SEL_PORT - clk_in_sel - - - C_INPUT_CLK_STOPPED_PORT - input_clk_stopped - - - C_CLKFB_STOPPED_PORT - clkfb_stopped - - - C_CLKIN1_JITTER_PS - 50.0 - - - C_CLKIN2_JITTER_PS - 100.0 - - - C_PRIMITIVE - MMCM - - - C_SS_MODE - CENTER_HIGH - - - C_SS_MOD_PERIOD - 4000 - - - C_SS_MOD_TIME - 0.004 - - - C_HAS_CDDC - 0 - - - C_CDDCDONE_PORT - cddcdone - - - C_CDDCREQ_PORT - cddcreq - - - C_CLKOUTPHY_MODE - VCO - - - C_ENABLE_CLKOUTPHY - 0 - - - C_INTERFACE_SELECTION - 0 - - - C_S_AXI_ADDR_WIDTH - C S Axi Addr Width - 11 - - - C_S_AXI_DATA_WIDTH - C S Axi Data Width - 32 - - - C_POWER_REG - 0000 - - - C_CLKOUT0_1 - 0000 - - - C_CLKOUT0_2 - 0000 - - - C_CLKOUT1_1 - 0000 - - - C_CLKOUT1_2 - 0000 - - - C_CLKOUT2_1 - 0000 - - - C_CLKOUT2_2 - 0000 - - - C_CLKOUT3_1 - 0000 - - - C_CLKOUT3_2 - 0000 - - - C_CLKOUT4_1 - 0000 - - - C_CLKOUT4_2 - 0000 - - - C_CLKOUT5_1 - 0000 - - - C_CLKOUT5_2 - 0000 - - - C_CLKOUT6_1 - 0000 - - - C_CLKOUT6_2 - 0000 - - - C_CLKFBOUT_1 - 0000 - - - C_CLKFBOUT_2 - 0000 - - - C_DIVCLK - 0000 - - - C_LOCK_1 - 0000 - - - C_LOCK_2 - 0000 - - - C_LOCK_3 - 0000 - - - C_FILTER_1 - 0000 - - - C_FILTER_2 - 0000 - - - C_DIVIDE1_AUTO - 1 - - - C_DIVIDE2_AUTO - 1.0 - - - C_DIVIDE3_AUTO - 1.0 - - - C_DIVIDE4_AUTO - 1.0 - - - C_DIVIDE5_AUTO - 1.0 - - - C_DIVIDE6_AUTO - 1.0 - - - C_DIVIDE7_AUTO - 1.0 - - - C_PLLBUFGCEDIV - false - - - C_MMCMBUFGCEDIV - false - - - C_PLLBUFGCEDIV1 - false - - - C_PLLBUFGCEDIV2 - false - - - C_PLLBUFGCEDIV3 - false - - - C_PLLBUFGCEDIV4 - false - - - C_MMCMBUFGCEDIV1 - false - - - C_MMCMBUFGCEDIV2 - false - - - C_MMCMBUFGCEDIV3 - false - - - C_MMCMBUFGCEDIV4 - false - - - C_MMCMBUFGCEDIV5 - false - - - C_MMCMBUFGCEDIV6 - false - - - C_MMCMBUFGCEDIV7 - false - - - C_CLKOUT1_MATCHED_ROUTING - false - - - C_CLKOUT2_MATCHED_ROUTING - false - - - C_CLKOUT3_MATCHED_ROUTING - false - - - C_CLKOUT4_MATCHED_ROUTING - false - - - C_CLKOUT5_MATCHED_ROUTING - false - - - C_CLKOUT6_MATCHED_ROUTING - false - - - C_CLKOUT7_MATCHED_ROUTING - false - - - C_CLKOUT0_ACTUAL_FREQ - 100.00000 - - - C_CLKOUT1_ACTUAL_FREQ - 100.000 - - - C_CLKOUT2_ACTUAL_FREQ - 100.000 - - - C_CLKOUT3_ACTUAL_FREQ - 100.000 - - - C_CLKOUT4_ACTUAL_FREQ - 100.000 - - - C_CLKOUT5_ACTUAL_FREQ - 100.000 - - - C_CLKOUT6_ACTUAL_FREQ - 100.000 - - - C_M_MAX - 64.000 - - - C_M_MIN - 2.000 - - - C_D_MAX - 93.000 - - - C_D_MIN - 1.000 - - - C_O_MAX - 128.000 - - - C_O_MIN - 1.000 - - - C_VCO_MIN - 600.000 - - - C_VCO_MAX - 1440.000 - - - - - - choice_list_1d3de01d - WAVEFORM - LATENCY - - - choice_list_876bfc32 - UI - PS - - - choice_list_a9bdfce0 - LOW - HIGH - OPTIMIZED - - - choice_list_ac75ef1e - Custom - - - choice_list_b9d38208 - CLKFBOUT - CLKOUT0 - - - choice_list_d0ea4aeb - MMCM - PLL - Auto - - - choice_pairs_035ca1c3 - SYSTEM_SYNCHRONOUS - SOURCE_SYNCHRONOUS - INTERNAL - EXTERNAL - - - choice_pairs_0920eb1b - Custom - sys_diff_clock - - - choice_pairs_11d71346 - Single_ended_clock_capable_pin - Differential_clock_capable_pin - Global_buffer - No_buffer - - - choice_pairs_15c806d5 - FDBK_AUTO - FDBK_AUTO_OFFCHIP - FDBK_ONCHIP - FDBK_OFFCHIP - - - choice_pairs_340369e0 - Custom - sys_clock - sys_diff_clock - - - choice_pairs_39d99e50 - Buffer - Buffer_with_CE - BUFG - BUFGCE - BUFGCE_DIV - No_buffer - - - choice_pairs_3c2d3ec7 - SINGLE - DIFF - - - choice_pairs_77d3d587 - MMCM - PLL - BUFGCE_DIV - - - choice_pairs_8b28f1f7 - Enable_AXI - Enable_DRP - - - choice_pairs_8eea9b32 - Units_MHz - Units_ns - - - choice_pairs_94e02745 - AUTO - EXTERNAL - INTERNAL - BUF_IN - ZHOLD - - - choice_pairs_a4fbc00c - ACTIVE_HIGH - ACTIVE_LOW - - - choice_pairs_a8642b4c - No_Jitter - Min_O_Jitter - Max_I_Jitter - - - choice_pairs_c5ef7212 - Units_UI - Units_ps - - - choice_pairs_e1c87518 - REL_PRIMARY - REL_SECONDARY - - - choice_pairs_f4e10086 - CENTER_HIGH - CENTER_LOW - DOWN_HIGH - DOWN_LOW - - - choice_pairs_f669c2f5 - frequency - Time - - - The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements. - - - Component_Name - clk_wiz_1 - - - USER_CLK_FREQ0 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ1 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ2 - User Frequency(MHz) - 100.0 - - - USER_CLK_FREQ3 - User Frequency(MHz) - 100.0 - - - ENABLE_CLOCK_MONITOR - Enable Clock Monitoring - false - - - ENABLE_USER_CLOCK0 - User Clock - false - - - ENABLE_USER_CLOCK1 - User Clock - false - - - ENABLE_USER_CLOCK2 - User Clock - false - - - ENABLE_USER_CLOCK3 - User Clock - false - - - Enable_PLL0 - User Clock - false - - - Enable_PLL1 - User Clock - false - - - REF_CLK_FREQ - Reference Frequency(MHz) - 100.0 - - - PRECISION - Tolerance(MHz) - 1 - - - PRIMITIVE - Primitive - MMCM - - - PRIMTYPE_SEL - Primtype Sel - mmcm_adv - - - CLOCK_MGR_TYPE - Clock Mgr Type - auto - - - USE_FREQ_SYNTH - true - - - USE_SPREAD_SPECTRUM - false - - - USE_PHASE_ALIGNMENT - true - - - USE_MIN_POWER - false - - - USE_DYN_PHASE_SHIFT - false - - - USE_DYN_RECONFIG - false - - - JITTER_SEL - No_Jitter - - - PRIM_IN_FREQ - 200.000 - - - PRIM_IN_TIMEPERIOD - 10.000 - - - IN_FREQ_UNITS - Units_MHz - - - PHASESHIFT_MODE - WAVEFORM - - - IN_JITTER_UNITS - Units_UI - - - RELATIVE_INCLK - REL_PRIMARY - - - USE_INCLK_SWITCHOVER - false - - - SECONDARY_IN_FREQ - 100.000 - - - SECONDARY_IN_TIMEPERIOD - 10.000 - - - SECONDARY_PORT - clk_in2 - - - SECONDARY_SOURCE - Single_ended_clock_capable_pin - - - JITTER_OPTIONS - UI - - - CLKIN1_UI_JITTER - 0.010 - - - CLKIN2_UI_JITTER - 0.010 - - - PRIM_IN_JITTER - 0.010 - - - SECONDARY_IN_JITTER - 0.010 - - - CLKIN1_JITTER_PS - 50.0 - - - CLKIN2_JITTER_PS - 100.0 - - - CLKOUT1_USED - true - - - CLKOUT2_USED - false - - - CLKOUT3_USED - false - - - CLKOUT4_USED - false - - - CLKOUT5_USED - false - - - CLKOUT6_USED - false - - - CLKOUT7_USED - false - - - NUM_OUT_CLKS - 1 - - - CLK_OUT1_USE_FINE_PS_GUI - false - - - CLK_OUT2_USE_FINE_PS_GUI - false - - - CLK_OUT3_USE_FINE_PS_GUI - false - - - CLK_OUT4_USE_FINE_PS_GUI - false - - - CLK_OUT5_USE_FINE_PS_GUI - false - - - CLK_OUT6_USE_FINE_PS_GUI - false - - - CLK_OUT7_USE_FINE_PS_GUI - false - - - PRIMARY_PORT - clk_in1 - - - CLK_OUT1_PORT - clk_out1 - - - CLK_OUT2_PORT - clk_out2 - - - CLK_OUT3_PORT - clk_out3 - - - CLK_OUT4_PORT - clk_out4 - - - CLK_OUT5_PORT - clk_out5 - - - CLK_OUT6_PORT - clk_out6 - - - CLK_OUT7_PORT - clk_out7 - - - DADDR_PORT - daddr - - - DCLK_PORT - dclk - - - DRDY_PORT - drdy - - - DWE_PORT - dwe - - - DIN_PORT - din - - - DOUT_PORT - dout - - - DEN_PORT - den - - - PSCLK_PORT - psclk - - - PSEN_PORT - psen - - - PSINCDEC_PORT - psincdec - - - PSDONE_PORT - psdone - - - CLKOUT1_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT1_REQUESTED_PHASE - 0.000 - - - CLKOUT1_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT2_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT2_REQUESTED_PHASE - 0.000 - - - CLKOUT2_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT3_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT3_REQUESTED_PHASE - 0.000 - - - CLKOUT3_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT4_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT4_REQUESTED_PHASE - 0.000 - - - CLKOUT4_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT5_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT5_REQUESTED_PHASE - 0.000 - - - CLKOUT5_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT6_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT6_REQUESTED_PHASE - 0.000 - - - CLKOUT6_REQUESTED_DUTY_CYCLE - 50.000 - - - CLKOUT7_REQUESTED_OUT_FREQ - 100.000 - - - CLKOUT7_REQUESTED_PHASE - 0.000 - - - CLKOUT7_REQUESTED_DUTY_CYCLE - 50.000 - - - USE_MAX_I_JITTER - false - - - USE_MIN_O_JITTER - false - - - CLKOUT1_MATCHED_ROUTING - false - - - CLKOUT2_MATCHED_ROUTING - false - - - CLKOUT3_MATCHED_ROUTING - false - - - CLKOUT4_MATCHED_ROUTING - false - - - CLKOUT5_MATCHED_ROUTING - false - - - CLKOUT6_MATCHED_ROUTING - false - - - CLKOUT7_MATCHED_ROUTING - false - - - PRIM_SOURCE - Differential_clock_capable_pin - - - CLKOUT1_DRIVES - Buffer - - - CLKOUT2_DRIVES - Buffer - - - CLKOUT3_DRIVES - Buffer - - - CLKOUT4_DRIVES - Buffer - - - CLKOUT5_DRIVES - Buffer - - - CLKOUT6_DRIVES - Buffer - - - CLKOUT7_DRIVES - Buffer - - - FEEDBACK_SOURCE - FDBK_AUTO - - - CLKFB_IN_SIGNALING - SINGLE - - - CLKFB_IN_PORT - clkfb_in - - - CLKFB_IN_P_PORT - clkfb_in_p - - - CLKFB_IN_N_PORT - clkfb_in_n - - - CLKFB_OUT_PORT - clkfb_out - - - CLKFB_OUT_P_PORT - clkfb_out_p - - - CLKFB_OUT_N_PORT - clkfb_out_n - - - PLATFORM - UNKNOWN - - - SUMMARY_STRINGS - empty - - - USE_LOCKED - true - - - CALC_DONE - empty - - - USE_RESET - true - - - USE_POWER_DOWN - false - - - USE_STATUS - false - - - USE_FREEZE - false - - - USE_CLK_VALID - false - - - USE_INCLK_STOPPED - false - - - USE_CLKFB_STOPPED - false - - - RESET_PORT - reset - - - LOCKED_PORT - locked - - - POWER_DOWN_PORT - power_down - - - CLK_VALID_PORT - CLK_VALID - - - STATUS_PORT - STATUS - - - CLK_IN_SEL_PORT - clk_in_sel - - - INPUT_CLK_STOPPED_PORT - input_clk_stopped - - - CLKFB_STOPPED_PORT - clkfb_stopped - - - SS_MODE - CENTER_HIGH - - - SS_MOD_FREQ - 250 - - - SS_MOD_TIME - 0.004 - - - OVERRIDE_MMCM - false - - - MMCM_NOTES - None - - - MMCM_DIVCLK_DIVIDE - 1 - - - MMCM_BANDWIDTH - OPTIMIZED - - - MMCM_CLKFBOUT_MULT_F - 5.000 - - - MMCM_CLKFBOUT_PHASE - 0.000 - - - MMCM_CLKFBOUT_USE_FINE_PS - false - - - MMCM_CLKIN1_PERIOD - 5.000 - - - MMCM_CLKIN2_PERIOD - 10.0 - - - MMCM_CLKOUT4_CASCADE - false - - - MMCM_CLOCK_HOLD - false - - - MMCM_COMPENSATION - AUTO - - - MMCM_REF_JITTER1 - 0.010 - - - MMCM_REF_JITTER2 - 0.010 - - - MMCM_STARTUP_WAIT - false - - - MMCM_CLKOUT0_DIVIDE_F - 10.000 - - - MMCM_CLKOUT0_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT0_PHASE - 0.000 - - - MMCM_CLKOUT0_USE_FINE_PS - false - - - MMCM_CLKOUT1_DIVIDE - 1 - - - MMCM_CLKOUT1_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT1_PHASE - 0.000 - - - MMCM_CLKOUT1_USE_FINE_PS - false - - - MMCM_CLKOUT2_DIVIDE - 1 - - - MMCM_CLKOUT2_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT2_PHASE - 0.000 - - - MMCM_CLKOUT2_USE_FINE_PS - false - - - MMCM_CLKOUT3_DIVIDE - 1 - - - MMCM_CLKOUT3_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT3_PHASE - 0.000 - - - MMCM_CLKOUT3_USE_FINE_PS - false - - - MMCM_CLKOUT4_DIVIDE - 1 - - - MMCM_CLKOUT4_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT4_PHASE - 0.000 - - - MMCM_CLKOUT4_USE_FINE_PS - false - - - MMCM_CLKOUT5_DIVIDE - 1 - - - MMCM_CLKOUT5_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT5_PHASE - 0.000 - - - MMCM_CLKOUT5_USE_FINE_PS - false - - - MMCM_CLKOUT6_DIVIDE - 1 - - - MMCM_CLKOUT6_DUTY_CYCLE - 0.500 - - - MMCM_CLKOUT6_PHASE - 0.000 - - - MMCM_CLKOUT6_USE_FINE_PS - false - - - OVERRIDE_PLL - false - - - PLL_NOTES - None - - - PLL_BANDWIDTH - OPTIMIZED - - - PLL_CLKFBOUT_MULT - 4 - - - PLL_CLKFBOUT_PHASE - 0.000 - - - PLL_CLK_FEEDBACK - CLKFBOUT - - - PLL_DIVCLK_DIVIDE - 1 - - - PLL_CLKIN_PERIOD - 10.000 - - - PLL_COMPENSATION - SYSTEM_SYNCHRONOUS - - - PLL_REF_JITTER - 0.010 - - - PLL_CLKOUT0_DIVIDE - 1 - - - PLL_CLKOUT0_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT0_PHASE - 0.000 - - - PLL_CLKOUT1_DIVIDE - 1 - - - PLL_CLKOUT1_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT1_PHASE - 0.000 - - - PLL_CLKOUT2_DIVIDE - 1 - - - PLL_CLKOUT2_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT2_PHASE - 0.000 - - - PLL_CLKOUT3_DIVIDE - 1 - - - PLL_CLKOUT3_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT3_PHASE - 0.000 - - - PLL_CLKOUT4_DIVIDE - 1 - - - PLL_CLKOUT4_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT4_PHASE - 0.000 - - - PLL_CLKOUT5_DIVIDE - 1 - - - PLL_CLKOUT5_DUTY_CYCLE - 0.500 - - - PLL_CLKOUT5_PHASE - 0.000 - - - RESET_TYPE - Reset Type - ACTIVE_HIGH - - - USE_SAFE_CLOCK_STARTUP - false - - - USE_CLOCK_SEQUENCING - false - - - CLKOUT1_SEQUENCE_NUMBER - 1 - - - CLKOUT2_SEQUENCE_NUMBER - 1 - - - CLKOUT3_SEQUENCE_NUMBER - 1 - - - CLKOUT4_SEQUENCE_NUMBER - 1 - - - CLKOUT5_SEQUENCE_NUMBER - 1 - - - CLKOUT6_SEQUENCE_NUMBER - 1 - - - CLKOUT7_SEQUENCE_NUMBER - 1 - - - USE_BOARD_FLOW - Generate Board based IO Constraints - false - - - CLK_IN1_BOARD_INTERFACE - Custom - - - CLK_IN2_BOARD_INTERFACE - Custom - - - DIFF_CLK_IN1_BOARD_INTERFACE - Custom - - - DIFF_CLK_IN2_BOARD_INTERFACE - Custom - - - AUTO_PRIMITIVE - MMCM - - - RESET_BOARD_INTERFACE - Custom - - - ENABLE_CDDC - false - - - CDDCDONE_PORT - cddcdone - - - CDDCREQ_PORT - cddcreq - - - ENABLE_CLKOUTPHY - false - - - CLKOUTPHY_REQUESTED_FREQ - 600.000 - - - CLKOUT1_JITTER - Clkout1 Jitter - 112.316 - - - CLKOUT1_PHASE_ERROR - Clkout1 Phase - 89.971 - - - CLKOUT2_JITTER - Clkout2 Jitter - 0.0 - - - CLKOUT2_PHASE_ERROR - Clkout2 Phase - 0.0 - - - CLKOUT3_JITTER - Clkout3 Jitter - 0.0 - - - CLKOUT3_PHASE_ERROR - Clkout3 Phase - 0.0 - - - CLKOUT4_JITTER - Clkout4 Jitter - 0.0 - - - CLKOUT4_PHASE_ERROR - Clkout4 Phase - 0.0 - - - CLKOUT5_JITTER - Clkout5 Jitter - 0.0 - - - CLKOUT5_PHASE_ERROR - Clkout5 Phase - 0.0 - - - CLKOUT6_JITTER - Clkout6 Jitter - 0.0 - - - CLKOUT6_PHASE_ERROR - Clkout6 Phase - 0.0 - - - CLKOUT7_JITTER - Clkout7 Jitter - 0.0 - - - CLKOUT7_PHASE_ERROR - Clkout7 Phase - 0.0 - - - INPUT_MODE - frequency - - - INTERFACE_SELECTION - Enable_AXI - - - AXI_DRP - Write DRP registers - false - - - PHASE_DUTY_CONFIG - Phase Duty Cycle Config - false - - - - - Clocking Wizard - - XPM_CDC - - 5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.1 - - - - - - - - diff --git a/hub_test/src/hub_test.vhd b/hub_test/src/hub_test.vhd index 3592497..fb93eb8 100644 --- a/hub_test/src/hub_test.vhd +++ b/hub_test/src/hub_test.vhd @@ -18,7 +18,7 @@ entity hub_test is SI5345_IN0_P : out std_logic; -- 100 MHz SI5345_IN0_N : out std_logic; - SI5345_OUT7_P : in std_logic; -- 100 MHz + SI5345_OUT7_P : in std_logic; -- 100 MHz, derived from SI5345_IN0_P SI5345_OUT7_N : in std_logic; MPOD_RX1_RESET_N : out std_logic; @@ -33,13 +33,13 @@ entity hub_test is PEX_I2C_SEL1 : out std_logic; UC_RESET_N : out std_logic; - MGTREFCLK_P : in std_logic; -- 100 MHz, sync. with SI5345_IN0_P + MGTREFCLK_P : in std_logic; -- 100 MHz, sync. with SI5345_OUT7_P MGTREFCLK_N : in std_logic; - RXN : in std_logic_vector(11 downto 0); - RXP : in std_logic_vector(11 downto 0); - TXN : out std_logic_vector(11 downto 0); - TXP : out std_logic_vector(11 downto 0); + RXN : in std_logic_vector(INTERFACE_NUM - 1 downto 0); + RXP : in std_logic_vector(INTERFACE_NUM - 1 downto 0); + TXN : out std_logic_vector(INTERFACE_NUM - 1 downto 0); + TXP : out std_logic_vector(INTERFACE_NUM - 1 downto 0); SDA : inout std_logic; SCL : inout std_logic; @@ -107,6 +107,10 @@ architecture behavioral of hub_test is ); end component; + type linknum_type is array (0 to 9) of integer; + constant mgtnum_from_linknum : linknum_type + := (5, 4, 6, 7, 11, 8, 9, 3, 1, 10); + signal clk_200_ibuf : std_logic; signal baseclk_100 : std_logic; signal baseclk_out : std_logic; @@ -117,10 +121,9 @@ architecture behavioral of hub_test is signal sysclk_200 : std_logic; signal sysclk_locked : std_logic; - signal usrclk_vec : std_logic_vector(3 downto 0); - signal usrclk_double_vec : std_logic_vector(3 downto 0); - signal mgtrefclk : std_logic; + signal mgtrefclk_hrow : std_logic; + signal mgtrefclk_bufg : std_logic; signal initial_clear_timer : unsigned(27 downto 0) := (others => '0'); signal initial_clear_n : std_logic := '0'; @@ -138,8 +141,6 @@ architecture behavioral of hub_test is signal med2int_i : med2int_array_t(0 to 10); signal int2med_i : int2med_array_t(0 to 10); - signal med2int_unused : med2int_array_t(0 to 1); - signal int2med_unused : int2med_array_t(0 to 1); signal ctrlbus_rx_i : CTRLBUS_RX; signal bussci1_rx : CTRLBUS_RX; @@ -239,19 +240,19 @@ architecture behavioral of hub_test is signal trg_out : std_logic := '0'; signal dlm : std_logic := '0'; - signal drpaddr : std_logic_vector(35 downto 0) := (others => '0'); - signal drpclk : std_logic_vector(3 downto 0) := (others => '0'); - signal drpdi : std_logic_vector(63 downto 0) := (others => '0'); - signal drpen : std_logic_vector(3 downto 0) := (others => '0'); - signal drpwe : std_logic_vector(3 downto 0) := (others => '0'); - signal drpdo : std_logic_vector(63 downto 0); - signal drprdy : std_logic_vector(3 downto 0); - signal eyescanreset : std_logic_vector(3 downto 0) := (others => '0'); - signal rxlpmen : std_logic_vector(3 downto 0) := (others => '0'); - signal rxrate : std_logic_vector(11 downto 0) := (others => '0'); - signal txdiffctrl : std_logic_vector(15 downto 0) := b"1100_1100_1100_1100"; - signal txpostcursor : std_logic_vector(19 downto 0) := (others => '0'); - signal txprecursor : std_logic_vector(19 downto 0) := (others => '0'); + signal drpaddr : std_logic_vector(17 downto 0) := (others => '0'); + signal drpclk : std_logic_vector(1 downto 0) := (others => '0'); + signal drpdi : std_logic_vector(31 downto 0) := (others => '0'); + signal drpen : std_logic_vector(1 downto 0) := (others => '0'); + signal drpwe : std_logic_vector(1 downto 0) := (others => '0'); + signal drpdo : std_logic_vector(31 downto 0); + signal drprdy : std_logic_vector(1 downto 0); + signal eyescanreset : std_logic_vector(1 downto 0) := b"0_0"; + signal rxlpmen : std_logic_vector(1 downto 0) := b"1_1"; + signal rxrate : std_logic_vector(5 downto 0) := b"000_000"; + signal txdiffctrl : std_logic_vector(7 downto 0) := b"1100_1100"; + signal txpostcursor : std_logic_vector(9 downto 0) := b"00000_00000"; + signal txprecursor : std_logic_vector(9 downto 0) := b"00000_00000"; begin IBUFDS_baseclk : IBUFDS port map ( @@ -307,13 +308,29 @@ begin clk_in1_n => SI5345_OUT7_N ); - THE_MGTREFCLK0_X0Y3 : IBUFDS_GTE3 + THE_MGTREFCLK1_X0Y3 : IBUFDS_GTE3 + generic map ( + REFCLK_EN_TX_PATH => '0', + REFCLK_HROW_CK_SEL => "00", + REFCLK_ICNTL_RX => "00" + ) port map ( I => MGTREFCLK_P, IB => MGTREFCLK_N, - CEB => '0', + CEB => mb_sysclk_reset, O => mgtrefclk, - ODIV2 => open + ODIV2 => mgtrefclk_hrow + ); + + BUFG_GT_MGTREFCLK1_X0Y3 : BUFG_GT + port map ( + O => mgtrefclk_bufg, + CE => '1', + CEMASK => '0', + CLR => mb_sysclk_reset, + CLRMASK => '0', + DIV => "000", + I => mgtrefclk_hrow ); THE_VIO : vio_0 @@ -360,79 +377,152 @@ begin DEBUG_OUT => open ); - usrclk_vec <= sysclk_100 & sysclk_100 & sysclk_100 & sysclk_100; - usrclk_double_vec <= sysclk_200 & sysclk_200 & sysclk_200 & sysclk_200; - THE_MEDIA_4_PCSB : entity work.med_xcku_sfp_sync_4 + THE_UPLINK : entity work.med_xcku_sfp_sync generic map ( - IS_SYNC_SLAVE => (c_YES, c_NO, c_NO, c_NO), - IS_USED => (c_YES,c_YES ,c_YES ,c_YES) + IS_SYNC_SLAVE => c_YES, + LINE_RATE_KBPS => 2000000, + REFCLK_FREQ_HZ => 100000000 ) port map ( SYSCLK => sysclk_100, - CLK_200 => sysclk_200, + CLK_100 => baseclk_100, GTREFCLK => mgtrefclk, + GTREFCLK_BUFG => mgtrefclk_bufg, RXOUTCLK => open, TXOUTCLK => open, - RXUSRCLK => usrclk_vec, - RXUSRCLK_DOUBLE => usrclk_double_vec, - TXUSRCLK => usrclk_vec, - TXUSRCLK_DOUBLE => usrclk_double_vec, + RXUSRCLK => sysclk_100, + RXUSRCLK_DOUBLE => sysclk_200, + TXUSRCLK => sysclk_100, + TXUSRCLK_DOUBLE => sysclk_200, RXUSRCLK_ACTIVE => sysclk_locked, TXUSRCLK_ACTIVE => sysclk_locked, RXPMARESETDONE => open, TXPMARESETDONE => open, RESET => reset, CLEAR => clear, - RXN => RXN(3 downto 0), - RXP => RXP(3 downto 0), - TXN => TXN(3 downto 0), - TXP => TXP(3 downto 0), - MEDIA_MED2INT(0) => med2int_i(INTERFACE_NUM - 1), - MEDIA_MED2INT(1) => med2int_i(4), - MEDIA_MED2INT(2) => med2int_i(5), - MEDIA_MED2INT(3) => med2int_i(6), - MEDIA_INT2MED(0) => int2med_i(INTERFACE_NUM - 1), - MEDIA_INT2MED(1) => int2med_i(4), - MEDIA_INT2MED(2) => int2med_i(5), - MEDIA_INT2MED(3) => int2med_i(6), + RXN => RXN(INTERFACE_NUM - 1), + RXP => RXP(INTERFACE_NUM - 1), + TXN => TXN(INTERFACE_NUM - 1), + TXP => TXP(INTERFACE_NUM - 1), + MEDIA_MED2INT => med2int_i(INTERFACE_NUM - 1), + MEDIA_INT2MED => int2med_i(INTERFACE_NUM - 1), RX_DLM => open, RX_DLM_WORD => open, - TX_DLM(0) => '0', - TX_DLM(1) => dlm, - TX_DLM(2) => dlm, - TX_DLM(3) => dlm, - TX_DLM_WORD => x"00_00_00_00", - SD_LOS_IN(0) => mpod_a_los(10), - SD_LOS_IN(1) => mpod_a_los(11), - SD_LOS_IN(2) => mpod_a_los(8), - SD_LOS_IN(3) => mpod_a_los(9), - SD_TXDIS_OUT(0) => mpod_a_txdis(10), - SD_TXDIS_OUT(1) => mpod_a_txdis(11), - SD_TXDIS_OUT(2) => mpod_a_txdis(8), - SD_TXDIS_OUT(3) => mpod_a_txdis(9), - BUS_RX => bussci2_rx, - BUS_TX => bussci2_tx, + TX_DLM => '0', + TX_DLM_WORD => x"00", + SD_LOS_IN => mpod_a_los(mgtnum_from_linknum(INTERFACE_NUM - 1)), + SD_TXDIS_OUT => mpod_a_txdis(mgtnum_from_linknum(INTERFACE_NUM - 1)), STAT_DEBUG => open, CTRL_DEBUG => (others => '0'), - DRPADDR => drpaddr, - DRPCLK => drpclk, - DRPDI => drpdi, - DRPEN => drpen, - DRPWE => drpwe, - DRPDO => drpdo, - DRPRDY => drprdy, - EYESCANRESET => eyescanreset, - RXLPMEN => rxlpmen, - RXRATE => rxrate, - TXDIFFCTRL => txdiffctrl, - TXPOSTCURSOR => txpostcursor, - TXPRECURSOR => txprecursor + DRPADDR => drpaddr(8 downto 0), + DRPCLK => drpclk(0), + DRPDI => drpdi(15 downto 0), + DRPEN => drpen(0), + DRPWE => drpwe(0), + DRPDO => drpdo(15 downto 0), + DRPRDY => drprdy(0), + EYESCANRESET => eyescanreset(0), + RXLPMEN => rxlpmen(0), + RXRATE => rxrate(2 downto 0), + TXDIFFCTRL => txdiffctrl(3 downto 0), + TXPOSTCURSOR => txpostcursor(4 downto 0), + TXPRECURSOR => txprecursor(4 downto 0) ); + + generate_downlinks: + for linknum in 0 to INTERFACE_NUM - 2 generate + signal drpaddr_i : std_logic_vector(8 downto 0) := (others => '0'); + signal drpclk_i : std_logic := '0'; + signal drpdi_i : std_logic_vector(15 downto 0) := (others => '0'); + signal drpen_i : std_logic := '0'; + signal drpwe_i : std_logic := '0'; + signal drpdo_i : std_logic_vector(15 downto 0); + signal drprdy_i : std_logic; + + signal eyescanreset_i : std_logic := '0'; + signal rxlpmen_i : std_logic := '1'; + signal rxrate_i : std_logic_vector(2 downto 0) := b"000"; + signal txdiffctrl_i : std_logic_vector(3 downto 0) := b"1100"; + signal txpostcursor_i : std_logic_vector(4 downto 0) := b"00000"; + signal txprecursor_i : std_logic_vector(4 downto 0) := b"00000"; + begin + THE_DOWNLINK : entity work.med_xcku_sfp_sync + generic map ( + IS_SYNC_SLAVE => c_NO, + LINE_RATE_KBPS => 2000000, + REFCLK_FREQ_HZ => 100000000 + ) + port map ( + SYSCLK => sysclk_100, + CLK_100 => baseclk_100, + GTREFCLK => mgtrefclk, + GTREFCLK_BUFG => mgtrefclk_bufg, + RXOUTCLK => open, + TXOUTCLK => open, + RXUSRCLK => sysclk_100, + RXUSRCLK_DOUBLE => sysclk_200, + TXUSRCLK => sysclk_100, + TXUSRCLK_DOUBLE => sysclk_200, + RXUSRCLK_ACTIVE => sysclk_locked, + TXUSRCLK_ACTIVE => sysclk_locked, + RXPMARESETDONE => open, + TXPMARESETDONE => open, + RESET => reset, + CLEAR => clear, + RXN => RXN(linknum), + RXP => RXP(linknum), + TXN => TXN(linknum), + TXP => TXP(linknum), + MEDIA_MED2INT => med2int_i(linknum), + MEDIA_INT2MED => int2med_i(linknum), + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => dlm, + TX_DLM_WORD => x"00", + SD_LOS_IN => mpod_a_los(mgtnum_from_linknum(linknum)), + SD_TXDIS_OUT => mpod_a_txdis(mgtnum_from_linknum(linknum)), + STAT_DEBUG => open, + CTRL_DEBUG => (others => '0'), + DRPADDR => drpaddr_i, + DRPCLK => drpclk_i, + DRPDI => drpdi_i, + DRPEN => drpen_i, + DRPWE => drpwe_i, + DRPDO => drpdo_i, + DRPRDY => drprdy_i, + EYESCANRESET => eyescanreset_i, + RXLPMEN => rxlpmen_i, + RXRATE => rxrate_i, + TXDIFFCTRL => txdiffctrl_i, + TXPOSTCURSOR => txpostcursor_i, + TXPRECURSOR => txprecursor_i + ); + + generate_downlink_4: + if linknum = 4 generate + begin + drpen_i <= drpen(1); + drpwe_i <= drpwe(1); + drpaddr_i <= drpaddr(17 downto 9); + drpdi_i <= drpdi(31 downto 16); + drprdy(1) <= drprdy_i; + drpdo(31 downto 16) <= drpdo_i; + + eyescanreset_i <= eyescanreset(1); + rxlpmen_i <= rxlpmen(1); + rxrate_i <= rxrate(5 downto 3); + txdiffctrl_i <= txdiffctrl(7 downto 4); + txpostcursor_i <= txpostcursor(9 downto 5); + txprecursor_i <= txprecursor(9 downto 5); + end generate generate_downlink_4; + end generate generate_downlinks; + + in_system_ibert_0_i : in_system_ibert_0 port map ( - drpclk_o => drpclk(1 downto 0), + drpclk_o => drpclk, gt0_drpen_o => drpen(0), gt0_drpwe_o => drpwe(0), gt0_drpaddr_o => drpaddr(8 downto 0), @@ -445,12 +535,12 @@ begin gt1_drpdi_o => drpdi(31 downto 16), gt1_drprdy_i => drprdy(1), gt1_drpdo_i => drpdo(31 downto 16), - eyescanreset_o => eyescanreset(1 downto 0), - rxrate_o => rxrate(5 downto 0), - txdiffctrl_o => txdiffctrl(7 downto 0), - txprecursor_o => txprecursor(9 downto 0), - txpostcursor_o => txpostcursor(9 downto 0), - rxlpmen_o => rxlpmen(1 downto 0), + eyescanreset_o => eyescanreset, + rxrate_o => rxrate, + txdiffctrl_o => txdiffctrl, + txprecursor_o => txprecursor, + txpostcursor_o => txpostcursor, + rxlpmen_o => rxlpmen, rxrate_i => b"000_000", txdiffctrl_i => b"1100_1100", txprecursor_i => b"00000_00000", @@ -516,116 +606,6 @@ begin ); - THE_MEDIA_4_PCSC : entity work.med_xcku_sfp_sync_4 - generic map ( - IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO), - IS_USED => (c_YES,c_YES ,c_YES ,c_YES) - ) - port map ( - SYSCLK => sysclk_100, - CLK_200 => sysclk_200, - GTREFCLK => mgtrefclk, - RXOUTCLK => open, - TXOUTCLK => open, - RXUSRCLK => usrclk_vec, - RXUSRCLK_DOUBLE => usrclk_double_vec, - TXUSRCLK => usrclk_vec, - TXUSRCLK_DOUBLE => usrclk_double_vec, - RXUSRCLK_ACTIVE => sysclk_locked, - TXUSRCLK_ACTIVE => sysclk_locked, - RXPMARESETDONE => open, - TXPMARESETDONE => open, - RESET => reset, - CLEAR => clear, - RXN => RXN(7 downto 4), - RXP => RXP(7 downto 4), - TXN => TXN(7 downto 4), - TXP => TXP(7 downto 4), - MEDIA_MED2INT(0) => med2int_i(2), - MEDIA_MED2INT(1) => med2int_i(3), - MEDIA_MED2INT(2) => med2int_i(0), - MEDIA_MED2INT(3) => med2int_i(1), - MEDIA_INT2MED(0) => int2med_i(2), - MEDIA_INT2MED(1) => int2med_i(3), - MEDIA_INT2MED(2) => int2med_i(0), - MEDIA_INT2MED(3) => int2med_i(1), - RX_DLM => open, - RX_DLM_WORD => open, - TX_DLM(0) => dlm, - TX_DLM(1) => dlm, - TX_DLM(2) => dlm, - TX_DLM(3) => dlm, - TX_DLM_WORD => x"00_00_00_00", - SD_LOS_IN(0) => mpod_a_los(6), - SD_LOS_IN(1) => mpod_a_los(7), - SD_LOS_IN(2) => mpod_a_los(5), - SD_LOS_IN(3) => mpod_a_los(4), - SD_TXDIS_OUT(0) => mpod_a_txdis(6), - SD_TXDIS_OUT(1) => mpod_a_txdis(7), - SD_TXDIS_OUT(2) => mpod_a_txdis(5), - SD_TXDIS_OUT(3) => mpod_a_txdis(4), - BUS_RX => bussci3_rx, - BUS_TX => bussci3_tx, - STAT_DEBUG => open, - CTRL_DEBUG => (others => '0') - ); - - - THE_MEDIA_4_PCSD : entity work.med_xcku_sfp_sync_4 - generic map ( - IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO), - IS_USED => (c_YES,c_YES ,c_NO ,c_NO) - ) - port map ( - SYSCLK => sysclk_100, - CLK_200 => sysclk_200, - GTREFCLK => mgtrefclk, - RXOUTCLK => open, - TXOUTCLK => open, - RXUSRCLK => usrclk_vec, - RXUSRCLK_DOUBLE => usrclk_double_vec, - TXUSRCLK => usrclk_vec, - TXUSRCLK_DOUBLE => usrclk_double_vec, - RXUSRCLK_ACTIVE => sysclk_locked, - TXUSRCLK_ACTIVE => sysclk_locked, - RXPMARESETDONE => open, - TXPMARESETDONE => open, - RESET => reset, - CLEAR => clear, - RXN => RXN(11 downto 8), - RXP => RXP(11 downto 8), - TXN => TXN(11 downto 8), - TXP => TXP(11 downto 8), - MEDIA_MED2INT(0) => med2int_i(8), - MEDIA_MED2INT(1) => med2int_i(7), - MEDIA_MED2INT(2) => med2int_unused(1), - MEDIA_MED2INT(3) => med2int_unused(0), - MEDIA_INT2MED(0) => int2med_i(8), - MEDIA_INT2MED(1) => int2med_i(7), - MEDIA_INT2MED(2) => int2med_unused(1), - MEDIA_INT2MED(3) => int2med_unused(0), - RX_DLM => open, - RX_DLM_WORD => open, - TX_DLM(0) => dlm, - TX_DLM(1) => dlm, - TX_DLM(2) => dlm, - TX_DLM(3) => dlm, - TX_DLM_WORD => x"00_00_00_00", - SD_LOS_IN(0) => mpod_a_los(1), - SD_LOS_IN(1) => mpod_a_los(3), - SD_LOS_IN(2) => mpod_a_los(2), - SD_LOS_IN(3) => mpod_a_los(0), - SD_TXDIS_OUT(0) => mpod_a_txdis(1), - SD_TXDIS_OUT(1) => mpod_a_txdis(3), - SD_TXDIS_OUT(2) => mpod_a_txdis(2), - SD_TXDIS_OUT(3) => mpod_a_txdis(0), - BUS_RX => bussci4_rx, - BUS_TX => bussci4_tx, - STAT_DEBUG => open, - CTRL_DEBUG => (others => '0') - ); - - THE_HUB : entity work.trb_net16_cri_hub generic map ( HUB_USED_CHANNELS => (0, 1, 0, 1), @@ -785,24 +765,36 @@ begin bustools_tx.data <= (others => '0'); bustc_tx.data <= (others => '0'); bussci1_tx.data <= (others => '0'); + bussci2_tx.data <= (others => '0'); + bussci3_tx.data <= (others => '0'); + bussci4_tx.data <= (others => '0'); busgbeip_tx.data <= (others => '0'); busgbereg_tx.data <= (others => '0'); bustools_tx.unknown <= bustools_rx.read or bustools_rx.write; bustc_tx.unknown <= bustc_rx.read or bustc_rx.write; bussci1_tx.unknown <= bussci1_rx.read or bussci1_rx.write; + bussci2_tx.unknown <= bussci2_rx.read or bussci2_rx.write; + bussci3_tx.unknown <= bussci3_rx.read or bussci3_rx.write; + bussci4_tx.unknown <= bussci4_rx.read or bussci4_rx.write; busgbeip_tx.unknown <= busgbeip_rx.read or busgbeip_rx.write; busgbereg_tx.unknown <= busgbereg_rx.read or busgbereg_rx.write; bustools_tx.ack <= '0'; bustc_tx.ack <= '0'; bussci1_tx.ack <= '0'; + bussci2_tx.ack <= '0'; + bussci3_tx.ack <= '0'; + bussci4_tx.ack <= '0'; busgbeip_tx.ack <= '0'; busgbereg_tx.ack <= '0'; bustools_tx.nack <= '0'; bustc_tx.nack <= '0'; bussci1_tx.nack <= '0'; + bussci2_tx.nack <= '0'; + bussci3_tx.nack <= '0'; + bussci4_tx.nack <= '0'; busgbeip_tx.nack <= '0'; busgbereg_tx.nack <= '0'; end if; -- 2.43.0