From 40909f86dc8ec248ef2defed7a94d6d08ddd3773 Mon Sep 17 00:00:00 2001
From: Peter Lemmens <p.j.j.lemmens@rug.nl>
Date: Thu, 11 Dec 2014 14:00:18 +0100
Subject: [PATCH] adding the DataConcentrator to the soda-git

---
 data_concentrator/data_concentrator.ldf       |  612 +++
 .../sources/DC_CF_MAX_correction.vhd          |  292 ++
 data_concentrator/sources/DC_LUT_package.vhd  | 3113 ++++++++++++++
 .../sources/DC_Quad_fiber_module.vhd          |  948 +++++
 .../sources/DC_check_timestamp.vhd            |  182 +
 data_concentrator/sources/DC_checkwave.vhd    |  145 +
 .../sources/DC_combine_pulses.vhd             |  418 ++
 .../sources/DC_data_wave_to_64bit.vhd         |  616 +++
 .../sources/DC_energy_correction.vhd          |  132 +
 data_concentrator/sources/DC_extract_data.vhd |  186 +
 data_concentrator/sources/DC_extract_wave.vhd |  374 ++
 .../sources/DC_fibermodule_interface.vhd      | 1001 +++++
 .../sources/DC_fifo32to8_SODA.vhd             |  195 +
 .../sources/DC_fifo8to32_SODA.vhd             |  155 +
 data_concentrator/sources/DC_histogram.vhd    |  274 ++
 .../sources/DC_max_lookuptable.vhd            |  102 +
 .../sources/DC_measure_frequency.vhd          |   90 +
 data_concentrator/sources/DC_module_TRB3.vhd  | 1602 +++++++
 data_concentrator/sources/DC_mux2to1.vhd      |  324 ++
 .../sources/DC_pulse_cross_switch.vhd         |  102 +
 .../sources/DC_read36bitsfifo.vhd             |  260 ++
 .../sources/DC_separate_data.vhd              |  454 ++
 .../sources/DC_slow_control_TRB3.vhd          |  647 +++
 .../sources/DC_slowcontrol_packetbuilder.vhd  |  368 ++
 .../DC_slowcontrol_receive_from_cpu.vhd       |  152 +
 .../sources/DC_slowcontrol_to_serial.vhd      |  278 ++
 data_concentrator/sources/DC_sorting_mux.vhd  |  471 +++
 data_concentrator/sources/DC_split_data.vhd   |  634 +++
 .../sources/DC_superburst2packet64.vhd        |  659 +++
 .../sources/DC_time_energy_LUTs.vhd           |  415 ++
 .../sources/DC_time_lookuptable.vhd           |  102 +
 .../sources/DC_timeshift_lookuptable.vhd      |  101 +
 .../sources/DC_wave2packet64.vhd              |  539 +++
 data_concentrator/sources/DC_wavemux.vhd      |  272 ++
 data_concentrator/sources/Panda_package.vhd   |  424 ++
 .../sources/SODA_packet_generator.vhd         |  387 ++
 .../sources/SODA_packet_receiver.vhd          |  313 ++
 data_concentrator/sources/blockmem.vhd        |   69 +
 .../sources/crc8_add_check32.vhd              |  140 +
 .../sources/crc8_add_check64.vhd              |  152 +
 .../sources/dataconversion_for_serdes.vhd     |  294 ++
 .../sources/gtpBufLayerPackage.vhd            |   24 +
 data_concentrator/sources/histogram.vhd       |  212 +
 .../sources/lattice/async_fifo_16x32.vhd      |   51 +
 .../sources/lattice/async_fifo_256x66.vhd     |   51 +
 .../sources/lattice/async_fifo_512x32.vhd     |   51 +
 .../sources/lattice/async_fifo_512x99.vhd     |   51 +
 .../sources/lattice/async_fifo_FWFT_16x32.vhd |  109 +
 .../lattice/async_fifo_FWFT_16x32_try1.vhd    |  173 +
 .../sources/lattice/async_fifo_af_512x32.vhd  |   54 +
 .../sources/lattice/async_fifo_af_512x36.vhd  |   54 +
 .../lattice/async_fifo_nn_16384x36.vhd        |   55 +
 .../lattice/async_fifo_nn_4096x103.vhd        |   55 +
 .../sources/lattice/async_fifo_nn_4096x36.vhd |   55 +
 .../lattice/async_fifo_nn_th_512x36.vhd       |   58 +
 .../async_fifo_nn_thfull_FWFT_512x36.vhd      |  116 +
 .../async_fifo_nn_thfull_FWFT_512x36_try1.vhd |  181 +
 .../async_fifo_nn_thfull_FWFT_512x36_try2.vhd |  117 +
 .../lattice/ecp3/async_fifo_16x32_ecp3.ipx    |    9 +
 .../lattice/ecp3/async_fifo_16x32_ecp3.lpc    |   47 +
 .../lattice/ecp3/async_fifo_16x32_ecp3.vhd    |  748 ++++
 .../ecp3/async_fifo_16x32_ecp3_tmpl.vhd       |   18 +
 .../lattice/ecp3/async_fifo_256x66_ecp3.ipx   |    9 +
 .../lattice/ecp3/async_fifo_256x66_ecp3.lpc   |   50 +
 .../lattice/ecp3/async_fifo_256x66_ecp3.vhd   | 1155 ++++++
 .../ecp3/async_fifo_256x66_ecp3_tmpl.vhd      |   18 +
 .../lattice/ecp3/async_fifo_512x32_ecp3.ipx   |    9 +
 .../lattice/ecp3/async_fifo_512x32_ecp3.lpc   |   50 +
 .../lattice/ecp3/async_fifo_512x32_ecp3.vhd   | 1195 ++++++
 .../ecp3/async_fifo_512x32_ecp3_tmpl.vhd      |   18 +
 .../lattice/ecp3/async_fifo_512x99_ecp3.ipx   |    9 +
 .../lattice/ecp3/async_fifo_512x99_ecp3.lpc   |   50 +
 .../lattice/ecp3/async_fifo_512x99_ecp3.vhd   | 1270 ++++++
 .../ecp3/async_fifo_512x99_ecp3_tmpl.vhd      |   18 +
 .../ecp3/async_fifo_af_512x32_ecp3.ipx        |    9 +
 .../ecp3/async_fifo_af_512x32_ecp3.lpc        |   47 +
 .../ecp3/async_fifo_af_512x32_ecp3.vhd        | 1350 ++++++
 .../ecp3/async_fifo_af_512x32_ecp3_tmpl.vhd   |   19 +
 .../ecp3/async_fifo_af_512x36_ecp3.ipx        |    9 +
 .../ecp3/async_fifo_af_512x36_ecp3.lpc        |   47 +
 .../ecp3/async_fifo_af_512x36_ecp3.vhd        | 1351 ++++++
 .../ecp3/async_fifo_af_512x36_ecp3_tmpl.vhd   |   19 +
 .../ecp3/async_fifo_nn_16384x36_ecp3.ipx      |    9 +
 .../ecp3/async_fifo_nn_16384x36_ecp3.lpc      |   47 +
 .../ecp3/async_fifo_nn_16384x36_ecp3.vhd      | 3696 +++++++++++++++++
 .../ecp3/async_fifo_nn_16384x36_ecp3_tmpl.vhd |   19 +
 .../ecp3/async_fifo_nn_4096x103_ecp3.ipx      |    9 +
 .../ecp3/async_fifo_nn_4096x103_ecp3.lpc      |   50 +
 .../ecp3/async_fifo_nn_4096x103_ecp3.vhd      | 3239 +++++++++++++++
 .../ecp3/async_fifo_nn_4096x103_ecp3_tmpl.vhd |   19 +
 .../ecp3/async_fifo_nn_4096x36_ecp3.ipx       |    9 +
 .../ecp3/async_fifo_nn_4096x36_ecp3.lpc       |   50 +
 .../ecp3/async_fifo_nn_4096x36_ecp3.vhd       | 2165 ++++++++++
 .../ecp3/async_fifo_nn_4096x36_ecp3_tmpl.vhd  |   19 +
 .../ecp3/async_fifo_nn_th_512x36_ecp3.ipx     |    9 +
 .../ecp3/async_fifo_nn_th_512x36_ecp3.lpc     |   47 +
 .../ecp3/async_fifo_nn_th_512x36_ecp3.vhd     | 1444 +++++++
 .../async_fifo_nn_th_512x36_ecp3_tmpl.vhd     |   19 +
 .../ecp3/async_fifo_nn_thfull_512x36_ecp3.ipx |    9 +
 .../ecp3/async_fifo_nn_thfull_512x36_ecp3.lpc |   50 +
 .../ecp3/async_fifo_nn_thfull_512x36_ecp3.vhd | 1450 +++++++
 .../async_fifo_nn_thfull_512x36_ecp3_tmpl.vhd |   19 +
 .../ecp3/async_fifo_nn_thfull_512x36_tmpl.vhd |   19 +
 .../sources/lattice/ecp3/pll_in100_out80M.ipx |    6 +
 .../sources/lattice/ecp3/pll_in100_out80M.lpc |   69 +
 .../sources/lattice/ecp3/pll_in100_out80M.vhd |  105 +
 .../lattice/ecp3/pll_in100_out80M_tmpl.vhd    |   13 +
 .../lattice/ecp3/pll_in125_out125_62M5.ipx    |    8 +
 .../lattice/ecp3/pll_in125_out125_62M5.lpc    |   69 +
 .../lattice/ecp3/pll_in125_out125_62M5.vhd    |  103 +
 .../ecp3/pll_in125_out125_62M5_tmpl.vhd       |   13 +
 .../lattice/ecp3/pll_in125_outshift.ipx       |    8 +
 .../lattice/ecp3/pll_in125_outshift.lpc       |   69 +
 .../lattice/ecp3/pll_in125_outshift.vhd       |  120 +
 .../lattice/ecp3/pll_in125_outshift_tmpl.vhd  |   17 +
 .../lattice/ecp3/pll_in200_out125_62M5.ipx    |    8 +
 .../lattice/ecp3/pll_in200_out125_62M5.lpc    |   66 +
 .../lattice/ecp3/pll_in200_out125_62M5.vhd    |  106 +
 .../ecp3/pll_in200_out125_62M5_tmpl.vhd       |   13 +
 .../lattice/ecp3/pll_in200_out160M_80M.ipx    |    8 +
 .../lattice/ecp3/pll_in200_out160M_80M.lpc    |   69 +
 .../lattice/ecp3/pll_in200_out160M_80M.vhd    |  102 +
 .../ecp3/pll_in200_out160M_80M_tmpl.vhd       |   13 +
 .../lattice/ecp3/pll_in200_out200M_100M.ipx   |    6 +
 .../lattice/ecp3/pll_in200_out200M_100M.lpc   |   69 +
 .../lattice/ecp3/pll_in200_out200M_100M.vhd   |  103 +
 .../ecp3/pll_in200_out200M_100M_tmpl.vhd      |   13 +
 .../lattice/ecp3/pll_in62M5_outshift.ipx      |    8 +
 .../lattice/ecp3/pll_in62M5_outshift.lpc      |   69 +
 .../lattice/ecp3/pll_in62M5_outshift.vhd      |  120 +
 .../lattice/ecp3/pll_in62M5_outshift_tmpl.vhd |   17 +
 .../lattice/ecp3/serdes_sync_125_full.ipx     |   11 +
 .../lattice/ecp3/serdes_sync_125_full.lpc     |  258 ++
 .../lattice/ecp3/serdes_sync_125_full.vhd     | 2810 +++++++++++++
 .../lattice/ecp3/serdes_sync_160_full.ipx     |   11 +
 .../lattice/ecp3/serdes_sync_160_full.lpc     |  258 ++
 .../lattice/ecp3/serdes_sync_160_full.vhd     | 2810 +++++++++++++
 .../lattice/ecp3/serdes_sync_200_full.ipx     |   11 +
 .../lattice/ecp3/serdes_sync_200_full.lpc     |  258 ++
 .../lattice/ecp3/serdes_sync_200_full.vhd     | 2810 +++++++++++++
 .../lattice/ecp3/sfp_1_2sync_3_200_int.ipx    |   11 +
 .../lattice/ecp3/sfp_1_2sync_3_200_int.lpc    |  258 ++
 .../lattice/ecp3/sfp_1_2sync_3_200_int.vhd    | 2753 ++++++++++++
 .../sources/lattice/ecp3/sfp_1_3_200_int.ipx  |   10 +
 .../sources/lattice/ecp3/sfp_1_3_200_int.lpc  |  258 ++
 .../sources/lattice/ecp3/sfp_1_3_200_int.vhd  | 3180 ++++++++++++++
 .../lattice/ecp3/sync_fifo_512x41_ecp3.ipx    |    9 +
 .../lattice/ecp3/sync_fifo_512x41_ecp3.lpc    |   48 +
 .../lattice/ecp3/sync_fifo_512x41_ecp3.vhd    |  691 +++
 .../ecp3/sync_fifo_512x41_ecp3_tmpl.vhd       |   16 +
 .../ecp3/tb_async_fifo_16x32_ecp3_tmpl.vhd    |  106 +
 .../ecp3/tb_async_fifo_256x66_ecp3_tmpl.vhd   |  106 +
 .../ecp3/tb_async_fifo_512x32_ecp3_tmpl.vhd   |  106 +
 .../ecp3/tb_async_fifo_512x99_ecp3_tmpl.vhd   |  106 +
 .../tb_async_fifo_af_512x32_ecp3_tmpl.vhd     |  107 +
 .../tb_async_fifo_af_512x36_ecp3_tmpl.vhd     |  107 +
 .../tb_async_fifo_nn_16384x36_ecp3_tmpl.vhd   |  108 +
 .../tb_async_fifo_nn_4096x103_ecp3_tmpl.vhd   |  108 +
 .../tb_async_fifo_nn_4096x36_ecp3_tmpl.vhd    |  108 +
 .../tb_async_fifo_nn_th_512x36_ecp3_tmpl.vhd  |  110 +
 ..._async_fifo_nn_thfull_512x36_ecp3_tmpl.vhd |  110 +
 .../tb_async_fifo_nn_thfull_512x36_tmpl.vhd   |  110 +
 .../ecp3/tb_sync_fifo_512x41_ecp3_tmpl.vhd    |   89 +
 .../sources/lattice/fifo_FWFT.vhd             |  123 +
 .../lattice/med_ecp3_quad_sfp_sync.vhd        |  879 ++++
 .../sources/lattice/phase_measurement.vhd     |  225 +
 .../sources/lattice/rx_reset_sm.vhd           |  196 +
 .../sources/lattice/sync_fifo_512x41.vhd      |   46 +
 .../trb_net16_med_1_2sync_3_ecp3_sfp.vhd      | 1216 ++++++
 .../trb_net16_med_1_2sync_3_ecp3_sfp_old.vhd  | 1151 +++++
 .../lattice/trb_net16_med_1_3_ecp3_sfp.vhd    | 1154 +++++
 .../sources/lattice/tx_reset_sm.vhd           |  174 +
 .../sources/posedge_to_pulse.vhd              |   72 +
 data_concentrator/sources/rxFifo_MUX.vhd      |  144 +
 .../sources/serdesQuadBufLayerMUX.vhd         |  695 ++++
 .../sources/serdesQuadMUXwrapper.vhd          |  370 ++
 data_concentrator/sources/shift_register.vhd  |   88 +
 .../sources/synchronizer_to_other_clock.vhd   |   91 +
 data_concentrator/sources/txFifo_MUX.vhd      |  144 +
 data_concentrator/test_module.vhd             |  174 +
 .../trb3_periph_data_concentrator.lpf         |  294 ++
 .../trb3_periph_data_concentrator.vhd         | 1480 +++++++
 ...ph_data_concentrator_only1error_200MHz.lpf |  268 ++
 .../trb3_periph_sodasource_constraints.lpf    |   53 +
 .../trb_net16_endpoint_data_concentrator.vhd  | 1079 +++++
 ...t16_endpoint_data_concentrator_handler.vhd |  801 ++++
 data_concentrator/version.vhd                 |   11 +
 187 files changed, 69552 insertions(+)
 create mode 100644 data_concentrator/data_concentrator.ldf
 create mode 100644 data_concentrator/sources/DC_CF_MAX_correction.vhd
 create mode 100644 data_concentrator/sources/DC_LUT_package.vhd
 create mode 100644 data_concentrator/sources/DC_Quad_fiber_module.vhd
 create mode 100644 data_concentrator/sources/DC_check_timestamp.vhd
 create mode 100644 data_concentrator/sources/DC_checkwave.vhd
 create mode 100644 data_concentrator/sources/DC_combine_pulses.vhd
 create mode 100644 data_concentrator/sources/DC_data_wave_to_64bit.vhd
 create mode 100644 data_concentrator/sources/DC_energy_correction.vhd
 create mode 100644 data_concentrator/sources/DC_extract_data.vhd
 create mode 100644 data_concentrator/sources/DC_extract_wave.vhd
 create mode 100644 data_concentrator/sources/DC_fibermodule_interface.vhd
 create mode 100644 data_concentrator/sources/DC_fifo32to8_SODA.vhd
 create mode 100644 data_concentrator/sources/DC_fifo8to32_SODA.vhd
 create mode 100644 data_concentrator/sources/DC_histogram.vhd
 create mode 100644 data_concentrator/sources/DC_max_lookuptable.vhd
 create mode 100644 data_concentrator/sources/DC_measure_frequency.vhd
 create mode 100644 data_concentrator/sources/DC_module_TRB3.vhd
 create mode 100644 data_concentrator/sources/DC_mux2to1.vhd
 create mode 100644 data_concentrator/sources/DC_pulse_cross_switch.vhd
 create mode 100644 data_concentrator/sources/DC_read36bitsfifo.vhd
 create mode 100644 data_concentrator/sources/DC_separate_data.vhd
 create mode 100644 data_concentrator/sources/DC_slow_control_TRB3.vhd
 create mode 100644 data_concentrator/sources/DC_slowcontrol_packetbuilder.vhd
 create mode 100644 data_concentrator/sources/DC_slowcontrol_receive_from_cpu.vhd
 create mode 100644 data_concentrator/sources/DC_slowcontrol_to_serial.vhd
 create mode 100644 data_concentrator/sources/DC_sorting_mux.vhd
 create mode 100644 data_concentrator/sources/DC_split_data.vhd
 create mode 100644 data_concentrator/sources/DC_superburst2packet64.vhd
 create mode 100644 data_concentrator/sources/DC_time_energy_LUTs.vhd
 create mode 100644 data_concentrator/sources/DC_time_lookuptable.vhd
 create mode 100644 data_concentrator/sources/DC_timeshift_lookuptable.vhd
 create mode 100644 data_concentrator/sources/DC_wave2packet64.vhd
 create mode 100644 data_concentrator/sources/DC_wavemux.vhd
 create mode 100644 data_concentrator/sources/Panda_package.vhd
 create mode 100644 data_concentrator/sources/SODA_packet_generator.vhd
 create mode 100644 data_concentrator/sources/SODA_packet_receiver.vhd
 create mode 100644 data_concentrator/sources/blockmem.vhd
 create mode 100644 data_concentrator/sources/crc8_add_check32.vhd
 create mode 100644 data_concentrator/sources/crc8_add_check64.vhd
 create mode 100644 data_concentrator/sources/dataconversion_for_serdes.vhd
 create mode 100644 data_concentrator/sources/gtpBufLayerPackage.vhd
 create mode 100644 data_concentrator/sources/histogram.vhd
 create mode 100644 data_concentrator/sources/lattice/async_fifo_16x32.vhd
 create mode 100644 data_concentrator/sources/lattice/async_fifo_256x66.vhd
 create mode 100644 data_concentrator/sources/lattice/async_fifo_512x32.vhd
 create mode 100644 data_concentrator/sources/lattice/async_fifo_512x99.vhd
 create mode 100644 data_concentrator/sources/lattice/async_fifo_FWFT_16x32.vhd
 create mode 100644 data_concentrator/sources/lattice/async_fifo_FWFT_16x32_try1.vhd
 create mode 100644 data_concentrator/sources/lattice/async_fifo_af_512x32.vhd
 create mode 100644 data_concentrator/sources/lattice/async_fifo_af_512x36.vhd
 create mode 100644 data_concentrator/sources/lattice/async_fifo_nn_16384x36.vhd
 create mode 100644 data_concentrator/sources/lattice/async_fifo_nn_4096x103.vhd
 create mode 100644 data_concentrator/sources/lattice/async_fifo_nn_4096x36.vhd
 create mode 100644 data_concentrator/sources/lattice/async_fifo_nn_th_512x36.vhd
 create mode 100644 data_concentrator/sources/lattice/async_fifo_nn_thfull_FWFT_512x36.vhd
 create mode 100644 data_concentrator/sources/lattice/async_fifo_nn_thfull_FWFT_512x36_try1.vhd
 create mode 100644 data_concentrator/sources/lattice/async_fifo_nn_thfull_FWFT_512x36_try2.vhd
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_16x32_ecp3.ipx
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_16x32_ecp3.lpc
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_16x32_ecp3.vhd
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_16x32_ecp3_tmpl.vhd
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_256x66_ecp3.ipx
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_256x66_ecp3.lpc
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_256x66_ecp3.vhd
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_256x66_ecp3_tmpl.vhd
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_512x32_ecp3.ipx
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_512x32_ecp3.lpc
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_512x32_ecp3.vhd
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_512x32_ecp3_tmpl.vhd
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_512x99_ecp3.ipx
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_512x99_ecp3.lpc
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_512x99_ecp3.vhd
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_512x99_ecp3_tmpl.vhd
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_af_512x32_ecp3.ipx
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_af_512x32_ecp3.lpc
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_af_512x32_ecp3.vhd
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_af_512x32_ecp3_tmpl.vhd
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_af_512x36_ecp3.ipx
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_af_512x36_ecp3.lpc
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_af_512x36_ecp3.vhd
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_af_512x36_ecp3_tmpl.vhd
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_nn_16384x36_ecp3.ipx
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_nn_16384x36_ecp3.lpc
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_nn_16384x36_ecp3.vhd
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_nn_16384x36_ecp3_tmpl.vhd
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x103_ecp3.ipx
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x103_ecp3.lpc
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x103_ecp3.vhd
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x103_ecp3_tmpl.vhd
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x36_ecp3.ipx
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x36_ecp3.lpc
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x36_ecp3.vhd
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x36_ecp3_tmpl.vhd
 create mode 100644 data_concentrator/sources/lattice/ecp3/async_fifo_nn_th_512x36_ecp3.ipx
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diff --git a/data_concentrator/data_concentrator.ldf b/data_concentrator/data_concentrator.ldf
new file mode 100644
index 0000000..1cc2cb8
--- /dev/null
+++ b/data_concentrator/data_concentrator.ldf
@@ -0,0 +1,612 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="3.2" title="trb3_periph" device="LFE3-150EA-8FN672C" default_implementation="data_concentrator">
+    <Options/>
+    <Implementation title="data_concentrator" dir="data_concentrator" description="data_concentrator" synthesis="synplify" default_strategy="Strategy1">
+        <Options def_top="DC_max_lookuptable" run_flow="NORMAL" top="trb3_periph_data_concentrator"/>
+        <Source name="../../trb3/base/version.vhd" type="VHDL" type_short="VHDL">
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+        <Source name="../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
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+        <Source name="../../trbnet/trb_net_CRC8.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
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+        </Source>
+        <Source name="../../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
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+        <Source name="../../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
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+        <Source name="../../trbnet/basics/state_sync.vhd" type="VHDL" type_short="VHDL">
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+        <Source name="../../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL">
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+        <Source name="../../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL">
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+        <Source name="../../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL">
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+        <Source name="../../trbnet/trb_net16_term.vhd" type="VHDL" type_short="VHDL">
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+        <Source name="../../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
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+            <Options/>
+        </Source>
+        <Source name="../source/soda_superburst_gen.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../source/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../source/soda_packet_builder.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../source/soda_packet_handler.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../source/soda_components.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/async_fifo_nn_thfull_FWFT_512x36.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/async_fifo_nn_th_512x36.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/async_fifo_nn_16384x36.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/async_fifo_nn_4096x36.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/async_fifo_FWFT_16x32.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/async_fifo_af_512x36.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/async_fifo_af_512x32.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/async_fifo_512x32.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/async_fifo_16x32.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/ecp3/async_fifo_16x32_ecp3.ipx" type="IPX_Module" type_short="IPX">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/ecp3/async_fifo_256x66_ecp3.ipx" type="IPX_Module" type_short="IPX">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/ecp3/async_fifo_16x32_ecp3.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/ecp3/async_fifo_af_512x32_ecp3.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/ecp3/async_fifo_512x32_ecp3.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/ecp3/async_fifo_af_512x36_ecp3.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/ecp3/async_fifo_nn_16384x36_ecp3.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/ecp3/async_fifo_nn_th_512x36_ecp3.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/ecp3/async_fifo_nn_thfull_512x36_ecp3.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/med_ecp3_quad_sfp_sync.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/async_fifo_nn_4096x103.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/async_fifo_256x66.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/ecp3/async_fifo_512x99_ecp3.ipx" type="IPX_Module" type_short="IPX">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/async_fifo_512x99.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/ecp3/sync_fifo_512x41_ecp3.ipx" type="IPX_Module" type_short="IPX">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/sync_fifo_512x41.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/ecp3/async_fifo_nn_thfull_512x36_ecp3.ipx" type="IPX_Module" type_short="IPX">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/ecp3/async_fifo_nn_4096x36_ecp3.ipx" type="IPX_Module" type_short="IPX">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/ecp3/async_fifo_nn_4096x103_ecp3.ipx" type="IPX_Module" type_short="IPX">
+            <Options/>
+        </Source>
+        <Source name="trb3_periph_data_concentrator.vhd" type="VHDL" type_short="VHDL">
+            <Options top_module="trb3_periph_data_concentrator"/>
+        </Source>
+        <Source name="trb_net16_endpoint_data_concentrator.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="trb_net16_endpoint_data_concentrator_handler.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/Panda_package.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/posedge_to_pulse.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/synchronizer_to_other_clock.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/blockmem.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/crc8_add_check32.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/crc8_add_check64.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/histogram.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_checkwave.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_extract_wave.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/rxFifo_MUX.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/serdesQuadBufLayerMUX.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/serdesQuadMUXwrapper.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/txFifo_MUX.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/gtpBufLayerPackage.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="test_module.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/dataconversion_for_serdes.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_energy_correction.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_pulse_cross_switch.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_separate_data.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_fibermodule_interface.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_Quad_fiber_module.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_superburst2packet64.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_mux2to1.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_read36bitsfifo.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_data_wave_to_64bit.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_extract_data.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_histogram.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_check_timestamp.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_module_TRB3.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_combine_pulses.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_sorting_mux.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_LUT_package.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_max_lookuptable.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_measure_frequency.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_slowcontrol_packetbuilder.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_slowcontrol_receive_from_cpu.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_slowcontrol_to_serial.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_split_data.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_time_energy_LUTs.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_time_lookuptable.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_timeshift_lookuptable.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_CF_MAX_correction.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_fifo32to8_SODA.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_fifo8to32_SODA.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_wave2packet64.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/div_pipe_r4_arch2/cond_add.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/div_pipe_r4_arch2/div_r4_pipe.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/div_pipe_r4_arch2/mypack.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/div_pipe_r4_arch2/nr_r4_cel.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/shift_register.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/ecp3/serdes_sync_200_full.ipx" type="IPX_Module" type_short="IPX">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/ecp3/pll_in200_out200M_100M.ipx" type="IPX_Module" type_short="IPX">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/ecp3/pll_in100_out80M.ipx" type="IPX_Module" type_short="IPX">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/ecp3/pll_in200_out200M_100M.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/ecp3/serdes_sync_200_full.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/ecp3/pll_in100_out80M.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_wavemux.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/DC_slow_control_TRB3.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/trb_net16_med_1_2sync_3_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/ecp3/sfp_1_2sync_3_200_int.ipx" type="IPX_Module" type_short="IPX">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/ecp3/sfp_1_2sync_3_200_int.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/ecp3/async_fifo_512x32_ecp3.ipx" type="IPX_Module" type_short="IPX">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/tx_reset_sm.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/rx_reset_sm.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="data_concentrator.xcf" type="Programming Project File" type_short="Programming">
+            <Options/>
+        </Source>
+        <Source name="revea_dc_test2.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
+            <Options/>
+        </Source>
+        <Source name="reveal_dc_testphase.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
+            <Options/>
+        </Source>
+        <Source name="reveal_slowcontrol.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
+            <Options/>
+        </Source>
+        <Source name="reveal_test64out.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
+            <Options/>
+        </Source>
+        <Source name="reveal_test_combine.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
+            <Options/>
+        </Source>
+        <Source name="reveal_test_fiber_input.rvl" type="Reveal" type_short="Reveal">
+            <Options/>
+        </Source>
+        <Source name="reveal_test_overflow.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
+            <Options/>
+        </Source>
+        <Source name="reveal_test_pulsemux.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
+            <Options/>
+        </Source>
+        <Source name="reveal_test_pulsemux2.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
+            <Options/>
+        </Source>
+        <Source name="reveal_test_trbreset.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
+            <Options/>
+        </Source>
+        <Source name="reveal_test_waveMUX.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
+            <Options/>
+        </Source>
+        <Source name="trb3_periph_data_concentrator.lpf" type="Logic Preference" type_short="LPF">
+            <Options/>
+        </Source>
+    </Implementation>
+    <Strategy name="Stragety2" file="Stragety2.sty"/>
+    <Strategy name="Strategy1" file="Strategy1.sty"/>
+</BaliProject>
diff --git a/data_concentrator/sources/DC_CF_MAX_correction.vhd b/data_concentrator/sources/DC_CF_MAX_correction.vhd
new file mode 100644
index 0000000..3ca3634
--- /dev/null
+++ b/data_concentrator/sources/DC_CF_MAX_correction.vhd
@@ -0,0 +1,292 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   11-09-2014
+-- Module Name:   DC_CF_MAX_correction
+-- Description:   Calculates energy and timestamp and performs correction with Look Up Table 
+-- Modifications:
+--   18-09-2014   different clock for loading
+--   11-10-2014   Energy is measured with integral, not with the maximum, so maximum-correction part is not valid 
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+library work;
+USE work.panda_package.all;
+
+------------------------------------------------------------------------------------------------------
+-- DC_CF_MAX_correction
+--     Calculates energy and timestamp and performs correction with Look Up Table 
+--     Input data contains timestamp, adcnumber, status-byte, two sequential samples, containing the maximum and 
+--     the Constant Fraction sample before and after the zero crossing.
+--
+--     The first part of the Constant Fraction is done in the ADC input modules:
+--           CF_signal = -ADCvalue + 4*ADCvalue'delayed
+--     This results in a signal that has a zero-crossing near the rising edge of the pulse.
+--     The CF_signal before and after the zerocrossing is passed on and now used to calculate the fractional part of the timestamp:
+--           timefraction = -CF_signal_before / (CF_signal_after - CF_signal_before) * 2^CF_FRACTIONBIT
+--           with CF_FRACTIONBIT the number of bits of the calculated timefraction
+--     After this the Constant Fraction fractional result is corrected for pulse shape with a Look Up Table:
+--         correctedFraction = LUT[timefraction]
+--
+--
+-- generics
+--     ADCBITS : number of ADC-bits, input data is 2-complement representation: one additional bit
+--     CF_FRACTIONBIT : number of bits for the calculated fraction of the precise timestamp
+--     MAX_DIVIDERSCALEBITS : number of scaling bits for division two largest samples
+--     MAX_LUTSIZEBITS : number of bits the maximum correction Look Up Table
+--     MAX_LUTSCALEBITS : number of scaling bits for the correction on the maximum (energy)
+--		
+-- inputs
+--     clock : clock
+--     load_clock : clock for loading
+--     reset : synchronous reset
+--     pulse_superburst : lowest 16-bits of the superburstnumber of the hit
+--     pulse_timestamp : 16-bits timestamp within superburst (time of sample before the CF zero crossing)
+--     pulse_adcnumber : 16-bits adc channel number
+--     pulse_statusbyte : 8-bits status
+--     pulse_energy : energy of the pulse, calculated with scaled integral
+--     pulse_CF_before : CF_signal value of the value before the zero-crossing (absolute value)
+--     pulse_CF_after : CF_signal value of the value after the zero-crossing (absolute value)
+--     pulse_write : write signal for pulsedata
+--     max_correction : use correction on maximum value with Look Up Table
+--     max_LUT_offset : offset for index in maximum correction Look Up Table
+--     max_LUT_loading : set in mode for loading a new maximum correction Look Up Table
+--     max_LUT_write : write next value in maximum correction Look Up Table
+--     fraction_correction : use correction on timestamp fraction with Look Up Table
+--     fraction_LUT_loading : set in mode for loading a new timestamp fraction correction Look Up Table
+--     fraction_LUT_write : write next value in timestamp fraction correction Look Up Table
+--     LUT_data_in : data for writing in the selected LUT : maximum correction or timestamp fraction correction
+--     result_allowed : writing of results allowed 
+--			  
+-- outputs
+--     pulse_allowed : allowed to write pulse data
+--     result_write : write signal for results
+--     adcnumber : 16-bits identification number of the adc
+--     superburst : 16 bits of the superburstnumber
+--     timestamp : 16 bits timestamp of the CF_signal before the zero-crossing
+--     timefraction : calculated fraction of the time-stamp using constant fraction method
+--     energy : energy, calculated maximum in waveform
+--     statusbyte : 8-bits status
+--
+-- components
+--     shift_register : shift register
+--     div_r4_pipe : unsigned divider
+--     DC_time_lookuptable : Look Up Table for timestamp fraction correction
+--
+--
+------------------------------------------------------------------------------------------------------
+
+
+
+entity DC_CF_MAX_correction is
+	generic (
+		ADCBITS                 : natural := 14;
+		CF_FRACTIONBIT          : natural := 11;
+		MAX_DIVIDERSCALEBITS    : natural := 12;
+		MAX_LUTSIZEBITS         : natural := 8;
+		MAX_LUTSCALEBITS        : natural := 14
+		);
+    Port (
+		clock                   : in std_logic;
+		load_clock              : in std_logic;
+		reset                   : in std_logic;
+		pulse_superburst        : in std_logic_vector(15 downto 0);
+		pulse_timestamp         : in std_logic_vector(15 downto 0);
+		pulse_adcnumber         : in std_logic_vector(15 downto 0);
+		pulse_statusbyte        : in std_logic_vector(7 downto 0);
+		pulse_energy            : in std_logic_vector(15 downto 0);
+		pulse_CF_before         : in std_logic_vector(15 downto 0);
+		pulse_CF_after          : in std_logic_vector(15 downto 0);
+		pulse_allowed           : out std_logic;
+		pulse_write             : in std_logic;
+		max_correction          : in std_logic;
+		max_LUT_offset          : in std_logic_vector(MAX_LUTSIZEBITS-1 downto 0);
+		max_LUT_loading         : in std_logic;
+		max_LUT_write           : in std_logic;
+		fraction_correction     : in std_logic;
+		fraction_LUT_loading    : in std_logic;
+		fraction_LUT_write      : in std_logic;
+		LUT_data_in             : in std_logic_vector(CF_FRACTIONBIT-1 downto 0);
+		result_write            : out std_logic;
+		result_allowed          : in std_logic;
+		adcnumber               : out std_logic_vector(15 downto 0);
+		superburst              : out std_logic_vector(15 downto 0);
+		timestamp               : out std_logic_vector(15 downto 0);
+		timefraction            : out std_logic_vector(CF_FRACTIONBIT-1 downto 0);
+		energy                  : out std_logic_vector(15 downto 0);
+		statusbyte              : out std_logic_vector(7 downto 0);
+		testword0               : out std_logic_vector(35 downto 0);
+		testword1               : out std_logic_vector(35 downto 0)
+		);
+end DC_CF_MAX_correction;
+
+architecture Behavioral of DC_CF_MAX_correction is
+
+component shift_register is
+	generic (
+		width                   : natural := 16; 
+		depthbits               : natural := 5
+		);
+    port (
+		clock                   : in  std_logic; 
+		reset                   : in  std_logic; 
+		hold                    : in  std_logic; 
+		data_in                 : in std_logic_vector((width-1) downto 0); 
+		depth                   : in std_logic_vector((depthbits-1) downto 0);
+		data_out                : out  std_logic_vector((width-1) downto 0));
+end component;
+
+component div_r4_pipe -- pipeline length=XBITS/GRAIN/DEPTH + 1
+	generic (
+		XBITS : natural := 32;
+		YBITS : natural := 32;
+		GRAIN : natural := 2;
+		DEPTH : natural := 1
+		);
+    port (
+      a                       : in std_logic_vector(XBITS-1 downto 0);
+      b                       : in std_logic_vector(YBITS-1 downto 0);
+      clk                     : in std_logic;          
+      q                       : out std_logic_vector(XBITS-1 downto 0);
+      r                       : out std_logic_vector(YBITS-1 downto 0)
+      );
+end component;
+
+component DC_time_lookuptable is
+	generic (
+		lut_addrwidth           : natural := CF_FRACTIONBIT;
+		lut_datawidth           : natural := CF_FRACTIONBIT
+		);
+	port ( 
+		clock                   : in std_logic;
+		load_clock              : in std_logic;
+		loading                 : in std_logic;
+		lut_write               : in std_logic;
+		address                 : in std_logic_vector (lut_addrwidth-1 downto 0);
+		data_in                 : in std_logic_vector (lut_datawidth-1 downto 0);
+		data_out                : out std_logic_vector (lut_datawidth-1 downto 0));
+end component;
+
+constant zeros                     : std_logic_vector(31 downto 0) := (others => '0');
+signal adcnumber_S                 : std_logic_vector(15 downto 0) := (others => '0');
+signal superburst_S                : std_logic_vector(15 downto 0);
+signal timestamp_S                 : std_logic_vector(15 downto 0);
+signal CF_before_S                 : std_logic_vector(15 downto 0);
+signal CF_after_S                  : std_logic_vector(15 downto 0);
+
+signal fraction_correction_S       : std_logic;
+
+signal cf_signal_before_S          : std_logic_vector(17 downto 0) := (others => '0');
+signal cf_signal_before_scaled_S   : std_logic_vector(27 downto 0);
+signal cf_signal_after_S           : std_logic_vector(17 downto 0) := (others => '0');
+signal cf_sum_S                    : std_logic_vector(17 downto 0) := (others => '0');
+signal timefraction28_S            : std_logic_vector(27 downto 0);
+
+signal timefraction_S              : std_logic_vector(CF_FRACTIONBIT-1 downto 0) := (others => '0');
+signal energy_S                    : std_logic_vector(15 downto 0) := (others => '0');
+signal energy_out_S                : std_logic_vector(15 downto 0) := (others => '0');
+
+signal statusbyte_S                : std_logic_vector(7 downto 0) := (others => '0');
+signal result_write_S              : std_logic := '0';
+
+signal result_shiftreg_in_S        : std_logic_vector(72 downto 0) := (others => '0');
+signal result_shiftreg_out_S       : std_logic_vector(72 downto 0) := (others => '0');
+
+
+signal timefraction_after1clk_S    : std_logic_vector(CF_FRACTIONBIT-1 downto 0) := (others => '0');
+signal timefraction_corrected_S    : std_logic_vector(CF_FRACTIONBIT-1 downto 0) := (others => '0');
+
+begin
+		
+superburst_S <= pulse_superburst;
+timestamp_S <= pulse_timestamp;
+adcnumber_S <= pulse_adcnumber;
+statusbyte_S <= pulse_statusbyte;
+energy_S <= pulse_energy;
+CF_before_S <= pulse_CF_before;
+CF_after_S <= pulse_CF_after;
+pulse_allowed <= result_allowed;
+result_write_S <= pulse_write;
+
+cf_signal_before_S <= conv_std_logic_vector(conv_integer(unsigned(CF_before_S)),18);
+cf_signal_after_S <= conv_std_logic_vector(conv_integer(unsigned(CF_after_S)),18);
+						
+cf_sum_S <= conv_std_logic_vector(conv_integer(unsigned(cf_signal_after_S))+conv_integer(unsigned(cf_signal_before_S)),18);
+
+cf_signal_before_scaled_S(CF_FRACTIONBIT-1 downto 0) <= (others => '0');
+cf_signal_before_scaled_S(27 downto CF_FRACTIONBIT) <= cf_signal_before_S(27-CF_FRACTIONBIT downto 0);
+div_r4_pipe1: div_r4_pipe -- pipeline length=XBITS/GRAIN/DEPTH + 1 = 15
+	generic map(
+		XBITS => 28,
+		YBITS => 18
+		)
+    port map (
+      a => cf_signal_before_scaled_S,
+      b => cf_sum_S,
+      clk => clock,   
+      q => timefraction28_S,
+      r => open);
+timefraction_S <= timefraction28_S(CF_FRACTIONBIT-1 downto 0);
+
+DC_time_lookuptable1: DC_time_lookuptable
+	generic map(
+		lut_addrwidth => CF_FRACTIONBIT,
+		lut_datawidth => CF_FRACTIONBIT
+		)
+	port map( 
+		clock => clock,
+		load_clock => load_clock,
+		loading => fraction_LUT_loading,
+		lut_write  => fraction_LUT_write,
+		address => timefraction_S,
+		data_in => LUT_data_in(CF_FRACTIONBIT-1 downto 0),
+		data_out => timefraction_corrected_S);
+
+
+result_shiftreg_in_S <=  result_write_S & energy_S & timestamp_S & superburst_S & adcnumber_S & statusbyte_S;
+shiftregister2: shift_register 
+	generic map(
+		width => result_shiftreg_in_S'length, -- signed signal 
+		depthbits => 5
+		)
+	port map(
+		clock => clock,
+		reset => '0', -- reset,
+		hold => '0',
+		data_in => result_shiftreg_in_S,
+		depth => conv_std_logic_vector(16,5),
+		data_out => result_shiftreg_out_S);
+
+
+energy_out_S <= result_shiftreg_out_S(71 downto 56);
+
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		timefraction_after1clk_S <= timefraction_S;
+		result_write <= result_shiftreg_out_S(72);
+		adcnumber <= result_shiftreg_out_S(23 downto 8);
+		superburst <= result_shiftreg_out_S(39 downto 24);
+		timestamp <= result_shiftreg_out_S(55 downto 40);
+		if fraction_correction_S='0' then
+			timefraction <= timefraction_after1clk_S;
+		else 
+			timefraction <= timefraction_corrected_S;
+		end if;
+		energy <= energy_out_S;
+		statusbyte <= result_shiftreg_out_S(7 downto 0);
+		fraction_correction_S <= fraction_correction;
+	end if;
+end process;
+
+		
+testword0 <= (others => '0');
+testword1 <= (others => '0');
+
+
+end Behavioral;
+
+
diff --git a/data_concentrator/sources/DC_LUT_package.vhd b/data_concentrator/sources/DC_LUT_package.vhd
new file mode 100644
index 0000000..b16fb85
--- /dev/null
+++ b/data_concentrator/sources/DC_LUT_package.vhd
@@ -0,0 +1,3113 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date:   11-09-2014
+-- Module Name:   DC_LUT_package
+-- Description: Package with constants for Look Up Table
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package DC_LUT_package is
+
+constant MAX_LUTSIZEBITS : natural := 10;
+constant MAXCORRLUTSWIDTH : natural := 8;
+constant MAXCORR : natural := 8;
+constant CF_FRACTIONBIT : natural := 11;
+
+type max_correction_lut_type is array (0 to 2**MAX_LUTSIZEBITS-1) 
+			of std_logic_vector (MAXCORRLUTSWIDTH-1 downto 0);
+			
+type time_correction_lut_type is array (0 to 2**CF_FRACTIONBIT-1) 
+			of std_logic_vector (CF_FRACTIONBIT-1 downto 0);
+			
+			
+constant MAXCORR_MINIMUM : natural := 224; -- fill in in io.c program function set_defaults()
+constant CF_DEFAULTDELAY : natural := 4;  -- fill in in io.c program function set_defaults()
+		
+constant DEFAULTMAXCORRLUT : max_correction_lut_type := (
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000001",
+"00000001",
+"00000001",
+"00000001",
+"00000001",
+"00000001",
+"00000001",
+"00000001",
+"00000001",
+"00000010",
+"00000010",
+"00000010",
+"00000010",
+"00000010",
+"00000010",
+"00000011",
+"00000011",
+"00000011",
+"00000011",
+"00000100",
+"00000100",
+"00000100",
+"00000100",
+"00000100",
+"00000101",
+"00000101",
+"00000101",
+"00000110",
+"00000110",
+"00000110",
+"00000110",
+"00000111",
+"00000111",
+"00000111",
+"00001000",
+"00001000",
+"00001000",
+"00001001",
+"00001001",
+"00001010",
+"00001010",
+"00001010",
+"00001011",
+"00001011",
+"00001100",
+"00001100",
+"00001100",
+"00001101",
+"00001101",
+"00001110",
+"00001110",
+"00001111",
+"00001111",
+"00010000",
+"00010000",
+"00010001",
+"00010001",
+"00010010",
+"00010010",
+"00010011",
+"00010011",
+"00010100",
+"00010100",
+"00010101",
+"00010101",
+"00010110",
+"00010111",
+"00010111",
+"00011000",
+"00011000",
+"00011001",
+"00011010",
+"00011010",
+"00011011",
+"00011100",
+"00011100",
+"00011101",
+"00011110",
+"00011110",
+"00011111",
+"00100000",
+"00100000",
+"00100001",
+"00100010",
+"00100010",
+"00100011",
+"00100100",
+"00100101",
+"00100110",
+"00100110",
+"00100111",
+"00101000",
+"00101001",
+"00101001",
+"00101010",
+"00101011",
+"00101100",
+"00101101",
+"00101110",
+"00101110",
+"00101111",
+"00110000",
+"00110001",
+"00110010",
+"00110011",
+"00110100",
+"00110101",
+"00110110",
+"00110110",
+"00110111",
+"00111000",
+"00111001",
+"00111010",
+"00111011",
+"00111100",
+"00111101",
+"00111110",
+"00111111",
+"01000000",
+"01000001",
+"01000010",
+"01000011",
+"01000100",
+"01000101",
+"01000110",
+"01001000",
+"01001001",
+"01001010",
+"01001011",
+"01001100",
+"01001101",
+"01001110",
+"01001111",
+"01010000",
+"01010010",
+"01010011",
+"01010100",
+"01010101",
+"01010110",
+"01010111",
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+"01011010",
+"01011011",
+"01011100",
+"01011110",
+"01011111",
+"01100000",
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+"01100011",
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+"11000000",
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+"00110011",
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+"00010010",
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+"00000011",
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+"00000010",
+"00000010",
+"00000010",
+"00000010",
+"00000010",
+"00000001",
+"00000001",
+"00000001",
+"00000001",
+"00000001",
+"00000001",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
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+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000",
+"00000000"
+);
+
+constant DEFAULTTIMECORRLUT : time_correction_lut_type := (
+"00000000000",
+"00000000001",
+"00000000010",
+"00000000011",
+"00000000100",
+"00000000101",
+"00000000110",
+"00000000111",
+"00000001001",
+"00000001010",
+"00000001011",
+"00000001100",
+"00000001101",
+"00000001110",
+"00000001111",
+"00000010000",
+"00000010010",
+"00000010011",
+"00000010100",
+"00000010101",
+"00000010110",
+"00000010111",
+"00000011000",
+"00000011001",
+"00000011011",
+"00000011100",
+"00000011101",
+"00000011110",
+"00000011111",
+"00000100000",
+"00000100001",
+"00000100010",
+"00000100100",
+"00000100101",
+"00000100110",
+"00000100111",
+"00000101000",
+"00000101001",
+"00000101010",
+"00000101011",
+"00000101101",
+"00000101110",
+"00000101111",
+"00000110000",
+"00000110001",
+"00000110010",
+"00000110011",
+"00000110100",
+"00000110110",
+"00000110111",
+"00000111000",
+"00000111001",
+"00000111010",
+"00000111011",
+"00000111100",
+"00000111101",
+"00000111111",
+"00001000000",
+"00001000001",
+"00001000010",
+"00001000011",
+"00001000100",
+"00001000101",
+"00001000111",
+"00001001000",
+"00001001001",
+"00001001010",
+"00001001011",
+"00001001100",
+"00001001101",
+"00001001110",
+"00001010000",
+"00001010001",
+"00001010010",
+"00001010011",
+"00001010100",
+"00001010101",
+"00001010110",
+"00001011000",
+"00001011001",
+"00001011010",
+"00001011011",
+"00001011100",
+"00001011101",
+"00001011110",
+"00001011111",
+"00001100001",
+"00001100010",
+"00001100011",
+"00001100100",
+"00001100101",
+"00001100110",
+"00001100111",
+"00001101001",
+"00001101010",
+"00001101011",
+"00001101100",
+"00001101101",
+"00001101110",
+"00001101111",
+"00001110001",
+"00001110010",
+"00001110011",
+"00001110100",
+"00001110101",
+"00001110110",
+"00001110111",
+"00001111000",
+"00001111010",
+"00001111011",
+"00001111100",
+"00001111101",
+"00001111110",
+"00001111111",
+"00010000000",
+"00010000010",
+"00010000011",
+"00010000100",
+"00010000101",
+"00010000110",
+"00010000111",
+"00010001000",
+"00010001010",
+"00010001011",
+"00010001100",
+"00010001101",
+"00010001110",
+"00010001111",
+"00010010000",
+"00010010010",
+"00010010011",
+"00010010100",
+"00010010101",
+"00010010110",
+"00010010111",
+"00010011000",
+"00010011010",
+"00010011011",
+"00010011100",
+"00010011101",
+"00010011110",
+"00010011111",
+"00010100000",
+"00010100010",
+"00010100011",
+"00010100100",
+"00010100101",
+"00010100110",
+"00010100111",
+"00010101001",
+"00010101010",
+"00010101011",
+"00010101100",
+"00010101101",
+"00010101110",
+"00010101111",
+"00010110001",
+"00010110010",
+"00010110011",
+"00010110100",
+"00010110101",
+"00010110110",
+"00010110111",
+"00010111001",
+"00010111010",
+"00010111011",
+"00010111100",
+"00010111101",
+"00010111110",
+"00011000000",
+"00011000001",
+"00011000010",
+"00011000011",
+"00011000100",
+"00011000101",
+"00011000110",
+"00011001000",
+"00011001001",
+"00011001010",
+"00011001011",
+"00011001100",
+"00011001101",
+"00011001110",
+"00011010000",
+"00011010001",
+"00011010010",
+"00011010011",
+"00011010100",
+"00011010101",
+"00011010111",
+"00011011000",
+"00011011001",
+"00011011010",
+"00011011011",
+"00011011100",
+"00011011101",
+"00011011111",
+"00011100000",
+"00011100001",
+"00011100010",
+"00011100011",
+"00011100100",
+"00011100110",
+"00011100111",
+"00011101000",
+"00011101001",
+"00011101010",
+"00011101011",
+"00011101100",
+"00011101110",
+"00011101111",
+"00011110000",
+"00011110001",
+"00011110010",
+"00011110011",
+"00011110101",
+"00011110110",
+"00011110111",
+"00011111000",
+"00011111001",
+"00011111010",
+"00011111100",
+"00011111101",
+"00011111110",
+"00011111111",
+"00100000000",
+"00100000001",
+"00100000011",
+"00100000100",
+"00100000101",
+"00100000110",
+"00100000111",
+"00100001000",
+"00100001001",
+"00100001011",
+"00100001100",
+"00100001101",
+"00100001110",
+"00100001111",
+"00100010000",
+"00100010010",
+"00100010011",
+"00100010100",
+"00100010101",
+"00100010110",
+"00100010111",
+"00100011001",
+"00100011010",
+"00100011011",
+"00100011100",
+"00100011101",
+"00100011110",
+"00100100000",
+"00100100001",
+"00100100010",
+"00100100011",
+"00100100100",
+"00100100101",
+"00100100111",
+"00100101000",
+"00100101001",
+"00100101010",
+"00100101011",
+"00100101100",
+"00100101101",
+"00100101111",
+"00100110000",
+"00100110001",
+"00100110010",
+"00100110011",
+"00100110100",
+"00100110110",
+"00100110111",
+"00100111000",
+"00100111001",
+"00100111010",
+"00100111011",
+"00100111101",
+"00100111110",
+"00100111111",
+"00101000000",
+"00101000001",
+"00101000010",
+"00101000100",
+"00101000101",
+"00101000110",
+"00101000111",
+"00101001000",
+"00101001001",
+"00101001011",
+"00101001100",
+"00101001101",
+"00101001110",
+"00101001111",
+"00101010000",
+"00101010010",
+"00101010011",
+"00101010100",
+"00101010101",
+"00101010110",
+"00101010111",
+"00101011001",
+"00101011010",
+"00101011011",
+"00101011100",
+"00101011101",
+"00101011110",
+"00101100000",
+"00101100001",
+"00101100010",
+"00101100011",
+"00101100100",
+"00101100110",
+"00101100111",
+"00101101000",
+"00101101001",
+"00101101010",
+"00101101011",
+"00101101101",
+"00101101110",
+"00101101111",
+"00101110000",
+"00101110001",
+"00101110010",
+"00101110100",
+"00101110101",
+"00101110110",
+"00101110111",
+"00101111000",
+"00101111001",
+"00101111011",
+"00101111100",
+"00101111101",
+"00101111110",
+"00101111111",
+"00110000000",
+"00110000010",
+"00110000011",
+"00110000100",
+"00110000101",
+"00110000110",
+"00110000111",
+"00110001001",
+"00110001010",
+"00110001011",
+"00110001100",
+"00110001101",
+"00110001110",
+"00110010000",
+"00110010001",
+"00110010010",
+"00110010011",
+"00110010100",
+"00110010110",
+"00110010111",
+"00110011000",
+"00110011001",
+"00110011010",
+"00110011011",
+"00110011101",
+"00110011110",
+"00110011111",
+"00110100000",
+"00110100001",
+"00110100010",
+"00110100100",
+"00110100101",
+"00110100110",
+"00110100111",
+"00110101000",
+"00110101001",
+"00110101011",
+"00110101100",
+"00110101101",
+"00110101110",
+"00110101111",
+"00110110001",
+"00110110010",
+"00110110011",
+"00110110100",
+"00110110101",
+"00110110110",
+"00110111000",
+"00110111001",
+"00110111010",
+"00110111011",
+"00110111100",
+"00110111101",
+"00110111111",
+"00111000000",
+"00111000001",
+"00111000010",
+"00111000011",
+"00111000100",
+"00111000110",
+"00111000111",
+"00111001000",
+"00111001001",
+"00111001010",
+"00111001100",
+"00111001101",
+"00111001110",
+"00111001111",
+"00111010000",
+"00111010001",
+"00111010011",
+"00111010100",
+"00111010101",
+"00111010110",
+"00111010111",
+"00111011000",
+"00111011010",
+"00111011011",
+"00111011100",
+"00111011101",
+"00111011110",
+"00111011111",
+"00111100001",
+"00111100010",
+"00111100011",
+"00111100100",
+"00111100101",
+"00111100111",
+"00111101000",
+"00111101001",
+"00111101010",
+"00111101011",
+"00111101100",
+"00111101110",
+"00111101111",
+"00111110000",
+"00111110001",
+"00111110010",
+"00111110011",
+"00111110101",
+"00111110110",
+"00111110111",
+"00111111000",
+"00111111001",
+"00111111011",
+"00111111100",
+"00111111101",
+"00111111110",
+"00111111111",
+"01000000000",
+"01000000010",
+"01000000011",
+"01000000100",
+"01000000101",
+"01000000110",
+"01000000111",
+"01000001001",
+"01000001010",
+"01000001011",
+"01000001100",
+"01000001101",
+"01000001110",
+"01000010000",
+"01000010001",
+"01000010010",
+"01000010011",
+"01000010100",
+"01000010110",
+"01000010111",
+"01000011000",
+"01000011001",
+"01000011010",
+"01000011011",
+"01000011101",
+"01000011110",
+"01000011111",
+"01000100000",
+"01000100001",
+"01000100010",
+"01000100100",
+"01000100101",
+"01000100110",
+"01000100111",
+"01000101000",
+"01000101010",
+"01000101011",
+"01000101100",
+"01000101101",
+"01000101110",
+"01000101111",
+"01000110001",
+"01000110010",
+"01000110011",
+"01000110100",
+"01000110101",
+"01000110110",
+"01000111000",
+"01000111001",
+"01000111010",
+"01000111011",
+"01000111100",
+"01000111101",
+"01000111111",
+"01001000000",
+"01001000001",
+"01001000010",
+"01001000011",
+"01001000100",
+"01001000110",
+"01001000111",
+"01001001000",
+"01001001001",
+"01001001010",
+"01001001100",
+"01001001101",
+"01001001110",
+"01001001111",
+"01001010000",
+"01001010001",
+"01001010011",
+"01001010100",
+"01001010101",
+"01001010110",
+"01001010111",
+"01001011000",
+"01001011010",
+"01001011011",
+"01001011100",
+"01001011101",
+"01001011110",
+"01001011111",
+"01001100001",
+"01001100010",
+"01001100011",
+"01001100100",
+"01001100101",
+"01001100110",
+"01001101000",
+"01001101001",
+"01001101010",
+"01001101011",
+"01001101100",
+"01001101110",
+"01001101111",
+"01001110000",
+"01001110001",
+"01001110010",
+"01001110011",
+"01001110101",
+"01001110110",
+"01001110111",
+"01001111000",
+"01001111001",
+"01001111010",
+"01001111100",
+"01001111101",
+"01001111110",
+"01001111111",
+"01010000000",
+"01010000001",
+"01010000011",
+"01010000100",
+"01010000101",
+"01010000110",
+"01010000111",
+"01010001000",
+"01010001010",
+"01010001011",
+"01010001100",
+"01010001101",
+"01010001110",
+"01010001111",
+"01010010001",
+"01010010010",
+"01010010011",
+"01010010100",
+"01010010101",
+"01010010110",
+"01010011000",
+"01010011001",
+"01010011010",
+"01010011011",
+"01010011100",
+"01010011101",
+"01010011111",
+"01010100000",
+"01010100001",
+"01010100010",
+"01010100011",
+"01010100100",
+"01010100110",
+"01010100111",
+"01010101000",
+"01010101001",
+"01010101010",
+"01010101011",
+"01010101101",
+"01010101110",
+"01010101111",
+"01010110000",
+"01010110001",
+"01010110010",
+"01010110100",
+"01010110101",
+"01010110110",
+"01010110111",
+"01010111000",
+"01010111001",
+"01010111011",
+"01010111100",
+"01010111101",
+"01010111110",
+"01010111111",
+"01011000000",
+"01011000010",
+"01011000011",
+"01011000100",
+"01011000101",
+"01011000110",
+"01011000111",
+"01011001000",
+"01011001010",
+"01011001011",
+"01011001100",
+"01011001101",
+"01011001110",
+"01011001111",
+"01011010001",
+"01011010010",
+"01011010011",
+"01011010100",
+"01011010101",
+"01011010110",
+"01011011000",
+"01011011001",
+"01011011010",
+"01011011011",
+"01011011100",
+"01011011101",
+"01011011111",
+"01011100000",
+"01011100001",
+"01011100010",
+"01011100011",
+"01011100100",
+"01011100101",
+"01011100111",
+"01011101000",
+"01011101001",
+"01011101010",
+"01011101011",
+"01011101100",
+"01011101110",
+"01011101111",
+"01011110000",
+"01011110001",
+"01011110010",
+"01011110011",
+"01011110101",
+"01011110110",
+"01011110111",
+"01011111000",
+"01011111001",
+"01011111010",
+"01011111011",
+"01011111101",
+"01011111110",
+"01011111111",
+"01100000000",
+"01100000001",
+"01100000010",
+"01100000100",
+"01100000101",
+"01100000110",
+"01100000111",
+"01100001000",
+"01100001001",
+"01100001010",
+"01100001100",
+"01100001101",
+"01100001110",
+"01100001111",
+"01100010000",
+"01100010001",
+"01100010011",
+"01100010100",
+"01100010101",
+"01100010110",
+"01100010111",
+"01100011000",
+"01100011001",
+"01100011011",
+"01100011100",
+"01100011101",
+"01100011110",
+"01100011111",
+"01100100000",
+"01100100001",
+"01100100011",
+"01100100100",
+"01100100101",
+"01100100110",
+"01100100111",
+"01100101000",
+"01100101001",
+"01100101011",
+"01100101100",
+"01100101101",
+"01100101110",
+"01100101111",
+"01100110000",
+"01100110010",
+"01100110011",
+"01100110100",
+"01100110101",
+"01100110110",
+"01100110111",
+"01100111000",
+"01100111010",
+"01100111011",
+"01100111100",
+"01100111101",
+"01100111110",
+"01100111111",
+"01101000000",
+"01101000010",
+"01101000011",
+"01101000100",
+"01101000101",
+"01101000110",
+"01101000111",
+"01101001000",
+"01101001010",
+"01101001011",
+"01101001100",
+"01101001101",
+"01101001110",
+"01101001111",
+"01101010000",
+"01101010010",
+"01101010011",
+"01101010100",
+"01101010101",
+"01101010110",
+"01101010111",
+"01101011000",
+"01101011001",
+"01101011011",
+"01101011100",
+"01101011101",
+"01101011110",
+"01101011111",
+"01101100000",
+"01101100001",
+"01101100011",
+"01101100100",
+"01101100101",
+"01101100110",
+"01101100111",
+"01101101000",
+"01101101001",
+"01101101011",
+"01101101100",
+"01101101101",
+"01101101110",
+"01101101111",
+"01101110000",
+"01101110001",
+"01101110010",
+"01101110100",
+"01101110101",
+"01101110110",
+"01101110111",
+"01101111000",
+"01101111001",
+"01101111010",
+"01101111100",
+"01101111101",
+"01101111110",
+"01101111111",
+"01110000000",
+"01110000001",
+"01110000010",
+"01110000011",
+"01110000101",
+"01110000110",
+"01110000111",
+"01110001000",
+"01110001001",
+"01110001010",
+"01110001011",
+"01110001100",
+"01110001110",
+"01110001111",
+"01110010000",
+"01110010001",
+"01110010010",
+"01110010011",
+"01110010100",
+"01110010101",
+"01110010111",
+"01110011000",
+"01110011001",
+"01110011010",
+"01110011011",
+"01110011100",
+"01110011101",
+"01110011110",
+"01110100000",
+"01110100001",
+"01110100010",
+"01110100011",
+"01110100100",
+"01110100101",
+"01110100110",
+"01110100111",
+"01110101001",
+"01110101010",
+"01110101011",
+"01110101100",
+"01110101101",
+"01110101110",
+"01110101111",
+"01110110000",
+"01110110010",
+"01110110011",
+"01110110100",
+"01110110101",
+"01110110110",
+"01110110111",
+"01110111000",
+"01110111001",
+"01110111010",
+"01110111100",
+"01110111101",
+"01110111110",
+"01110111111",
+"01111000000",
+"01111000001",
+"01111000010",
+"01111000011",
+"01111000100",
+"01111000110",
+"01111000111",
+"01111001000",
+"01111001001",
+"01111001010",
+"01111001011",
+"01111001100",
+"01111001101",
+"01111001111",
+"01111010000",
+"01111010001",
+"01111010010",
+"01111010011",
+"01111010100",
+"01111010101",
+"01111010110",
+"01111010111",
+"01111011001",
+"01111011010",
+"01111011011",
+"01111011100",
+"01111011101",
+"01111011110",
+"01111011111",
+"01111100000",
+"01111100001",
+"01111100010",
+"01111100100",
+"01111100101",
+"01111100110",
+"01111100111",
+"01111101000",
+"01111101001",
+"01111101010",
+"01111101011",
+"01111101100",
+"01111101110",
+"01111101111",
+"01111110000",
+"01111110001",
+"01111110010",
+"01111110011",
+"01111110100",
+"01111110101",
+"01111110110",
+"01111110111",
+"01111111001",
+"01111111010",
+"01111111011",
+"01111111100",
+"01111111101",
+"01111111110",
+"01111111111",
+"10000000000",
+"10000000001",
+"10000000010",
+"10000000100",
+"10000000101",
+"10000000110",
+"10000000111",
+"10000001000",
+"10000001001",
+"10000001010",
+"10000001011",
+"10000001100",
+"10000001101",
+"10000001110",
+"10000010000",
+"10000010001",
+"10000010010",
+"10000010011",
+"10000010100",
+"10000010101",
+"10000010110",
+"10000010111",
+"10000011000",
+"10000011001",
+"10000011011",
+"10000011100",
+"10000011101",
+"10000011110",
+"10000011111",
+"10000100000",
+"10000100001",
+"10000100010",
+"10000100011",
+"10000100100",
+"10000100101",
+"10000100110",
+"10000101000",
+"10000101001",
+"10000101010",
+"10000101011",
+"10000101100",
+"10000101101",
+"10000101110",
+"10000101111",
+"10000110000",
+"10000110001",
+"10000110010",
+"10000110100",
+"10000110101",
+"10000110110",
+"10000110111",
+"10000111000",
+"10000111001",
+"10000111010",
+"10000111011",
+"10000111100",
+"10000111101",
+"10000111110",
+"10000111111",
+"10001000000",
+"10001000010",
+"10001000011",
+"10001000100",
+"10001000101",
+"10001000110",
+"10001000111",
+"10001001000",
+"10001001001",
+"10001001010",
+"10001001011",
+"10001001100",
+"10001001101",
+"10001001110",
+"10001010000",
+"10001010001",
+"10001010010",
+"10001010011",
+"10001010100",
+"10001010101",
+"10001010110",
+"10001010111",
+"10001011000",
+"10001011001",
+"10001011010",
+"10001011011",
+"10001011100",
+"10001011110",
+"10001011111",
+"10001100000",
+"10001100001",
+"10001100010",
+"10001100011",
+"10001100100",
+"10001100101",
+"10001100110",
+"10001100111",
+"10001101000",
+"10001101001",
+"10001101010",
+"10001101011",
+"10001101100",
+"10001101110",
+"10001101111",
+"10001110000",
+"10001110001",
+"10001110010",
+"10001110011",
+"10001110100",
+"10001110101",
+"10001110110",
+"10001110111",
+"10001111000",
+"10001111001",
+"10001111010",
+"10001111011",
+"10001111100",
+"10001111101",
+"10001111111",
+"10010000000",
+"10010000001",
+"10010000010",
+"10010000011",
+"10010000100",
+"10010000101",
+"10010000110",
+"10010000111",
+"10010001000",
+"10010001001",
+"10010001010",
+"10010001011",
+"10010001100",
+"10010001101",
+"10010001110",
+"10010001111",
+"10010010001",
+"10010010010",
+"10010010011",
+"10010010100",
+"10010010101",
+"10010010110",
+"10010010111",
+"10010011000",
+"10010011001",
+"10010011010",
+"10010011011",
+"10010011100",
+"10010011101",
+"10010011110",
+"10010011111",
+"10010100000",
+"10010100001",
+"10010100010",
+"10010100011",
+"10010100100",
+"10010100110",
+"10010100111",
+"10010101000",
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+"11111111001",
+"11111111010",
+"11111111010",
+"11111111011",
+"11111111100",
+"11111111100",
+"11111111101",
+"11111111110",
+"11111111110",
+"11111111111"
+);
+
+end DC_LUT_package;
+
+
+package body DC_LUT_package is
+
+
+end DC_LUT_package;
diff --git a/data_concentrator/sources/DC_Quad_fiber_module.vhd b/data_concentrator/sources/DC_Quad_fiber_module.vhd
new file mode 100644
index 0000000..cc435c5
--- /dev/null
+++ b/data_concentrator/sources/DC_Quad_fiber_module.vhd
@@ -0,0 +1,948 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   05-03-2014
+-- Module Name:   DC_Quad_fiber_module
+-- Description:   Module for the connection between cpu/multiplexer and fiber-interface
+-- Modifications:
+--   30-07-2014   Timestamp from FEE is now composed by 16 bits superburstnumber and timestamp counter within superburst
+--   29-08-2014   ADCCLOCKFREQUENCY added: SODA clock at 80MHz 
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- DC_Quad_fiber_module
+-- Module for the connection between cpu/multiplexer and dual-fiber-interface on the Panda Data collector board
+-- Slowcontrol commands from the soft-core CPU are put in fiber packets and sent to the fibers.
+-- Data packets are received from the fiber, analysed and translated to Pulse-data and slowcontrol data.
+--
+-- Library
+--     work.panda_package :  for type declarations and constants
+-- 
+-- Generics:
+--     NROFADCS : number of ADCs in each FEE
+--     ADCINDEXSHIFT : ADC channel numbers lowest bit indicates the high or low gain ADC, 0=high, 1=low
+--     ADCCLOCKFREQUENCY : Frequency of the ADCclock in Hz, defines also the SODA clock frequency
+--     CF_FRACTIONBIT : number of valid constant fraction bits
+--     ENERGYSCALINGBITS : number of scaling bits for energy adjustment: energy = (original_energy * gainfactor<<scalingbits)>>scalingbits
+--     MAX_DIVIDERSCALEBITS : number of scaling bits for division two largest samples
+--     MAX_LUTSIZEBITS : number of bits the maximum correction Look Up Table
+--     MAX_LUTSCALEBITS : number of scaling bits for the correction on the maximum (energy)
+-- 
+-- Inputs:
+--     slowcontrol_clock : clock for the slowcontrol input/output
+--     packet_clock : clock for data from the fiber module
+--     MUX_clock : clock from multiplexer, only used for multiplexer status
+--     SODA_clock : clock for SODA signals
+--     reset : reset of all components
+--     reset_fibers : reset fiber connections (serdes or GTP/GTX)
+--     channel : index of the fiber
+--     superburst_number : most recent superburst-number
+--     superburst_update : new most recent superburst-number (synchronized on SODA_clock)
+--     IO_byte : 5-bits slowcontrol data from CPU
+--         Byte0 : Read bit , "000", index of the fiber 
+--         Byte1,2,3,4 : alternating: 
+--                     request-bit 101 xxxx 24-bits_address(MSB first)
+--                     32-bits_data, MSB first
+--     IO_write : write signal for byte-data, only selected fiber (with index in first byte) should react
+--     G0_muxstat_infifo_fullness : channel0: number of words in multiplexer input fifo, report to slowcontrol
+--     muxstat_outfifo_fullness : channel0: number of words in multiplexer output fifo, report to slowcontrol
+--     timestamp_errors : channel0: number of timestamp-errors in data stream, report to slowcontrol
+--     skipped_pulses : channel0: number of pulses skipped due to buffer overflow, report to slowcontrol
+--     dataerrors : channel0: number of errors in data stream, report to slowcontrol
+--     G0_pulse_data_out_allowed : channel0: allowed to write pulse data (not fifo-full signal from connected fifo)
+--     G0_wave_data_out_allowed : channel0: allowed to write full pileup waveform data (not fifo-full signal from connected fifo)
+--     G0_TX_DLM : transmit SODA character
+--     G0_TX_DLM_WORD : SODA character to be transmitted
+--     gtpClk : reference clock for serdes, should be synchronous with SODA
+--     gtpClkDiv2 : reference clock for serdes divided by two
+--     G0_LOS : no fiber signal detected
+--     G0_gtpRxP,G0_gtpRxN : Serdes differential inputs from fiber module channel0
+--     G1_muxstat_infifo_fullness : channel1: number of words in multiplexer input fifo, report to slowcontrol
+--     G1_pulse_data_out_allowed : channel1: allowed to write pulse data (not fifo-full signal from connected fifo)
+--     G1_wave_data_out_allowed : channel1: allowed to write full pileup waveform data (not fifo-full signal from connected fifo)
+--     G1_TX_DLM : transmit SODA character
+--     G1_TX_DLM_WORD : SODA character to be transmitted
+--     G1_LOS : no fiber signal detected
+--     G1_gtpRxP,G1_gtpRxN : Serdes ifferential inputs from fiber module channel1
+--     G2_muxstat_infifo_fullness : channel2: number of words in multiplexer input fifo, report to slowcontrol
+--     G2_pulse_data_out_allowed : channel2: allowed to write pulse data (not fifo-full signal from connected fifo)
+--     G2_wave_data_out_allowed : channel2: allowed to write full pileup waveform data (not fifo-full signal from connected fifo)
+--     G2_TX_DLM : transmit SODA character
+--     G2_TX_DLM_WORD : SODA character to be transmitted
+--     G2_LOS : no fiber signal detected
+--     G2_gtpRxP,G2_gtpRxN : Serdes ifferential inputs from fiber module channel2
+--     G3_muxstat_infifo_fullness : channel3: number of words in multiplexer input fifo, report to slowcontrol
+--     G3_pulse_data_out_allowed : channel3: allowed to write pulse data (not fifo-full signal from connected fifo)
+--     G3_wave_data_out_allowed : channel3: allowed to write full pileup waveform data (not fifo-full signal from connected fifo)
+--     G3_TX_DLM : transmit SODA character
+--     G3_TX_DLM_WORD : SODA character to be transmitted
+--     G3_LOS : no fiber signal detected
+--     G3_gtpRxP,G3_gtpRxN : Serdes ifferential inputs from fiber module channel3
+--     SCI_DATA_IN : serdes control interface : data
+--     SCI_ADDR : serdes control interface : address
+--     SCI_READ : serdes control interface : read
+--     SCI_WRITE : serdes control interface : write
+-- 
+-- Outputs:
+--     refClkOut : buffered output of the GTP/GTX reference clock
+--     refClk_OK : GTP/GTX reference clock is valid (PLL locked)
+--     G0_IO_serialdata : Channel0: Serial slowcontrol: request&address or data alternating
+--     G0_IO_serialavailable : Slowcontrol data is available from channel0
+--     G1_IO_serialdata : Channel1: Serial slowcontrol: request&address or data alternating
+--     G1_IO_serialavailable : Slowcontrol data is available from channel1
+--     G2_IO_serialdata : Channel2: Serial slowcontrol: request&address or data alternating
+--     G2_IO_serialavailable : Slowcontrol data is available from channel2
+--     G3_IO_serialdata : Channel3: Serial slowcontrol: request&address or data alternating
+--     G3_IO_serialavailable : Slowcontrol data is available from channel3
+--     G0_pulse_data_out : channel0: 36 bits data with Feature Extraction Results, each 4*36-bits:
+--         word0 : 0 & 0000 & timestamp(15..0)
+--         word1 : 1 & 0 & superburstnumber(30..0)
+--         word2 : 2 & statusbyte & 00 & adcnumber
+--         word3 : 3 & timefraction & energy
+--     G0_pulse_data_write : write signal for pulse data from channel0
+--     G0_wave_data_out : channel0: 36 bits data with pileup waveforms:
+--        	bits(35..32)="0000" : bits(15..0)=timestamp of maximum value in waveform
+--        	bits(35..32)="0001" : bits(31)=0 bits(30..0)=SuperBurst number
+--        	bits(35..32)="0010" : 
+--              bits(31..24) = statusbyte (bit7=overflow) 
+--              bits(23..16) = 00
+--              bits(15..0) = adcnumber (channel identification)
+--        	bits(35..32)="0011" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+--        	bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+--        	bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+--        	bits(35..32)="1111" : error: buffer full, waveform not valid
+--     G0_wave_data_write : write signal for pileup waveform data from channel0
+--     G0_resetDone : channel0: reset done signal, used for transmit clock divider
+--     G0_txLocked : channel0: transmitter locked signal, used for transmit clock divider
+--     G0_rxLocked : channel0: receiver locked signal
+--     G0_RX_DLM : SODA character received
+--     G0_RX_DLM_WORD : SODA character 
+--     G0_gtpTxP,G0_gtpTxN : Serdes differential outputs to fiber module0
+--     G1_pulse_data_out : channel1: 36 bits data with Feature Extraction Results, each 4*36-bits:
+--         word0 : 0 & 0000 & timestamp(15..0)
+--         word1 : 1 & 0 & superburstnumber(30..0)
+--         word2 : 2 & statusbyte & 00 & adcnumber
+--         word3 : 3 & timefraction & energy
+--     G1_pulse_data_write : write signal for pulse data from channel1
+--     G1_wave_data_out : channel1: 36 bits data with pileup waveforms:
+--        	bits(35..32)="0000" : bits(15..0)=timestamp of maximum value in waveform
+--        	bits(35..32)="0001" : bits(31)=0 bits(30..0)=SuperBurst number
+--        	bits(35..32)="0010" : 
+--              bits(31..24) = statusbyte (bit7=overflow) 
+--              bits(23..16) = 00
+--              bits(15..0) = adcnumber (channel identification)
+--        	bits(35..32)="0011" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+--        	bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+--        	bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+--        	bits(35..32)="1111" : error: buffer full, waveform not valid
+--     G1_wave_data_write : write signal for pileup waveform data from channel1
+--     G1_resetDone : channel1: reset done signal, used for transmit clock divider
+--     G1_txLocked : channel1: transmitter locked signal, used for transmit clock divider
+--     G1_rxLocked : channel1: receiver locked signal
+--     G1_RX_DLM : SODA character received
+--     G1_RX_DLM_WORD : SODA character 
+--     G1_gtpTxP,G0_gtpTxN : Serdes differential outputs to fiber module1
+--     G2_pulse_data_out : channel2: 36 bits data with Feature Extraction Results, each 4*36-bits:
+--         word0 : 0 & 0000 & timestamp(15..0)
+--         word1 : 1 & 0 & superburstnumber(30..0)
+--         word2 : 2 & statusbyte & 00 & adcnumber
+--         word3 : 3 & timefraction & energy
+--     G2_pulse_data_write : write signal for pulse data from channel2
+--     G2_wave_data_out : channel2: 36 bits data with pileup waveforms:
+--        	bits(35..32)="0000" : bits(15..0)=timestamp of maximum value in waveform
+--        	bits(35..32)="0001" : bits(31)=0 bits(30..0)=SuperBurst number
+--        	bits(35..32)="0010" : 
+--              bits(31..24) = statusbyte (bit7=overflow) 
+--              bits(23..16) = 00
+--              bits(15..0) = adcnumber (channel identification)
+--        	bits(35..32)="0011" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+--        	bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+--        	bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+--        	bits(35..32)="1111" : error: buffer full, waveform not valid
+--     G2_wave_data_write : write signal for pileup waveform data from channel2
+--     G2_resetDone : channel2: reset done signal, used for transmit clock divider
+--     G2_txLocked : channel2: transmitter locked signal, used for transmit clock divider
+--     G2_rxLocked : channel2: receiver locked signal
+--     G2_RX_DLM : SODA character received
+--     G2_RX_DLM_WORD : SODA character 
+--     G2_gtpTxP,G0_gtpTxN : Serdes differential outputs to fiber module2
+--     G3_pulse_data_out : channel3: 36 bits data with Feature Extraction Results, each 4*36-bits:
+--         word0 : 0 & 0000 & timestamp(15..0)
+--         word1 : 1 & 0 & superburstnumber(30..0)
+--         word2 : 2 & statusbyte & 00 & adcnumber
+--         word3 : 3 & timefraction & energy
+--     G3_pulse_data_write : write signal for pulse data from channel3
+--     G3_wave_data_out : channel3: 36 bits data with pileup waveforms:
+--        	bits(35..32)="0000" : bits(15..0)=timestamp of maximum value in waveform
+--        	bits(35..32)="0001" : bits(31)=0 bits(30..0)=SuperBurst number
+--        	bits(35..32)="0010" : 
+--              bits(31..24) = statusbyte (bit7=overflow) 
+--              bits(23..16) = 00
+--              bits(15..0) = adcnumber (channel identification)
+--        	bits(35..32)="0011" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+--        	bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+--        	bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+--        	bits(35..32)="1111" : error: buffer full, waveform not valid
+--     G3_wave_data_write : write signal for pileup waveform data from channel3
+--     G3_resetDone : channel3: reset done signal, used for transmit clock divider
+--     G3_txLocked : channel3: transmitter locked signal, used for transmit clock divider
+--     G3_rxLocked : channel3: receiver locked signal
+--     G3_RX_DLM : SODA character received
+--     G3_RX_DLM_WORD : SODA character 
+--     G3_gtpTxP,G0_gtpTxN : Serdes differential outputs to fiber module3
+--     SCI_DATA_OUT : serdes control interface : data
+--     SCI_ACK : serdes control interface : acknowledge
+--     SCI_NACK : serdes control interface : not acknowledge
+--     LEDs_link_ok : serdes status for LED on extension board : link ok
+--     LEDs_rx : serdes status for LED on extension board : receive
+--     LEDs_tx : serdes status for LED on extension board : transmit
+-- 
+-- Components:
+--     DC_fibermodule_interface : Module with slowcontrol translation, data receive, packet builder for one channel
+--     serdesQuadBufLayerMUX : quad serdes with transmitter synchronized and 16-bits interface
+--
+----------------------------------------------------------------------------------
+
+entity DC_Quad_fiber_module is
+	generic (
+		NROFADCS                : natural := 16;
+		ADCINDEXSHIFT           : natural := 1;
+		ADCBITS                 : natural := 14;
+		ADCCLOCKFREQUENCY       : natural := 62500000;
+		CF_FRACTIONBIT          : natural := 11;
+		ENERGYSCALINGBITS       : natural := 13;
+		MAX_DIVIDERSCALEBITS    : natural := 12;
+		MAX_LUTSIZEBITS         : natural := 8;
+		MAX_LUTSCALEBITS        : natural := 14
+	);
+	port ( 
+		slowcontrol_clock       : in std_logic;
+		packet_clock            : in std_logic;
+		MUX_clock               : in std_logic;
+		SODA_clock              : in std_logic;
+		reset                   : in std_logic;
+		reset_fibers            : in std_logic;
+		channel                 : in std_logic_vector (3 downto 0);
+		superburst_number       : in std_logic_vector(30 downto 0);
+		superburst_update       : in std_logic;
+
+-- txUsr clock
+		refClkOut               : out std_logic;
+		refClk_OK               : out std_logic;
+		txpll_clocks            : out std_logic_vector(3 downto 0);
+
+-- SlowControl to/from cpu
+		IO_byte                 : in std_logic_vector(7 downto 0);
+		IO_write                : in std_logic;
+		G0_IO_serialdata        : out std_logic;
+		G0_IO_serialavailable   : out std_logic;
+		G1_IO_serialdata        : out std_logic;
+		G1_IO_serialavailable   : out std_logic;
+		G2_IO_serialdata        : out std_logic;
+		G2_IO_serialavailable   : out std_logic;
+		G3_IO_serialdata        : out std_logic;
+		G3_IO_serialavailable   : out std_logic;
+		
+-- multiplexer status
+		G0_muxstat_infifo_fullness : in std_logic_vector (15 downto 0);
+		muxstat_outfifo_fullness : in std_logic_vector (15 downto 0);
+		timestamp_errors        : in std_logic_vector(9 downto 0);
+		skipped_pulses          : in std_logic_vector(9 downto 0);
+		dataerrors              : in std_logic_vector(9 downto 0);
+
+-- Pulse data
+		G0_pulse_data_out       : out std_logic_vector(35 downto 0);
+		G0_pulse_data_write     : out std_logic;
+		G0_pulse_data_out_allowed  : in std_logic;
+
+-- Wave data
+		G0_wave_data_out        : out std_logic_vector(35 downto 0);
+		G0_wave_data_write      : out std_logic;
+		G0_wave_data_out_allowed: in std_logic;
+		
+-- Status
+		G0_resetDone            : out std_logic;
+		G0_txLocked             : out std_logic;
+		G0_rxLocked             : out std_logic;
+	
+-- SODA 
+		G0_TX_DLM               : in  std_logic := '0';
+		G0_TX_DLM_WORD          : in  std_logic_vector(7 downto 0) := x"00";   
+		G0_RX_DLM               : out std_logic;
+		G0_RX_DLM_WORD          : out std_logic_vector(7 downto 0);
+		
+-- fiber interface signals:
+		gtpClk                  : in std_logic; -- 200MHz = SODA
+		gtpClkDiv2              : in std_logic; -- 100MHz
+		G0_LOS                  : in std_logic;
+		G0_gtpTxP               : out std_logic;
+		G0_gtpTxN               : out std_logic;
+		G0_gtpRxP               : in std_logic;
+		G0_gtpRxN               : in std_logic;
+
+-- multiplexer status
+		G1_muxstat_infifo_fullness : in std_logic_vector (15 downto 0);
+
+-- Pulse data
+		G1_pulse_data_out       : out std_logic_vector(35 downto 0);
+		G1_pulse_data_write     : out std_logic;
+		G1_pulse_data_out_allowed  : in std_logic;
+
+-- Wave data
+		G1_wave_data_out        : out std_logic_vector(35 downto 0);
+		G1_wave_data_write      : out std_logic;
+		G1_wave_data_out_allowed: in std_logic;
+
+-- Status
+		G1_resetDone            : out std_logic;
+		G1_txLocked             : out std_logic;
+		G1_rxLocked             : out std_logic;
+		
+-- SODA 
+		G1_TX_DLM               : in  std_logic := '0';
+		G1_TX_DLM_WORD          : in  std_logic_vector(7 downto 0) := x"00";   
+		G1_RX_DLM               : out std_logic;
+		G1_RX_DLM_WORD          : out std_logic_vector(7 downto 0);
+
+-- fiber interface signals:
+		G1_LOS                  : in std_logic;
+		G1_gtpTxP               : out std_logic;
+		G1_gtpTxN               : out std_logic;
+		G1_gtpRxP               : in std_logic;
+		G1_gtpRxN               : in std_logic;
+
+-- multiplexer status
+		G2_muxstat_infifo_fullness : in std_logic_vector (15 downto 0);
+
+-- Pulse data
+		G2_pulse_data_out       : out std_logic_vector(35 downto 0);
+		G2_pulse_data_write     : out std_logic;
+		G2_pulse_data_out_allowed  : in std_logic;
+
+-- Wave data
+		G2_wave_data_out        : out std_logic_vector(35 downto 0);
+		G2_wave_data_write      : out std_logic;
+		G2_wave_data_out_allowed: in std_logic;
+
+-- Status
+		G2_resetDone            : out std_logic;
+		G2_txLocked             : out std_logic;
+		G2_rxLocked             : out std_logic;
+		
+-- SODA 
+		G2_TX_DLM               : in  std_logic := '0';
+		G2_TX_DLM_WORD          : in  std_logic_vector(7 downto 0) := x"00";   
+		G2_RX_DLM               : out std_logic;
+		G2_RX_DLM_WORD          : out std_logic_vector(7 downto 0);
+		
+-- fiber interface signals:
+		G2_LOS                  : in std_logic;
+		G2_gtpTxP               : out std_logic;
+		G2_gtpTxN               : out std_logic;
+		G2_gtpRxP               : in std_logic;
+		G2_gtpRxN               : in std_logic;
+
+-- multiplexer status
+		G3_muxstat_infifo_fullness : in std_logic_vector (15 downto 0);
+
+-- Pulse data
+		G3_pulse_data_out       : out std_logic_vector(35 downto 0);
+		G3_pulse_data_write     : out std_logic;
+		G3_pulse_data_out_allowed  : in std_logic;
+
+-- Wave data
+		G3_wave_data_out        : out std_logic_vector(35 downto 0);
+		G3_wave_data_write      : out std_logic;
+		G3_wave_data_out_allowed: in std_logic;
+
+-- Status
+		G3_resetDone            : out std_logic;
+		G3_txLocked             : out std_logic;
+		G3_rxLocked             : out std_logic;
+		
+-- SODA 
+		G3_TX_DLM               : in  std_logic := '0';
+		G3_TX_DLM_WORD          : in  std_logic_vector(7 downto 0) := x"00";   
+		G3_RX_DLM               : out std_logic;
+		G3_RX_DLM_WORD          : out std_logic_vector(7 downto 0);
+		
+-- fiber interface signals:
+		G3_LOS                  : in std_logic;
+		G3_gtpTxP               : out std_logic;
+		G3_gtpTxN               : out std_logic;
+		G3_gtpRxP               : in std_logic;
+		G3_gtpRxN               : in std_logic;
+		
+		--Control Interface
+		SCI_DATA_IN             : in  std_logic_vector(7 downto 0) := (others => '0');
+		SCI_DATA_OUT            : out std_logic_vector(7 downto 0) := (others => '0');
+		SCI_ADDR                : in  std_logic_vector(8 downto 0) := (others => '0');
+		SCI_READ                : in  std_logic := '0';
+		SCI_WRITE               : in  std_logic := '0';
+		SCI_ACK                 : out std_logic := '0';
+		SCI_NACK                : out std_logic := '0';
+
+-- tests		
+		LEDs_link_ok            : out std_logic_vector(0 to 3);
+		LEDs_rx                 : out std_logic_vector(0 to 3); 
+		LEDs_tx                 : out std_logic_vector(0 to 3);
+		testword0               : out std_logic_vector (35 downto 0);
+		testword0clock          : out std_logic;
+		testword1               : out std_logic_vector (35 downto 0);
+		testPin                 : out std_logic_vector (3 downto 0)
+		);
+end DC_Quad_fiber_module;
+
+architecture Behavioral of DC_Quad_fiber_module is
+
+component DC_fibermodule_interface is
+	generic (
+		NROFADCS                : natural := NROFADCS;
+		ADCINDEXSHIFT           : natural := ADCINDEXSHIFT;
+		ADCBITS                 : natural := ADCBITS;
+		CF_FRACTIONBIT          : natural := CF_FRACTIONBIT;
+		ENERGYSCALINGBITS       : natural := ENERGYSCALINGBITS;
+		MAX_DIVIDERSCALEBITS    : natural := MAX_DIVIDERSCALEBITS;
+		MAX_LUTSIZEBITS         : natural := MAX_LUTSIZEBITS;
+		MAX_LUTSCALEBITS        : natural := MAX_LUTSCALEBITS
+	);
+	port ( 
+		slowcontrol_clock       : in std_logic;
+		packet_clock            : in std_logic;
+		MUX_clock               : in std_logic;
+		SODA_clock              : in std_logic;
+		reset                   : in std_logic;
+		resetDone               : in std_logic;
+		channel                 : in std_logic_vector (3 downto 0);
+		superburst_number       : in std_logic_vector(30 downto 0);
+		superburst_update       : in std_logic;
+
+-- SlowControl to/from cpu
+		IO_byte                 : in std_logic_vector(7 downto 0);
+		IO_write                : in std_logic;
+		IO_serialdata           : out std_logic;
+		IO_serialavailable      : out std_logic;
+		
+-- multiplexer status
+		muxstat_infifo_fullness : in std_logic_vector (15 downto 0);
+		muxstat_outfifo_fullness : in std_logic_vector (15 downto 0);
+		timestamp_errors        : in std_logic_vector(9 downto 0);
+		skipped_pulses          : in std_logic_vector(9 downto 0);
+		dataerrors              : in std_logic_vector(9 downto 0);
+		
+-- Pulse data
+		pulse_data_out          : out std_logic_vector (35 downto 0);
+		pulse_data_write        : out std_logic;
+		pulse_data_out_allowed  : in std_logic;
+
+-- Wave data
+		wave_data_out           : out std_logic_vector(35 downto 0);
+		wave_data_write         : out std_logic;
+		wave_data_out_allowed   : in std_logic;
+
+-- Testpoints
+		testword0               : out std_logic_vector (35 downto 0);
+		testword1               : out std_logic_vector (35 downto 0);
+
+-- MUX tx interface signals:
+		txAsyncDataWrite        : out std_logic;
+		txAsyncData             : out std_logic_vector(31 downto 0);
+		txEndOfAsyncData        : out std_logic;
+		txAsyncFifoFull         : in std_logic;
+		txLocked                : in std_logic;
+
+-- MUX rx interface signals:
+		rxAsyncClk              : out std_logic;
+		rxAsyncDataRead         : out std_logic;
+		rxAsyncDataPresent      : in std_logic;
+		rxAsyncData             : in std_logic_vector(31 downto 0);
+		rxNotInTable            : in std_logic;
+		rxLocked                : in std_logic
+		);
+end component;
+
+component serdesQuadBufLayerMUX is 
+	port (
+		gtpClk                  : in std_logic;
+		sysClk                  : in  std_logic;
+		reset                   : in std_logic;
+		reset_fibers            : in std_logic;
+		txAsyncClk              : in std_logic;
+		rxAsyncClk              : in std_logic;
+
+		txUsrClkDiv2            : in std_logic;
+		refClkOut               : out std_logic;
+		refClk_OK               : out std_logic;
+		txpll_clocks            : out std_logic_vector(3 downto 0);
+
+		G0_txAsyncData          : in std_logic_vector (31 downto 0);
+		G0_txAsyncDataWrite     : in std_logic;
+		G0_txAsyncFifoFull      : out std_logic;
+		G0_rxAsyncData          : out std_logic_vector (31 downto 0);
+		G0_rxAsyncDataRead      : in std_logic;
+		G0_rxAsyncDataOverflow  : out std_logic;
+		G0_rxAsyncDataPresent   : out std_logic;
+		G0_status               : out std_logic_vector (7 downto 0);
+		G0_TX_DLM               : in  std_logic;
+		G0_TX_DLM_WORD          : in  std_logic_vector(7 downto 0);  
+		G0_RX_DLM               : out std_logic;
+		G0_RX_DLM_WORD          : out std_logic_vector(7 downto 0);
+		G0_LOS                  : in std_logic;
+		G0_txP                  : out std_logic;
+		G0_txN                  : out std_logic;
+		G0_rxP                  : in std_logic;
+		G0_rxN                  : in std_logic;
+  
+		G1_txAsyncData          : in std_logic_vector (31 downto 0);
+		G1_txAsyncDataWrite     : in std_logic;
+		G1_txAsyncFifoFull      : out std_logic;
+		G1_rxAsyncData          : out std_logic_vector (31 downto 0);
+		G1_rxAsyncDataRead      : in std_logic;
+		G1_rxAsyncDataOverflow  : out std_logic;
+		G1_rxAsyncDataPresent   : out std_logic;
+		G1_status               : out std_logic_vector (7 downto 0);
+		G1_TX_DLM               : in  std_logic;
+		G1_TX_DLM_WORD          : in  std_logic_vector(7 downto 0);  
+		G1_RX_DLM               : out std_logic;
+		G1_RX_DLM_WORD          : out std_logic_vector(7 downto 0);
+		G1_LOS                  : in std_logic;
+		G1_txP                  : out std_logic;
+		G1_txN                  : out std_logic;
+		G1_rxP                  : in std_logic;
+		G1_rxN                  : in std_logic;
+
+		G2_txAsyncData          : in std_logic_vector (31 downto 0);
+		G2_txAsyncDataWrite     : in std_logic;
+		G2_txAsyncFifoFull      : out std_logic;
+		G2_rxAsyncData          : out std_logic_vector (31 downto 0);
+		G2_rxAsyncDataRead      : in std_logic;
+		G2_rxAsyncDataOverflow  : out std_logic;
+		G2_rxAsyncDataPresent   : out std_logic;
+		G2_status               : out std_logic_vector (7 downto 0);
+		G2_TX_DLM               : in  std_logic;
+		G2_TX_DLM_WORD          : in  std_logic_vector(7 downto 0);  
+		G2_RX_DLM               : out std_logic;
+		G2_RX_DLM_WORD          : out std_logic_vector(7 downto 0);
+		G2_LOS                  : in std_logic;
+		G2_txP                  : out std_logic;
+		G2_txN                  : out std_logic;
+		G2_rxP                  : in std_logic;
+		G2_rxN                  : in std_logic;
+
+		G3_txAsyncData          : in std_logic_vector (31 downto 0);
+		G3_txAsyncDataWrite     : in std_logic;
+		G3_txAsyncFifoFull      : out std_logic;
+		G3_rxAsyncData          : out std_logic_vector (31 downto 0);
+		G3_rxAsyncDataRead      : in std_logic;
+		G3_rxAsyncDataOverflow  : out std_logic;
+		G3_rxAsyncDataPresent   : out std_logic;
+		G3_status               : out std_logic_vector (7 downto 0);
+		G3_TX_DLM               : in  std_logic;
+		G3_TX_DLM_WORD          : in  std_logic_vector(7 downto 0);   
+		G3_RX_DLM               : out std_logic;
+		G3_RX_DLM_WORD          : out std_logic_vector(7 downto 0);
+		G3_LOS                  : in std_logic;
+		G3_txP                  : out std_logic;
+		G3_txN                  : out std_logic;
+		G3_rxP                  : in std_logic;
+		G3_rxN                  : in std_logic;
+
+		--Control Interface
+		SCI_DATA_IN             : in  std_logic_vector(7 downto 0) := (others => '0');
+		SCI_DATA_OUT            : out std_logic_vector(7 downto 0) := (others => '0');
+		SCI_ADDR                : in  std_logic_vector(8 downto 0) := (others => '0');
+		SCI_READ                : in  std_logic := '0';
+		SCI_WRITE               : in  std_logic := '0';
+		SCI_ACK                 : out std_logic := '0';
+		SCI_NACK                : out std_logic := '0';
+
+		LEDs_link_ok            : out std_logic_vector(0 to 3);
+		LEDs_rx                 : out std_logic_vector(0 to 3); 
+		LEDs_tx                 : out std_logic_vector(0 to 3);
+
+		testPin                 : out  std_logic_vector(3 downto 0);
+		testword0               : out std_logic_vector (35 downto 0); 
+		testword0clock          : out std_logic
+	);
+end component;
+
+
+signal G0_txAsyncDataWrite_S  : std_logic;
+signal G0_txAsyncData_S       : std_logic_vector(31 downto 0);
+signal G0_txEndOfAsyncData_S  : std_logic;
+signal G0_txAsyncFifoFull_S   : std_logic;
+
+signal G0_rxAsyncClk_S        : std_logic;
+signal G0_rxAsyncDataRead_S   : std_logic;
+signal G0_rxAsyncDataPresent_S: std_logic;
+signal G0_rxAsyncData_S       : std_logic_vector(31 downto 0);
+
+signal G0_channel_S           : std_logic_vector(3 downto 0);
+signal G0_status_S            : std_logic_vector(7 downto 0);
+signal G0_resetDone_S         : std_logic;
+signal G0_txLocked_S          : std_logic;
+signal G0_rxLocked_S          : std_logic;
+signal G0_rxNotInTable_S      : std_logic;
+
+signal G1_txAsyncDataWrite_S  : std_logic;
+signal G1_txAsyncData_S       : std_logic_vector(31 downto 0);
+signal G1_txEndOfAsyncData_S  : std_logic;
+signal G1_txAsyncFifoFull_S   : std_logic;
+
+signal G1_rxAsyncClk_S        : std_logic;
+signal G1_rxAsyncDataRead_S   : std_logic;
+signal G1_rxAsyncDataPresent_S: std_logic;
+signal G1_rxAsyncData_S       : std_logic_vector(31 downto 0);
+
+signal G1_channel_S           : std_logic_vector(3 downto 0);
+signal G1_status_S            : std_logic_vector(7 downto 0);
+signal G1_resetDone_S         : std_logic;
+signal G1_txLocked_S          : std_logic;
+signal G1_rxLocked_S          : std_logic;
+signal G1_rxNotInTable_S      : std_logic;
+
+signal G2_txAsyncDataWrite_S  : std_logic;
+signal G2_txAsyncData_S       : std_logic_vector(31 downto 0);
+signal G2_txEndOfAsyncData_S  : std_logic;
+signal G2_txAsyncFifoFull_S   : std_logic;
+
+signal G2_rxAsyncClk_S        : std_logic;
+signal G2_rxAsyncDataRead_S   : std_logic;
+signal G2_rxAsyncDataPresent_S: std_logic;
+signal G2_rxAsyncData_S       : std_logic_vector(31 downto 0);
+
+signal G2_channel_S           : std_logic_vector(3 downto 0);
+signal G2_status_S            : std_logic_vector(7 downto 0);
+signal G2_resetDone_S         : std_logic;
+signal G2_txLocked_S          : std_logic;
+signal G2_rxLocked_S          : std_logic;
+signal G2_rxNotInTable_S      : std_logic;
+
+signal G3_txAsyncDataWrite_S  : std_logic;
+signal G3_txAsyncData_S       : std_logic_vector(31 downto 0);
+signal G3_txEndOfAsyncData_S  : std_logic;
+signal G3_txAsyncFifoFull_S   : std_logic;
+
+signal G3_rxAsyncClk_S        : std_logic;
+signal G3_rxAsyncDataRead_S   : std_logic;
+signal G3_rxAsyncDataPresent_S: std_logic;
+signal G3_rxAsyncData_S       : std_logic_vector(31 downto 0);
+
+signal G3_channel_S           : std_logic_vector(3 downto 0);
+signal G3_status_S            : std_logic_vector(7 downto 0);
+signal G3_resetDone_S         : std_logic;
+signal G3_txLocked_S          : std_logic;
+signal G3_rxLocked_S          : std_logic;
+signal G3_rxNotInTable_S      : std_logic;
+
+signal testword0_S            : std_logic_vector(35 downto 0);
+signal testword1_S            : std_logic_vector(35 downto 0);
+
+begin
+
+G0_DC_fibermodule_interface: DC_fibermodule_interface port map(
+		slowcontrol_clock => slowcontrol_clock,
+		packet_clock => packet_clock,
+		MUX_clock => MUX_clock,
+		SODA_clock => SODA_clock,
+		reset => reset,
+		resetDone => G0_resetDone_S,
+		channel => G0_channel_S,
+		superburst_number => superburst_number,
+		superburst_update => superburst_update,
+		IO_byte => IO_byte,
+		IO_write => IO_write,
+		IO_serialdata => G0_IO_serialdata,
+		IO_serialavailable => G0_IO_serialavailable,
+		muxstat_infifo_fullness => G0_muxstat_infifo_fullness,
+		muxstat_outfifo_fullness => muxstat_outfifo_fullness,
+		timestamp_errors => timestamp_errors,
+		skipped_pulses => skipped_pulses,
+		dataerrors => dataerrors,
+		pulse_data_out => G0_pulse_data_out,
+		pulse_data_write => G0_pulse_data_write,
+		pulse_data_out_allowed => G0_pulse_data_out_allowed,
+		wave_data_out => G0_wave_data_out,
+		wave_data_write => G0_wave_data_write,
+		wave_data_out_allowed => G0_wave_data_out_allowed,
+		testword0 => open,
+		testword1 => testword1,
+		txAsyncDataWrite => G0_txAsyncDataWrite_S,
+		txAsyncData => G0_txAsyncData_S,
+		txEndOfAsyncData => G0_txEndOfAsyncData_S,
+		txAsyncFifoFull => G0_txAsyncFifoFull_S,
+		txLocked => G0_txLocked_S,
+		rxAsyncClk => G0_rxAsyncClk_S,
+		rxAsyncDataRead => G0_rxAsyncDataRead_S,
+		rxAsyncDataPresent => G0_rxAsyncDataPresent_S,
+		rxAsyncData => G0_rxAsyncData_S,
+		rxNotInTable => G0_rxNotInTable_S,
+		rxLocked => G0_rxLocked_S);
+G0_channel_S <= channel(3 downto 2) & "00";
+
+G1_DC_fibermodule_interface: DC_fibermodule_interface port map(
+		slowcontrol_clock => slowcontrol_clock,
+		packet_clock => packet_clock,
+		MUX_clock => MUX_clock,
+		SODA_clock => SODA_clock,
+		reset => reset,
+		resetDone => G1_resetDone_S,
+		channel => G1_channel_S,
+		superburst_number => superburst_number,
+		superburst_update => superburst_update,
+		IO_byte => IO_byte,
+		IO_write => IO_write,
+		IO_serialdata => G1_IO_serialdata,
+		IO_serialavailable => G1_IO_serialavailable,
+		muxstat_infifo_fullness => G1_muxstat_infifo_fullness,
+		muxstat_outfifo_fullness => (others => '0'),
+		timestamp_errors => (others => '0'),
+		skipped_pulses => (others => '0'),
+		dataerrors => (others => '0'),
+		pulse_data_out => G1_pulse_data_out,
+		pulse_data_write => G1_pulse_data_write,
+		pulse_data_out_allowed => G1_pulse_data_out_allowed,
+		wave_data_out => G1_wave_data_out,
+		wave_data_write => G1_wave_data_write,
+		wave_data_out_allowed => G1_wave_data_out_allowed,
+		testword0 => open,
+		testword1 => open,
+		txAsyncDataWrite => G1_txAsyncDataWrite_S,
+		txAsyncData => G1_txAsyncData_S,
+		txEndOfAsyncData => G1_txEndOfAsyncData_S,
+		txAsyncFifoFull => G1_txAsyncFifoFull_S,
+		txLocked => G1_txLocked_S,
+		rxAsyncClk => G1_rxAsyncClk_S,
+		rxAsyncDataRead => G1_rxAsyncDataRead_S,
+		rxAsyncDataPresent => G1_rxAsyncDataPresent_S,
+		rxAsyncData => G1_rxAsyncData_S,
+		rxNotInTable => G1_rxNotInTable_S,
+		rxLocked => G1_rxLocked_S);
+G1_channel_S <= channel(3 downto 2) & "01";
+		
+G2_DC_fibermodule_interface: DC_fibermodule_interface port map(
+		slowcontrol_clock => slowcontrol_clock,
+		packet_clock => packet_clock,
+		MUX_clock => MUX_clock,
+		SODA_clock => SODA_clock,
+		reset => reset,
+		resetDone => G2_resetDone_S,
+		channel => G2_channel_S,
+		superburst_number => superburst_number,
+		superburst_update => superburst_update,
+		IO_byte => IO_byte,
+		IO_write => IO_write,
+		IO_serialdata => G2_IO_serialdata,
+		IO_serialavailable => G2_IO_serialavailable,
+		muxstat_infifo_fullness => G2_muxstat_infifo_fullness,
+		muxstat_outfifo_fullness => (others => '0'),
+		timestamp_errors => (others => '0'),
+		skipped_pulses => (others => '0'),
+		dataerrors => (others => '0'),
+		pulse_data_out => G2_pulse_data_out,
+		pulse_data_write => G2_pulse_data_write,
+		pulse_data_out_allowed => G2_pulse_data_out_allowed,
+		wave_data_out => G2_wave_data_out,
+		wave_data_write => G2_wave_data_write,
+		wave_data_out_allowed => G2_wave_data_out_allowed,
+		testword0 => open,
+		testword1 => open,
+		txAsyncDataWrite => G2_txAsyncDataWrite_S,
+		txAsyncData => G2_txAsyncData_S,
+		txEndOfAsyncData => G2_txEndOfAsyncData_S,
+		txAsyncFifoFull => G2_txAsyncFifoFull_S,
+		txLocked => G2_txLocked_S,
+		rxAsyncClk => G2_rxAsyncClk_S,
+		rxAsyncDataRead => G2_rxAsyncDataRead_S,
+		rxAsyncDataPresent => G2_rxAsyncDataPresent_S,
+		rxAsyncData => G2_rxAsyncData_S,
+		rxNotInTable => G2_rxNotInTable_S,
+		rxLocked => G2_rxLocked_S);
+G2_channel_S <= channel(3 downto 2) & "10";
+
+G3_DC_fibermodule_interface: DC_fibermodule_interface port map(
+		slowcontrol_clock => slowcontrol_clock,
+		packet_clock => packet_clock,
+		MUX_clock => MUX_clock,
+		SODA_clock => SODA_clock,
+		reset => reset,
+		resetDone => G3_resetDone_S,
+		channel => G3_channel_S,
+		superburst_number => superburst_number,
+		superburst_update => superburst_update,
+		IO_byte => IO_byte,
+		IO_write => IO_write,
+		IO_serialdata => G3_IO_serialdata,
+		IO_serialavailable => G3_IO_serialavailable,
+		muxstat_infifo_fullness => G3_muxstat_infifo_fullness,
+		muxstat_outfifo_fullness => (others => '0'),
+		timestamp_errors => (others => '0'),
+		skipped_pulses => (others => '0'),
+		dataerrors => (others => '0'),
+		pulse_data_out => G3_pulse_data_out,
+		pulse_data_write => G3_pulse_data_write,
+		pulse_data_out_allowed => G3_pulse_data_out_allowed,
+		wave_data_out => G3_wave_data_out,
+		wave_data_write => G3_wave_data_write,
+		wave_data_out_allowed => G3_wave_data_out_allowed,
+		testword0 => open,
+		testword1 => open,
+		txAsyncDataWrite => G3_txAsyncDataWrite_S,
+		txAsyncData => G3_txAsyncData_S,
+		txEndOfAsyncData => G3_txEndOfAsyncData_S,
+		txAsyncFifoFull => G3_txAsyncFifoFull_S,
+		txLocked => G3_txLocked_S,
+		rxAsyncClk => G3_rxAsyncClk_S,
+		rxAsyncDataRead => G3_rxAsyncDataRead_S,
+		rxAsyncDataPresent => G3_rxAsyncDataPresent_S,
+		rxAsyncData => G3_rxAsyncData_S,
+		rxNotInTable => G3_rxNotInTable_S,
+		rxLocked => G3_rxLocked_S);
+G3_channel_S <= channel(3 downto 2) & "11";
+
+serdesQuadBufLayerMUX1: serdesQuadBufLayerMUX port map(
+		gtpClk => gtpClk,
+		sysClk => slowcontrol_clock, 
+		reset => reset,
+		reset_fibers => reset_fibers,
+		txAsyncClk => slowcontrol_clock, 
+		rxAsyncClk => packet_clock,
+
+		txUsrClkDiv2 => gtpClkDiv2,
+		refClkOut => refClkOut,
+		refClk_OK => refClk_OK,
+		txpll_clocks => txpll_clocks,
+		
+		G0_txAsyncData => G0_txAsyncData_S,
+		G0_txAsyncDataWrite => G0_txAsyncDataWrite_S,
+		G0_txAsyncFifoFull => G0_txAsyncFifoFull_S,
+		G0_rxAsyncData => G0_rxAsyncData_S,
+		G0_rxAsyncDataRead => G0_rxAsyncDataRead_S,
+		G0_rxAsyncDataOverflow => open,
+		G0_rxAsyncDataPresent => G0_rxAsyncDataPresent_S,
+		G0_status => G0_status_S,
+		G0_TX_DLM => G0_TX_DLM,
+		G0_TX_DLM_WORD => G0_TX_DLM_WORD,
+		G0_RX_DLM => G0_RX_DLM,
+		G0_RX_DLM_WORD => G0_RX_DLM_WORD,
+		G0_LOS => G0_LOS,
+		G0_txP => G0_gtpTxP,
+		G0_txN => G0_gtpTxN,
+		G0_rxP => G0_gtpRxP,
+		G0_rxN => G0_gtpRxN,
+
+		G1_txAsyncData => G1_txAsyncData_S,
+		G1_txAsyncDataWrite => G1_txAsyncDataWrite_S,
+		G1_txAsyncFifoFull => G1_txAsyncFifoFull_S,
+		G1_rxAsyncData => G1_rxAsyncData_S,
+		G1_rxAsyncDataRead => G1_rxAsyncDataRead_S,
+		G1_rxAsyncDataOverflow => open,
+		G1_rxAsyncDataPresent => G1_rxAsyncDataPresent_S,
+		G1_status => G1_status_S,
+		G1_TX_DLM => G1_TX_DLM,
+		G1_TX_DLM_WORD => G1_TX_DLM_WORD,
+		G1_RX_DLM => G1_RX_DLM,
+		G1_RX_DLM_WORD => G1_RX_DLM_WORD,
+		G1_LOS => G1_LOS,
+		G1_txP => G1_gtpTxP,
+		G1_txN => G1_gtpTxN,
+		G1_rxP => G1_gtpRxP,
+		G1_rxN => G1_gtpRxN,
+
+		G2_txAsyncData => G2_txAsyncData_S,
+		G2_txAsyncDataWrite => G2_txAsyncDataWrite_S,
+		G2_txAsyncFifoFull => G2_txAsyncFifoFull_S,
+		G2_rxAsyncData => G2_rxAsyncData_S,
+		G2_rxAsyncDataRead => G2_rxAsyncDataRead_S,
+		G2_rxAsyncDataOverflow => open,
+		G2_rxAsyncDataPresent => G2_rxAsyncDataPresent_S,
+		G2_status => G2_status_S,
+		G2_TX_DLM => G2_TX_DLM,
+		G2_TX_DLM_WORD => G2_TX_DLM_WORD,
+		G2_RX_DLM => G2_RX_DLM,
+		G2_RX_DLM_WORD => G2_RX_DLM_WORD,
+		G2_LOS => G2_LOS,
+		G2_txP => G2_gtpTxP,
+		G2_txN => G2_gtpTxN,
+		G2_rxP => G2_gtpRxP,
+		G2_rxN => G2_gtpRxN,
+
+		G3_txAsyncData => G3_txAsyncData_S,
+		G3_txAsyncDataWrite => G3_txAsyncDataWrite_S,
+		G3_txAsyncFifoFull => G3_txAsyncFifoFull_S,
+		G3_rxAsyncData => G3_rxAsyncData_S,
+		G3_rxAsyncDataRead => G3_rxAsyncDataRead_S,
+		G3_rxAsyncDataOverflow => open,
+		G3_rxAsyncDataPresent => G3_rxAsyncDataPresent_S,
+		G3_status => G3_status_S,
+		G3_TX_DLM => G3_TX_DLM,
+		G3_TX_DLM_WORD => G3_TX_DLM_WORD,
+		G3_RX_DLM => G3_RX_DLM,
+		G3_RX_DLM_WORD => G3_RX_DLM_WORD,
+		G3_LOS => G3_LOS,
+		G3_txP => G3_gtpTxP,
+		G3_txN => G3_gtpTxN,
+		G3_rxP => G3_gtpRxP,
+		G3_rxN => G3_gtpRxN,
+
+		--Control Interface
+		SCI_DATA_IN => SCI_DATA_IN,
+		SCI_DATA_OUT => SCI_DATA_OUT,
+		SCI_ADDR => SCI_ADDR,
+		SCI_READ => SCI_READ,
+		SCI_WRITE => SCI_READ,
+		SCI_ACK => SCI_ACK,
+		SCI_NACK => SCI_NACK,
+
+		LEDs_link_ok => LEDs_link_ok,
+		LEDs_rx => LEDs_rx,
+		LEDs_tx => LEDs_tx,
+
+		testPin => testPin,
+		testword0 => testword0,
+		testword0clock => testword0clock
+		);
+
+G0_resetDone_S <= G0_status_S(0);			-- '1' => OK
+G0_txLocked_S <= G0_status_S(1);				-- '1' => OK
+G0_rxLocked_S <= G0_status_S(2);				-- '1' => OK
+G0_rxNotInTable_S <= G0_status_S(3);
+G0_resetDone <= G0_resetDone_S;
+G0_txLocked <= G0_txLocked_S;
+G0_rxLocked <= G0_rxLocked_S;
+
+G1_resetDone_S <= G1_status_S(0);			-- '1' => OK
+G1_txLocked_S <= G1_status_S(1);				-- '1' => OK
+G1_rxLocked_S <= G1_status_S(2);				-- '1' => OK
+G1_rxNotInTable_S <= G1_status_S(3);
+G1_resetDone <= G1_resetDone_S;
+G1_txLocked <= G1_txLocked_S;
+G1_rxLocked <= G1_rxLocked_S;
+
+G2_resetDone_S <= G2_status_S(0);			-- '1' => OK
+G2_txLocked_S <= G2_status_S(1);				-- '1' => OK
+G2_rxLocked_S <= G2_status_S(2);				-- '1' => OK
+G2_rxNotInTable_S <= G2_status_S(3);
+G2_resetDone <= G2_resetDone_S;
+G2_txLocked <= G2_txLocked_S;
+G2_rxLocked <= G2_rxLocked_S;
+
+G3_resetDone_S <= G3_status_S(0);			-- '1' => OK
+G3_txLocked_S <= G3_status_S(1);				-- '1' => OK
+G3_rxLocked_S <= G3_status_S(2);				-- '1' => OK
+G3_rxNotInTable_S <= G3_status_S(3);
+G3_resetDone <= G3_resetDone_S;
+G3_txLocked <= G3_txLocked_S;
+G3_rxLocked <= G3_rxLocked_S;
+
+--testword0(35 downto 0) <= testword0_S(35 downto 0);
+--testword0(35) <= testword1_S(35);
+-- testword1 <= testword1_S;
+
+end Behavioral;
diff --git a/data_concentrator/sources/DC_check_timestamp.vhd b/data_concentrator/sources/DC_check_timestamp.vhd
new file mode 100644
index 0000000..9f0226b
--- /dev/null
+++ b/data_concentrator/sources/DC_check_timestamp.vhd
@@ -0,0 +1,182 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   27-02-2014
+-- Module Name:   DC_check_timestamp
+-- Description:   Checks pulse data on consistently increased timestamp and the skipped pulses 
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- DC_check_timestamp
+-- Checks the timestamp and timestamp fraction of 36-bits data stream and counts the number of skipped pulses;
+-- The timestamps should be sorted. The errors are counted in a 32-bit register.
+-- The input pulse data consists of the following items (parallel)
+--        channel : adc-index
+--        statusbyte : 8 bit status information
+--        energy : pulse energy
+--        timefraction : fraction part of the timestamp
+--        timestamp : 32 bits timestamp, synchronised to master SODA clock
+--        superburstnumber : 31 bits superburst number
+--
+-- Library
+--     work.panda_package :  for type declarations and constants
+-- 
+-- Generics:
+-- 
+-- Inputs:
+--     clock : clock for incoming data
+--     reset : reset of all components
+--     clear : clears the error counter
+--     pulse_data : 36 bits data with Feature Extraction Results, each 4*36-bits:
+--        word0 : 0 & timestamp(31..0)
+--        word1 : 1 & 00 & superburstnumber(23..0)
+--        word2 : 2 & statusbyte & 00 & adcnumber
+--        word3 : 3 & timefraction & energy
+--     pulse_data_write : write signal for the pulse_data
+--     multiplexer_error : error in multiplexer : count as data error
+-- 
+-- Outputs:
+--     timestamp_errors : number of timestamp errors occurred
+--     skipped_pulses : number of pulses skipped in FEE
+--     dataerrors : number of errors in data plus number of errors in multiplexer
+-- 
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity DC_check_timestamp is
+	port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		clear                   : in std_logic;
+		channel                 : in std_logic_vector(15 downto 0);
+		statusbyte              : in std_logic_vector(7 downto 0);
+		energy                  : in std_logic_vector(15 downto 0);
+		timefraction            : in std_logic_vector(11 downto 0);
+		timestamp               : in std_logic_vector(15 downto 0);
+		superburstnumber        : in std_logic_vector(30 downto 0);		
+		pulse_data_write        : in std_logic;
+		multiplexer_error       : in std_logic;
+		timestamp_errors        : out std_logic_vector(9 downto 0);	
+		skipped_pulses          : out std_logic_vector(9 downto 0);
+		dataerrors              : out std_logic_vector(9 downto 0)
+		);
+end DC_check_timestamp;
+
+
+
+architecture Behavioral of DC_check_timestamp is
+
+signal clear_S                    : std_logic := '0';
+signal pulsevalue_write_S         : std_logic := '0';
+signal adcnumber_S                : std_logic_vector(15 downto 0) := (others => '0');
+signal statusbyte_S               : std_logic_vector(7 downto 0) := (others => '0');
+signal superburstnumber_prev_S    : std_logic_vector(30 downto 0) := (others => '0');
+signal timestamp_S                : std_logic_vector(15 downto 0) := (others => '0');
+signal timestamp_prev_S           : std_logic_vector(15 downto 0) := (others => '0');
+signal timefraction_S             : std_logic_vector(11 downto 0) := (others => '0');
+signal timefraction_prev_S        : std_logic_vector(11 downto 0) := (others => '0');
+
+signal timestampsmaller_S          : std_logic := '0';
+
+signal timestamp_errors_S         : std_logic_vector(9 downto 0) := (others => '0');
+signal skipped_pulses_S           : std_logic_vector(9 downto 0) := (others => '0');
+signal dataerrors_S               : std_logic_vector(9 downto 0) := (others => '0');
+
+signal multiplexer_error_S        : std_logic := '0';
+signal prev_multiplexer_error_S   : std_logic := '0';
+
+
+begin
+
+timestamp_errors <= timestamp_errors_S;
+skipped_pulses <= skipped_pulses_S;
+dataerrors <= dataerrors_S;
+
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if (reset = '1') then
+			clear_S <= '1';
+			pulsevalue_write_S <= '0';
+		else
+			clear_S <= clear;
+			if (pulse_data_write='1') then
+				timestamp_S <= timestamp;
+				adcnumber_S <= channel;
+				statusbyte_S <= statusbyte;
+				timefraction_S <= timefraction;
+				pulsevalue_write_S <= '1';
+			else
+				pulsevalue_write_S <= '0';
+			end if;
+		end if;
+	end if;
+end process;
+
+timestampsmaller_S <= '1' when 
+		(superburstnumber_prev_S>superburstnumber) or
+		((superburstnumber_prev_S=superburstnumber) and (timestamp_prev_S>timestamp_S)) -- or
+--		((superburstnumber_prev_S=superburstnumber) and (timestamp_prev_S=timestamp_S) and (timefraction_prev_S>timefraction_S))
+	else '0';
+
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if (clear_S='1') or (clear='1') then
+			timestamp_errors_S <= (others => '0');
+		elsif (pulsevalue_write_S = '1') then
+			if timestampsmaller_S='1' then 
+				if timestamp_errors_S/="1111111111" then
+					timestamp_errors_S <= timestamp_errors_S+1;
+				end if;
+			end if;
+		end if;
+		superburstnumber_prev_S <= superburstnumber;
+		timestamp_prev_S <= timestamp_S;
+		timefraction_prev_S <= timefraction_S;
+	end if;
+end process;
+
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if clear_S='1' then
+			skipped_pulses_S <= (others => '0');
+		elsif (pulsevalue_write_S = '1') then
+			if statusbyte_S(7)='1' then 
+				if skipped_pulses_S/="1111111111" then
+					skipped_pulses_S <= skipped_pulses_S+1;
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if clear_S='1' then
+			dataerrors_S <= (others => '0');
+		elsif (multiplexer_error_S = '1') then
+			if dataerrors_S/="1111111111" then
+				dataerrors_S <= dataerrors_S+1;
+			end if;
+		end if;
+		if (multiplexer_error='1') and (prev_multiplexer_error_S='0') then
+			multiplexer_error_S <= '1';
+		else
+			multiplexer_error_S <= '0';
+		end if;
+		prev_multiplexer_error_S <= multiplexer_error;
+	end if;
+end process;
+
+
+end Behavioral;
diff --git a/data_concentrator/sources/DC_checkwave.vhd b/data_concentrator/sources/DC_checkwave.vhd
new file mode 100644
index 0000000..a818875
--- /dev/null
+++ b/data_concentrator/sources/DC_checkwave.vhd
@@ -0,0 +1,145 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   16-06-2012
+-- Module Name:   DC_checkwave
+-- Description:   Checks waveform data
+-- Modifications:
+--    16-09-2014: name changed from MUX_checkwave to DC_checkwave
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+USE work.panda_package.all;
+
+------------------------	----------------------------------------------------------
+-- DC_checkwave
+-- Checks waveform data
+--
+-- Input data:
+--        	bits(35..32)="0000" : bits(31..0)=timestamp of maximum value in waveform
+--        	bits(35..32)="0001" : bits(31..24)=00 bits(23..0)=SuperBurst number
+--        	bits(35..32)="0010" : 
+--              bits(31..24) = statusbyte (bit6=overflow) 
+--              bits(23..16) = 00
+--              bits(15..0) = adcnumber (channel identification)
+--        	bits(35..32)="0011" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+--        	bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+--        	bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+--        	bits(35..32)="1111" : error: buffer full, waveform not valid
+--
+-- 
+--
+--
+--
+-- Library:
+--     work.panda_package: types and constants
+--
+-- Generics:
+--
+-- Inputs:
+--     clock : clock for input and output data
+--     reset : reset
+--     wave_in : waveform input data, 36-bits stream
+--        	bits(35..32)="0000" : bits(31..0)=timestamp of maximum value in waveform
+--        	bits(35..32)="0001" : bits(31..24)=00 bits(23..0)=SuperBurst number
+--        	bits(35..32)="0010" : 
+--              bits(31..24) = statusbyte (bit6=overflow) 
+--              bits(23..16) = 00
+--              bits(15..0) = adcnumber (channel identification)
+--        	bits(35..32)="0011" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+--        	bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+--        	bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+--        	bits(35..32)="1111" : error: buffer full, waveform not valid
+--     wave_in_write : waveform data is availabe
+-- 
+-- Outputs:
+--     error : error
+-- 
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity DC_checkwave is
+    Port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		wave_in                 : in std_logic_vector(35 downto 0);
+		wave_in_write           : in std_logic;
+		error                   : out std_logic
+	);    
+end DC_checkwave;
+
+
+architecture Behavioral of DC_checkwave is
+
+signal wave_prev_S                : std_logic_vector(3 downto 0) := "0100";
+signal error_S                    : std_logic := '0';
+
+begin
+
+error <= error_S;
+
+
+writeprocess: process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if (reset = '1') then 
+			wave_prev_S <= "0100";
+			error_S <= '0';
+		else
+			if wave_in_write='1' then
+				case wave_prev_S is
+					when "0000"  =>
+						if wave_in(35 downto 32)="0001" then
+							error_S <= '0';
+						else
+							error_S <= '1';
+						end if;
+					when "0001" => 
+						if wave_in(35 downto 32)="0010" then
+							error_S <= '0';
+						else
+							error_S <= '1';
+						end if;
+					when "0010" => 
+						if wave_in(35 downto 32)="0011" then
+							error_S <= '0';
+						else
+							error_S <= '1';
+						end if;
+					when "0011" => 
+						if (wave_in(35 downto 32)="0011") or (wave_in(35 downto 32)="0101") or (wave_in(35 downto 32)="0100") then
+							error_S <= '0';
+						else
+							error_S <= '1';
+						end if;
+					when "0100" => 
+						if (wave_in(35 downto 32)="0000") then
+							error_S <= '0';
+						else
+							error_S <= '1';
+						end if;
+					when "0101" => 
+						if (wave_in(35 downto 32)="0000") then
+							error_S <= '0';
+						else
+							error_S <= '1';
+						end if;
+					when others => 
+						error_S <= '1';
+				end case;
+				wave_prev_S <= wave_in(35 downto 32);
+			end if;
+		end if;
+	end if;
+end process;
+
+
+
+
+
+end Behavioral;
+
diff --git a/data_concentrator/sources/DC_combine_pulses.vhd b/data_concentrator/sources/DC_combine_pulses.vhd
new file mode 100644
index 0000000..2f023c7
--- /dev/null
+++ b/data_concentrator/sources/DC_combine_pulses.vhd
@@ -0,0 +1,418 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   14-07-2014
+-- Module Name:   DC_combine_pulses
+-- Description:   Combine pulses (=hits) from corresponding ADC channels
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+
+------------------------------------------------------------------------------------------------------
+-- DC_combine_pulses
+--     Combine Feature Extraction data from corresponding ADC channels.
+--
+--     Each ADC has a corresponding channel: the one with the same index connected to the neighbour fiber.
+--     The fiber nummer comes as separated input, the ADC index is determined by the lower few bits of the channel number.
+--     If the ADCs are organised as high/low gain pairs then the last bit indicates low or high gain and in that case
+--     both ADC channels are combined with the corresponding ADC low/high gain pair (see generic ADCINDEXSHIFT)
+--
+--     The input and output consist of the members that describe a hit : time&energy (plus status and superburst)
+--     The sequence of the pulses is not changed, but the resulting combined hit will be placed on the first of the two hits
+--
+--     The conditions for combining: 
+--     1) Hits are combined if time difference is below a fixed time (generic COMBINETIMEDIFFERENCE), within one superburst
+--     2) The combined hit is placed at the position of the first hit. The timestamp is an average of both hits.
+--     3) Hits are combined if their energy difference is within 25%: the check is ((a>b*0.75)&&(b>a*0.75))
+--     4) If the energy difference is larger then 25% then only the smallest will be kept.
+--     5) High and low gain channels can be combined. The correction gain must be calibrated beforehand.
+--
+--     With input combine_pulse it is possible to select which ADCs should be combined (calibration run)
+--     Bit 7 of the statusbyte indicates that 2 channels where combined.
+--     Bit 6 of the statusbyte indicates that the corresponding channel was discarded
+--
+--     Description of the algortithm:
+--     Data is written in a fifo, and at the same time written in a block of memory that contains the latest data for each ADC index.
+--     Before the data is written in the fifo it is compared with the latest data from the corresponding ADC.
+--     If the time difference is small then the combined data or the new data (depending of the energy comparison)
+--     will be written at the position of the corresponding data (that was written earlier in the fifo).
+--     The block memory also contains the address in the fifo.
+--     The data is read out of the fifo. This is done after some delay and some check on the amount of data in the fiber,
+--     to prevent that data combining takes place after the data is already read from the fifo.
+--     
+--
+-- Library
+--     work.panda_package :  for type declarations and constants
+--
+-- generics
+--     NROFFIBERS : number of fiber connection of the MUX board
+--     NROFADCS : number of ADCs in each FEE
+--     ADCINDEXSHIFT : ADC channel numbers lowest bit indicates the high or low gain ADC, 0=high, 1=low
+--     COMBINEPULSESMEMSIZE : addressbits for the fifo buffer for combining hits
+--     COMBINETIMEDIFFERENCE : largest time difference between hits to be combined, number of timefraction units
+--     CF_FRACTIONBIT : number of valid constant fraction bits
+--		
+-- inputs
+--     clock : clock
+--     reset : synchronous reset
+--     combine_pulse : enable combining if corresponding bit is set, only even fibernumbers; low or high gain bits are removed
+--     fiber_index_in : index of the fiber
+--     channel_in : data input : adc channel
+--     statusbyte_in : data input : status
+--     energy_in : data input : pulse energy
+--     timefraction_in : data input : Constant Fraction time
+--     timestamp_in : data input : time within superburst
+--     superburstnumber_in : data input : superburst number
+--     data_in_available : hit data is available
+--     data_out_read : read signal to read from fifo output
+--		
+-- outputs
+--     data_in_read : read signal for reading data at the input (from connected fifo)
+--     channel_out : data output : adc channel
+--     statusbyte_out : data output : status
+--     energy_out : data output : pulse energy
+--     timefraction_out : data output : Constant Fraction time
+--     timestamp_out : data output : time within superburst
+--     superburstnumber_out : data output : superburst number
+--     data_out_available : hit data is available at the output of the fifo
+--
+-- components
+--     blockmem : memory for the fifo and for saving the latest hit data
+--
+--
+------------------------------------------------------------------------------------------------------
+
+entity DC_combine_pulses is
+	generic (
+		NROFFIBERS              : natural := 4;
+		NROFADCS                : natural := 32;
+		ADCINDEXSHIFT           : natural := 1;
+		COMBINEPULSESMEMSIZE    : natural := 10;
+		COMBINETIMEDIFFERENCE   : natural := 5000;
+		CF_FRACTIONBIT          : natural := 11
+		);
+	port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		combine_pulse           : in std_logic_vector((NROFFIBERS*NROFADCS)/(2*(ADCINDEXSHIFT+1))-1 downto 0);
+		fiber_index_in          : in std_logic_vector(3 downto 0);
+		channel_in              : in std_logic_vector(15 downto 0);
+		statusbyte_in           : in std_logic_vector(7 downto 0);
+		energy_in               : in std_logic_vector(15 downto 0);
+		timefraction_in         : in std_logic_vector(11 downto 0);
+		timestamp_in            : in std_logic_vector(15 downto 0);
+		superburstnumber_in     : in std_logic_vector(30 downto 0);
+		data_in_read            : out std_logic;
+		data_in_available       : in std_logic;
+
+		channel_out             : out std_logic_vector(15 downto 0);
+		statusbyte_out          : out std_logic_vector(7 downto 0);
+		energy_out              : out std_logic_vector(15 downto 0);
+		timefraction_out        : out std_logic_vector(11 downto 0);
+		timestamp_out           : out std_logic_vector(15 downto 0);
+		superburstnumber_out    : out std_logic_vector(30 downto 0);
+		data_out_read           : in std_logic;
+		data_out_available      : out std_logic
+	);
+end DC_combine_pulses;
+
+architecture behavioral of DC_combine_pulses is
+
+component blockmem is
+	generic (
+		ADDRESS_BITS : natural := 8;
+		DATA_BITS  : natural := 18
+		);
+	port (
+		clock                   : in  std_logic; 
+		write_enable            : in std_logic;
+		write_address           : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_in                 : in std_logic_vector(DATA_BITS-1 downto 0);
+		read_address            : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_out                : out std_logic_vector(DATA_BITS-1 downto 0)
+	);
+end component;
+
+constant COMBINETIMEDIFF         : std_logic_vector(CF_FRACTIONBIT+15 downto 0) := conv_std_logic_vector(COMBINETIMEDIFFERENCE,CF_FRACTIONBIT+16);
+constant CHECK_FRACTIONTIME      : boolean := TRUE;
+constant ZEROS                   : std_logic_vector (311 downto 0) := (others => '0');
+
+type combine_type is (store,combine,overwrite,preserve);
+signal combine_S                 : combine_type := store;
+
+signal combine_pulse_S           : std_logic_vector((NROFFIBERS*NROFADCS)/(2*(ADCINDEXSHIFT+1))-1 downto 0);
+-- register with newly arrived data
+signal fiber_index1_S            : std_logic_vector(twologarray(NROFFIBERS)-1 downto 0);
+signal channel1_S                : std_logic_vector(15 downto 0);
+signal statusbyte1_S             : std_logic_vector(7 downto 0);
+signal energy1_S                 : std_logic_vector(15 downto 0);
+signal timefraction1_S           : std_logic_vector(11 downto 0) := (others => '0');
+signal timestamp1_S              : std_logic_vector(15 downto 0);
+signal superburstnumber1_S       : std_logic_vector(30 downto 0);
+
+-- latest data in memory from the selected ADC:
+signal fiber_indexL_S            : std_logic_vector(twologarray(NROFFIBERS)-1 downto 0);
+signal channelL_S                : std_logic_vector(15 downto 0);
+signal statusbyteL_S             : std_logic_vector(7 downto 0);
+signal energyL_S                 : std_logic_vector(15 downto 0);
+signal timefractionL_S           : std_logic_vector(11 downto 0) := (others => '0');
+signal timestampL_S              : std_logic_vector(15 downto 0);
+signal superburstnumberL_S       : std_logic_vector(30 downto 0);
+
+-- combined data: newly arrived data and data from memory
+signal fiber_indexC_S            : std_logic_vector(twologarray(NROFFIBERS)-1 downto 0);
+signal channelC_S                : std_logic_vector(15 downto 0);
+signal statusbyteC_S             : std_logic_vector(7 downto 0);
+signal energyC_S                 : std_logic_vector(15 downto 0);
+signal timefractionC_S           : std_logic_vector(11 downto 0) := (others => '0');
+signal timestampC_S              : std_logic_vector(15 downto 0);
+signal superburstnumberC_S       : std_logic_vector(30 downto 0);
+signal energyCbf_S               : std_logic_vector(16 downto 0);
+signal energy_diff_small_s       : std_logic;
+signal data_validl_s             : std_logic;
+		
+signal hires_time1_s             : std_logic_vector(CF_FRACTIONBIT+15 downto 0) := (others => '0');
+signal hires_timeL_s             : std_logic_vector(CF_FRACTIONBIT+15 downto 0) := (others => '0');
+signal hires_diff_s              : std_logic_vector(CF_FRACTIONBIT+15 downto 0) := (others => '0');
+signal time_diff_small_S         : std_logic := '0';
+
+signal hires_diff_pos_S          : std_logic_vector(CF_FRACTIONBIT+15 downto 0) := (others => '0');
+signal hires_diff_div2_S         : std_logic_vector(CF_FRACTIONBIT+15 downto 0) := (others => '0');
+signal hires_meantime_S          : std_logic_vector(CF_FRACTIONBIT+15 downto 0) := (others => '0');
+
+signal index_S                   : std_logic_vector(twologarray(NROFFIBERS/2)+twologarray(NROFADCS/(ADCINDEXSHIFT+1))-1 downto 0);
+signal indexI_S                  : integer range 0 to (NROFFIBERS*NROFADCS)/(2*(ADCINDEXSHIFT+1))-1;
+signal data_in_read_S            : std_logic := '0';
+signal data_in_read1_S           : std_logic := '0';
+signal data_in_read2_S           : std_logic := '0';
+
+
+signal data_out_available_S      : std_logic;
+signal fifo_write_S              : std_logic;
+signal fifo_write_address_S      : std_logic_vector(COMBINEPULSESMEMSIZE-1 downto 0) := (others => '0');
+signal fifo_data_in_S            : std_logic_vector(99 downto 0) := (others => '0');
+signal fifo_read_address_S       : std_logic_vector(COMBINEPULSESMEMSIZE-1 downto 0) := (others => '1');
+signal fifo_read_address0_S      : std_logic_vector(COMBINEPULSESMEMSIZE-1 downto 0) := (others => '1');
+signal fifo_nextwriteaddress_S   : std_logic_vector(COMBINEPULSESMEMSIZE-1 downto 0) := (others => '0');
+signal fifo_read_addressplus1_S  : std_logic_vector(COMBINEPULSESMEMSIZE-1 downto 0) := (others => '1');
+signal fifo_nextwriteaddressplus1_S : std_logic_vector(COMBINEPULSESMEMSIZE-1 downto 0) := (others => '1');
+signal fifo_nextwriteaddressplus2_S : std_logic_vector(COMBINEPULSESMEMSIZE-1 downto 0) := (others => '1');
+signal fifo_out_valid_S          : std_logic;
+signal fifo_almost_full_S        : std_logic;
+signal fifoaddressl_s            : std_logic_vector(COMBINEPULSESMEMSIZE-1 downto 0) := (others => '0');
+
+signal last_write_S              : std_logic;
+signal last_write_address_S      : std_logic_vector(twologarray(NROFFIBERS)+twologarray(NROFADCS)-ADCINDEXSHIFT-1 downto 0);
+signal last_data_in_S            : std_logic_vector(100+twologarray(NROFFIBERS)+COMBINEPULSESMEMSIZE-1 downto 0);
+signal last_read_address_S       : std_logic_vector(twologarray(NROFFIBERS)+twologarray(NROFADCS)-ADCINDEXSHIFT-1 downto 0);
+
+signal timeafterlastwrite_S      : integer range 0 to 2*NROFFIBERS*NROFADCS := 0;
+signal wordsinbuffer0_S          : std_logic_vector(COMBINEPULSESMEMSIZE-1 downto 0) := (others => '0');
+signal wordsinbuffer_S           : integer range 0 to 2*COMBINEPULSESMEMSIZE-1 := 0;
+
+
+begin
+
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		combine_pulse_S <= combine_pulse;
+	end if;
+end process;
+
+fifoblockmem: blockmem 
+	generic map(
+		ADDRESS_BITS => COMBINEPULSESMEMSIZE,
+		DATA_BITS  => 100
+	)
+	port map(
+		clock => clock,
+		write_enable => fifo_write_S,
+		write_address => fifo_write_address_S,
+		data_in => fifo_data_in_S,
+		read_address => fifo_read_address0_S,
+		data_out(15 downto 0) => channel_out,
+		data_out(23 downto 16) => statusbyte_out,
+		data_out(39 downto 24) => energy_out,
+		data_out(51 downto 40) => timefraction_out,
+		data_out(67 downto 52) => timestamp_out,
+		data_out(98 downto 68) => superburstnumber_out,
+		data_out(99) => fifo_out_valid_S
+		);
+		
+lastblockmem: blockmem
+	generic map(
+		ADDRESS_BITS => twologarray(NROFFIBERS)+twologarray(NROFADCS)-ADCINDEXSHIFT,
+		DATA_BITS  => 100+twologarray(NROFFIBERS)+COMBINEPULSESMEMSIZE
+	)
+	port map(
+		clock => clock,
+		write_enable => last_write_S,
+		write_address => last_write_address_S,
+		data_in => last_data_in_S,
+		read_address => last_read_address_S,
+		data_out(15 downto 0) => channelL_S,
+		data_out(23 downto 16) => statusbyteL_S,
+		data_out(39 downto 24) => energyL_S,
+		data_out(51 downto 40) => timefractionL_S,
+		data_out(67 downto 52) => timestampL_S,
+		data_out(98 downto 68) => superburstnumberL_S,
+		data_out(99) => data_validL_S,
+		data_out(twologarray(NROFFIBERS)+99 downto 100) => fiber_indexL_S,
+		data_out(twologarray(NROFFIBERS)+COMBINEPULSESMEMSIZE+99 downto twologarray(NROFFIBERS)+100) => fifoaddressL_S
+		);
+last_read_address_S <= fiber_index_in(twologarray(NROFFIBERS)-1 downto 1) & (not fiber_index_in(0)) & (channel_in(twologarray(NROFADCS)-1 downto ADCINDEXSHIFT));
+		
+-- calculate if timedifference between pulses is small: ---------------------------------
+hires_time1_S <= timestamp1_S & timefraction1_S(CF_FRACTIONBIT-1 downto 0);
+hires_timeL_S <= timestampL_S & timefractionL_S(CF_FRACTIONBIT-1 downto 0);
+hires_diff_S <= hires_timeL_S-hires_time1_S;
+time_diff_small_S <= '1' when 
+		(superburstnumber1_S=superburstnumberL_S) and
+		(((hires_diff_S(CF_FRACTIONBIT+15)='0') and (hires_diff_S<COMBINETIMEDIFF)) or -- L newer than 1
+		((hires_diff_S(CF_FRACTIONBIT+15)='1') and ((not hires_diff_S)<(COMBINETIMEDIFF-1)))) -- 1 newer than L
+	else '0';
+hires_diff_pos_S <= 
+		hires_timeL_S-hires_time1_S when (hires_diff_S(CF_FRACTIONBIT+15)='0') else -- L newer than 1
+		hires_time1_S-hires_timeL_S;
+hires_diff_div2_S <= '0' & hires_diff_pos_S(CF_FRACTIONBIT+15 downto 1);	
+hires_meantime_S <= 
+	hires_time1_S + hires_diff_div2_S when (hires_diff_S(CF_FRACTIONBIT+15)='0') else -- L newer than 1
+	hires_timeL_S + hires_diff_div2_S; -- L newer than 1
+
+-- energy difference is small when a>b(1-b/4) and b>a(1-1/4)
+energy_diff_small_S <= '1' when
+	(energyL_S >= energy1_S-("00" & energy1_S(15 downto 2))) and 
+	(energy1_S >= energyL_S-("00" & energyL_S(15 downto 2)))
+	else '0';
+	
+-- Combined hit: time and energy averaged ----------------------------------------------------
+fiber_indexC_S <= fiber_indexL_S;
+channelC_S <= channelL_S;
+statusbyteC_S <= (statusbyte1_S or statusbyteL_S) or STATBYTE_DCCOMBINEDHITS;
+energyCbf_S <= ('0' & energy1_S) + ('0' & energyL_S);
+energyC_S <= energyCbf_S(16 downto 1);
+timefractionC_S(CF_FRACTIONBIT-1 downto 0) <= hires_meantime_S(CF_FRACTIONBIT-1 downto 0);
+timestampC_S <= hires_meantime_S(CF_FRACTIONBIT+15 downto CF_FRACTIONBIT);
+superburstnumberC_S <= superburstnumber1_S;
+ 
+-- channel0=high gain, channel1=low gain
+-- how to combine:
+--   store=save new hit if time difference is large or combining is disabled
+--   combine=save mean value of two hits in old fifo memory 
+--   overwrite=save new hit at position of the corresponding channel
+--   preserve=preserve the hit of the corresponding channel and discard new value
+index_S <= fiber_indexL_S(twologarray(NROFFIBERS)-1 downto 1) & channelL_S(twologarray(NROFADCS)-1 downto ADCINDEXSHIFT);
+indexI_S <= conv_integer(index_S);
+combine_S <= 
+	store when (combine_pulse_S(indexI_S)='0') else
+	store when (data_validL_S='0') else
+	combine when ((time_diff_small_S='1') and (energy_diff_small_S='1')) else
+	overwrite when ((time_diff_small_S='1') and (energy_diff_small_S='0') and (energy1_S<energyL_S)) else
+	preserve when ((time_diff_small_S='1') and (energy_diff_small_S='0') and (energy1_S>energyL_S)) 
+	else store;
+
+-- write data in memory block for latest data, organised for each ADC ------------------------
+last_write_S <= '1' when data_in_read2_S='1' else '0';
+last_write_address_S <=
+	fiber_index1_S(twologarray(NROFFIBERS)-1 downto 0) & (channel1_S(twologarray(NROFADCS)-1 downto ADCINDEXSHIFT))
+		when (combine_S=store) else
+	fiber_index1_S(twologarray(NROFFIBERS)-1 downto 1) & (not fiber_index1_S(0)) & (channel1_S(twologarray(NROFADCS)-1 downto ADCINDEXSHIFT));
+last_data_in_S <= -- save new hit in case of store, otherwise set corresponding data to invalid
+	fifo_nextwriteaddress_S & fiber_index1_S & '1' & superburstnumber1_S & timestamp1_S & timefraction1_S & energy1_S & statusbyte1_S & channel1_S
+		when (combine_S=store) else
+	fifo_nextwriteaddress_S & fiber_index1_S & '0' & superburstnumber1_S & timestamp1_S & timefraction1_S & energy1_S & statusbyte1_S & channel1_S;
+--maybe: additional write on next clock to make corresponding data invalid ?
+
+-- write data in fifo (sequential) ------------------------------------------------------------
+fifo_write_S <= '1' when data_in_read2_S='1' else '0';
+fifo_write_address_S <=
+	fifo_nextwriteaddress_S when combine_S=store else fifoaddressL_S;
+fifo_data_in_S <=
+	'1' & superburstnumber1_S & timestamp1_S & timefraction1_S & energy1_S & statusbyte1_S & channel1_S
+		when (combine_S=store) else
+	'1' & superburstnumber1_S & timestamp1_S & timefraction1_S & energy1_S & (statusbyte1_S or STATBYTE_DCCOMBINEDDISCARDED) & channel1_S
+		when (combine_S=overwrite) else
+	'1' & superburstnumberC_S & timestampC_S & timefractionC_S & energyC_S & statusbyteC_S & channelC_S
+		when (combine_S=combine) else
+	'1' & superburstnumberL_S & timestampL_S & timefractionL_S & energyL_S & (statusbyteL_S or STATBYTE_DCCOMBINEDDISCARDED) & channelL_S
+		when (combine_S=preserve);
+	
+-- read data from moduel input -------------------------------------------------------------------
+data_in_read <= data_in_read_S;
+data_in_read_S <= '1' when (data_in_available='1') and (data_in_read1_S='0') and (fifo_almost_full_S='0') else '0';
+
+read_data_process: process (clock)
+begin
+	if (rising_edge(clock)) then 
+		if reset='1' then
+			data_in_read1_S <= '0';
+			data_in_read2_S <= '0';
+			fifo_nextwriteaddress_S <= (others => '0');
+		else
+			if data_in_read1_S='1' then
+				fiber_index1_S <= fiber_index_in(twologarray(NROFFIBERS)-1 downto 0);
+				channel1_S <= channel_in;
+				statusbyte1_S <= statusbyte_in;
+				energy1_S <= energy_in;
+				timefraction1_S <= timefraction_in;
+				timestamp1_S <= timestamp_in;
+				superburstnumber1_S <= superburstnumber_in;			
+			end if;
+			data_in_read1_S <= data_in_read_S;
+			data_in_read2_S <= data_in_read1_S;
+			if (data_in_read2_S='1') and (combine_S=store) then
+				fifo_nextwriteaddress_S <= fifo_nextwriteaddress_S+1;
+			end if;
+		end if;
+	end if;
+end process;
+
+-- read from fifo -----------------------------------------------------
+fifo_read_address0_S <= fifo_read_addressplus1_S when data_out_read='1' else fifo_read_address_S;
+
+fifo_read_addressplus1_S <= fifo_read_address_S+1;
+fifo_nextwriteaddressplus1_S <= fifo_nextwriteaddress_S+1;
+fifo_nextwriteaddressplus2_S <= fifo_nextwriteaddressplus1_S+1;
+data_out_available <= data_out_available_S;
+data_out_available_S <= '1' 
+		when (wordsinbuffer_S>NROFFIBERS*NROFADCS) or 
+			((timeafterlastwrite_S=2*NROFFIBERS*NROFADCS) and (fifo_read_addressplus1_S/=fifo_nextwriteaddress_S)) 
+	else '0';
+
+process (clock)
+begin
+	if (rising_edge(clock)) then 
+		if reset='1' then
+			fifo_read_address_S <= (others => '1');
+			timeafterlastwrite_S <= 0;
+		else
+			if data_out_read='1' then
+				fifo_read_address_S <= fifo_read_address_S+1;
+			end if;
+			if (fifo_read_address_S=fifo_nextwriteaddress_S) or (fifo_read_address_S=fifo_nextwriteaddressplus1_S) or (fifo_read_address_S=fifo_nextwriteaddressplus2_S) then
+				fifo_almost_full_S <= '1';
+			else
+				fifo_almost_full_S <= '0';
+			end if;
+			
+			if fifo_write_S='1' then
+				timeafterlastwrite_S <= 0;
+			else
+				if timeafterlastwrite_S/=2*NROFFIBERS*NROFADCS then
+					timeafterlastwrite_S <= timeafterlastwrite_S+1;
+				end if;
+			end if;
+			wordsinbuffer0_S <= fifo_nextwriteaddress_S-fifo_read_addressplus1_S;
+			wordsinbuffer_S <= conv_integer(wordsinbuffer0_S);
+		end if;
+	end if;
+end process;
+
+
+
+end architecture behavioral;
diff --git a/data_concentrator/sources/DC_data_wave_to_64bit.vhd b/data_concentrator/sources/DC_data_wave_to_64bit.vhd
new file mode 100644
index 0000000..3c01ffa
--- /dev/null
+++ b/data_concentrator/sources/DC_data_wave_to_64bit.vhd
@@ -0,0 +1,616 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   27-02-2014
+-- Module Name:   DC_data_wave_to_64bit
+-- Description:   Transfer pulse-data and waveforms as packets with 64-bits width
+-- Modifications:
+--   17-07-2014   buffer_almost_full_S in clocked process
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+
+----------------------------------------------------------------------------------
+-- DC_data_wave_to_64bit
+-- Transfer pulse-data and waveforms as packets with 64-bits width
+--
+-- The input pulse data consists of the following items (parallel)
+--        channel : adc-index
+--        statusbyte : 8 bit status information
+--        energy : pulse energy
+--        timefraction : fraction part of the timestamp
+--        timestamp : 16 bits timestamp, synchronised to master SODA clock
+--        superburstnumber : 31 bits superburst number
+--
+-- All the pulse data from one superburst is put in one data-packet.
+-- The first word-64 contains the superburst number and the timestamp of the first pulse.
+-- The superburst are sequential. If there is no data in a superburst then the packet 
+-- contains only the superburst and zero for the timestamp.
+-- For each pulse a 64-bits word is written with measured data.
+-- The time offset in respect to the first pulse is part of this 64-bits word
+--
+-- The input waveform consist of 36-bit data:
+--        bits(35..32)="0000" : 0000 & bits(15..0)=timestamp of maximum value in waveform
+--        bits(35..32)="0001" : bits(314)=0 bits(30..0)=SuperBurst number
+--        bits(35..32)="0010" : 
+--        bits(31..24) = statusbyte (bit6=overflow) 
+--        bits(23..16) = 00
+--        bits(15..0) = adcnumber (channel identification)
+--        bits(35..32)="0011" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+--        bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+--        bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+--        bits(35..32)="1111" : error: buffer full, waveform not valid
+--
+-- The 64 bits output packets, according to 32bits SODAnet specs:
+-- 32bits word1:   
+--        bit31      = last-packet flag
+--        bit30..16  = packet number
+--        bit15..0   = data size in bytes
+-- 32bits word2:   
+--        bit31..0   = Not used (same as HADES)
+-- 32bits word3:   
+--        bit31..16  = Status
+--           bit16=internal data-error
+--           bit17=internal error
+--           bit18=error in pulse-data/superburst number
+--           bit31=  0:pulse data packet, 1:waveform packet
+--        bit15..0   = System ID
+-- 32bits word4:   
+--        bit31      = 0
+--        bit30..0   = Super-burst number
+-- 32bits word5 ...  = data
+--
+--    for pulse data
+-- 32bits word7,9,11.. ,odd, for each pulse:   
+--        bit31..19  = offset in respect to superburst
+--        bit18..8   = Time fraction (11 bits used)
+--        bit7..0    = status byte
+-- 32bits word8,10,12.. ,even, for each pulse:   
+--        bit31..16  = adc channel
+--        bit15..0   = Energy (pulse height)
+--
+--    for wave data
+-- 32bits word5:
+--        bit31..24  = status byte
+--        bit23..8   = adc channel
+--        bit7..0    = number of samples in wave
+-- 32bits word6:
+--        bit15..0  = timestamp in respect to superburst of sample on the top of the waveform
+-- 32bits word7..lastsample : next_adcsample(15:0) next_adcsample(15:0) ....
+-- 
+--
+--
+-- Library:
+--
+-- Generics:
+--     TRANSITIONBUFFERBITS : number of bits for the buffer that stores data from the next superburst
+--     PANDAPACKETBUFFERBITS : number of bits for the buffer to store packet for size calculation
+--     CF_FRACTIONBIT : number of valid constant fraction bits
+--     SYSTEM_ID : ID number of this Data Concentrator
+--
+-- Inputs:
+--     clock : clock for 36-bits input data 
+--     reset : reset
+--     latestsuperburstnumber : latest superburst number that has been issued by SODA
+--     channel : pulse-data : adc channel number
+--     statusbyte : pulse-data : status
+--     energy : pulse-data : energy
+--     timefraction : pulse-data : Constant Fraction time
+--     timestamp : pulse-data : time (ADC-clock)
+--     superburstnumber : pulse-data : superburstnumber
+--     data_in_available : input data available (NOT fifo-empty from connected fifo)
+--     wave_in : input data :
+--        bits(35..32)="0000" : 0000 & bits(15..0)=timestamp of maximum value in waveform
+--        bits(35..32)="0001" : bits(31)=0 bits(30..0)=SuperBurst number
+--        bits(35..32)="0010" : 
+--        bits(31..24) = statusbyte (bit6=overflow) 
+--        bits(23..16) = 00
+--        bits(15..0) = adcnumber (channel identification)
+--        bits(35..32)="0011" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+--        bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+--        bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+--        bits(35..32)="1111" : error: buffer full, waveform not valid
+--     wave_in_available : input data available (NOT fifo-empty from connected fifo)
+--     data_out_allowed : allowed to write 64-bits output data (normally:: fifo not empty)
+-- 
+-- Outputs:
+--     data_in_read : read signal for pulse data
+--     wave_in_read : read signal for waveform data
+--     data_out : 64 bits data output
+--     data_out_write : write signal for 64 bits output data
+--     data_out_first : indicates first 64-bits data in packet
+--     data_out_last : indicates last 64-bits data in packet
+--     error : error in data
+-- 
+-- Components:
+--     DC_superburst2packet64 : Put Pulse data from one superburst into packets with 64-bits width data
+--     DC_wave2packet64 : Put waveform data into packets with 64-bits width data
+--     blockmem : memory for saving packets temporarily to calculate the packetsize and add a header
+--
+----------------------------------------------------------------------------------
+
+entity DC_data_wave_to_64bit is
+	generic (
+		TRANSITIONBUFFERBITS    : natural := 7;
+		PANDAPACKETBUFFERBITS   : natural := 13;
+		CF_FRACTIONBIT          : natural := 11;
+		SYSTEM_ID : std_logic_vector(15 downto 0) := x"5555"
+	);
+    Port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		latestsuperburstnumber  : in std_logic_vector(30 downto 0);
+		channel                 : in std_logic_vector(15 downto 0);
+		statusbyte              : in std_logic_vector(7 downto 0);
+		energy                  : in std_logic_vector(15 downto 0);
+		timefraction            : in std_logic_vector(11 downto 0);
+		timestamp               : in std_logic_vector(15 downto 0);
+		superburstnumber        : in std_logic_vector(30 downto 0);		
+		data_in_available       : in std_logic;
+		data_in_read            : out std_logic;
+		wave_in                 : in std_logic_vector(35 downto 0);
+		wave_in_available       : in std_logic;
+		wave_in_read            : out std_logic;
+		data_out_allowed        : in std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_write          : out std_logic;
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		error                   : out std_logic;
+		testword0               : out std_logic_vector(35 downto 0);
+		testword1               : out std_logic_vector(35 downto 0)
+		);
+end DC_data_wave_to_64bit;
+
+architecture Behavioral of DC_data_wave_to_64bit is
+
+component DC_superburst2packet64 is
+	generic (
+		TRANSITIONBUFFERBITS : natural := TRANSITIONBUFFERBITS;
+		CF_FRACTIONBIT       : natural := CF_FRACTIONBIT
+	);
+    Port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		channel                 : in std_logic_vector(15 downto 0);
+		statusbyte              : in std_logic_vector(7 downto 0);
+		energy                  : in std_logic_vector(15 downto 0);
+		timefraction            : in std_logic_vector(11 downto 0);
+		timestamp               : in std_logic_vector(15 downto 0);
+		superburstnumber        : in std_logic_vector(30 downto 0);
+		data_in_read            : out std_logic;
+		data_in_available       : in std_logic;
+		latestsuperburstnumber  : in std_logic_vector(30 downto 0);
+		data64_out              : out std_logic_vector(63 downto 0);
+		data64_out_write        : out std_logic;
+		data64_out_first        : out std_logic;
+		data64_out_last         : out std_logic;
+		data64_out_allowed      : in std_logic;
+		error                   : out std_logic;
+		testword0               : out std_logic_vector(35 downto 0)
+	);    
+end component;
+
+component DC_wave2packet64 is
+	generic (
+		BUFFER_BITS : natural := 9
+	);
+    Port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		wave_in                 : in std_logic_vector(35 downto 0);
+		wave_in_read            : out std_logic;
+		wave_in_available       : in std_logic;
+		wave64_out              : out std_logic_vector(63 downto 0);
+		wave64_out_write        : out std_logic;
+		wave64_out_first        : out std_logic;
+		wave64_out_last         : out std_logic;
+		wave64_out_allowed      : in std_logic;
+		error                   : out std_logic;
+		testword0               : out std_logic_vector(35 downto 0)
+	);    
+end component;
+
+component blockmem is
+	generic (
+		ADDRESS_BITS : natural := PANDAPACKETBUFFERBITS;
+		DATA_BITS  : natural := 66
+		);
+	port (
+		clock                   : in  std_logic; 
+		write_enable            : in std_logic;
+		write_address           : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_in                 : in std_logic_vector(DATA_BITS-1 downto 0);
+		read_address            : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_out                : out std_logic_vector(DATA_BITS-1 downto 0)
+	);
+end component;
+
+attribute syn_keep     : boolean;
+attribute syn_preserve : boolean;
+
+type readmode_type is (waitforfirst,writeemptypulsepacket1,writepulseheader,writepulsedata,
+		finishpulseheader,preparenextheader,writewaveheader,writewavedata,finishwaveheader);
+signal readmode_S             : readmode_type := waitforfirst;
+
+signal wave_in_read_S         : std_logic := '0';
+
+signal pulse64_S              : std_logic_vector(63 downto 0) := (others => '0');
+signal pulse64_write_S        : std_logic := '0';
+signal pulse64_first_S        : std_logic := '0';
+signal pulse64_last_S         : std_logic := '0';
+signal pulse64_allowed_S      : std_logic := '0';
+signal pulse64_error_S        : std_logic := '0';
+
+signal wave64_S               : std_logic_vector(63 downto 0) := (others => '0');
+signal wave64_write_S         : std_logic := '0';
+signal wave64_first_S         : std_logic := '0';
+signal wave64_last_S          : std_logic := '0';
+signal wave64_allowed_S       : std_logic := '0';
+signal wave64_error_S         : std_logic := '0';
+
+signal mem_write_S            : std_logic := '0';
+signal mem_datain_S           : std_logic_vector(65 downto 0) := (others => '0');
+signal mem_dataout_S          : std_logic_vector(65 downto 0) := (others => '0');
+signal mem_writeaddress_S     : std_logic_vector(PANDAPACKETBUFFERBITS-1 downto 0) := (others => '0');
+signal mem_readaddress_S      : std_logic_vector(PANDAPACKETBUFFERBITS-1 downto 0) := (others => '0');
+signal mem_readaddress0_S     : std_logic_vector(PANDAPACKETBUFFERBITS-1 downto 0) := (others => '0');
+signal mem_readaddress_saved_S  : std_logic_vector(PANDAPACKETBUFFERBITS-1 downto 0) := (others => '0');
+signal mem_startpacketaddress_S : std_logic_vector(PANDAPACKETBUFFERBITS-1 downto 0) := (others => '0');
+signal mem_startpacketaddress_after1clk_S : std_logic_vector(PANDAPACKETBUFFERBITS-1 downto 0) := (others => '0');
+signal mem_endpacketaddress_S : std_logic_vector(PANDAPACKETBUFFERBITS-1 downto 0) := (others => '0');
+signal data_w64_counter_S     : std_logic_vector(12 downto 0) := (others => '0');
+
+signal pulse_buffer_s         : std_logic_vector(63 downto 0) := (others => '0');
+
+signal buffer_almost_full_s   : std_logic := '0';
+signal wavemode_S             : std_logic := '0';
+signal clear_pulse64_error_s  : std_logic := '0';
+signal pulse64_erroroccurred_s: std_logic := '0';
+signal error_occurred_s       : std_logic := '0';
+signal datavalid_S            : std_logic := '0';
+signal decrement_address_S    : std_logic := '0';
+
+
+signal pulse_superburstnr_S   : std_logic_vector(30 downto 0) := (others => '0');
+signal wave_superburstnr_S    : std_logic_vector(30 downto 0) := (others => '0');
+signal prioritytopulsedata_S  : std_logic := '0';
+signal data_out_write_S       : std_logic := '0';
+signal data_out_write0_S      : std_logic := '0';
+
+signal debug_samesuperburstnumber_S      : std_logic := '0';
+signal debug_superburstnumber_S   : std_logic_vector(30 downto 0) := (others => '0');
+attribute syn_keep of debug_samesuperburstnumber_S : signal is true;
+attribute syn_preserve of debug_samesuperburstnumber_S : signal is true;
+attribute syn_keep of debug_superburstnumber_S : signal is true;
+attribute syn_preserve of debug_superburstnumber_S : signal is true;
+
+signal testword0_S            : std_logic_vector(35 downto 0) := (others => '0');
+signal testword1_S            : std_logic_vector(35 downto 0) := (others => '0');
+
+begin
+
+
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		if (pulse64_error_S='1') or (wave64_error_S='1') then
+			error <= '1';
+		else
+			error <= '0';
+		end if;
+	end if;
+end process;
+
+
+DC_superburst2packet641: DC_superburst2packet64 port map(
+		clock => clock,
+		reset => reset,
+		channel => channel,
+		statusbyte => statusbyte,
+		energy => energy,
+		timefraction => timefraction,
+		timestamp => timestamp,
+		superburstnumber => superburstnumber,
+		data_in_read => data_in_read,
+		data_in_available => data_in_available,
+		latestsuperburstnumber => latestsuperburstnumber,
+		data64_out => pulse64_S,
+		data64_out_write => pulse64_write_S,
+		data64_out_first => pulse64_first_S,
+		data64_out_last => pulse64_last_S,
+		data64_out_allowed => pulse64_allowed_S,
+		error => pulse64_error_S,
+		testword0 => testword1_S);  
+
+
+		
+DC_wave2packet641: DC_wave2packet64 port map(
+		clock => clock,
+		reset => reset,
+		wave_in => wave_in,
+		wave_in_read => wave_in_read_S,
+		wave_in_available => wave_in_available,
+		wave64_out => wave64_S,
+		wave64_out_write => wave64_write_S,
+		wave64_out_first => wave64_first_S,
+		wave64_out_last => wave64_last_S,
+		wave64_out_allowed => wave64_allowed_S,
+		error => wave64_error_S,
+		testword0 => open);    
+wave_in_read <= wave_in_read_S;
+
+blockmem1: blockmem port map(
+		clock => clock,
+		write_enable => mem_write_S,
+		write_address => mem_writeaddress_S,
+		data_in => mem_datain_S,
+		read_address => mem_readaddress_S,
+		data_out => mem_dataout_S);
+
+process(clock)
+begin
+	if (rising_edge(clock)) then		
+		if ((mem_readaddress_S=mem_writeaddress_S+1) or 
+			(mem_readaddress_S=mem_writeaddress_S+2) or 
+			(mem_readaddress_S=mem_writeaddress_S+3) or 
+			(mem_readaddress_S=mem_writeaddress_S+4)) then
+			buffer_almost_full_S <= '1';
+		else
+			buffer_almost_full_S <= '0';
+		end if;
+	end if;
+end process;
+		
+pulse64_allowed_S <= '1' when (buffer_almost_full_S='0') and
+		(((readmode_S=waitforfirst) and ((prioritytopulsedata_S='1') or ((wave64_write_S='0') and (wave_in_available='0')))) or ---- wave highest priority ?
+		((readmode_S=writepulsedata) and (wavemode_S='0'))) 
+	else '0';
+wave64_allowed_S <= '1' when (buffer_almost_full_S='0') and
+		(((readmode_S=waitforfirst) and ((prioritytopulsedata_S='0') or (pulse64_write_S='0'))) or 
+		((readmode_S=writewaveheader) and (wavemode_S='1')) or 
+		((readmode_S=writewavedata) and (wavemode_S='1')))
+	else '0';
+
+
+superburstcompare_process: process(clock)
+begin
+	if (rising_edge(clock)) then
+		if readmode_S=writepulseheader then
+			prioritytopulsedata_S <= '0';
+		else
+			if pulse_superburstnr_S<wave_superburstnr_S then
+				prioritytopulsedata_S <= '1';
+			else
+				prioritytopulsedata_S <= '0';
+			end if;
+		end if;
+	end if;
+end process;
+
+	
+writetomem_process: process(clock)
+variable status_V : std_logic_vector(15 downto 0);
+begin
+	if (rising_edge(clock)) then 
+		mem_write_S <= '0';
+		clear_pulse64_error_S <= '0';
+		if reset='1' then
+			pulse64_erroroccurred_S <= '0';
+			mem_writeaddress_S <= (others => '0');
+			mem_startpacketaddress_S <= (others => '0');
+			readmode_S <= waitforfirst;
+		else
+			if (pulse64_error_S='1') or (wave64_error_S='1') then
+				pulse64_erroroccurred_S <= '1';
+			elsif clear_pulse64_error_S='1' then
+				pulse64_erroroccurred_S <= '0';
+			end if;
+			case readmode_S is
+				when waitforfirst =>
+					mem_startpacketaddress_S <= mem_writeaddress_S;
+					if pulse64_write_S='1' then
+						wavemode_S <= '0';
+						if pulse64_first_S='1' then
+							pulse_buffer_S <= pulse64_S(63 downto 0);
+							if pulse64_last_S='1' then -- empty packet
+								mem_datain_S <= '1' & '0' & x"8000" & x"0010" & x"00000000"; -- w64:1 last packet flag, packet nr=0, size=16 bytes , 32bits not used
+								mem_write_S <= '1';
+--								mem_writeaddress_S <= mem_writeaddress_S+1;
+--								mem_startpacketaddress_S <= mem_writeaddress_S+1;
+								readmode_S <= writeemptypulsepacket1;
+							else
+								status_V := x"0000";
+								status_V(0) := pulse64_S(63); -- error, bit 63 must be 0
+								status_V(1) := error_occurred_S;
+								status_V(2) := pulse64_erroroccurred_S;
+								status_V(15) := '0'; -- indicates packet with pulse data
+								error_occurred_S <= '0';
+								clear_pulse64_error_S <= '1';
+								mem_datain_S <= '0' & '0' & status_V & SYSTEM_ID & '0' & pulse64_S(62 downto 32); -- w64:2  status, system_id and superburstntr
+								pulse_superburstnr_S <= pulse64_S(62 downto 32);
+								mem_write_S <= '1';
+--								mem_startpacketaddress_S <= mem_writeaddress_S+1;
+								mem_writeaddress_S <= mem_writeaddress_S+1; -- write second word
+								readmode_S <= writepulseheader;
+							end if;
+						else -- not first : error, cleanup
+							error_occurred_S <= '1';
+						end if;
+					elsif wave64_write_S='1' then
+						if (wave64_first_S='1') and (wave64_last_S='0') then
+							wavemode_S <= '1';
+							pulse_buffer_S <= wave64_S(63 downto 0);
+							status_V := x"0000";
+							if wave64_S(63 downto 56)/=x"dd" then
+								status_V(0) := '1'; -- error, must be DD
+							end if;
+							status_V(1) := error_occurred_S;
+							status_V(15) := '1'; -- packet containing waveform
+							error_occurred_S <= '0';
+							mem_datain_S <= '0' & '0' & status_V & SYSTEM_ID & '0' & wave64_S(30 downto 0); -- w64:2 status, system_id and superburstntr
+							wave_superburstnr_S <= wave64_S(30 downto 0);
+							mem_write_S <= '1';
+--							mem_startpacketaddress_S <= mem_writeaddress_S+1;
+							mem_writeaddress_S <= mem_writeaddress_S+1; -- write second word
+							readmode_S <= writewaveheader;
+						else -- not first : error, cleanup
+							error_occurred_S <= '1';
+						end if;
+					else
+					end if;
+				when writeemptypulsepacket1 =>
+					if buffer_almost_full_S='0' then
+						status_V := x"0000";
+						status_V(0) := pulse_buffer_S(63); -- error, bit 63 must be 0
+						status_V(1) := error_occurred_S;
+						status_V(2) := pulse64_erroroccurred_S;
+						status_V(15) := '0'; -- indicates packet with pulse data
+						error_occurred_S <= '0';
+						clear_pulse64_error_S <= '1';
+						mem_datain_S <= '0' & '1' & status_V & SYSTEM_ID & '0' & pulse_buffer_S(62 downto 32); -- w64:2 status, system_id and superburstntr
+						pulse_superburstnr_S <= pulse_buffer_S(62 downto 32);
+						mem_write_S <= '1';
+						mem_writeaddress_S <= mem_writeaddress_S+1;
+						mem_endpacketaddress_S <= mem_writeaddress_S+1;
+						readmode_S <= preparenextheader;
+					end if;
+				when writepulseheader => -- do not write, wait for allowed, set counter
+					data_w64_counter_S <= '0' & x"002";
+					if buffer_almost_full_S='0' then
+						readmode_S <= writepulsedata;
+					end if;
+				when writepulsedata => 
+					if pulse64_write_S='1' then
+						data_w64_counter_S <= data_w64_counter_S+1;
+						if pulse64_first_S='1' then -- error
+							error_occurred_S <= '1';
+							mem_writeaddress_S <= mem_startpacketaddress_S;
+							readmode_S <= waitforfirst;
+						else
+							mem_datain_S <= '0' & pulse64_last_S & pulse64_S; -- w64:4..  : pulse data
+							mem_write_S <= '1';
+							if pulse64_last_S='1' then
+								mem_endpacketaddress_S <= mem_writeaddress_S+1;
+								readmode_S <= finishpulseheader;
+							end if;
+							mem_writeaddress_S <= mem_writeaddress_S+1;
+						end if;
+					end if;
+				when finishpulseheader =>
+					if buffer_almost_full_S='0' then
+						mem_writeaddress_S <= mem_startpacketaddress_S;
+						mem_datain_S <= '1' & '0' & x"8000" & data_w64_counter_S & "000" & x"00000000"; -- w64:1  1 last packet flag, packet nr=0, size(bytes), 32bits not used
+						mem_write_S <= '1';
+						readmode_S <= preparenextheader;
+					end if;
+				when preparenextheader =>
+					mem_writeaddress_S <= mem_endpacketaddress_S+1;
+					mem_startpacketaddress_S <= mem_endpacketaddress_S+1;
+					readmode_S <= waitforfirst;
+					
+				when writewaveheader =>
+					if wave64_write_S='1' then -- second wave word 
+						mem_writeaddress_S <= mem_writeaddress_S+1;
+						mem_datain_S <= '0' & '0' & pulse_buffer_S(55 downto 48) & pulse_buffer_S(47 downto 32) & wave64_S(15 downto 8) & wave64_S(47 downto 16); -- w64:3 status, adc-channel, nrofsamples and timestamp
+						mem_write_S <= '1';
+						data_w64_counter_S <= '0' & x"003";
+						readmode_S <= writewavedata;
+					end if;
+				when writewavedata =>
+					if wave64_write_S='1' then -- second wave word 
+						data_w64_counter_S <= data_w64_counter_S+1;
+						if wave64_first_S='1' then -- error
+							error_occurred_S <= '1';
+							mem_writeaddress_S <= mem_startpacketaddress_S;
+							readmode_S <= waitforfirst;
+						else
+							mem_datain_S <= '0' & wave64_last_S & wave64_S; 
+							mem_write_S <= '1';
+							if wave64_last_S='1' then
+								mem_endpacketaddress_S <= mem_writeaddress_S+1;
+								readmode_S <= finishwaveheader;
+							end if;
+							mem_writeaddress_S <= mem_writeaddress_S+1;
+						end if;
+					end if;
+				when finishwaveheader =>
+					if buffer_almost_full_S='0' then
+						mem_writeaddress_S <= mem_startpacketaddress_S;
+						mem_datain_S <= '1' & '0' & x"8000" & data_w64_counter_S & "000" & x"00000000"; -- w64:1 last packet flag, packet nr=0, size=16 bytes , 32bits not used
+						mem_write_S <= '1';
+						readmode_S <= preparenextheader;
+					end if;
+			end case;
+		end if;
+	end if;
+end process;
+
+data_out <= mem_dataout_S(63 downto 0);
+data_out_first <= mem_dataout_S(65);
+data_out_last <= mem_dataout_S(64);
+data_out_write <= data_out_write_S;
+data_out_write_S <= '1' when (data_out_allowed='1') and (datavalid_S='1') and (decrement_address_S='0') else '0';
+
+data_out_write0_S <= '1' when (mem_readaddress_S/=mem_startpacketaddress_after1clk_S) else '0';
+mem_readaddress_S <= mem_readaddress_saved_S when (datavalid_S='1') and (data_out_allowed='0') else mem_readaddress0_S;
+
+readfrommem_process: process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if reset='1' then
+			mem_readaddress0_S <= (others => '0');
+			mem_readaddress_saved_S <= (others => '0');
+			mem_startpacketaddress_after1clk_S <= (others => '0');
+			decrement_address_S <= '0';
+		else
+			if data_out_allowed='1' then
+				if (data_out_write0_S='1') then
+					mem_readaddress0_S <= mem_readaddress0_S+1;
+					mem_readaddress_saved_S <= mem_readaddress0_S;
+					datavalid_S <= '1';
+				else
+					datavalid_S <= '0';
+				end if;
+				decrement_address_S <= '0';
+			else
+				if (datavalid_S='1') then -- retry
+					datavalid_S <= '1';
+					if (decrement_address_S='0') then
+						mem_readaddress0_S <= mem_readaddress0_S-1;
+						decrement_address_S <= '1';
+					end if;
+				end if;
+			end if;
+		end if;
+--		if data_out_allowed='1' then
+			mem_startpacketaddress_after1clk_S <= mem_startpacketaddress_S;
+--		end if;
+	end if;
+end process;
+
+
+		
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		debug_samesuperburstnumber_S <= '0';
+		if (pulse64_write_S='1') and (pulse64_first_S='1') then
+			if debug_superburstnumber_S=pulse64_S(62 downto 32) then
+				debug_samesuperburstnumber_S <= '1';
+			end if;
+			debug_superburstnumber_S <= pulse64_S(62 downto 32);
+		end if;
+	end if;
+end process;
+
+testword0 <= (others => '0');
+testword1 <= (others => '0');
+
+
+
+end Behavioral;
+
diff --git a/data_concentrator/sources/DC_energy_correction.vhd b/data_concentrator/sources/DC_energy_correction.vhd
new file mode 100644
index 0000000..148cd7b
--- /dev/null
+++ b/data_concentrator/sources/DC_energy_correction.vhd
@@ -0,0 +1,132 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   14-03-2014
+-- Module Name:   DC_energy_correction
+-- Description:   Look Up Table for energy correction
+-- Modifications:
+--   18-09-2014   different clock for loading
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+
+------------------------------------------------------------------------------------------------------
+-- DC_energy_correction
+--     Look Up Table 
+--     Energy correction with offset and linair gain factor in Look Up Table for each ADC (address). 
+--     Writing of LUT : make loading input 1, LUT address will start at 0
+--     On each write signal the next position in the LUT is written.
+--     The data in the LUT: bits 15..0 : gain correction, bits 30..16 : offset correction
+--     The offset is signed (15 bits), the output is clipped between 0 and 65535
+--     The equation: energy = ((original_energy+offset) * gainfactor)>>scalingbits
+--     with gainfactor scaled by scaling bits: if the requested gainfactor is 4 and SCALINGBITS=13, then the gainfactor is 32768 (4*2^13)
+--     
+--
+-- Library
+--     work.panda_package :  for type declarations and constants
+--
+-- generics
+--     SCALINGBITS : number of bits for scaling the gain correction
+--     LUT_ADDRWIDTH : number of bits for Look Up Table addresses : LUT depth
+--     LUT_DATAWIDTH : number of bits for Look Up Table data : LUT width
+--		
+-- inputs
+--     clock : clock
+--     loading : mode loading new LUT data, 0 means start next on position 0
+--     lut_write : write signal for writing new data to LUT, on each write the next index is selected
+--     address : index of LUT : gives corresponding value on data_out
+--     data_in : new data for LUT : bit15..0=gainfactor(>>scalingbits), bit30..16=offset
+--     energy_in : energy input
+--		
+-- outputs
+--     energy_out : corrected energy:  energy = ((original_energy+offset) * gainfactor)>>scalingbits
+--
+-- components
+--
+--
+------------------------------------------------------------------------------------------------------
+
+entity DC_energy_correction is
+	generic (
+		SCALINGBITS : natural := 13;
+		LUT_ADDRWIDTH : natural := 5;
+		LUT_DATAWIDTH  : natural := 30
+		);
+	port ( 
+		clock                   : in std_logic;
+		load_clock              : in std_logic;
+		loading                 : in std_logic;
+		lut_write               : in std_logic;
+		address                 : in std_logic_vector (LUT_ADDRWIDTH-1 downto 0);
+		data_in                 : in std_logic_vector (LUT_DATAWIDTH-1 downto 0);
+		energy_in               : in std_logic_vector (15 downto 0);
+		energy_out              : out std_logic_vector (15 downto 0));
+end DC_energy_correction;
+
+architecture behavioral of DC_energy_correction is
+
+constant ZEROS                : std_logic_vector (311 downto 0) := (others => '0');
+type energy_correction_lut_type is array (0 to 2**LUT_ADDRWIDTH-1) 
+			of std_logic_vector (LUT_DATAWIDTH-1 downto 0);
+signal lut_S                  : energy_correction_lut_type := (others => (others => '0'));
+signal data_out_S             : std_logic_vector (LUT_DATAWIDTH-1 downto 0);
+signal load_address_S         : std_logic_vector (LUT_ADDRWIDTH-1 downto 0);
+signal loading_S              : std_logic;
+signal energy_corrected_S     : std_logic_vector (31 downto 0);
+
+begin
+
+process(load_clock)
+begin
+	if (rising_edge(load_clock)) then 
+		if (lut_write = '1') then
+			lut_S(conv_integer(load_address_S)) <= data_in;
+		end if;
+	end if;
+end process;
+
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		data_out_S <= lut_S(conv_integer(address));
+	end if;
+end process;
+
+process (load_clock)
+begin
+	if (rising_edge(load_clock)) then 
+		if loading_S='0' then
+			load_address_S <= (others => '0');
+		else
+			if (lut_write='1') then
+				load_address_S <= load_address_S+1;
+			end if;
+		end if;
+		loading_S <= loading;
+	end if;
+end process;
+
+process (clock)
+variable energy_V : integer range -65536 to 65535;
+variable energy_offsetted_V : std_logic_vector(15 downto 0);
+begin
+	if (rising_edge(clock)) then 
+		energy_V := conv_integer(signed(energy_in)) + conv_integer(signed(data_out_S(30 downto 16)));
+		if energy_V<0 then
+			energy_offsetted_V := (others => '0');
+		else
+			energy_offsetted_V := conv_std_logic_vector(energy_V,16);
+		end if;
+		energy_corrected_S <= energy_offsetted_V * data_out_S(15 downto 0);
+	end if;
+end process;
+
+energy_out <= energy_corrected_S(SCALINGBITS+15 downto SCALINGBITS) 
+		when energy_corrected_S(31 downto SCALINGBITS+16) = ZEROS(31 downto SCALINGBITS+16)
+	else (others => '1');
+
+end architecture behavioral;
diff --git a/data_concentrator/sources/DC_extract_data.vhd b/data_concentrator/sources/DC_extract_data.vhd
new file mode 100644
index 0000000..03a292e
--- /dev/null
+++ b/data_concentrator/sources/DC_extract_data.vhd
@@ -0,0 +1,186 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   27-02-2012
+-- Module Name:   DC_extract_data
+-- Description:   Extract one data record from stream
+-- Modifications:
+--   30-07-2014   Timestamp from FEE is now timestamp counter within superburst, output word2 is the superburstnumber
+--   27-10-2014   Fifo for all data members in parallel
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- DC_extract_data
+-- Extract one data record from stream.
+-- The input pulse data consists of the following items (parallel)
+--        channel : adc-index
+--        statusbyte : 8 bit status information
+--        energy : pulse energy
+--        timefraction : fraction part of the timestamp
+--        timestamp : 16 bits timestamp within superburst, synchronised to master SODA clock
+--        superburstnumber : 31 bits superburst number
+-- The output :
+--        word0 : statusbyte & 00 & adcnumber
+--        word1 : timefraction & energy
+--        word2 : '0' & superburstnumber
+--        word3 : 0000 & timestamp(15..0)
+--
+-- Library
+--     work.panda_package :  for type declarations and constants
+-- 
+-- Generics:
+-- 
+-- Inputs:
+--     write_clock : clock for incoming data
+--     read_clock : clock for outgoing data
+--     reset : reset of all components
+--     start : start waiting for data and extract one data-pulse
+--     make_selection : select one adcnumber from the stream, otherwise take the first arriving data
+--     dualgain : select both high and low gain channels (discard lowest bit from adcnumber)
+--     adcnumber : number of the adc to extract, if make_selection='1'
+--     channel : data input : adc channel
+--     statusbyte : data input : status
+--     energy : data input : pulse energy
+--     timefraction : data input : Constant Fraction time
+--     timestamp : data input : time within superburst
+--     superburstnumber : data input : superburst number
+--     pulse_data_write : write signal for the pulse_data
+--     pulse_data_select : select the 32-bits word index of the extracted data
+-- 
+-- Outputs:
+--     ready : extracted pulse-data available
+--     pulse_data_out : extracted pulse data (32 bits, select with pulse_data_select):
+--        word0 : statusbyte & 00 & adcnumber
+--        word1 : timefraction & energy
+--        word2 : '0' & superburstnumber
+--        word3 : 0000 & timestamp(15..0)
+-- 
+-- Components:
+--     async_fifo_af_512x36 : Asynchronous fifo 36bits wide, 512 words deep
+--
+----------------------------------------------------------------------------------
+
+entity DC_extract_data is
+	port ( 
+		write_clock             : in std_logic;
+		read_clock              : in std_logic;
+		reset                   : in std_logic;
+		start                   : in std_logic;
+		make_selection          : in std_logic;
+		dualgain                : in std_logic;
+		adcnumber               : in std_logic_vector(15 downto 0);		
+		channel                 : in std_logic_vector(15 downto 0);
+		statusbyte              : in std_logic_vector(7 downto 0);
+		energy                  : in std_logic_vector(15 downto 0);
+		timefraction            : in std_logic_vector(11 downto 0);
+		timestamp               : in std_logic_vector(15 downto 0);
+		superburstnumber        : in std_logic_vector(30 downto 0);		
+		pulse_data_write        : in std_logic;
+		ready                   : out std_logic;
+		pulse_data_select       : in std_logic_vector(1 downto 0);
+		pulse_data_out          : out std_logic_vector(31 downto 0);
+		testword0               : out std_logic_vector(35 downto 0)
+		);
+end DC_extract_data;
+
+architecture Behavioral of DC_extract_data is
+
+component async_fifo_512x99 is
+	port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(98 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(98 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic);
+end component;
+
+
+signal make_selection_S       : std_logic;
+signal dualgain_S             : std_logic;
+signal ready_S                : std_logic := '0';
+
+signal timestamp_S            : std_logic_vector(15 downto 0);
+signal superburstnumber_S     : std_logic_vector(30 downto 0);
+signal statusbyte_S           : std_logic_vector(7 downto 0);
+signal channel_S              : std_logic_vector(15 downto 0);
+signal timefraction_S         : std_logic_vector(11 downto 0);
+signal energy_S               : std_logic_vector(15 downto 0);
+
+
+signal fifo_write_S           : std_logic := '0';
+signal fifo_read_S            : std_logic := '0';
+signal fifo_full_S            : std_logic := '0';
+signal fifo_empty_S           : std_logic := '0';
+
+begin
+
+asyncdatafifo: async_fifo_512x99 port map(
+		rst => reset,
+		wr_clk => write_clock,
+		rd_clk => read_clock,
+		din(15 downto 0) => channel,
+		din(31 downto 16) => energy,
+		din(47 downto 32) => timestamp,
+		din(55 downto 48) => statusbyte,
+		din(67 downto 56) => timefraction,
+		din(98 downto 68) => superburstnumber,
+		wr_en => fifo_write_S,
+		rd_en => fifo_read_S,
+		dout(15 downto 0) => channel_S,
+		dout(31 downto 16) => energy_S,
+		dout(47 downto 32) => timestamp_S,
+		dout(55 downto 48) => statusbyte_S,
+		dout(67 downto 56) => timefraction_S,
+		dout(98 downto 68) => superburstnumber_S,
+		full => fifo_full_S,
+		empty => fifo_empty_S);
+		
+fifo_write_S <= '1' when ((pulse_data_write='1') and (fifo_full_S='0')) and
+		((make_selection_S='0') or
+			((channel=adcnumber) and (dualgain_S='0')) or
+			((channel(15 downto 1)=adcnumber(15 downto 1)) and (dualgain_S='1')))
+	else '0';
+
+process(write_clock)
+begin
+	if (rising_edge(write_clock)) then 
+		make_selection_S <= make_selection;
+		dualgain_S <= dualgain;
+	end if;
+end process;
+		
+pulse_data_out <= 
+	statusbyte_S & x"00" & channel_S when pulse_data_select="00" else
+	"0000" & timefraction_S & energy_S when pulse_data_select="01" else
+	'0' & superburstnumber_S when pulse_data_select="10" else
+	x"0000" & timestamp_S; -- when pulse_data_select="11" else
+	
+ready <= ready_S;
+process(read_clock)
+begin
+	if (rising_edge(read_clock)) then 
+		fifo_read_S <= '0';
+		if start='1' then
+			ready_S <= '0';
+		elsif ready_S='0' then
+			if fifo_empty_S='0' then
+				fifo_read_S <= '1';
+				ready_S <= '1';
+			end if;
+		end if;
+	end if;
+end process;		
+
+testword0 <= (others => '0');
+
+end Behavioral;
\ No newline at end of file
diff --git a/data_concentrator/sources/DC_extract_wave.vhd b/data_concentrator/sources/DC_extract_wave.vhd
new file mode 100644
index 0000000..8ab462b
--- /dev/null
+++ b/data_concentrator/sources/DC_extract_wave.vhd
@@ -0,0 +1,374 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   13-03-2012
+-- Module Name:   DC_extract_wave
+-- Description:   Extract one waveform from stream
+-- Modifications:
+--    16-09-2014: name changed from MUX_extract_wave to DC_extract_wave
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- DC_extract_wave
+-- Extract one data record from stream.
+-- The input data consists of 36 bits words, same format as used in waveform multiplexer.
+-- The output is 32 bits wide, adc-samples are truncated to 15 bit (signed).
+--
+--
+-- Library
+--     work.panda_package :  for type declarations and constants
+-- 
+-- Generics:
+-- 
+-- Inputs:
+--     write_clock : clock for incoming data
+--     read_clock : clock for outgoing data
+--     reset : reset of all components
+--     start : start waiting for data and extract one data-pulse
+--     make_selection : select one adcnumber from the stream, otherwise take the first arriving data
+--     dualgain : select both high and low gain channels (discard lowest bit from adcnumber)
+--     adcnumber : number of the adc to extract, if make_selection='1'
+--     wave_data_in : 36 bits data with Feature Extraction Results, each 4*36-bits:
+--        	bits(35..32)="0000" : bits(31..0)=timestamp of maximum value in waveform
+--        	bits(35..32)="0001" : bits(31..24)=00 bits(23..0)=SuperBurst number
+--        	bits(35..32)="0010" : 
+--              bits(31..24) = statusbyte (bit6=overflow) 
+--              bits(23..16) = 00
+--              bits(15..0) = adcnumber (channel identification)
+--        	bits(35..32)="0011" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+--        	bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+--        	bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+--        	bits(35..32)="1111" : error: buffer full, waveform not valid
+--     wave_data_in_write : write signal for 36-bits input data
+--     wave_data_out_read : read signal for extracted waveform
+-- 
+-- Outputs:
+--     ready : extracted pulse-data available
+--     wave_data_read : read 36-bits wave data
+--     wave_data_out : extracted pulse data (32 bits, sequential with each wave_data_out_read):
+--        	word0: bits(31..0)=timestamp of maximum value in waveform
+--        	word1: bits(31..24)=00, bits(23..0)=SuperBurst number
+--        	word2: bits(31..24) = statusbyte, bits(23..16) = 00, bits(15..0) = adcnumber (channel identification)
+--        	word3..n: bit(31)=0, bits(30..16)=adc sample, bit(15)=0, bits(14..0)=next adc sample
+--        	last word (1sample): bits(31)=1, bits(30..16)=last adc sample, bit(15)=0, bits(14..0)=0
+--        	last word (2samples): bits(31)=0, bits(30..16)=adc sample, bit15=1, bits(14..0)=last adc sample
+--        	last word (error): bits(31)=1, bits(30..16)=don't care, bit15=1, bits(14..0)=don't care
+-- 
+-- Components:
+--     async_fifo_af_512x36 : Asynchronous fifo 36bits wide, 512 words deep
+--     posedge_to_pulse : Makes a 1-clock pulse on rising edge from signal with different clock
+--
+----------------------------------------------------------------------------------
+
+entity DC_extract_wave is
+	port ( 
+		write_clock             : in std_logic;
+		read_clock              : in std_logic;
+		reset                   : in std_logic;
+		start                   : in std_logic;
+		make_selection          : in std_logic;
+		dualgain                : in std_logic;
+		adcnumber               : in std_logic_vector(15 downto 0);		
+		wave_data_in            : in std_logic_vector(35 downto 0);
+		wave_data_in_write      : in std_logic;
+		ready                   : out std_logic;
+		wave_data_out           : out std_logic_vector(31 downto 0);
+		wave_data_out_read      : in std_logic;
+		testword0               : out std_logic_vector(35 downto 0)
+		);
+end DC_extract_wave;
+
+
+architecture Behavioral of DC_extract_wave is
+
+component async_fifo_512x32 is
+	port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(31 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(31 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic);
+end component;
+
+component posedge_to_pulse is
+	port (
+		clock_in                : in  std_logic;
+		clock_out               : in  std_logic;
+		en_clk                  : in  std_logic;
+		signal_in               : in  std_logic;
+		pulse                   : out std_logic);
+end component;
+
+signal reset_wrclk_S          : std_logic := '0';
+signal ready_S                : std_logic := '0';
+
+
+signal fifo_reset_S           : std_logic := '0';
+signal fifo_reset0_S          : std_logic := '0';
+signal fifo_resetting_S       : std_logic := '0';
+signal fifo_write_S           : std_logic := '0';
+signal fifo_read_S            : std_logic := '0';
+signal fifo_empty_S           : std_logic := '0';
+signal fifo_data_in_S         : std_logic_vector(31 downto 0) := (others => '0');
+signal fifo_data_out_S        : std_logic_vector(31 downto 0) := (others => '0');
+
+signal startpulse_S           : std_logic := '0';
+signal fifo_writing_S         : std_logic := '0';
+signal fifo_writing0_S        : std_logic := '0';
+signal started_S              : std_logic := '0';
+
+signal error1_S               : std_logic := '0';
+signal error2_S               : std_logic := '0';
+signal readcount_S            : integer range 0 to 255 := 0;
+
+begin
+
+process(read_clock)
+begin
+	if (rising_edge(read_clock)) then 
+		ready <= ready_S;
+	end if;
+end process;
+
+
+makestartepulse: posedge_to_pulse port map(
+		clock_in => read_clock,
+		clock_out => write_clock,
+		en_clk => '1',
+		signal_in => start,
+		pulse => startpulse_S);
+
+asyncdatafifo: async_fifo_512x32 port map(
+		rst => fifo_reset_S,
+		wr_clk => write_clock,
+		rd_clk => read_clock,
+		din => fifo_data_in_S,
+		wr_en => fifo_write_S,
+		rd_en => fifo_read_S,
+		dout => fifo_data_out_S,
+		full => open,
+		empty => fifo_empty_S);
+		
+fifo_reset_S <= '1' when (startpulse_S='1') or (reset_wrclk_S='1') or (fifo_reset0_S='1') else '0';
+fifo_write_S <= '1' when (wave_data_in_write='1') and (fifo_writing_S='1') 
+		and ((fifo_resetting_S='0') and (fifo_reset_S='0')) 
+	else '0';
+fifo_writing_S <= '1' when (fifo_writing0_S='1')
+		or ((wave_data_in(35 downto 32)="0000") and (wave_data_in_write='1') and (started_S='1'))
+	else '0';
+
+fifo_data_in_S <= 
+		wave_data_in(31 downto 0) 
+			when ((wave_data_in(35 downto 32)="0000") or (wave_data_in(35 downto 32)="0001") or (wave_data_in(35 downto 32)="0010")) else
+		'0' & wave_data_in(30 downto 16) & '0' & wave_data_in(14 downto 0) 
+			when (wave_data_in(35 downto 32)="0011") else
+		'0' & wave_data_in(30 downto 16) & '1' & wave_data_in(14 downto 0) 
+			when (wave_data_in(35 downto 32)="0101") else
+		'1' & wave_data_in(30 downto 16) & '0' & "000000000000000" 
+			when (wave_data_in(35 downto 32)="0100") else
+		'1' & "000000000000000" & '1' & "000000000000000";
+		
+wave_data_out <= fifo_data_out_S;
+fifo_read_S <= wave_data_out_read;
+
+
+process(write_clock)
+variable resetcounter_V : integer range 0 to 3 := 0;
+begin
+	if (rising_edge(write_clock)) then 
+		if fifo_reset_S='1' then
+			resetcounter_V := 0;
+			fifo_resetting_S <= '1';
+		elsif resetcounter_V<3 then
+			resetcounter_V := resetcounter_V+1;
+			fifo_resetting_S <= '1';
+		else
+			fifo_resetting_S <= '0';
+		end if;
+		if (reset_wrclk_S = '1') then
+			fifo_writing0_S <= '0';
+			started_S <= '0';
+			ready_S <= '0';
+			fifo_reset0_S <= '0';
+		else
+			if started_S='1' then
+				if fifo_writing0_S='0' then
+					if (wave_data_in(35 downto 32)="0000") and (fifo_write_S='1') then 
+						fifo_writing0_S <= '1';
+					end if;
+					fifo_reset0_S <= '0';
+				else
+					if wave_data_in_write='1' then
+						if (wave_data_in(35 downto 32)="0010") then
+							if  (make_selection='0') or 
+								((adcnumber(15 downto 0)=wave_data_in(15 downto 0)) and (dualgain='0')) or
+								((adcnumber(15 downto 1)=wave_data_in(15 downto 1)) and (dualgain='1')) then
+								fifo_reset0_S <= '0';
+							else
+								fifo_writing0_S <= '0';
+								ready_S <= '0';
+								fifo_reset0_S <= '1';
+							end if;
+						elsif (wave_data_in(35 downto 32)="0000") or (wave_data_in(35 downto 32)="0001")  or (wave_data_in(35 downto 32)="0011") then
+							fifo_reset0_S <= '0';
+						elsif (wave_data_in(35 downto 32)="1111") then
+							fifo_writing0_S <= '0';
+							ready_S <= '0';
+							fifo_reset0_S <= '1';
+						else
+							fifo_reset0_S <= '0';
+							fifo_writing0_S <= '0';
+							started_S <= '0';
+							ready_S <= '1';
+						end if;
+					else
+						fifo_reset0_S <= '0';
+					end if;
+				end if;
+			else
+				fifo_reset0_S <= '0';
+				if startpulse_S='1' then
+					fifo_writing0_S <= '0';
+					started_S <= '1';
+					ready_S <= '0';
+				end if;					
+			end if;
+		end if;
+		reset_wrclk_S <= reset;
+	end if;
+end process;
+
+
+process(write_clock)
+variable last_tfifo_in_V : std_logic_vector(3 downto 0) := "0100";
+begin
+	if (rising_edge(write_clock)) then 
+		error1_S <= '0';
+		if (wave_data_in_write='1') then
+			case last_tfifo_in_V is
+				when "0000" =>
+					if wave_data_in(35 downto 32)/="0001" then
+						error1_S <= '1';
+					elsif wave_data_in(31 downto 24)/=x"00" then
+						error1_S <= '1';
+					end if;
+				when "0001" =>
+					if wave_data_in(35 downto 32)/="0010" then
+						error1_S <= '1';
+					elsif wave_data_in(15 downto 4)/=x"111" then
+						error1_S <= '1';
+					end if;
+				when "0010" =>
+					if wave_data_in(35 downto 32)/="0011" then
+						error1_S <= '1';
+					end if;
+				when "0011" =>
+					if (wave_data_in(35 downto 32)/="0011") and (wave_data_in(35 downto 33)/="010") then
+						error1_S <= '1';
+					end if;
+				when "0100" =>
+					if (wave_data_in(35 downto 32)/="0000") then
+						error1_S <= '1';
+					end if;
+				when "0101" =>
+					if (wave_data_in(35 downto 32)/="0000") then
+						error1_S <= '1';
+					end if;
+				when others =>
+					error1_S <= '1';
+			end case;
+			last_tfifo_in_V := wave_data_in(35 downto 32);
+		end if;
+	end if;
+end process;
+
+
+
+process(read_clock)
+variable last_tfifo_in_V : std_logic_vector(31 downto 0) := (others => '0');
+variable fifo_read_V : std_logic := '0';
+variable resetted_V : integer range 0 to 3 := 0;
+variable last_V : std_logic := '0';
+begin
+	if (rising_edge(read_clock)) then 
+		error2_S <= '0';
+		if fifo_reset_S='1' then
+			resetted_V := 0;
+			last_V := '0';
+			readcount_S <= 0;
+		else
+			if fifo_read_V='1' then
+				readcount_S <= readcount_S+1;
+				if resetted_V<3 then
+					if resetted_V=0 then -- timestamp
+					elsif resetted_V=1 then -- burst
+						if fifo_data_out_S(31 downto 24)/=x"00" then
+							error2_S <= '1';
+						end if;
+					elsif resetted_V=2 then -- adcnr
+						if fifo_data_out_S(15 downto 4)/=x"111" then
+							error2_S <= '1';
+						end if;
+					end if;
+					resetted_V := resetted_V+1;
+					last_V := '0';
+				else
+					if last_V='1' then
+						error2_S <= '1';
+					else					
+						if (fifo_data_out_S(31)='0') and (fifo_data_out_S(15)='0') then
+						elsif (fifo_data_out_S(31)='0') and (fifo_data_out_S(15)='1') then
+							last_V := '1';
+						elsif (fifo_data_out_S(31)='1') and (fifo_data_out_S(15)='0') then
+							last_V := '1';
+						else 
+							last_V := '1';
+							error2_S <= '1';
+						end if;
+					end if;
+				end if;
+			end if;
+		end if;
+		fifo_read_V := fifo_read_S;
+	end if;
+end process;
+
+testword0(7 downto 0) <= conv_std_logic_vector(readcount_S,8); -- fifo_data_in_S(11 downto 4);
+testword0(8) <= fifo_data_in_S(15);
+testword0(9) <= fifo_data_in_S(31);
+testword0(10) <= fifo_write_S;
+testword0(11) <= fifo_writing_S;
+testword0(12) <= fifo_writing0_S;
+
+testword0(13) <= fifo_reset_S;
+testword0(14) <= fifo_reset0_S;
+
+testword0(15) <= ready_S;
+testword0(16) <= startpulse_S;
+testword0(17) <= started_S;
+
+testword0(18) <= fifo_empty_S;
+testword0(19) <= fifo_read_S;
+testword0(27 downto 20) <= fifo_data_out_S(11 downto 4);
+testword0(28) <= fifo_data_out_S(15);
+testword0(29) <= fifo_data_out_S(31);
+testword0(30) <= error1_S;
+testword0(31) <= error2_S;
+testword0(32) <= fifo_resetting_S;
+testword0(33) <= '1' when (started_S='1') and (fifo_writing0_S='0') and (wave_data_in(35 downto 32)="0000") and (fifo_write_S='1') else '0';
+
+testword0(35 downto 34) <= (others => '0');
+
+
+
+end Behavioral;
diff --git a/data_concentrator/sources/DC_fibermodule_interface.vhd b/data_concentrator/sources/DC_fibermodule_interface.vhd
new file mode 100644
index 0000000..958a81b
--- /dev/null
+++ b/data_concentrator/sources/DC_fibermodule_interface.vhd
@@ -0,0 +1,1001 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   05-03-2014
+-- Module Name:   DC_fibermodule_interface
+-- Description:   Module for connection between fiber module to/from FEE and MUX board
+-- Modifications:
+--   30-07-2014   Timestamp from FEE is now composed by 16 bits superburstnumber and timestamp counter within superburst
+--   16-09-2014   New data format between FEE and DC, correction LUTs are now in DC
+--   18-09-2014   different clock for loading
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- DC_fibermodule_interface
+-- Module for connection between fiber module to/from FEE and multiplexer and CPU slowcontrol modules on
+-- the Panda Data collector board:
+-- Slowcontrol commands from the control system are put in packets and sent to the fiber module.
+-- SODA packets are passed through to the fiber.
+-- Data packets are received from the fiber, analysed and translated to Pulse-data, Pileup Waveforms and slowcontrol data.
+-- This module can also send some slowcontrol commands to the CPU by itself, see work.panda_package for constants:
+--     ADDRESS_BOARDNUMBER :
+--         bit11..0 = sets the unique boardnumber
+--         bit31 = initialize all FEE registers that have been set
+--     ADDRESS_MUX_MAXCFLUTS : 
+--         bit15..0 : data for the CF or MAX Look Up Table
+--         bit25..16 :offset for maximum correction LUT
+--         bit26 : write signal for maximum LUT
+--         bit27 : loading maximum correction LUT
+--         bit28 : enable maximum correction
+--         bit29 : write signal for Constant Fraction LUT
+--         bit30 : loading CF correction LUT
+--         bit31 : enable CF correction
+--     ADDRESS_MUX_FIBERMODULE_STATUS :
+--         command: clear error bits, pulse skipped counter
+--         request : request status; Reply, or in case of error: Status of the fibermodule:
+--         bit0 : error in slowcontrol to cpu occured
+--         bit1 : error if slowcontrol transmit data
+--         bit1 : error if fiber receive data
+--         bit3 : pulse data skipped due to full multiplexer fifo
+--         bit4 : receiver locked
+--         bit15..8 : number of pulse data packets skipped due to full buffers
+--     ADDRESS_MUX_MULTIPLEXER_STATUS :  status/fullness of the multiplexer
+--         bit 15..0 : number of words in input fifo of the multiplexer
+--         bit 15..0 : number of words in output fifo of the multiplexer, only for fiber index 0
+--     ADDRESS_MUX_TIMESTAMP_ERRORS
+--         bit 9..0 : number of timestamp mismatches
+--         bit 19..10 : number of skipped pulses
+--         bit 29..20 : number of data errors
+--     ADDRESS_MUX_TIMESHIFT
+--       number of  clockcycles (incl. constant fraction) to compensate for delay SODA to FEE
+--         bit 10..0 : compensation time, fractional part; number of bits for constant fraction, see CF_FRACTIONBIT
+--         bit 30..16 : compensation time, integer part
+--         bit 31 : load mode, after set to 1 starts with ADC0 on each write, and so on
+--     ADDRESS_MUX_ENERGYCORRECTION
+--       energy correction Look Up Table
+--         bit 15..0 : gain correction (multiplying factor shifted by number of scalingsbits)
+--         bit 30..16 : offset for energy
+--         bit 31 : loading LUT mode, after set to 1 starts with ADC0 on each write, and so on
+--
+-- Library
+--     work.panda_package :  for type declarations and constants
+-- 
+-- Generics:
+--     NROFADCS : number of ADCs per FEE
+--     ADCBITS : number of ADC-bits
+--     ADCINDEXSHIFT : ADC channel numbers lowest bit indicates the high or low gain ADC, 0=high, 1=low
+--     CF_FRACTIONBIT : number of valid constant fraction bits
+--     ENERGYSCALINGBITS : number of scaling bits for energy adjustment
+--     MAX_DIVIDERSCALEBITS : number of scaling bits for division two largest samples
+--     MAX_LUTSIZEBITS : number of bits the maximum correction Look Up Table
+--     MAX_LUTSCALEBITS : number of scaling bits for the correction on the maximum (energy)
+-- 
+-- Inputs:
+--     slowcontrol_clock : clock for the slowcontrol input/output
+--     packet_clock : clock for data from the fiber module
+--     MUX_clock : clock from multiplexer, only used for multiplexer status
+--     SODA_clock : clock SODA, used to update superburst
+--     reset : reset of all components
+--     resetDone : signal from gtp/gtx/serdes that reset is done
+--     channel : index of the fiber
+--     superburst_number : most recent superburst-number
+--     superburst_update : new most recent superburst-number+timestamp
+--     IO_byte : 5-bits slowcontrol data from CPU
+--         Byte0 : Read bit , "000", index of the fiber 
+--         Byte1,2,3,4 : alternating: 
+--                     request-bit 101 xxxx 24-bits_address(MSB first)
+--                     32-bits_data, MSB first
+--     IO_write : write signal for byte-data, only selected fiber (with index in first byte) should react
+--     muxstat_infifo_fullness : number of words in multiplexer input fifo, report to slowcontrol
+--     muxstat_outfifo_fullness : number of words in multiplexer output fifo, report to slowcontrol
+--     timestamp_errors : number of timestamp-errors in data stream, report to slowcontrol
+--     skipped_pulses : number of pulses skipped due to buffer overflow, report to slowcontrol
+--     dataerrors : number of errors in data stream, report to slowcontrol
+--     pulse_data_out_allowed : allowed to write pulse data (not fifo-full signal from connected fifo)
+--     wave_data_out_allowed : allowed to write full pileup waveform data (not fifo-full signal from connected fifo)
+--     txAsyncFifoFull : fifo-full signal from fiber async data fifo
+--     txLocked : signal that transmitter clock is locked
+--     rxAsyncDataPresent : receive data available
+--     rxAsyncData : receive data 
+--     rxNotInTable : received 10 bits was not in conversion table to 8 bits: error!
+--     rxLocked : signal that the receiver clock is locked
+--
+-- Outputs:
+--     IO_serialdata : Serial slowcontrol: request&address or data alternating
+--     IO_serialavailable : Slowcontrol data is available
+--     pulse_data_out : 36 bits data with Feature Extraction Results, each 4*36-bits:
+--         word0 : 0 & 0000 & timestamp(15..0)
+--         word1 : 1 & 0 & superburstnumber(30..0)
+--         word2 : 2 & statusbyte & 00 & adcnumber
+--         word3 : 3 & timefraction & energy
+--     pulse_data_write : write signal for pulse data
+--     wave_data_out : 36 bits data with pileup waveforms:
+--        	bits(35..32)="0000" : bits(15..0)=timestamp of waveform
+--        	bits(35..32)="0001" : bits(31)=0 bits(30..0)=SuperBurst number
+--        	bits(35..32)="0010" : 
+--              bits(31..24) = statusbyte (bit7=overflow) 
+--              bits(23..16) = 00
+--              bits(15..0) = adcnumber (channel identification)
+--        	bits(35..32)="0011" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+--        	bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+--        	bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+--        	bits(35..32)="1111" : error: buffer full, waveform not valid
+--     wave_data_write : write signal for ileup waveform data
+--     txAsyncDataWrite : async data write signal
+--     txAsyncData : async data to GTP/GTX/serdes (32 bits)
+--     txEndOfAsyncData : indicates last data word
+--     rxAsyncClk : clock for async data
+--     rxAsyncDataRead : read signal for reading async data from the receiver fifo
+
+-- 
+-- Components:
+--     DC_slowcontrol_packetbuilder : makes fiber-packet from slowcontrol command
+--     DC_slowcontrol_receive_from_cpu : receive byte-wise data from CPU and translate to parallel slowcontrol
+--     DC_slowcontrol_to_serial : sends slow control data serially to the CPU
+--     DC_separate_data : translate received fiber packets to slowcontrol data, pulse data or waveform
+--     synchronize_to_other_clock : synchronize data to other clock
+--     DC_measure_frequency : Measure the frequency of the pulses from one fiber
+--     posedge_to_pulse : Makes a 1-clock pulse on rising edge from signal with different clock
+--
+----------------------------------------------------------------------------------
+
+entity DC_fibermodule_interface is
+	generic (
+		NROFADCS                : natural := 16;
+		ADCINDEXSHIFT           : natural := 1;
+		ADCBITS                 : natural := 14;
+		CF_FRACTIONBIT          : natural := 11;
+		ENERGYSCALINGBITS       : natural := 13;
+		MAX_DIVIDERSCALEBITS    : natural := 12;
+		MAX_LUTSIZEBITS         : natural := 8;
+		MAX_LUTSCALEBITS        : natural := 14
+	);
+	port ( 
+		slowcontrol_clock       : in std_logic;
+		packet_clock            : in std_logic;
+		MUX_clock               : in std_logic;
+		SODA_clock              : in std_logic;
+		reset                   : in std_logic;
+		resetDone               : in std_logic;
+		channel                 : in std_logic_vector (3 downto 0);
+		superburst_number       : in std_logic_vector(30 downto 0);
+		superburst_update       : in std_logic;
+
+-- SlowControl to/from cpu
+		IO_byte                 : in std_logic_vector(7 downto 0);
+		IO_write                : in std_logic;
+		IO_serialdata           : out std_logic;
+		IO_serialavailable      : out std_logic;
+		
+-- multiplexer status
+		muxstat_infifo_fullness : in std_logic_vector (15 downto 0);
+		muxstat_outfifo_fullness : in std_logic_vector (15 downto 0);
+		timestamp_errors        : in std_logic_vector(9 downto 0);
+		skipped_pulses          : in std_logic_vector(9 downto 0);
+		dataerrors              : in std_logic_vector(9 downto 0);
+		
+-- Pulse data
+		pulse_data_out          : out std_logic_vector (35 downto 0);
+		pulse_data_write        : out std_logic;
+		pulse_data_out_allowed  : in std_logic;
+
+-- Wave data
+		wave_data_out           : out std_logic_vector(35 downto 0);
+		wave_data_write         : out std_logic;
+		wave_data_out_allowed   : in std_logic;
+
+-- Testpoints
+		testword0               : out std_logic_vector (35 downto 0);
+		testword1               : out std_logic_vector (35 downto 0);
+
+-- MUX tx interface signals:
+		txAsyncDataWrite        : out std_logic;
+		txAsyncData             : out std_logic_vector(31 downto 0);
+		txEndOfAsyncData        : out std_logic;
+		txAsyncFifoFull         : in std_logic;
+		txLocked                : in std_logic;
+
+-- MUX rx interface signals:
+		rxAsyncClk              : out std_logic;
+		rxAsyncDataRead         : out std_logic;
+		rxAsyncDataPresent      : in std_logic;
+		rxAsyncData             : in std_logic_vector(31 downto 0);
+		rxNotInTable            : in std_logic;
+		rxLocked                : in std_logic
+		);
+end DC_fibermodule_interface;
+
+architecture Behavioral of DC_fibermodule_interface is
+
+component DC_slowcontrol_packetbuilder is
+	port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		init_FEE                : in  std_logic; 
+		slowcontrol_data        : in std_logic_vector (31 downto 0);
+		slowcontrol_address     : in std_logic_vector (23 downto 0);
+		slowcontrol_request     : in std_logic;
+		slowcontrol_write       : in std_logic; 
+		slowcontrol_allowed     : out std_logic; 
+		packet_data_out         : out std_logic_vector (31 downto 0);
+		packet_lastword         : out std_logic;
+		packet_datawrite        : out std_logic;
+		packet_fifofull         : in std_logic
+	);		
+end component;
+
+component DC_slowcontrol_receive_from_cpu is
+	port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		channel                 : in std_logic_vector (3 downto 0);
+		IO_byte                 : in std_logic_vector(7 downto 0);
+		IO_write                : in std_logic;
+		slowcontrol_data        : out std_logic_vector (31 downto 0);
+		slowcontrol_address     : out std_logic_vector (23 downto 0);
+		slowcontrol_request     : out std_logic;
+		slowcontrol_write       : out std_logic; 
+		slowcontrol_fifofull    : in std_logic; 
+		error                   : out std_logic
+		);
+end component;
+
+component DC_slowcontrol_to_serial is
+	port ( 
+		write_clock             : in std_logic;
+		read_clock              : in std_logic;
+		reset                   : in std_logic;
+		channel                 : in std_logic_vector (3 downto 0);
+		slowcontrol_data        : in std_logic_vector (31 downto 0);
+		slowcontrol_address     : in std_logic_vector (23 downto 0);
+		slowcontrol_reply       : in std_logic;
+		slowcontrol_write       : in std_logic;			  
+		IO_byte                 : in std_logic_vector (7 downto 0);
+		IO_write                : in std_logic;
+		IO_serialdata           : out std_logic;
+		IO_serialavailable      : out std_logic;
+		error                   : out std_logic
+		);
+end component;
+
+component DC_separate_data is
+	generic (
+		NROFADCS                : natural := NROFADCS;
+		ADCBITS                 : natural := ADCBITS;
+		ADCINDEXSHIFT           : natural := ADCINDEXSHIFT;
+		CF_FRACTIONBIT          : natural := CF_FRACTIONBIT;
+		ENERGYSCALINGBITS       : natural := ENERGYSCALINGBITS;
+		MAX_DIVIDERSCALEBITS    : natural := MAX_DIVIDERSCALEBITS;
+		MAX_LUTSIZEBITS         : natural := MAX_LUTSIZEBITS;
+		MAX_LUTSCALEBITS        : natural := MAX_LUTSCALEBITS
+	);
+    Port ( 
+		clock                   : in  std_logic;
+		load_clock              : in std_logic;
+		SODA_clock              : in  std_logic;
+		reset                   : in  std_logic;
+		enable                  : in  std_logic;
+		
+		timeshiftLUT_write      : in  std_logic;
+		timeshiftLUT_loading    : in  std_logic;
+		timeshiftLUT_data       : in  std_logic_vector (30 downto 0);
+		
+		energyLUT_write         : in  std_logic;
+		energytLUT_loading      : in  std_logic;
+		energyLUT_data          : in  std_logic_vector (30 downto 0);
+		
+		max_correction          : in std_logic;
+		max_LUT_offset          : in std_logic_vector(MAX_LUTSIZEBITS-1 downto 0);
+		max_LUT_loading         : in std_logic;
+		max_LUT_write           : in std_logic;
+		
+		fraction_correction     : in std_logic;
+		fraction_LUT_loading    : in std_logic;
+		fraction_LUT_write      : in std_logic;
+		LUT_data_in             : in std_logic_vector(CF_FRACTIONBIT-1 downto 0);
+		
+		packet_data_in          : in  std_logic_vector (31 downto 0);
+		packet_data_present     : in  std_logic;
+		packet_data_read        : out std_logic;
+		
+		pulse_data_out          : out std_logic_vector(35 downto 0);
+		pulse_data_write        : out std_logic;
+		pulse_data_out_allowed  : in  std_logic;
+		
+		slowcontrol_data        : out std_logic_vector (31 downto 0);
+		slowcontrol_address     : out std_logic_vector (7 downto 0);
+		slowcontrol_reply       : out std_logic;
+		slowcontrol_write       : out std_logic;
+		
+		wave_data_out           : out std_logic_vector(35 downto 0);
+		wave_data_write         : out std_logic;
+		wave_data_out_allowed   : in std_logic;
+		
+		FEEboardnumber          : in std_logic_vector (15 downto 0);
+		superburst_number       : in std_logic_vector(30 downto 0);
+		superburst_update       : in std_logic;
+		
+		error                   : out std_logic;
+		pulse_data_skipped      : out std_logic;
+		testword0               : out std_logic_vector (35 downto 0));
+end component;
+		
+component synchronize_to_other_clock is
+    generic (
+        DATA_WIDTH            : natural := 16
+    );
+    port (
+		data_in_clock : in std_logic;
+		data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
+		data_out_clock : in std_logic;
+		data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
+    );
+end component;
+
+component DC_measure_frequency is
+	generic (
+		CLOCKFREQUENCY          : natural := 125000000
+	);
+	port ( 
+		clock                   : in std_logic;
+		pulse                   : in std_logic;
+		frequency               : out std_logic_vector(31 downto 0)
+	);
+end component;
+
+component MUX_check_timestamp is
+	port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		clear                   : in std_logic;
+		pulse_data              : in std_logic_vector(35 downto 0);
+		pulse_data_write        : in std_logic;
+		timestamp_errors        : out std_logic_vector(9 downto 0);
+		skipped_pulses          : out std_logic_vector(9 downto 0);
+		dataerrors              : out std_logic_vector(9 downto 0)
+		);
+end component;
+
+component posedge_to_pulse is
+	port (
+		clock_in                : in  std_logic;
+		clock_out               : in  std_logic;
+		en_clk                  : in  std_logic;
+		signal_in               : in  std_logic;
+		pulse                   : out std_logic);
+end component;
+
+constant zeros : std_logic_vector(0 to NROFADCS/(ADCINDEXSHIFT+1)-1) := (others => '0');
+signal reset_packetclock_S              : std_logic := '0';
+signal reset_slowcontrolclock_S         : std_logic := '0';
+
+signal boardnumber_S                    : std_logic_vector (15 downto 0) := (others => '0');
+signal init_FEE_registers_S             : std_logic := '0';
+signal request_init_FEE_registers_S     : std_logic;
+signal cmd_init_FEE_registers_S         : std_logic := '0';
+
+signal slowcontrol_tx_data_S            : std_logic_vector (31 downto 0) := (others => '0');
+signal slowcontrol_tx_address_S         : std_logic_vector (23 downto 0) := (others => '0');
+signal slowcontrol_tx_request_S         : std_logic := '0';
+signal slowcontrol_tx_write_S           : std_logic := '0';
+signal slowcontrol_tx_write_checked_S   : std_logic := '0';
+signal slowcontrol_tx_fifofull_S        : std_logic := '0';
+signal slowcontrol_tx_allowed_S         : std_logic := '0';
+signal slowcontrol_tx_error_S           : std_logic := '0';
+signal slowcontrol_tx_error_async_S     : std_logic := '0';
+
+signal slowcontrol_to_cpu_data_S        : std_logic_vector (31 downto 0) := (others => '0');
+signal slowcontrol_to_cpu_address_S     : std_logic_vector (23 downto 0) := (others => '0');
+signal slowcontrol_to_cpu_reply_S       : std_logic := '0';
+signal slowcontrol_to_cpu_write_S       : std_logic := '0';
+signal slowcontrol_to_cpu_error_S       : std_logic := '0';
+signal slowcontrol_to_cpu_error_async_S : std_logic := '0';
+
+signal slowcontrol_rx_data_S            : std_logic_vector (31 downto 0) := (others => '0');
+signal slowcontrol_rx_address_S         : std_logic_vector (7 downto 0) := (others => '0');
+signal slowcontrol_rx_reply_S           : std_logic := '0';
+signal slowcontrol_rx_write_S           : std_logic := '0';
+signal slowcontrol_tx_enable_S          : std_logic := '0';
+
+signal slowcontrol_insert_data_S        : std_logic_vector (31 downto 0) := (others => '0');
+signal slowcontrol_insert_address_S     : std_logic_vector (23 downto 0) := (others => '0');
+signal slowcontrol_insert_reply_S       : std_logic := '0';
+signal slowcontrol_insert_write_S       : std_logic := '0';
+
+signal IO_serialdata_S                  : std_logic := '0';
+signal IO_serialavailable_S             : std_logic := '0';
+
+
+signal MUX_Read_enable_S                : std_logic := '0';
+signal rxAsyncDataRead_S                : std_logic := '0';
+signal fiber_data_error_S               : std_logic := '0';
+signal fiber_data_error_async_S         : std_logic := '0';
+
+signal rxNotInTable_S                   : std_logic := '0';
+
+signal pulse_skipped_counter_S          : std_logic_vector (7 downto 0) := (others => '0');
+signal prev_pulse_skipped_S             : std_logic := '0';
+
+signal pulse_data_write_S               : std_logic := '0';
+signal pulse_data_out_S                 : std_logic_vector (35 downto 0) := (others => '0');
+
+signal pulse_data_skipped_S             : std_logic := '0';
+signal pulse_data_skipped_delayed_S     : std_logic := '0';
+signal prev_pulse_data_skipped_S        : std_logic := '0';
+signal prev_slowcontrol_tx_error_S      : std_logic := '0';
+signal prev_slowcontrol_to_cpu_error_S  : std_logic := '0';
+signal prev_fiber_data_error_S          : std_logic := '0';
+signal prev_rxNotInTable_S              : std_logic := '0';
+
+
+signal request_boardnumber_S            : std_logic := '0';
+signal request_boardnumber_async_S      : std_logic := '0';
+signal prev_request_boardnumber_S       : std_logic := '0';
+
+signal request_status_S                 : std_logic := '0';
+signal request_status_async_S           : std_logic := '0';
+signal prev_request_status_S            : std_logic := '0';
+
+signal request_muxstat_S                : std_logic := '0';
+signal request_muxstat_async_S          : std_logic := '0';
+signal prev_request_muxstat_S           : std_logic := '0';
+
+signal request_measurefrequency_S       : std_logic := '0';
+signal request_measurefrequency_async_S : std_logic := '0';
+signal prev_request_measurefrequency_S  : std_logic := '0';
+
+signal request_timestamperrors_S        : std_logic := '0';
+signal request_timestamperrors_async_S  : std_logic := '0';
+signal prev_request_timestamperrors_S   : std_logic := '0';
+
+signal clear_errors_async_S             : std_logic := '0';
+signal clear_errors_S                   : std_logic := '0';
+
+signal muxstat_infifo_fullness_S        : std_logic_vector(15 downto 0) := (others => '0');
+signal muxstat_outfifo_fullness_S       : std_logic_vector(15 downto 0) := (others => '0');
+
+signal pulse_S                          : std_logic := '0';
+signal measurefrequency_S               : std_logic_vector(31 downto 0) := (others => '0');
+signal measurefrequency_sync_S          : std_logic_vector(31 downto 0) := (others => '0');
+
+signal txAsyncData_S                    : std_logic_vector(31 downto 0) := (others => '0');
+signal txAsyncDataWrite_S               : std_logic := '0';
+signal txEndOfAsyncData_S               : std_logic := '0';
+
+signal LUT_data_in_S                    : std_logic_vector(CF_FRACTIONBIT-1 downto 0);
+signal max_LUT_offset_S                 : std_logic_vector(MAX_LUTSIZEBITS-1 downto 0);
+signal max_correction_S                 : std_logic := '0';
+signal max_LUT_loading_S                : std_logic := '0';
+signal max_LUT_write_S                  : std_logic;
+signal fraction_correction_S            : std_logic := '0';
+signal fraction_LUT_loading_S           : std_logic := '0';
+signal fraction_LUT_write_S             : std_logic;
+
+signal timeshiftLUT_write_S             : std_logic := '0';
+signal timeshiftLUT_loading_S           : std_logic := '0';
+signal energyLUT_write_S                : std_logic := '0';
+signal energyLUT_loading_S              : std_logic := '0';
+
+signal timestamperrors_S                : std_logic_vector(9 downto 0) := (others => '0');
+signal timestamperrors_sync_S           : std_logic_vector(9 downto 0) := (others => '0');
+signal skipped_pulses_S                 : std_logic_vector(9 downto 0) := (others => '0');
+signal skipped_pulses_sync_S            : std_logic_vector(9 downto 0) := (others => '0');
+signal dataerrors_S                     : std_logic_vector(9 downto 0) := (others => '0');
+signal dataerrors_sync_S                : std_logic_vector(9 downto 0) := (others => '0');
+
+
+begin
+
+IO_serialdata <= IO_serialdata_S;
+IO_serialavailable <= IO_serialavailable_S;
+
+DC_slowcontrol_receive_from_cpu1: DC_slowcontrol_receive_from_cpu port map(
+		clock => slowcontrol_clock,
+		reset => reset_slowcontrolclock_S,
+		channel => channel,
+		IO_byte => IO_byte,
+		IO_write => IO_write,
+		slowcontrol_data => slowcontrol_tx_data_S,
+		slowcontrol_address => slowcontrol_tx_address_S,
+		slowcontrol_request => slowcontrol_tx_request_S,
+		slowcontrol_write => slowcontrol_tx_write_S,
+		slowcontrol_fifofull => slowcontrol_tx_fifofull_S,
+		error => slowcontrol_tx_error_async_S);
+slowcontrol_tx_fifofull_S <= '1' when slowcontrol_tx_allowed_S <= '0' else '0';
+
+DC_slowcontrol_packetbuilder1: DC_slowcontrol_packetbuilder port map(
+		clock => slowcontrol_clock,
+		reset => reset_slowcontrolclock_S,
+		init_FEE => init_FEE_registers_S,
+		slowcontrol_data => slowcontrol_tx_data_S,
+		slowcontrol_address => slowcontrol_tx_address_S,
+		slowcontrol_request => slowcontrol_tx_request_S,
+		slowcontrol_write => slowcontrol_tx_write_checked_S,
+		slowcontrol_allowed => slowcontrol_tx_allowed_S,
+		packet_data_out => txAsyncData_S,
+		packet_lastword => txEndOfAsyncData_S,
+		packet_datawrite => txAsyncDataWrite_S,
+		packet_fifofull => txAsyncFifoFull);
+txAsyncData <= txAsyncData_S;
+txEndOfAsyncData <= txEndOfAsyncData_S;
+txAsyncDataWrite <= txAsyncDataWrite_S;
+slowcontrol_tx_write_checked_S <= '1' when 
+	(slowcontrol_tx_address_S(23)='0') and (slowcontrol_tx_enable_S='1') and
+	(slowcontrol_tx_write_S='1') else '0';
+
+request_init_FEE_registers_S <= '1' when 
+		((slowcontrol_rx_address_S=ADDRESS_FEE_REQUESTALLREGISTERS) and 
+		(slowcontrol_rx_reply_S='1') and 
+		(slowcontrol_rx_write_S='1')) or
+		(cmd_init_FEE_registers_S='1')
+	else '0';
+	
+sinc_initFEE1: posedge_to_pulse port map(
+	clock_in => packet_clock,
+	clock_out => slowcontrol_clock,
+	en_clk => '1',
+	signal_in => request_init_FEE_registers_S,
+	pulse => init_FEE_registers_S);
+
+
+process(slowcontrol_clock)
+begin
+	if rising_edge(slowcontrol_clock) then
+		if reset_slowcontrolclock_S='1' then
+			slowcontrol_tx_enable_S <= '0';
+		else
+			if (resetDone='1') and (txLocked='1') then
+				slowcontrol_tx_enable_S <= '1';
+			else
+				slowcontrol_tx_enable_S <= '0';
+			end if;
+		end if;
+		reset_slowcontrolclock_S <= reset;
+	end if;
+end process;
+
+DC_slowcontrol_to_serial1: DC_slowcontrol_to_serial port map(
+		write_clock => packet_clock,
+		read_clock => slowcontrol_clock,
+		reset => reset_packetclock_S,
+		channel => channel,
+		slowcontrol_data => slowcontrol_to_cpu_data_S,
+		slowcontrol_address => slowcontrol_to_cpu_address_S,
+		slowcontrol_reply => slowcontrol_to_cpu_reply_S,
+		slowcontrol_write => slowcontrol_to_cpu_write_S,
+		IO_byte => IO_byte,
+		IO_write => IO_write,
+		IO_serialdata => IO_serialdata_S,
+		IO_serialavailable => IO_serialavailable_S,
+		error => slowcontrol_to_cpu_error_async_S);
+		
+
+slowcontrol_to_cpu_data_S <= slowcontrol_rx_data_S 
+	when (slowcontrol_rx_write_S='1') and (slowcontrol_insert_write_S='0') else 
+	slowcontrol_insert_data_S;
+		
+slowcontrol_to_cpu_address_S <= x"0000" & slowcontrol_rx_address_S 
+	when (slowcontrol_rx_write_S='1') and (slowcontrol_insert_write_S='0') else 
+	slowcontrol_insert_address_S;
+		
+slowcontrol_to_cpu_reply_S <= slowcontrol_rx_reply_S 
+	when (slowcontrol_rx_write_S='1') and (slowcontrol_insert_write_S='0') else 
+	slowcontrol_insert_reply_S;
+		
+slowcontrol_to_cpu_write_S <= '1' 
+	when (slowcontrol_rx_write_S='1') or (slowcontrol_insert_write_S='1') else 
+	'0';
+
+sync_muxstat1: synchronize_to_other_clock 
+    generic map (
+        DATA_WIDTH => 16
+    )
+	port map(
+		data_in_clock => MUX_clock,
+		data_in => muxstat_infifo_fullness,
+		data_out_clock => packet_clock,
+		data_out => muxstat_infifo_fullness_S);
+		
+--sync_measurefrequency: synchronize_to_other_clock 
+--	generic map ( DATA_WIDTH => 32 )
+--	port map(
+--		data_in_clock => packet_clock,
+--		data_in => measurefrequency_S,
+--		data_out_clock => packet_clock,
+--		data_out => measurefrequency_sync_S);
+measurefrequency_sync_S <= measurefrequency_S;
+
+sync_muxstat2: synchronize_to_other_clock 
+    generic map (
+        DATA_WIDTH => 16
+    )
+	port map(
+		data_in_clock => MUX_clock,
+		data_in => muxstat_outfifo_fullness,
+		data_out_clock => packet_clock,
+		data_out => muxstat_outfifo_fullness_S);
+
+timestamperrors_S <= timestamp_errors;
+sync_timestamperrors: synchronize_to_other_clock 
+    generic map (
+        DATA_WIDTH => 10
+    )
+	port map(
+		data_in_clock => packet_clock,
+		data_in => timestamperrors_S,
+		data_out_clock => slowcontrol_clock,
+		data_out => timestamperrors_sync_S);
+
+skipped_pulses_S <= skipped_pulses;
+sync_skipped_pulses: synchronize_to_other_clock 
+    generic map (
+        DATA_WIDTH => 10
+    )
+	port map(
+		data_in_clock => packet_clock,
+		data_in => skipped_pulses_S,
+		data_out_clock => slowcontrol_clock,
+		data_out => skipped_pulses_sync_S);
+
+dataerrors_S <= dataerrors;
+sync_dataerrors: synchronize_to_other_clock 
+	generic map ( DATA_WIDTH => 10 )
+	port map(
+		data_in_clock => packet_clock,
+		data_in => dataerrors_S,
+		data_out_clock => slowcontrol_clock,
+		data_out => dataerrors_sync_S);
+
+
+
+process(packet_clock)
+begin
+	if rising_edge(packet_clock) then
+		if (rxLocked='1') and (resetDone='1') then
+			MUX_Read_enable_S <= '1';
+		else 
+			MUX_Read_enable_S <= '0';
+		end if;
+	end if;
+end process;
+
+
+rxAsyncClk <= packet_clock;
+pulse_data_out <= pulse_data_out_S;
+pulse_data_write <= pulse_data_write_S;
+DC_separate_data1: DC_separate_data port map(
+		clock => packet_clock,
+		load_clock => slowcontrol_clock,
+		SODA_clock => SODA_clock,
+		reset => reset_packetclock_S,
+		enable => MUX_Read_enable_S,
+		max_correction => max_correction_S,
+		max_LUT_offset => max_LUT_offset_S,
+		max_LUT_loading => max_LUT_loading_S,
+		max_LUT_write => max_LUT_write_S,
+		fraction_correction => fraction_correction_S,
+		fraction_LUT_loading => fraction_LUT_loading_S,
+		fraction_LUT_write => fraction_LUT_write_S,
+		LUT_data_in => LUT_data_in_S,
+		timeshiftLUT_write => timeshiftLUT_write_S,
+		timeshiftLUT_loading => timeshiftLUT_loading_S,
+		timeshiftLUT_data => slowcontrol_tx_data_S(30 downto 0),
+		energyLUT_write => energyLUT_write_S,
+		energytLUT_loading => energyLUT_loading_S,
+		energyLUT_data => slowcontrol_tx_data_S(30 downto 0),
+		packet_data_in => rxAsyncData,
+		packet_data_present => rxAsyncDataPresent,
+		packet_data_read => rxAsyncDataRead_S,
+		pulse_data_out => pulse_data_out_S,
+		pulse_data_write => pulse_data_write_S,
+		pulse_data_out_allowed => pulse_data_out_allowed,
+		slowcontrol_data => slowcontrol_rx_data_S,
+		slowcontrol_address => slowcontrol_rx_address_S,
+		slowcontrol_reply => slowcontrol_rx_reply_S,
+		slowcontrol_write => slowcontrol_rx_write_S,	  
+		wave_data_out => wave_data_out,
+		wave_data_write => wave_data_write,
+		wave_data_out_allowed => wave_data_out_allowed,
+		FEEboardnumber => boardnumber_S,
+		superburst_number => superburst_number,
+		superburst_update => superburst_update,
+		error => fiber_data_error_async_S,
+		pulse_data_skipped => pulse_data_skipped_S,
+		testword0 => testword1);
+rxAsyncDataRead <= rxAsyncDataRead_S;
+	 
+slowcontrol_check_process: process(slowcontrol_clock)
+variable clear_errors_V : std_logic := '0';
+begin
+	if rising_edge(slowcontrol_clock) then
+		timeshiftLUT_write_S <= '0';
+		fraction_LUT_write_S <= '0';
+		energyLUT_write_S <= '0';
+		max_LUT_write_S <= '0';
+		cmd_init_FEE_registers_S <= '0';
+		if reset_slowcontrolclock_S='1' then
+			request_boardnumber_async_S <= '0';
+			request_status_async_S <= '0';
+			request_muxstat_async_S <= '0';
+			request_timestamperrors_async_S <= '0';
+			request_measurefrequency_async_S <= '0';
+			clear_errors_V := '0';
+		else
+			if (slowcontrol_tx_write_S='1') and 
+					(slowcontrol_tx_address_S=ADDRESS_BOARDNUMBER) and 
+					(slowcontrol_tx_request_S='0') then
+				boardnumber_S <= slowcontrol_tx_data_S(11 downto 0) & "0000";
+				cmd_init_FEE_registers_S <= slowcontrol_tx_data_S(31);
+			elsif (slowcontrol_tx_write_S='1') and 
+					(slowcontrol_tx_address_S=ADDRESS_BOARDNUMBER) and 
+					(slowcontrol_tx_request_S='1') then
+				request_boardnumber_async_S <= '1';
+			elsif (slowcontrol_tx_write_S='1') and 
+					(slowcontrol_tx_address_S=ADDRESS_MUX_FIBERMODULE_STATUS) then
+				if (slowcontrol_tx_request_S='1') then
+					request_status_async_S <= '1';
+				else
+					clear_errors_async_S <= '1';
+				end if;
+			elsif (slowcontrol_tx_write_S='1') and 
+					(slowcontrol_tx_address_S=ADDRESS_MUX_MAXCFLUTS) and 
+					(slowcontrol_tx_request_S='0') then
+				LUT_data_in_S <= slowcontrol_tx_data_S(CF_FRACTIONBIT-1 downto 0);
+				if slowcontrol_tx_data_S(26)='1' then 
+					max_LUT_write_S <= '1';
+				end if;
+				max_LUT_loading_S <= slowcontrol_tx_data_S(27);
+				max_correction_S <= slowcontrol_tx_data_S(28);
+				max_LUT_offset_S <= slowcontrol_tx_data_S(MAX_LUTSIZEBITS+15 downto 16);
+				if slowcontrol_tx_data_S(29)='1' then 
+					fraction_LUT_write_S <= '1';
+				end if;
+				fraction_LUT_loading_S <= slowcontrol_tx_data_S(30);
+				fraction_correction_S <= slowcontrol_tx_data_S(31);
+			elsif (slowcontrol_tx_write_S='1') and 
+					(slowcontrol_tx_address_S=ADDRESS_MUX_MULTIPLEXER_STATUS) and 
+					(slowcontrol_tx_request_S='1') then
+				request_muxstat_async_S <= '1';
+			elsif (slowcontrol_tx_write_S='1') and 
+					(slowcontrol_tx_address_S=ADDRESS_FEE_MEASURE_FREQUENCY) and 
+					(slowcontrol_tx_request_S='1') then
+				request_measurefrequency_async_S <= '1';
+			elsif (slowcontrol_tx_write_S='1') and 
+					(slowcontrol_tx_address_S=ADDRESS_MUX_TIMESTAMP_ERRORS) and 
+					(slowcontrol_tx_request_S='1') then
+				request_timestamperrors_async_S <= '1';
+			elsif (slowcontrol_tx_write_S='1') and 
+					(slowcontrol_tx_address_S=ADDRESS_MUX_TIMESHIFT) and 
+					(slowcontrol_tx_request_S='0') then
+				timeshiftLUT_loading_S <= slowcontrol_tx_data_S(31);
+				if (slowcontrol_tx_data_S(31)='1') and (timeshiftLUT_loading_S='1') then
+					timeshiftLUT_write_S <= '1';
+				end if;
+			elsif (slowcontrol_tx_write_S='1') and 
+					(slowcontrol_tx_address_S=ADDRESS_MUX_ENERGYCORRECTION) and 
+					(slowcontrol_tx_request_S='0') then
+				energyLUT_loading_S <= slowcontrol_tx_data_S(31);
+				if (slowcontrol_tx_data_S(31)='1') and (energyLUT_loading_S='1') then
+					energyLUT_write_S <= '1';
+				end if;
+			else
+				if request_boardnumber_S='1' then
+					request_boardnumber_async_S <= '0';
+				end if;
+				if request_status_S='1' then 
+					request_status_async_S <= '0';
+				end if;
+				if request_muxstat_S='1' then 
+					request_muxstat_async_S <= '0';
+				end if;
+				if request_measurefrequency_S='1' then 
+					request_measurefrequency_async_S <= '0';
+				end if;
+				if request_timestamperrors_S='1' then 
+					request_timestamperrors_async_S <= '0';
+				end if;
+			end if;
+			if clear_errors_V='1' then
+				clear_errors_async_S <= '0';
+			end if;
+			clear_errors_V := clear_errors_S;
+		end if;
+	end if;
+end process;
+
+pulse_skip_process: process(packet_clock)
+begin
+	if rising_edge(packet_clock) then
+		if (reset_packetclock_S='1') or (clear_errors_S='1') then
+			pulse_skipped_counter_S <= (others => '0');
+			prev_pulse_skipped_S <= '0';
+		else
+			if (pulse_data_skipped_S='1') and (prev_pulse_skipped_S='0') then
+				if pulse_skipped_counter_S/=x"ff" then
+					pulse_skipped_counter_S <= pulse_skipped_counter_S+1;
+				end if;
+			end if;
+			prev_pulse_skipped_S <= pulse_data_skipped_S;
+		end if;
+		reset_packetclock_S <= reset;
+	end if;
+end process;
+
+
+slowcontrol_insert_process: process(packet_clock)
+variable send_boardnumber_V               : std_logic := '0';
+variable send_error_V                     : std_logic := '0';
+variable send_muxstat_V                   : std_logic := '0';
+variable send_measurefrequency_V          : std_logic := '0';
+variable send_timestamperrors_V           : std_logic := '0';
+variable pulse_data_skipped_sent_V        : std_logic := '0';
+variable slowcontrol_tx_error_sent_V      : std_logic := '0';
+variable slowcontrol_to_cpu_error_sent_V  : std_logic := '0';
+variable fiber_data_error_sent_V          : std_logic := '0';
+variable rxNotInTable_sent_V              : std_logic := '0';
+variable request_boardnumber_sent_V       : std_logic := '0';
+variable request_status_sent_V            : std_logic := '0';
+variable request_muxstat_sent_V           : std_logic := '0';
+variable request_measurefrequency_sent_V  : std_logic := '0';
+variable request_timestamperrors_sent_V   : std_logic := '0';
+begin
+	if rising_edge(packet_clock) then
+		if (slowcontrol_insert_write_S='1') and (slowcontrol_rx_write_S='1') then -- unsuccessful write
+			slowcontrol_insert_write_S <= '1';
+		else
+			send_error_V := '0';
+			if (pulse_data_skipped_delayed_S='1') and (prev_pulse_data_skipped_S='0') and (pulse_data_skipped_sent_V='0') then
+				pulse_data_skipped_sent_V := '1';
+				send_error_V := '1';
+			end if;
+			if (slowcontrol_tx_error_S='1') and (prev_slowcontrol_tx_error_S='0') and (slowcontrol_tx_error_sent_V='0') then
+				slowcontrol_tx_error_sent_V := '1';
+				send_error_V := '1';
+			end if;
+			if (slowcontrol_to_cpu_error_S='1') and (prev_slowcontrol_to_cpu_error_S='0') and (slowcontrol_to_cpu_error_sent_V='0') then
+				slowcontrol_to_cpu_error_sent_V := '1';
+				send_error_V := '1';
+			end if;
+			if (fiber_data_error_S='1') and (prev_fiber_data_error_S='0') and (fiber_data_error_sent_V='0') then
+				fiber_data_error_sent_V := '1';
+				send_error_V := '1';
+			end if;
+			if (rxNotInTable_S='1') and (prev_rxNotInTable_S='0') and (rxNotInTable_sent_V='0') then
+				rxNotInTable_sent_V := '1';
+				send_error_V := '1';
+			end if;
+			if (request_boardnumber_S='1') and (prev_request_boardnumber_S='0') and (request_boardnumber_sent_V='0') then
+				request_boardnumber_sent_V := '1';
+				send_boardnumber_V := '1';
+			end if;
+			if (request_status_S='1') and (prev_request_status_S='0') and (request_status_sent_V='0') then
+				request_status_sent_V := '1';
+				send_error_V := '1';
+			end if;
+			if (request_muxstat_S='1') and (prev_request_muxstat_S='0') and (request_muxstat_sent_V='0') then
+				request_muxstat_sent_V := '1';
+				send_muxstat_V := '1';
+			end if;
+			if (request_measurefrequency_S='1') and (prev_request_measurefrequency_S='0') and (request_measurefrequency_sent_V='0') then
+				request_measurefrequency_sent_V := '1';
+				send_measurefrequency_V := '1';
+			end if;
+			if (request_timestamperrors_S='1') and (prev_request_timestamperrors_S='0') and (request_timestamperrors_sent_V='0') then
+				request_timestamperrors_sent_V := '1';
+				send_timestamperrors_V := '1';
+			end if;				
+			if send_error_V='1' then			
+				slowcontrol_insert_data_S(0) <= slowcontrol_to_cpu_error_sent_V;
+				slowcontrol_insert_data_S(1) <= slowcontrol_tx_error_sent_V;
+				slowcontrol_insert_data_S(2) <= fiber_data_error_sent_V;
+				slowcontrol_insert_data_S(3) <= rxNotInTable_sent_V;
+				slowcontrol_insert_data_S(4) <= pulse_data_skipped_sent_V;
+				slowcontrol_insert_data_S(5) <= rxLocked;					
+				slowcontrol_insert_data_S(7 downto 6) <= (others => '0');
+				slowcontrol_insert_data_S(15 downto 8) <= pulse_skipped_counter_S;
+				slowcontrol_insert_data_S(31 downto 16) <= (others => '0');
+				slowcontrol_insert_address_S <= ADDRESS_MUX_FIBERMODULE_STATUS;
+				slowcontrol_insert_reply_S <= request_status_S or request_status_sent_V;
+				slowcontrol_insert_write_S <= '1';
+				request_status_sent_V := '0';
+			elsif send_boardnumber_V='1' then
+				slowcontrol_insert_data_S(31 downto 12) <= (others => '0');
+				slowcontrol_insert_data_S(11 downto 0) <= boardnumber_S(15 downto 4);
+				slowcontrol_insert_address_S <= ADDRESS_BOARDNUMBER;
+				slowcontrol_insert_reply_S <= '1';
+				slowcontrol_insert_write_S <= '1';				
+				request_boardnumber_sent_V := '0';
+				send_boardnumber_V := '0';
+			elsif send_muxstat_V='1' then			
+				slowcontrol_insert_data_S(31 downto 16) <= muxstat_outfifo_fullness_S;
+				slowcontrol_insert_data_S(15 downto 0) <= muxstat_infifo_fullness_S;
+				slowcontrol_insert_address_S <= ADDRESS_MUX_MULTIPLEXER_STATUS;
+				slowcontrol_insert_reply_S <= '1';
+				slowcontrol_insert_write_S <= '1';				
+				request_muxstat_sent_V := '0';
+				send_muxstat_V := '0';
+			elsif send_measurefrequency_V='1' then			
+				slowcontrol_insert_data_S(31 downto 0) <= measurefrequency_sync_S;
+				slowcontrol_insert_address_S <= x"0000" & ADDRESS_FEE_MEASURE_FREQUENCY;
+				slowcontrol_insert_reply_S <= '1';
+				slowcontrol_insert_write_S <= '1';				
+				request_measurefrequency_sent_V := '0';
+				send_measurefrequency_V := '0';
+			elsif send_timestamperrors_V='1' then			
+				slowcontrol_insert_data_S(31 downto 0) <= "00" & dataerrors_sync_S & skipped_pulses_sync_S & timestamperrors_sync_S;
+				slowcontrol_insert_address_S <= ADDRESS_MUX_TIMESTAMP_ERRORS;
+				slowcontrol_insert_reply_S <= '1';
+				slowcontrol_insert_write_S <= '1';				
+				request_timestamperrors_sent_V := '0';					
+				send_timestamperrors_V := '0';
+			else
+				slowcontrol_insert_write_S <= '0';
+				if clear_errors_S='1' then
+					slowcontrol_to_cpu_error_sent_V := '0';
+					slowcontrol_tx_error_sent_V := '0';
+					fiber_data_error_sent_V := '0';
+					rxNotInTable_sent_V := '0';
+					pulse_data_skipped_sent_V := '0';
+				end if;
+			end if;
+			request_boardnumber_S <= request_boardnumber_async_S;
+			request_status_S <= request_status_async_S;
+			request_muxstat_S <= request_muxstat_async_S;
+			request_measurefrequency_S <= request_measurefrequency_async_S;
+			request_timestamperrors_S <= request_timestamperrors_async_S;
+			slowcontrol_tx_error_S <= slowcontrol_tx_error_async_S;
+			slowcontrol_to_cpu_error_S <= slowcontrol_to_cpu_error_async_S;
+			fiber_data_error_S <= fiber_data_error_async_S;
+			
+			prev_slowcontrol_to_cpu_error_S <= slowcontrol_to_cpu_error_S;
+			prev_pulse_data_skipped_S <= pulse_data_skipped_delayed_S;
+			pulse_data_skipped_delayed_S <= pulse_data_skipped_S; -- delay one clock cycle to allow the proper count-value to be sent
+			prev_slowcontrol_tx_error_S <= slowcontrol_tx_error_S;
+			prev_fiber_data_error_S <= fiber_data_error_S;
+			prev_rxNotInTable_S <= rxNotInTable_S;
+			prev_request_boardnumber_S <= request_boardnumber_S;
+			prev_request_status_S <= request_status_S;
+			prev_request_muxstat_S <= request_muxstat_S;
+			prev_request_measurefrequency_S <= request_measurefrequency_S;
+			prev_request_timestamperrors_S <= request_timestamperrors_S;
+			clear_errors_S <= clear_errors_async_S;
+		end if;
+		rxNotInTable_S <= rxNotInTable;
+	end if;
+end process;
+
+DC_measure_frequency1: DC_measure_frequency port map(
+		clock => packet_clock,
+		pulse => pulse_S,
+		frequency => measurefrequency_S);
+pulse_S  <= '1' when (pulse_data_write_S='1') and (pulse_data_out_allowed='1') and (pulse_data_out_S(33 downto 32)="11") else '0';
+
+
+--MUX_check_timestamp1: MUX_check_timestamp port map(
+--		clock => packet_clock,
+--		reset => reset_packetclock_S,
+--		clear => clear_errors_S,
+--		pulse_data => pulse_data_out_S,
+--		pulse_data_write => MUX_check_pulse_data_write_S,
+--		timestamp_errors => timestamperrors_S,
+--		skipped_pulses => skipped_pulses_S,
+--		dataerrors => dataerrors_S);
+----MUX_check_pulse_data_write_S <= '1' when (pulse_data_write_S='1') and (pulse_data_out_allowed='1') else '0';
+
+
+		
+testword0(31 downto 0) <= rxAsyncData;
+testword0(32) <= rxAsyncDataPresent;
+testword0(33) <= rxAsyncDataRead_S;
+testword0(34) <= MUX_Read_enable_S;
+testword0(35) <= wave_data_out_allowed;
+
+
+
+end Behavioral;
diff --git a/data_concentrator/sources/DC_fifo32to8_SODA.vhd b/data_concentrator/sources/DC_fifo32to8_SODA.vhd
new file mode 100644
index 0000000..28af48c
--- /dev/null
+++ b/data_concentrator/sources/DC_fifo32to8_SODA.vhd
@@ -0,0 +1,195 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   19-11-2014
+-- Module Name:   DC_fifo32to8_SODA
+-- Description:   FIFO with 32 bits to 8 bits conversion and SODA
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+library work;
+use work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- DC_fifo32to8_SODA
+-- FIFO with 32 bits to 8 bits conversion and additional K-character
+-- Data is written in asynchronous 32-bits fifo
+-- After reading the data is splitted in bytes.
+-- If no data is available an Idle is put on the output (BC and the K-character signal).
+-- SODA signals (DLM) are passed on directly (highest priority).
+--
+-- Library
+--     work.gtpBufLayer : for GTP/GTX/serdes constants
+--
+-- Generics:
+-- 
+-- Inputs:
+--     write_clock : clock for the 32-bits input data
+--     read_clock : clock for the 16-bits output data
+--     reset : reset
+--     data_in : 32-bits input data
+--     data_write : write signal for 32-bits input data
+--     TX_DLM : transmit SODA character
+--     TX_DLM_WORD : SODA character to be transmitted
+-- 
+-- Outputs:
+--     data_out : 16-bits output data
+--     char_is_k : corresponding byte in 16-bits output data is K-character
+-- 
+-- Components:
+--     async_fifo_512x32 : 32-bits asynchronous fifo
+--
+----------------------------------------------------------------------------------
+
+
+entity DC_fifo32to8_SODA is
+	port ( 
+		write_clock             : in std_logic;
+		read_clock              : in std_logic;
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(31 downto 0);
+		data_write              : in std_logic;
+		full                    : out std_logic;
+		TX_DLM                  : in std_logic;
+		TX_DLM_WORD             : in std_logic_vector(7 downto 0);
+		data_out                : out std_logic_vector(7 downto 0);
+		char_is_k               : out std_logic
+	);
+end DC_fifo32to8_SODA;
+
+architecture Behavioral of DC_fifo32to8_SODA is
+
+component async_fifo_512x32
+	port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(31 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(31 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic);
+end component;
+
+signal fifo_read_S              : std_logic;
+signal fifo_dataout_S           : std_logic_vector(31 downto 0);
+signal fifo_databuf_S           : std_logic_vector(31 downto 0);
+signal data_out_S               : std_logic_vector(7 downto 0);
+signal char_is_k_S              : std_logic;
+signal fifo_empty_S             : std_logic;
+signal prev_fifo_empty_S        : std_logic;
+
+signal fifo_buffilled_S         : std_logic := '0';
+signal fifo_read_after1clk_S    : std_logic := '0';
+signal TX_DLM_S                 : std_logic;
+signal TX_DLM_WORD_S            : std_logic_vector(7 downto 0);
+signal bytecounter_S            : integer range 0 to 3 := 0;
+signal write_data_S             : std_logic;
+signal lastbytefilled_S         : std_logic;
+signal lastbyte_S               : std_logic_vector(7 downto 0);
+
+
+begin
+
+process (read_clock)
+begin
+	if rising_edge(read_clock) then
+		data_out <= data_out_S;
+		char_is_k <= char_is_k_S;
+	end if;
+end process;
+
+	
+fifo: async_fifo_512x32 port map(
+		rst => reset,
+		wr_clk => write_clock,
+		rd_clk => read_clock,
+		din => data_in,
+		wr_en => data_write, 
+		rd_en => fifo_read_S,
+		dout => fifo_dataout_S,
+		full => full,
+		empty => fifo_empty_S);
+
+fifo_read_S <= '1' when (fifo_empty_S='0') and (TX_DLM='0') and (fifo_read_after1clk_S='0') and (lastbytefilled_S='0')
+		and (((bytecounter_S=0)  and (fifo_buffilled_S='0')) or ((bytecounter_S=3) and (fifo_buffilled_S='0')))
+	else '0';
+	
+data_out_S <= 
+	KCHARSODA when TX_DLM='1' else
+	TX_DLM_WORD_S when (TX_DLM_S='1') else
+	KCHAR285 when (write_data_S='0') else
+	lastbyte_S when (lastbytefilled_S='1') else
+	fifo_dataout_S(31 downto 24) when (fifo_read_after1clk_S='1') else
+	fifo_databuf_S((3-bytecounter_S)*8+7 downto (3-bytecounter_S)*8);
+	
+char_is_k_S <=
+	'1' when TX_DLM='1' else
+	'0' when (TX_DLM_S='1') else
+	'1' when (write_data_S='0') else
+	'0' when fifo_read_after1clk_S='1' else 
+	'0';
+
+write_data_S <= '1' when ((TX_DLM='0') and (TX_DLM_S='0')) and 
+	((fifo_read_after1clk_S='1') or (bytecounter_S/=0) or (fifo_buffilled_S='1') or (lastbytefilled_S='1')) else '0';
+
+tx_process : process (read_clock)
+begin
+	if rising_edge(read_clock) then
+		if reset='1' then
+			fifo_read_after1clk_S <= '0';
+			TX_DLM_S <= '0';
+			lastbytefilled_S <= '0';
+			bytecounter_S <= 0;
+		else
+			TX_DLM_S <= TX_DLM;
+			if TX_DLM='1' then
+				TX_DLM_WORD_S <= TX_DLM_WORD;
+			end if;
+			fifo_read_after1clk_S <= fifo_read_S;
+			prev_fifo_empty_S <= fifo_empty_S;
+			if not ((TX_DLM='1') or (TX_DLM_S='1') or (write_data_S='0')) then
+				lastbytefilled_S <= '0';
+			end if;
+			if (fifo_read_after1clk_S='1') then
+				if (TX_DLM='1') and (fifo_buffilled_S='0') and (bytecounter_S=3) then 
+					lastbytefilled_S <= '1';
+					lastbyte_S <= fifo_databuf_S(7 downto 0);
+				end if;
+				fifo_databuf_S <= fifo_dataout_S;
+				fifo_buffilled_S <= '1';
+			end if;	
+			if (TX_DLM='1') or (TX_DLM_S='1') then
+			elsif lastbytefilled_S='1' then
+				bytecounter_S <= 0;
+			else
+				case bytecounter_S is
+					when 0 =>
+						if (fifo_buffilled_S='1') or (fifo_read_after1clk_S='1') then
+							fifo_buffilled_S <= '1';
+							bytecounter_S <= 1;
+						end if;
+					when 1 =>
+						fifo_buffilled_S <= '1';
+						bytecounter_S <= 2;
+					when 2 =>
+						fifo_buffilled_S <= '0';
+						bytecounter_S <= 3;
+					when 3 =>
+						fifo_buffilled_S <= '0';
+						bytecounter_S <= 0;
+					when others =>
+						fifo_buffilled_S <= '0';
+						bytecounter_S <= 0;
+				end case;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+end Behavioral;
+
diff --git a/data_concentrator/sources/DC_fifo8to32_SODA.vhd b/data_concentrator/sources/DC_fifo8to32_SODA.vhd
new file mode 100644
index 0000000..fd75de7
--- /dev/null
+++ b/data_concentrator/sources/DC_fifo8to32_SODA.vhd
@@ -0,0 +1,155 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   19-11-2014
+-- Module Name:   DC_fifo8to32_SODA
+-- Description:   FIFO with 8 bits to 32 bits conversion and SODA
+-- Modifications:
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+library work;
+use work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- DC_fifo8to32_SODA
+-- FIFO with 8 bits to 32 bits conversion and SODA
+-- Byte data is converted to 32-bits, alignment is done with check on first word after idles
+-- The resulting 32-bits word is written in an asynchronous 32-bits fifo.
+-- SODA signals (DLM) are passed on directly (highest priority).
+--
+-- Library
+--     work.gtpBufLayer : for GTP/GTX/serdes constants
+--
+-- Generics:
+-- 
+-- Inputs:
+--     write_clock : clock for the 32-bits input data
+--     read_clock : clock for the 16-bits output data
+--     reset : reset
+--     data_in : 8-bits input data
+--     char_is_k : corresponding byte in 16-bits data input is K-character
+--     data_read : read signal for 32-bits output data
+-- 
+-- Outputs:
+--     RX_DLM : SODA character received
+--     RX_DLM_WORD : SODA character 
+--     data_out : 32-bits output data (asynchrounous)
+--     data_available : 32-bits output data available (fifo not empty)
+--     overflow : fifo overflow : data has been thrown away
+--     error : error in input data
+-- 
+-- Components:
+--     async_fifo_512x32 : 32-bits asynchronous fifo
+--
+----------------------------------------------------------------------------------
+
+
+entity DC_fifo8to32_SODA is
+	port ( 
+		write_clock             : in std_logic;
+		read_clock              : in std_logic;
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(7 downto 0);
+		char_is_k               : in std_logic;
+		RX_DLM                  : out std_logic;
+		RX_DLM_WORD             : out std_logic_vector(7 downto 0);
+		data_out                : out std_logic_vector(31 downto 0);
+		data_read               : in std_logic;
+		data_available          : out std_logic;
+		overflow                : out std_logic;
+		error                   : out std_logic		
+	);
+end DC_fifo8to32_SODA;
+
+architecture Behavioral of DC_fifo8to32_SODA is
+
+component async_fifo_512x32
+	port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(31 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(31 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic);
+end component;
+
+signal fifo_write_S             : std_logic;
+signal fifo_datain_S            : std_logic_vector(31 downto 0);
+signal fifo_full_S              : std_logic;
+signal fifo_empty_S             : std_logic;
+signal error_S                  : std_logic := '0';
+signal RX_DLM0_S                : std_logic := '0';
+signal RX_DLM_S                 : std_logic := '0';
+signal RX_DLM_WORD_S            : std_logic_vector(7 downto 0) := (others => '0');
+signal bytecounter_S            : integer range 0 to 3 := 0;
+
+begin
+
+error <= error_S;
+RX_DLM_WORD <= RX_DLM_WORD_S;
+RX_DLM <= RX_DLM_S;
+
+fifo: async_fifo_512x32 port map(
+		rst => reset,
+		wr_clk => write_clock,
+		rd_clk => read_clock,
+		din => fifo_datain_S,
+		wr_en => fifo_write_S, 
+		rd_en => data_read,
+		dout => data_out,
+		full => fifo_full_S,
+		empty => fifo_empty_S);
+data_available <= '1' when fifo_empty_S='0' else '0';
+
+overflow <= '1' when (fifo_write_S='1') and (fifo_full_S='1') else '0';
+
+rx_process : process(write_clock)
+variable idlecounter_V : integer range 0 to 4;
+begin
+	if rising_edge(write_clock) then
+		RX_DLM_S <= '0';
+		error_S <= '0';
+		fifo_write_S <= '0';
+		if reset='1' then
+			RX_DLM0_S <= '0';
+			bytecounter_S <= 0;
+			idlecounter_V := 0;
+		else
+			if (char_is_k='1') and (data_in=KCHARSODA) then
+				RX_DLM0_S <= '1';
+				error_S <= RX_DLM0_S; -- not 2 DLM after each other
+			elsif RX_DLM0_S='1' then
+				RX_DLM0_S <= '0';
+				RX_DLM_S <= '1';
+				RX_DLM_WORD_S <= data_in; 
+			elsif (char_is_k='1') then -- idle: ignore a few
+				if idlecounter_V<4 then
+					idlecounter_V := idlecounter_V+1;
+				else
+					bytecounter_S <= 0;
+				end if;
+			else -- data
+				idlecounter_V := 0;
+				fifo_datain_S(31 downto 24) <= fifo_datain_S(23 downto 16);
+				fifo_datain_S(23 downto 16) <= fifo_datain_S(15 downto 8);
+				fifo_datain_S(15 downto 8) <= fifo_datain_S(7 downto 0);
+				fifo_datain_S(7 downto 0) <= data_in;
+				if bytecounter_S=3 then
+					bytecounter_S <= 0;
+					fifo_write_S <= '1';
+				else
+					bytecounter_S <= bytecounter_S+1;
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+end Behavioral;
+
diff --git a/data_concentrator/sources/DC_histogram.vhd b/data_concentrator/sources/DC_histogram.vhd
new file mode 100644
index 0000000..16237bf
--- /dev/null
+++ b/data_concentrator/sources/DC_histogram.vhd
@@ -0,0 +1,274 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   05-03-2012
+-- Module Name:   DC_histogram
+-- Description:   Puts the results in a histogram
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- DC_histogram
+-- Module make a histogram of the energies of the results of one adc-channel.
+-- The input pulse data consists of the following items (parallel)
+--        channel : adc-index
+--        statusbyte : 8 bit status information
+--        energy : pulse energy
+--        timefraction : fraction part of the timestamp
+--        timestamp : 15 bits timestamp, synchronised to master SODA clock
+--        superburstnumber : 31 bits superburst number
+-- Only the energy from the data from the selected adcnumber (16 bits) is taken into account.
+--
+-- Library
+--     work.panda_package :  for type declarations and constants
+-- 
+-- Generics:
+--     HISTOGRAM_SIZEBITS : number of bits for the histogram x-axis, 2^HISTOGRAM_SIZEBITS=number of histogram channels
+-- 
+-- Inputs:
+--     write_clock : clock for incoming data
+--     read_clock : clock for outgoing data
+--     reset : reset of all components
+--     adcnumber : unique number of the adc
+--     clear : starts clearing the histogram
+--     binning : scale the histogram : 
+--            000 = no scaling
+--            001 = div 2
+--            010 = div 4
+--            011 = div 8
+--            100 = div 16
+--            101 = div 32
+--            110 = div 64
+--            111 = div 128
+--     pulse_data : 36 bits data with Feature Extraction Results, each 4*36-bits:
+--        word0 : 0 & 0000 & timestamp(15..0)
+--        word1 : 1 & 00 & superburstnumber(23..0)
+--        word2 : 2 & statusbyte & 00 & adcnumber
+--        word3 : 3 & timefraction & energy
+--     pulse_data_write : write signal for the pulse_data
+--     histogram_startreading : start reading the histogram data
+--     histogram_read : read signak for the histogram buffer fifo
+-- 
+-- Outputs:
+--     histogram_data : resulting histogram data: on every read the next value
+--     histogram_available : histogram_data available (not empty from fifo)
+-- 
+-- Components:
+--     histogram : Module for histogram 
+--     async_fifo_af_512x32 : fifo with almost_full for histogram data
+--
+----------------------------------------------------------------------------------
+
+entity DC_histogram is
+	generic (
+		HISTOGRAM_SIZEBITS : natural := 12
+	);
+	port ( 
+		write_clock             : in std_logic;
+		read_clock              : in std_logic;
+		reset                   : in std_logic;
+		testword0               : out std_logic_vector (35 downto 0);
+		adcnumber               : in std_logic_vector(15 downto 0);
+		clear                   : in std_logic;
+		binning                 : in std_logic_vector(2 downto 0);
+		channel                 : in std_logic_vector(15 downto 0);
+		statusbyte              : in std_logic_vector(7 downto 0);
+		energy                  : in std_logic_vector(15 downto 0);
+		timefraction            : in std_logic_vector(11 downto 0);
+		timestamp               : in std_logic_vector(15 downto 0);
+		superburstnumber        : in std_logic_vector(30 downto 0);		
+		pulse_data_write        : in std_logic;
+		histogram_startreading  : in std_logic;
+		histogram_data          : out std_logic_vector(31 downto 0);
+		histogram_read          : in std_logic;
+		histogram_available     : out std_logic		
+		);
+end DC_histogram;
+
+architecture Behavioral of DC_histogram is
+
+component histogram is
+	generic (
+		HISTOGRAM_SIZEBITS      : natural := HISTOGRAM_SIZEBITS;
+		rangebits  : natural    := 32
+		);
+	port (
+		clock                   : in std_logic;
+		clear                   : in std_logic;
+		datain                  : in std_logic_vector(HISTOGRAM_SIZEBITS-1 downto 0);
+		writerequest            : in std_logic;
+		address                 : in std_logic_vector(HISTOGRAM_SIZEBITS-1 downto 0);
+		readrequest             : in std_logic;
+		dataout                 : out std_logic_vector(rangebits-1 downto 0);
+		dataout_valid           : out std_logic
+		);
+end component;
+
+component async_fifo_af_512x32
+	port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(31 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(31 downto 0);
+		full                    : out std_logic;
+		almost_full             : out std_logic;
+		empty                   : out std_logic);
+end component;
+
+signal reset_writeclock_S     : std_logic := '0';
+signal clear_S                : std_logic := '0';
+signal pulsevalue_S           : std_logic_vector(HISTOGRAM_SIZEBITS-1 downto 0) := (others => '0');
+signal pulsevalue_write_S     : std_logic := '0';
+signal pulsevalue_address_S   : std_logic_vector(HISTOGRAM_SIZEBITS-1 downto 0) := (others => '0');
+signal histogram_read_S       : std_logic := '0';
+signal histogram_data_S       : std_logic_vector(31 downto 0) := (others => '0');
+signal histogram_data_valid_S : std_logic := '0';
+signal fifoempty_S            : std_logic := '0';
+signal fifo_write_S           : std_logic := '0';
+signal fifofull_S             : std_logic := '0';
+signal fifoalmost_full        : std_logic := '0';
+
+signal fifo_data_in_S         : std_logic_vector(31 downto 0) := (others => '0');
+
+signal histogram_startreading_S : std_logic := '0';
+signal reading_s              : std_logic := '0';
+
+
+begin
+
+fifo: async_fifo_af_512x32 port map(
+		rst => histogram_startreading,
+		wr_clk => write_clock,
+		rd_clk => read_clock,
+		din => fifo_data_in_S,
+		wr_en => fifo_write_S,
+		rd_en => histogram_read,
+		dout => histogram_data,
+		full => fifofull_S,
+		almost_full => fifoalmost_full,
+		empty => fifoempty_S);
+histogram_available <= '1' when fifoempty_S='0' else '0';
+
+process(write_clock)
+constant ones  : std_logic_vector(HISTOGRAM_SIZEBITS-1 downto 0) := (others => '1');
+begin
+	if (rising_edge(write_clock)) then 
+		if (reset_writeclock_S = '1') then
+			histogram_startreading_S <= '0';
+			reading_S <= '0';
+			histogram_read_S <= '0';
+			fifo_write_S <= '0';
+		else
+			if (histogram_startreading='1') and (histogram_startreading_S='0') then
+				reading_S <= '1';
+				pulsevalue_address_S <= (others => '0');
+				histogram_read_S <= '1';
+			elsif reading_S='1' then
+				if (histogram_data_valid_S='1') and (histogram_read_S/='1') then -- check also on read
+					fifo_data_in_S <= histogram_data_S;
+					if fifoalmost_full='0' then
+						fifo_write_S <= '1';
+						if pulsevalue_address_S /= ones then
+							pulsevalue_address_S <= pulsevalue_address_S+1;
+							histogram_read_S <= '1';
+						else
+							reading_S <= '0';
+							histogram_read_S <= '0';
+						end if;
+					else
+						fifo_write_S <= '0';				
+						histogram_read_S <= '0';
+					end if;
+				else
+					fifo_write_S <= '0';
+					histogram_read_S <= '0';
+				end if;
+			else
+				fifo_write_S <= '0';
+				histogram_read_S <= '0';
+			end if;
+			histogram_startreading_S <= histogram_startreading;
+		end if;
+		reset_writeclock_S <= reset;
+	end if;
+end process;
+
+histogram1: histogram port map(
+		clock => write_clock,
+		clear => clear_S,
+		datain => pulsevalue_S,
+		writerequest => pulsevalue_write_S,
+		address => pulsevalue_address_S,
+		readrequest => histogram_read_S,
+		dataout => histogram_data_S,
+		dataout_valid => histogram_data_valid_S);
+
+process(write_clock)
+constant zeros  : std_logic_vector(15 downto 0) := (others => '0');
+variable val_V : std_logic_vector(15 downto 0);
+variable his_V : std_logic_vector(15 downto 0);
+begin
+	if (rising_edge(write_clock)) then 
+		if (reset_writeclock_S = '1') then
+			clear_S <= '1';
+			pulsevalue_write_S <= '0';
+		else
+			clear_S <= clear;
+			if pulse_data_write='1' then
+				val_V := energy;
+				case binning is 
+					when "000" => his_V := val_V;
+					when "001" => his_V := '0' & val_V(15 downto 1);
+					when "010" => his_V := "00" & val_V(15 downto 2);
+					when "011" => his_V := "000" & val_V(15 downto 3);
+					when "100" => his_V := "0000" & val_V(15 downto 4);
+					when "101" => his_V := "00000" & val_V(15 downto 5);
+					when "110" => his_V := "000000" & val_V(15 downto 6);
+					when "111" => his_V := "0000000" & val_V(15 downto 7);
+					when others => his_V := val_V;
+				end case;
+				if channel=adcnumber then
+					if (HISTOGRAM_SIZEBITS<16) and (his_V(15 downto HISTOGRAM_SIZEBITS)/=zeros(15 downto HISTOGRAM_SIZEBITS)) then
+--							if conv_integer(unsigned(his_V))>2**HISTOGRAM_SIZEBITS-1 then
+						pulsevalue_S <= (others => '1');
+					else
+						pulsevalue_S <= his_V(HISTOGRAM_SIZEBITS-1 downto 0);
+					end if;
+					pulsevalue_write_S <= '1';
+				end if;
+			else
+				pulsevalue_write_S <= '0';
+			end if;
+		end if;
+	end if;
+end process;
+
+testword0(12 downto 0) <= histogram_data_S(12 downto 0); -- pulsevalue_S(HISTOGRAM_SIZEBITS-1 downto 0);
+testword0(13) <= clear_S;
+testword0(14) <= pulsevalue_write_S;
+testword0(15) <= histogram_read_S;
+testword0(16) <= histogram_data_valid_S;
+testword0(17) <= fifoempty_S;
+testword0(18) <= fifo_write_S;
+testword0(19) <= fifofull_S;
+testword0(20) <= fifoalmost_full;
+testword0(21) <= histogram_startreading_S;
+testword0(22) <= reading_s;
+testword0(23) <= '0';
+testword0(35 downto 24) <= pulsevalue_address_S;
+
+
+
+
+
+
+
+end Behavioral;
diff --git a/data_concentrator/sources/DC_max_lookuptable.vhd b/data_concentrator/sources/DC_max_lookuptable.vhd
new file mode 100644
index 0000000..619f4d9
--- /dev/null
+++ b/data_concentrator/sources/DC_max_lookuptable.vhd
@@ -0,0 +1,102 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   08-05-2012
+-- Module Name:   DC_max_lookuptable
+-- Description:   Look Up Table with default value for maximum correction
+-- Modifications:
+--   11-09-2014   Name change from max_lookuptable to DC_max_lookuptable
+--   18-09-2014   different clock for loading
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use work.DC_LUT_package.all;
+
+------------------------------------------------------------------------------------------------------
+-- DC_max_lookuptable
+--     Look Up Table with default value for maximum correction.
+--     Look Up Table can be written with different values
+--
+-- Library
+--     work.FEE_LUT_package :  for default LUT value
+--
+-- generics
+--     LUT_ADDRWIDTH : number of bits for Look Up Table addresses : LUT depth
+--     LUT_DATAWIDTH : number of bits for Look Up Table data : LUT width
+--		
+-- inputs
+--     clock : clock
+--     load_clock : clock for loading
+--     loading : mode loading new LUT data, 0 means start next on position 0
+--     lut_write : write signal for writing new data to LUT, on each write the next index is selected
+--     address : index of LUT : gives corresponding value on data_out
+--     data_in : new data for LUT
+--		
+-- outputs
+--     data_out : resulting data
+--
+-- components
+--
+--
+------------------------------------------------------------------------------------------------------
+
+entity DC_max_lookuptable is
+	generic (
+		LUT_ADDRWIDTH : natural := 8;
+		LUT_DATAWIDTH  : natural := 36
+		);
+	port ( 
+		clock                   : in std_logic;
+		load_clock              : in std_logic;
+		loading                 : in std_logic;
+		lut_write               : in std_logic;
+		address                 : in std_logic_vector (LUT_ADDRWIDTH-1 downto 0);
+		data_in                 : in std_logic_vector (LUT_DATAWIDTH-1 downto 0);
+		data_out                : out std_logic_vector (LUT_DATAWIDTH-1 downto 0));
+end DC_max_lookuptable;
+
+architecture behavioral of DC_max_lookuptable is
+
+signal lut_S                  : max_correction_lut_type := DEFAULTMAXCORRLUT;
+signal load_address_S         : std_logic_vector (LUT_ADDRWIDTH-1 downto 0);
+signal loading0_S             : std_logic;
+signal loading1_S             : std_logic;
+
+begin
+
+
+process(load_clock)
+begin
+	if (rising_edge(load_clock)) then 
+		if (lut_write = '1') then
+			lut_S(conv_integer(load_address_S)) <= data_in;
+		end if;
+	end if;
+end process;
+
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		data_out <= lut_S(conv_integer(address));
+	end if;
+end process;
+
+
+process (load_clock)
+begin
+	if (rising_edge(load_clock)) then 
+		if (loading0_S='1') and (loading1_S='0') then
+			load_address_S <= (others => '0');
+		elsif (lut_write='1') and (loading1_S='1') then
+			load_address_S <= load_address_S+1;
+		end if;
+		loading1_S <= loading0_S;
+		loading0_S <= loading;
+	end if;
+end process;
+
+
+end architecture behavioral;
diff --git a/data_concentrator/sources/DC_measure_frequency.vhd b/data_concentrator/sources/DC_measure_frequency.vhd
new file mode 100644
index 0000000..cd18678
--- /dev/null
+++ b/data_concentrator/sources/DC_measure_frequency.vhd
@@ -0,0 +1,90 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   21-06-2011
+-- Module Name:   DC_measure_frequency
+-- Description:   Measures the frequency of pulses 
+-- Modifications:
+--    16-09-2014: name changed from MUX_measure_frequency to DC_measure_frequency
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- DC_measure_frequency
+-- Measures the number of pulses in one second
+--
+-- Library
+--     work.panda_package :  for type declarations and constants
+-- 
+-- Generics:
+--     CLOCKFREQUENCY : frequency of the clock
+-- 
+-- Inputs:
+--     clock : clock
+--     pulse : pulse to count
+-- 
+-- Outputs:
+--     frequency : number of pulses measured in one second
+-- 
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity DC_measure_frequency is
+	generic (
+		CLOCKFREQUENCY          : natural := 62500000
+	);
+	port ( 
+		clock                   : in std_logic;
+		pulse                   : in std_logic;
+		frequency               : out std_logic_vector(31 downto 0)
+	);
+end DC_measure_frequency;
+
+architecture Behavioral of DC_measure_frequency is
+
+signal counter_S                  : std_logic_vector(31 downto 0) := (others => '0');
+signal onesecondpulse_S           : std_logic := '0';
+
+
+begin
+process(clock)
+variable counter : integer range 0 to CLOCKFREQUENCY-1 := 0;
+begin
+	if (rising_edge(clock)) then 
+		if counter/=0 then
+			counter := counter-1;
+			onesecondpulse_S <= '0';
+		else
+			counter := CLOCKFREQUENCY-1;
+			onesecondpulse_S <= '1';
+		end if;
+	end if;
+end process;
+
+
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if onesecondpulse_S='1' then
+			frequency <= counter_S;
+			if pulse='1' then
+				counter_S <= x"00000001";
+			else
+				counter_S <= x"00000000";
+			end if;
+		else
+			if pulse='1' then
+				counter_S <= counter_S+1;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+end Behavioral;
diff --git a/data_concentrator/sources/DC_module_TRB3.vhd b/data_concentrator/sources/DC_module_TRB3.vhd
new file mode 100644
index 0000000..0a97562
--- /dev/null
+++ b/data_concentrator/sources/DC_module_TRB3.vhd
@@ -0,0 +1,1602 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   12-07-2013
+-- Module Name:   DC_module_TRB3
+-- Description:   Multiplexer module for TRB3
+-- Modifications:
+--   30-07-2014   Timestamp from FEE is now composed by 16 bits superburstnumber and timestamp counter within superburst
+--   29-08-2014   ADCCLOCKFREQUENCY added: SODA clock at 80MHz 
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+use work.soda_components.all;
+
+----------------------------------------------------------------------------------
+-- DC_module_TRB3
+-- Module to describe the behavioral of the Panda Data collector multiplexer.
+-- Soda signals are generated by a SODA generator.
+-- Slow control is done by TRBnet.
+--    
+-- Connection to the Front End Electronics fibers is implemented with synchronized serdes fiber link:
+-- From MUX to FEE the clock is phase aligned for SODA signals. Asynchronous data is used for slow control.
+-- From FEE to MUX the clock is not phase aligned. The connection is used for pulse data and slow control.
+-- Pulse data from the FEE fiber data is available in packets of 4*36-bits words.
+-- The pulse data from the fibres are combined to one stream. The pulse-data is sorted on the timestamp and the time-fraction.
+-- The pileup waveform data from the fibres are also combined to one stream. This is not sorted.
+-- The resulting streams with pulse data and with pileup waveforms are combined. The interface to the Compute Node is not yet available.
+-- The timestamp is checked and the pulse energy is put in a histogram. The resuls of these functions are read by the slowcontrol.
+--
+-- Adresses from slowcontrol module, see work.panda_package for constants:
+--     ADDRESS_MUX_SODA_CONTROL :
+--         only write: settings for the SODA : 
+--         bit0 : enable SODA packets
+--         bit1 : reset timestamp counters
+--         bit2 : Enable data taking 
+--         bit3 : Disable data taking
+--         bit4 : Enable 64-bit output data
+--         bit5 : Enable Pileup Waveform sending
+--         bit6 : Select source for multiplexer status (ADDRESS_MUX_MULTIPLEXER_STATUS): 0=pulse, 1=waveform
+--
+--     ADDRESS_MUX_HISTOGRAM
+--         only write:  settings for the histogram : 
+--         bit0 : clear the histogram
+--         bit1 : start reading of the histogram
+--         bit10..8 : Binning of the histogram channels, scaling x-axis :
+--              000 = no scaling
+--              001 = div 2
+--              010 = div 4
+--              011 = div 8
+--              100 = div 16
+--              101 = div 32
+--              110 = div 64
+--              111 = div 128
+--         bit31..16 : Selected unique adc-number (12-bits board-number and 4 bits ADC-index)
+--         The reply will be:
+--         32-bits word0  : bits(31..24)=0xD0, bits23..0=ADDRESS_MUX_HISTOGRAM
+--         32-bits word1  : bits(31..0)=0
+--         32-bits word2  : bits(31..0)=histogram channel 0  
+--         ...
+--         32-bits word4097 : bits(31..0)=histogram channel 4095   
+--
+--     ADDRESS_MUX_EXTRACTWAVE
+--         request: start extracting waveform of 1 pileup pulse:
+--         bit 15..0 : selected adcnumber (if bit 16 is set)
+--         bit 16 : select 1 adc, otherwise take first data arriving
+--         bit 17 : select 1 low/high combination instead of 1 adc channel
+--         The reply will be (after a waveform has been measured) :
+--         32-bits word0  : bits(31..24)=0xD0, bits23..0=ADDRESS_MUX_EXTRACTWAVE
+--         32-bits word1  : bits(31..0)=timestamp of maximum value in waveform
+--         32-bits word2  : bits(31)=0, bits(30..0)=SuperBurst number
+--         32-bits word3  : bits(31..24) = statusbyte, bits(23..16) = 00, bits(15..0) = adcnumber 
+--         32-bits word4..n: bit(31)=0, bits(30..16)=adc sample, bit(15)=0, bits(14..0)=next adc sample
+--         32-bits last word (1sample): bits(31)=1, bits(30..16)=last adc sample, bit(15)=0, bits(14..0)=0
+--         32-bits last word (2samples): bits(31)=0, bits(30..16)=adc sample, bit15=1, bits(14..0)=last adc sample
+--         32-bits last word (error): bits(31)=1, bits(30..16)=don't care, bit15=1, bits(14..0)=don't care
+--
+--     ADDRESS_MUX_EXTRACTDATA
+--         request: start extracting data of 1 pulse:
+--         bit 15..0 : selected adcnumber
+--         bit 16 : select 1 adc, otherwise take first data arriving
+--         bit 17 : select 1 low/high combination instead of 1 adc channel
+--         The reply will be :
+--         32-bits word0  : bits(31..24=0xD0, bits23..0=ADDRESS_MUX_EXTRACTDATA
+--         32-bits word1  : bits(31..24)=statusbyte, bits(23..16)=0, bits(15..0)=adcnumber
+--         32-bits word2  : bits(31..24)=0xD0, bits(23..0)=ADDRESS_MUX_EXTRACTDATA+1
+--         32-bits word3  : bits(31..24)=timefraction, bits(15..0)=energy
+--         32-bits word4  : bits(31..24)=0xD0, bits(23..0)= ADDRESS_MUX_EXTRACTDATA+2
+--         32-bits word5  : bits(31..0)= timestamp(47..16) with bits 47..32 set to 0
+--         32-bits word6  : bits(31..24)=0xD0, bits23..0= ADDRESS_MUX_EXTRACTDATA+3
+--         32-bits word7  : bits(31..16)=0, bits(15..0)=timestamp(15..0)
+--
+--     ADDRESS_MUX_SYSMON
+--         write to FPGA system monitor
+--         bit 31 : slect read/write, write='0', read='1'
+--         bit 30 : reset/reconfigure FPGA system monitor
+--         bit 22..16 : 7-bits address of FPGA system monitor
+--         bit 15..0 : 16-bits data for FPGA system monitor
+--         read from FPGA system monitor, effective address is the last address at data bits 30..16 that was written
+--         bit 30..16 : 7-bits effective address of FPGA system monitor
+--         bit 15..0 : data from FPGA system monitor
+--
+--
+-- Library
+--     work.panda_package :  for type declarations and constants
+-- 
+-- Generics:
+--     NROFFIBERS : number of fiber connection of the MUX board (only 4 is possible)
+--     NROFADCS : number of ADCs in each FEE
+--     SODAPERIOD_IN_PS : Clock period of SODA clock in ps
+--     SODACLOCKDIV : SODA Clock divider factor : 1,2 or 4 for 8,16 or 32 bits data
+--     ADCCLOCKFREQUENCY : Frequency of the ADCclock in Hz, defines also the SODA clock frequency
+--     MAX_DIVIDERSCALEBITS : number of scaling bits for division two largest samples
+--     MAX_LUTSIZEBITS : number of bits the maximum correction Look Up Table
+--     MAX_LUTSCALEBITS : number of scaling bits for the correction on the maximum (energy)
+--     HISTOGRAM_SIZEBITS : bits for the histogram x-axis : 2^HISTOGRAM_SIZEBITS = number of histogram channels
+--     MUXINFIFOSIZE : size (fifo-depth bits) of the input fifo's of the multiplexer
+--     TRANSFERFIFOSIZE : size (fifo-depth bits) of multiplexer transfer fifo
+--     CF_FRACTIONBIT : number of valid constant fraction bits
+--     TRANSITIONBUFFERBITS : number of bits for the buffer that stores data from the next superburst
+--     PANDAPACKETBUFFERBITS : number of bits for the buffer to store packet for size calculation
+--     ADCINDEXSHIFT : ADC channel numbers lowest bit indicates the high or low gain ADC, 0=high, 1=low
+--     ENERGYSCALINGBITS : number of scaling bits for energy adjustment: energy = (original_energy * gainfactor<<scalingbits)>>scalingbits
+--     COMBINEPULSESMEMSIZE : addressbits for the fifo buffer for combining hits
+--     COMBINETIMEDIFFERENCE : largest time difference between hits to be combined, number of timefraction units
+--     SYSTEM_ID : ID number of this Data Concentrator
+-- 
+-- Inputs:
+--     slowcontrol_clock : clock for the slowcontrol input/output
+--     packet_in_clock : clock for data from the fiber module
+--     MUX_clock : clock for the multiplexer
+--     packet_out_clock : clock for data from the multiplexer output
+--     SODA_clock : clock for SODA signals: SODA source frequency divided by SODACLOCKDIV
+--     reset : reset of all components
+--     BUS_READ_IN : TRBnet local bus read signal
+--     BUS_WRITE_IN : TRBnet local bus write signal
+--     BUS_ADDR_IN : TRBnet local bus address
+--     BUS_DATA_IN : TRBnet local bus data
+--     gtpClk : reference clock for the quad serdes
+--     gtpClkDiv2 : reference clock divided by 2 for the quad serdes
+--     gtpLOS : no fiber signal detected
+--     gtpRxP0,gtpRxN0 : serdes differential inputs from each fiber module
+--     TX_DLM : transmit SODA character (for each fiber)
+--     TX_DLM_WORD : SODA character to be transmitted (for each fiber)
+--     data_out_allowed : 64-bits output data allowed to write (normally: connected fifo not full)
+--     SCI_DATA_IN : serdes control interface : data
+--     SCI_ADDR : serdes control interface : address
+--     SCI_READ : serdes control interface : read
+--     SCI_WRITE : serdes control interface : write
+-- 
+-- Outputs:
+--     BUS_BUSY_OUT : TRBnet local bus busy signal
+--     BUS_ACK_OUT : TRBnet local bus acknowledge signal
+--     BUS_DATA_OUT : TRBnet local bus data
+--     refClkOut : buffered output of the serdes reference clock
+--     refClk_OK : serdes reference clock is valid (PLL locked)
+--     gtpTxP0,gtpTxN0 : serdes differential outputs to each fiber module
+--     RX_DLM : SODA character received (for each fiber)
+--     RX_DLM_WORD : SODA character (for each fiber)
+--     EnableExternalSODA : Enable external (fibre coupled) SODA instead of internal SODA generation
+--     data_out : 64-bits output data
+--     data_out_write : 64-bits output data write signal
+--     data_out_first : 64-bits output data first word in packet
+--     data_out_last : 64-bits output data last word in packet
+--     data_out_error : error occured in 64-bits output data		
+--     SCI_DATA_OUT : serdes control interface : data
+--     SCI_ACK : serdes control interface : acknowledge
+--     SCI_NACK : serdes control interface : not acknowledge
+--     LEDs_link_ok : serdes status for LED on extension board : link ok
+--     LEDs_rx : serdes status for LED on extension board : receive
+--     LEDs_tx : serdes status for LED on extension board : transmit
+-- 
+-- Components:
+--     DC_slow_control_TRB3 : module for slow control : TRBnet local bus to Data Concentrator registers/status
+--     posedge_to_pulse : Makes a 1-clock pulse on rising edge from signal with different clock
+--     synchronize_to_other_clock : Synchronise parallel data to a other clock
+--     DC_Quad_fiber_module : Handles the connection to/from the FEE, builds & entangles fiber packets (for one module for 4 fibers)
+--     DC_sorting_mux : Multiplex the pulse data from all the fiber inputs to one output and sort it based on timestamp
+--     DC_wavemux : Multiplex the pileup waveform data from all the fiber inputs to one output
+--     DC_histogram : Creates a histogram of the energies of one adc of one of the fiber inputs
+--     DC_check_timestamp : check if the timestamps are sorted well
+--     DC_extract_data : Extract pulse data from the data stream for handling by slow control
+--     DC_extract_wave : Extract pileup waveform from the data stream for handling by slow control
+--     DC_data_wave_to_64bit : put pulse and waveform data in packets with 64-bits wide bus
+--     DC_combine_pulses : Combine pulses (=hits) from corresponding ADC channels
+--
+----------------------------------------------------------------------------------
+
+entity DC_module_TRB3 is
+	generic (
+		NROFFIBERS              : natural := 4;
+		NROFADCS                : natural := 16;
+		ADCBITS                 : natural := 14;
+		SODAPERIOD_IN_PS        : natural := 8000; -- SODA clock period in ps 155.52MHz=6430, 125MHz=8000
+		SODACLOCKDIV            : natural := 2; -- 1,2,4 : SODA clock divide factor
+		SODA_16BIT_INTERFACE	: boolean := FALSE;
+		ADCCLOCKFREQUENCY       : natural := 80000000;
+		MAX_DIVIDERSCALEBITS    : natural := 12;
+		MAX_LUTSIZEBITS         : natural := 8;
+		MAX_LUTSCALEBITS        : natural := 14;
+		HISTOGRAM_SIZEBITS      : natural := 12;
+		MUXINFIFOSIZE           : natural := 9;
+		TRANSFERFIFOSIZE        : natural := 14;
+		CF_FRACTIONBIT          : natural := 11;
+		TRANSITIONBUFFERBITS    : natural := 7;
+		PANDAPACKETBUFFERBITS   : natural := 13;
+		ADCINDEXSHIFT           : natural := 1;
+		ENERGYSCALINGBITS       : natural := 13;
+		COMBINEPULSESMEMSIZE    : natural := 10;
+		COMBINETIMEDIFFERENCE   : natural := 5000;
+		SYSTEM_ID               : std_logic_vector(15 downto 0) := x"5555"		
+	);
+	port ( 
+		slowcontrol_clock       : in std_logic;
+		packet_in_clock         : in std_logic;
+		MUX_clock               : in std_logic;
+		packet_out_clock        : in std_logic;
+		SODA_clock              : in std_logic;
+		reset                   : in std_logic;
+
+-- Slave bus
+		BUS_READ_IN             : in   std_logic;
+		BUS_WRITE_IN            : in   std_logic;
+		BUS_BUSY_OUT            : out  std_logic;
+		BUS_ACK_OUT             : out  std_logic;
+		BUS_ADDR_IN             : in   std_logic_vector(1 downto 0);
+		BUS_DATA_IN             : in   std_logic_vector(31 downto 0);
+		BUS_DATA_OUT            : out  std_logic_vector(31 downto 0);
+		
+-- fiber interface signals:
+		gtpClk                  : in std_logic; -- 200MHz
+		gtpClkDiv2              : in std_logic; -- 100MHz
+		refClkOut               : out std_logic;
+		refClk_OK               : out std_logic;
+		gtpLOS                  : in std_logic_vector(0 to NROFFIBERS-1);
+		gtpTxP0                 : out std_logic_vector(0 to NROFFIBERS-1);
+		gtpTxN0                 : out std_logic_vector(0 to NROFFIBERS-1);
+		gtpRxP0                 : in std_logic_vector(0 to NROFFIBERS-1);
+		gtpRxN0                 : in std_logic_vector(0 to NROFFIBERS-1);
+
+-- SODA signals
+		TX_DLM                  : in std_logic_vector(0 to NROFFIBERS-1);
+		TX_DLM_WORD             : in array_fiber8bits_type;  
+		RX_DLM                  : out std_logic_vector(0 to NROFFIBERS-1);
+		RX_DLM_WORD             : out array_fiber8bits_type;
+		EnableExternalSODA      : out std_logic;
+
+-- 64 bits data output
+		data_out_allowed        : in std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_write          : out std_logic;
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_error          : out std_logic;
+
+-- Control Interface
+		SCI_DATA_IN             : in  std_logic_vector(7 downto 0) := (others => '0');
+		SCI_DATA_OUT            : out std_logic_vector(7 downto 0) := (others => '0');
+		SCI_ADDR                : in  std_logic_vector(8 downto 0) := (others => '0');
+		SCI_READ                : in  std_logic := '0';
+		SCI_WRITE               : in  std_logic := '0';
+		SCI_ACK                 : out std_logic := '0';
+		SCI_NACK                : out std_logic := '0';
+		
+-- testpoints
+		txpll_clocks            : out std_logic_vector(3 downto 0); 
+		LEDs_link_ok            : out std_logic_vector(0 to 3);
+		LEDs_rx                 : out std_logic_vector(0 to 3); 
+		LEDs_tx                 : out std_logic_vector(0 to 3);
+		testword0               : out std_logic_vector (35 downto 0);
+		testword0clock          : out std_logic;
+		testword1               : out std_logic_vector (35 downto 0);
+		testword2               : out std_logic_vector (35 downto 0)
+
+		);
+end DC_module_TRB3;
+
+architecture Behavioral of DC_module_TRB3 is
+
+component DC_slow_control_TRB3 is
+	port(	
+		rst                     : in std_logic;
+		clk                     : in std_logic;
+-- Slave bus
+		BUS_READ_IN             : in   std_logic;
+		BUS_WRITE_IN            : in   std_logic;
+		BUS_BUSY_OUT            : out  std_logic;
+		BUS_ACK_OUT             : out  std_logic;
+		BUS_ADDR_IN             : in   std_logic_vector(1 downto 0);
+		BUS_DATA_IN             : in   std_logic_vector(31 downto 0);
+		BUS_DATA_OUT            : out  std_logic_vector(31 downto 0);
+
+		io_data_in              : in std_logic_vector(0 to NROFFIBERS-1);
+		IO_data_in_available    : in std_logic_vector(0 to NROFFIBERS-1);
+		io_data_out             : out std_logic_vector(7 downto 0);
+		io_write_out            : out std_logic;
+
+		extract_data_available  : in std_logic;
+		extract_wave_available  : in std_logic;
+
+		board_status            : in array_muxregister_type;
+		board_status_read       : out std_logic_vector(0 to NROFMUXREGS-1);
+		board_control           : out array_muxregister_type;
+		board_control_write     : out std_logic_vector(0 to NROFMUXREGS-1);
+		testword0               : out std_logic_vector (35 downto 0)
+		);
+end component;
+
+component DC_Quad_fiber_module is
+	generic (
+		NROFADCS                : natural := NROFADCS;
+		ADCINDEXSHIFT           : natural := ADCINDEXSHIFT;
+		ADCBITS                 : natural := ADCBITS;
+		ADCCLOCKFREQUENCY       : natural := ADCCLOCKFREQUENCY;
+		CF_FRACTIONBIT          : natural := CF_FRACTIONBIT;
+		ENERGYSCALINGBITS       : natural := ENERGYSCALINGBITS;
+		MAX_DIVIDERSCALEBITS    : natural := MAX_DIVIDERSCALEBITS;
+		MAX_LUTSIZEBITS         : natural := MAX_LUTSIZEBITS;
+		MAX_LUTSCALEBITS        : natural := MAX_LUTSCALEBITS
+
+		);
+	port ( 
+		slowcontrol_clock       : in std_logic;
+		packet_clock            : in std_logic;
+		MUX_clock               : in std_logic;
+		SODA_clock              : in std_logic;
+		reset                   : in std_logic;
+		reset_fibers            : in std_logic;
+		channel                 : in std_logic_vector (3 downto 0);
+		superburst_number       : in std_logic_vector(30 downto 0);
+		superburst_update       : in std_logic;
+
+-- txUsr clock
+		refClkOut               : out std_logic;
+		refClk_OK               : out std_logic;
+		txpll_clocks            : out std_logic_vector(3 downto 0);
+
+-- SlowControl to/from cpu
+		IO_byte                 : in std_logic_vector(7 downto 0);
+		IO_write                : in std_logic;
+		G0_IO_serialdata        : out std_logic;
+		G0_IO_serialavailable   : out std_logic;
+		G1_IO_serialdata        : out std_logic;
+		G1_IO_serialavailable   : out std_logic;
+		G2_IO_serialdata        : out std_logic;
+		G2_IO_serialavailable   : out std_logic;
+		G3_IO_serialdata        : out std_logic;
+		G3_IO_serialavailable   : out std_logic;
+		
+-- multiplexer status/control
+		G0_muxstat_infifo_fullness : in std_logic_vector (15 downto 0);
+		muxstat_outfifo_fullness : in std_logic_vector (15 downto 0);
+		timestamp_errors        : in std_logic_vector(9 downto 0);
+		skipped_pulses          : in std_logic_vector(9 downto 0);
+		dataerrors              : in std_logic_vector(9 downto 0);
+
+-- Pulse data
+		G0_pulse_data_out       : out std_logic_vector(35 downto 0);
+		G0_pulse_data_write     : out std_logic;
+		G0_pulse_data_out_allowed  : in std_logic;
+
+-- Wave data
+		G0_wave_data_out        : out std_logic_vector(35 downto 0);
+		G0_wave_data_write      : out std_logic;
+		G0_wave_data_out_allowed: in std_logic;
+		
+-- Status
+		G0_resetDone            : out std_logic;
+		G0_txLocked             : out std_logic;
+		G0_rxLocked             : out std_logic;
+	
+-- SODA 
+		G0_TX_DLM               : in  std_logic := '0';
+		G0_TX_DLM_WORD          : in  std_logic_vector(7 downto 0) := x"00";   
+		G0_RX_DLM               : out std_logic;
+		G0_RX_DLM_WORD          : out std_logic_vector(7 downto 0);
+		
+-- fiber interface signals:
+		gtpClk                  : in std_logic; -- 200MHz
+		gtpClkDiv2              : in std_logic; -- 100MHz
+		G0_LOS                  : in std_logic;
+		G0_gtpTxP               : out std_logic;
+		G0_gtpTxN               : out std_logic;
+		G0_gtpRxP               : in std_logic;
+		G0_gtpRxN               : in std_logic;
+
+-- multiplexer status
+		G1_muxstat_infifo_fullness : in std_logic_vector (15 downto 0);
+
+-- Pulse data
+		G1_pulse_data_out       : out std_logic_vector(35 downto 0);
+		G1_pulse_data_write     : out std_logic;
+		G1_pulse_data_out_allowed  : in std_logic;
+
+-- Wave data
+		G1_wave_data_out        : out std_logic_vector(35 downto 0);
+		G1_wave_data_write      : out std_logic;
+		G1_wave_data_out_allowed: in std_logic;
+
+-- Status
+		G1_resetDone            : out std_logic;
+		G1_txLocked             : out std_logic;
+		G1_rxLocked             : out std_logic;
+		
+-- SODA 
+		G1_TX_DLM               : in  std_logic := '0';
+		G1_TX_DLM_WORD          : in  std_logic_vector(7 downto 0) := x"00";   
+		G1_RX_DLM               : out std_logic;
+		G1_RX_DLM_WORD          : out std_logic_vector(7 downto 0);
+
+-- fiber interface signals:
+		G1_LOS                  : in std_logic;
+		G1_gtpTxP               : out std_logic;
+		G1_gtpTxN               : out std_logic;
+		G1_gtpRxP               : in std_logic;
+		G1_gtpRxN               : in std_logic;
+
+-- multiplexer status
+		G2_muxstat_infifo_fullness : in std_logic_vector (15 downto 0);
+
+-- Pulse data
+		G2_pulse_data_out       : out std_logic_vector(35 downto 0);
+		G2_pulse_data_write     : out std_logic;
+		G2_pulse_data_out_allowed  : in std_logic;
+
+-- Wave data
+		G2_wave_data_out        : out std_logic_vector(35 downto 0);
+		G2_wave_data_write      : out std_logic;
+		G2_wave_data_out_allowed: in std_logic;
+
+-- Status
+		G2_resetDone            : out std_logic;
+		G2_txLocked             : out std_logic;
+		G2_rxLocked             : out std_logic;
+		
+-- SODA 
+		G2_TX_DLM               : in  std_logic := '0';
+		G2_TX_DLM_WORD          : in  std_logic_vector(7 downto 0) := x"00";   
+		G2_RX_DLM               : out std_logic;
+		G2_RX_DLM_WORD          : out std_logic_vector(7 downto 0);
+		
+-- fiber interface signals:
+		G2_LOS                  : in std_logic;
+		G2_gtpTxP               : out std_logic;
+		G2_gtpTxN               : out std_logic;
+		G2_gtpRxP               : in std_logic;
+		G2_gtpRxN               : in std_logic;
+
+-- multiplexer status
+		G3_muxstat_infifo_fullness : in std_logic_vector (15 downto 0);
+
+-- Pulse data
+		G3_pulse_data_out       : out std_logic_vector(35 downto 0);
+		G3_pulse_data_write     : out std_logic;
+		G3_pulse_data_out_allowed  : in std_logic;
+
+-- Wave data
+		G3_wave_data_out        : out std_logic_vector(35 downto 0);
+		G3_wave_data_write      : out std_logic;
+		G3_wave_data_out_allowed: in std_logic;
+
+-- Status
+		G3_resetDone            : out std_logic;
+		G3_txLocked             : out std_logic;
+		G3_rxLocked             : out std_logic;
+		
+-- SODA 
+		G3_TX_DLM               : in  std_logic := '0';
+		G3_TX_DLM_WORD          : in  std_logic_vector(7 downto 0) := x"00";   
+		G3_RX_DLM               : out std_logic;
+		G3_RX_DLM_WORD          : out std_logic_vector(7 downto 0);
+		
+-- fiber interface signals:
+		G3_LOS                  : in std_logic;
+		G3_gtpTxP               : out std_logic;
+		G3_gtpTxN               : out std_logic;
+		G3_gtpRxP               : in std_logic;
+		G3_gtpRxN               : in std_logic;
+		
+		--Control Interface
+		SCI_DATA_IN             : in  std_logic_vector(7 downto 0) := (others => '0');
+		SCI_DATA_OUT            : out std_logic_vector(7 downto 0) := (others => '0');
+		SCI_ADDR                : in  std_logic_vector(8 downto 0) := (others => '0');
+		SCI_READ                : in  std_logic := '0';
+		SCI_WRITE               : in  std_logic := '0';
+		SCI_ACK                 : out std_logic := '0';
+		SCI_NACK                : out std_logic := '0';
+
+-- tests		
+		LEDs_link_ok            : out std_logic_vector(0 to 3);
+		LEDs_rx                 : out std_logic_vector(0 to 3); 
+		LEDs_tx                 : out std_logic_vector(0 to 3);
+		testword0               : out std_logic_vector (35 downto 0);
+		testword0clock          : out std_logic;
+		testword1               : out std_logic_vector (35 downto 0);
+		testPin                 : out std_logic_vector (3 downto 0)
+		);
+end component;
+
+component DC_sorting_mux is
+	generic(
+		NROFMUXINPUTS           : natural := NROFFIBERS;
+		MUXINFIFOSIZE           : natural := MUXINFIFOSIZE;
+		TRANSFERFIFOSIZE        : natural := TRANSFERFIFOSIZE;
+		CF_FRACTIONBIT          : natural := CF_FRACTIONBIT
+	);
+    port ( 
+		inputclock              : in std_logic;
+		MUXclock                : in std_logic; 
+		outputclock             : in std_logic; 
+		reset                   : in std_logic;
+		data_in                 : in array_fiber36bits_type;
+		data_in_write           : in std_logic_vector(0 to NROFMUXINPUTS-1);
+		data_in_allowed         : out std_logic_vector(0 to NROFMUXINPUTS-1);
+		fiber_index             : out std_logic_vector(3 downto 0);
+		channel                 : out std_logic_vector(15 downto 0);
+		statusbyte              : out std_logic_vector(7 downto 0);
+		energy                  : out std_logic_vector(15 downto 0);
+		timefraction            : out std_logic_vector(11 downto 0);
+		timestamp               : out std_logic_vector(15 downto 0);
+		superburstnumber        : out std_logic_vector(30 downto 0);		
+		data_out_read           : in std_logic;
+		data_out_available      : out std_logic;
+		infifo_fullness         : out array_fiber16bits_type;
+		outfifo_fullness        : out std_logic_vector(15 downto 0);
+		testword0               : out std_logic_vector(35 downto 0);
+		testword1               : out std_logic_vector(35 downto 0);
+		error                   : out std_logic);
+end component;
+
+component DC_combine_pulses is
+	generic (
+		NROFFIBERS              : natural := NROFFIBERS;
+		NROFADCS                : natural := NROFADCS;
+		ADCINDEXSHIFT           : natural := ADCINDEXSHIFT;
+		COMBINEPULSESMEMSIZE    : natural := COMBINEPULSESMEMSIZE;
+		COMBINETIMEDIFFERENCE   : natural := COMBINETIMEDIFFERENCE;
+		CF_FRACTIONBIT          : natural := CF_FRACTIONBIT
+		);
+	port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		combine_pulse           : in std_logic_vector((NROFFIBERS*NROFADCS)/(2*(ADCINDEXSHIFT+1))-1 downto 0);
+		fiber_index_in          : in std_logic_vector(3 downto 0);
+		channel_in              : in std_logic_vector(15 downto 0);
+		statusbyte_in           : in std_logic_vector(7 downto 0);
+		energy_in               : in std_logic_vector(15 downto 0);
+		timefraction_in         : in std_logic_vector(11 downto 0);
+		timestamp_in            : in std_logic_vector(15 downto 0);
+		superburstnumber_in     : in std_logic_vector(30 downto 0);
+		data_in_read            : out std_logic;
+		data_in_available       : in std_logic;
+
+		channel_out             : out std_logic_vector(15 downto 0);
+		statusbyte_out          : out std_logic_vector(7 downto 0);
+		energy_out              : out std_logic_vector(15 downto 0);
+		timefraction_out        : out std_logic_vector(11 downto 0);
+		timestamp_out           : out std_logic_vector(15 downto 0);
+		superburstnumber_out    : out std_logic_vector(30 downto 0);
+		data_out_read           : in std_logic;
+		data_out_available      : out std_logic
+	);
+end component;
+
+component DC_wavemux is
+	generic(
+		NROFMUXINPUTS           : natural := NROFFIBERS
+	);
+    Port ( 
+		inputclock              : in std_logic;
+		MUXclock                : in std_logic; 
+		outputclock             : in std_logic; 
+		reset                   : in std_logic;
+		data_in                 : in array_fiber36bits_type;
+		data_in_write           : in std_logic_vector(0 to NROFMUXINPUTS-1);
+		data_in_wave_allowed    : out std_logic_vector(0 to NROFMUXINPUTS-1);
+		data_out                : out std_logic_vector(35 downto 0);
+		data_out_read           : in std_logic;
+		data_out_available      : out std_logic;
+		infifo_fullness         : out array_fiber16bits_type;
+		outfifo_fullness        : out std_logic_vector(15 downto 0);
+		testword0               : out std_logic_vector(35 downto 0);
+		testword1               : out std_logic_vector(35 downto 0);
+		error                   : out std_logic);
+end component;
+
+component DC_check_timestamp is
+	port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		clear                   : in std_logic;
+		channel                 : in std_logic_vector(15 downto 0);
+		statusbyte              : in std_logic_vector(7 downto 0);
+		energy                  : in std_logic_vector(15 downto 0);
+		timefraction            : in std_logic_vector(11 downto 0);
+		timestamp               : in std_logic_vector(15 downto 0);
+		superburstnumber        : in std_logic_vector(30 downto 0);		
+		pulse_data_write        : in std_logic;
+		multiplexer_error       : in std_logic;
+		timestamp_errors        : out std_logic_vector(9 downto 0);	
+		skipped_pulses          : out std_logic_vector(9 downto 0);
+		dataerrors              : out std_logic_vector(9 downto 0)
+		);
+end component;
+
+component DC_histogram is
+	generic (
+		HISTOGRAM_SIZEBITS : natural := HISTOGRAM_SIZEBITS
+	);
+	port ( 
+		write_clock             : in std_logic;
+		read_clock              : in std_logic;
+		reset                   : in std_logic;
+		testword0               : out std_logic_vector (35 downto 0);
+		adcnumber               : in std_logic_vector(15 downto 0);
+		clear                   : in std_logic;
+		binning                 : in std_logic_vector(2 downto 0);
+		channel                 : in std_logic_vector(15 downto 0);
+		statusbyte              : in std_logic_vector(7 downto 0);
+		energy                  : in std_logic_vector(15 downto 0);
+		timefraction            : in std_logic_vector(11 downto 0);
+		timestamp               : in std_logic_vector(15 downto 0);
+		superburstnumber        : in std_logic_vector(30 downto 0);		
+		pulse_data_write        : in std_logic;
+		histogram_startreading  : in std_logic;
+		histogram_data          : out std_logic_vector(31 downto 0);
+		histogram_read          : in std_logic;
+		histogram_available     : out std_logic		
+		);
+end component;
+
+component posedge_to_pulse is
+	port (
+		clock_in                : in  std_logic;
+		clock_out               : in  std_logic;
+		en_clk                  : in  std_logic;
+		signal_in               : in  std_logic;
+		pulse                   : out std_logic);
+end component;
+
+component DC_data_wave_to_64bit is
+	generic (
+		TRANSITIONBUFFERBITS : natural := TRANSITIONBUFFERBITS;
+		PANDAPACKETBUFFERBITS : natural := PANDAPACKETBUFFERBITS;
+		SYSTEM_ID               : std_logic_vector(15 downto 0) := SYSTEM_ID
+	);
+    Port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		latestsuperburstnumber  : in std_logic_vector(30 downto 0);
+		channel                 : in std_logic_vector(15 downto 0);
+		statusbyte              : in std_logic_vector(7 downto 0);
+		energy                  : in std_logic_vector(15 downto 0);
+		timefraction            : in std_logic_vector(11 downto 0);
+		timestamp               : in std_logic_vector(15 downto 0);
+		superburstnumber        : in std_logic_vector(30 downto 0);		
+		data_in_available       : in std_logic;
+		data_in_read            : out std_logic;
+		wave_in                 : in std_logic_vector(35 downto 0);
+		wave_in_available       : in std_logic;
+		wave_in_read            : out std_logic;
+		data_out_allowed        : in std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_write          : out std_logic;
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		error                   : out std_logic;
+		testword0               : out std_logic_vector(35 downto 0);
+		testword1               : out std_logic_vector(35 downto 0)
+		);
+end component;
+
+component DC_extract_data is
+	port ( 
+		write_clock             : in std_logic;
+		read_clock              : in std_logic;
+		reset                   : in std_logic;
+		start                   : in std_logic;
+		make_selection          : in std_logic;
+		dualgain                : in std_logic;
+		adcnumber               : in std_logic_vector(15 downto 0);		
+		channel                 : in std_logic_vector(15 downto 0);
+		statusbyte              : in std_logic_vector(7 downto 0);
+		energy                  : in std_logic_vector(15 downto 0);
+		timefraction            : in std_logic_vector(11 downto 0);
+		timestamp               : in std_logic_vector(15 downto 0);
+		superburstnumber        : in std_logic_vector(30 downto 0);		
+		pulse_data_write        : in std_logic;
+		ready                   : out std_logic;
+		pulse_data_select       : in std_logic_vector(1 downto 0);
+		pulse_data_out          : out std_logic_vector(31 downto 0);
+		testword0               : out std_logic_vector(35 downto 0)
+		);
+end component;
+
+component DC_extract_wave is
+	port ( 
+		write_clock             : in std_logic;
+		read_clock              : in std_logic;
+		reset                   : in std_logic;
+		start                   : in std_logic;
+		make_selection          : in std_logic;
+		dualgain                : in std_logic;
+		adcnumber               : in std_logic_vector(15 downto 0);		
+		wave_data_in            : in std_logic_vector(35 downto 0);
+		wave_data_in_write      : in std_logic;
+		ready                   : out std_logic;
+		wave_data_out           : out std_logic_vector(31 downto 0);
+		wave_data_out_read      : in std_logic;
+		testword0               : out std_logic_vector(35 downto 0)
+		);
+end component;
+
+component synchronize_to_other_clock is
+    generic (
+        DATA_WIDTH : natural := 8
+    );
+    port (
+		data_in_clock : in std_logic;
+		data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
+		data_out_clock : in std_logic;
+		data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
+    );
+end component;
+
+component MUX_checkwave is
+    Port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		wave_in                 : in std_logic_vector(35 downto 0);
+		wave_in_write           : in std_logic;
+		error                   : out std_logic
+	);    
+end component;
+
+constant ones                        : std_logic_vector(31 downto 0) := (others => '1');
+signal reset_slowcontrolclock_S      : std_logic;
+signal reset_packet_in_clock_S       : std_logic;
+signal reset_packet_out_clock_S      : std_logic;
+signal reset_SODAclock_S             : std_logic;
+signal reset_fibers0_S               : std_logic;
+signal reset_fibers_S                : std_logic;
+
+signal EnableOutputFibre_S           : std_logic;
+signal EnableOutputFibre0_S          : std_logic;
+signal EnableWaveformSending_S       : std_logic;
+signal SODA_TimeTagValid_S           : std_logic;
+
+signal reset_timestamp_counter_S     : std_logic;
+signal superburst_number_S           : std_logic_vector(30 downto 0);
+signal superburst_update_S           : std_logic;
+
+signal pulse_data_array_S            : array_fiber36bits_type;             
+signal pulse_data_array_write_S      : std_logic_vector (0 to NROFFIBERS-1);
+signal pulse_data_array_allowed_S    : std_logic_vector (0 to NROFFIBERS-1);
+
+signal wave_data_array_S             : array_fiber36bits_type;             
+signal wave_data_array_write_S       : std_logic_vector (0 to NROFFIBERS-1);
+signal wave_data_array_allowed_S     : std_logic_vector (0 to NROFFIBERS-1);
+
+signal wave_data_available_S         : std_logic;
+signal wave_data_read_S              : std_logic;
+signal wave_data_read0_S             : std_logic;
+signal wave_data_S                   : std_logic_vector (35 downto 0);
+signal wave_data_in_write_S          : std_logic;
+--signal wave_data_read0_S             : std_logic;
+		
+signal fiber_index_S                 : std_logic_vector(3 downto 0);
+signal mux_channel_S                 : std_logic_vector(15 downto 0);
+signal mux_statusbyte_S              : std_logic_vector(7 downto 0);
+signal mux_energy_S                  : std_logic_vector(15 downto 0);
+signal mux_timefraction_S            : std_logic_vector(11 downto 0);
+signal mux_timestamp_S               : std_logic_vector(15 downto 0);
+signal mux_superburstnumber_S        : std_logic_vector(30 downto 0);
+signal mux_data_out_read_S           : std_logic;
+signal mux_data_out_available_S      : std_logic;
+
+signal pulse_channel_S               : std_logic_vector(15 downto 0);
+signal pulse_statusbyte_S            : std_logic_vector(7 downto 0);
+signal pulse_energy_S                : std_logic_vector(15 downto 0);
+signal pulse_timefraction_S          : std_logic_vector(11 downto 0);
+signal pulse_timestamp_S             : std_logic_vector(15 downto 0);
+signal pulse_superburstnumber_S      : std_logic_vector(30 downto 0);
+
+signal pulse_packet_write_S          : std_logic;
+signal pulse_packet_request_S        : std_logic;
+signal pulse_packet_read_S           : std_logic;
+signal pulse_packet_available_S      : std_logic;
+signal pulse_data_read_after1clk_S   : std_logic;
+
+signal data64_pulse_packet_available_S : std_logic;
+signal data64_wave_in_available_S    : std_logic;
+signal wave_in_read_S                : std_logic;
+
+signal combine_pulse_S               : std_logic_vector((NROFFIBERS*NROFADCS)/(2*(ADCINDEXSHIFT+1))-1 downto 0) := (others => '0');
+
+		
+signal muxstat_outfifo_fullness_S    : array_fiber16bits_type := (others => (others => '0'));
+signal pulse_infifo_maxfullness_S    : array_fiber16bits_type := (others => (others => '0'));
+signal muxstat_infifo_fullness_S     : array_fiber16bits_type := (others => (others => '0'));
+signal pulse_outfifo_fullness_S      : std_logic_vector (15 downto 0) := (others => '0');
+signal wave_infifo_fullness_S        : array_fiber16bits_type := (others => (others => '0'));
+signal wave_outfifo_fullness_S       : std_logic_vector (15 downto 0) := (others => '0');
+signal SelectWaveMUXfullness_S       : std_logic := '0';
+signal SelectWaveMUXfullness_sync_S  : std_logic;
+
+signal latestsuperburst_write_S      : std_logic := '0';
+signal latestsuperburstnumber_S      : std_logic_vector (30 downto 0) := (others => '0');
+
+signal timestamperrors_S             : array_fiber10bits_type := (others => (others => '0'));
+signal skipped_pulses_S              : array_fiber10bits_type := (others => (others => '0'));
+signal dataerrors_S                  : array_fiber10bits_type := (others => (others => '0'));
+signal pulsemux_error_S              : std_logic;
+signal wavemux_error_S               : std_logic;
+signal pulsemux_error1_S             : std_logic;
+signal wavemux_error1_S              : std_logic;
+signal multiplexer_error_S           : std_logic;
+
+-- SlowControl to/from cpu
+signal IO_serialdata_S               : std_logic_vector(0 to NROFFIBERS-1);
+signal IO_serialavailable_S          : std_logic_vector(0 to NROFFIBERS-1);
+signal IO_byte_S                     : std_logic_vector (7 downto 0);
+signal IO_write_S                    : std_logic; 
+
+signal board_status_S                : array_muxregister_type;
+signal board_status_read_S           : std_logic_vector(0 to NROFMUXREGS-1);
+signal board_control_S               : array_muxregister_type;
+signal board_control_write_S         : std_logic_vector(0 to NROFMUXREGS-1);
+
+signal reset_timestampcounter_S      : std_logic;	
+signal SODA_enable_S                 : std_logic;	
+signal reset_timestampcounter0_S     : std_logic;	
+signal SODA_enable0_S                : std_logic;	
+signal reset_timestampcounter1_S     : std_logic;		
+signal reset_timestampcounter2_S     : std_logic;	
+
+signal SODA_cmd_word_S               : std_logic_vector(30 downto 0) := (others => '0');
+signal SODA_cmd_valid_S              : std_logic := '0';
+
+signal resetDone_S                   : std_logic_vector(0 to NROFFIBERS-1);
+signal txLocked_S                    : std_logic_vector(0 to NROFFIBERS-1);
+signal rxLocked_S                    : std_logic_vector(0 to NROFFIBERS-1);
+
+signal histogram_adcnumber_S         : std_logic_vector(15 downto 0) := x"0000";
+signal histogram_clear_S             : std_logic := '0';	
+signal histogram_startreading_S      : std_logic := '0';	
+signal histogram_data_S              : std_logic_vector(31 downto 0);
+signal histogram_read_S              : std_logic := '0';	
+signal histogram_available_S         : std_logic := '0';	
+signal histogram_startreading0_s     : std_logic := '0';	
+signal histogram_clear0_s            : std_logic := '0';	
+signal histogram_binning_s           : std_logic_vector(2 downto 0);
+
+signal extractdata_start_S           : std_logic := '0';	
+signal extractdata_make_selection_S  : std_logic := '0';	
+signal extractdata_bothgain_S        : std_logic := '0';
+signal extractdata_adcnumber_S       : std_logic_vector(15 downto 0);	
+signal extractdata_ready_S           : std_logic := '0';	
+signal extractdata_after1clk_ready_S : std_logic := '0';	
+signal extractdata_after1clk_ready0_S : std_logic := '0';	
+signal extractdata_select_S          : std_logic_vector(1 downto 0);
+signal extractdata_data_S            : std_logic_vector(31 downto 0);
+
+signal extractwave_start_S           : std_logic := '0';	
+signal extractwave_make_selection_S  : std_logic := '0';	
+signal extractwave_bothgain_S        : std_logic := '0';	
+signal extractwave_adcnumber_S       : std_logic_vector(15 downto 0);	
+signal extractwave_ready_S           : std_logic := '0';
+signal extractwave_after1clk_ready_S : std_logic := '0';
+signal extractwave_after1clk_ready0_S : std_logic := '0';
+signal extractwave_data_read_S       : std_logic := '0';	
+signal extractwave_data_S            : std_logic_vector(31 downto 0);
+
+signal serdes_txpll_clocks_S         : std_logic_vector(3 downto 0) := (others => '0');
+ 		
+signal check_error_S                 : std_logic_vector(0 to NROFFIBERS-1);
+signal wave_data_read_prev_S         : std_logic := '0';	
+signal check_error2_S                : std_logic := '0';	
+		
+signal testword0_S                   : array_fiber36bits_type := (others => (others => '0'));
+signal testword1_S                   : array_fiber36bits_type := (others => (others => '0'));
+signal testword2_S                   : array_fiber36bits_type := (others => (others => '0'));
+signal testPin_S                     : array_fiber4bits_type := (others => (others => '0'));
+signal testword0clock_S              : std_logic_vector(0 to NROFFIBERS-1);
+
+begin
+
+-- LEDs(0) <= '0';
+-- LEDs(1) <= resetDone_S(0);
+-- LEDs(2) <= txLocked_S(0);
+-- LEDs(3) <= rxLocked_S(0);
+-- LEDs(7 downto 4) <= testPin_S(0);
+
+process(slowcontrol_clock)
+variable counter_V : integer range 0 to 7 := 0;
+begin
+	if (rising_edge(slowcontrol_clock)) then 
+		reset_slowcontrolclock_s <= reset;
+	end if;
+end process;
+process(packet_in_clock)
+begin
+	if (rising_edge(packet_in_clock)) then 
+		reset_packet_in_clock_S <= reset;
+	end if;
+end process;
+process(packet_out_clock)
+begin
+	if (rising_edge(packet_out_clock)) then 
+		reset_packet_out_clock_S <= reset;
+	end if;
+end process;
+
+		
+DC_slow_control_TRB3_1: DC_slow_control_TRB3 port map(
+		rst => reset_slowcontrolclock_S,
+		clk => slowcontrol_clock,
+		BUS_READ_IN => BUS_READ_IN,
+		BUS_WRITE_IN => BUS_WRITE_IN,
+		BUS_BUSY_OUT => BUS_BUSY_OUT,
+		BUS_ACK_OUT => BUS_ACK_OUT,
+		BUS_ADDR_IN => BUS_ADDR_IN,
+		BUS_DATA_IN => BUS_DATA_IN,
+		BUS_DATA_OUT => BUS_DATA_OUT,
+		
+		io_data_in => IO_serialdata_S,
+		IO_data_in_available => IO_serialavailable_S,
+		io_data_out => IO_byte_S,
+		io_write_out => IO_write_S,
+
+		extract_data_available => extractdata_after1clk_ready_S,
+		extract_wave_available => extractwave_after1clk_ready_S,
+
+		board_status => board_status_S,
+		board_status_read => board_status_read_S,
+		board_control => board_control_S,
+		board_control_write => board_control_write_S,
+		testword0 => open);
+
+		
+-- ADDRESS_MUX_FIBERMODULE_STATUS : adr=0 in MUX_fibermodule_interface
+-- ADDRESS_MUX_SLOWCONTROL_SKIPPED : adr=1 not used anymore
+-- ADDRESS_MUX_MULTIPLEXER_STATUS : adr=2 in MUX_fibermodule_interface
+
+-- ADDRESS_MUX_SODA_CONTROL : adr=3 
+SODA_enable0_S <= board_control_S(conv_integer(ADDRESS_MUX_SODA_CONTROL(3 downto 0)))(0);
+reset_timestampcounter0_S <= board_control_S(conv_integer(ADDRESS_MUX_SODA_CONTROL(3 downto 0)))(1);
+EnableOutputFibre0_S <= board_control_S(conv_integer(ADDRESS_MUX_SODA_CONTROL(3 downto 0)))(4);
+EnableWaveformSending_S <= board_control_S(conv_integer(ADDRESS_MUX_SODA_CONTROL(3 downto 0)))(5);
+SelectWaveMUXfullness_S <= board_control_S(conv_integer(ADDRESS_MUX_SODA_CONTROL(3 downto 0)))(6);
+EnableExternalSODA <= board_control_S(conv_integer(ADDRESS_MUX_SODA_CONTROL(3 downto 0)))(7);
+reset_fibers0_S <= board_control_S(conv_integer(ADDRESS_MUX_SODA_CONTROL(3 downto 0)))(8);
+posedge_to_pulse_resetfibers: posedge_to_pulse port map(
+    clock_in => slowcontrol_clock,
+    clock_out => SODA_clock,
+    en_clk => '1',
+    signal_in => reset_fibers0_S,
+    pulse => reset_fibers_S);
+
+-- ADDRESS_MUX_HISTOGRAM : adr=4
+-- histogram_clear0_S <= board_control_S(conv_integer(ADDRESS_MUX_HISTOGRAM(3 downto 0)))(0);
+-- histogram_startreading0_S <= '1' when
+			-- (board_control_S(conv_integer(ADDRESS_MUX_HISTOGRAM(3 downto 0)))(1)='1')
+		-- and (board_control_write_S(conv_integer(ADDRESS_MUX_HISTOGRAM(3 downto 0)))='1')
+	-- else '0';
+-- histogram_binning_S <= board_control_S(conv_integer(ADDRESS_MUX_HISTOGRAM(3 downto 0)))(10 downto 8);
+-- histogram_adcnumber_S <= board_control_S(conv_integer(ADDRESS_MUX_HISTOGRAM(3 downto 0)))(31 downto 16);
+-- histogram_read_S <= board_status_read_S(conv_integer(ADDRESS_MUX_HISTOGRAM(3 downto 0)));
+-- board_status_S(conv_integer(ADDRESS_MUX_HISTOGRAM(3 downto 0))) <= histogram_data_S;
+
+-- ADDRESS_MUX_TIMESTAMP_ERRORS : adr=5 in MUX_fibermodule_interface
+
+
+-- ADDRESS_MUX_EXTRACTWAVE : adr=7
+extractwave_start_S <= board_control_write_S(conv_integer(ADDRESS_MUX_EXTRACTWAVE(3 downto 0)));
+extractwave_adcnumber_S <= board_control_S(conv_integer(ADDRESS_MUX_EXTRACTWAVE(3 downto 0)))(15 downto 0);
+extractwave_make_selection_S <= board_control_S(conv_integer(ADDRESS_MUX_EXTRACTWAVE(3 downto 0)))(16);
+extractwave_bothgain_S <= board_control_S(conv_integer(ADDRESS_MUX_EXTRACTWAVE(3 downto 0)))(17);
+board_status_S(conv_integer(ADDRESS_MUX_EXTRACTWAVE(3 downto 0))) 
+	<= ones(31 downto 0) when extractwave_after1clk_ready_S='0' else extractwave_data_S;
+extractwave_data_read_S <= '1' when (board_status_read_S(conv_integer(ADDRESS_MUX_EXTRACTWAVE(3 downto 0)))='1') and (extractwave_ready_S='1') else '0';
+
+extractwave_after1clk_ready_S <= '1' when (extractwave_after1clk_ready0_S='1') and (extractwave_start_S='0') else '0';
+process(slowcontrol_clock)
+variable counter_V : integer range 0 to 7 := 0;
+begin
+	if (rising_edge(slowcontrol_clock)) then 
+		if extractwave_start_S='1' then
+			counter_V := 0;
+			extractwave_after1clk_ready0_S <= '0';
+		elsif counter_V<7 then
+			counter_V := counter_V+1;
+			extractwave_after1clk_ready0_S <= '0';
+		else
+			extractwave_after1clk_ready0_S <= extractwave_ready_S;
+		end if;
+	end if;
+end process;
+
+-- ADDRESS_MUX_EXTRACTDATA : adr=8
+extractdata_start_S <= board_control_write_S(conv_integer(ADDRESS_MUX_EXTRACTDATA(3 downto 0)));
+extractdata_adcnumber_S <= board_control_S(conv_integer(ADDRESS_MUX_EXTRACTDATA(3 downto 0)))(15 downto 0);
+extractdata_make_selection_S <= board_control_S(conv_integer(ADDRESS_MUX_EXTRACTDATA(3 downto 0)))(16);
+extractdata_bothgain_S <= board_control_S(conv_integer(ADDRESS_MUX_EXTRACTDATA(3 downto 0)))(17);
+board_status_S(conv_integer(ADDRESS_MUX_EXTRACTDATA(3 downto 0))) 
+	<= ones(31 downto 0) when extractdata_after1clk_ready_S='0' else extractdata_data_S;
+
+extractdata_after1clk_ready_S <= '1' when (extractdata_after1clk_ready0_S='1') and (extractdata_start_S='0') else '0';
+process(slowcontrol_clock)
+variable counter_V : integer range 0 to 7 := 0;
+begin
+	if (rising_edge(slowcontrol_clock)) then 
+		if extractdata_start_S='1' then
+			counter_V := 0;
+			extractdata_after1clk_ready0_S <= '0';
+		elsif counter_V<7 then
+			counter_V := counter_V+1;
+			extractdata_after1clk_ready0_S <= '0';
+		else
+			extractdata_after1clk_ready0_S <= extractdata_ready_S;
+		end if;
+	end if;
+end process; 
+
+-- ADDRESS_MUX_SYSMON : adr=12 not used
+board_status_S(conv_integer(ADDRESS_MUX_SYSMON(3 downto 0))) <= (others => '0');
+txpll_clocks <= serdes_txpll_clocks_S;
+	
+-- ADDRESS_MUX_CROSSSWITCH : adr=0xd
+process(slowcontrol_clock)
+begin
+	if (rising_edge(slowcontrol_clock)) then
+		if reset_slowcontrolclock_S = '1' then 	
+			for i in 0 to NROFFIBERS*NROFADCS/(ADCINDEXSHIFT+1)-1 loop
+				combine_pulse_S <= (others => '0');
+			end loop;
+		else
+			if (board_control_write_S(conv_integer(ADDRESS_MUX_CROSSSWITCH(3 downto 0)))='1') then
+				for i in 0 to 31 loop
+					combine_pulse_S(i) <= board_control_S(conv_integer(ADDRESS_MUX_CROSSSWITCH(3 downto 0)))(i);
+				end loop;
+			end if;
+		end if;
+	end if;
+end process;
+
+-- ADDRESS_BOARDNUMBER : adr=0x2000 in MUX_fibermodule_interface
+
+process(slowcontrol_clock)
+begin
+	if (rising_edge(slowcontrol_clock)) then 
+		if reset_slowcontrolclock_S = '1' then 	
+			extractdata_select_S <= "00";
+		else
+			if extractdata_start_S='1' then
+				extractdata_select_S <= "00";
+			elsif (board_status_read_S(conv_integer(ADDRESS_MUX_EXTRACTDATA(3 downto 0)))='1') and (extractdata_after1clk_ready_S='1') then
+				extractdata_select_S <= extractdata_select_S+1;
+			end if;
+		end if;
+	end if;
+end process;
+
+posedge_to_pulse1: posedge_to_pulse port map(
+    clock_in => slowcontrol_clock,
+    clock_out => packet_out_clock,
+    en_clk => '1',
+    signal_in => histogram_clear0_S,
+    pulse => histogram_clear_S);
+posedge_to_pulse2: posedge_to_pulse port map(
+    clock_in => slowcontrol_clock,
+    clock_out => packet_out_clock,
+    en_clk => '1',
+    signal_in => histogram_startreading0_S,
+    pulse => histogram_startreading_S);
+
+
+SODA_sync: process(SODA_clock) -- synchronise SODA commands
+variable phase_V : std_logic := '0';
+begin
+	if (rising_edge(SODA_clock)) then 
+		if reset_SODAclock_S = '1' then
+			reset_timestampcounter_S <= '0';
+			reset_timestampcounter1_S <= '0';
+			reset_timestampcounter2_S <= '0';
+			SODA_enable_S <= '1';
+		else
+			if (reset_timestampcounter2_S='0') and (reset_timestampcounter1_S='1') then
+				reset_timestampcounter_S <= '1';
+			else
+				reset_timestampcounter_S <= '0';
+			end if;
+			reset_timestampcounter2_S <= reset_timestampcounter1_S;
+			reset_timestampcounter1_S <= reset_timestampcounter0_S;
+			SODA_enable_S <= SODA_enable0_S;
+		end if;
+		reset_SODAclock_S <= reset;
+	end if;
+end process;
+
+soda_packet_handler1 : soda_packet_handler
+	generic map (
+		SODA_16BIT_INTERFACE => SODA_16BIT_INTERFACE
+	)
+	port map(
+		SODACLK => SODA_clock,
+		RESET => reset_SODAclock_S,
+		CLEAR => '0',
+		CLK_EN => '1',
+		--Internal Connection
+		START_OF_SUPERBURST_OUT => SODA_TimeTagValid_S,
+		SUPER_BURST_NR_OUT => superburst_number_S,
+		SODA_CMD_VALID_OUT => soda_cmd_valid_S,
+		SODA_CMD_WORD_OUT => soda_cmd_word_S,
+		EXPECTED_REPLY_OUT => open,
+		CRC_VALID_OUT => open,
+		CRC_DATA_OUT => open,
+		RX_DLM_IN => TX_DLM(0),
+		RX_DLM_WORD_IN => TX_DLM_WORD(0)
+	);
+reset_timestamp_counter_S <= '1' when (SODA_cmd_valid_S='1') and (SODA_cmd_word_S=(30)) else '0'; -- reset timestamp to I/O pin
+--EnableDataTaking_S <= '1' when (SODA_cmd_valid_S='1') and (SODA_cmd_word_S=(29)) else '0';
+--DisableDataTaking_S <= '1' when (SODA_cmd_valid_S='1') and (SODA_cmd_word_S=(28)) else '0';
+
+sync_superburstupdate: posedge_to_pulse port map(
+    clock_in => SODA_clock,
+    clock_out => packet_in_clock,
+    en_clk => '1',
+    signal_in => SODA_TimeTagValid_S,
+    pulse => superburst_update_S);
+
+sync_superburstwrite: posedge_to_pulse port map(
+    clock_in => SODA_clock,
+    clock_out => packet_out_clock,
+    en_clk => '1',
+    signal_in => SODA_TimeTagValid_S,
+    pulse => latestsuperburst_write_S);
+sync_superburstwrite_process: process(packet_out_clock)
+begin
+	if (rising_edge(packet_out_clock)) then 
+		if latestsuperburst_write_S='1' then
+			latestsuperburstnumber_S <= superburst_number_S;
+		end if;
+	end if;
+end process;
+
+
+--MUX_fiber_module_generate: for index in 0 to (NROFFIBERS/2)-1 generate
+
+DC_Quad_fiber_module_all: DC_Quad_fiber_module port map(
+		slowcontrol_clock => slowcontrol_clock,
+		packet_clock => packet_in_clock,
+		MUX_clock => MUX_clock,
+		SODA_clock => SODA_clock,
+		reset => reset,
+		reset_fibers => reset_fibers_S,
+		channel => conv_std_logic_vector(0,4),
+		superburst_number => superburst_number_S,
+		superburst_update => superburst_update_S,
+
+-- txUsr clock
+		refClkOut => refClkOut,
+		refClk_OK => refClk_OK,	
+		txpll_clocks => serdes_txpll_clocks_S,
+	
+-- SlowControl to/from cpu
+		IO_byte => IO_byte_S,
+		IO_write => IO_write_S,
+		G0_IO_serialdata => IO_serialdata_S(0),
+		G0_IO_serialavailable => IO_serialavailable_S(0),
+		G1_IO_serialdata => IO_serialdata_S(1),
+		G1_IO_serialavailable => IO_serialavailable_S(1),
+		G2_IO_serialdata => IO_serialdata_S(2),
+		G2_IO_serialavailable => IO_serialavailable_S(2),
+		G3_IO_serialdata => IO_serialdata_S(3),
+		G3_IO_serialavailable => IO_serialavailable_S(3),
+		
+-- multiplexer status
+		G0_muxstat_infifo_fullness => muxstat_infifo_fullness_S(0),
+		muxstat_outfifo_fullness => muxstat_outfifo_fullness_S(0),
+		timestamp_errors => timestamperrors_S(0),
+		skipped_pulses => skipped_pulses_S(0),
+		dataerrors => dataerrors_S(0),
+
+-- Pulse data
+		G0_pulse_data_out => pulse_data_array_S(0),
+		G0_pulse_data_write => pulse_data_array_write_S(0),
+		G0_pulse_data_out_allowed => pulse_data_array_allowed_S(0),
+
+-- Wave data
+		G0_wave_data_out => wave_data_array_S(0),
+		G0_wave_data_write => wave_data_array_write_S(0),
+		G0_wave_data_out_allowed => wave_data_array_allowed_S(0),
+		
+-- Status
+		G0_resetDone => resetDone_S(0),
+		G0_txLocked => txLocked_S(0),
+		G0_rxLocked => rxLocked_S(0),
+
+-- SODA 
+		G0_TX_DLM => TX_DLM(0),
+		G0_TX_DLM_WORD => TX_DLM_WORD(0), 
+		G0_RX_DLM => RX_DLM(0),
+		G0_RX_DLM_WORD => RX_DLM_WORD(0),
+		
+-- fiber interface signals:
+		gtpClk => gtpClk,
+		gtpClkDiv2 => gtpClkDiv2,
+		G0_LOS => gtpLOS(0),
+		G0_gtpTxP => gtpTxP0(0),
+		G0_gtpTxN => gtpTxN0(0),
+		G0_gtpRxP => gtpRxP0(0),
+		G0_gtpRxN => gtpRxN0(0),
+
+-- multiplexer status
+		G1_muxstat_infifo_fullness => muxstat_infifo_fullness_S(1),
+
+-- Pulse data
+		G1_pulse_data_out => pulse_data_array_S(1),
+		G1_pulse_data_write => pulse_data_array_write_S(1),
+		G1_pulse_data_out_allowed => pulse_data_array_allowed_S(1),
+
+-- Wave data
+		G1_wave_data_out => wave_data_array_S(1),
+		G1_wave_data_write => wave_data_array_write_S(1),
+		G1_wave_data_out_allowed => wave_data_array_allowed_S(1),
+
+-- Status
+		G1_resetDone => resetDone_S(1),
+		G1_txLocked => txLocked_S(1),
+		G1_rxLocked => rxLocked_S(1),
+		
+-- SODA receive
+		G1_TX_DLM => TX_DLM(1),
+		G1_TX_DLM_WORD => TX_DLM_WORD(1), 
+		G1_RX_DLM => RX_DLM(1),
+		G1_RX_DLM_WORD => RX_DLM_WORD(1),
+		
+-- fiber interface signals:
+		G1_LOS => gtpLOS(1),
+		G1_gtpTxP => gtpTxP0(1),
+		G1_gtpTxN => gtpTxN0(1),
+		G1_gtpRxP => gtpRxP0(1),
+		G1_gtpRxN => gtpRxN0(1),
+
+-- multiplexer status
+		G2_muxstat_infifo_fullness => muxstat_infifo_fullness_S(2),
+
+-- Pulse data
+		G2_pulse_data_out => pulse_data_array_S(2),
+		G2_pulse_data_write => pulse_data_array_write_S(2),
+		G2_pulse_data_out_allowed => pulse_data_array_allowed_S(2),
+
+-- Wave data
+		G2_wave_data_out => wave_data_array_S(2),
+		G2_wave_data_write => wave_data_array_write_S(2),
+		G2_wave_data_out_allowed => wave_data_array_allowed_S(2),
+
+-- Status
+		G2_resetDone => resetDone_S(2),
+		G2_txLocked => txLocked_S(2),
+		G2_rxLocked => rxLocked_S(2),
+		
+-- SODA receive
+		G2_TX_DLM => TX_DLM(2),
+		G2_TX_DLM_WORD => TX_DLM_WORD(2), 
+		G2_RX_DLM => RX_DLM(2),
+		G2_RX_DLM_WORD => RX_DLM_WORD(2),
+		
+-- fiber interface signals:
+		G2_LOS => gtpLOS(2),
+		G2_gtpTxP => gtpTxP0(2),
+		G2_gtpTxN => gtpTxN0(2),
+		G2_gtpRxP => gtpRxP0(2),
+		G2_gtpRxN => gtpRxN0(2),
+	
+-- multiplexer status
+		G3_muxstat_infifo_fullness => muxstat_infifo_fullness_S(3),
+
+-- Pulse data
+		G3_pulse_data_out => pulse_data_array_S(3),
+		G3_pulse_data_write => pulse_data_array_write_S(3),
+		G3_pulse_data_out_allowed => pulse_data_array_allowed_S(3),
+
+-- Wave data
+		G3_wave_data_out => wave_data_array_S(3),
+		G3_wave_data_write => wave_data_array_write_S(3),
+		G3_wave_data_out_allowed => wave_data_array_allowed_S(3),
+
+-- Status
+		G3_resetDone => resetDone_S(3),
+		G3_txLocked => txLocked_S(3),
+		G3_rxLocked => rxLocked_S(3),
+		
+-- SODA receive
+		G3_TX_DLM => TX_DLM(3),
+		G3_TX_DLM_WORD => TX_DLM_WORD(3), 
+		G3_RX_DLM => RX_DLM(3),
+		G3_RX_DLM_WORD => RX_DLM_WORD(3),
+		
+-- fiber interface signals:
+		G3_LOS => gtpLOS(3),
+		G3_gtpTxP => gtpTxP0(3),
+		G3_gtpTxN => gtpTxN0(3),
+		G3_gtpRxP => gtpRxP0(3),
+		G3_gtpRxN => gtpRxN0(3),
+		
+		--Control Interface
+		SCI_DATA_IN => SCI_DATA_IN,
+		SCI_DATA_OUT => SCI_DATA_OUT,
+		SCI_ADDR => SCI_ADDR,
+		SCI_READ => SCI_READ,
+		SCI_WRITE => SCI_READ,
+		SCI_ACK => SCI_ACK,
+		SCI_NACK => SCI_NACK,
+
+-- tests		
+		LEDs_link_ok => LEDs_link_ok,
+		LEDs_rx => LEDs_rx,
+		LEDs_tx => LEDs_tx,
+		testword0 => open,
+		testword0clock => testword0clock_S(0),
+		testword1 => open, -- testword1_S(index*2),
+		testPin => open);
+
+
+testword0 <= testword0_S(0);
+testword0clock <= testword0clock_S(0); -- gtp_SODA_clockdiv2_S;
+
+muxstat_outfifo_fullness_generate: for index in 1 to NROFFIBERS-1 generate
+
+muxstat_outfifo_fullness_S(index) <= (others => '0');
+timestamperrors_S(index) <= (others => '0');
+skipped_pulses_S(index) <= (others => '0');
+dataerrors_S(index) <= (others => '0');
+
+end generate;
+
+
+sync_selectmuxfullness: process(MUX_clock)
+begin
+	if (rising_edge(MUX_clock)) then 
+		SelectWaveMUXfullness_sync_S <= SelectWaveMUXfullness_S;
+	end if;
+end process;
+muxstat_infifo_fullness_S <= pulse_infifo_maxfullness_S when SelectWaveMUXfullness_sync_S='0' else wave_infifo_fullness_S;
+muxstat_outfifo_fullness_S(0) <= pulse_outfifo_fullness_S when SelectWaveMUXfullness_sync_S='0' else wave_outfifo_fullness_S;
+
+DC_sorting_mux1: DC_sorting_mux port map(
+		inputclock => packet_in_clock,
+		MUXclock => MUX_clock,
+		outputclock => packet_out_clock,
+		reset => reset,
+		data_in => pulse_data_array_S,
+		data_in_write => pulse_data_array_write_S,
+		data_in_allowed => pulse_data_array_allowed_S,
+		fiber_index => fiber_index_S,
+		channel => mux_channel_S,
+		statusbyte => mux_statusbyte_S,
+		energy => mux_energy_S,
+		timefraction => mux_timefraction_S,
+		timestamp => mux_timestamp_S,
+		superburstnumber => mux_superburstnumber_S,
+		data_out_read => mux_data_out_read_S,
+		data_out_available => mux_data_out_available_S,
+		infifo_fullness => pulse_infifo_maxfullness_S,
+		outfifo_fullness => pulse_outfifo_fullness_S,
+		testword0 => open,
+		testword1 => open,
+		error => pulsemux_error_S);
+
+DC_combine_pulses1: DC_combine_pulses port map(
+		clock => packet_out_clock,
+		reset => reset_packet_out_clock_S,
+		combine_pulse => combine_pulse_S,
+		fiber_index_in => fiber_index_S,
+		channel_in => mux_channel_S,
+		statusbyte_in => mux_statusbyte_S,
+		energy_in => mux_energy_S,
+		timefraction_in => mux_timefraction_S,
+		timestamp_in => mux_timestamp_S,
+		superburstnumber_in => mux_superburstnumber_S,
+		data_in_read => mux_data_out_read_S,
+		data_in_available => mux_data_out_available_S,
+		channel_out => pulse_channel_S,
+		statusbyte_out => pulse_statusbyte_S,
+		energy_out => pulse_energy_S,
+		timefraction_out => pulse_timefraction_S,
+		timestamp_out => pulse_timestamp_S,
+		superburstnumber_out => pulse_superburstnumber_S,
+		data_out_read => pulse_packet_read_S,
+		data_out_available => pulse_packet_available_S
+		);
+
+
+		
+pulse_packet_read_S <= '1' when 
+		((EnableOutputFibre_S='1') and (pulse_packet_request_S='1') and (pulse_packet_available_S='1')) or  
+		((EnableOutputFibre_S='0') and (pulse_packet_available_S='1')) 
+	else '0';
+pulse_packet_write_S <= '1' when (pulse_data_read_after1clk_S='1') else '0';
+data64_pulse_packet_available_S <= pulse_packet_available_S when EnableOutputFibre_S='1' else '0';
+
+packet_read_process: process(packet_out_clock)
+begin
+	if (rising_edge(packet_out_clock)) then 
+		if reset_packet_out_clock_S = '1' then
+			pulse_data_read_after1clk_S <= '0';
+		else
+			pulse_data_read_after1clk_S <= pulse_packet_read_S;
+		end if;
+		EnableOutputFibre_S <= EnableOutputFibre0_S;
+	end if;
+end process;
+
+DC_wavemux1: DC_wavemux port map(
+		inputclock => packet_in_clock,
+		MUXclock => MUX_clock,
+		outputclock => packet_out_clock,
+		reset => reset,
+		data_in => wave_data_array_S,
+		data_in_write => wave_data_array_write_S,
+		data_in_wave_allowed => wave_data_array_allowed_S,
+		data_out => wave_data_S,
+		data_out_read => wave_data_read_S,
+		data_out_available => wave_data_available_S,
+		infifo_fullness => wave_infifo_fullness_S,
+		outfifo_fullness => wave_outfifo_fullness_S,
+		testword0 => open,
+		testword1 => open,
+		error => wavemux_error_S);
+		
+wave_data_read_S <= '1' when 
+			((EnableOutputFibre_S='1') and (EnableWaveformSending_S='1') 
+				and (wave_in_read_S='1') and (wave_data_available_S='1')) 
+		or  
+			(((EnableOutputFibre_S='0') or (EnableWaveformSending_S='0')) 
+				and ((wave_data_read0_S='1') and (wave_data_available_S='1')))
+	else '0';
+data64_wave_in_available_S <= wave_data_available_S 
+	when (EnableOutputFibre_S='1') and (EnableWaveformSending_S='1') 
+	else '0';
+	
+process(packet_out_clock)
+begin
+	if (rising_edge(packet_out_clock)) then 
+		if wave_data_available_S='1' then
+			wave_data_read0_S <= '1';
+		else
+			wave_data_read0_S <= '0';
+		end if;
+		wave_data_in_write_S <= wave_data_read_S;
+	end if;
+end process;
+	
+
+
+DC_data_wave_to_64bit1: DC_data_wave_to_64bit port map(
+		clock => packet_out_clock,
+		reset => reset_packet_out_clock_S,
+		latestsuperburstnumber => latestsuperburstnumber_S,
+		channel => pulse_channel_S,
+		statusbyte => pulse_statusbyte_S,
+		energy => pulse_energy_S,
+		timefraction => pulse_timefraction_S,
+		timestamp => pulse_timestamp_S,
+		superburstnumber => pulse_superburstnumber_S,
+		data_in_available => data64_pulse_packet_available_S,
+		data_in_read => pulse_packet_request_S,
+		wave_in => wave_data_S,
+		wave_in_available => data64_wave_in_available_S,
+		wave_in_read => wave_in_read_S,
+		data_out_allowed => data_out_allowed,
+		data_out => data_out,
+		data_out_write => data_out_write,
+		data_out_first => data_out_first,
+		data_out_last => data_out_last,
+		error => data_out_error,
+		testword0 => open,
+		testword1 => open);
+		
+-- DC_histogram1: DC_histogram port map(
+		-- write_clock => packet_out_clock,
+		-- read_clock => slowcontrol_clock,
+		-- reset => reset,
+		-- testword0 => open, -- testword2,
+		-- adcnumber => histogram_adcnumber_S,
+		-- clear => histogram_clear_S,
+		-- binning => histogram_binning_S,
+		-- channel => pulse_channel_S,
+		-- statusbyte => pulse_statusbyte_S,
+		-- energy => pulse_energy_S,
+		-- timefraction => pulse_timefraction_S,
+		-- timestamp => pulse_timestamp_S,
+		-- superburstnumber => pulse_superburstnumber_S,
+		-- pulse_data_write => pulse_packet_write_S,
+		-- histogram_startreading => histogram_startreading_S,
+		-- histogram_data => histogram_data_S,
+		-- histogram_read => histogram_read_S,
+		-- histogram_available => histogram_available_S);
+		
+posedge_to_pulse3: posedge_to_pulse port map(
+    clock_in => slowcontrol_clock,
+    clock_out => packet_out_clock,
+    en_clk => '1',
+    signal_in => pulsemux_error_S,
+    pulse => pulsemux_error1_S);
+posedge_to_pulse4: posedge_to_pulse port map(
+    clock_in => slowcontrol_clock,
+    clock_out => packet_out_clock,
+    en_clk => '1',
+    signal_in => wavemux_error_S,
+    pulse => wavemux_error1_S);
+multiplexer_error_S <= '1' when (pulsemux_error1_S='1') or (wavemux_error1_S='1') else '0';
+		
+DC_check_timestamp1: DC_check_timestamp port map(
+		clock => packet_out_clock,
+		reset => reset_packet_out_clock_S,
+		clear => histogram_clear_S,
+		channel => pulse_channel_S,
+		statusbyte => pulse_statusbyte_S,
+		energy => pulse_energy_S,
+		timefraction => pulse_timefraction_S,
+		timestamp => pulse_timestamp_S,
+		superburstnumber => pulse_superburstnumber_S,
+		pulse_data_write => pulse_packet_write_S,
+		multiplexer_error => multiplexer_error_S,
+		timestamp_errors => timestamperrors_S(0),
+		skipped_pulses => skipped_pulses_S(0),
+		dataerrors => dataerrors_S(0));
+	
+DC_extract_data1: DC_extract_data port map(
+		write_clock => packet_out_clock,
+		read_clock => slowcontrol_clock,
+		reset => reset,
+		start => extractdata_start_S,
+		make_selection => extractdata_make_selection_S,
+		dualgain => extractdata_bothgain_S,
+		adcnumber => extractdata_adcnumber_S,
+		channel => pulse_channel_S,
+		statusbyte => pulse_statusbyte_S,
+		energy => pulse_energy_S,
+		timefraction => pulse_timefraction_S,
+		timestamp => pulse_timestamp_S,
+		superburstnumber => pulse_superburstnumber_S,
+		pulse_data_write => pulse_packet_write_S,
+		ready => extractdata_ready_S,
+		pulse_data_select => extractdata_select_S,
+		pulse_data_out => extractdata_data_S,
+		testword0 => open);
+
+DC_extract_wave1: DC_extract_wave port map(
+		write_clock => packet_out_clock,
+		read_clock => slowcontrol_clock,
+		reset => reset,
+		start => extractwave_start_S,
+		make_selection => extractwave_make_selection_S,
+		dualgain => extractwave_bothgain_S,
+		adcnumber => extractwave_adcnumber_S,
+		wave_data_in => wave_data_S,
+		wave_data_in_write => wave_data_in_write_S,
+		ready => extractwave_ready_S,
+		wave_data_out => extractwave_data_S,
+		wave_data_out_read => extractwave_data_read_S,
+		testword0 => open);
+
+MUX_checkwave_all: for index in 0 to NROFFIBERS-1 generate
+
+MUX_checkwave1: MUX_checkwave port map(
+		clock => packet_in_clock,
+		reset => reset_packet_in_clock_S,
+		wave_in => wave_data_array_S(index),
+		wave_in_write => wave_data_array_write_S(index),
+		error => check_error_S(index));
+
+end generate;
+
+MUX_checkwave2: MUX_checkwave port map(
+		clock => packet_out_clock,
+		reset => reset_packet_out_clock_S,
+		wave_in => wave_data_S,
+		wave_in_write => wave_data_read_prev_S,
+		error => check_error2_S);
+
+
+process(packet_out_clock)
+begin
+	if (rising_edge(packet_out_clock)) then 
+		wave_data_read_prev_S <= wave_data_read_S;
+	end if;
+end process;
+
+
+testword1 <= testword1_S(0);
+testword2 <= (others => '0');
+
+		
+		
+end Behavioral;
diff --git a/data_concentrator/sources/DC_mux2to1.vhd b/data_concentrator/sources/DC_mux2to1.vhd
new file mode 100644
index 0000000..b95fd30
--- /dev/null
+++ b/data_concentrator/sources/DC_mux2to1.vhd
@@ -0,0 +1,324 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   25-02-2014
+-- Module Name:   DC_mux2to1
+-- Description:   compare timestamp of two hits and pass data on in right order
+-- Modifications:
+--   30-07-2014   Timestamp is now the time within the superburst
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+
+------------------------------------------------------------------------------------------------------
+-- DC_mux2to1
+--    Compare timestamp of two hits and pass data on in right order.
+--    If data from only one is available then this data is passed on directly
+--    The data consists of the members of a hit :
+--        fiber_index : index of the fiber from where the hit came from
+--        channel : number of the ADC
+--        statusbyte : 8 bits with status
+--        energy : energy (top value) of a hit
+--        timefraction : fractional part of the timestamp of a hit
+--        timestamp : integer part of the timestamp of a hit within the superburst, unit: sample-clock cycles
+--        superburstnumber : number of the superburst to which the hit belongs
+--
+--
+-- generics
+--     CF_FRACTIONBIT : number of valid constant fraction bits
+--		
+-- inputs
+--    clock : ADC sampling clock 
+--    reset : synchronous reset
+--    fiber_index1 : index of the fiber
+--    channel1 : data input 1 : adc channel
+--    statusbyte1 : data input 1 : status
+--    energy1 : data input 1 : pulse energy
+--    timefraction1 : data input 1 : Constant Fraction time
+--    timestamp1 : data input 1 : time
+--    superburstnumber1 : data input 1 : superburst number
+--    data1_in_write : write signal for data1_in
+--    data1_in_inpipe : more data available: wait with timestamp check until the timestamp is read
+--    fiber_index2 : index of the fiber
+--    channel2 : data input 2 : adc channel
+--    statusbyte2 : data input 2 : status
+--    energy2 : data input 2 : pulse energy
+--    timefraction2 : data input 2 : Constant Fraction time
+--    timestamp2 : data input 2 : time
+--    superburstnumber2 : data input 2 : superburst number
+--    data2_in_write : write signal for data2_in
+--    data2_in_inpipe : more data available: wait with timestamp check until the timestamp is read
+--    data_out_allowed : writing of resulting data allowed
+--			  
+-- outputs
+--    data1_in_allowed : signal to allow data input 1
+--    data2_in_allowed : signal to allow data input 2
+--    fiber_index : index of the fiber
+--    channel : data output : adc channel
+--    statusbyte : data output : status
+--    energy : data output : pulse energy
+--    timefraction : data output : Constant Fraction time
+--    timestamp : data output : time
+--    superburstnumber : data output : superburst number
+--    data_out_write : write signal for 36-bits output data
+--    data_out_inpipe : data available: in this module or at the input
+--    error : error in data bits 35..32
+--
+-- components
+--
+------------------------------------------------------------------------------------------------------
+
+
+
+entity DC_mux2to1 is
+ 	generic (
+		CF_FRACTIONBIT          : natural := 11
+	);
+   port (
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		fiber_index1            : in std_logic_vector(3 downto 0);
+		channel1                : in std_logic_vector(15 downto 0);
+		statusbyte1             : in std_logic_vector(7 downto 0);
+		energy1                 : in std_logic_vector(15 downto 0);
+		timefraction1           : in std_logic_vector(11 downto 0);
+		timestamp1              : in std_logic_vector(15 downto 0);
+		superburstnumber1       : in std_logic_vector(30 downto 0);
+		data1_in_write          : in std_logic;
+		data1_in_inpipe         : in std_logic;
+		data1_in_allowed        : out std_logic;
+		fiber_index2            : in std_logic_vector(3 downto 0);
+		channel2                : in std_logic_vector(15 downto 0);
+		statusbyte2             : in std_logic_vector(7 downto 0);
+		energy2                 : in std_logic_vector(15 downto 0);
+		timefraction2           : in std_logic_vector(11 downto 0);
+		timestamp2              : in std_logic_vector(15 downto 0);
+		superburstnumber2       : in std_logic_vector(30 downto 0);
+		data2_in_write          : in std_logic;
+		data2_in_inpipe         : in std_logic;
+		data2_in_allowed        : out std_logic;
+		fiber_index             : out std_logic_vector(3 downto 0);
+		channel                 : out std_logic_vector(15 downto 0);
+		statusbyte              : out std_logic_vector(7 downto 0);
+		energy                  : out std_logic_vector(15 downto 0);
+		timefraction            : out std_logic_vector(11 downto 0);
+		timestamp               : out std_logic_vector(15 downto 0);
+		superburstnumber        : out std_logic_vector(30 downto 0);
+		data_out_write          : out std_logic;
+		data_out_inpipe         : out std_logic;
+		data_out_allowed        : in std_logic;
+		error                   : out std_logic;
+		testword0               : out std_logic_vector(35 downto 0)
+		);
+end DC_mux2to1;
+
+
+architecture Behavioral of DC_mux2to1 is
+
+attribute syn_keep     : boolean;
+attribute syn_preserve : boolean;
+
+constant CHECK_FRACTIONTIME      : boolean := TRUE;
+constant TIMEOUTBITS             : integer := 12;
+signal timeout_counter_S         : std_logic_vector(TIMEOUTBITS-1 downto 0) := (others => '0');
+signal clear_timeout_counter_S   : std_logic := '0';
+signal inc_timeout_counter_S     : std_logic := '0';
+
+
+		
+signal error_S                   : std_logic;
+signal data1_in_write_S          : std_logic;
+signal data2_in_write_S          : std_logic;
+signal data_out_write_S          : std_logic;
+signal data1_in_inpipe_S         : std_logic;
+signal data2_in_inpipe_S         : std_logic;
+signal data_out_inpipe_S         : std_logic;
+signal data1_in_allowed_S        : std_logic;
+signal data2_in_allowed_S        : std_logic;
+signal data_out_allowed_S        : std_logic;
+signal data1_timestamp_valid_S   : std_logic := '0';
+signal data2_timestamp_valid_S   : std_logic := '0';
+signal timestamp_S               : std_logic_vector(15 downto 0) := (others => '0');
+signal timefraction_S            : std_logic_vector(11 downto 0) := (others => '0');
+
+
+signal outreg_filled_S           : std_logic := '0';
+
+signal time1equalorlarger_S      : std_logic := '0';
+signal time2equalorlarger_S      : std_logic := '0';
+
+attribute syn_keep of data1_in_write_S     : signal is true;
+attribute syn_preserve of data1_in_write_S : signal is true;
+attribute syn_keep of data2_in_write_S     : signal is true;
+attribute syn_preserve of data2_in_write_S : signal is true;
+attribute syn_keep of data_out_write_S     : signal is true;
+attribute syn_preserve of data_out_write_S : signal is true;
+
+attribute syn_keep of data1_in_inpipe_S     : signal is true;
+attribute syn_preserve of data1_in_inpipe_S : signal is true;
+attribute syn_keep of data2_in_inpipe_S     : signal is true;
+attribute syn_preserve of data2_in_inpipe_S : signal is true;
+attribute syn_keep of data_out_inpipe_S     : signal is true;
+attribute syn_preserve of data_out_inpipe_S : signal is true;
+
+attribute syn_keep of data1_in_allowed_S     : signal is true;
+attribute syn_preserve of data1_in_allowed_S : signal is true;
+attribute syn_keep of data2_in_allowed_S     : signal is true;
+attribute syn_preserve of data2_in_allowed_S : signal is true;
+attribute syn_keep of data_out_allowed_S     : signal is true;
+attribute syn_preserve of data_out_allowed_S : signal is true;
+
+
+begin
+
+data1_in_allowed <= data1_in_allowed_S;
+data2_in_allowed <= data2_in_allowed_S;
+data_out_allowed_S <= data_out_allowed;
+data1_in_write_S <= data1_in_write;
+data2_in_write_S <= data2_in_write;
+data_out_write <= data_out_write_S;
+data1_in_inpipe_S <= data1_in_inpipe;
+data2_in_inpipe_S <= data2_in_inpipe;
+data_out_inpipe <= data_out_inpipe_S;
+
+error <= error_S;
+timestamp <= timestamp_S;
+timefraction <= timefraction_S;
+
+data_out_write_S <= '1' when (outreg_filled_S='1') and (data_out_allowed_S='1') else '0';
+
+data_out_inpipe_S <= '1' when 
+		(data1_in_inpipe_S='1') or (data2_in_inpipe_S='1')  or
+		(outreg_filled_S='1') 
+	else '0';
+	
+--data1_in_allowed_S <= '1' when
+--		((data_out_allowed_S='1') or (outreg_filled_S='0')) and
+--		(data1_timestamp_valid_S='1')
+--	else '0';
+data1_in_allowed_S <= '1' when
+		(outreg_filled_S='0') and
+		(data1_timestamp_valid_S='1')
+	else '0';
+
+	
+--data2_in_allowed_S <= '1' when
+--		((data_out_allowed_S='1') or (outreg_filled_S='0')) and
+--		(data2_timestamp_valid_S='1') and
+--		(data1_in_write_S='0')
+--	else '0';
+data2_in_allowed_S <= '1' when
+		(outreg_filled_S='0') and
+		(data2_timestamp_valid_S='1') and
+		(data1_in_write_S='0')
+	else '0';
+
+
+gencomparetimeCF: if CHECK_FRACTIONTIME generate
+	time1equalorlarger_S <= '1' when 
+			(superburstnumber1>superburstnumber2) or
+			((superburstnumber1=superburstnumber2) and 
+				(timestamp1 & timefraction1(CF_FRACTIONBIT-1 downto 0)>=timestamp2 & timefraction2(CF_FRACTIONBIT-1 downto 0)))
+		else '0';
+	time2equalorlarger_S <= '1' when 
+			(superburstnumber2>superburstnumber1) or
+			((superburstnumber2=superburstnumber1) and 
+				(timestamp2 & timefraction2(CF_FRACTIONBIT-1 downto 0)>=timestamp1 & timefraction1(CF_FRACTIONBIT-1 downto 0)))
+		else '0';
+end generate;
+gencomparetime: if not CHECK_FRACTIONTIME generate
+	time1equalorlarger_S <= '1' when 
+			(superburstnumber1>superburstnumber2) or
+			((superburstnumber1=superburstnumber2) and 
+				(timestamp1>=timestamp2))
+		else '0';
+	time2equalorlarger_S <= '1' when 
+			(superburstnumber2>superburstnumber1) or
+			((superburstnumber2=superburstnumber1) and 
+				(timestamp2>=timestamp1))
+		else '0';
+end generate;
+
+
+data1_timestamp_valid_S <= '1' when -- when timestamp1<=timestamp2
+		((time2equalorlarger_S='1') and (data1_in_inpipe_S='1')) or 
+		(data2_in_inpipe_S='0') 
+	else '0';
+data2_timestamp_valid_S <= '1' when -- when timestamp2<=timestamp1
+		((time1equalorlarger_S='1') and (data2_in_inpipe_S='1')) or
+		(data1_in_inpipe_S='0') 
+	else '0';
+
+process(clock)
+begin
+	if rising_edge(clock) then	
+		clear_timeout_counter_S <= '0';
+		inc_timeout_counter_S <= '0';
+		if reset='1' then
+			error_S <= '0';
+			timestamp_S <= (others => '0');
+			timefraction_S <= (others => '0');
+		else
+			if data1_in_write_S='1' then
+				clear_timeout_counter_S <= '1';
+				fiber_index <= fiber_index1;
+				channel <= channel1;
+				statusbyte <= statusbyte1;
+				energy <= energy1;
+				timefraction_S <= timefraction1;
+				timestamp_S <= timestamp1;
+				superburstnumber <= superburstnumber1;
+				outreg_filled_S <= '1';
+				error_S <= '0';
+			elsif data2_in_write_S='1' then
+				clear_timeout_counter_S <= '1';
+				fiber_index <= fiber_index2;
+				channel <= channel2;
+				statusbyte <= statusbyte2;
+				energy <= energy2;
+				timefraction_S <= timefraction2;
+				timestamp_S <= timestamp2;
+				superburstnumber <= superburstnumber2;
+				outreg_filled_S <= '1';
+				error_S <= '0';
+			else
+				if data_out_write_S='1' then
+					outreg_filled_S <= '0';
+					clear_timeout_counter_S <= '1';
+				elsif outreg_filled_S='1' then
+					if timeout_counter_S(TIMEOUTBITS-1)='1' then
+						error_S <= '1';
+						outreg_filled_S <= '0';
+					else
+						inc_timeout_counter_S <= '1';
+					end if;
+				else
+					clear_timeout_counter_S <= '1';
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+process(clock)
+begin
+	if rising_edge(clock) then	
+		if (reset='1') or (clear_timeout_counter_S='1') then
+			timeout_counter_S <= (others => '0');
+		elsif inc_timeout_counter_S='1' then
+			timeout_counter_S <= timeout_counter_S+1;
+		end if;
+	end if;
+end process;
+
+testword0(35 downto 0) <= (others => '0');
+
+
+end Behavioral;
+
+
diff --git a/data_concentrator/sources/DC_pulse_cross_switch.vhd b/data_concentrator/sources/DC_pulse_cross_switch.vhd
new file mode 100644
index 0000000..ace55db
--- /dev/null
+++ b/data_concentrator/sources/DC_pulse_cross_switch.vhd
@@ -0,0 +1,102 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   25-02-2014
+-- Module Name:   DC_pulse_cross_switch
+-- Description:   Cross Switch to select which output should be connected to which input
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+USE work.panda_package.all;
+
+
+------------------------------------------------------------------------------------------------------
+-- DC_pulse_cross_switch
+--	  Cross Switch to select which output should be connected to which input
+--
+--
+-- generics
+--     NROFMUXINPUTS : number of inputs and outputs
+--     ADCINDEXSHIFT : ADC channel numbers lowest bit indicates the high or low gain ADC, 0=high, 1=low
+--		
+-- inputs
+--		clock : clock 
+--		pulse_data_in : array with 36-bits width pulse-data to be directed to selectable output
+--		pulse_data_in_write : array with write for input pulse-data 
+--		pulse_data_out_allowed : array with allow signals for pulse-data output
+--		selections : select for each output where the input should come from
+--			  
+-- outputs
+--		pulse_data_in_allowed : array with allow signals for pulse-data input
+--		pulse_data_out : array with 36-bits width pulse-data directed from one input
+--		pulse_data_out_write : array with write for output pulse-data 
+--
+-- components
+--
+------------------------------------------------------------------------------------------------------
+
+
+
+entity DC_pulse_cross_switch is
+	generic(
+		NROFMUXINPUTS           : natural := 64;
+		ADCINDEXSHIFT           : natural := 0
+	);
+    port ( 
+		clock                   : in std_logic;
+		pulse_data_in           : in array_fiberXadc36bits_type;
+		pulse_data_in_write     : in std_logic_vector(0 to NROFMUXINPUTS-1);
+		pulse_data_in_allowed   : out std_logic_vector(0 to NROFMUXINPUTS-1);
+		pulse_data_out          : out array_fiberXadc36bits_type;
+		pulse_data_out_write    : out std_logic_vector(0 to NROFMUXINPUTS-1);
+		pulse_data_out_allowed  : in std_logic_vector(0 to NROFMUXINPUTS-1);
+		selections              : in array_fiberXadcCrossSwitch_type;
+		reverse_selections      : in array_fiberXadcCrossSwitch_type
+	);	
+end DC_pulse_cross_switch;
+
+
+architecture Behavioral of DC_pulse_cross_switch is
+
+
+type chooseADC_type is array(0 to NROFMUXINPUTS-1) of integer range 0 to NROFMUXINPUTS-1;
+signal chooseADC_S               : chooseADC_type := (others => 0);
+signal rev_chooseADC_S           : chooseADC_type := (others => 0); 
+
+
+begin
+
+
+process(clock)
+begin
+	if rising_edge(clock) then	
+		for i in 0 to NROFMUXINPUTS-1 loop
+			chooseADC_S(i) <= conv_integer(unsigned(selections(i)));
+			rev_chooseADC_S(i) <= conv_integer(unsigned(reverse_selections(i)));
+			-- for j in 0 to NROFMUXINPUTS-1 loop
+				-- if conv_integer(unsigned(selections(j)))=i then
+					-- rev_chooseADC_S(i) <= j; -- calculate the reverse number: input number that is connected to selected output
+				-- end if;
+			-- end loop;
+		end loop;
+	end if;
+end process;
+
+-- gen_selections: for i in 0 to NROFMUXINPUTS-1 generate
+	-- pulse_data_out(i) <= pulse_data_in(chooseADC_S(i));
+	-- pulse_data_out_write(i) <= pulse_data_in_write(chooseADC_S(i));
+	-- pulse_data_in_allowed(i) <= pulse_data_out_allowed(rev_chooseADC_S(i));
+-- end generate;
+
+gen_selections: for i in 0 to NROFMUXINPUTS-1 generate
+	pulse_data_out(i) <= pulse_data_in(i);
+	pulse_data_out_write(i) <= pulse_data_in_write(i);
+	pulse_data_in_allowed(i) <= pulse_data_out_allowed(i);
+end generate;
+
+end Behavioral;
+
+
diff --git a/data_concentrator/sources/DC_read36bitsfifo.vhd b/data_concentrator/sources/DC_read36bitsfifo.vhd
new file mode 100644
index 0000000..e805087
--- /dev/null
+++ b/data_concentrator/sources/DC_read36bitsfifo.vhd
@@ -0,0 +1,260 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   25-02-2014
+-- Module Name:   DC_read36bitsfifo
+-- Description:   Breaks 36-bit data stream into its members
+-- Modifications:
+--   30-07-2014   Timestamp is now the time within the superburst
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- DC_read36bitsfifo
+-- The 36-bits input data is translated to its members as parallel data:
+--   channel : adc-index
+--   statusbyte : 8 bit status information
+--   energy : pulse energy
+--   timefraction : fraction part of the timestamp
+--   timestamp : 16 bits time within superburst, synchronised to master SODA clock
+--   superburstnumber : 31 bits superburstnumber, assigned by DC, based on time
+--
+-- The data is double buffered so that the next data can be read while the data is being processed.
+-- A signal that indicates if more data is in the buffer is passed on.
+--
+--
+-- Library:
+--     work.panda_package: types and constants
+--
+-- Generics:
+--
+-- Inputs:
+--     clock : clock for input and output data
+--     reset : reset
+--     data_in : input data :
+--        word0 : 0 & 0000 & timestamp(15..0)
+--        word1 : 1 & 0 & superburstnumber(30..0)
+--        word2 : 2 & statusbyte & 00 & adcnumber
+--        word3 : 3 & timefraction & energy
+--     data_in_available : input data available (NOT fifo-empty from connected fifo)
+--     data_out_allowed : allowed to write output data
+-- 
+-- Outputs:
+--     data_in_read : read signal for input data (read for connected fifo)
+--     channel : adc-index
+--     statusbyte : 8 bit status information
+--     energy : pulse energy
+--     timefraction : fraction part of the timestamp
+--     timestamp : 16 bits timestamp within superburst, synchronised to master SODA clock
+--     superburstnumber : superburst index number where the data is assigned to
+--     data_out_write : write signal for output data
+--     data_out_trywrite : output is trying to write data, but data_out_allowed is preventing this
+--     data_out_inpipe : more data available in near future
+--     error : data error
+-- 
+-- Components:
+--
+--
+--
+----------------------------------------------------------------------------------
+
+entity DC_read36bitsfifo is
+	port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(35 downto 0);
+		data_in_available       : in std_logic;
+		data_in_read            : out std_logic;
+		channel                 : out std_logic_vector(15 downto 0);
+		statusbyte              : out std_logic_vector(7 downto 0);
+		energy                  : out std_logic_vector(15 downto 0);
+		timefraction            : out std_logic_vector(11 downto 0);
+		timestamp               : out std_logic_vector(15 downto 0);
+		superburstnumber        : out std_logic_vector(30 downto 0);
+		data_out_write          : out std_logic;
+		data_out_trywrite       : out std_logic;
+		data_out_inpipe         : out std_logic;
+		data_out_allowed        : in std_logic;
+		error                   : out std_logic);
+end DC_read36bitsfifo;
+
+
+architecture Behavioral of DC_read36bitsfifo is
+
+attribute syn_keep     : boolean;
+attribute syn_preserve : boolean;
+
+signal data_in_available_S    : std_logic := '0';
+signal data_in_read_S         : std_logic := '0';
+signal data_in_read_prev_S    : std_logic := '0';
+signal data_out_inpipe_S      : std_logic := '0';
+signal data_out_write_S       : std_logic := '0';
+signal data_out_trywrite_S    : std_logic := '0';
+signal data_out_allowed_S     : std_logic := '0';
+signal error_S                : std_logic := '0';
+signal data_in_index_S        : integer range 0 to 3 := 0;
+signal writebuf_S             : std_logic := '0';
+signal try_writebuf_S         : std_logic := '0';
+signal buf_filled_S           : std_logic := '0';
+signal channel_S              : std_logic_vector(15 downto 0);
+signal statusbyte_S           : std_logic_vector(7 downto 0);
+signal energy_S               : std_logic_vector(15 downto 0);
+signal timefraction_S         : std_logic_vector(11 downto 0);
+signal timestamp_S            : std_logic_vector(15 downto 0) := (others => '0');
+signal timestamp_out_S        : std_logic_vector(15 downto 0) := (others => '0');
+signal superburstnumber_S     : std_logic_vector(30 downto 0);
+
+
+attribute syn_keep of data_in_available     : signal is true;
+attribute syn_preserve of data_in_available : signal is true;
+attribute syn_keep of data_in_read_S     : signal is true;
+attribute syn_preserve of data_in_read_S : signal is true;
+attribute syn_keep of data_out_inpipe_S     : signal is true;
+attribute syn_preserve of data_out_inpipe_S : signal is true;
+attribute syn_keep of data_out_write_S     : signal is true;
+attribute syn_preserve of data_out_write_S : signal is true;
+attribute syn_keep of data_out_allowed_S     : signal is true;
+attribute syn_preserve of data_out_allowed_S : signal is true;
+
+
+begin
+
+data_in_available_S <= data_in_available;
+data_in_read <= data_in_read_S;
+data_out_inpipe <= data_out_inpipe_S;
+data_out_write <= data_out_write_S;
+data_out_allowed_S <= data_out_allowed;
+
+error <= error_S;
+timestamp <= timestamp_out_S;
+data_out_trywrite <= data_out_trywrite_S;
+
+data_in_read_S <= '1' when 
+		(((try_writebuf_S='1') and (writebuf_S='1')) or
+		((data_in_index_S=1) or (data_in_index_S=2)) or
+		((data_in_index_S=3) and (buf_filled_S='0')) or
+		((data_in_index_S=0) and (buf_filled_S='0'))) and
+		(data_in_available_S='1') 
+	else '0';
+		
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		if (data_in_available_S='1') or (data_in_read_prev_S='1') or (buf_filled_S='1') or (data_in_read_S='1') or (data_in_index_S/=0) then
+			data_out_inpipe_S <= '1';
+		else
+			data_out_inpipe_S <= '0';
+		end if;
+	end if;
+end process;
+	
+-- data_out_inpipe_S <= '1' when (data_in_available_S='1') or (data_in_read_prev_S='1') or (buf_filled_S='1') or
+	-- (data_in_read_S='1') or (data_in_index_S/=0) else '0';
+
+data_out_write_S <= '1' when (data_out_allowed_S='1') and (data_out_trywrite_S='1') else '0';
+
+writebuf_S <= '1' when 
+		((try_writebuf_S='1') and (buf_filled_S='0')) or 
+		((try_writebuf_S='1') and (data_out_write_S='1')) 		
+	else '0';
+
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if (reset = '1') then 
+			buf_filled_S <= '0';
+			timestamp_out_S <= (others => '0');
+		else
+			if writebuf_S='1' then
+				buf_filled_S <= '1';
+				channel <= channel_S;
+				statusbyte <= statusbyte_S;
+				energy <= energy_S;
+				timefraction <= timefraction_S;
+				timestamp_out_S <= timestamp_S;
+				superburstnumber <= superburstnumber_S;
+				data_out_trywrite_S <= '1';
+			else
+				if data_out_write_S='1' then
+					buf_filled_S <= '0';
+					data_out_trywrite_S <= '0';
+				end if;
+			end if;		
+		end if;
+	end if;
+end process;
+
+
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		data_in_read_prev_S <= data_in_read_S;
+		if (reset = '1') then 
+			error_S <= '0';
+			data_in_index_S <= 0;
+			try_writebuf_S <= '0';
+			timestamp_S <= (others => '0');
+		else
+			if data_in_read_prev_S='1' then
+				case data_in_index_S is
+					when 0 => --        word0 : 0 & 0000 & timestamp(15..0)
+						try_writebuf_S <= '0';
+						if data_in(35 downto 32) /= "0000" then
+							error_S <= '1';
+							data_in_index_S <= 0;
+						else
+							timestamp_S(15 downto 0) <= data_in(15 downto 0);
+							error_S <= '0';
+							data_in_index_S <= 1;
+						end if;
+					when 1 => --        word1 : 1 & 00 & superburstnumber(30..0)
+						try_writebuf_S <= '0';
+						if data_in(35 downto 32) /= "0001" then
+							error_S <= '1';
+							data_in_index_S <= 0;
+						else
+							error_S <= '0';
+							superburstnumber_S <= data_in(30 downto 0);
+							data_in_index_S <= 2;
+						end if;
+					when 2 => --        word2 : 2 & statusbyte & 00 & adcnumber
+						try_writebuf_S <= '0';
+						if data_in(35 downto 32) /= "0010" then
+							error_S <= '1';
+							data_in_index_S <= 0;
+						else
+							channel_S <= data_in(15 downto 0);
+							statusbyte_S <= data_in(31 downto 24);
+							error_S <= '0';
+							data_in_index_S <= 3;
+						end if;
+					when 3 => --        word3 : 3 & timefraction & energy
+						if data_in(35 downto 32) /= "0011" then
+							try_writebuf_S <= '0';
+							error_S <= '1';
+							data_in_index_S <= 0;
+						else
+							energy_S <= data_in(15 downto 0);
+							timefraction_S <= data_in(27 downto 16);
+							error_S <= '0';
+							data_in_index_S <= 0;
+							try_writebuf_S <= '1';
+						end if;
+					when others => 
+				end case;
+			else
+				if (try_writebuf_S='1') and (writebuf_S='1') then
+					try_writebuf_S <= '0';
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+end Behavioral;
+
diff --git a/data_concentrator/sources/DC_separate_data.vhd b/data_concentrator/sources/DC_separate_data.vhd
new file mode 100644
index 0000000..61712e9
--- /dev/null
+++ b/data_concentrator/sources/DC_separate_data.vhd
@@ -0,0 +1,454 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   04-03-2014
+-- Module Name:   DC_separate_data 
+-- Description:   Read and interprets data from Front End Electronics
+-- Modifications:
+--   30-07-2014   Timestamp from FEE is now composed by 16 bits superburstnumber and timestamp counter within superburst
+--   11-09-2014   New fiber data structure; moved functionality to several modules
+--   18-09-2014   different clock for loading
+--   11-10-2014   Energy is measured with integral, not with the maximum
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- DC_separate_data
+-- Gets packet data from the fiber receive module and analyses them.
+-- The hit data is processed: two CF-samples are used to calculate the time-fraction.
+-- With a Look Up Table this timefraction is corrected for non-linearity.
+--
+-- The timestamp (superburst part, integer part and fraction) is corrected for the delay of SODA signals
+-- and data transmission with a Look Up Table.
+-- The energy is adjusted with for each ADC channel a gain and offset value in a Look Up Table.
+-- Slowcontrol should fill in the two LUTs.
+-- Each pulse is assigned to a superburst number, based on timestamp.
+-- 
+--
+-- Three types of packets are possible:
+--
+-- The data packets : 4 32-bit words, with CRC8 in last word
+--   0xDA ADCnumber(7..0) superburstnumber(15..0)
+--   0000 energy(15..0)
+--   CF_before(15..0) CF_after(15..0)
+--   timestamp(15..0) statusbyte(7..0) CRC8(7..0)
+--
+-- The slow control packets : 2 32-bit words, with CRC8 in last word
+--   0x5C address(7..0) replybit 0000000 data(31..24)
+--   data(23..0) CRC8(7..0)
+--
+-- The waveform packets : 32-bit words, with CRC8 in last word
+--   0xAF ADCnumber(7..0) superburstnumber(15..0)
+--   timestamp(15..0) 0x00 statusbyte(7..0)
+--   0 adc0(14..0) 0 adc1(14..0) : 2 adc-samples 15 bits signed
+--   0 adc2(14..0) 0 adc3(14..0) : next 2 adc-samples 15 bits signed
+--   .........
+--   1 adcn(14..0) 1 00 CRC8(7..0) : last 32-bit word: last adc-sample 15 bits signed
+--         or
+--   0 0000 1 00 CRC8(7..0) : last 32-bit word: no sample--
+--
+-- The slow-control commands are written as parallel data and address. It should be connected to a fifo 
+-- that is large enough to handle all slow-control data, otherwise commands will be lost.
+-- The pulse-data in the data packets will be sent to a multiplexer (MUX).
+--
+-- The timeshift Look Up Table has 31 bits data:
+--   bit 30.. 16 : correction for the integer part
+--   bit CF_FRACTIONBIT-1..0 : correction for the fraction part
+--
+-- The Energy correction Look Up Table has 31 bits data:
+--   bit 30..16 : offset correction (signed)
+--   bit 15..0 : gain correction
+--   equation:  energy = ((original_energy+offset) * gainfactor)>>scalingbits 
+--
+--
+-- Library:
+--     work.panda_package :  for type declarations and constants
+-- 
+-- Generics:
+--     NROFADCS : number of ADCs in the FEE: total high and low gain ADCs 
+--     ADCBITS : number of ADC-bits
+--     ADCINDEXSHIFT : ADC channel numbers lowest bit indicates the high or low gain ADC, 0=high, 1=low
+--     CF_FRACTIONBIT : number of valid constant fraction bits
+--     ENERGYSCALINGBITS : number of scaling bits for energy adjustment: energy = (original_energy * gainfactor<<scalingbits)>>scalingbits
+--     MAX_DIVIDERSCALEBITS : number of scaling bits for division two largest samples
+--     MAX_LUTSIZEBITS : number of bits the maximum correction Look Up Table
+--     MAX_LUTSCALEBITS : number of scaling bits for the correction on the maximum (energy)
+-- 
+-- Inputs:
+--     clock : clock input : fiber receiver clock
+--     load_clock : clock for loading
+--     SODA_clock : clock SODA, used to update superburst
+--     reset : synchronous reset
+--     enable : enable datareading from receiver
+--     timeshiftLUT_write : write signal for Look Up Table time-correction for each adc-channel
+--     timeshiftLUT_loading : high : load LUT mode, low : normal correction mode
+--     timeshiftLUT_data : correction data to be written in the LUT
+--     energyLUT_write : write signal for Look Up Table energy adjustment for each adc-channel
+--     energytLUT_loading : high : load LUT mode, low : normal correction mode
+--     energyLUT_data : correction data to be written in the LUT: bit15..0=gainfactor(>>scalingbits), bit30..16=offset
+--     max_correction : use correction on maximum value with Look Up Table
+--     max_LUT_offset : offset for index in maximum correction Look Up Table
+--     max_LUT_loading : set in mode for loading a new maximum correction Look Up Table
+--     max_LUT_write : write next value in maximum correction Look Up Table
+--     fraction_correction : use correction on timestamp fraction with Look Up Table
+--     fraction_LUT_loading : set in mode for loading a new timestamp fraction correction Look Up Table
+--     fraction_LUT_write : write next value in timestamp fraction correction Look Up Table
+--     LUT_data_in : data for writing in the selected LUT : maximum correction or timestamp fraction correction
+--     packet_data_in : 32 bits data input from fiber module
+--     packet_data_present : data available from fiber module
+--     pulse_data_out_allowed : output data writing (4 words) allowed  : not fifo-almostfull of connected fifo
+--     wave_data_out_allowed : output of full waveform writing allowed : possible to write 254 samples!!
+--     FEEboardnumber : number of the board, this will be added to the ADC channel number for the final ADC channel identification
+--     superburst_number : most recent superburst-number
+--     superburst_update : new most recent superburst-number+timestamp
+-- 
+-- Outputs:
+--     packet_data_read : read signal to fiber module to read next data
+--     pulse_data_out : data with pulse results; 4 sequential 36-bits words with bits 35..32 as index
+--         word0 : 0 & 0000 & timestamp(15..0) (time within superburst)
+--         word1 : 1 & 0 & superburstnumber(30..0)
+--         word2 : 2 & statusbyte & 00 & adcnumber
+--         word3 : 3 & timefraction & energy
+--     pulse_data_write :  pulse data write signal
+--     slowcontrol_data : slow-control command : data 32-bits 
+--     slowcontrol_address : slow-control command : address 8-bits (only part for FEE)
+--     slowcontrol_reply : indicates if the slow-control is a reply, or a independent message
+--     slowcontrol_write : write of slow-control data/address/reply
+--     wave_data_out : data with waveform: 36-bits words with bits 35..32 as index
+--        	bits(35..32)="0000" : bits(15..0)=timestamp within superburst of waveform
+--        	bits(35..32)="0001" : bits(31)=0 bits(30..0)=SuperBurst number
+--        	bits(35..32)="0010" : 
+--              bits(31..24) = statusbyte (bit7=overflow) 
+--              bits(23..16) = 00
+--              bits(15..0) = adcnumber (channel identification)
+--        	bits(35..32)="0011" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+--        	bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+--        	bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+--        	bits(35..32)="1111" : error: buffer full, waveform not valid
+--     wave_data_write :  waveform data write signal
+--     error : error in packet-data : CRC-error, error in data bits
+--     pulse_data_skipped : data remove due to full connected fifo
+--
+-- Components:
+--     DC_split_data : splits incoming packets into pulse data members, waveform packets and slow-control reply commands
+--     DC_CF_MAX_correction : calculate the maximum and time-fraction with Look Up Tables
+--     DC_time_energy_LUTs : correction for time and energy: offset for time and gain/offset for energy with LUTs
+-- 
+----------------------------------------------------------------------------------
+
+entity DC_separate_data is
+	generic (
+		NROFADCS                : natural := 32;
+		ADCBITS                 : natural := 14;
+		ADCINDEXSHIFT           : natural := 1;
+		CF_FRACTIONBIT          : natural := 11;
+		ENERGYSCALINGBITS       : natural := 13;
+		MAX_DIVIDERSCALEBITS    : natural := 12;
+		MAX_LUTSIZEBITS         : natural := 8;
+		MAX_LUTSCALEBITS        : natural := 14
+	);
+    Port ( 
+		clock                   : in  std_logic;
+		load_clock              : in std_logic;
+		SODA_clock              : in  std_logic;
+		reset                   : in  std_logic;
+		enable                  : in  std_logic;
+		
+		timeshiftLUT_write      : in  std_logic;
+		timeshiftLUT_loading    : in  std_logic;
+		timeshiftLUT_data       : in  std_logic_vector (30 downto 0);
+		
+		energyLUT_write         : in  std_logic;
+		energytLUT_loading      : in  std_logic;
+		energyLUT_data          : in  std_logic_vector (30 downto 0);
+		
+		max_correction          : in std_logic;
+		max_LUT_offset          : in std_logic_vector(MAX_LUTSIZEBITS-1 downto 0);
+		max_LUT_loading         : in std_logic;
+		max_LUT_write           : in std_logic;
+		
+		fraction_correction     : in std_logic;
+		fraction_LUT_loading    : in std_logic;
+		fraction_LUT_write      : in std_logic;
+		LUT_data_in             : in std_logic_vector(CF_FRACTIONBIT-1 downto 0);
+		
+		packet_data_in          : in  std_logic_vector (31 downto 0);
+		packet_data_present     : in  std_logic;
+		packet_data_read        : out std_logic;
+		
+		pulse_data_out          : out std_logic_vector(35 downto 0);
+		pulse_data_write        : out std_logic;
+		pulse_data_out_allowed  : in  std_logic;
+		
+		slowcontrol_data        : out std_logic_vector (31 downto 0);
+		slowcontrol_address     : out std_logic_vector (7 downto 0);
+		slowcontrol_reply       : out std_logic;
+		slowcontrol_write       : out std_logic;
+		
+		wave_data_out           : out std_logic_vector(35 downto 0);
+		wave_data_write         : out std_logic;
+		wave_data_out_allowed   : in std_logic;
+		
+		FEEboardnumber          : in std_logic_vector (15 downto 0);
+		superburst_number       : in std_logic_vector(30 downto 0);
+		superburst_update       : in std_logic;
+		
+		error                   : out std_logic;
+		pulse_data_skipped      : out std_logic;
+		testword0               : out std_logic_vector (35 downto 0));
+end DC_separate_data;
+
+architecture Behavioral of DC_separate_data is
+
+component DC_split_data is
+	generic (
+		NROFADCS                : natural := NROFADCS;
+		ADCINDEXSHIFT           : natural := ADCINDEXSHIFT;
+		CF_FRACTIONBIT          : natural := CF_FRACTIONBIT
+	);
+    Port ( 
+		clock                   : in std_logic;
+		SODA_clock              : in  std_logic;
+		reset                   : in std_logic;
+		enable                  : in std_logic;
+		FEEboardnumber          : in std_logic_vector (15 downto 0);
+		packet_data_in          : in std_logic_vector (31 downto 0);
+		packet_data_present     : in std_logic;
+		packet_data_read        : out std_logic;
+		pulse_superburst        : out std_logic_vector(15 downto 0);
+		pulse_timestamp         : out std_logic_vector(15 downto 0);
+		pulse_adcnumber         : out std_logic_vector(15 downto 0);
+		pulse_statusbyte        : out std_logic_vector(7 downto 0);
+		pulse_energy            : out std_logic_vector(15 downto 0);
+		pulse_CF_before         : out std_logic_vector(15 downto 0);
+		pulse_CF_after          : out std_logic_vector(15 downto 0);
+		pulse_allowed           : in std_logic;
+		pulse_write             : out std_logic;
+		slowcontrol_data        : out std_logic_vector(31 downto 0);
+		slowcontrol_address     : out std_logic_vector(7 downto 0);
+		slowcontrol_reply       : out std_logic;
+		slowcontrol_write       : out std_logic;			  
+		wave_data_out           : out std_logic_vector(35 downto 0);
+		wave_data_write         : out std_logic;
+		wave_data_out_allowed   : in std_logic;
+		superburst_number       : in std_logic_vector(30 downto 0);
+		superburst_update       : in std_logic;
+		pulse_data_skipped      : out std_logic;
+		data_error              : out std_logic;
+		testword0               : out std_logic_vector(35 downto 0));
+end component;
+
+component DC_CF_MAX_correction is
+	generic (
+		ADCBITS                 : natural := ADCBITS;
+		CF_FRACTIONBIT          : natural := CF_FRACTIONBIT;
+		MAX_DIVIDERSCALEBITS    : natural := MAX_DIVIDERSCALEBITS;
+		MAX_LUTSIZEBITS         : natural := MAX_LUTSIZEBITS;
+		MAX_LUTSCALEBITS        : natural := MAX_LUTSCALEBITS
+		);
+    Port (
+		clock                   : in std_logic;
+		load_clock              : in std_logic;
+		reset                   : in std_logic;
+		pulse_superburst        : in std_logic_vector(15 downto 0);
+		pulse_timestamp         : in std_logic_vector(15 downto 0);
+		pulse_adcnumber         : in std_logic_vector(15 downto 0);
+		pulse_statusbyte        : in std_logic_vector(7 downto 0);
+		pulse_energy            : in std_logic_vector(15 downto 0);
+		pulse_CF_before         : in std_logic_vector(15 downto 0);
+		pulse_CF_after          : in std_logic_vector(15 downto 0);
+		pulse_allowed           : out std_logic;
+		pulse_write             : in std_logic;
+		max_correction          : in std_logic;
+		max_LUT_offset          : in std_logic_vector(MAX_LUTSIZEBITS-1 downto 0);
+		max_LUT_loading         : in std_logic;
+		max_LUT_write           : in std_logic;
+		fraction_correction     : in std_logic;
+		fraction_LUT_loading    : in std_logic;
+		fraction_LUT_write      : in std_logic;
+		LUT_data_in             : in std_logic_vector(CF_FRACTIONBIT-1 downto 0);
+		result_write            : out std_logic;
+		result_allowed          : in std_logic;
+		adcnumber               : out std_logic_vector(15 downto 0);
+		superburst              : out std_logic_vector(15 downto 0);
+		timestamp               : out std_logic_vector(15 downto 0);
+		timefraction            : out std_logic_vector(CF_FRACTIONBIT-1 downto 0);
+		energy                  : out std_logic_vector(15 downto 0);
+		statusbyte              : out std_logic_vector(7 downto 0);
+		testword0               : out std_logic_vector(35 downto 0);
+		testword1               : out std_logic_vector(35 downto 0)
+		);
+end component;
+
+component DC_time_energy_LUTs is
+	generic (
+		NROFADCS                : natural := NROFADCS;
+		ADCINDEXSHIFT           : natural := ADCINDEXSHIFT;
+		CF_FRACTIONBIT          : natural := CF_FRACTIONBIT;
+		ENERGYSCALINGBITS       : natural := ENERGYSCALINGBITS
+	);
+    Port ( 
+		clock                   : in  std_logic;
+		load_clock              : in std_logic;
+		SODA_clock              : in  std_logic;
+		reset                   : in  std_logic;
+		enable                  : in  std_logic;
+		timeshiftLUT_write      : in  std_logic;
+		timeshiftLUT_loading    : in  std_logic;
+		timeshiftLUT_data       : in  std_logic_vector (30 downto 0);
+		energyLUT_write         : in  std_logic;
+		energytLUT_loading      : in  std_logic;
+		energyLUT_data          : in  std_logic_vector (30 downto 0);
+		
+		datain_write            : in std_logic;
+		datain_allowed          : out std_logic;
+		adcnumber               : in std_logic_vector(15 downto 0); -- should be 1 clockcycle valid before datain_write
+		superburst              : in std_logic_vector(15 downto 0);
+		timestamp               : in std_logic_vector(15 downto 0);
+		timefraction            : in std_logic_vector(CF_FRACTIONBIT-1 downto 0);
+		energy                  : in std_logic_vector(15 downto 0);
+		statusbyte              : in std_logic_vector(7 downto 0);
+
+		pulse_data_out          : out std_logic_vector(35 downto 0);
+		pulse_data_write        : out std_logic;
+		pulse_data_out_allowed  : in  std_logic;
+		pulse_data_skipped      : out std_logic;
+		superburst_number       : in std_logic_vector(30 downto 0);
+		superburst_update       : in std_logic;
+		testword0               : out std_logic_vector (35 downto 0));
+end component;
+
+signal pulse_superburst_S      : std_logic_vector(15 downto 0);
+signal pulse_timestamp_S       : std_logic_vector(15 downto 0);
+signal pulse_adcnumber_S       : std_logic_vector(15 downto 0);
+signal pulse_statusbyte_S      : std_logic_vector(7 downto 0);
+signal pulse_energy_S          : std_logic_vector(15 downto 0);
+signal pulse_CF_before_S       : std_logic_vector(15 downto 0);
+signal pulse_CF_after_S        : std_logic_vector(15 downto 0);
+signal pulse_allowed_S         : std_logic;
+signal pulse_write_S           : std_logic;
+
+signal pulse_data_skipped1_S   : std_logic;
+signal pulse_data_skipped2_S   : std_logic;
+signal data_error_S            : std_logic;
+
+signal result_write_S          : std_logic;
+signal result_allowed_S        : std_logic;
+signal result_adcnumber_S      : std_logic_vector(15 downto 0);
+signal result_superburst_S     : std_logic_vector(15 downto 0);
+signal result_timestamp_S      : std_logic_vector(15 downto 0);
+signal result_timefraction_S   : std_logic_vector(CF_FRACTIONBIT-1 downto 0);
+signal result_energy_S         : std_logic_vector(15 downto 0);
+signal result_statusbyte_S     : std_logic_vector(7 downto 0);
+
+begin
+
+pulse_data_skipped <= '1' when (pulse_data_skipped1_S='1') or (pulse_data_skipped2_S='1') else '0';
+error <= '1' when (data_error_S='1') else '0';
+
+
+DC_split_data1: DC_split_data port map(
+		clock => clock,
+		SODA_clock => SODA_clock,
+		reset => reset,
+		enable => enable,
+		FEEboardnumber => FEEboardnumber,
+		packet_data_in => packet_data_in,
+		packet_data_present => packet_data_present,
+		packet_data_read => packet_data_read,
+		pulse_superburst => pulse_superburst_S,
+		pulse_timestamp => pulse_timestamp_S,
+		pulse_adcnumber => pulse_adcnumber_S,
+		pulse_statusbyte => pulse_statusbyte_S,
+		pulse_energy => pulse_energy_S,
+		pulse_CF_before => pulse_CF_before_S,
+		pulse_CF_after => pulse_CF_after_S,
+		pulse_allowed => pulse_allowed_S,
+		pulse_write => pulse_write_S,
+		slowcontrol_data => slowcontrol_data,
+		slowcontrol_address => slowcontrol_address,
+		slowcontrol_reply => slowcontrol_reply,
+		slowcontrol_write => slowcontrol_write,		  
+		wave_data_out => wave_data_out,
+		wave_data_write => wave_data_write,
+		wave_data_out_allowed => wave_data_out_allowed,
+		superburst_number => superburst_number,
+		superburst_update => superburst_update,
+		pulse_data_skipped => pulse_data_skipped1_S,
+		data_error => data_error_S,
+		testword0 => open
+	);
+
+		
+DC_CF_MAX_correction1: DC_CF_MAX_correction port map(
+		clock => clock,
+		load_clock => load_clock,
+		reset => reset,
+		pulse_superburst => pulse_superburst_S,
+		pulse_timestamp => pulse_timestamp_S,
+		pulse_adcnumber => pulse_adcnumber_S,
+		pulse_statusbyte => pulse_statusbyte_S,
+		pulse_energy => pulse_energy_S,
+		pulse_CF_before => pulse_CF_before_S,
+		pulse_CF_after => pulse_CF_after_S,
+		pulse_allowed => pulse_allowed_S,
+		pulse_write => pulse_write_S,
+		max_correction => max_correction,
+		max_LUT_offset => max_LUT_offset,
+		max_LUT_loading => max_LUT_loading,
+		max_LUT_write => max_LUT_write,
+		fraction_correction => fraction_correction,
+		fraction_LUT_loading => fraction_LUT_loading,
+		fraction_LUT_write => fraction_LUT_write,
+		LUT_data_in => LUT_data_in,
+		result_write => result_write_S,
+		result_allowed => pulse_data_out_allowed, -- allowed when fifo has enough space -- result_allowed_S,
+		adcnumber => result_adcnumber_S,
+		superburst => result_superburst_S,
+		timestamp => result_timestamp_S,
+		timefraction => result_timefraction_S,
+		energy => result_energy_S,
+		statusbyte => result_statusbyte_S,
+		testword0 => open,
+		testword1 => open
+		);
+		
+DC_time_energy_LUTs1: DC_time_energy_LUTs port map(
+		clock => clock,
+		load_clock => load_clock,
+		SODA_clock => SODA_clock,
+		reset => reset,
+		enable => enable,
+		timeshiftLUT_write => timeshiftLUT_write,
+		timeshiftLUT_loading => timeshiftLUT_loading,
+		timeshiftLUT_data => timeshiftLUT_data,
+		energyLUT_write => energyLUT_write,
+		energytLUT_loading => energytLUT_loading,
+		energyLUT_data => energyLUT_data,
+		
+		datain_write => result_write_S,
+		datain_allowed => result_allowed_S,
+		adcnumber => result_adcnumber_S,
+		superburst => result_superburst_S,
+		timestamp => result_timestamp_S,
+		timefraction => result_timefraction_S,
+		energy => result_energy_S,
+		statusbyte => result_statusbyte_S,
+
+		pulse_data_out => pulse_data_out,
+		pulse_data_write => pulse_data_write,
+		pulse_data_out_allowed => pulse_data_out_allowed,
+		pulse_data_skipped => pulse_data_skipped2_S,
+		superburst_number => superburst_number,
+		superburst_update => superburst_update,
+		testword0 => open
+		);
+
+
+end Behavioral;
+
diff --git a/data_concentrator/sources/DC_slow_control_TRB3.vhd b/data_concentrator/sources/DC_slow_control_TRB3.vhd
new file mode 100644
index 0000000..09e1d23
--- /dev/null
+++ b/data_concentrator/sources/DC_slow_control_TRB3.vhd
@@ -0,0 +1,647 @@
+----------------------------------------------------------------------------------
+-- Company:       KVIcart/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   17-04-2014
+-- Module Name:   DC_slow_control_TRB3
+-- Description:   Slow control : TRBnet local bus to Data Concentrator registers/status
+-- Modifications:
+--   26-11-2014   name changed from MUX_slow_control_TRB3 to DC_slow_control_TRB3
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+
+----------------------------------------------------------------------------------
+-- DC_slow_control_TRB3
+-- Module to translate TRBnet commands/reads to Panda Data Concentrator and Front End Electronics slowcontrol.
+-- The Data Concentrator slowcontrol was previously done with a soft-core CPU (ZPU).
+-- This is replaced by a TRBnet slave module, but the register access is still the same:
+--    from processor (TRBnet or CPU)
+--       write :
+--          first 32 bits  = selection/address word : request-bit, "101", 4-bits fiber-indexnumber, 24 bits address 
+--          second 32 bits = data word : 32 bits data 
+--       read :
+--          first 32 bits  = selection/address word : reply-bit, "101", 4-bits fiber-indexnumber, 24 bits address 
+--          second 32 bits = data word : 32 bits data 
+-- 
+-- For TRBnet this implemented by using 4 TRBnet addresses :
+--     bit(1..0)=00 write/read DC internal address, bit31=request, bit30..28=101, bit 27..24=fiber
+--     bit(1..0)=01 write/read DC internal data
+--     bit(1..0)=10 read status: bit0=readfifo data available, bit1= readfifo full
+--     bit(1..0)=11 read fifo address or data
+--
+-- Writing slowcontrol to FEE and fiber connection parts are done byte wise.
+-- Reading is initiated by the same byte command, but the data is returned serially, from each fiber.
+-- The byte-wise data is sent to all fiber-modules, 2 times 5 bytes
+-- The first byte of each 5 determines which fiber should accept this data and if it is a read action:
+--         Byte0 : Read bit , "000", index of the fiber 
+--         Byte1,2,3,4 : alternating: 
+--                     request-bit 101 xxxx 24-bits_address(MSB first)
+--                     32-bits_data, MSB first
+-- The serials data that is returned will contain alternating adddress information and data information.
+-- The transmission starts after the first IO_byte bit 7 is 1 and bits 3..0 corresponds with the channel number.
+-- Then 32 bits data will be returned to the cpu, MSB first
+--     first 5 bytes:
+--       byte1=fibernumber
+--       byte3..1, second address 
+-- The address word has bit 30..28 set to 101 as check
+--
+-- Additional to the FEE and fiber slowcontrol there are several (NROFMUXREGS) 32-bits registers.
+-- These registers are used for setting and reading the parameters in the Data Concentrator.
+--
+-- Library
+--     work.panda_package :  for type declarations and constants
+-- 
+-- Generics:
+-- 
+-- Inputs:
+--     rst : reset of all components
+--     clk : clock input
+--     BUS_READ_IN : TRBnet local bus read signal
+--     BUS_WRITE_IN : TRBnet local bus write signal
+--     BUS_ADDR_IN : TRBnet local bus address
+--     BUS_DATA_IN : TRBnet local bus data
+--     io_data_in : serial data : 32 bits:  bit31..0 : data, MSB first
+--     IO_data_in_available : serial data is available
+--     extract_data_available : pulse data is available for reading, used to set a status bit
+--     extract_wave_available : waveform data is available for reading, used to set a status bit
+--     board_status : registers contents from the Data Concentrator
+-- 
+-- Outputs:
+--     BUS_BUSY_OUT : TRBnet local bus busy signal
+--     BUS_ACK_OUT : TRBnet local bus acknowledge signal
+--     BUS_DATA_OUT : TRBnet local bus data
+--     io_data_out : 5-byte slowcontrol to fiber modules:
+--         Byte0 : Read bit , "000", index of the fiber 
+--         Byte1,2,3,4 : alternating: 
+--                     request-bit 101 xxxx 24-bits_address(MSB first)
+--                     32-bits_data, MSB first
+--     io_write_out : write signal for byte-data, only selected fiber (with index in first byte equals channel) should read
+--     board_status_read : read signals to read the registers contents from the Data Concentrator
+--     board_control : registers for the parameters in the Data Concentrator
+--     board_control_write : write signals to write to the registers in the Data Concentrator
+-- 
+-- Components:
+--     async_fifo_512x32 : fifo buffer for the data from Data Concentrator to TRBnet
+--
+----------------------------------------------------------------------------------
+
+library work;
+use work.panda_package.all;
+
+entity DC_slow_control_TRB3 is
+	port(	
+		rst                     : in std_logic;
+		clk                     : in std_logic;
+-- Slave bus
+		BUS_READ_IN             : in   std_logic;
+		BUS_WRITE_IN            : in   std_logic;
+		BUS_BUSY_OUT            : out  std_logic;
+		BUS_ACK_OUT             : out  std_logic;
+		BUS_ADDR_IN             : in   std_logic_vector(1 downto 0);
+		BUS_DATA_IN             : in   std_logic_vector(31 downto 0);
+		BUS_DATA_OUT            : out  std_logic_vector(31 downto 0);
+
+		io_data_in              : in std_logic_vector(0 to NROFFIBERS-1);
+		IO_data_in_available    : in std_logic_vector(0 to NROFFIBERS-1);
+		io_data_out             : out std_logic_vector(7 downto 0);
+		io_write_out            : out std_logic;
+
+		extract_data_available  : in std_logic;
+		extract_wave_available  : in std_logic;
+
+		board_status            : in array_muxregister_type;
+		board_status_read       : out std_logic_vector(0 to NROFMUXREGS-1);
+		board_control           : out array_muxregister_type;
+		board_control_write     : out std_logic_vector(0 to NROFMUXREGS-1);
+		testword0               : out std_logic_vector (35 downto 0)
+		);
+end DC_slow_control_TRB3;
+
+architecture Behavioral of DC_slow_control_TRB3 is
+
+component async_fifo_512x32 is
+port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(31 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(31 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic
+	);
+end component;
+
+-- Signals
+type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);
+signal CURRENT_STATE, NEXT_STATE: STATES;
+
+-- slave bus signals
+signal bus_ack_x                     : std_logic;
+signal bus_ack                       : std_logic;
+signal store_wr_x                    : std_logic;
+signal store_wr                      : std_logic;
+signal store_rd_x                    : std_logic;
+signal store_rd                      : std_logic;
+signal buf_bus_data_out              : std_logic_vector(31 downto 0);
+
+signal board_control_S               : array_muxregister_type := (others => (others => '0'));
+signal address_register_i            : std_logic_vector(31 downto 0);
+signal address_register_copy_i       : std_logic_vector(31 downto 0);
+signal data_register_i               : std_logic_vector(31 downto 0);
+signal board_status_read_i           : std_logic_vector(0 to NROFMUXREGS-1) := (others => '0');
+signal board_status_read7_i          : std_logic;
+signal extractwave_requested_i       : std_logic;
+signal extractdata_requested_i       : std_logic;
+signal read_histogram_requested_i    : std_logic;
+signal sysmon_requested_i            : std_logic;
+signal start_write_byte_i            : std_logic;
+signal clear_extractwave_requested_i : std_logic;
+signal clear_extractdata_requested_i : std_logic;
+signal clear_histogram_requested_i   : std_logic;
+signal clear_sysmon_requested_i      : std_logic;
+signal io_data_in_S                  : std_logic_vector(0 to NROFFIBERS-1);
+
+signal io_byte_out_S                 : std_logic_vector(7 downto 0);
+signal io_byte_request_S             : std_logic_vector(7 downto 0);
+signal io_write_out_S                : std_logic;
+signal io_request_out_S              : std_logic;
+signal byte_index_S                  : integer range 0 to 10 := 0;
+signal io_data_idx_i                 : integer range 0 to 63 := 0;
+signal io_data_par_S                 : std_logic_vector(31 downto 0) := (others => '0');
+signal extractdata_idx_i             : integer range 0 to 7 := 0;
+signal extractwave_idx_i             : integer range 0 to 4 := 0;
+signal read_histogram_idx_i          : integer range 0 to 4096 := 0;
+signal read_sysmon_idx_i             : std_logic := '0';
+signal addresscycle_i                : std_logic;
+signal fibernr_i                     : integer range 0 to NROFFIBERS-1 := 0;
+signal skipfirstread_i               : std_logic := '0';
+signal rdhistophase_S                : integer range 0 to 7 := 0;
+
+signal readfifo_write_i              : std_logic;
+signal readfifo_write_bf_i           : std_logic;
+signal readfifo_datain_i             : std_logic_vector(31 downto 0);
+signal readfifo_read_i               : std_logic;
+signal readfifo_dataout_i            : std_logic_vector(31 downto 0);
+signal readfifo_full_i               : std_logic;
+signal readfifo_empty_i              : std_logic;
+
+begin
+
+board_control <= board_control_S;
+
+---------------------------------------------------------
+-- Statemachine                                        --
+---------------------------------------------------------
+  STATE_MEM: process(clk)
+    begin
+      if( rising_edge(clk) ) then
+        if( rst = '1' ) then
+          CURRENT_STATE <= SLEEP;
+          bus_ack       <= '0';
+          store_wr      <= '0';
+          store_rd      <= '0';
+        else
+          CURRENT_STATE <= NEXT_STATE;
+          bus_ack       <= bus_ack_x;
+          store_wr      <= store_wr_x;
+          store_rd      <= store_rd_x;
+        end if;
+      end if;
+    end process STATE_MEM;
+
+-- Transition matrix
+  TRANSFORM: process(CURRENT_STATE, BUS_read_in, BUS_write_in )
+    begin
+      NEXT_STATE <= SLEEP;
+      bus_ack_x  <= '0';
+      store_wr_x <= '0';
+      store_rd_x <= '0';
+      case CURRENT_STATE is
+        when SLEEP    =>
+          if   ( (BUS_read_in = '1') ) then
+            NEXT_STATE <= RD_RDY;
+            store_rd_x <= '1';
+          elsif( (BUS_write_in = '1') ) then
+            NEXT_STATE <= WR_RDY;
+            store_wr_x <= '1';
+          else
+            NEXT_STATE <= SLEEP;
+          end if;
+
+        when RD_RDY    =>
+          NEXT_STATE <= RD_ACK;
+
+        when WR_RDY    =>
+          NEXT_STATE <= WR_ACK;
+
+        when RD_ACK    =>
+          if( BUS_read_in = '0' ) then
+            NEXT_STATE <= DONE;
+            bus_ack_x  <= '1';
+          else
+            NEXT_STATE <= RD_ACK;
+            bus_ack_x  <= '1';
+          end if;
+
+        when WR_ACK    =>
+          if( BUS_write_in = '0' ) then
+            NEXT_STATE <= DONE;
+            bus_ack_x  <= '1';
+          else
+            NEXT_STATE <= WR_ACK;
+            bus_ack_x  <= '1';
+          end if;
+
+        when DONE    =>
+          NEXT_STATE <= SLEEP;
+
+        when others    =>
+          NEXT_STATE <= SLEEP;
+  end case;
+end process TRANSFORM;
+
+
+---------------------------------------------------------
+-- data handling                                       --
+---------------------------------------------------------
+
+-- register write
+THE_WRITE_REG_PROC: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (rst='1') then
+				address_register_i <= (others => '0');
+			elsif ( (store_wr = '1') and (bus_addr_in = "00") ) then
+				address_register_i <= bus_data_in;
+			elsif ( (store_wr = '1') and (bus_addr_in = "01") ) then
+				data_register_i <= bus_data_in;
+			end if;
+		end if;
+	end process THE_WRITE_REG_PROC;
+  
+  
+THE_WRITE_PROC: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (rst='1') then
+				board_control_write <= (others => '0');
+				extractwave_requested_i <= '0';
+				extractdata_requested_i <= '0';
+				read_histogram_requested_i <= '0';
+				sysmon_requested_i <= '0';
+				start_write_byte_i <= '0';
+			else
+				board_control_write <= (others => '0');
+				start_write_byte_i <= '0';
+				if clear_extractwave_requested_i='1' then
+					extractwave_requested_i <= '0';
+				end if;
+				if clear_extractdata_requested_i='1' then
+					extractdata_requested_i <= '0';
+				end if;		
+				if clear_histogram_requested_i='1' then
+					read_histogram_requested_i <= '0';
+				end if;		
+				if clear_sysmon_requested_i='1' then
+					sysmon_requested_i <= '0';
+				end if;		
+				if ((store_wr='1') and (bus_addr_in="01")) and (address_register_i(30 downto 28)="101") then -- act when writing data register
+					if (address_register_i(23 downto 0)=ADDRESS_MUX_SODA_CONTROL) and (address_register_i(31)='0') then
+						board_control_S(3) <= bus_data_in;
+						board_control_write(3) <= '1';
+					elsif (address_register_i(23 downto 0)=ADDRESS_MUX_HISTOGRAM) then
+						board_control_S(4) <= bus_data_in;
+						board_control_write(4) <= '1';
+						if (address_register_i(31)='0') and (bus_data_in(1)='1') then
+							read_histogram_requested_i <= '1';
+						end if;
+					elsif (address_register_i(23 downto 0)=ADDRESS_MUX_EXTRACTWAVE) and (address_register_i(31)='1') then
+						board_control_S(7) <= bus_data_in;
+						board_control_write(7) <= '1';
+						extractwave_requested_i <= '1';
+					elsif (address_register_i(23 downto 0)=ADDRESS_MUX_EXTRACTDATA) and (address_register_i(31)='1') then
+						board_control_S(8) <= bus_data_in;
+						board_control_write(8) <= '1';
+						extractdata_requested_i <= '1';
+					elsif (address_register_i(23 downto 0)=ADDRESS_MUX_CROSSSWITCH) and (address_register_i(31)='0') then
+						board_control_S(13) <= bus_data_in;
+						board_control_write(13) <= '1';
+					elsif (address_register_i(23 downto 0)=ADDRESS_MUX_SYSMON) and (address_register_i(31)='1') then
+						board_control_S(12) <= bus_data_in;
+						board_control_write(12) <= '1';
+						sysmon_requested_i <= '1';
+					else -- IO
+						address_register_copy_i <= address_register_i;	
+						start_write_byte_i <= '1';						
+					end if;
+				end if;
+			end if;
+		end if;
+	end process THE_WRITE_PROC;
+
+THE_BYTE_WRITE_PROC: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (rst='1') then
+			else
+				case byte_index_S is 
+					when 1 => 
+						io_byte_out_S <= address_register_copy_i(31 downto 24);
+						io_write_out_S <= '1';
+						byte_index_S <= byte_index_S+1;
+					when 2 => 
+						io_byte_out_S <= address_register_copy_i(23 downto 16);
+						io_write_out_S <= '1';
+						byte_index_S <= byte_index_S+1;
+					when 3 => 
+						io_byte_out_S <= address_register_copy_i(15 downto 8);
+						io_write_out_S <= '1';
+						byte_index_S <= byte_index_S+1;
+					when 4 => 
+						io_byte_out_S <= address_register_copy_i(7 downto 0);	
+						io_write_out_S <= '1';
+						byte_index_S <= byte_index_S+1;
+					when 5 => 
+						io_write_out_S <= '0';
+						byte_index_S <= byte_index_S+1;
+					when 6 => 
+						io_byte_out_S <= "0000" & address_register_copy_i(27 downto 24);
+						io_write_out_S <= '1';
+						byte_index_S <= byte_index_S+1;
+					when 7 => 
+						io_byte_out_S <= data_register_i(31 downto 24);
+						io_write_out_S <= '1';
+						byte_index_S <= byte_index_S+1;
+					when 8 => 
+						io_byte_out_S <= data_register_i(23 downto 16);
+						io_write_out_S <= '1';
+						byte_index_S <= byte_index_S+1;
+					when 9 => 
+						io_byte_out_S <= data_register_i(15 downto 8);
+						io_write_out_S <= '1';
+						byte_index_S <= byte_index_S+1;
+					when 10 => 
+						io_byte_out_S <= data_register_i(7 downto 0);	
+						io_write_out_S <= '1';
+						byte_index_S <= 0;
+					when others =>
+						if start_write_byte_i='1' then
+							io_byte_out_S <= "0000" & address_register_copy_i(27 downto 24);
+							io_write_out_S <= '1';
+							byte_index_S <= 1;
+						else
+							io_write_out_S <= '0';
+						end if;
+				end case;
+			end if;
+		end if;
+	end process THE_BYTE_WRITE_PROC;
+	
+board_status_read_i(7) <= '1' when (extractwave_idx_i/=0) and (readfifo_full_i='0') else '0';
+
+
+THE_READ_IO_PROC: process(clk)
+constant zeros : std_logic_vector(0 to NROFFIBERS-1) := (others => '0');
+variable fibernr : integer range 0 to NROFFIBERS-1 := 0;
+	begin
+		if( rising_edge(clk) ) then
+			io_request_out_S <= '0';
+			skipfirstread_i <= '0';
+			board_status_read_i(4) <= '0';
+			board_status_read_i(8) <= '0';
+			clear_extractwave_requested_i <= '0';
+			clear_extractdata_requested_i <= '0';
+			clear_histogram_requested_i <= '0';
+			readfifo_write_i <= '0';
+			io_data_par_S <= io_data_par_S(30 downto 0) & io_data_in_S(fibernr_i);
+			io_data_in_S <= io_data_in;
+			if (rst='1') then
+				clear_sysmon_requested_i <= '0';
+				io_data_idx_i <= 0;
+				extractdata_idx_i <= 0;
+				read_sysmon_idx_i <= '0';
+				addresscycle_i <= '0';
+			else
+				if io_data_idx_i/=0 then
+					if io_data_idx_i<36 then
+						io_data_idx_i <= io_data_idx_i+1;
+					elsif io_data_idx_i=36 then
+						readfifo_write_i <= '1';
+						if (addresscycle_i='1') and (io_data_par_S(29 downto 27)="101") then -- dataword
+							readfifo_datain_i <= io_data_par_S(30 downto 27) & conv_std_logic_vector(fibernr_i,4) & io_data_par_S(22 downto 0) & io_data_in_S(fibernr_i);
+							io_data_idx_i <= io_data_idx_i+1;
+						else
+							readfifo_datain_i <= io_data_par_S(30 downto 0) & io_data_in_S(fibernr_i);
+							io_data_idx_i <= 0;
+						end if;
+						addresscycle_i <= '0';
+					elsif io_data_idx_i=37 then 
+						io_data_idx_i <= io_data_idx_i+1;
+						addresscycle_i <= '0';
+					else
+						io_byte_request_S <= "10" & conv_std_logic_vector(fibernr_i,6);
+						io_request_out_S <= '1';
+						io_data_idx_i <= 1;
+						addresscycle_i <= '0';
+					end if;
+--					io_data_par_S <= io_data_par_S(30 downto 0) & io_data_in_S(fibernr_i);
+				elsif extractdata_idx_i/=0 then
+					if readfifo_full_i='0' then
+						case extractdata_idx_i is
+							when 1 => 
+								readfifo_datain_i <= board_status(8);
+								extractdata_idx_i <= extractdata_idx_i+1;
+								board_status_read_i(8) <= '1'; -- next word
+							when 2 => 
+								readfifo_datain_i <= (x"d0" & ADDRESS_MUX_EXTRACTDATA)+1;
+								extractdata_idx_i <= extractdata_idx_i+1;
+							when 3 => 
+								readfifo_datain_i <= board_status(8);
+								extractdata_idx_i <= extractdata_idx_i+1;
+								board_status_read_i(8) <= '1'; -- next word
+							when 4 => 
+								readfifo_datain_i <= (x"d0" & ADDRESS_MUX_EXTRACTDATA)+2;
+								extractdata_idx_i <= extractdata_idx_i+1;
+							when 5 => 
+								readfifo_datain_i <= board_status(8);
+								extractdata_idx_i <= extractdata_idx_i+1;
+								board_status_read_i(8) <= '1'; -- next word
+							when 6 => 
+								readfifo_datain_i <= (x"d0" & ADDRESS_MUX_EXTRACTDATA)+3;
+								extractdata_idx_i <= extractdata_idx_i+1;
+							when 7 => 
+								readfifo_datain_i <= board_status(8);
+								extractdata_idx_i <= 0;
+							when others =>
+								extractdata_idx_i <= 0;
+						end case;
+						readfifo_write_i <= '1';
+					else
+						readfifo_write_i <= '1';
+					end if;
+				elsif extractwave_idx_i/=0 then
+					if readfifo_full_i='0' then
+						if skipfirstread_i='0' then
+							readfifo_write_i <= '1';
+							readfifo_datain_i <= board_status(7);	
+							if ((board_status(7)(31)='1') or (board_status(7)(15)='1')) and (extractwave_idx_i>3) then
+								extractwave_idx_i <= 0; -- stop reading waveform
+							else
+								if extractwave_idx_i<4 then
+									extractwave_idx_i <= extractwave_idx_i+1;
+								end if;
+							end if;
+						end if;
+					else -- full
+						readfifo_write_i <= '1';
+					end if;
+				elsif read_histogram_idx_i/=0 then
+					if skipfirstread_i='1' then -- second word always 0x00000000
+						rdhistophase_S <= 0;
+						if readfifo_full_i='0' then
+							readfifo_write_i <= '1';
+							readfifo_datain_i <= (others => '0');
+						else
+							skipfirstread_i <= '1';
+						end if;
+					else
+						if rdhistophase_S=0 then
+							board_status_read_i(4) <= '1';
+							rdhistophase_S <= rdhistophase_S+1;
+						elsif rdhistophase_S=1 then
+							if readfifo_full_i='0' then
+								readfifo_write_i <= '1';
+								readfifo_datain_i <= board_status(4);
+								rdhistophase_S <= rdhistophase_S+1;
+								if read_histogram_idx_i<=4096 then
+									read_histogram_idx_i <= read_histogram_idx_i+1;
+								else
+									read_histogram_idx_i <= 0;
+								end if;
+							end if;
+						elsif rdhistophase_S<7 then
+							rdhistophase_S <= rdhistophase_S+1;
+						else
+							rdhistophase_S <= 0;							
+						end if;
+					end if;
+				elsif read_sysmon_idx_i='1' then
+					if readfifo_full_i='0' then
+						readfifo_datain_i <= board_status(12);
+						read_sysmon_idx_i <= '0';
+						readfifo_write_i <= '1';
+					else -- full
+						readfifo_write_i <= '1';
+					end if;
+				elsif (extractdata_requested_i='1') and (extract_data_available='1') and (readfifo_full_i='0') then -- (board_status(8)/=x"ffffffff") then
+					clear_extractdata_requested_i <= '1';
+					readfifo_write_i <= '1';
+					readfifo_datain_i <= (x"d0" & ADDRESS_MUX_EXTRACTDATA)+0;
+					extractdata_idx_i <= 1;
+				elsif (extractwave_requested_i='1') and (extract_wave_available='1') and (readfifo_full_i='0') then -- and (board_status(7)/=x"ffffffff") then
+					clear_extractwave_requested_i <= '1';
+					readfifo_write_i <= '1';
+					readfifo_datain_i <= x"d0" & ADDRESS_MUX_EXTRACTWAVE;
+					extractwave_idx_i <= 1;
+					skipfirstread_i <= '1';
+				elsif (sysmon_requested_i='1') and (readfifo_full_i='0') then 
+					clear_sysmon_requested_i <= '1';
+					readfifo_write_i <= '1';
+					readfifo_datain_i <= (x"d0" & ADDRESS_MUX_SYSMON);
+					read_sysmon_idx_i <= '1';					
+				elsif IO_data_in_available/=zeros(0 to NROFFIBERS-1) then
+					fibernr := 0;
+					for i in 0 to NROFFIBERS-1 loop
+						if IO_data_in_available(i)='1' then
+							fibernr := i;
+						end if;
+					end loop;
+					io_byte_request_S <= "10" & conv_std_logic_vector(fibernr,6);
+					fibernr_i <= fibernr;
+					io_request_out_S <= '1';
+					io_data_idx_i <= 1;
+					addresscycle_i <= '1';
+				elsif (read_histogram_requested_i='1') and (readfifo_full_i='0') then
+					clear_histogram_requested_i <= '1';
+					read_histogram_idx_i <= 1;
+					readfifo_write_i <= '1';
+					readfifo_datain_i <= x"d0" & ADDRESS_MUX_HISTOGRAM;
+					skipfirstread_i <= '1';
+				else				
+				end if;
+			end if;
+		end if;
+	end process THE_READ_IO_PROC;
+	
+board_status_read <= board_status_read_i;
+--io_write_out <= '1' when (io_write_out_S='1') or (io_request_out_S='1') else '0';
+--io_data_out <= io_byte_request_S when (io_request_out_S='1') else io_byte_out_S;
+
+process(clk)
+begin
+	if rising_edge(clk) then
+		if (io_write_out_S='1') or (io_request_out_S='1') then
+			io_write_out <= '1';
+		else
+			io_write_out <= '0';
+		end if;
+		if (io_request_out_S='1') then
+			io_data_out <= io_byte_request_S;
+		else
+			io_data_out <= io_byte_out_S;
+		end if;
+	end if;
+end process;
+
+readfifo: async_fifo_512x32 port map(
+	rst => rst,
+	wr_clk => clk,
+	rd_clk => clk,
+	din => readfifo_datain_i,
+	wr_en => readfifo_write_i,
+	rd_en => readfifo_read_i,
+	dout => readfifo_dataout_i,
+	full => readfifo_full_i,
+	empty => readfifo_empty_i);
+readfifo_write_bf_i <= '1' when (readfifo_write_i='1') and (readfifo_full_i='0') else '0';
+	
+readfifo_read_i <= '1' when (CURRENT_STATE=SLEEP) and (BUS_read_in='1') and (bus_addr_in="11") 
+	and (readfifo_empty_i='0') else '0';
+		  
+					
+-- register read
+THE_READ_REG_PROC: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (rst='1') then
+				buf_bus_data_out <= (others => '0');
+			elsif( (store_rd = '1') and (bus_addr_in = "00") ) then
+				buf_bus_data_out <= address_register_i;
+			elsif( (store_rd = '1') and (bus_addr_in = "01") ) then
+				buf_bus_data_out <= data_register_i;
+			elsif( (store_rd = '1') and (bus_addr_in = "10") ) then
+				buf_bus_data_out(0) <= not readfifo_empty_i;
+				buf_bus_data_out(1) <= readfifo_full_i;
+				buf_bus_data_out(31 downto 2) <= (others => '0');
+			elsif( (store_rd = '1') and (bus_addr_in = "11") ) then
+				buf_bus_data_out <= readfifo_dataout_i;
+			end if;
+		end if;
+	end process THE_READ_REG_PROC;
+ 
+
+-- output signals
+BUS_DATA_OUT <= buf_bus_data_out;
+BUS_ACK_OUT  <= bus_ack;
+BUS_BUSY_OUT <= '0';
+
+testword0 <= (others => '0');
+
+	
+end Behavioral;
+
diff --git a/data_concentrator/sources/DC_slowcontrol_packetbuilder.vhd b/data_concentrator/sources/DC_slowcontrol_packetbuilder.vhd
new file mode 100644
index 0000000..16074a0
--- /dev/null
+++ b/data_concentrator/sources/DC_slowcontrol_packetbuilder.vhd
@@ -0,0 +1,368 @@
+	----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   04-03-2011
+-- Module Name:   DC_slowcontrol_packetbuilder
+-- Description:   Puts the slow control command in packets for the fiber module
+-- Modifications:
+--   12-09-2014   New dataformat, name changed to DC_slowcontrol_packetbuilder, no boardnumber
+--   08-10-2014   Initialize FEE registers, ending with status register read request
+--   08-10-2014   Input-FIFO for slow control commands
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- DC_slowcontrol_packetbuilder
+-- Makes a packet from a slowcontrol command
+--
+-- The slow control packets : 2 32-bit words, with CRC8 in last word
+--   0x5C address(7..0) replybit 0000000 data(31..24)
+--   data(23..0) CRC8(7..0)
+-- The address is the lowest 8 bits of the 24-bits slowcontrol address, the other bits must by 0 for FEE access.
+-- The request bit indicates that the FEE should replay with the contents of the sent address.
+-- The command bit sends a data to the specified address
+--
+-- Library:
+--     work.panda_package :  for type declarations and constants
+--
+-- Generics:
+-- 
+-- Inputs:
+--     clock : clock input
+--     reset : synchronous reset
+--     init_FEE : start sending all stored commands to FEE
+--     slowcontrol_data : slow-control command : data
+--     slowcontrol_address : slow-control command : address
+--     slowcontrol_request : indicates if this is a request for the contents of the specified address
+--     slowcontrol_write : slow-control command : address
+--     packet_fifofull : full signal from connected packet fifo
+-- 
+-- Outputs:
+--     slowcontrol_allowed : module can accept data
+--     packet_data_out : packet data 32 bits
+--     packet_lastword :  last packet data word
+--     packet_datawrite : packet_data_out valid
+-- 
+-- Components:
+--     crc8_add_check32 : add (and checks) a CRC8 code to a stream of 32 bits data words
+--     blockmem : memory to store slowcontrol commands
+--     sync_fifo_512x41 : input fifo for slow control commands
+--
+----------------------------------------------------------------------------------
+
+entity DC_slowcontrol_packetbuilder is
+	port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		init_FEE                : in  std_logic; 
+		slowcontrol_data        : in std_logic_vector (31 downto 0);
+		slowcontrol_address     : in std_logic_vector (23 downto 0);
+		slowcontrol_request     : in std_logic;
+		slowcontrol_write       : in std_logic; 
+		slowcontrol_allowed     : out std_logic; 
+		packet_data_out         : out std_logic_vector (31 downto 0);
+		packet_lastword         : out std_logic;
+		packet_datawrite        : out std_logic;
+		packet_fifofull         : in std_logic
+	);		
+end DC_slowcontrol_packetbuilder;
+
+architecture Behavioral of DC_slowcontrol_packetbuilder is
+
+component crc8_add_check32 is 
+   PORT(           
+		clock              : in  std_logic; 
+		reset              : in  std_logic; 
+		data_in            : in  std_logic_vector(31 DOWNTO 0); 
+		data_in_valid      : in  std_logic; 
+		data_in_last       : in  std_logic; 
+		data_out           : out std_logic_vector(31 DOWNTO 0); 
+		data_out_valid     : out std_logic;
+		data_out_last      : out std_logic;
+		crc_error          : out std_logic
+	);
+end component; 
+
+component blockmem is
+	generic (
+		ADDRESS_BITS : natural := 8;
+		DATA_BITS  : natural := 34
+		);
+	port (
+		clock                   : in  std_logic; 
+		write_enable            : in std_logic;
+		write_address           : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_in                 : in std_logic_vector(DATA_BITS-1 downto 0);
+		read_address            : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_out                : out std_logic_vector(DATA_BITS-1 downto 0)
+	);
+end component;
+
+component sync_fifo_512x41 is
+port (
+		rst                     : in std_logic;
+		clk                     : in std_logic;
+		din                     : in std_logic_vector(40 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(40 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic
+	);
+end component;
+
+type tx_state_type is (init,idle,slow1,init_FEE0,init_FEE1,init_FEE2,init_FEE3,init_FEE4,init_FEE5);
+signal tx_state_S                   : tx_state_type := init;
+
+signal slowcontrol_data_S           : std_logic_vector (31 downto 0);
+signal slowcontrol_data_buf_S       : std_logic_vector (31 downto 0);
+signal slowcontrol_address_S        : std_logic_vector (7 downto 0);
+signal slowcontrol_request_S        : std_logic := '0';
+signal fifo_write_S                 : std_logic := '0';
+signal fifo_read_S                  : std_logic := '0';
+signal fifo_full_S                  : std_logic := '0';
+signal fifo_empty_S                 : std_logic := '0';
+signal fifo_read_aftr1clk_S         : std_logic := '0';
+
+signal crc8_data_in_S               : std_logic_vector (31 downto 0);
+signal crc8_reset_S                 : std_logic := '0';
+signal crc8_clear_S                 : std_logic := '0';
+signal crc8_data_in_valid_S         : std_logic := '0';
+signal crc8_data_in_last_S          : std_logic := '0';
+signal crc8_writeword_S             : std_logic := '0';
+signal crc8_data_out_valid_S        : std_logic := '0';
+signal prev_crc8_data_out_valid_S   : std_logic := '0';
+signal crc8_data_out_last_S         : std_logic := '0';
+signal prev_crc8_data_out_last_S    : std_logic := '0';
+
+signal init_FEE_S                   : std_logic := '0';
+signal start_init_FEE_S             : std_logic := '0';
+signal mem_write_S                  : std_logic := '0';
+signal mem_data_in_S                : std_logic_vector (33 downto 0);
+signal mem_data_out_S               : std_logic_vector (33 downto 0);
+signal mem_read_address_S           : std_logic_vector (7 downto 0);
+
+
+begin
+
+slowcontrol_allowed <= '1' when fifo_full_S='0' else '0';
+		
+inputfifo: sync_fifo_512x41 port map(
+		rst => reset,
+		clk => clock,
+		din(31 downto 0) => slowcontrol_data,
+		din(39 downto 32) => slowcontrol_address(7 downto 0),
+		din(40) => slowcontrol_request,
+		wr_en => fifo_write_S,
+		rd_en => fifo_read_S,
+		dout(31 downto 0) => slowcontrol_data_S,
+		dout(39 downto 32) => slowcontrol_address_S,
+		dout(40) => slowcontrol_request_S,
+		full => fifo_full_S,
+		empty => fifo_empty_S);
+fifo_write_S <= '1' when (slowcontrol_write='1') and (slowcontrol_address(23 downto 8)=x"0000") else '0';
+fifo_read_S <= '1' when  (tx_state_S=idle) and (fifo_empty_S='0') else '0';
+
+crc8_data_in_valid_S <= '1' when (crc8_writeword_S='1') and (packet_fifofull='0') else '0';
+crc8_reset_S <= '1' when (crc8_clear_S='1') or (reset='1') else '0';
+crc8check: crc8_add_check32 port map(
+	clock => clock,
+	reset => crc8_reset_S,
+	data_in => crc8_data_in_S,
+	data_in_valid => crc8_data_in_valid_S,
+	data_in_last => crc8_data_in_last_S, 
+	data_out => packet_data_out,
+	data_out_valid => crc8_data_out_valid_S,
+	data_out_last => crc8_data_out_last_S,
+	crc_error => open); -- only generate, no check
+
+	  
+packet_datawrite <= '1' when ((crc8_data_out_valid_S='1') and (packet_fifofull='0')) or 
+		((prev_crc8_data_out_valid_S='1') and (packet_fifofull='0')) else '0';
+packet_lastword <= '1' when (crc8_data_out_last_S='1') or (prev_crc8_data_out_last_S='1') else '0';
+
+crc8_process: process(clock) -- process to freeze output of crc8 in case of packet_fifofull
+begin
+	if rising_edge(clock) then
+		if reset='1' then
+			prev_crc8_data_out_valid_S <= '0';
+			prev_crc8_data_out_last_S <= '0';
+		else
+			if ((crc8_data_out_valid_S='1') and (packet_fifofull='1')) then
+				prev_crc8_data_out_valid_S <= '1';
+				prev_crc8_data_out_last_S <= crc8_data_out_last_S;
+			elsif ((crc8_data_out_valid_S='1') and (packet_fifofull='0')) then
+				prev_crc8_data_out_valid_S <= '0';
+				prev_crc8_data_out_last_S <= '0';
+			elsif ((crc8_data_out_valid_S='0') and (packet_fifofull='0')) then
+				prev_crc8_data_out_last_S <= '0';
+				prev_crc8_data_out_valid_S <= '0';
+			elsif ((crc8_data_out_valid_S='0') and (packet_fifofull='1')) then
+			end if;				
+		end if;
+	end if;
+end process;
+
+blockmem1: blockmem port map(
+	clock => clock,
+	write_enable => mem_write_S,
+	write_address => slowcontrol_address_S(7 downto 0),
+	data_in => mem_data_in_S,
+	read_address => mem_read_address_S,
+	data_out => mem_data_out_S);
+	
+mem_write_S <= fifo_read_aftr1clk_S;
+mem_data_in_S(33) <= '1';
+mem_data_in_S(32) <= slowcontrol_request_S;
+mem_data_in_S(31 downto 0) <= slowcontrol_data_S;
+
+slowcontrolhandling_process: process(clock)
+variable counter_V : integer range 0 to 3;
+begin
+	if (rising_edge(clock)) then 
+		if (reset = '1') then 
+			crc8_data_in_last_S <= '0';
+			crc8_writeword_S <= '0';
+			crc8_clear_S <= '1'; -- clear crc
+			tx_state_S <= idle;
+		else
+			if (init_FEE='1') and (init_FEE_S='0') then
+				start_init_FEE_S <= '1';
+			end if;
+			case tx_state_S is
+				when init =>
+					crc8_data_in_last_S <= '0';
+					crc8_writeword_S <= '0';
+					crc8_clear_S <= '1'; -- clear crc
+					tx_state_S <= idle;
+				when idle =>
+					mem_read_address_S <= (others => '0');
+					if (crc8_writeword_S='1') and (crc8_data_in_valid_S='0') then -- unsuccessfull write
+						crc8_writeword_S <= '1';
+						tx_state_S <= idle;
+						crc8_clear_S <= '0';
+					else
+						if (fifo_read_aftr1clk_S='1') then -- only addresses 0..255
+							crc8_clear_S <= '0';
+							slowcontrol_data_buf_S <= slowcontrol_data_S;
+							crc8_data_in_S <= x"5c" & slowcontrol_address_S & slowcontrol_request_S & "0000000" & slowcontrol_data_S(31 downto 24);
+							crc8_data_in_last_S <= '0';
+							crc8_writeword_S <= '1';
+							tx_state_S <= slow1;
+						else
+							crc8_clear_S <= '0'; -- no clear crc ??????????
+							crc8_data_in_last_S <= '0';
+							crc8_writeword_S <= '0';
+							if start_init_FEE_S='1' then
+								tx_state_S <= init_FEE0;
+								start_init_FEE_S <= '0';
+							else
+								tx_state_S <= idle;			
+							end if;
+						end if;
+					end if;
+				when slow1 =>
+					crc8_clear_S <= '0';
+					if (crc8_writeword_S='1') and (crc8_data_in_valid_S='0') then -- unsuccessfull write
+						crc8_writeword_S <= '1';
+					else
+						crc8_data_in_S <= slowcontrol_data_buf_S(23 downto 0) & x"00";
+						crc8_data_in_last_S <= '1';
+						crc8_writeword_S <= '1';
+						tx_state_S <= idle;
+					end if;
+				when init_FEE0 =>
+					crc8_clear_S <= '0';
+					if (crc8_writeword_S='1') and (crc8_data_in_valid_S='0') then -- unsuccessfull write
+						crc8_writeword_S <= '1';
+						tx_state_S <= idle;
+					else
+						if (mem_data_out_S(33)='1') then -- address valid then
+							crc8_data_in_S <= x"5c" & mem_read_address_S & x"00" & mem_data_out_S(31 downto 24); -- no request
+							crc8_data_in_last_S <= '0';
+							crc8_writeword_S <= '1';
+							tx_state_S <= init_FEE1;
+						else
+							crc8_writeword_S <= '0';
+							if conv_integer(unsigned(mem_read_address_S))<FEESLOWCONTROLADRESSES then
+								mem_read_address_S <= mem_read_address_S+1;
+								tx_state_S <= init_FEE3;
+							else
+								tx_state_S <= init_FEE4;
+							end if;
+						end if;
+					end if;
+				when init_FEE1 =>
+					crc8_clear_S <= '0';
+					if (crc8_writeword_S='1') and (crc8_data_in_valid_S='0') then -- unsuccessfull write
+						crc8_writeword_S <= '1';
+					else
+						crc8_data_in_S <= mem_data_out_S(23 downto 0) & x"00";
+						crc8_data_in_last_S <= '1';
+						crc8_writeword_S <= '1';
+						if conv_integer(unsigned(mem_read_address_S))<FEESLOWCONTROLADRESSES then
+							mem_read_address_S <= mem_read_address_S+1;
+							tx_state_S <= init_FEE2;
+						else
+							tx_state_S <= init_FEE4;
+						end if;
+					end if;
+					counter_V := 0;
+				when init_FEE2 => -- wait 1 clock for memory output
+					crc8_clear_S <= '0';
+					if (crc8_writeword_S='1') and (crc8_data_in_valid_S='0') then -- unsuccessfull write
+						crc8_writeword_S <= '1';
+					else
+						crc8_writeword_S <= '0';
+					end if;
+					if counter_V<3 then
+						counter_V := counter_V+1;
+					else
+						tx_state_S <= init_FEE0;
+					end if;
+				when init_FEE3 => -- wait 1 clock for memory output
+					crc8_clear_S <= '0';
+					if (crc8_writeword_S='1') and (crc8_data_in_valid_S='0') then -- unsuccessfull write
+						crc8_writeword_S <= '1';
+					else
+						crc8_writeword_S <= '0';
+					end if;
+					tx_state_S <= init_FEE0;
+				when init_FEE4 => 
+					crc8_clear_S <= '0';
+					if (crc8_writeword_S='1') and (crc8_data_in_valid_S='0') then -- unsuccessfull write
+						crc8_writeword_S <= '1';
+					else
+						crc8_data_in_S <= x"5c" & ADDRESS_FEE_STATUS & x"80" & x"00"; -- request
+						crc8_data_in_last_S <= '0';
+						crc8_writeword_S <= '1';
+						tx_state_S <= init_FEE5;
+					end if;
+				when init_FEE5 => 
+					crc8_clear_S <= '0';
+					if (crc8_writeword_S='1') and (crc8_data_in_valid_S='0') then -- unsuccessfull write
+						crc8_writeword_S <= '1';
+					else
+						crc8_data_in_S <= x"00000000"; -- data=0
+						crc8_data_in_last_S <= '1';
+						crc8_writeword_S <= '1';
+						tx_state_S <= idle;
+					end if;
+				when others =>
+					crc8_clear_S <= '0';
+					crc8_data_in_last_S <= '0';
+					crc8_writeword_S <= '0';
+					tx_state_S <= init;
+			end case;
+			fifo_read_aftr1clk_S <= fifo_read_S;
+			init_FEE_S <= init_FEE;
+		end if;
+	end if;
+end process;
+
+end Behavioral;
diff --git a/data_concentrator/sources/DC_slowcontrol_receive_from_cpu.vhd b/data_concentrator/sources/DC_slowcontrol_receive_from_cpu.vhd
new file mode 100644
index 0000000..73543d3
--- /dev/null
+++ b/data_concentrator/sources/DC_slowcontrol_receive_from_cpu.vhd
@@ -0,0 +1,152 @@
+	----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   21-03-2011
+-- Module Name:   DC_slowcontrol_receive_from_cpu
+-- Description:   Module to receive slowcontrol data from soft-core cpu to fiber modules
+-- Modifications:
+--   12-09-2014   Name changed to DC_slowcontrol_receive_from_cpu
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+
+----------------------------------------------------------------------------------
+-- DC_slowcontrol_receive_from_cpu
+-- Module to receive byte-wise data from soft-core cpu and translates it into parallel slowcontrol data.
+-- The byte-wise input data is sent to all fibermodules as packets of 8 bytes.
+-- The first packet determines which fiber should sent this data and if it is a read action:
+--         Byte0 : Read bit , "000", index of the fiber 
+--         Byte1,2,3,4 : alternating: 
+--                     request-bit 101 xxxx 24-bits_address(MSB first)
+--                     32-bits_data, MSB first
+-- The output of the module is parallel slowcontrol address and data and request bit
+--
+-- Library:
+-- 
+-- Generics:
+-- 
+-- Inputs:
+--     clock : clock input and output
+--     reset : synchronous reset 
+--     channel : index of the fiber
+--     IO_byte : 5-byte slowcontrol:
+--         Byte0 : Read bit , "000", index of the fiber 
+--         Byte1,2,3,4 : alternating: 
+--                     request-bit 101 xxxx 24-bits_address(MSB first)
+--                     32-bits_data, MSB first
+--     IO_write : write signal for byte-data, only selected fiber (with index in first byte equals channel) should read
+--     slowcontrol_fifofull : fifofull signal for slow-control write to fibermodule
+-- 
+-- Outputs:
+--     slowcontrol_data : slowcontrol parallel command : data (32 bits)
+--     slowcontrol_address : slowcontrol parallel command : address (24 bits)
+--     slowcontrol_request : slowcontrol parallel command : request (1 bit)
+--     slowcontrol_write : write signal for slowcontrol parallel command
+--     error : error: connected fifo full, or incomplete data burst
+-- 
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity DC_slowcontrol_receive_from_cpu is
+	port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		channel                 : in std_logic_vector (3 downto 0);
+		IO_byte                 : in std_logic_vector(7 downto 0);
+		IO_write                : in std_logic;
+		slowcontrol_data        : out std_logic_vector (31 downto 0);
+		slowcontrol_address     : out std_logic_vector (23 downto 0);
+		slowcontrol_request     : out std_logic;
+		slowcontrol_write       : out std_logic; 
+		slowcontrol_fifofull    : in std_logic; 
+		error                   : out std_logic
+		);
+end DC_slowcontrol_receive_from_cpu;
+
+architecture Behavioral of DC_slowcontrol_receive_from_cpu is
+
+type array8bits_type is array(0 to 3) of std_logic_vector(7 downto 0);
+
+signal bytedata_S             : array8bits_type := (others => (others => '0'));
+signal byteaddress_S          : array8bits_type := (others => (others => '0'));
+signal byte_idx_S             : integer range 0 to 4 := 0;
+signal selected_S             : std_logic := '0';
+signal slowcontrol_write_S    : std_logic := '0';
+signal expect_data_S          : std_logic := '0';
+signal error1_S               : std_logic := '0';
+
+begin
+
+slowcontrol_write <= slowcontrol_write_S;
+error <= '1' when ((slowcontrol_write_S='1') and (slowcontrol_fifofull='1')) or (error1_S='1') else '0';
+
+slowcontrol_request <= byteaddress_S(0)(7);
+slowcontrol_address <= byteaddress_S(1) & byteaddress_S(2) & byteaddress_S(3);
+slowcontrol_data <=  bytedata_S(0) & bytedata_S(1) & bytedata_S(2)& bytedata_S(3);
+
+rd_process: process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if reset='1' then
+			byte_idx_S <= 0;
+			slowcontrol_write_S <= '0';
+			selected_S <= '0';
+			expect_data_S <= '0';
+			error1_S <= '0';
+		else
+			if byte_idx_S=0 then
+				slowcontrol_write_S <= '0';
+				error1_S <= '0';
+				if (IO_write='1') and (IO_byte(7)='0') then
+					if (IO_byte(3 downto 0)=channel) then
+						selected_S <= '1';
+						bytedata_S(0) <= IO_byte;
+					else
+						selected_S <= '0';
+					end if;
+					byte_idx_S <= 1;
+				else
+					selected_S <= '0';
+				end if;
+			else
+				if (IO_write='1')  then
+					error1_S <= '0';
+					if selected_S='1' then
+						if expect_data_S='1' then
+							bytedata_S(byte_idx_S-1) <= IO_byte;
+						else
+							byteaddress_S(byte_idx_S-1) <= IO_byte;
+						end if;
+					end if;
+					if byte_idx_S<4 then
+						byte_idx_S <= byte_idx_S + 1;
+						slowcontrol_write_S <= '0';
+					else
+						if expect_data_S='1' then
+							slowcontrol_write_S <= selected_S;
+							expect_data_S <= '0';
+						else
+							if byteaddress_S(0)(6 downto 4)="101" then
+								expect_data_S <= '1';
+							else -- error
+								expect_data_S <= '0';
+							end if;
+						end if;
+						byte_idx_S <= 0;
+					end if;
+				else -- error
+					error1_S <= '1';
+					slowcontrol_write_S <= '0';
+					expect_data_S <= '0';
+					byte_idx_S <= 0;
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+					
+end Behavioral;
diff --git a/data_concentrator/sources/DC_slowcontrol_to_serial.vhd b/data_concentrator/sources/DC_slowcontrol_to_serial.vhd
new file mode 100644
index 0000000..36eccf0
--- /dev/null
+++ b/data_concentrator/sources/DC_slowcontrol_to_serial.vhd
@@ -0,0 +1,278 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   07-03-2012
+-- Module Name:   DC_slowcontrol_to_serial
+-- Description:   Module to send slowcontrol data serially to the soft-core cpu
+-- Modifications:
+--    16-09-2014: name changed from MUX_slowcontrol_to_serial to DC_slowcontrol_to_serial
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+
+----------------------------------------------------------------------------------
+-- DC_slowcontrol_to_serial
+-- Module to transfer slowcontrol serially to the soft-core cpu.
+-- The slowcontrol data input is parallel data: address, data and reply bit.
+-- The serials data starts if the first IO_byte bit 7 is 1 and 
+-- bits 3..0 corresponds with the channel number.
+-- Then 32 bits data will be returned to the cpu, MSB first.
+-- Slowcontrol address and data are sent after each other.
+-- The address word has bit 30..28 set to 101 as check
+-- Bit 31 of the address word is the slow control reply bit.
+--
+-- Library:
+-- 
+-- Generics:
+-- 
+-- Inputs:
+--     write_clock : clock for the slowcontrol data from the GTP receiver module
+--     read_clock : clock for the slowcontrol serial data
+--     reset : reset
+--     channel : index of the fiber
+--     slowcontrol_data : slowcontrol data; 32bits
+--     slowcontrol_address : slowcontrol address; 24bits
+--     slowcontrol_reply : slowcontrol reply bit
+--     slowcontrol_write : write signals for the slowcontrol data/address/reply	  
+--     IO_byte : 5-byte slowcontrol:
+--         Byte0 : Read bit , "000", index of the fiber 
+--         Byte1,2,3,4 : alternating: 
+--                     request-bit 101 xxxx 24-bits_address(MSB first)
+--                     32-bits_data, MSB first
+--     IO_write : write signal for byte-data, only selected fiber (with index in first byte equals channel) should read
+-- 
+-- Outputs:
+--     IO_serialdata : serial data : 32 bits:
+--          bit31..0 : data, MSB first
+--     IO_serialavailable : data is available
+--     error : error is a slowcontrol command is skipped
+-- 
+-- Components:
+--     async_fifo_512x32 : Fifo with 32-bits input and output
+--
+----------------------------------------------------------------------------------
+
+entity DC_slowcontrol_to_serial is
+	port ( 
+		write_clock             : in std_logic;
+		read_clock              : in std_logic;
+		reset                   : in std_logic;
+		channel                 : in std_logic_vector (3 downto 0);
+		slowcontrol_data        : in std_logic_vector (31 downto 0);
+		slowcontrol_address     : in std_logic_vector (23 downto 0);
+		slowcontrol_reply       : in std_logic;
+		slowcontrol_write       : in std_logic;			  
+		IO_byte                 : in std_logic_vector (7 downto 0);
+		IO_write                : in std_logic;
+		IO_serialdata           : out std_logic;
+		IO_serialavailable      : out std_logic;
+		error                   : out std_logic
+		);
+end DC_slowcontrol_to_serial;
+
+architecture Behavioral of DC_slowcontrol_to_serial is
+
+component async_fifo_512x32
+	port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(31 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(31 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic);
+end component;
+
+
+signal reset_write_clock_S    : std_logic;
+signal reset_read_clock_S     : std_logic;
+signal sfifo_data_in_S        : std_logic_vector(31 downto 0);
+signal sfifo_data_out_S       : std_logic_vector(31 downto 0);
+signal sfifo_write_S          : std_logic;
+signal sfifo_read_S           : std_logic;
+signal sfifo_full_S           : std_logic;
+signal sfifo_empty_S          : std_logic;
+
+signal skipped_S              : std_logic;
+signal writefifo_S            : std_logic;
+signal write_seconddata_S     : std_logic;
+
+signal secondword_S           : std_logic_vector(31 downto 0);
+signal buffer_firstword_S     : std_logic_vector(31 downto 0);
+signal buffer_secondword_S    : std_logic_vector(31 downto 0);
+signal buffer_written_S       : std_logic;
+
+signal bit_idx_S              : integer range 0 to 31 := 0;
+signal byte_idx_S             : integer range 0 to 4 := 0;
+
+signal IO_serialdata_S        : std_logic;
+signal error1_S               : std_logic;
+
+begin
+
+error <= '1' when (skipped_S='1') or (error1_S='1') else '0';
+IO_serialavailable <= '1' when sfifo_empty_S='0' else '0';
+
+async_outfifo: async_fifo_512x32 port map(
+	rst => reset_write_clock_S,
+	wr_clk => write_clock,
+	rd_clk => read_clock,
+	din => sfifo_data_in_S,
+	wr_en => sfifo_write_S,
+	rd_en => sfifo_read_S,
+	dout => sfifo_data_out_S,
+	full => sfifo_full_S,
+	empty => sfifo_empty_S);
+sfifo_write_S <= '1' when (writefifo_S='1') and (sfifo_full_S='0') else '0';
+	
+process(write_clock)
+begin
+	if (rising_edge(write_clock)) then 
+		if (reset_write_clock_S = '1') then
+			write_seconddata_S <= '0';
+			skipped_S <= '0';
+			writefifo_S <= '0';
+			buffer_written_S <= '0';
+		else
+			if write_seconddata_S='1' then
+				if (writefifo_S='1') and (sfifo_write_S='0') then -- unsuccessfull write
+					write_seconddata_S <= '1';
+					writefifo_S <= '1'; -- keep trying
+				else 
+					sfifo_data_in_S <= secondword_S;
+					writefifo_S <= '1';
+					write_seconddata_S <= '0';
+				end if;
+				if slowcontrol_write='1' then
+					if buffer_written_S = '1' then
+						skipped_S <= '1';
+					else
+						buffer_firstword_S <= slowcontrol_reply & "101000" & skipped_S & slowcontrol_address;
+						buffer_secondword_S <= slowcontrol_data;
+						buffer_written_S <= '1';
+					end if;
+				end if;
+			else
+				if (writefifo_S='1') and (sfifo_write_S='0') then -- unsuccessfull write
+					writefifo_S <= '1'; -- keep trying
+					write_seconddata_S <= '0';
+					if slowcontrol_write='1' then
+						if buffer_written_S = '1' then
+							skipped_S <= '1';
+						else
+							buffer_firstword_S <= slowcontrol_reply & "101000" & skipped_S & slowcontrol_address;
+							buffer_secondword_S <= slowcontrol_data;
+							buffer_written_S <= '1';
+						end if;
+					end if;
+				else 
+					if buffer_written_S='1' then
+						if slowcontrol_write='1' then
+							sfifo_data_in_S <= buffer_firstword_S(31 downto 25) & '1' & buffer_firstword_S(23 downto 0);							
+						else
+							sfifo_data_in_S <= buffer_firstword_S(31 downto 25) & skipped_S & buffer_firstword_S(23 downto 0);							
+						end if;
+						writefifo_S <= '1';
+						write_seconddata_S <= '1';
+						skipped_S <= '0';				
+					elsif slowcontrol_write='1' then
+						sfifo_data_in_S <= slowcontrol_reply & "101000" & skipped_S & slowcontrol_address;
+						secondword_S <= slowcontrol_data;
+						writefifo_S <= '1';
+						write_seconddata_S <= '1';
+						skipped_S <= '0';
+					else
+						write_seconddata_S <= '0';
+						writefifo_S <= '0';
+					end if;
+					buffer_written_S <= '0';
+				end if;
+			end if;
+		end if;
+		reset_write_clock_S <= reset;
+	end if;
+end process;
+
+
+sfifo_read_S <= '1' when (byte_idx_S=0) and (IO_write='1') and (IO_byte(7)='1') and 
+		(IO_byte(3 downto 0)=channel) and (sfifo_empty_S='0') 
+	else '0';
+	
+process(read_clock) -- one additional clockcycle to meet constraint
+begin
+	if (rising_edge(read_clock)) then 
+		if (bit_idx_S=1) then
+			IO_serialdata <= sfifo_data_out_S(31);
+		else
+			IO_serialdata <= IO_serialdata_S;
+		end if;
+	end if;
+end process;
+
+--	IO_serialdata <= sfifo_data_out_S(31) when (bit_idx_S=1) else IO_serialdata_S;
+
+rd_process: process(read_clock)
+begin
+	if (rising_edge(read_clock)) then 
+		if reset_read_clock_S='1' then
+			bit_idx_S <= 0;
+			IO_serialdata_S <= '0';
+		else
+			if bit_idx_S=0 then
+				if sfifo_read_S='1' then
+					bit_idx_S <= 1;
+				else
+					IO_serialdata_S <= '0';
+				end if;
+			else 
+				IO_serialdata_S <= sfifo_data_out_S(31-bit_idx_S);				
+				if bit_idx_S<31 then 
+					bit_idx_S <= bit_idx_S+1;
+				else
+					bit_idx_S <= 0;					
+				end if;
+			end if;
+		end if;
+		reset_read_clock_S <= reset;
+	end if;
+end process;
+
+rdbyte_process: process(read_clock)
+begin
+	if (rising_edge(read_clock)) then 
+		if reset_read_clock_S='1' then
+			byte_idx_S <= 0;
+			error1_S <= '0';
+		else
+			if byte_idx_S=0 then
+				error1_S <= '0';
+				if (IO_write='1') then
+					if (IO_byte(7)='0') then
+						byte_idx_S <= 1;
+					end if;
+				end if;
+			else
+				if (IO_write='1')  then
+					error1_S <= '0';
+					if byte_idx_S<4 then
+						byte_idx_S <= byte_idx_S + 1;
+					else
+						byte_idx_S <= 0;
+					end if;
+				else -- error
+					error1_S <= '1';
+					byte_idx_S <= 0;
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+
+end Behavioral;
diff --git a/data_concentrator/sources/DC_sorting_mux.vhd b/data_concentrator/sources/DC_sorting_mux.vhd
new file mode 100644
index 0000000..5474c6e
--- /dev/null
+++ b/data_concentrator/sources/DC_sorting_mux.vhd
@@ -0,0 +1,471 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   25-02-2014
+-- Module Name:   DC_sorting_mux
+-- Description:   Multiplexer for pulse (=hit) data, sorting on timestamp
+-- Modifications:
+--   30-07-2014   Timestamp is now the time within the superburst
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- DC_sorting_mux
+-- Multiplexes multiple input pulse data stream to one stream.
+-- The input consists of packets with four 36-bits words: 32 bits data and 4 bits for index/check
+-- The data is sorted based on the superburst number, the 16-bits timestamp within the superburst and the fractional part.
+-- This sorting is done by comparing the time of 2 items; the first in time is passed on.
+-- Multiple of these comparators are placed in a tree structure. The last segment provides the sorted data.
+--
+-- Library:
+--     work.panda_package: constants and types
+--
+-- Generics:
+--     NROFMUXINPUTS : number of input-channels
+--     MUXINFIFOSIZE : size of the input fifos (in address-bits)
+--     TRANSFERFIFOSIZE : size of the output fifo (in address-bits)
+--     CF_FRACTIONBIT : number of valid constant fraction bits
+--
+-- Inputs:
+--     inputclock : clock for input data (write side incomming fifo)
+--     MUXclock : clock for multiplexer part, between the fifos
+--     outputclock : clock for output data (read side outgoing fifo)
+--     reset : reset, must be long enough for all clocks
+--     data_in : array of input data streams, structure of each:
+--        word0 : 0 & 0000 & timestamp(15..0)
+--        word1 : 1 & 0 & superburstnumber(30..0)
+--        word2 : 2 & statusbyte & 00 & adcnumber
+--        word3 : 3 & timefraction & energy
+--     data_in_write : write signal for data_in (write into fifo)
+--     data_out_read : read signal for outgoing data (read from fifo)
+-- 
+-- Outputs:
+--     data_in_allowed : write to input data allowed (not full)
+--     fiber_index : index of the fiber
+--     channel : pulse-data : adc channel number
+--     statusbyte : pulse-data : status
+--     energy : pulse-data : energy
+--     timefraction : pulse-data : Constant Fraction time
+--     timestamp : pulse-data : time (ADC-clock)
+--     superburstnumber : pulse-data : superburstnumber
+--     data_out_available : data_out available (output fifo not empty)
+--     infifo_fullness : array with number of words in input fifo's
+--     outfifo_fullness : number of words in output fifo
+--     error : data error, index in data words incorrect
+-- 
+-- Components:
+--     DC_read36bitsfifo : read data from fifo and writes to next level
+--     DC_mux2to1 : compares the data and passes the first in time on
+--     async_fifo_nn_th_512x36 : asynchronous fifo with number of words in fifo
+--     async_fifo_nn_4096x103 : large asynchronous fifo with number of words in fifo
+--
+--
+--
+----------------------------------------------------------------------------------
+
+entity DC_sorting_mux is
+	generic(
+		NROFMUXINPUTS           : natural := 4;
+		MUXINFIFOSIZE           : natural := 9;
+		TRANSFERFIFOSIZE        : natural := 12;
+		CF_FRACTIONBIT          : natural := 11
+	);
+    port ( 
+		inputclock              : in std_logic;
+		MUXclock                : in std_logic; 
+		outputclock             : in std_logic; 
+		reset                   : in std_logic;
+		data_in                 : in array_fiber36bits_type;
+		data_in_write           : in std_logic_vector(0 to NROFMUXINPUTS-1);
+		data_in_allowed         : out std_logic_vector(0 to NROFMUXINPUTS-1);
+		fiber_index             : out std_logic_vector(3 downto 0);
+		channel                 : out std_logic_vector(15 downto 0);
+		statusbyte              : out std_logic_vector(7 downto 0);
+		energy                  : out std_logic_vector(15 downto 0);
+		timefraction            : out std_logic_vector(11 downto 0);
+		timestamp               : out std_logic_vector(15 downto 0);
+		superburstnumber        : out std_logic_vector(30 downto 0);		
+		data_out_read           : in std_logic;
+		data_out_available      : out std_logic;
+		infifo_fullness         : out array_fiber16bits_type;
+		outfifo_fullness        : out std_logic_vector(15 downto 0);
+		testword0               : out std_logic_vector(35 downto 0);
+		testword1               : out std_logic_vector(35 downto 0);
+		error                   : out std_logic);
+end DC_sorting_mux;
+
+
+architecture Behavioral of DC_sorting_mux is
+
+component DC_read36bitsfifo is
+	port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(35 downto 0);
+		data_in_available       : in std_logic;
+		data_in_read            : out std_logic;
+		channel                 : out std_logic_vector(15 downto 0);
+		statusbyte              : out std_logic_vector(7 downto 0);
+		energy                  : out std_logic_vector(15 downto 0);
+		timefraction            : out std_logic_vector(11 downto 0);
+		timestamp               : out std_logic_vector(15 downto 0);
+		superburstnumber        : out std_logic_vector(30 downto 0);
+		data_out_write          : out std_logic;
+		data_out_trywrite       : out std_logic;
+		data_out_inpipe         : out std_logic;
+		data_out_allowed        : in std_logic;
+		error                   : out std_logic);
+end component;
+
+component DC_mux2to1 is
+	generic (
+		CF_FRACTIONBIT          : natural := CF_FRACTIONBIT
+	);
+	port (
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		fiber_index1            : in std_logic_vector(3 downto 0);
+		channel1                : in std_logic_vector(15 downto 0);
+		statusbyte1             : in std_logic_vector(7 downto 0);
+		energy1                 : in std_logic_vector(15 downto 0);
+		timefraction1           : in std_logic_vector(11 downto 0);
+		timestamp1              : in std_logic_vector(15 downto 0);
+		superburstnumber1       : in std_logic_vector(30 downto 0);
+		data1_in_write          : in std_logic;
+		data1_in_inpipe         : in std_logic;
+		data1_in_allowed        : out std_logic;
+		fiber_index2            : in std_logic_vector(3 downto 0);
+		channel2                : in std_logic_vector(15 downto 0);
+		statusbyte2             : in std_logic_vector(7 downto 0);
+		energy2                 : in std_logic_vector(15 downto 0);
+		timefraction2           : in std_logic_vector(11 downto 0);
+		timestamp2              : in std_logic_vector(15 downto 0);
+		superburstnumber2       : in std_logic_vector(30 downto 0);
+		data2_in_write          : in std_logic;
+		data2_in_inpipe         : in std_logic;
+		data2_in_allowed        : out std_logic;
+		fiber_index             : out std_logic_vector(3 downto 0);
+		channel                 : out std_logic_vector(15 downto 0);
+		statusbyte              : out std_logic_vector(7 downto 0);
+		energy                  : out std_logic_vector(15 downto 0);
+		timefraction            : out std_logic_vector(11 downto 0);
+		timestamp               : out std_logic_vector(15 downto 0);
+		superburstnumber        : out std_logic_vector(30 downto 0);
+		data_out_write          : out std_logic;
+		data_out_inpipe         : out std_logic;
+		data_out_allowed        : in std_logic;
+		error                   : out std_logic;
+		testword0               : out std_logic_vector(35 downto 0)
+		);
+end component;
+
+component async_fifo_nn_th_512x36
+	port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(35 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(35 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic;
+		rd_data_count           : out std_logic_vector(MUXINFIFOSIZE-1 downto 0);
+		prog_empty              : out std_logic);
+end component;
+
+component async_fifo_nn_4096x103
+	port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(102 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(102 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic;
+		rd_data_count           : out std_logic_vector(11 downto 0));
+end component;
+
+
+type twologarray_type is array(0 to 63) of natural;
+constant twologarray : twologarray_type :=
+(0,0,1,1,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5);
+
+constant mux2to1_gen_max      : integer := twologarray(NROFMUXINPUTS); 
+constant INPIPE_DELAY         : integer := 63;
+constant zeros                : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+constant ones                 : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '1');
+
+
+type fiber_index_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic_vector(3 downto 0);
+type channel_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic_vector(15 downto 0);
+type statusbyte_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic_vector(7 downto 0);
+type energy_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic_vector(15 downto 0);
+type timefraction_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic_vector(11 downto 0);
+type timestamp_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic_vector(15 downto 0);
+type superburstnumber_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic_vector(30 downto 0);
+
+
+attribute syn_keep     : boolean;
+attribute syn_preserve : boolean;
+
+type singlebit_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic_vector(30 downto 0);
+
+signal error_S                : std_logic := '0';
+signal DC_read36_error_S      : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+
+signal fiber_index_S          : fiber_index_type;
+signal channel_S              : channel_type;
+signal statusbyte_S           : statusbyte_type;
+signal energy_S               : energy_type;
+signal timefraction_S         : timefraction_type;
+signal timestamp_S            : timestamp_type;
+signal superburstnumber_S     : superburstnumber_type;
+
+signal data_out_inpipe_S      : singlebit_type := (others => (others => (others => '0')));
+signal data_write_S           : singlebit_type := (others => (others => (others => '0')));
+signal data_allowed_S         : singlebit_type := (others => (others => (others => '0')));
+signal error_array_S          : singlebit_type := (others => (others => (others => '0')));
+
+signal reset_MUXclock_S       : std_logic := '0';
+
+-- signals for fifo from adc-fe to adc-mux
+signal dfifo_wr_S             : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_rd_S             : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_out_S            : array_fiber36bits_type := (others => (others => '0'));
+signal dfifo_full_S           : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_empty_S          : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal data_in_available_S    : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal infifo_fullness_S      : array_fiber16bits_type;
+signal dfifo_prog_empty_S     : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+
+signal delay_inpipe_S         : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal read36_inpipe_S        : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_wr_MUXclock_S    : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+
+
+-- signals for fifo from adc-mux to packet-composer
+signal tfifo_in_S             : std_logic_vector (102 downto 0);
+signal tfifo_rd_S             : std_logic := '0';
+signal tfifo_full_S           : std_logic := '0';
+signal tfifo_empty_S          : std_logic := '0';
+
+--type testword_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic_vector (35 downto 0);
+--signal testword0_S            : testword_type;
+signal time_error_S           : std_logic := '0';
+signal idx_error_S            : std_logic := '0';
+
+attribute syn_keep of data_write_S     : signal is true;
+attribute syn_preserve of data_write_S : signal is true;
+attribute syn_keep of data_allowed_S     : signal is true;
+attribute syn_preserve of data_allowed_S : signal is true;
+attribute syn_keep of data_out_inpipe_S     : signal is true;
+attribute syn_preserve of data_out_inpipe_S : signal is true;
+
+begin
+
+error <= '1' when (error_S='1') or (DC_read36_error_S/=zeros) else '0';
+
+
+MUX_mux_inputs: for index in 0 to NROFMUXINPUTS-1 generate 
+
+process(MUXclock)
+type inpipe_counter_type is array(0 to NROFMUXINPUTS-1) of integer range 0 to INPIPE_DELAY;
+variable inpipe_counter_V : inpipe_counter_type := (others => 0);
+variable index_other : integer range 0 to NROFMUXINPUTS-1;
+begin
+	if rising_edge(MUXclock) then
+		if reset_MUXclock_S='1' then
+			inpipe_counter_V(index) := 0;
+			delay_inpipe_S(index) <= '0';
+			dfifo_wr_MUXclock_S(index) <= '0';
+		else
+			index_other := conv_integer(unsigned((conv_std_logic_vector(index,8) xor x"01")));
+			if ((dfifo_wr_MUXclock_S(index)='1') and (dfifo_prog_empty_S(index)='1')) or
+				((dfifo_wr_MUXclock_S(index_other)='1') and (dfifo_prog_empty_S(index_other)='1'))
+				then
+				inpipe_counter_V(index) := INPIPE_DELAY;
+				delay_inpipe_S(index) <= '1';
+			else			
+				if inpipe_counter_V(index)/=0 then
+					inpipe_counter_V(index) := inpipe_counter_V(index)-1;
+					delay_inpipe_S(index) <= '1';
+				else
+					delay_inpipe_S(index) <= '0';
+				end if;
+			end if;
+			dfifo_wr_MUXclock_S(index) <= dfifo_wr_S(index);
+		end if;
+	end if;
+end process;
+
+
+dfifo: async_fifo_nn_th_512x36 port map(
+		rst => reset,
+		wr_clk => inputclock,
+		rd_clk => MUXclock,
+		din => data_in(index),
+		wr_en => dfifo_wr_S(index),
+		rd_en => dfifo_rd_S(index),
+		dout => dfifo_out_S(index),
+		full => dfifo_full_S(index),
+		empty => dfifo_empty_S(index),
+		rd_data_count => infifo_fullness_S(index)(MUXINFIFOSIZE-1 downto 0),
+		prog_empty => dfifo_prog_empty_S(index));
+		
+infifo_fullness_S(index)(15 downto MUXINFIFOSIZE) <= (others => '0');
+infifo_fullness <= infifo_fullness_S;
+dfifo_wr_S(index) <= '1' when (dfifo_full_S(index)='0') and (data_in_write(index)='1') else '0';
+data_in_allowed(index) <= NOT dfifo_full_S(index);
+
+data_in_available_S(index) <= '1' when dfifo_empty_S(index)='0' else '0';
+
+DC_read36bitsfifo1: DC_read36bitsfifo port map(
+		clock => MUXclock,
+		reset => reset_MUXclock_S,
+		data_in => dfifo_out_S(index),
+		data_in_available => data_in_available_S(index),
+		data_in_read => dfifo_rd_S(index),
+		channel => channel_S(0,index),
+		statusbyte => statusbyte_S(0,index),
+		energy => energy_S(0,index),
+		timefraction => timefraction_S(0,index),
+		timestamp => timestamp_S(0,index),
+		data_out_trywrite => open,
+		superburstnumber => superburstnumber_S(0,index),
+		data_out_write => data_write_S(0,index)(0),
+		data_out_inpipe => read36_inpipe_S(index),
+		data_out_allowed => data_allowed_S(0,index)(0),
+		error => DC_read36_error_S(index));
+fiber_index_S(0,index) <= conv_std_logic_vector(index,4);
+
+--process(data_out_inpipe_S(0,index)(0),read36_inpipe_S(index),dfifo_prog_empty_S,delay_inpipe_S,dfifo_wr_MUXclock_S)
+process(data_out_inpipe_S(0,index)(0),read36_inpipe_S(index),delay_inpipe_S,dfifo_wr_MUXclock_S)
+--variable index_other : integer range 0 to NROFMUXINPUTS-1;
+begin
+--	index_other := conv_integer(unsigned((conv_std_logic_vector(index,16) xor x"0001")));
+--	if (read36_inpipe_S(index)='1') or ((dfifo_prog_empty_S(index_other)='1') and (delay_inpipe_S(index)='1')) or
+--		(dfifo_wr_occuredrecently_S(index)='1') or -- was there a write recently (time: one datapacket plus a few slowcontrols ?
+ 	if (read36_inpipe_S(index)='1') or (delay_inpipe_S(index)='1') or
+		(dfifo_wr_MUXclock_S(index)='1') then
+		data_out_inpipe_S(0,index)(0) <= '1';
+	else
+		data_out_inpipe_S(0,index)(0) <= '0';
+	end if;
+end process;
+			
+end generate;
+
+
+MUX_multiplex2to1_all: for i1 in 0 to mux2to1_gen_max-1 generate 
+
+	MUX_multiplex2to1_i: for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 generate 
+	
+		DC_mux2to1_1: DC_mux2to1 port map(
+			clock => MUXclock,
+			reset => reset_MUXclock_S,
+			fiber_index1 => fiber_index_S(i1,i2*2),
+			channel1 => channel_S(i1,i2*2),
+			statusbyte1 => statusbyte_S(i1,i2*2),
+			energy1 => energy_S(i1,i2*2),
+			timefraction1 => timefraction_S(i1,i2*2),
+			timestamp1 => timestamp_S(i1,i2*2),
+			superburstnumber1 => superburstnumber_S(i1,i2*2),
+			data1_in_write => data_write_S(i1,i2*2)(0),
+			data1_in_inpipe => data_out_inpipe_S(i1,i2*2)(0),
+			data1_in_allowed => data_allowed_S(i1,i2*2)(0),
+			fiber_index2 => fiber_index_S(i1,i2*2+1),
+			channel2 => channel_S(i1,i2*2+1),
+			statusbyte2 => statusbyte_S(i1,i2*2+1),
+			energy2 => energy_S(i1,i2*2+1),
+			timefraction2 => timefraction_S(i1,i2*2+1),
+			timestamp2 => timestamp_S(i1,i2*2+1),
+			superburstnumber2 => superburstnumber_S(i1,i2*2+1),
+			data2_in_write => data_write_S(i1,i2*2+1)(0),
+			data2_in_inpipe => data_out_inpipe_S(i1,i2*2+1)(0),
+			data2_in_allowed => data_allowed_S(i1,i2*2+1)(0),
+			fiber_index => fiber_index_S(i1+1,i2),
+			channel => channel_S(i1+1,i2),
+			statusbyte => statusbyte_S(i1+1,i2),
+			energy => energy_S(i1+1,i2),
+			timefraction => timefraction_S(i1+1,i2),
+			timestamp => timestamp_S(i1+1,i2),
+			superburstnumber => superburstnumber_S(i1+1,i2),
+			data_out_write => data_write_S(i1+1,i2)(0),
+			data_out_inpipe => data_out_inpipe_S(i1+1,i2)(0),
+			data_out_allowed => data_allowed_S(i1+1,i2)(0),
+			error => error_array_S(i1,i2)(0),
+			testword0 => open); -- testword0_S(i1,i2));
+
+	end generate;
+end generate;
+
+process(MUXclock)
+begin
+	if (rising_edge(MUXclock)) then 
+		error_S <= '0';
+		for i1 in 0 to mux2to1_gen_max-1 loop 
+			for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 loop 
+				if error_array_S(i1,i2)(0)='1' then
+					error_S <= '1';
+				end if;
+			end loop;
+		end loop;
+	end if;
+end process;
+
+data_allowed_S(mux2to1_gen_max,0)(0) <= '1' when (tfifo_full_S='0') else '0';
+
+tfifo_in_S <= 
+			fiber_index_S(mux2to1_gen_max,0) &        -- 102..99
+			superburstnumber_S(mux2to1_gen_max,0) &   -- 98..68
+			timestamp_S(mux2to1_gen_max,0) &          -- 67..52
+			timefraction_S(mux2to1_gen_max,0) &       -- 51..40
+			energy_S(mux2to1_gen_max,0) &             -- 39..24
+			statusbyte_S(mux2to1_gen_max,0) &         -- 23..16
+			channel_S(mux2to1_gen_max,0);             -- 15..0
+
+tfifo: async_fifo_nn_4096x103 port map(
+		rst => reset,
+		wr_clk => MUXclock,
+		rd_clk => outputclock,
+		din => tfifo_in_S,
+		wr_en => data_write_S(mux2to1_gen_max,0)(0),
+		rd_en => tfifo_rd_S,
+		dout(15 downto 0) => channel,
+		dout(23 downto 16) => statusbyte,
+		dout(39 downto 24) => energy,
+		dout(51 downto 40) => timefraction,
+		dout(67 downto 52) => timestamp,
+		dout(98 downto 68) => superburstnumber,
+		dout(102 downto 99) => fiber_index,
+		full => tfifo_full_S,
+		empty => tfifo_empty_S,
+		rd_data_count => outfifo_fullness(TRANSFERFIFOSIZE-1 downto 0));
+outfifo_fullness(15 downto TRANSFERFIFOSIZE) <= (others => '0');
+		
+tfifo_rd_S <= '1' when (data_out_read='1') and (tfifo_empty_S='0') else '0';
+data_out_available <= '1' when tfifo_empty_S='0' else '0';
+
+
+process(MUXclock)
+begin
+	if (rising_edge(MUXclock)) then 
+		reset_MUXclock_S <= reset;
+	end if;
+end process;
+
+
+
+testword0(35 downto 0) <= (others => '0');
+testword1(35 downto 0) <= (others => '0');
+
+end Behavioral;
+
diff --git a/data_concentrator/sources/DC_split_data.vhd b/data_concentrator/sources/DC_split_data.vhd
new file mode 100644
index 0000000..d1f247f
--- /dev/null
+++ b/data_concentrator/sources/DC_split_data.vhd
@@ -0,0 +1,634 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   04-03-2014
+-- Module Name:   DC_split_data 
+-- Description:   Read and interprets data from Front End Electronics
+-- Modifications:
+--   30-07-2014   Timestamp from FEE is now composed by 16 bits superburstnumber and timestamp counter within superburst
+--   11-09-2014   New name, new fiber data structure; removed correction LUTs (will be done separately)
+--   11-10-2014   Energy is measured with integral, not with the maximum
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- DC_split_data
+-- Gets packet data from the fiber receive module and separate pulse-data, waveforms and slowcontrol.
+-- The waveforms are assigned to a superburst number, based on timestamp.
+-- 
+--
+-- Three types of packets are possible:
+--
+-- The data packets : 4 32-bit words, with CRC8 in last word
+--   0xDA ADCnumber(7..0) superburstnumber(15..0)
+--   0000 energy(15..0) 
+--   CF_before(15..0) CF_after(15..0)
+--   timestamp(15..0) statusbyte(7..0) CRC8(7..0)
+--
+-- The slow control packets : 2 32-bit words, with CRC8 in last word
+--   0x5C address(7..0) replybit 0000000 data(31..24)
+--   data(23..0) CRC8(7..0)
+--
+-- The waveform packets : 32-bit words, with CRC8 in last word
+--   0xAF ADCnumber(7..0) superburstnumber(15..0)
+--   timestamp(15..0) 0x00 statusbyte(7..0)
+--   0 adc0(14..0) 0 adc1(14..0) : 2 adc-samples 15 bits signed
+--   0 adc2(14..0) 0 adc3(14..0) : next 2 adc-samples 15 bits signed
+--   .........
+--   1 adcn(14..0) 1 00 CRC8(7..0) : last 32-bit word: last adc-sample 15 bits signed
+--         or
+--   0 0000 1 00 CRC8(7..0) : last 32-bit word: no sample--
+--
+-- The slow-control commands are written as parallel data and address. It should be connected to a fifo 
+-- that is large enough to handle all slow-control data, otherwise commands will be lost.
+--
+--
+--
+-- Library:
+--     work.panda_package :  for type declarations and constants
+-- 
+-- Generics:
+--     NROFADCS : number of ADCs in the FEE: total high and low gain ADCs 
+--     ADCINDEXSHIFT : ADC channel numbers lowest bit indicates the high or low gain ADC, 0=high, 1=low
+--     CF_FRACTIONBIT : number of valid constant fraction bits
+-- 
+-- Inputs:
+--     clock : clock input : fiber receiver clock
+--     SODA_clock : clock SODA, used for superburstnumber
+--     reset : synchronous reset
+--     enable : enable datareading from receiver
+--     FEEboardnumber : number of the board, this is added to the ADC channel number for the final ADC channel identification
+--     packet_data_in : 32 bits data input from fiber module
+--     packet_data_present : data available from fiber module
+--     pulse_allowed : output data writing (4 words) allowed  : not fifo-almostfull of connected fifo
+--     wave_data_out_allowed : output of full waveform writing allowed : possible to write 254 samples!!
+--     superburst_number : most recent superburst-number
+--     superburst_update : new most recent superburst-number+timestamp
+-- 
+-- Outputs:
+--     packet_data_read : read signal to fiber module to read next data
+--     pulse_superburst : lowest 16-bits of the superburstnumber of the hit
+--     pulse_timestamp : 16-bits timestamp within superburst (time of sample before the CF zero crossing)
+--     pulse_adcnumber : 16-bits adc channel number
+--     pulse_statusbyte : 8-bits status
+--     pulse_energy : energy of the pulse, measured with scaled integral
+--     pulse_CF_before : CF_signal value of the value before the zero-crossing (absolute value)
+--     pulse_CF_after : CF_signal value of the value after the zero-crossing (absolute value)
+--     pulse_write : write signal for pulsedata
+--     slowcontrol_data : slow-control command : data 32-bits 
+--     slowcontrol_address : slow-control command : only FEE part: address 8-bits 
+--     slowcontrol_reply : indicates if the slow-control is a reply, or a independent message
+--     slowcontrol_write : write of slow-control data/address/reply
+--     wave_data_out : data with waveform: 36-bits words with bits 35..32 as index
+--        	bits(35..32)="0000" : bits(15..0)=timestamp within superburst in waveform
+--        	bits(35..32)="0001" : bits(31)=0 bits(30..0)=SuperBurst number
+--        	bits(35..32)="0010" : 
+--              bits(31..24) = statusbyte (bit7=overflow) 
+--              bits(23..16) = 00
+--              bits(15..0) = adcnumber (channel identification)
+--        	bits(35..32)="0011" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+--        	bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+--        	bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+--        	bits(35..32)="1111" : error: buffer full, waveform not valid
+--     wave_data_write :  waveform data write signal
+--     pulse_data_skipped : data remove due to full connected fifo
+--     data_error : error in packet-data : CRC-error, hamming-code error, error in data bits
+--
+-- Components:
+--     crc8_add_check32 : add and checks a CRC8 code to a stream of 32 bits data words
+-- 
+----------------------------------------------------------------------------------
+
+entity DC_split_data is
+	generic (
+		NROFADCS                : natural := 32;
+		ADCINDEXSHIFT           : natural := 1;
+		CF_FRACTIONBIT          : natural := 11
+	);
+    Port ( 
+		clock                   : in std_logic;
+		SODA_clock              : in  std_logic;
+		reset                   : in std_logic;
+		enable                  : in std_logic;
+		FEEboardnumber          : in std_logic_vector (15 downto 0);
+		packet_data_in          : in std_logic_vector (31 downto 0);
+		packet_data_present     : in std_logic;
+		packet_data_read        : out std_logic;
+		pulse_superburst        : out std_logic_vector(15 downto 0);
+		pulse_timestamp         : out std_logic_vector(15 downto 0);
+		pulse_adcnumber         : out std_logic_vector(15 downto 0);
+		pulse_statusbyte        : out std_logic_vector(7 downto 0);
+		pulse_energy            : out std_logic_vector(15 downto 0);
+		pulse_CF_before         : out std_logic_vector(15 downto 0);
+		pulse_CF_after          : out std_logic_vector(15 downto 0);
+		pulse_allowed           : in std_logic;
+		pulse_write             : out std_logic;
+		slowcontrol_data        : out std_logic_vector(31 downto 0);
+		slowcontrol_address     : out std_logic_vector(7 downto 0);
+		slowcontrol_reply       : out std_logic;
+		slowcontrol_write       : out std_logic;			  
+		wave_data_out           : out std_logic_vector(35 downto 0);
+		wave_data_write         : out std_logic;
+		wave_data_out_allowed   : in std_logic;
+		superburst_number       : in std_logic_vector(30 downto 0);
+		superburst_update       : in std_logic;
+		pulse_data_skipped      : out std_logic;
+		data_error              : out std_logic;
+		testword0               : out std_logic_vector(35 downto 0));
+end DC_split_data;
+
+architecture Behavioral of DC_split_data is
+
+component crc8_add_check32 is 
+   port(           
+		clock                   : in  std_logic; 
+		reset                   : in  std_logic; 
+		data_in                 : in  std_logic_vector(31 DOWNTO 0); 
+		data_in_valid           : in  std_logic; 
+		data_in_last            : in  std_logic; 
+		data_out                : out std_logic_vector(31 DOWNTO 0); 
+		data_out_valid          : out std_logic;
+		data_out_last           : out std_logic;
+		crc_error               : out std_logic
+       );
+end component; 
+
+--     PASTSUPERBURSTBITS : number of bits for data array remembering previous SUPERBURSTS, depends on data latency from FEE
+constant PASTSUPERBURSTBITS         : natural := 3;
+constant zeros                      : std_logic_vector(31 downto 0) := (others => '0');
+
+type superbursttime_type is array (0 to 2**PASTSUPERBURSTBITS-1) of std_logic_vector (15 downto 0);
+type superbursts_type is array (0 to 2**PASTSUPERBURSTBITS-1) of std_logic_vector (30 downto 0);
+ 
+type rec_state_type is (init,expect_first,data1,data2,data3,slow1,wave1,wave2,wave3,wave4,wave5);
+signal rec_state_S                  : rec_state_type := init;
+
+signal timestampcounter_S           : std_logic_vector (15 downto 0) := (others => '0');
+--signal superburst_timestamps_S      : superbursttime_type := (others => (others => '0'));
+signal superburst_numbers0_S        : superbursts_type := (others => (others => '0'));
+signal superburst_numbers_S         : superbursts_type;
+
+signal FEEboardnumber_S             : std_logic_vector (15 downto 0);
+signal reset_S                      : std_logic := '0';
+signal error_S                      : std_logic := '0';
+signal enable_S                     : std_logic := '0';
+signal packet_data_read_S           : std_logic := '0';
+signal packet_data_valid_S          : std_logic := '0';
+
+signal crc8_data_in_S               : std_logic_vector (31 downto 0) := (others => '0');
+signal crc8_data_in_valid_S         : std_logic := '0';
+signal crc8_data_in_last_S          : std_logic := '0';
+signal crc8_data_out_S              : std_logic_vector (31 downto 0) := (others => '0');
+signal crc8_data_out_valid_S        : std_logic := '0';
+signal crc8_data_out_last_S         : std_logic := '0';
+signal crc8_error_S                 : std_logic := '0';
+signal crc8_dataerror_S             : std_logic := '0';
+signal datapacketcounter_S          : integer range 0 to 3 := 0; 
+signal slowpacketvalid_S            : std_logic := '0';
+signal crc8_slowerror_S             : std_logic := '0';
+	
+signal pulse_superburst16_S         : std_logic_vector (15 downto 0);
+signal pulse_timestamp_S            : std_logic_vector (15 downto 0);
+signal pulse_adc_number_S           : std_logic_vector (15 downto 0);
+signal pulse_energy_S               : std_logic_vector (15 downto 0);
+signal pulse_CF_before_S            : std_logic_vector (15 downto 0);
+signal pulse_CF_after_S             : std_logic_vector (15 downto 0);
+signal pulse_statusbyte_S           : std_logic_vector (7 downto 0);
+
+signal wave_superburst16_S          : std_logic_vector (15 downto 0);
+signal wave_adc_number_S            : std_logic_vector (15 downto 0);
+signal wave_statusbyte_S            : std_logic_vector (7 downto 0);
+
+signal pulse_valid_S                : std_logic;
+signal pulse_data_write_S           : std_logic;
+signal pulse_data_skipped_S         : std_logic := '0';
+
+signal wave_data_out_S              : std_logic_vector (35 downto 0);
+signal wave_data_write_S            : std_logic := '0';
+signal wave_overflow_S              : std_logic := '0';
+signal wave_valid_S                 : std_logic := '0';
+signal wave_allow_write_S           : std_logic := '1';
+signal wave_last_singledata_S       : std_logic := '0';
+signal wave_overflow_occurred_S     : std_logic := '0';
+signal wave_superburstmissed_S      : std_logic := '0';
+signal wave_superburstnr_S          : std_logic_vector (30 downto 0);
+
+signal adcsample0_S                 : std_logic_vector (15 downto 0);
+signal adcsample1_S                 : std_logic_vector (15 downto 0);
+
+
+begin
+
+pulse_data_skipped <= '1' when (pulse_data_skipped_S='1') or (wave_overflow_S='1') else '0';
+data_error <= '1' when (error_S='1') else '0';
+
+process(SODA_clock)
+begin
+	if rising_edge(SODA_clock) then
+		if superburst_update='1' then
+--			superburst_timestamps0_S(conv_integer(unsigned(superburst_number(PASTSUPERBURSTBITS-1 downto 0)))) <= timestampcounter_S;
+			superburst_numbers0_S(conv_integer(unsigned(superburst_number(PASTSUPERBURSTBITS-1 downto 0)))) <= superburst_number;
+			timestampcounter_S <= x"0001"; --(others => '0');
+		else
+			timestampcounter_S <= timestampcounter_S+1;
+		end if;
+	end if;
+end process;
+
+process(clock)
+begin
+	if rising_edge(clock) then
+--		superburst_timestamps_S <= superburst_timestamps0_S;
+		superburst_numbers_S <= superburst_numbers0_S;
+		reset_S <= reset;
+		FEEboardnumber_S <= FEEboardnumber;
+	end if;
+end process;
+			
+
+packet_data_read <= packet_data_read_S;
+packet_data_read_S <= '1' when (packet_data_present='1') and (rec_state_S/=init) and (rec_state_S/=wave2) else '0';
+
+crc8_data_in_S <= packet_data_in;
+crc8_data_in_valid_S <= '1' when (packet_data_valid_S='1') or (rec_state_S=init) else '0';
+crc8_data_in_last_S <= 
+	'1' when (rec_state_S=data3)
+			or (rec_state_S=slow1) 
+			or (rec_state_S=init) 
+			or ((rec_state_S=wave5) and (packet_data_valid_S='1') and (packet_data_in(15)='1'))
+		else '0';
+
+crc8check: crc8_add_check32 port map(
+	  clock          => clock,
+	  reset          => reset_S,
+	  data_in        => crc8_data_in_S,
+	  data_in_valid  => crc8_data_in_valid_S,
+	  data_in_last   => crc8_data_in_last_S, 
+	  data_out       => crc8_data_out_S,
+	  data_out_valid => crc8_data_out_valid_S,
+	  data_out_last  => crc8_data_out_last_S,
+	  crc_error      => crc8_error_S);
+
+wave_data_out <= wave_data_out_S;
+wave_data_write <= wave_data_write_S;
+
+inputdatahandling: process(clock)
+variable timeoutcounter_V        : integer range 0 to 15 := 0;
+variable superburstnr_V          : std_logic_vector(30 downto 0);
+variable statusbyte_V            : std_logic_vector(7 downto 0);
+begin
+	if rising_edge(clock) then
+		pulse_valid_S <= '0';
+		if reset_S='1' then
+			error_S <= '0';
+			pulse_valid_S <= '0';
+			rec_state_S <= init;
+			wave_valid_S <= '0';
+			wave_allow_write_S <= '1';
+			wave_last_singledata_S <= '0';
+			wave_overflow_S <= '0';
+			wave_overflow_occurred_S <= '0'; 
+			wave_superburstmissed_S <= '0';
+		elsif (crc8_dataerror_S='1') or (crc8_slowerror_S='1') then
+			error_S <= '1';
+			rec_state_S <= init;
+		else
+			case rec_state_S is
+				when init =>
+					timeoutcounter_V := 0;
+					error_S <= '0';
+					if wave_valid_S='1' then
+						wave_valid_S <= '0';
+						if error_S='1' then
+							wave_data_out_S <= "1111" & x"00000000";
+							wave_data_write_S <= wave_allow_write_S;
+						else
+							wave_data_write_S <= '0';
+						end if;
+					else
+						wave_data_write_S <= '0';
+					end if;
+					if enable_S ='1' then
+						rec_state_S <= expect_first;
+					end if;
+				when expect_first =>
+					if wave_valid_S='1' then
+						wave_valid_S <= '0';
+						if (crc8_data_out_valid_S='1') and (crc8_data_out_last_S='1') and (crc8_error_S='0') then -- everything ok
+							if wave_last_singledata_S='1' then
+								wave_data_out_S <= "0100" & adcsample0_S & x"0000";
+								wave_data_write_S <= wave_allow_write_S;
+							else
+								wave_data_write_S <= wave_allow_write_S;
+							end if;
+						else
+							wave_data_out_S <= "1111" & x"00000000";
+							wave_data_write_S <= wave_allow_write_S;
+						end if;
+					else
+						wave_data_write_S <= '0';
+					end if;					
+					timeoutcounter_V := 0;
+					if enable_S='0' then
+						rec_state_S <= init;
+					else
+						if packet_data_valid_S='1' then
+							if packet_data_in(31 downto 24)=x"DA" then -- pulse data
+								pulse_adc_number_S <= (x"00" & packet_data_in(23 downto 16)) + FEEboardnumber_S;
+								pulse_superburst16_S <= packet_data_in(15 downto 0);
+								error_S <= '0';
+								wave_overflow_S <= '0';
+								rec_state_S <= data1;
+							elsif packet_data_in(31 downto 24)=x"AF" then -- waveform
+								wave_adc_number_S <= (x"00" & packet_data_in(23 downto 16)) + FEEboardnumber_S;
+								wave_superburst16_S <= packet_data_in(15 downto 0);
+								wave_allow_write_S <= wave_data_out_allowed;
+								if wave_data_out_allowed='1' then
+									wave_overflow_S <= '0';
+								else
+									wave_overflow_occurred_S <= '1';
+									wave_overflow_S <= '1';
+								end if;
+								error_S <= '0';
+								rec_state_S <= wave1;
+							elsif packet_data_in(31 downto 24)=x"5C" then -- slowcontrol
+								slowcontrol_address <= packet_data_in(23 downto 16);
+								slowcontrol_reply <= packet_data_in(15);
+								slowcontrol_data(31 downto 24) <= packet_data_in(7 downto 0);
+								error_S <= '0';
+								rec_state_S <= slow1;
+							else -- error
+								error_S <= '1';
+								rec_state_S <= init;
+							end if;
+						else
+							rec_state_S <= expect_first;
+						end if;
+					end if;
+				when data1 =>
+					wave_valid_S <= '0';
+					wave_data_write_S <= '0';
+					if packet_data_valid_S='1' then
+						timeoutcounter_V := 0;
+						pulse_energy_S <= packet_data_in(15 downto 0);
+						rec_state_S <= data2;
+					else
+						if timeoutcounter_V=15 then
+							error_S <= '1';
+							rec_state_S <= init;
+						else
+							timeoutcounter_V := timeoutcounter_V+1;
+							rec_state_S <= data1;
+						end if;
+					end if;
+				when data2 =>
+					wave_valid_S <= '0';
+					wave_data_write_S <= '0';
+					if packet_data_valid_S='1' then
+						timeoutcounter_V := 0;
+						pulse_CF_before_S <= packet_data_in(31 downto 16);
+						pulse_CF_after_S <= packet_data_in(15 downto 0);
+						rec_state_S <= data3;
+					else
+						if timeoutcounter_V=15 then
+							error_S <= '1';
+							rec_state_S <= init;
+						else
+							timeoutcounter_V := timeoutcounter_V+1;
+							rec_state_S <= data2;
+						end if;
+					end if;
+				when data3 =>
+					wave_data_write_S <= '0';
+					wave_valid_S <= '0';
+					if packet_data_valid_S='1' then
+						timeoutcounter_V := 0;
+						pulse_timestamp_S <= packet_data_in(31 downto 16);
+						pulse_valid_S <= '1';
+						statusbyte_V := packet_data_in(15 downto 8);
+						if pulse_data_skipped_S='1' then
+							statusbyte_V := statusbyte_V or STATBYTE_DCPULSESKIPPED;
+						end if;
+						if wave_overflow_occurred_S='1' then
+							statusbyte_V := statusbyte_V or STATBYTE_DCWAVESKIPPED;
+							wave_overflow_occurred_S <= '0';
+						end if;
+						if wave_superburstmissed_S='1' then
+							statusbyte_V := statusbyte_V or STATBYTE_DCSUPERBURSTMISSED;
+							wave_superburstmissed_S <= '0';
+						end if;
+						pulse_statusbyte_S <= statusbyte_V;
+						rec_state_S <= expect_first;
+					else
+						if timeoutcounter_V=15 then
+							error_S <= '1';
+							rec_state_S <= init;
+						else
+							timeoutcounter_V := timeoutcounter_V+1;
+							rec_state_S <= data3;
+						end if;
+					end if;
+					
+				when slow1 =>
+					wave_data_write_S <= '0';
+					wave_valid_S <= '0';
+					if packet_data_valid_S='1' then
+						timeoutcounter_V := 0;
+						slowcontrol_data(23 downto 0) <= packet_data_in(31 downto 8);
+						rec_state_S <= expect_first;
+					else
+						if timeoutcounter_V=15 then
+							error_S <= '1';
+							rec_state_S <= init;
+						else
+							timeoutcounter_V := timeoutcounter_V+1;
+							rec_state_S <= slow1;
+						end if;
+					end if;
+
+				when wave1 =>
+					if packet_data_valid_S='1' then
+						wave_valid_S <= '0';
+						timeoutcounter_V := 0;
+						wave_data_out_S <= "0000" & x"0000" & packet_data_in(31 downto 16); -- timestamp 16 bits
+						if (wave_overflow_occurred_S='1') and (wave_allow_write_S='1') then
+							wave_statusbyte_S(7 downto 0) <= packet_data_in(7 downto 0) or STATBYTE_DCWAVESKIPPED;
+							wave_overflow_occurred_S <= '0';
+						else
+							wave_statusbyte_S <= packet_data_in(7 downto 0);
+						end if;
+						superburstnr_V := superburst_numbers_S(conv_integer(unsigned(wave_superburst16_S(PASTSUPERBURSTBITS-1 downto 0))));						
+						wave_superburstnr_S <= superburstnr_V;
+						if superburstnr_V(15 downto 0) /= wave_superburst16_S then
+							wave_data_write_S <= '0';
+							wave_allow_write_S <= '0';
+							wave_superburstmissed_S <= '1';
+							wave_overflow_occurred_S <= '1';
+							wave_overflow_S <= '1';
+							rec_state_S <= wave2;
+						else
+							wave_data_write_S <= wave_allow_write_S;
+							rec_state_S <= wave2;
+						end if;
+					else
+						wave_data_write_S <= '0';
+						if timeoutcounter_V=15 then
+							wave_valid_S <= '1';
+							error_S <= '1';
+							rec_state_S <= init;
+						else
+							wave_valid_S <= '0';
+							timeoutcounter_V := timeoutcounter_V+1;
+						end if;
+					end if;
+				when wave2 =>
+					wave_data_out_S <= "0001" & '0' & wave_superburstnr_S;
+					wave_data_write_S <= wave_allow_write_S;
+					wave_valid_S <= '0';
+					timeoutcounter_V := 0;
+					if packet_data_valid_S='1' then
+						adcsample0_S <= packet_data_in(30) & packet_data_in(30 downto 16);
+						adcsample1_S <= packet_data_in(14) & packet_data_in(14 downto 0);
+						rec_state_S <= wave3;
+					else
+						rec_state_S <= wave4;
+					end if;
+				when wave3 =>
+					wave_data_out_S <= "0010" & wave_statusbyte_S & x"00" & wave_adc_number_S;
+					wave_data_write_S <= wave_allow_write_S;
+					wave_valid_S <= '0';
+					timeoutcounter_V := 0;
+					rec_state_S <= wave5;
+				when wave4 =>
+					if packet_data_valid_S='1' then
+						wave_valid_S <= '0';
+						timeoutcounter_V := 0;
+						adcsample0_S <= packet_data_in(30) & packet_data_in(30 downto 16);
+						adcsample1_S <= packet_data_in(14) & packet_data_in(14 downto 0);
+						wave_data_out_S <= "0010" & wave_statusbyte_S & x"00" & wave_adc_number_S;
+						wave_data_write_S <= wave_allow_write_S;
+						wave_valid_S <= '0';
+						timeoutcounter_V := 0;
+						rec_state_S <= wave5;
+					else
+						wave_data_write_S <= '0';
+						if timeoutcounter_V=15 then
+							wave_valid_S <= '1';
+							error_S <= '1';
+							rec_state_S <= init;
+						else
+							wave_valid_S <= '0';
+							timeoutcounter_V := timeoutcounter_V+1;
+						end if;
+					end if;
+				when wave5 =>
+					if packet_data_valid_S='1' then
+						timeoutcounter_V := 0;
+						if (packet_data_in(31)='0') and (packet_data_in(15)='0') then -- 2 samples
+							wave_data_out_S <= "0011" & adcsample0_S & adcsample1_S;
+							wave_data_write_S <= wave_allow_write_S;
+							adcsample0_S <= packet_data_in(30) & packet_data_in(30 downto 16);
+							adcsample1_S <= packet_data_in(14) & packet_data_in(14 downto 0);
+						elsif (packet_data_in(31)='1') and (packet_data_in(15)='1') then -- 1 sample and CRC
+							wave_data_out_S <= "0011" & adcsample0_S & adcsample1_S;
+							wave_data_write_S <= wave_allow_write_S;
+							adcsample0_S <= packet_data_in(30) & packet_data_in(30 downto 16);
+							wave_last_singledata_S <= '1';
+							wave_valid_S <= '1';
+							rec_state_S <= expect_first;
+						elsif (packet_data_in(31)='0') and (packet_data_in(15)='1') then -- 0 samples and CRC
+							wave_data_out_S <= "0101" & adcsample0_S & adcsample1_S;
+							wave_data_write_S <= '0'; -- check CRC first
+							wave_last_singledata_S <= '0';
+							wave_valid_S <= '1';
+							rec_state_S <= expect_first;
+						else -- error
+							wave_valid_S <= '1';
+							error_S <= '1';
+							rec_state_S <= init;
+						end if;
+					else
+						wave_data_write_S <= '0';
+						if timeoutcounter_V=15 then
+							wave_valid_S <= '1';
+							error_S <= '1';
+							rec_state_S <= init;
+						else
+							wave_valid_S <= '0';
+							timeoutcounter_V := timeoutcounter_V+1;
+						end if;
+					end if;
+			end case;
+		end if;
+		enable_S <= enable;
+		packet_data_valid_S <= packet_data_read_S;
+	end if;
+end process inputdatahandling;
+
+
+pulse_superburst <= pulse_superburst16_S;
+pulse_timestamp <= pulse_timestamp_S;
+pulse_adcnumber <= pulse_adc_number_S;
+pulse_statusbyte <= pulse_statusbyte_S;
+pulse_energy <= pulse_energy_S;
+pulse_CF_before <= pulse_CF_before_S;
+pulse_CF_after <= pulse_CF_after_S;
+
+pulse_write <= '1' when (pulse_data_write_S='1') and (pulse_allowed='1') else '0';
+pulse_data_write_S <= '1' when (pulse_valid_S='1') and (crc8_data_out_valid_S='1') and (crc8_data_out_last_S='1') and (crc8_error_S='0') else '0';
+crc8_dataerror_S <= '1' when (pulse_valid_S='1') and (pulse_data_write_S='0') else '0';
+
+pulseskippedhandling: process(clock)								
+begin
+	if rising_edge(clock) then
+		if reset_S='1' then
+			pulse_data_skipped_S <= '0';
+		else
+			if (pulse_data_write_S='1') and (pulse_allowed='0') then
+				pulse_data_skipped_S <= '1';
+			elsif (pulse_data_write_S='1') and (pulse_allowed='1') then
+				pulse_data_skipped_S <= '0';
+			end if;
+		end if;
+	end if;
+end process;
+
+slowcontrolpackethandling: process(clock)
+begin
+	if rising_edge(clock) then
+		if reset_S='1' then
+			slowcontrol_write <= '0';
+			slowpacketvalid_S <= '0';
+			crc8_slowerror_S <= '0';
+		else
+			if slowpacketvalid_S='0' then
+				slowcontrol_write <= '0';
+				crc8_slowerror_S <= '0';
+				if (rec_state_S=slow1) and (packet_data_valid_S='1') then
+					slowpacketvalid_S <= '1';			
+				end if;
+			else
+				slowpacketvalid_S <= '0';
+				if (crc8_data_out_valid_S='1') and (crc8_data_out_last_S='1') and (crc8_error_S='0') then -- everything ok
+					slowcontrol_write <= '1';
+					crc8_slowerror_S <= '0';
+				else
+					slowcontrol_write <= '0';
+					crc8_slowerror_S <= '1';
+				end if;
+			end if;
+		end if;
+	end if;
+end process slowcontrolpackethandling;
+
+
+testword0 <= (others => '0');
+
+
+end Behavioral;
+
diff --git a/data_concentrator/sources/DC_superburst2packet64.vhd b/data_concentrator/sources/DC_superburst2packet64.vhd
new file mode 100644
index 0000000..b83c66d
--- /dev/null
+++ b/data_concentrator/sources/DC_superburst2packet64.vhd
@@ -0,0 +1,659 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   27-01-2014
+-- Module Name:   DC_superburst2packet64
+-- Description:   Put pulse data in 64-bits packets, based on Superburstnumber
+-- Modifications:
+--     18-07-2014 Check for too many superbirst without data, see MAXSUPERBURSTBEHIND
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- DC_superburst2packet64
+-- The pulse data members are transferred to 64bits data for fiber connection
+-- The incomming pulse data is passed on as packets with 64-bits width data.
+-- All the data from one superburst is put in one data-packet.
+-- The first word-64 contains the superburst number and the timestamp of the first pulse.
+-- The superburst are sequential. If there is no data in a superburst then the packet 
+-- contains only the superburst and zero for the timestamp.
+-- For each pulse a 64-bits word is written with measured data.
+-- The highest byte gives the number of ADC-clockcycles after the first pulse (for the first pulse this is 0)
+-- If a pulse from the next superburst is received then it is stored temporarily and 
+-- sent after a timeout, if data from a even more recent superburst is received, or if the buffer is full.
+-- The first and last 64-bits words of a packet are marked with separated signals.
+-- An empty packet has both first and last signal assigned at the same time.
+--
+-- Input data:
+--   channel : adc-index
+--   statusbyte : 8 bit status information
+--   energy : pulse energy
+--   timefraction : fraction part of the timestamp
+--   timestamp : 48 bits timestamp, synchronised to master SODA clock
+--
+-- Output data 64 bits: (for CF_FRACTIONBIT=11)
+--   U64_0 : bit63=0 SuperburstNumber(30 downto 0) 0x00000000
+--   U64_1 : offsettime(12:0) TimeFraction(10:0) status(7:0) ADCchannel(15:0) Energy(15:0) 
+--   U64_2 : offsettime(12:0) TimeFraction(10:0) status(7:0) ADCchannel(15:0) Energy(15:0)
+--   ..         ..          ..             ..                  ..            ..
+--
+--
+--
+-- Library:
+--     work.panda_package: types and constants
+--
+-- Generics:
+--     TRANSITIONBUFFERBITS : number of bits for the buffer that stores data from the next supreburst
+--     CF_FRACTIONBIT : number of valid constant fraction bits
+--
+-- Inputs:
+--     clock : clock for input and output data
+--     reset : reset
+--     channel : adc-index
+--     statusbyte : 8 bit status information
+--     energy : pulse energy
+--     timefraction : fraction part of the timestamp
+--     timestamp : 16 bits timestamp within superburst, synchronised to master SODA clock
+--     superburstnumber : superburst index number where the data is assigned to
+--     data_in_available : input data available (NOT fifo-empty from connected fifo)
+--     latestsuperburstnumber : latest superburst number that has been issued by SODA
+--     data64_out_allowed : allowed to write 64 output data (connecting fifo not full)
+-- 
+-- Outputs:
+--     data_in_read : read signal for input data
+--     data64_out : 64 bits data
+--     data64_out_write : write signal for 64 bits data
+--     data64_out_first : first 64-bits word in packet
+--     data64_out_last : last 64-bits word in packet
+--     error : error reading or writing or superburstnumber
+-- 
+-- Components:
+--     blockmem : memory block to buffer a packet before transmitting
+--
+----------------------------------------------------------------------------------
+
+entity DC_superburst2packet64 is
+	generic (
+		TRANSITIONBUFFERBITS    : natural := 9;
+		CF_FRACTIONBIT          : natural := 11
+	);
+    Port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		channel                 : in std_logic_vector(15 downto 0);
+		statusbyte              : in std_logic_vector(7 downto 0);
+		energy                  : in std_logic_vector(15 downto 0);
+		timefraction            : in std_logic_vector(11 downto 0);
+		timestamp               : in std_logic_vector(15 downto 0);
+		superburstnumber        : in std_logic_vector(30 downto 0);
+		data_in_read            : out std_logic;
+		data_in_available       : in std_logic;
+		latestsuperburstnumber  : in std_logic_vector(30 downto 0);
+		data64_out              : out std_logic_vector(63 downto 0);
+		data64_out_write        : out std_logic;
+		data64_out_first        : out std_logic;
+		data64_out_last         : out std_logic;
+		data64_out_allowed      : in std_logic;
+		error                   : out std_logic;
+		testword0               : out std_logic_vector(35 downto 0)
+	);    
+end DC_superburst2packet64;
+
+
+architecture Behavioral of DC_superburst2packet64 is
+
+component blockmem is
+	generic (
+		ADDRESS_BITS : natural := TRANSITIONBUFFERBITS;
+		DATA_BITS  : natural := 64
+		);
+	port (
+		clock                   : in  std_logic; 
+		write_enable            : in std_logic;
+		write_address           : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_in                 : in std_logic_vector(DATA_BITS-1 downto 0);
+		read_address            : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_out                : out std_logic_vector(DATA_BITS-1 downto 0)
+	);
+end component;
+
+
+constant ones                     : std_logic_vector(31 downto 0) := (others => '1');
+constant zeros                    : std_logic_vector(31 downto 0) := (others => '0');
+constant MAXWAITTIIMEBITS         : integer := 14;
+constant ENABLESUPPRESSSTARTZEROS : boolean := false;
+constant MAXSUPERBURSTBEHIND      : std_logic_vector(30 downto 0) := conv_std_logic_vector(10,31);
+type readinmode_type is (waitforfirstpacket,writesomemissingpackets,writemissingpackets,writefirstpacket,waitfornextdata,waitforallowed,
+				waitforcleanupallowed,cleanupmemoryzero,cleanupmemoryfirst,cleanupmemorynext,
+				writelastdatafrommemory);
+signal readinmode_S               : readinmode_type := waitforfirstpacket;
+
+
+signal reset_S                    : std_logic := '0';
+signal data_in_read_S             : std_logic := '0';
+signal data_in_read_after1clk_S   : std_logic := '0';
+signal data64_out_write_S         : std_logic := '0';
+signal data64_out_S               : std_logic_vector(63 downto 0) := (others => '0');
+signal data64_out_write_retry_S   : std_logic := '0';
+signal data64_out_write_final_S   : std_logic := '0';
+signal blockmem_datatin_S         : std_logic_vector(63 downto 0) := (others => '0');
+	
+signal mem_write_enable_S         : std_logic := '0';
+signal mem_write_address_S        : std_logic_vector(TRANSITIONBUFFERBITS-1 downto 0) := (others => '0');
+signal mem_read_address_S         : std_logic_vector(TRANSITIONBUFFERBITS-1 downto 0) := (others => '0');
+signal mem_read_address_p1_S      : std_logic_vector(TRANSITIONBUFFERBITS-1 downto 0) := (others => '0');
+signal mem_read_address_now_S     : std_logic_vector(TRANSITIONBUFFERBITS-1 downto 0) := (others => '0');
+signal mem_read_address_plus1_S   : std_logic_vector(TRANSITIONBUFFERBITS-1 downto 0) := (others => '0');
+
+signal timefraction_corr_S        : std_logic_vector(CF_FRACTIONBIT-1 downto 0) := (others => '0');
+signal timestamp_corr_S           : std_logic_vector(23-CF_FRACTIONBIT downto 0) := (others => '0');
+signal channel_S                  : std_logic_vector(15 downto 0) := (others => '0');
+signal statusbyte_S               : std_logic_vector(7 downto 0) := (others => '0');
+signal energy_S                   : std_logic_vector(15 downto 0) := (others => '0');
+signal timefraction_S             : std_logic_vector(CF_FRACTIONBIT-1 downto 0) := (others => '0');
+signal timestamp_S                : std_logic_vector(23-CF_FRACTIONBIT downto 0) := (others => '0');
+signal superburstnumber_S         : std_logic_vector(30 downto 0) := (others => '0');
+signal actual_superburstnumber_S  : std_logic_vector(30 downto 0) := (others => '0');
+signal actual_superburstnumber_p1_S  : std_logic_vector(30 downto 0) := (others => '0');
+signal actual_superburstnumber_p2_S  : std_logic_vector(30 downto 0) := (others => '0');
+
+signal actual_superburstnumberplusMAX_S  : std_logic_vector(30 downto 0) := (others => '0');
+
+
+signal mem_channel_S              : std_logic_vector(15 downto 0) := (others => '0');
+signal mem_statusbyte_S           : std_logic_vector(7 downto 0) := (others => '0');
+signal mem_energy_S               : std_logic_vector(15 downto 0) := (others => '0');
+signal mem_timefraction_S         : std_logic_vector(CF_FRACTIONBIT-1 downto 0) := (others => '0');
+signal mem_timestamp_S            : std_logic_vector(23-CF_FRACTIONBIT downto 0) := (others => '0');
+signal data64frommem_S            : std_logic := '0';
+
+signal superburst_new_error_S     : std_logic := '0';
+signal superburst_old_error_S     : std_logic := '0';
+signal zerosuperburst_S           : std_logic := '0';
+signal zerosuperburst_prev_S      : std_logic := '0';
+signal suppress_startzeros_S      : std_logic := '0';
+				
+signal data64buf_S                : std_logic_vector(63 downto 0) := (others => '0');
+
+signal data64buf_available_S      : std_logic := '0';
+signal data_in_memory_S           : std_logic := '0';
+signal newdataavailable_S         : std_logic := '0';
+signal error_S                    : std_logic := '0';
+signal timeoutcounter_S           : std_logic_vector(MAXWAITTIIMEBITS-1 downto 0) := (others => '0');
+
+attribute syn_keep     : boolean;
+attribute syn_preserve : boolean;
+
+type readinmode_array is array(0 to 7) of std_logic_vector(3 downto 0);
+signal debug_readinmodes_S : readinmode_array;
+signal debug_readinmode_S : std_logic_vector(3 downto 0);
+attribute syn_keep of debug_readinmodes_S : signal is true;
+attribute syn_preserve of debug_readinmodes_S : signal is true;
+attribute syn_keep of debug_readinmode_S : signal is true;
+attribute syn_preserve of debug_readinmode_S : signal is true;
+
+begin
+
+timefraction_corr_S <= timefraction(CF_FRACTIONBIT-1 downto 0);
+timestamp_corr_S <= ones(23-CF_FRACTIONBIT downto 0) when timestamp>ones(23-CF_FRACTIONBIT downto 0)
+	else timestamp(23-CF_FRACTIONBIT downto 0);
+
+
+
+zerosuperburst_S <= '1' when latestsuperburstnumber=zeros(30 downto 0) else '0';
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if (zerosuperburst_S='1') and (zerosuperburst_prev_S='0') then
+			reset_S <= '1';
+		else
+			reset_S <= reset;
+		end if;
+		zerosuperburst_prev_S <= zerosuperburst_S;
+	end if;
+end process;
+
+
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		error <= error_S;
+	end if;
+end process;
+
+error_S <= '1' when
+	((data64_out_write_final_S='1') and (data64_out_allowed='0')) or
+	((data_in_read_after1clk_S='1') and (not ((readinmode_S=waitforfirstpacket) or (readinmode_S=waitfornextdata)))) or
+	(superburst_new_error_S='1') or
+	(superburst_old_error_S='1')
+	else '0';
+	
+blockmem1: blockmem port map(
+		clock => clock,
+		write_enable => mem_write_enable_S,
+		write_address => mem_write_address_S,
+		data_in => blockmem_datatin_S,
+		read_address => mem_read_address_S,
+		data_out(15 downto 0) => mem_channel_S,
+		data_out(31 downto 16) => mem_energy_S,
+		data_out(39 downto 32) => mem_statusbyte_S,
+		data_out(CF_FRACTIONBIT+39 downto 40) => mem_timefraction_S,
+		data_out(63 downto CF_FRACTIONBIT+40) => mem_timestamp_S
+		);
+blockmem_datatin_S <= timestamp_S & timefraction_S & statusbyte_S & energy_S & channel_S; -- (24-CF_FRACTIONBIT)+CF_FRACTIONBIT+8+16+16 = 24+8+16+16
+
+data_in_read <= data_in_read_S;
+data_in_read_S <= '1' when 
+	((data_in_available='1') and (reset_S='0') and (data64_out_allowed='1') and (data64_out_write_retry_S='0')) and
+	(
+		(
+			(readinmode_S=waitforfirstpacket) and
+			(data_in_read_after1clk_S='0')
+		) or
+		(
+			(readinmode_S=waitfornextdata) and
+			((data_in_read_after1clk_S='0') or (superburstnumber=actual_superburstnumber_S)) and
+			((data_in_read_after1clk_S='0') or 
+				((superburstnumber=actual_superburstnumber_p1_S) and 
+					(mem_write_address_S(TRANSITIONBUFFERBITS-1 downto 1)=ones(TRANSITIONBUFFERBITS-1 downto 1)))) 
+		)
+	)
+	else '0';
+
+
+
+data64_out_write <= data64_out_write_final_S;
+data64_out_write_final_S <= '1' when ((data64_out_write_S='1') and (data64_out_allowed='1')) or 
+	((data64_out_write_retry_S='1') and (data64_out_allowed='1'))
+	else '0';
+	
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if (data64_out_write_S='1') and (data64_out_allowed='0') then
+			data64_out_write_retry_S <= '1';
+		elsif data64_out_allowed='1' then
+			data64_out_write_retry_S <= '0';
+		end if;
+	end if;
+end process;
+
+mem_read_address_S <= 
+	(others => '0') when ((readinmode_S/=cleanupmemorynext) and (readinmode_S/=writelastdatafrommemory)) else
+	mem_read_address_plus1_S when (data64_out_allowed='1') else
+	mem_read_address_now_S;
+			
+data64_out <= data64_out_S when data64frommem_S='0' else 
+	mem_timestamp_S & mem_timefraction_S & mem_statusbyte_S & mem_channel_S & mem_energy_S; -- = 13+11+8+16+16
+		
+superburst_new_error_S <= '1' when
+	((data_in_read_after1clk_S='1') and (superburstnumber<actual_superburstnumber_S)) or
+	((data_in_read_after1clk_S='1') and (superburstnumber>latestsuperburstnumber)) 
+--	((data_in_read_after1clk_S='1') and (superburstnumber+(MAXSUPERBURSTBEHIND(29 downto 0)&'0')<actual_superburstnumber_S))
+	else '0';
+
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if (data_in_read_after1clk_S='1') and (superburst_new_error_S='0') then
+			channel_S <= channel;
+			statusbyte_S <= statusbyte;
+			energy_S <= energy;
+			timefraction_S <= timefraction_corr_S;
+			timestamp_S <= timestamp_corr_S;
+			superburstnumber_S <= superburstnumber;
+		end if;
+	end if;
+end process;
+
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if reset_S='1' then
+			mem_write_address_S <= (others => '0');
+		else
+			if (readinmode_S=writelastdatafrommemory) or
+				(readinmode_S=waitforfirstpacket) then
+					mem_write_address_S <= (others => '0');
+			else
+				if mem_write_enable_S='1' then -- increase address automatically after write
+					mem_write_address_S <= mem_write_address_S+1;
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		if ((superburstnumber=zeros(30 downto 0)) or (actual_superburstnumber_S=zeros(30 downto 0))) and (ENABLESUPPRESSSTARTZEROS) then
+			suppress_startzeros_S <= '1';
+		else
+			suppress_startzeros_S <= '0';
+		end if;
+	end if;
+end process;
+					
+actual_superburstnumberplusMAX_S <= actual_superburstnumber_S+MAXSUPERBURSTBEHIND;
+actual_superburstnumber_p1_S <= actual_superburstnumber_S+1;
+actual_superburstnumber_p2_S <= actual_superburstnumber_S+2;
+mem_read_address_p1_S <= mem_read_address_S+1;
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		superburst_old_error_S <= '0';
+		data64_out_write_S <= '0';
+		mem_write_enable_S <= '0';
+		if reset_S='1' then
+			readinmode_S <= waitforfirstpacket;
+			data_in_read_after1clk_S <= '0';
+			data64_out_first <= '0';
+			data64_out_last <= '0';
+			data64buf_available_S <= '0';
+			data_in_memory_S <= '0';
+			actual_superburstnumber_S <= (others => '0');
+			data64frommem_S <= '0';
+			newdataavailable_S <= '0';
+			mem_read_address_plus1_S <= (others => '0');
+			mem_read_address_now_S <= (others => '0');
+		else
+			data_in_read_after1clk_S <= data_in_read_S;
+			case readinmode_S is
+				when waitforfirstpacket =>
+					data64frommem_S <= '0';
+					data_in_memory_S <= '0';
+					timeoutcounter_S <= (others => '0');
+					if data_in_read_after1clk_S='1' then
+						if (superburst_new_error_S='0') then
+							if (superburstnumber>actual_superburstnumber_p1_S) and (suppress_startzeros_S='0') then
+								readinmode_S <= writemissingpackets;
+							elsif (superburstnumber=actual_superburstnumber_p1_S) or (actual_superburstnumber_S=zeros(30 downto 0)) then
+								data64_out_S <= '0' & superburstnumber & x"00000000";
+								data64_out_write_S <= '1';
+								data64_out_first <= '1';
+								data64_out_last <= '0';
+								data64buf_S <= timestamp_corr_S & timefraction_corr_S & statusbyte & channel & energy; -- = 13+11+8+16+16
+								data64buf_available_S <= '1';
+								actual_superburstnumber_S <= superburstnumber;
+								readinmode_S <= waitfornextdata;
+							else
+								superburst_old_error_S <= '1';
+							end if;
+						end if;
+					else -- no hit, check superburstnumber
+						if (actual_superburstnumberplusMAX_S<latestsuperburstnumber) and
+								(suppress_startzeros_S='0') and
+								(data_in_available='0') and
+								(data_in_read_S='0') then --//necessary?
+							readinmode_S <= writesomemissingpackets;
+						end if;
+					end if;
+				when writesomemissingpackets => -- write all missing packets 
+					data64frommem_S <= '0';
+					if data64_out_allowed='1' then -- check if allowed
+						data64_out_S <= '0' & actual_superburstnumber_p1_S & x"00000000";
+						data64_out_write_S <= '1';
+						data64_out_first <= '1';
+						data64_out_last <= '1';
+						if (actual_superburstnumberplusMAX_S<latestsuperburstnumber) then
+							readinmode_S <= writesomemissingpackets;
+						else
+							readinmode_S <= waitforfirstpacket;
+						end if;
+						actual_superburstnumber_S <= actual_superburstnumber_p1_S;
+					end if;
+				when writemissingpackets => -- write all missing packets 
+					data64frommem_S <= '0';
+					if data64_out_allowed='1' then -- check if allowed
+						data64_out_S <= '0' & actual_superburstnumber_p1_S & x"00000000";
+						data64_out_write_S <= '1';
+						data64_out_first <= '1';
+						data64_out_last <= '1';
+						if (actual_superburstnumber_p2_S>=superburstnumber_S) then --//
+							readinmode_S <= writefirstpacket; -- write the first data of the new packet
+						end if;
+						actual_superburstnumber_S <= actual_superburstnumber_p1_S;
+					end if;
+				when writefirstpacket => -- write first data in packet
+					data64frommem_S <= '0';
+					if data64_out_allowed='1' then -- check if allowed
+						data64_out_S <= '0' & superburstnumber_S & x"00000000";
+						data64_out_write_S <= '1';
+						data64_out_first <= '1';
+						data64_out_last <= '0';
+						data64buf_S <= timestamp_S & timefraction_S & statusbyte_S & channel_S & energy_S; -- = 13+11+8+16+16
+						data64buf_available_S <= '1';
+						actual_superburstnumber_S <= superburstnumber_S;
+						readinmode_S <= waitfornextdata;				
+					end if;
+				when waitfornextdata =>
+					data64frommem_S <= '0';
+					if data_in_read_after1clk_S='1' then
+						if (superburst_new_error_S='0') then
+							if superburstnumber=actual_superburstnumber_S then
+								if data64buf_available_S='1' then
+									if data64_out_allowed='1' then -- check if allowed
+										data64_out_S <= data64buf_S;
+										data64_out_write_S <= '1';
+										data64_out_first <= '0';
+										data64_out_last <= '0';
+										data64buf_S <= timestamp_corr_S & timefraction_corr_S & statusbyte & channel & energy; -- = 13+11+8+16+16
+										data64buf_available_S <= '1';
+									else
+										readinmode_S <= waitforallowed;
+									end if;
+								else
+									data64buf_S <= timestamp_corr_S & timefraction_corr_S & statusbyte & channel & energy; -- = 13+11+8+16+16
+									data64buf_available_S <= '1';
+								end if;
+							elsif superburstnumber=actual_superburstnumber_p1_S then -- write im mem
+								data_in_memory_S <= '1';
+								mem_write_enable_S <= '1';
+								if mem_write_address_S(TRANSITIONBUFFERBITS-1 downto 1)=ones(TRANSITIONBUFFERBITS-1 downto 1) then -- cleanup all if memory full
+									newdataavailable_S <= '1'; 
+									if data64_out_allowed='1' then
+										data64_out_S <= data64buf_S;
+										data64_out_write_S <= '1';
+										data64_out_first <= '0';
+										data64_out_last <= '1';
+										data64buf_available_S <= '0';
+										readinmode_S <= cleanupmemoryfirst;
+									else
+										readinmode_S <= cleanupmemoryzero;
+									end if;
+								end if;
+							elsif superburstnumber>actual_superburstnumber_p1_S then -- new superburst: cleanup all
+								if data64buf_available_S='1' then
+									newdataavailable_S <= '1'; 
+									if data64_out_allowed='1' then
+										data64_out_S <= data64buf_S;
+										data64_out_write_S <= '1';
+										data64_out_first <= '0';
+										data64_out_last <= '1';
+										data64buf_available_S <= '0';
+										if data_in_memory_S='1' then
+											readinmode_S <= cleanupmemoryfirst;
+										else
+											readinmode_S <= waitforfirstpacket;
+										end if;
+									else
+										if data_in_memory_S='1' then
+											readinmode_S <= cleanupmemoryzero;
+										else
+											readinmode_S <= waitforcleanupallowed;
+										end if;
+									end if;
+								else
+									if data_in_memory_S='1' then
+										readinmode_S <= cleanupmemoryfirst;
+									else
+										readinmode_S <= waitforfirstpacket;
+									end if;
+								end if;
+							end if;
+						end if;
+					else -- not data_in_read_after1clk_S
+						if data64_out_allowed = '1' then
+							if timeoutcounter_S(timeoutcounter_S'left)='1' then
+								timeoutcounter_S <= (others => '0');
+								if data64buf_available_S='1' then
+									data64_out_S <= data64buf_S;
+									data64_out_write_S <= '1';
+									data64_out_first <= '0';
+									data64_out_last <= '1';
+									newdataavailable_S <= '0'; 
+									data64buf_available_S <= '0';
+								end if;
+								if data_in_memory_S='1' then
+									readinmode_S <= cleanupmemoryfirst;
+								else
+									readinmode_S <= waitforfirstpacket;
+								end if;
+							else						
+								timeoutcounter_S <= timeoutcounter_S+1;
+							end if;
+						end if;
+					end if;
+				when waitforallowed =>
+					data64frommem_S <= '0';
+					if data64_out_allowed='1' then -- check if allowed
+						data64_out_S <= data64buf_S;
+						data64_out_write_S <= '1';
+						data64_out_first <= '0';
+						data64_out_last <= '0';
+						data64buf_S <= timestamp_S & timefraction_S & statusbyte_S & channel_S & energy_S; -- = 13+11+8+16+16
+						data64buf_available_S <= '1';
+						readinmode_S <= waitfornextdata;
+					end if;
+				when waitforcleanupallowed =>
+					data64frommem_S <= '0';
+					if data64_out_allowed='1' then
+						data64_out_S <= data64buf_S;
+						data64_out_write_S <= '1';
+						data64_out_first <= '0';
+						data64_out_last <= '1';
+						data64buf_available_S <= '0';
+						readinmode_S <= waitforfirstpacket;
+					end if;
+				when cleanupmemoryzero =>
+					data64frommem_S <= '0';
+					if data64_out_allowed='1' then
+						data64_out_S <= data64buf_S;
+						data64_out_write_S <= '1';
+						data64_out_first <= '0';
+						data64_out_last <= '1';
+						data64buf_available_S <= '0';
+						readinmode_S <= cleanupmemoryfirst;
+					end if;
+				when cleanupmemoryfirst =>
+					data64frommem_S <= '0';
+					timeoutcounter_S <= (others => '0');
+					data_in_memory_S <= '0';
+					if data64_out_allowed = '1' then
+						data64_out_S <= '0' & actual_superburstnumber_p1_S & x"00000000";
+						data64_out_write_S <= '1';
+						data64_out_first <= '1';
+						data64_out_last <= '0';
+						actual_superburstnumber_S <= actual_superburstnumber_p1_S;
+						mem_read_address_now_S <= (others => '0');
+						mem_read_address_plus1_S <= (others => '0');
+						readinmode_S <= cleanupmemorynext;
+					end if;
+				when cleanupmemorynext =>
+					mem_read_address_now_S <= mem_read_address_S;
+					timeoutcounter_S <= (others => '0');
+					data_in_memory_S <= '0';
+					if data64_out_allowed = '1' then
+						if mem_read_address_p1_S=mem_write_address_S then
+							data64frommem_S <= '0';
+							readinmode_S <= writelastdatafrommemory;
+						else
+							data64frommem_S <= '1';
+							data64_out_write_S <= '1';
+							data64_out_first <= '0';
+							data64_out_last <= '0';
+							mem_read_address_plus1_S <= mem_read_address_p1_S;
+						end if;
+					end if;
+				when writelastdatafrommemory =>
+					if newdataavailable_S='1' then
+						if superburstnumber_S=actual_superburstnumber_p1_S then -- write new data in memory
+							data64buf_S <= mem_timestamp_S & mem_timefraction_S & mem_statusbyte_S & mem_channel_S & mem_energy_S; -- = 13+11+8+16+16
+							data64frommem_S <= '0';
+							data64buf_available_S <= '1';	
+							mem_write_enable_S <= '1';
+							data_in_memory_S <= '1';
+							newdataavailable_S <= '0';
+							readinmode_S <= waitfornextdata;
+						elsif superburstnumber_S=actual_superburstnumber_S then -- continue with current superburst
+							data64buf_S <= mem_timestamp_S & mem_timefraction_S & mem_statusbyte_S & mem_channel_S & mem_energy_S; -- = 13+11+8+16+16
+							data64frommem_S <= '0';
+							data64buf_available_S <= '1';	
+							mem_write_enable_S <= '0';
+							data_in_memory_S <= '0';
+							newdataavailable_S <= '0';
+							readinmode_S <= waitfornextdata;
+						else -- write last data in superburst packet
+							if data64_out_allowed = '1' then
+								data64frommem_S <= '1';
+								data64_out_write_S <= '1';
+								data64_out_first <= '0';
+								data64_out_last <= '1';
+								-- if (actual_superburstnumber_p2_S=superburstnumber_S) and (actual_superburstnumber_p2_S<=latestsuperburstnumber) then
+									-- readinmode_S <= writefirstpacket; -- write the first data of the new packet
+								-- else
+									-- readinmode_S <= waitforfirstpacket;
+								-- end if;
+								readinmode_S <= writemissingpackets;
+							end if;
+						end if;
+					else
+						data64buf_S <= mem_timestamp_S & mem_timefraction_S & mem_statusbyte_S & mem_channel_S & mem_energy_S; -- = 13+11+8+16+16
+						data64frommem_S <= '0';
+						data64buf_available_S <= '1';	
+						data_in_memory_S <= '0';
+						readinmode_S <= waitfornextdata;
+					end if;
+			end case;
+		end if;
+	end if;
+end process;	
+
+debug_readinmode_S <=
+	"0000" when readinmode_S=waitforfirstpacket else
+	"0001" when readinmode_S=writesomemissingpackets else
+	"0010" when readinmode_S=writemissingpackets else
+	"0011" when readinmode_S=writefirstpacket else
+	"0100" when readinmode_S=waitfornextdata else
+	"0101" when readinmode_S=waitforallowed else
+	"0110" when readinmode_S=waitforcleanupallowed else
+	"0111" when readinmode_S=cleanupmemoryzero else
+	"1000" when readinmode_S=cleanupmemoryfirst else
+	"1001" when readinmode_S=cleanupmemorynext else
+	"1010" when readinmode_S=writelastdatafrommemory else
+	"1111";
+
+	
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+			
+		if debug_readinmode_S/=debug_readinmodes_S(0) then
+			for i in 1 to 7 loop
+				debug_readinmodes_S(i) <= debug_readinmodes_S(i-1);
+			end loop;
+			debug_readinmodes_S(0) <= debug_readinmode_S;
+		end if;
+	end if;
+end process;
+			
+testword0(35 downto 0) <= (others => '0');
+
+end Behavioral;
+
diff --git a/data_concentrator/sources/DC_time_energy_LUTs.vhd b/data_concentrator/sources/DC_time_energy_LUTs.vhd
new file mode 100644
index 0000000..cb52193
--- /dev/null
+++ b/data_concentrator/sources/DC_time_energy_LUTs.vhd
@@ -0,0 +1,415 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   11-09-2014
+-- Module Name:   DC_time_energy_LUTs 
+-- Description:   Performs correction on time and energy of pulses
+-- Modifications:
+--   18-09-2014   different clock for loading LUTs
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- DC_time_energy_LUTs
+-- Performs correction on time and energy of pulses: 
+--    offset for time (timestamp+fraction) of each ADC-channel
+--    offset and gain (scaling) for energy of each ADC-channel
+--
+-- The hits are assigned to a superburst number, based on timestamp/timefraction.
+-- The SODA superburstnumbers and duration from a few superburst in the past are stored to 
+-- make this possible if the hits arrive late due to buffering.
+-- If the hit arrive too late then the hit is skipped. This is reported on the next hit and status bit.
+-- 
+-- The results are put in a packet of 36-bits wide data words:
+--         word0 : 0 & 0000 & timestamp(15..0) (time within superburst)
+--         word1 : 1 & 0 & superburstnumber(30..0)
+--         word2 : 2 & statusbyte & 00 & adcnumber
+--         word3 : 3 & timefraction & energy
+--
+--
+-- The timeshift Look Up Table has 31 bits data:
+--   bit 30.. 16 : correction for the integer part
+--   bit CF_FRACTIONBIT-1..0 : correction for the fraction part
+--
+-- The Energy correction Look Up Table has 31 bits data:
+--   bit 30..16 : offset correction (signed)
+--   bit 15..0 : gain correction
+--   equation:  energy = ((original_energy+offset) * gainfactor)>>scalingbits 
+--
+--
+-- Library:
+--     work.panda_package :  for type declarations and constants
+-- 
+-- Generics:
+--     NROFADCS : number of ADCs in the FEE: total high and low gain ADCs 
+--     ADCINDEXSHIFT : ADC channel numbers lowest bit indicates the high or low gain ADC, 0=high, 1=low
+--     CF_FRACTIONBIT : number of valid constant fraction bits
+--     ENERGYSCALINGBITS : number of scaling bits for energy adjustment: energy = (original_energy * gainfactor<<scalingbits)>>scalingbits
+-- 
+-- Inputs:
+--     clock : clock input : fiber receiver clock
+--     load_clock : clock for loading
+--     SODA_clock : clock SODA, used to update superburst
+--     reset : synchronous reset
+--     enable : enable datareading from receiver
+--     timeshiftLUT_write : write signal for Look Up Table time-correction for each adc-channel
+--     timeshiftLUT_loading : high : load LUT mode, low : normal correction mode
+--     timeshiftLUT_data : correction data to be written in the LUT
+--     energyLUT_write : write signal for Look Up Table energy adjustment for each adc-channel
+--     energytLUT_loading : high : load LUT mode, low : normal correction mode
+--     energyLUT_data : correction data to be written in the LUT: bit15..0=gainfactor(>>scalingbits), bit30..16=offset
+--     datain_write : write signal for the pulse data
+--     adcnumber : 16-bits identification number of the adc
+--     superburst : lowest 16 bits of the superburstnumber
+--     timestamp : 16 bits timestamp of the CF_signal before the zero-crossing
+--     timefraction : calculated fraction of the time-stamp using constant fraction method
+--     energy : energy, calculated maximum in waveform
+--     statusbyte : 8-bits status
+--     pulse_data_out_allowed : output data writing (4 words) allowed  : not fifo-almostfull of connected fifo
+--     superburst_number : most recent superburst-number
+--     superburst_update : new most recent superburst-number+timestamp
+-- 
+-- Outputs:
+--     datain_allowed : allowed to write pulse data members
+--     pulse_data_out : data with pulse results; 4 sequential 36-bits words with bits 35..32 as index
+--         word0 : 0 & 0000 & timestamp(15..0) (time within superburst)
+--         word1 : 1 & 0 & superburstnumber(30..0)
+--         word2 : 2 & statusbyte & 00 & adcnumber
+--         word3 : 3 & timefraction & energy
+--     pulse_data_write :  pulse data write signal
+--     slowcontrol_data : slow-control command : data 32-bits 
+--     slowcontrol_address : slow-control command : address 24-bits 
+--     slowcontrol_reply : indicates if the slow-control is a reply, or a independent message
+--     slowcontrol_write : write of slow-control data/address/reply
+--     wave_data_out : data with waveform: 36-bits words with bits 35..32 as index
+--        	bits(35..32)="0000" : bits(15..0)=timestamp within superburst of maximum value in waveform
+--        	bits(35..32)="0001" : bits(31)=0 bits(30..0)=SuperBurst number
+--        	bits(35..32)="0010" : 
+--              bits(31..24) = statusbyte (bit7=overflow) 
+--              bits(23..16) = 00
+--              bits(15..0) = adcnumber (channel identification)
+--        	bits(35..32)="0011" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+--        	bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+--        	bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+--        	bits(35..32)="1111" : error: buffer full, waveform not valid
+--     data_error : error
+--     pulse_data_skipped : data remove due to full connected fifo
+--
+-- Components:
+--     DC_timeshift_lookuptable : Look Up Table with time delay values for each ADC channel
+--     DC_energy_correction : Look Up Table with offset and gain for each ADC channel
+-- 
+----------------------------------------------------------------------------------
+
+entity DC_time_energy_LUTs is
+	generic (
+		NROFADCS                : natural := 32;
+		ADCINDEXSHIFT           : natural := 1;
+		CF_FRACTIONBIT          : natural := 11;
+		ENERGYSCALINGBITS       : natural := 13
+	);
+    Port ( 
+		clock                   : in  std_logic;
+		load_clock              : in std_logic;
+		SODA_clock              : in  std_logic;
+		reset                   : in  std_logic;
+		enable                  : in  std_logic;
+		timeshiftLUT_write      : in  std_logic;
+		timeshiftLUT_loading    : in  std_logic;
+		timeshiftLUT_data       : in  std_logic_vector (30 downto 0);
+		energyLUT_write         : in  std_logic;
+		energytLUT_loading      : in  std_logic;
+		energyLUT_data          : in  std_logic_vector (30 downto 0);
+		
+		datain_write            : in std_logic;
+		datain_allowed          : out std_logic;
+		adcnumber               : in std_logic_vector(15 downto 0); -- should be 1 clockcycle valid before datain_write
+		superburst              : in std_logic_vector(15 downto 0);
+		timestamp               : in std_logic_vector(15 downto 0);
+		timefraction            : in std_logic_vector(CF_FRACTIONBIT-1 downto 0);
+		energy                  : in std_logic_vector(15 downto 0);
+		statusbyte              : in std_logic_vector(7 downto 0);
+
+		pulse_data_out          : out std_logic_vector(35 downto 0);
+		pulse_data_write        : out std_logic;
+		pulse_data_out_allowed  : in  std_logic;
+		pulse_data_skipped      : out std_logic;
+		superburst_number       : in std_logic_vector(30 downto 0);
+		superburst_update       : in std_logic;
+		testword0               : out std_logic_vector (35 downto 0));
+end DC_time_energy_LUTs;
+
+architecture Behavioral of DC_time_energy_LUTs is
+
+component DC_timeshift_lookuptable is
+	generic (
+		lut_addrwidth : natural := twologarray(NROFADCS);
+		lut_datawidth  : natural := 31
+		);
+	port ( 
+		clock                   : in std_logic;
+		load_clock              : in std_logic;
+		loading                 : in std_logic;
+		lut_write               : in std_logic;
+		address                 : in std_logic_vector (lut_addrwidth-1 downto 0);
+		data_in                 : in std_logic_vector (lut_datawidth-1 downto 0);
+		data_out                : out std_logic_vector (lut_datawidth-1 downto 0));
+end component;
+
+component DC_energy_correction is
+	generic (
+		SCALINGBITS : natural := ENERGYSCALINGBITS;
+		LUT_ADDRWIDTH : natural := twologarray(NROFADCS);
+		LUT_DATAWIDTH  : natural := 31
+		);
+	port ( 
+		clock                   : in std_logic;
+		load_clock              : in std_logic;
+		loading                 : in std_logic;
+		lut_write               : in std_logic;
+		address                 : in std_logic_vector (LUT_ADDRWIDTH-1 downto 0);
+		data_in                 : in std_logic_vector (LUT_DATAWIDTH-1 downto 0);
+		energy_in               : in std_logic_vector (15 downto 0);
+		energy_out              : out std_logic_vector (15 downto 0));
+end component;
+
+--     PASTSUPERBURSTBITS : number of bits for data array remembering previous SUPERBURSTS, depends on data latency from FEE
+constant PASTSUPERBURSTBITS         : natural := 3;
+constant zeros                      : std_logic_vector(31 downto 0) := (others => '0');
+ 
+type superbursttime_type is array (0 to 2**PASTSUPERBURSTBITS-1) of std_logic_vector (15 downto 0);
+type superbursts_type is array (0 to 2**PASTSUPERBURSTBITS-1) of std_logic_vector (30 downto 0);
+
+signal datapacketcounter_S          : integer range 0 to 3 := 0; 
+signal timeshift_data_s             : std_logic_vector (30 downto 0);
+signal energy_corrected_S           : std_logic_vector (15 downto 0);
+
+signal pulse_valid_S                : std_logic := '0';
+signal pulse_data_skipped_S         : std_logic := '0';
+signal superburst_missed_S          : std_logic := '0';
+
+signal pulse_data_write_S           : std_logic := '0';
+signal pulse_data_out_S             : std_logic_vector (35 downto 0);
+signal pulse_data_out2_S            : std_logic_vector (35 downto 0);
+signal pulse_data_out3_S            : std_logic_vector (35 downto 0);
+signal pulse_data_out4_S            : std_logic_vector (35 downto 0);
+
+signal timestampcounter_S           : std_logic_vector (15 downto 0) := (others => '0');
+signal superburstnr_S               : std_logic_vector (30 downto 0) := (others => '0');
+signal superburst_timestamps_S      : superbursttime_type := (others => (others => '0'));
+signal superburst_numbers_S         : superbursts_type := (others => (others => '0'));
+
+
+begin
+
+datain_allowed <= '1' when (pulse_data_out_allowed='1') and ((datapacketcounter_S=0) or (datapacketcounter_S=3)) else '0';
+					
+pulse_data_skipped <= '1' when (pulse_data_skipped_S='1') and (enable='1') else '0';
+
+process(SODA_clock)
+begin
+	if rising_edge(SODA_clock) then
+		if superburst_update='1' then
+			superburst_timestamps_S(conv_integer(unsigned(superburst_number(PASTSUPERBURSTBITS-1 downto 0)))) <= timestampcounter_S;
+			superburst_numbers_S(conv_integer(unsigned(superburst_number(PASTSUPERBURSTBITS-1 downto 0)))) <= superburst_number;
+			timestampcounter_S <= x"0001"; --(others => '0');
+		else
+			timestampcounter_S <= timestampcounter_S+1;
+		end if;
+	end if;
+end process;
+
+	
+pulse_data_out <= pulse_data_out_S;
+pulse_data_write <= '1' when (pulse_data_write_S='1') and (pulse_data_out_allowed='1') and (enable='1') else '0';
+
+DC_timeshift_lookuptable1: DC_timeshift_lookuptable port map(
+		clock => clock,
+		load_clock => load_clock,
+		loading => timeshiftLUT_loading,
+		lut_write => timeshiftLUT_write,
+		address => adcnumber(twologarray(NROFADCS)-1 downto 0),
+		data_in => timeshiftLUT_data,
+		data_out => timeshift_data_S);
+
+DC_energy_correction1: DC_energy_correction port map(
+		clock => clock,
+		load_clock => load_clock,
+		loading => energytLUT_loading,
+		lut_write => energyLUT_write,
+		address => adcnumber(twologarray(NROFADCS)-1 downto 0),
+		data_in => energyLUT_data,
+		energy_in => energy,
+		energy_out => energy_corrected_S);
+
+datapackethandling: process(clock)
+variable precise_time_vector_V    : std_logic_vector(CF_FRACTIONBIT+15 downto 0);
+variable precise_time_V           : integer range -2**(CF_FRACTIONBIT+15) to 2**(CF_FRACTIONBIT+15)-1;
+variable timeshift_vector_V       : std_logic_vector(CF_FRACTIONBIT+15 downto 0);
+variable timeshift_V              : integer range -2**(CF_FRACTIONBIT+15) to 2**(CF_FRACTIONBIT+15)-1;
+variable precise_shifted_time_V   : std_logic_vector(CF_FRACTIONBIT+15 downto 0);
+variable precise_superburst_timevctr_V: std_logic_vector(CF_FRACTIONBIT+15 downto 0);
+variable precise_superburst_time_V: integer range -2**(CF_FRACTIONBIT+15) to 2**(CF_FRACTIONBIT+15)-1;
+variable precise_shifted_time_pr_V : std_logic_vector(CF_FRACTIONBIT+15 downto 0);
+variable superburstidx_V          : integer range 0 to 2**PASTSUPERBURSTBITS-1;
+variable superburstidx_pr_vector_V : std_logic_vector(PASTSUPERBURSTBITS-1 downto 0);
+variable superburstidx_pr_V       : integer range 0 to 2**PASTSUPERBURSTBITS-1;
+
+variable timestamp_V              : std_logic_vector(15 downto 0);
+variable timefraction_V           : std_logic_vector(15 downto 0);
+variable superburstnr_V           : std_logic_vector(30 downto 0);
+variable superburstnr_error_V     : boolean;
+
+variable superburstidx_nx_vector_V : std_logic_vector(PASTSUPERBURSTBITS-1 downto 0);
+variable superburstidx_nx_V       : integer range 0 to 2**PASTSUPERBURSTBITS-1;
+variable precise_superburst_timevctr_nx_V: std_logic_vector(CF_FRACTIONBIT+15 downto 0);
+variable precise_superburst_time_nx_V: integer range -2**(CF_FRACTIONBIT+15) to 2**(CF_FRACTIONBIT+15)-1;
+variable precise_shifted_time_nx_V : std_logic_vector(CF_FRACTIONBIT+15 downto 0);
+
+variable statusbyte_V              : std_logic_vector(7 downto 0);
+
+begin
+	if rising_edge(clock) then
+		if reset='1' then
+			pulse_data_write_S <= '0';
+			datapacketcounter_S <= 0;
+			pulse_data_skipped_S <= '0';
+			superburst_missed_S <= '0';
+		else
+			case datapacketcounter_S is
+				when 0 =>
+					if (pulse_data_write_S='1') and (pulse_data_out_allowed='0') then -- write unsuccessful
+						if pulse_valid_S='1' then
+							pulse_data_skipped_S <= '1';
+						end if;
+					else
+						if datain_write='1' then
+							if (pulse_data_out_allowed='1') then 
+								precise_time_vector_V := timestamp & timefraction;
+								precise_time_V := conv_integer(signed(precise_time_vector_V));
+								
+								timeshift_vector_V := '0' & timeshift_data_S(30 downto 16) & timeshift_data_S(CF_FRACTIONBIT-1 downto 0);
+								timeshift_V := conv_integer(signed(timeshift_vector_V));
+								
+								superburstidx_V := conv_integer(unsigned(superburst(PASTSUPERBURSTBITS-1 downto 0)));
+								superburstidx_pr_vector_V := superburst(PASTSUPERBURSTBITS-1 downto 0)-"01"; -- index for previous superburst
+								superburstidx_pr_V := conv_integer(unsigned(superburstidx_pr_vector_V)); -- index for previous superburst (integer)
+								superburstidx_nx_vector_V := superburst(PASTSUPERBURSTBITS-1 downto 0)+"01"; -- index for next superburst
+								superburstidx_nx_V := conv_integer(unsigned(superburstidx_nx_vector_V)); -- index for next superburst (integer)
+								
+								precise_shifted_time_V := conv_std_logic_vector(precise_time_V - timeshift_V,CF_FRACTIONBIT+16);
+								precise_superburst_timevctr_V := superburst_timestamps_S(superburstidx_pr_V) & zeros(CF_FRACTIONBIT-1 downto 0);
+								precise_superburst_time_V := conv_integer(unsigned(precise_superburst_timevctr_V));
+								precise_shifted_time_pr_V := conv_std_logic_vector( -- precision time in respect to previous superburst
+										precise_superburst_time_V + precise_time_V - timeshift_V,CF_FRACTIONBIT+16);
+
+								precise_superburst_timevctr_nx_V := superburst_timestamps_S(superburstidx_V) & zeros(CF_FRACTIONBIT-1 downto 0);
+								precise_superburst_time_nx_V := conv_integer(unsigned(precise_superburst_timevctr_nx_V));
+								precise_shifted_time_nx_V := conv_std_logic_vector( -- precision time in respect to next superburst
+										(precise_time_V - timeshift_V) - precise_superburst_time_nx_V,CF_FRACTIONBIT+16);
+										
+								superburstnr_error_V := false;
+								if precise_shifted_time_V(CF_FRACTIONBIT+15)='1' then -- negative: decrease superburst
+									timestamp_V := precise_shifted_time_pr_V(CF_FRACTIONBIT+15 downto CF_FRACTIONBIT);
+									superburstnr_V := superburst_numbers_S(superburstidx_pr_V);
+									if superburst_numbers_S(superburstidx_V)(15 downto 0) /= superburst then
+										superburstnr_error_V := true;
+									end if;
+--										if superburstnr_V(15 downto 0) /= superburst-x"0001") then
+--											superburstnr_error_V := true;
+--										end if;
+									timefraction_V(CF_FRACTIONBIT-1 downto 0) := precise_shifted_time_pr_V(CF_FRACTIONBIT-1 downto 0);
+								elsif (precise_shifted_time_V>=precise_superburst_time_nx_V) and -- check if hit-time is beyond superburst
+									(superburst_numbers_S(superburstidx_nx_V)(15 downto 0)=(superburst+x"0001")) then -- check if next superburst is already valid
+									timestamp_V := precise_shifted_time_nx_V(CF_FRACTIONBIT+15 downto CF_FRACTIONBIT);
+									superburstnr_V := superburst_numbers_S(superburstidx_nx_V);
+									if superburst_numbers_S(superburstidx_V)(15 downto 0) /= superburst then
+										superburstnr_error_V := true;
+									end if;
+									timefraction_V(CF_FRACTIONBIT-1 downto 0) := precise_shifted_time_nx_V(CF_FRACTIONBIT-1 downto 0);
+								else
+									timestamp_V := precise_shifted_time_V(CF_FRACTIONBIT+15 downto CF_FRACTIONBIT);										
+									superburstnr_V := superburst_numbers_S(superburstidx_V);
+									if superburstnr_V(15 downto 0) /= superburst then
+										superburstnr_error_V := true;
+									end if;
+									timefraction_V(CF_FRACTIONBIT-1 downto 0) := precise_shifted_time_V(CF_FRACTIONBIT-1 downto 0);
+								end if;
+								timefraction_V(15 downto CF_FRACTIONBIT) := (others => '0');
+								if superburstnr_error_V then
+									superburst_missed_S <= '1';
+									pulse_data_skipped_S <= '1';
+									pulse_data_write_S <= '0';
+									datapacketcounter_S <= 0;
+								else
+									statusbyte_V := statusbyte;
+									if superburst_missed_S='1' then
+										statusbyte_V := statusbyte or STATBYTE_DCSUPERBURSTMISSED;
+									end if;
+									if pulse_data_skipped_S='1' then
+										statusbyte_V := statusbyte or STATBYTE_DCPULSESKIPPED;
+									end if;
+									pulse_data_out_S <= "0000" & x"0000" & timestamp_V;
+									pulse_data_out2_S <= "0001" & '0' & superburstnr_V;
+									pulse_data_out3_S <= "0010" & statusbyte_V & x"00" & adcnumber;
+									pulse_data_out4_S <= "0011" & timefraction_V & energy_corrected_S;
+									pulse_data_write_S <= '1';
+									datapacketcounter_S <= 1;
+									pulse_data_skipped_S <= '0';
+									superburst_missed_S <= '0';
+								end if;
+							else 
+								pulse_data_skipped_S <= '1';
+								pulse_data_write_S <= '0';
+								datapacketcounter_S <= 0;
+							end if;
+						else
+							pulse_data_skipped_S <= '0';
+							pulse_data_write_S <= '0';
+							datapacketcounter_S <= 0;					
+						end if;
+					end if;
+				when 1 =>
+					pulse_data_write_S <= '1';
+					if pulse_data_out_allowed='1' then -- if write successful
+						pulse_data_out_S <= pulse_data_out2_S;
+						datapacketcounter_S <= 2;
+					end if;
+					if pulse_valid_S='1' then
+						pulse_data_skipped_S <= '1';
+					end if;
+				when 2 =>
+					pulse_data_write_S <= '1';
+					if pulse_data_out_allowed='1' then -- if write successful
+						pulse_data_out_S <= pulse_data_out3_S;
+						datapacketcounter_S <= 3;
+					end if;
+					if pulse_valid_S='1' then
+						pulse_data_skipped_S <= '1';
+					end if;
+				when 3 =>
+					pulse_data_write_S <= '1';
+					if pulse_data_out_allowed='1' then -- if write successful
+						pulse_data_out_S <= pulse_data_out4_S;
+						datapacketcounter_S <= 0;
+					end if;
+					if pulse_valid_S='1' then
+						pulse_data_skipped_S <= '1';
+					end if;
+				when others =>
+					pulse_data_write_S <= '0';
+					datapacketcounter_S <= 0;
+			end case;
+		end if;
+	end if;
+end process datapackethandling;
+
+testword0 <= (others => '0');
+
+end Behavioral;
+
diff --git a/data_concentrator/sources/DC_time_lookuptable.vhd b/data_concentrator/sources/DC_time_lookuptable.vhd
new file mode 100644
index 0000000..28f04cc
--- /dev/null
+++ b/data_concentrator/sources/DC_time_lookuptable.vhd
@@ -0,0 +1,102 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   08-05-2012
+-- Module Name:   DC_time_lookuptable
+-- Description:   Look Up Table with default value for timestamp fraction correction
+-- Modifications:
+--   11-09-2014   Name change from time_lookuptable to DC_time_lookuptable
+--   18-09-2014   different clock for loading
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use work.DC_LUT_package.all;
+
+------------------------------------------------------------------------------------------------------
+-- DC_time_lookuptable
+--     Look Up Table with default value for timestamp fraction.
+--     Look Up Table can be written with different values
+--
+-- Library
+--     work.FEE_LUT_package :  for default LUT value
+--
+-- generics
+--     LUT_ADDRWIDTH : number of bits for Look Up Table addresses : LUT depth
+--     LUT_DATAWIDTH : number of bits for Look Up Table data : LUT width
+--		
+-- inputs
+--     clock : clock
+--     load_clock : clock for loading
+--     loading : mode loading new LUT data, 0 means start next on position 0
+--     lut_write : write signal for writing new data to LUT, on each write the next index is selected
+--     address : index of LUT : gives corresponding value on data_out
+--     data_in : new data for LUT
+--		
+-- outputs
+--     data_out : resulting data
+--
+-- components
+--
+--
+------------------------------------------------------------------------------------------------------
+
+entity DC_time_lookuptable is
+	generic (
+		lut_addrwidth : natural := 11;
+		lut_datawidth  : natural := 11
+		);
+	port ( 
+		clock                   : in std_logic;
+		load_clock              : in std_logic;
+		loading                 : in std_logic;
+		lut_write               : in std_logic;
+		address                 : in std_logic_vector (lut_addrwidth-1 downto 0);
+		data_in                 : in std_logic_vector (lut_datawidth-1 downto 0);
+		data_out                : out std_logic_vector (lut_datawidth-1 downto 0));
+end DC_time_lookuptable;
+
+architecture behavioral of DC_time_lookuptable is
+
+signal lut_S                  : time_correction_lut_type := DEFAULTTIMECORRLUT;
+signal load_address_S         : std_logic_vector (lut_addrwidth-1 downto 0);
+signal loading0_S             : std_logic;
+signal loading1_S             : std_logic;
+
+begin
+
+
+process(load_clock)
+begin
+	if (rising_edge(load_clock)) then 
+		if (lut_write = '1') then
+			lut_S(conv_integer(load_address_S)) <= data_in;
+		end if;
+	end if;
+end process;
+
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		data_out <= lut_S(conv_integer(address));
+	end if;
+end process;
+
+
+process (load_clock)
+begin
+	if (rising_edge(load_clock)) then 
+		if (loading0_S='1') and (loading1_S='0') then
+			load_address_S <= (others => '0');
+		elsif (lut_write='1') and (loading1_S='1') then
+			load_address_S <= load_address_S+1;
+		end if;
+		loading1_S <= loading0_S;
+		loading0_S <= loading;
+	end if;
+end process;
+
+
+end architecture behavioral;
diff --git a/data_concentrator/sources/DC_timeshift_lookuptable.vhd b/data_concentrator/sources/DC_timeshift_lookuptable.vhd
new file mode 100644
index 0000000..4254769
--- /dev/null
+++ b/data_concentrator/sources/DC_timeshift_lookuptable.vhd
@@ -0,0 +1,101 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   24-01-2014
+-- Module Name:   DC_timeshift_lookuptable
+-- Description:   Look Up Table for timestamp correction
+-- Modifications:
+--   11-09-2014   Name change from timeshift_lookuptable to DC_timeshift_lookuptable
+--   18-09-2014   different clock for loading
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+------------------------------------------------------------------------------------------------------
+-- DC_timeshift_lookuptable
+--     Look Up Table for timestamp fraction.
+--     Writing of LUT : make 'loading' input 1, LUT address will start at 0
+--     On each write signal the next position in the LUT is written.
+--
+-- Library
+--     work.FEE_LUT_package :  for default LUT value
+--
+-- generics
+--     LUT_ADDRWIDTH : number of bits for Look Up Table addresses : LUT depth
+--     LUT_DATAWIDTH : number of bits for Look Up Table data : LUT width
+--		
+-- inputs
+--     clock : clock for reading
+--     load_clock : clock for loading
+--     loading : mode loading new LUT data, 0 means start next on position 0
+--     lut_write : write signal for writing new data to LUT, on each write the next index is selected
+--     address : index of LUT : gives corresponding value on data_out
+--     data_in : new data for LUT
+--		
+-- outputs
+--     data_out : resulting data
+--
+-- components
+--     blockmem_dualclk : memory with different clock for writing and reading
+--
+--
+------------------------------------------------------------------------------------------------------
+
+entity DC_timeshift_lookuptable is
+	generic (
+		LUT_ADDRWIDTH : natural := 5;
+		LUT_DATAWIDTH  : natural := 31
+		);
+	port ( 
+		clock                   : in std_logic;
+		load_clock              : in std_logic;
+		loading                 : in std_logic;
+		lut_write               : in std_logic;
+		address                 : in std_logic_vector (LUT_ADDRWIDTH-1 downto 0);
+		data_in                 : in std_logic_vector (LUT_DATAWIDTH-1 downto 0);
+		data_out                : out std_logic_vector (LUT_DATAWIDTH-1 downto 0));
+end DC_timeshift_lookuptable;
+
+architecture behavioral of DC_timeshift_lookuptable is
+
+type timeshift_correction_lut_type is array (0 to 2**LUT_ADDRWIDTH-1) 
+			of std_logic_vector (lut_datawidth-1 downto 0);
+signal lut_S                  : timeshift_correction_lut_type := (others => (others => '0'));
+signal load_address_S         : std_logic_vector (LUT_ADDRWIDTH-1 downto 0);
+signal loading_S              : std_logic;
+
+begin
+
+process(load_clock)
+begin
+	if (rising_edge(load_clock)) then 
+		if (lut_write = '1') then
+			lut_S(conv_integer(load_address_S)) <= data_in;
+		end if;
+	end if;
+end process;
+
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		data_out <= lut_S(conv_integer(address));
+	end if;
+end process;
+
+
+process (load_clock)
+begin
+	if (rising_edge(load_clock)) then 
+		if (loading_S='0') then
+			load_address_S <= (others => '0');
+		elsif (lut_write='1') then
+			load_address_S <= load_address_S+1;
+		end if;
+		loading_S <= loading;
+	end if;
+end process;
+
+end architecture behavioral;
diff --git a/data_concentrator/sources/DC_wave2packet64.vhd b/data_concentrator/sources/DC_wave2packet64.vhd
new file mode 100644
index 0000000..05fab9f
--- /dev/null
+++ b/data_concentrator/sources/DC_wave2packet64.vhd
@@ -0,0 +1,539 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   16-04-2012
+-- Module Name:   DC_wave2packet64
+-- Description:   Put waveform data in 64 bits packets
+-- Modifications:
+--   17-07-2014   buffer_full_S in clocked process
+--   07-10-2014   buffer_full_S removed from clocked process, depending on mem64_unequal_S
+--   26-11-2014   name changed from DC_wave2packet64 to DC_wave2packet64
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+USE work.panda_package.all;
+
+------------------------	----------------------------------------------------------
+-- DC_wave2packet64
+-- The waveform data is transferred to 64bits data.
+-- The incoming waveform data is 36 bits. The waveform length is variable.
+-- The output data is 64 bits. A has a small header and 8-bits CRC check.
+--
+-- Input data:
+--        	bits(35..32)="0000" : bits(31..0)=timestamp of maximum value in waveform
+--        	bits(35..32)="0001" : bits(31)=0 bits(30..0)=SuperBurst number
+--        	bits(35..32)="0010" : 
+--              bits(31..24) = statusbyte (bit6=overflow) 
+--              bits(23..16) = 00
+--              bits(15..0) = adcnumber (channel identification)
+--        	bits(35..32)="0011" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+--        	bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+--        	bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+--        	bits(35..32)="1111" : error: buffer full, waveform not valid
+--
+-- Output data 64 bits:
+--          U64_0 : 0xdd  status(7:0) ADCchannel(15:0) '0' SuperburstNr
+--          U64_1 : Time(47:0) NumberOfSamples(7:0) CRC(7:0)
+--          U64_2 : adcsample(15:0) next_adcsample(15:0) next_adcsample(15:0) next_adcsample(15:0)
+-- 
+--
+--
+--
+-- Library:
+--     work.panda_package: types and constants
+--
+-- Generics:
+--     BUFFER_BITS : number of bits for address for buffer-memory 
+--
+-- Inputs:
+--     clock : clock for input and output data
+--     reset : reset
+--     wave_in : waveform input data, 36-bits stream
+--        	bits(35..32)="0000" : bits(31..0)=timestamp of maximum value in waveform
+--        	bits(35..32)="0001" : bits(31)=0 bits(30..0)=SuperBurst number
+--        	bits(35..32)="0010" : 
+--              bits(31..24) = statusbyte (bit6=overflow) 
+--              bits(23..16) = 00
+--              bits(15..0) = adcnumber (channel identification)
+--        	bits(35..32)="0011" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+--        	bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+--        	bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+--        	bits(35..32)="1111" : error: buffer full, waveform not valid
+--     wave_in_available : waveform data is availabe
+--     wave64_out_allowed : allowed to write 64 output data (connecting fifo not full)
+-- 
+-- Outputs:
+--     wave_in_read : read signal for input waveform data
+--     wave64_out : 64 bits data
+--     wave64_out_write : write signal for 64 bits data
+--     wave64_out_first : first 64-bits word in packet
+--     wave64_out_last : last 64-bits word in packet
+--     error : error
+-- 
+-- Components:
+--     crc8_add_check64 : adds 8 bit crc to last 64-word in packet
+--     blockmem : memory block to buffer a packet before transmitting
+--
+----------------------------------------------------------------------------------
+
+entity DC_wave2packet64 is
+	generic (
+		BUFFER_BITS : natural := 9
+	);
+    Port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		wave_in                 : in std_logic_vector(35 downto 0);
+		wave_in_read            : out std_logic;
+		wave_in_available       : in std_logic;
+		wave64_out              : out std_logic_vector(63 downto 0);
+		wave64_out_write        : out std_logic;
+		wave64_out_first        : out std_logic;
+		wave64_out_last         : out std_logic;
+		wave64_out_allowed      : in std_logic;
+		error                   : out std_logic;
+		testword0               : out std_logic_vector(35 downto 0)
+	);    
+end DC_wave2packet64;
+
+
+architecture Behavioral of DC_wave2packet64 is
+
+component crc8_add_check64 is 
+   port(           
+		clock                   : in  std_logic; 
+		reset                   : in  std_logic; 
+		data_in                 : in  std_logic_vector(63 downto 0); 
+		data_in_valid           : in  std_logic; 
+		data_in_last            : in  std_logic; 
+		data_out                : out std_logic_vector(63 downto 0); 
+		data_out_valid          : out std_logic;
+		data_out_last           : out std_logic;
+		crc_error               : out std_logic
+	);
+end component; 
+
+component blockmem is
+	generic (
+		ADDRESS_BITS : natural := BUFFER_BITS;
+		DATA_BITS  : natural := 66
+		);
+	port (
+		clock                   : in  std_logic; 
+		write_enable            : in std_logic;
+		write_address           : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_in                 : in std_logic_vector(DATA_BITS-1 downto 0);
+		read_address            : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_out                : out std_logic_vector(DATA_BITS-1 downto 0)
+	);
+end component;
+
+
+signal wave_in_read_S             : std_logic := '0';
+signal wave_in_read_after1clk_S   : std_logic := '0';
+signal expect_S                   : std_logic_vector(3 downto 0) := "0000"; 
+
+signal crc_data_in_S              : std_logic_vector(63 downto 0); 
+signal crc_data_in_valid_S        : std_logic := '0'; 
+signal crc_data_in_last_S         : std_logic := '0'; 
+signal crc_data_out_S             : std_logic_vector(63 downto 0); 
+signal crc_data_out_valid_S       : std_logic := '0';
+signal crc_data_out_first_S       : std_logic := '0';
+signal crc_data_out_last_S        : std_logic := '0';
+signal crc_data_out_ready_S       : std_logic := '0';
+signal crc_reset_s                : std_logic := '0';
+
+signal mem_write_enable_S         : std_logic;
+signal mem_write_address_S        : std_logic_vector(BUFFER_BITS-1 downto 0);
+signal mem_data_in_S              : std_logic_vector(65 downto 0);
+signal mem_read_address_S         : std_logic_vector(BUFFER_BITS-1 downto 0);
+signal mem_data_out_S             : std_logic_vector(65 downto 0);
+signal memdata_in_first_S         : std_logic := '0';
+signal memdata_in_last_S          : std_logic := '0';
+
+signal mem64_writeaddress_S       : std_logic_vector(BUFFER_BITS-1 downto 0) := (others => '0');
+signal mem64_writeaddress0_S      : std_logic_vector(BUFFER_BITS-1 downto 0) := (others => '0');
+signal mem64_writeaddresslast_S   : std_logic_vector(BUFFER_BITS-1 downto 0) := (others => '1');
+signal mem64_readaddress_S        : std_logic_vector(BUFFER_BITS-1 downto 0) := (others => '0');
+signal mem64_readaddressprev_S    : std_logic_vector(BUFFER_BITS-1 downto 0) := (others => '0');
+signal mem64_writeaddress_next_S  : std_logic_vector(BUFFER_BITS-1 downto 0) := (others => '0');
+signal mem64_unequal_S            : std_logic := '0';
+signal mem64_unequal_prev_S       : std_logic := '0';
+
+
+signal buffer_full_S              : std_logic := '0';
+
+signal wave64_out_write0_S        : std_logic := '0';
+signal wave64_out_write_S         : std_logic := '0';
+signal wave64_out_first_S         : std_logic := '0';
+signal wave64_out_last_S          : std_logic := '0';
+
+signal write_adress1_S            : std_logic := '0';
+signal samplephase_S              : std_logic := '0';
+signal wavesize_S                 : integer range 0 to 255;
+signal crc_data_in_high_S         : std_logic_vector(31 downto 0);
+signal timestamp_S                : std_logic_vector(15 downto 0);
+signal superburstnr_S             : std_logic_vector(30 downto 0);
+signal statusbyte_S               : std_logic_vector(7 downto 0);
+signal adcnumber_S                : std_logic_vector(15 downto 0);
+signal error_S                    : std_logic := '0';
+
+
+begin
+
+error <= error_S;
+wave_in_read <= wave_in_read_S;
+
+wave_in_read_S <= '1' when 
+	(reset = '0') and (buffer_full_S='0') and (wave_in_available='1') 
+and (wave64_out_allowed='1')
+	else '0';
+	
+-- process(clock)
+-- begin
+	-- if (rising_edge(clock)) then 
+		-- if ((write_adress1_S='0') and
+				-- ((mem64_writeaddress_S=mem_read_address_S) or
+				-- (mem64_writeaddress_S+1=mem_read_address_S) or
+				-- (mem64_writeaddress_S+2=mem_read_address_S) or
+				-- (mem64_writeaddress_S+3=mem_read_address_S))) or
+			-- ((write_adress1_S='1') and
+				-- ((mem64_writeaddress_next_S=mem_read_address_S) or
+				-- (mem64_writeaddress_next_S+1=mem_read_address_S) or
+				-- (mem64_writeaddress_next_S+2=mem_read_address_S) or
+				-- (mem64_writeaddress_next_S+3=mem_read_address_S))) then
+			-- buffer_full_S <= '1';
+		-- else
+			-- buffer_full_S <= '0';
+		-- end if;
+	-- end if;
+-- end process;
+
+
+buffer_full_S <= '1'
+		when (mem64_unequal_S='1') and 
+			(((write_adress1_S='0') and
+				((mem64_writeaddress_S=mem_read_address_S) or
+				(mem64_writeaddress_S+1=mem_read_address_S) or
+				(mem64_writeaddress_S+2=mem_read_address_S) or
+				(mem64_writeaddress_S+3=mem_read_address_S))) or
+			((write_adress1_S='1') and
+				((mem64_writeaddress_next_S=mem_read_address_S) or
+				(mem64_writeaddress_next_S+1=mem_read_address_S) or
+				(mem64_writeaddress_next_S+2=mem_read_address_S) or
+				(mem64_writeaddress_next_S+3=mem_read_address_S))))
+		else '0';
+
+
+crc8_add_check64_comp: crc8_add_check64 port map(
+		clock => clock,
+		reset => crc_reset_S,
+		data_in => crc_data_in_S, 
+		data_in_valid => crc_data_in_valid_S,
+		data_in_last => crc_data_in_last_S,
+		data_out => crc_data_out_S, 
+		data_out_valid => crc_data_out_valid_S,
+		data_out_last => crc_data_out_last_S,
+		crc_error => open);
+		
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if reset='1' then
+			crc_data_out_ready_S <= '1';
+		else
+			if (crc_data_out_valid_S='1') and (crc_data_out_last_S='1') then
+				crc_data_out_ready_S <= '1';
+			elsif (crc_data_out_valid_S='1') then
+				crc_data_out_ready_S <= '0';
+			end if;	
+		end if;
+	end if;
+end process;
+crc_data_out_first_S <= '1' when (crc_data_out_valid_S='1') and (crc_data_out_ready_S='1') else '0';
+
+blockmem1: blockmem port map(
+		clock => clock,
+		write_enable => mem_write_enable_S,
+		write_address => mem_write_address_S,
+		data_in => mem_data_in_S,
+		read_address => mem_read_address_S,
+		data_out => mem_data_out_S);
+mem_data_in_S(63 downto 0) <= crc_data_out_S;
+mem_write_enable_S <= crc_data_out_valid_S;
+
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		mem_write_address_S <= mem64_writeaddress_S;
+		mem_data_in_S(64) <= memdata_in_first_S;
+		mem_data_in_S(65) <= memdata_in_last_S;
+	end if;
+end process;
+		
+
+writeprocess: process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if (reset = '1') then 
+			crc_data_in_valid_S <= '0';
+			crc_data_in_last_S <= '0';
+			crc_reset_S <= '1';
+			wave_in_read_after1clk_S <= '0';
+			mem64_writeaddress_next_S <= (others => '0');
+			mem64_writeaddress0_S <= (others => '0');
+			mem64_writeaddress_S <= (others => '0');
+			mem64_writeaddresslast_S <= (others => '1');
+			memdata_in_first_S <= '0';
+			memdata_in_last_S <= '0';
+			write_adress1_S <= '0';
+			wavesize_S <= 0;
+			samplephase_S <= '0';
+			expect_S <= "0000";
+		else
+			if wave_in_read_after1clk_S='1' then
+				case expect_S is
+					when "0000"  =>
+						if write_adress1_S='1' then
+							crc_data_in_S <= x"00000000" & timestamp_S & conv_std_logic_vector(wavesize_S,8) & x"00"; --48+8+8
+							mem64_writeaddress_S <= mem64_writeaddress0_S+1;
+							mem64_writeaddresslast_S <= mem64_writeaddress_next_S-1;
+							crc_data_in_valid_S <= '1';
+							crc_data_in_last_S <= '1';
+							write_adress1_S <= '0';
+						else
+							crc_data_in_valid_S <= '0';
+							crc_data_in_last_S <= '0';
+							crc_reset_S <= '1';
+						end if;
+						if wave_in(35 downto 32)=expect_S then
+							error_S <= '0';
+							timestamp_S <= wave_in(15 downto 0);
+							memdata_in_last_S <= '0';
+							memdata_in_first_S <= '0';
+							wavesize_S <= 0;
+							mem64_writeaddress0_S <= mem64_writeaddress_next_S;
+							expect_S <= "0001";
+						else -- error
+							error_S <= '1';
+						end if;
+						write_adress1_S <= '0';
+					
+					when "0001" => 
+						if wave_in(35 downto 32)=expect_S then
+							superburstnr_S <= wave_in(30 downto 0);
+							crc_reset_S <= '0';
+							expect_S <= "0010";
+						else
+							crc_reset_S <= '1';
+							error_S <= '1';
+							expect_S <= "0000";
+						end if;
+						memdata_in_first_S <= '0';
+						memdata_in_last_S <= '0';
+						crc_data_in_valid_S <= '0';
+						crc_data_in_last_S <= '0';
+						wavesize_S <= 0;
+						write_adress1_S <= '0';
+					when "0010" => 
+						if wave_in(35 downto 32)=expect_S then
+							statusbyte_S <= wave_in(31 downto 24);
+							adcnumber_S <= wave_in(15 downto 0);
+							crc_data_in_S <= x"dd" & wave_in(31 downto 24) & wave_in(15 downto 0) & '0' & superburstnr_S; --8+8+16+32
+							crc_data_in_valid_S <= '1';
+							memdata_in_first_S <= '1';
+							memdata_in_last_S <= '0';
+							mem64_writeaddress_S <= mem64_writeaddress0_S;
+							crc_reset_S <= '0';
+							expect_S <= "0011";
+						else
+							crc_reset_S <= '1';
+							error_S <= '1';
+							expect_S <= "0000";
+						end if;
+						wavesize_S <= 0;
+						samplephase_S <= '0';
+						write_adress1_S <= '0';
+					when "0011" => 
+						if wave_in(35 downto 32)="0011" then
+							crc_data_in_last_S <= '0';
+							memdata_in_first_S <= '0';
+							memdata_in_last_S <= '0';
+							if samplephase_S='0' then
+								crc_data_in_high_S <= wave_in(31 downto 16) & wave_in(15 downto 0);
+								crc_data_in_valid_S <= '0';
+								if wavesize_S=0 then
+									mem64_writeaddress_S <= mem64_writeaddress0_S+1;
+								end if;
+								samplephase_S <= '1';
+								wavesize_S <= wavesize_S+2;
+							else
+								crc_data_in_S <= crc_data_in_high_S & wave_in(31 downto 16) & wave_in(15 downto 0); --32+16+16
+								crc_data_in_valid_S <= '1';
+								mem64_writeaddress_S <= mem64_writeaddress_S+1;
+								wavesize_S <= wavesize_S+2;
+								samplephase_S <= '0';
+							end if;
+							write_adress1_S <= '0';
+							crc_reset_S <= '0';
+							expect_S <= "0011";
+						elsif wave_in(35 downto 32)="0100" then
+							crc_data_in_last_S <= '0';
+							memdata_in_first_S <= '0';
+							memdata_in_last_S <= '1';
+							if samplephase_S='0' then
+								crc_data_in_S <= wave_in(31 downto 16) & x"000000000000";
+								crc_data_in_valid_S <= '1';
+								mem64_writeaddress_S <= mem64_writeaddress_S+1;
+								mem64_writeaddress_next_S <= mem64_writeaddress_S+2;
+								write_adress1_S <= '1';
+								wavesize_S <= wavesize_S+1;
+							else
+								crc_data_in_S <= crc_data_in_high_S & wave_in(31 downto 16) & x"0000";
+								crc_data_in_valid_S <= '1';
+								mem64_writeaddress_S <= mem64_writeaddress_S+1;
+								mem64_writeaddress_next_S <= mem64_writeaddress_S+2;
+								write_adress1_S <= '1';
+								wavesize_S <= wavesize_S+1;
+							end if;
+							crc_reset_S <= '0';
+							expect_S <= "0000";
+						elsif wave_in(35 downto 32)="0101" then
+							crc_data_in_last_S <= '0';
+							memdata_in_first_S <= '0';
+							memdata_in_last_S <= '1';
+							if samplephase_S='0' then
+								crc_data_in_S <= wave_in(31 downto 16) & wave_in(15 downto 0) & x"00000000";
+								crc_data_in_valid_S <= '1';
+								mem64_writeaddress_S <= mem64_writeaddress_S+1;
+								mem64_writeaddress_next_S <= mem64_writeaddress_S+2;
+								write_adress1_S <= '1';
+								wavesize_S <= wavesize_S+2;
+							else
+								crc_data_in_S <= crc_data_in_high_S & wave_in(31 downto 16) & wave_in(15 downto 0);
+								crc_data_in_valid_S <= '1';
+								mem64_writeaddress_S <= mem64_writeaddress_S+1;
+								mem64_writeaddress_next_S <= mem64_writeaddress_S+2;
+								write_adress1_S <= '1';
+								wavesize_S <= wavesize_S+2;
+							end if;
+							crc_reset_S <= '0';
+							expect_S <= "0000";
+						elsif wave_in(35 downto 32)="1111" then
+							crc_reset_S <= '1';
+							crc_data_in_last_S <= '0';
+							crc_data_in_valid_S <= '0';
+							memdata_in_first_S <= '0';
+							expect_S <= "0000";
+						else -- error
+							error_S <= '1';
+							crc_reset_S <= '1';
+							crc_data_in_last_S <= '0';
+							crc_data_in_valid_S <= '0';
+							memdata_in_first_S <= '0';
+							expect_S <= "0000";
+						end if;
+					when others => 
+						error_S <= '1';
+						crc_reset_S <= '1';
+						crc_data_in_last_S <= '0';
+						crc_data_in_valid_S <= '0';
+						memdata_in_first_S <= '0';
+						expect_S <= "0000";
+				end case;
+			else
+				if write_adress1_S='1' then
+					crc_data_in_S <= x"00000000" & timestamp_S & conv_std_logic_vector(wavesize_S,8) & x"00"; --48+8+8
+					mem64_writeaddress_S <= mem64_writeaddress0_S+1;
+					mem64_writeaddresslast_S <= mem64_writeaddress_next_S-1;
+					memdata_in_first_S <= '0';
+					memdata_in_last_S <= '0';
+					crc_data_in_valid_S <= '1';
+					crc_data_in_last_S <= '1';
+				else
+					memdata_in_first_S <= '0';
+					memdata_in_last_S <= '0';
+					crc_data_in_valid_S <= '0';
+					crc_data_in_last_S <= '0';
+				end if;
+				write_adress1_S <= '0';
+			end if;
+			wave_in_read_after1clk_S <= wave_in_read_S;
+		end if;
+	end if;
+end process;
+
+
+wave64_out <= mem_data_out_S(63 downto 0);  
+wave64_out_first_S <= mem_data_out_S(64);
+wave64_out_first <= wave64_out_first_S;
+wave64_out_last_S <= mem_data_out_S(65);
+wave64_out_last <= wave64_out_last_S;
+
+
+wave64_out_write_S <= '1' when (wave64_out_write0_S='1') and (wave64_out_allowed='1') else '0'; 
+wave64_out_write <= wave64_out_write_S;
+mem_read_address_S <= mem64_readaddressprev_S when (wave64_out_write_S='0') and (wave64_out_write0_S='1') else mem64_readaddress_S;
+mem64_unequal_S <= '1' when (mem64_readaddress_S/=mem64_writeaddresslast_S) else '0';
+readprocess: process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if (reset = '1') then 
+			mem64_readaddress_S <= (others => '1');
+			mem64_readaddressprev_S <= (others => '1');
+			mem64_unequal_prev_S <= '0';
+		else
+			if (wave64_out_write0_S='1') and (wave64_out_write_S='0') then -- unsucessfull write
+				wave64_out_write0_S <= '1';
+				mem64_unequal_prev_S <= '0';
+				mem64_readaddress_S <= mem64_readaddressprev_S; -- keep same address
+			else
+				mem64_readaddressprev_S <= mem64_readaddress_S;
+				if (wave64_out_allowed='1') then
+					if (mem64_unequal_S='1') then 
+						mem64_readaddress_S <= mem64_readaddress_S+1;
+						mem64_unequal_prev_S <= '1';
+					else
+						mem64_unequal_prev_S <= '0';
+					end if;
+					if mem64_unequal_prev_S='1' then
+						wave64_out_write0_S <= '1';
+					else
+						wave64_out_write0_S <= '0';
+					end if;
+				else
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+
+testword0(7 downto 0) <= mem_data_out_S(63 downto 56);
+testword0(15 downto 8) <= mem_read_address_S(7 downto 0);
+testword0(23 downto 16) <= mem_write_address_S(7 downto 0);
+
+testword0(24) <= wave64_out_write_S;
+testword0(25) <= wave64_out_write0_S;
+testword0(26) <= wave64_out_first_S;
+testword0(27) <= wave64_out_last_S;
+testword0(28) <= wave64_out_allowed;
+testword0(29) <= wave_in_read_S;
+testword0(30) <= wave_in_available;
+testword0(31) <= wave_in_read_after1clk_S;
+testword0(32) <= crc_data_in_valid_S;
+testword0(33) <= crc_data_in_last_S;
+
+testword0(34) <= mem_write_enable_S;
+testword0(35) <= buffer_full_S;
+
+
+
+
+
+end Behavioral;
+
diff --git a/data_concentrator/sources/DC_wavemux.vhd b/data_concentrator/sources/DC_wavemux.vhd
new file mode 100644
index 0000000..2d44228
--- /dev/null
+++ b/data_concentrator/sources/DC_wavemux.vhd
@@ -0,0 +1,272 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   12-03-2012
+-- Module Name:   DC_wavemux
+-- Description:   Multiplexer for pileup waveform data, non sorting
+-- Modifications:
+--   26-11-2014   name changed from MUX_wavemux to DC_wavemux
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- DC_wavemux
+-- Multiplexes multiple input data with waveforms to one stream.
+-- The data width is 36-bits, 32 bits valid data and the highest bits for 
+-- word identification : first and last word in waveform packets.
+-- The data is not sorted; each time the next data input is chosen
+-- if data is available.
+-- There are fifo's for each input and one for the output.
+-- 
+--
+--
+--
+-- Library:
+--     work.panda_package:
+--        function calc_next_channel : calculate the next channel that has data available
+--
+-- Generics:
+--     NROFMUXINPUTS : number of input-channels
+--
+-- Inputs:
+--     inputclock : clock for input data (write side incomming fifo)
+--     MUXclock : clock for multiplexer part, between the fifos
+--     outputclock : clock for output data (read side outgoing fifo)
+--     reset : reset, must be long enough for all clocks
+--     data_in : input data :
+--        	bits(35..32)="0000" : bits(31..0)=timestamp of maximum value in waveform
+--        	bits(35..32)="0001" : bits(31)=0 bits(30..0)=SuperBurst number
+--        	bits(35..32)="0010" : 
+--              bits(31..24) = statusbyte (bit6=overflow) 
+--              bits(23..16) = 00
+--              bits(15..0) = adcnumber (channel identification)
+--        	bits(35..32)="0011" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+--        	bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+--        	bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+--        	bits(35..32)="1111" : error: buffer full, waveform not valid
+--     data_in_write : write signal for data_in (write into fifo)
+--     data_out_read : read signal for outgoing data (read from fifo)
+-- 
+-- Outputs:
+--     data_in_wave_allowed : writing of a full waveform (max 254 samples) to input allowed
+--     data_out : output data
+--        	bits(35..32)="0000" : bits(31..0)=timestamp of maximum value in waveform
+--        	bits(35..32)="0001" : bits(31)=0 bits(30..0)=SuperBurst number
+--        	bits(35..32)="0010" : 
+--              bits(31..24) = statusbyte (bit6=overflow) 
+--              bits(23..16) = 00
+--              bits(15..0) = adcnumber (channel identification)
+--        	bits(35..32)="0011" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+--        	bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+--        	bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+--        	bits(35..32)="1111" : error: buffer full, waveform not valid
+--     data_out_available : data_out available (output fifo not empty)
+--     infifo_fullness : array with number of words in input fifo's
+--     outfifo_fullness : number of words in output fifo
+--     error : data error
+-- 
+-- Components:
+--     async_fifo_nn_FWFT_512x36 : asynchronous fifo with number of words and First Word Fall Through
+--     async_fifo_nn_4096x36 : asynchronous fifo with number of words available in fifo
+--
+--
+----------------------------------------------------------------------------------
+
+entity DC_wavemux is
+	generic(
+		NROFMUXINPUTS           : natural := 4
+	);
+    Port ( 
+		inputclock              : in std_logic;
+		MUXclock                : in std_logic; 
+		outputclock             : in std_logic; 
+		reset                   : in std_logic;
+		data_in                 : in array_fiber36bits_type;
+		data_in_write           : in std_logic_vector(0 to NROFMUXINPUTS-1);
+		data_in_wave_allowed    : out std_logic_vector(0 to NROFMUXINPUTS-1);
+		data_out                : out std_logic_vector(35 downto 0);
+		data_out_read           : in std_logic;
+		data_out_available      : out std_logic;
+		infifo_fullness         : out array_fiber16bits_type;
+		outfifo_fullness        : out std_logic_vector(15 downto 0);
+		testword0               : out std_logic_vector(35 downto 0);
+		testword1               : out std_logic_vector(35 downto 0);
+		error                   : out std_logic);
+end DC_wavemux;
+
+
+architecture Behavioral of DC_wavemux is
+
+component async_fifo_nn_thfull_FWFT_512x36
+	port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(35 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(35 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic;
+		rd_data_count           : out std_logic_vector(8 downto 0);
+		prog_full               : out std_logic);
+end component;
+
+--component async_fifo_nn_512x36
+component async_fifo_nn_4096x36
+	port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(35 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(35 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic;
+		rd_data_count           : out std_logic_vector(11 downto 0));
+end component;
+
+
+component async_fifo_nn_512x36to18
+	port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(35 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(17 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic;
+		wr_data_count           : out std_logic_vector(8 downto 0));
+end component;
+
+signal reset_MUXclock_S       : std_logic;
+
+signal adcreading_S           : integer range 0 to NROFMUXINPUTS-1 := 0;
+
+signal error_S                : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+
+
+-- signals for fifo from adc-fe to adc-mux
+signal dfifo_wr_S             : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_rd_S             : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_out_S            : array_fiber36bits_type;
+signal dfifo_full_S           : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_prog_full_S      : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_empty_S          : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+
+-- signals for fifo from adc-mux to packet-composer
+signal tfifo_in_S             : std_logic_vector (35 downto 0);
+signal tfifo_wr_S             : std_logic := '0';
+signal tfifo_rd_S             : std_logic := '0';
+signal tfifo_full_S           : std_logic := '0';
+signal tfifo_empty_S          : std_logic := '0';
+
+signal waitfordata_S          : std_logic := '1';
+signal timeoutcounter_S       : std_logic_vector(15 downto 0) := (others => '0');
+
+constant zeros                : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+begin
+
+error <= '1' when (error_S(0 to NROFMUXINPUTS-1)/=zeros(0 to NROFMUXINPUTS-1)) else '0';
+
+inputfifos: for index in 0 to NROFMUXINPUTS-1 generate
+
+dfifo: async_fifo_nn_thfull_FWFT_512x36 port map(
+		rst => reset,
+		wr_clk => inputclock,
+		rd_clk => MUXclock,
+		din => data_in(index),
+		wr_en => dfifo_wr_S(index),
+		rd_en => dfifo_rd_S(index),
+		dout => dfifo_out_S(index),
+		full => dfifo_full_S(index),
+		empty => dfifo_empty_S(index),
+		rd_data_count => infifo_fullness(index)(8 downto 0),
+		prog_full => dfifo_prog_full_S(index));
+data_in_wave_allowed(index) <= '1' when dfifo_prog_full_S(index)='0' else '0';
+infifo_fullness(index)(15 downto 9) <= (others => '0');
+dfifo_wr_S(index) <= '1' when (dfifo_full_S(index)='0') and (data_in_write(index)='1') else '0';
+error_S(index) <= '1' when (dfifo_full_S(index)='1') and (data_in_write(index)='1') else '0';
+
+dfifo_rd_S(index) <= '1' when 
+		(tfifo_full_S='0')  
+		and (index=adcreading_S)
+		and (dfifo_empty_S(index)='0')
+		else '0';
+			
+end generate;
+
+
+process(MUXclock)
+constant ones : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '1');
+begin
+	if (rising_edge(MUXclock)) then 
+		if (reset_MUXclock_S = '1') then 
+			adcreading_S <= 0;
+			waitfordata_S <= '0';
+		else
+			if ((dfifo_out_S(adcreading_S)(35 downto 33)="010") 
+						or (dfifo_out_S(adcreading_S)(35 downto 32)="1111")) -- error
+				and dfifo_rd_S(adcreading_S)='1' then ----
+				waitfordata_S <= '1';
+				timeoutcounter_S <= (others => '0');
+				adcreading_S <= calc_next_channel(adcreading_S,dfifo_empty_S);
+			else
+				if waitfordata_S='1' then
+					if (dfifo_empty_S /= ones) then -- data available
+						if dfifo_rd_S(adcreading_S)='0' then
+							adcreading_S <= calc_next_channel(adcreading_S,dfifo_empty_S);
+						end if;
+						waitfordata_S <= '0';
+						timeoutcounter_S <= (others => '0');
+					end if;
+				else
+					if timeoutcounter_S(timeoutcounter_S'length-1)='1' then
+						if (dfifo_empty_S /= ones) then -- data available
+							if dfifo_rd_S(adcreading_S)='0' then
+								adcreading_S <= calc_next_channel(adcreading_S,dfifo_empty_S);
+							end if;
+							timeoutcounter_S <= (others => '0');
+						end if;
+					else
+						timeoutcounter_S <= timeoutcounter_S+1;
+					end if;
+				end if;
+			end if;
+		end if;
+		reset_MUXclock_S <= reset;
+	end if;
+end process;
+
+
+tfifo_wr_S <= '1' when (tfifo_full_S='0') and (dfifo_empty_S(adcreading_S)='0') else '0';
+tfifo_in_S <= dfifo_out_S(adcreading_S);
+tfifo: async_fifo_nn_4096x36 port map(
+		rst => reset,
+		wr_clk => MUXclock,
+		rd_clk => outputclock,
+		din => tfifo_in_S,
+		wr_en => tfifo_wr_S,
+		rd_en => tfifo_rd_S,
+		dout => data_out,
+		full => tfifo_full_S,
+		empty => tfifo_empty_S,
+		rd_data_count => outfifo_fullness(11 downto 0));
+outfifo_fullness(15 downto 12) <= (others => '0');
+
+tfifo_rd_S <= '1' when (data_out_read='1') and (tfifo_empty_S='0') else '0';
+data_out_available <= '1' when tfifo_empty_S='0' else '0';
+		
+testword0(35 downto 0) <= (others => '0');
+
+		
+end Behavioral;
+
diff --git a/data_concentrator/sources/Panda_package.vhd b/data_concentrator/sources/Panda_package.vhd
new file mode 100644
index 0000000..e3a552d
--- /dev/null
+++ b/data_concentrator/sources/Panda_package.vhd
@@ -0,0 +1,424 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date:   04-03-2011
+-- Module Name:   panda_package
+-- Description: Package with constants and function for Panda
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+package panda_package is
+
+	constant NROFADCS : natural := 32;
+	constant NROFFIBERS : natural := 4;
+	constant ADCINDEXSHIFT : natural := 1;
+	constant NROFMUXREGS : natural := 14;
+	constant ADCBITS : natural := 14;
+	constant ADCCLOCKFREQUENCY : natural := 80000000; -- 80000000; -- 62500000;
+	constant FEESLOWCONTROLADRESSES : natural := 2*NROFADCS/(ADCINDEXSHIFT+1)+4;
+	constant FEESLOWCONTROLBOARDADDRESS : natural := 2*NROFADCS/(ADCINDEXSHIFT+1);
+	
+-- statusbyte in data stream :
+    constant STATBYTE_DCPULSESKIPPED     : std_logic_vector(7 downto 0) := "00000100";
+    constant STATBYTE_DCWAVESKIPPED      : std_logic_vector(7 downto 0) := "00000100";
+    constant STATBYTE_DCCOMBINEDHITS     : std_logic_vector(7 downto 0) := "00000001";
+    constant STATBYTE_DCCOMBINEDDISCARDED : std_logic_vector(7 downto 0) := "00000010";
+    constant STATBYTE_DCSUPERBURSTMISSED : std_logic_vector(7 downto 0) := "00001100";
+
+    constant STATBYTE_FEEPULSESKIPPED    : std_logic_vector(7 downto 0) := "01000000";
+    constant STATBYTE_FEECFNOZEROCROSS   : std_logic_vector(7 downto 0) := "00100000";
+    constant STATBYTE_FEECFERROR         : std_logic_vector(7 downto 0) := "00010000";
+
+-- fiber constants
+constant KCHAR280        : std_logic_vector(7 downto 0) := "00011100"; -- 1C
+constant KCHAR281        : std_logic_vector(7 downto 0) := "00111100"; -- 3C
+constant KCHAR285        : std_logic_vector(7 downto 0) := "10111100"; -- BC
+-- constant KCHAR277        : std_logic_vector(7 downto 0) := "11111011"; -- FB
+constant KCHAR286        : std_logic_vector(7 downto 0) := x"DC";
+
+constant KCHARIDLE       : std_logic_vector(15 downto 0) := KCHAR281 & KCHAR285;  -- 3CBC peter: bytes different for word sync
+constant KCHARSODASTART  : std_logic_vector(15 downto 0) := KCHAR280 & KCHAR280;  -- 1C1C
+constant KCHARSODASTOP   : std_logic_vector(15 downto 0) := KCHAR281 & KCHAR281;  -- 3C3C
+constant KCHARSODA       : std_logic_vector(7 downto 0) := KCHAR286;  -- DC
+	
+-- addresses slowcontrol commands for Multiplexer board
+	constant ADDRESS_MUX_FIBERMODULE_STATUS : std_logic_vector(23 downto 0) := x"800000";
+--       request : request status
+--       command: clear error bits, pulse skipped counter
+--       Reply, or in case of error: Status of the fibermodule:
+--         bit0 : error in slowcontrol to cpu occured
+--         bit1 : error if slowcontrol transmit data
+--         bit2 : error if fiber receive data
+--         bit3 : received character not in table: fiber error
+--         bit4 : pulse data skipped due to full multiplexer fifo
+--         bit5 : receiver locked
+--         bit15..8 : number of pulse data packets skipped due to full buffers
+--         bit31..16 : number of successful hamming code corrections
+	constant ADDRESS_MUX_MAXCFLUTS : std_logic_vector(23 downto 0) := x"800001";
+--         bit15..0 : data for the CF or MAX Look Up Table
+--         bit25..16 :offset for maximum correction LUT
+--         bit26 : write signal for maximum LUT
+--         bit27 : loading maximum correction LUT
+--         bit28 : enable maximum correction
+--         bit29 : write signal for Constant Fraction LUT
+--         bit30 : loading CF correction LUT
+--         bit31 : enable CF correction
+	constant ADDRESS_MUX_MULTIPLEXER_STATUS : std_logic_vector(23 downto 0) := x"800002";
+--       status/fullness of the multiplexer:
+--         bit 15..0 : number of words in input fifo of the multiplexer
+--         bit 15..0 : number of words in output fifo of the multiplexer, only for fiber index 0
+	constant ADDRESS_MUX_SODA_CONTROL : std_logic_vector(23 downto 0) := x"800003";
+--       settings for the SODA : 
+--         bit0 : enable SODA packets
+--         bit1 : reset timestamp counters
+--         bit2 : Enable data taking 
+--         bit3 : Disable data taking
+--         bit4 : Enable Aurora interface to Computer Node
+	constant ADDRESS_MUX_HISTOGRAM : std_logic_vector(23 downto 0) := x"800004";
+--       settings for the histogram : 
+--         bit0 : clear the histogram
+--         bit1 : start reading of the histogram
+--         bit10..8 : Binning of the histogram channels, scaling x-axis :
+--            000 = no scaling
+--            001 = div 2
+--            010 = div 4
+--            011 = div 8
+--            100 = div 16
+--            101 = div 32
+--            110 = div 64
+--            111 = div 128
+--         bit31..16 : Selected unique adc-number
+	constant ADDRESS_MUX_TIMESTAMP_ERRORS : std_logic_vector(23 downto 0) := x"800005";
+--       number of errors:
+--         bit 9..0 : number of timestamp mismatches
+--         bit 19..10 : number of skipped pulses
+--         bit 29..20 : number of data errors
+	constant ADDRESS_MUX_TIMESHIFT : std_logic_vector(23 downto 0) := x"800006";
+--       number of  clockcycles (incl. constant fraction) to compensate for delay SODA to FEE
+--         bit 10..0 : compensation time, fractional part; number of bits for constant fraction, see CF_FRACTIONBIT
+--         bit 30..16 : compensation time, integer part
+--         bit 31 : load LUT mode, after set to 1 starts with ADC0 on each write, and so on
+	constant ADDRESS_MUX_EXTRACTWAVE : std_logic_vector(23 downto 0) := x"800007";
+--       start extracting waveform of 1 pileup pulse:
+--         bit 15..0 : selected adcnumber
+--         bit 16 : select 1 adc, otherwise take first data arriving
+--         bit 17 : select 1 low/high combination instead of 1 adc channel
+	constant ADDRESS_MUX_EXTRACTDATA : std_logic_vector(23 downto 0) := x"800008";
+--       start extracting data of 1 pulse:
+--         bit 15..0 : selected adcnumber
+--         bit 16 : select 1 adc, otherwise take first data arriving
+--         bit 17 : select 1 low/high combination instead of 1 adc channel
+	constant ADDRESS_MUX_SYSMON : std_logic_vector(23 downto 0) := x"80000c";
+--       write to FPGA system monitor
+--         bit 31 : slect read/write, write='0', read='1'
+--         bit 30 : reset/reconfigure FPGA system monitor
+--         bit 22..16 : 7-bits address of FPGA system monitor
+--         bit 15..0 : 16-bits data for FPGA system monitor
+--       read from FPGA system monitor, effective address is the last address at data bits 30..16 that was written
+--         bit 30..16 : 7-bits effective address of FPGA system monitor
+--         bit 15..0 : data from FPGA system monitor
+	constant ADDRESS_MUX_CROSSSWITCH : std_logic_vector(23 downto 0) := x"80000d";
+--       write to cross switch configuration
+--         bit 7..0 : selected multiplexer input
+--         bit 15..8 : ADC-channel to switch to selected multiplexer input (fibernr*NROFADCS+adcnumber or fibernr*NROFADCS/2+adcnumber/2 if high/low gain ADCs are used)
+--         bit 16 : select if selected multiplexer input will be combined with neighbour (only for even inputs)
+--         bit 31 : write to configuration register (extra check)
+	constant ADDRESS_MUX_ENERGYCORRECTION : std_logic_vector(23 downto 0) := x"80000e";
+--       energy correction Look Up Table
+--         bit 15..0 : gain correction (multiplying factor shifted by number of scalingsbits)
+--         bit 30..16 : offset for energy
+--         bit 31 : loading LUT mode, after set to 1 starts with ADC0 on each write, and so on
+
+-- addresses slowcontrol commands for Multiplexer
+	constant ADDRESS_BOARDNUMBER : std_logic_vector(23 downto 0) := x"002000";
+--         bit11..0 = sets the unique boardnumber
+--         bit31 = initialize all FEE registers that have been set
+
+-- addresses slowcontrol commands for Front End Electronics board
+	constant ADDRESS_FEE_CONTROL : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS,8);
+--         bit0: reset all
+--         bit2: clear errors
+--         bit3: enable waveforms
+--         bit 17..16 = ADC index from FPGA System monitor: 0=temp, 1=VCCint, 2=VCCaux, 3=spare, change activates read
+--         bit 18 = reset/initializes FPGA System monitor
+	constant ADDRESS_FEE_STATUS : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+1,8);
+--         bit1 : Data Taken enabled (enable and disabled is done with SODA packets)
+--         bit 5..4 = ADC index from FPGA System monitor: 0=temp, 1=VCCint, 2=VCCaux, 3=spare
+--         bit 15..6 = ADC value from FPGA System monitor
+--         bit23..16 : error occurred bits: in case of error a bit is set. Clearing is done with ADDRESS_FEE_CONTROL
+--            bit16 : error : NotInTable
+--            bit17 : error : receive data error (slowcontrol)
+--            bit18 : error : slowcontrol buffer overrun
+--            bit19 : error : not used
+--            bit20 : error : transmit data error, multipleser error
+--            bit21 : error : receive data buffer overrun
+--            bit22 : error : adc data buffer overrun
+--            bit23 : error : receive fiber not locked
+	constant ADDRESS_FEE_SLOWCONTROLERROR : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+2,8);
+--            data not important; this slowcontrol command indicates buffer full
+	constant ADDRESS_FEE_MEASURE_FREQUENCY : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+3,8);
+--            bit31..0 : number of hits in one second
+	constant ADDRESS_FEE_REQUESTALLREGISTERS : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+4,8);
+
+	type array_muxregister_type is array(0 to NROFMUXREGS-1) of std_logic_vector(31 downto 0);
+	
+	type array_adc_type is array(0 to NROFADCS-1) of std_logic_vector(ADCBITS-1 downto 0);
+	type array_adc64bits_type is array(0 to NROFADCS-1) of std_logic_vector(63 downto 0);
+	type array_adc48bits_type is array(0 to NROFADCS-1) of std_logic_vector(47 downto 0);
+	type array_adc36bits_type is array(0 to NROFADCS-1) of std_logic_vector(35 downto 0);
+	type array_adc32bits_type is array(0 to NROFADCS-1) of std_logic_vector(31 downto 0);
+	type array_adc24bits_type is array(0 to NROFADCS-1) of std_logic_vector(23 downto 0);
+	type array_adc16bits_type is array(0 to NROFADCS-1) of std_logic_vector(15 downto 0);
+	type array_adc9bits_type is array(0 to NROFADCS-1) of std_logic_vector(8 downto 0);
+	type array_adc8bits_type is array(0 to NROFADCS-1) of std_logic_vector(7 downto 0);
+	type array_adc4bits_type is array(0 to NROFADCS-1) of std_logic_vector(3 downto 0);
+
+	type array_halfadc36bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(35 downto 0);
+	type array_halfadc32bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(31 downto 0);
+	type array_halfadc16bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(15 downto 0);
+	type array_halfadc9bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(8 downto 0);
+	type array_halfadc8bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(7 downto 0);
+	
+	type array_fiber64bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(63 downto 0);
+	type array_fiber48bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(47 downto 0);
+	type array_fiber36bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(35 downto 0);
+	type array_fiber32bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(31 downto 0);
+	type array_fiber31bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(30 downto 0);
+	type array_fiber24bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(23 downto 0);
+	type array_fiber16bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(15 downto 0);
+	type array_fiber12bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(11 downto 0);
+	type array_fiber10bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(9 downto 0);
+	type array_fiber9bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(8 downto 0);
+	type array_fiber8bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(7 downto 0);
+	type array_fiber4bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(3 downto 0);
+
+	type array_DCadc36bits_type is array(0 to NROFADCS/(ADCINDEXSHIFT+1)-1) of std_logic_vector(35 downto 0);
+	type array_fiberXadc36bits_type is array(0 to NROFFIBERS*(NROFADCS/(ADCINDEXSHIFT+1))-1) of std_logic_vector(35 downto 0);
+	type array_fiberXadc16bits_type is array(0 to NROFFIBERS*(NROFADCS/(ADCINDEXSHIFT+1))-1) of std_logic_vector(15 downto 0);
+	type twologarray_type is array(0 to 128) of natural;
+	constant twologarray : twologarray_type :=
+(0,0,1,1,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
+6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,7);
+	type array_fiberXadcCrossSwitch_type is array(0 to NROFFIBERS*NROFADCS/(ADCINDEXSHIFT+1)-1) of std_logic_vector(twologarray(NROFFIBERS*NROFADCS/(ADCINDEXSHIFT+1))-1 downto 0);
+
+----------------------------------------------------------------------------------
+-- add_hamming_code_26_32
+-- Fills in Hamming code bits on positions 0,1,3,7,15,31 of a 32-bits word.
+-- The Hamming code is calculated with additional parity to be able to detect
+-- an error in 2 bits.
+-- 
+-- Inputs:
+--     data_in : 32 bits data input, with 26 bits real data, the others will be filled with Hamming code
+-- 
+-- Return:
+--     32 bits data output, 26 bits original data and bits 0,1,3,7,15,31 filled with Hamming code
+-- 
+----------------------------------------------------------------------------------
+	function add_hamming_code_26_32 (data_in : in std_logic_vector) return std_logic_vector;
+	
+
+----------------------------------------------------------------------------------
+-- calc_next_channel
+-- Calculates the next index in a std_logic_vector that has value '0';
+-- Used to determine the next ADC-channel to select in a multiplexer.
+-- If all values are '1' then the same index is returned.
+-- 
+-- Inputs:
+--     adcreading : starting index in the std_logic_vector
+--     dfifo_empty : std_logic_vector to select the next index with value '0'
+-- 
+-- Return:
+--     Next index in std_logic_vector with '0'
+-- 
+----------------------------------------------------------------------------------
+	function calc_next_channel(adcreading : integer; dfifo_empty : std_logic_vector) return integer;
+
+
+----------------------------------------------------------------------------------
+-- calc_next_channel
+-- Calculates the next index in a std_logic_vector that has value '1';
+-- Used to determine the next ADC-channel to select in a multiplexer.
+-- If all values are '0' then the same index is returned.
+-- 
+-- Inputs:
+--     adcreading : starting index in the std_logic_vector
+--     data_available : std_logic_vector to select the next index with value '1'
+-- 
+-- Return:
+--     Next index in std_logic_vector with '1'
+-- 
+----------------------------------------------------------------------------------
+	function calc_next_channel_set(adcreading : integer; data_available : std_logic_vector) return integer;
+
+
+----------------------------------------------------------------------------------
+-- std_logic_vector_valid
+-- Checks if all bits in std_logic_vector are valid (0 or 1) to suppress conv_integer warnings during simulation
+-- 
+-- Inputs:
+--     data : std_logic_vector to check
+-- 
+-- Return:
+--     true if the std_logic_vector data is valid (only '0' and '1')
+-- 
+----------------------------------------------------------------------------------
+	function std_logic_vector_valid(data : in std_logic_vector) return boolean;
+
+
+end panda_package;
+
+
+package body panda_package is
+
+function calc_next_channel(adcreading : integer; dfifo_empty : std_logic_vector) return integer is
+variable i : integer range 0 to dfifo_empty'high+1;
+variable c : integer range 0 to dfifo_empty'high;
+begin
+	i := 0;
+	if adcreading=dfifo_empty'high then
+		c := 0;
+	else
+		c := adcreading+1;
+	end if;
+	while (i/=dfifo_empty'high+1) and (dfifo_empty(c)='1') loop
+		i := i+1;
+		if (c<dfifo_empty'high) then 
+			c := c+1;
+		else
+			c:=0;
+		end if;
+	end loop;
+	return c;
+end function;
+
+function calc_next_channel_set(adcreading : integer; data_available : std_logic_vector) return integer is
+variable i : integer range 0 to data_available'high+1;
+variable c : integer range 0 to data_available'high;
+begin
+	i := 0;
+	if adcreading=data_available'high then
+		c := 0;
+	else
+		c := adcreading+1;
+	end if;
+	while (i/=data_available'high+1) and (data_available(c)='0') loop
+		i := i+1;
+		if (c<data_available'high) then 
+			c := c+1;
+		else
+			c:=0;
+		end if;
+	end loop;
+	return c;
+end function;
+
+
+function add_hamming_code_26_32 (data_in : in std_logic_vector) return std_logic_vector is
+variable din_S : std_logic_vector(25 downto 0);
+variable parity_S : std_logic_vector(5 downto 0);
+variable dout_S : std_logic_vector(31 downto 0);
+begin
+	din_S(0) := data_in(2);
+	din_S(1) := data_in(4);
+	din_S(2) := data_in(5);
+	din_S(3) := data_in(6);
+	din_S(4) := data_in(8);
+	din_S(5) := data_in(9);
+	din_S(6) := data_in(10);
+	din_S(7) := data_in(11);
+	din_S(8) := data_in(12);
+	din_S(9) := data_in(13);
+	din_S(10) := data_in(14);
+	din_S(11) := data_in(16);
+	din_S(12) := data_in(17);
+	din_S(13) := data_in(18);
+	din_S(14) := data_in(19);
+	din_S(15) := data_in(20);
+	din_S(16) := data_in(21);
+	din_S(17) := data_in(22);
+	din_S(18) := data_in(23);
+	din_S(19) := data_in(24);
+	din_S(20) := data_in(25);
+	din_S(21) := data_in(26);
+	din_S(22) := data_in(27);
+	din_S(23) := data_in(28);
+	din_S(24) := data_in(29);
+	din_S(25) := data_in(30);
+
+-- calculates the Hamming code parity bits
+parity_S(0) := din_S(0) xor din_S(1) xor din_S(3) xor din_S(4) xor din_S(6) xor din_S(8) xor din_S(10) xor din_S(11) 
+			xor din_S(13) xor din_S(15) xor din_S(17) xor din_S(19) xor din_S(21) xor din_S(23) xor din_S(25);
+parity_S(1) := din_S(0) xor din_S(2) xor din_S(3) xor din_S(5) xor din_S(6) xor din_S(9) xor din_S(10) xor din_S(12) 
+			xor din_S(13) xor din_S(16) xor din_S(17) xor din_S(20) xor din_S(21) xor din_S(24) xor din_S(25);
+parity_S(2) := din_S(1) xor din_S(2) xor din_S(3) xor din_S(7) xor din_S(8) xor din_S(9) xor din_S(10) xor din_S(14) 
+			xor din_S(15) xor din_S(16) xor din_S(17) xor din_S(22) xor din_S(23) xor din_S(24) xor din_S(25);
+parity_S(3) := din_S(4) xor din_S(5) xor din_S(6) xor din_S(7) xor din_S(8) xor din_S(9) xor din_S(10) xor din_S(18) 
+			xor din_S(19) xor din_S(20) xor din_S(21) xor din_S(22) xor din_S(23) xor din_S(24) xor din_S(25);
+parity_S(4) := din_S(11) xor din_S(12) xor din_S(13) xor din_S(14) xor din_S(15) xor din_S(16) xor din_S(17) xor din_S(18) 
+			xor din_S(19) xor din_S(20) xor din_S(21) xor din_S(22) xor din_S(23) xor din_S(24) xor din_S(25);
+parity_S(5) := din_S(0) xor din_S(1) xor din_S(2) xor din_S(3) xor din_S(4) xor din_S(5) xor din_S(6) xor din_S(7) 
+			xor din_S(8) xor din_S(9) xor din_S(10) xor din_S(11) xor din_S(12) xor din_S(13) xor din_S(14) 
+			xor din_S(15) xor din_S(16) xor din_S(17) xor din_S(18) xor din_S(19) xor din_S(20) xor din_S(21) 
+			xor din_S(22) xor din_S(23) xor din_S(24) xor din_S(25) xor parity_S(0) xor parity_S(1) xor parity_S(2) 
+			xor parity_S(3) xor parity_S(4);
+
+-- collect the right bits
+	dout_S(0) := parity_S(0);
+	dout_S(1) := parity_S(1);
+	dout_S(3) := parity_S(2);
+	dout_S(7) := parity_S(3);
+	dout_S(15) := parity_S(4);
+	dout_S(31) := parity_S(5);
+
+	dout_S(2) := din_S(0);
+	dout_S(4) := din_S(1);
+	dout_S(5) := din_S(2);
+	dout_S(6) := din_S(3);
+	dout_S(8) := din_S(4);
+	dout_S(9) := din_S(5);
+	dout_S(10) := din_S(6);
+	dout_S(11) := din_S(7);
+	dout_S(12) := din_S(8);
+	dout_S(13) := din_S(9);
+	dout_S(14) := din_S(10);
+	dout_S(16) := din_S(11);
+	dout_S(17) := din_S(12);
+	dout_S(18) := din_S(13);
+	dout_S(19) := din_S(14);
+	dout_S(20) := din_S(15);
+	dout_S(21) := din_S(16);
+	dout_S(22) := din_S(17);
+	dout_S(23) := din_S(18);
+	dout_S(24) := din_S(19);
+	dout_S(25) := din_S(20);
+	dout_S(26) := din_S(21);
+	dout_S(27) := din_S(22);
+	dout_S(28) := din_S(23);
+	dout_S(29) := din_S(24);
+	dout_S(30) := din_S(25);
+	return dout_S;
+end function;
+
+
+function std_logic_vector_valid(data : in std_logic_vector) return boolean is
+variable i : integer range 0 to data'high;
+variable b : boolean;
+begin
+	i := 0;
+	b := true;
+   while i<data'high loop
+		if (data(i)='0') or (data(i)='1') then
+		else
+			b := false;
+		end if;
+		i := i+1;
+	end loop;
+	return b;
+end function;
+
+
+end panda_package;
diff --git a/data_concentrator/sources/SODA_packet_generator.vhd b/data_concentrator/sources/SODA_packet_generator.vhd
new file mode 100644
index 0000000..06081dd
--- /dev/null
+++ b/data_concentrator/sources/SODA_packet_generator.vhd
@@ -0,0 +1,387 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   04-03-2011
+-- Module Name:   SODA command generator
+-- Description:   Generates Panda SODA commands for testing and simulations
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE ieee.math_real.all;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- SODA_packet_generator
+-- Generates SODA (Synchronization Of Data Acquisition) packets for Panda
+-- These commands are used to synchronize all modules and send time-information about the bundel
+-- The packets will be synchronised to a 155.52 MHz clock.
+-- Because the data is normally 16-bits and the final ADC-clock will be the SODA clock divided by 3
+-- the generated packets are put on multiple of 6-clock cycles.
+-- The SODA packets includes begin and end k-characters (see work.panda_package).
+-- The width is 16 bits data and a bit that indicates the k-character is also sent.
+--
+-- There are two types of SODA packets: a 32-bit one and a 64-bit one.
+-- The first word contains Hamming code plus parity.
+--
+-- SODA 32-bit packet : Control packet = 4 bytes:
+--   P32 JTAG_TMS JTAG_TCK JTAG_TDI spare spare id="00" 
+--   spare(3..0) DisableDataTaking EnableDataTaking StopRun ResetToZero
+--   P16 GatedReadOut NU StartSuperburst TimeOffset(3..0) 
+--   P8 EndOfBurst StartOfBurst P4 GlobalReset P2 P1
+--
+-- SODA 64-bit packet : Time Tag packet = 2 32-bits words:
+--   P32 spare(4..0) id="01" TimeWithinBurst(7..0) P16 spare(6..0) P8 spare(2..0) P4 spare P2 P1
+--   SuperBurstNumber(23..0) BurstNumber(7..0)
+--
+-- Library
+--     work.panda_package :  for type declarations and constants
+--
+-- Generics:
+--     SUPERBURSTTIME : period time in us, must be larger than 615
+--     SODAPERIOD_IN_PS : Clock period of SODA clock in ps
+--     SODACLOCKDIV : SODA Clock divider factor : 1,2 or 4 for 8,16 or 32 bits data
+-- 
+-- Inputs:
+--     clock : clock input : SODA clock (155.52MHz divided by SODACLOCKDIV)
+--     reset : synchronous reset
+--     enable : enable sending of packets
+--     reset_timestampcounter : sets the timestamp to zero
+--     EnableDataTaking : sends packet with EnableDataTaking bit set
+--     DisableDataTaking : sends packet with DisableDataTaking bit set
+-- 
+-- Outputs:
+--     SMAs : test pins on SMA connector
+--     packet_data_out : packet data 16 bits
+--     packet_data_kchar : k-character data
+--     packet_data_out_write : packet_data_out valid
+--     packet_data_last :  last packet data word
+-- 
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity SODA_packet_generator is
+	generic (
+		SUPERBURSTTIME          : integer := 1000; -- time in us, must be larger than 615
+		SODAPERIOD_IN_PS        : natural := 8000; -- SODA clock period in ps 155.52MHz=6430, 125MHz=8000
+		SODACLOCKDIV            : natural := 2 -- 1,2,4 : SODA clock divide factor
+	);
+	port ( 
+		clock                   : in std_logic; -- 155.52 MHz divided by SODACLOCKDIV
+		reset                   : in std_logic;
+		enable                  : in std_logic;
+		reset_timestampcounter  : in std_logic;
+		EnableDataTaking        : in std_logic;
+		DisableDataTaking       : in std_logic;	
+		SMAs                    : out std_logic_vector (1 downto 0);
+		packet_data_out         : out std_logic_vector(15 downto 0);
+		packet_data_kchar       : out std_logic;
+		packet_data_out_write   : out std_logic;
+		packet_data_last        : out std_logic
+	);		
+end SODA_packet_generator;
+
+architecture Behavioral of SODA_packet_generator is
+
+signal clock12_S              : std_logic := '0';
+signal InitStartSuperBurst_S  : std_logic := '0';
+signal StartSuperBurst_S      : std_logic := '0';
+signal SuperBurstFinished_S   : std_logic := '0';
+signal Burst_S                : std_logic := '0';
+signal prev_Burst_S           : std_logic := '0';
+signal SuperBurstNumber_S     : std_logic_vector(23 downto 0) := (others => '0');
+signal BurstNumber_S          : std_logic_vector(7 downto 0) := (others => '0');
+signal request_SODA64_packet1_S : std_logic := '0';
+
+signal SODA64word1_S           : std_logic_vector(31 downto 0) := (others => '0');
+signal SODA64word2_S           : std_logic_vector(31 downto 0) := (others => '0');
+signal SODA32word_S            : std_logic_vector(31 downto 0) := (others => '0');
+
+signal JTAG_TMS_S             : std_logic := '0';
+signal JTAG_TCK_S             : std_logic := '0';
+signal JTAG_TDI_S             : std_logic := '0';
+signal StopRun_S              : std_logic := '0';
+signal GatedReadOut_S         : std_logic := '0';
+signal NU_S                   : std_logic := '0';
+signal BufferReset_S          : std_logic := '0';
+signal GlobalReset_S          : std_logic := '0';
+
+signal TimeOffset_S           : std_logic_vector(8 downto 0) := (others => '0');
+
+begin
+
+
+div12process: process(clock)
+variable counter12_V : integer range 0 to (12/SODACLOCKDIV)-1;
+begin
+	if (rising_edge(clock)) then 
+		if (reset = '1') then 
+			counter12_V := 0;
+			clock12_S <= '0';
+		else
+			if counter12_V<((12/SODACLOCKDIV)-1) then
+				counter12_V := counter12_V+1;
+				clock12_S <= '0';
+			else
+				counter12_V := 0;
+				clock12_S <= '1';
+			end if;
+		end if;
+	end if;
+end process;
+
+
+superburstprocess: process(clock)
+variable timecounter_V : integer := 0;
+variable uscounter_V : integer := 0;
+variable SODA64_delaycounter_V : integer range 0 to 31 := 31;
+begin
+	if (rising_edge(clock)) then 
+		InitStartSuperBurst_S <= '0';
+		if (reset = '1') then 
+			timecounter_V := 0;
+			uscounter_V := SUPERBURSTTIME;
+			request_SODA64_packet1_S <= '0';
+			SODA64_delaycounter_V := 31;
+		elsif enable='1' then
+		   timecounter_V := timecounter_V+(SODACLOCKDIV*SODAPERIOD_IN_PS); -- increment with ps
+			if timecounter_V>=1000000 then -- after 2us
+				timecounter_V := timecounter_V-1000000;
+				if uscounter_V=SUPERBURSTTIME then
+					InitStartSuperBurst_S <= '1';
+					uscounter_V := 0;
+				else
+					uscounter_V := uscounter_V+1;
+				end if;
+			end if;
+			if InitStartSuperBurst_S = '1' then
+				SODA64_delaycounter_V := 0;
+				request_SODA64_packet1_S <= '0';
+			else
+				if SODA64_delaycounter_V<30 then
+					SODA64_delaycounter_V:=SODA64_delaycounter_V+1;
+					request_SODA64_packet1_S <= '0';
+				elsif SODA64_delaycounter_V=30 then
+					request_SODA64_packet1_S <= '1';
+					SODA64_delaycounter_V := 31;
+				else
+					SODA64_delaycounter_V := 31;
+					request_SODA64_packet1_S <= '0';
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+burstprocess: process(clock)
+variable timecounter_V : integer;
+begin
+	if (rising_edge(clock)) then 
+		if (reset = '1') then 
+			timecounter_V := 0;
+			SuperBurstFinished_S <= '1';
+			Burst_S <= '0';
+			StartSuperBurst_S <= '0';
+			BurstNumber_S <= (others => '0');
+			SuperBurstNumber_S <= (others => '0');
+		elsif InitStartSuperBurst_S='1' then
+			timecounter_V := 0;
+			BurstNumber_S <= (others => '0');
+			SuperBurstNumber_S <= SuperBurstNumber_S+1;
+			SuperBurstFinished_S <= '0';
+			Burst_S <= '1';
+			StartSuperBurst_S <= '1';
+		elsif SuperBurstFinished_S='0' then
+			StartSuperBurst_S <= '0';
+		   timecounter_V := timecounter_V+(SODACLOCKDIV*SODAPERIOD_IN_PS); -- increment with ps
+			if Burst_S = '1' then
+				if timecounter_V>=2000000 then -- after 2us
+					timecounter_V := timecounter_V-2000000;
+					Burst_S <= '0';
+				end if;
+			else
+				if timecounter_V>=400000 then -- after 0.4us
+					timecounter_V := timecounter_V-400000;
+					if BurstNumber_S=x"ff" then
+						SuperBurstFinished_S <= '1';
+						BurstNumber_S <= (others => '0');
+						Burst_S <= '0';
+					else
+						BurstNumber_S <= BurstNumber_S+1;
+						Burst_S <= '1';
+					end if;
+				end if;				
+			end if;
+		else -- wait for next
+			StartSuperBurst_S <= '0';
+			Burst_S <= '0';
+		end if;
+	end if;
+end process;
+
+makepacketprocess: process(clock)
+variable pckt_V : std_logic_vector(31 downto 0);
+variable make_SODA32_packet_V : integer range 0 to 5;
+variable make_SODA64_packet_V : integer range 0 to 7;
+variable StartOfBurst_V : std_logic := '0';
+variable EndOfBurst_V : std_logic := '0';
+variable ResetToZero_V : std_logic := '0';
+variable DisableDataTaking_V : std_logic := '0';
+variable EnableDataTaking_V : std_logic := '0';
+variable StartSuperburst_V : std_logic := '0';
+begin
+	if (rising_edge(clock)) then 
+		if (reset = '1') then 
+			prev_Burst_S <= '0';
+			StartOfBurst_V := '0';
+			EndOfBurst_V := '0';
+			make_SODA32_packet_V := 0;
+			make_SODA64_packet_V := 0;
+			packet_data_kchar <= '0';
+			EnableDataTaking_V := '0';
+			DisableDataTaking_V := '0';
+			packet_data_out_write <= '0';
+			TimeOffset_S <= (others => '0');
+		else
+			SMAs <= (others => '0');
+			if (prev_Burst_S='0') and (Burst_S='1') and (enable='1') then -- start burst
+				make_SODA32_packet_V := 1;
+				StartSuperburst_V := StartSuperburst_S;
+				StartOfBurst_V := '1';
+				TimeOffset_S <= (others => '0');
+			elsif (prev_Burst_S='1') and (Burst_S='0') and (enable='1') then -- end burst
+				make_SODA32_packet_V := 1;
+				EndOfBurst_V := '1';
+				StartOfBurst_V := '0';
+				TimeOffset_S <= TimeOffset_S+1;
+			end if;
+			if (request_SODA64_packet1_S='1') and  (enable='1') then
+				make_SODA64_packet_V := 1;
+			end if;
+			if (reset_timestampcounter='1') and (enable='1') then
+				make_SODA32_packet_V := 1;
+				ResetToZero_V := '1';
+			end if;
+			if (EnableDataTaking = '1') and (enable='1') then
+				make_SODA32_packet_V := 1;
+				EnableDataTaking_V := '1';
+			end if;
+			if (DisableDataTaking = '1') and (enable='1') then
+				make_SODA32_packet_V := 1;
+				DisableDataTaking_V := '1';
+			end if;
+			if make_SODA64_packet_V=2 then
+				packet_data_out <= SODA64word1_S(15 downto 0);
+				packet_data_kchar <= '0';
+				packet_data_out_write <= '1';		
+				packet_data_last <= '0';
+				make_SODA64_packet_V := 3;
+			elsif make_SODA64_packet_V=3 then
+				packet_data_out <= SODA64word1_S(31 downto 16);
+				packet_data_kchar <= '0';
+				packet_data_out_write <= '1';		
+				packet_data_last <= '0';
+				make_SODA64_packet_V := 4;
+			elsif make_SODA64_packet_V=4 then
+				packet_data_out <= SODA64word2_S(15 downto 0);
+				packet_data_kchar <= '0';
+				packet_data_out_write <= '1';		
+				packet_data_last <= '0';
+				make_SODA64_packet_V := 5;
+			elsif make_SODA64_packet_V=5 then
+				packet_data_out <= SODA64word2_S(31 downto 16);
+				packet_data_kchar <= '0';
+				packet_data_out_write <= '1';		
+				packet_data_last <= '0';
+				make_SODA64_packet_V := 6;
+			elsif make_SODA64_packet_V=6 then
+				packet_data_out <= KCHARSODASTOP;
+				packet_data_kchar <= '1';
+				packet_data_out_write <= '1';		
+				packet_data_last <= '1';
+				make_SODA64_packet_V := 7;
+			elsif make_SODA64_packet_V=7 then
+				packet_data_out <= (others => '0');
+				packet_data_kchar <= '0';
+				packet_data_out_write <= '0';		
+				packet_data_last <= '0';
+				make_SODA64_packet_V := 0;
+			elsif make_SODA32_packet_V=2 then
+				packet_data_out <= SODA32word_S(15 downto 0);
+				packet_data_kchar <= '0';
+				packet_data_out_write <= '1';		
+				packet_data_last <= '0';
+				make_SODA32_packet_V := 3;
+			elsif make_SODA32_packet_V=3 then
+				packet_data_out <= SODA32word_S(31 downto 16);
+				packet_data_kchar <= '0';
+				packet_data_out_write <= '1';					
+				packet_data_last <= '0';
+				make_SODA32_packet_V := 4;
+			elsif make_SODA32_packet_V=4 then
+				packet_data_out <= KCHARSODASTOP;  
+				packet_data_kchar <= '1';
+				packet_data_out_write <= '1';		
+				packet_data_last <= '1';
+				make_SODA32_packet_V := 5;
+			elsif make_SODA32_packet_V=5 then
+				packet_data_out <= (others => '0');  
+				packet_data_kchar <= '0';
+				packet_data_out_write <= '0';		
+				packet_data_last <= '0';
+				make_SODA32_packet_V := 0;
+			elsif clock12_S='1' then
+				if make_SODA32_packet_V=1 then
+					pckt_V(31 downto 24) := "0" & JTAG_TMS_S & JTAG_TCK_S & JTAG_TDI_S & "00" & "00"; 
+					pckt_V(23 downto 16) := "0000" & DisableDataTaking_V & EnableDataTaking_V & StopRun_S & ResetToZero_V; 
+					pckt_V(15 downto 8) := "0" & GatedReadOut_S & NU_S & StartSuperburst_V &  TimeOffset_S(3 downto 0);
+					pckt_V(7 downto 0) := "0" & EndOfBurst_V & StartOfBurst_V & BufferReset_S & "0" & GlobalReset_S & "00";
+					SODA32word_S <= add_hamming_code_26_32(pckt_V);
+					SMAs(0) <= StartOfBurst_V;
+					SMAs(1) <= StartSuperburst_V; -- EndOfBurst_V;
+					packet_data_out <= KCHARSODASTART;  
+					packet_data_kchar <= '1';
+					packet_data_out_write <= '1';
+					packet_data_last <= '0';
+					packet_data_last <= '1';
+					EnableDataTaking_V := '0';
+					DisableDataTaking_V := '0';
+					StartOfBurst_V := '0';
+					StartSuperburst_V := '0';
+					EndOfBurst_V := '0';
+					StartOfBurst_V := '0';
+					ResetToZero_V := '0';
+					make_SODA32_packet_V := 2;
+				elsif make_SODA64_packet_V=1 then
+					pckt_V(31 downto 24) := "0" & "00000" & "01"; 
+					pckt_V(23 downto 16) := TimeOffset_S(8 downto 1); -- TimeOffset_S ; 
+					pckt_V(15 downto 8) := "0" & "0000000";
+					pckt_V(7 downto 0) := "0" & "000" & "0" & "0" & "00";
+					SODA64word1_S <= add_hamming_code_26_32(pckt_V);
+					SODA64word2_S(31 downto 8) <= SuperBurstNumber_S;
+					SODA64word2_S(7 downto 0) <= BurstNumber_S;
+					packet_data_out <= KCHARSODASTART;
+					packet_data_kchar <= '1';
+					packet_data_out_write <= '1';
+					packet_data_last <= '0';
+					packet_data_last <= '0';
+					make_SODA64_packet_V := 2;
+				else
+					packet_data_kchar <= '0';
+					packet_data_out_write <= '0';		
+					packet_data_last <= '0';
+				end if;
+			else
+				packet_data_kchar <= '0';
+				packet_data_out_write <= '0';		
+				packet_data_last <= '0';
+			end if;
+			prev_Burst_S <= Burst_S;
+		end if;
+	end if;
+end process;
+
+end Behavioral;
diff --git a/data_concentrator/sources/SODA_packet_receiver.vhd b/data_concentrator/sources/SODA_packet_receiver.vhd
new file mode 100644
index 0000000..fbf88bb
--- /dev/null
+++ b/data_concentrator/sources/SODA_packet_receiver.vhd
@@ -0,0 +1,313 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   04-03-2011
+-- Module Name:   SODA_packet_receiver
+-- Description:   Receives and checks SODA packets
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- SODA_packet_receiver
+-- Receives SODA (Synchronization Of Data Acquisition) packets for Panda
+-- These SODA commands are used to synchronize all modules and send time-information about the bundel
+-- The packets are synchronised to a 155.52 MHz clock.
+--
+-- There are two types of SODA packets: a 32-bit one and a 64-bit one.
+-- The first word contains Hamming code plus parity.
+--
+-- SODA 32-bit packet : Control packet = 4 bytes:
+--   P32 JTAG_TMS JTAG_TCK JTAG_TDI spare spare id="00" 
+--   spare(3..0) DisableDataTaking EnableDataTaking StopRun ResetToZero
+--   P16 GatedReadOut NU StartSuperburst TimeOffset(3..0) 
+--   P8 EndOfBurst StartOfBurst BufferReset P4 GlobalReset P2 P1
+--
+-- SODA 64-bit packet : Time Tag packet = 2 32-bits words:
+--   P32 spare(4..0) id="01" TimeWithinBurst(7..0) P16 spare(6..0) P8 spare(2..0) P4 spare P2 P1
+--   SuperBurstNumber(23..0) BurstNumber(7..0)
+--
+-- Library
+--     work.panda_package :  for type declarations and constants
+--
+-- Generics:
+--     SODACLOCKDIV : SODA Clock divider factor : 1,2 or 4 for 8,16 or 32 bits data
+-- 
+-- Inputs:
+--     clock : clock input : SODA clock (155.52MHz divided by SODACLOCKDIV)
+--     reset : reset
+--     enable : enable sending of packets
+--     SODA_data : SODA packet data received
+--     SODA_kchar : SODA packet data is k-character
+--     SODA_data_present : SODA packet data received
+--     clear_hamming_corrections : clear the counter for the hamming-code corrections
+-- 
+-- Outputs:
+--     JTAG_TMS : Jtag TMS signal
+--     JTAG_TCK : Jtag TCK signal
+--     JTAG_TDI : Jtag TDI signal
+--     DisableDataTaking : Disable Data Taking signal
+--     EnableDataTaking :  Enable Data Taking signal
+--     StopRun :  Stop Run signal
+--     ResetToZero :  Reset timepstamp clock to zero
+--     GatedReadOut :  Gated Read Out signal
+--     NU :  NU signal
+--     StartSuperburst :  Start Super Burst signal
+--     TimeOffset : Offset of SODA packet in actual burst
+--     EndOfBurst : End of Burst signal
+--     StartOfBurst : Start of Burst signal
+--     BufferReset :  Bufer Reset
+--     GlobalReset :  Global Reset
+--     error :  error in SODA packet detected
+--     TimeWithinBurst : number of clock cycles inside the burst
+--     BurstNumber : Index of the burst within a superburst
+--     SuperBurstNumber : Index of the Superbursts
+--     TimeTagValid : Data from Time Tag Packet is valid : TimeWithinBurst,BurstNumber,SuperBurstNumber
+--     hamming_correction : pulse that indicates successful correction by the Hamming code
+--     hamming_corrections : number of successful correction by the Hamming code
+-- 
+-- Components:
+--     HammingDecode26_32 : Decodes Hamming code, (not clocked)
+--
+----------------------------------------------------------------------------------
+
+entity SODA_packet_receiver is
+	generic (
+		SODACLOCKDIV : natural  := 2 -- 1,2,4 : SODA clock divide factor
+	);
+	port ( 
+		clock                   : in std_logic; -- 155.52 MHz divided by SODACLOCKDIV
+		reset                   : in std_logic;
+		enable                  : in std_logic;
+		SODA_data               : in std_logic_vector(15 downto 0);
+		SODA_kchar              : in std_logic;
+		SODA_data_present       : in std_logic;
+		JTAG_TMS                : out std_logic;
+		JTAG_TCK                : out std_logic;
+		JTAG_TDI                : out std_logic;
+		DisableDataTaking       : out std_logic;
+		EnableDataTaking        : out std_logic;
+		StopRun                 : out std_logic;
+		ResetToZero             : out std_logic;
+		GatedReadOut            : out std_logic;
+		NU                      : out std_logic;
+		StartSuperburst         : out std_logic;
+		TimeOffset              : out std_logic_vector(3 downto 0);
+		EndOfBurst              : out std_logic;
+		StartOfBurst            : out std_logic;
+		BufferReset             : out std_logic;
+		GlobalReset             : out std_logic;
+		TimeWithinBurst         : out std_logic_vector(7 downto 0);
+		BurstNumber             : out std_logic_vector(7 downto 0);
+		SuperBurstNumber        : out std_logic_vector(23 downto 0);
+		TimeTagValid            : out std_logic;
+		hamming_correction      : out std_logic;
+		hamming_corrections     : out std_logic_vector (15 downto 0);
+		clear_hamming_corrections : in std_logic;
+		error                   : out std_logic);
+end SODA_packet_receiver;
+
+
+
+
+architecture Behavioral of SODA_packet_receiver is
+
+component HammingDecode26_32 is
+    Port ( 
+		data_in                 : in  std_logic_vector (31 downto 0);
+		data_out                : out  std_logic_vector (31 downto 0);
+		corrected               : out  std_logic;
+		error                   : out  std_logic);
+end component;
+
+
+signal reset_S                      : std_logic;
+signal data_hamming_S               : std_logic_vector (31 downto 0);
+signal data_hamming_corrected_S     : std_logic;
+signal data_hamming_error_S         : std_logic;
+signal hamming_corrections_S        : std_logic_vector (15 downto 0) := (others => '0');
+
+signal SODA_data_S                  : std_logic_vector (31 downto 0) := (others => '0');
+signal SODA_data_present_S          : std_logic := '0';
+
+signal SODA_data_LSB_S              : std_logic_vector (15 downto 0) := (others => '0');
+signal SODA_data_second16_S         : std_logic := '0';
+
+signal SODA32_S                     : std_logic_vector (31 downto 0) := (others => '0');
+signal SODA32_valid_S               : std_logic := '0';
+signal expectsecond_S               : std_logic := '0';
+signal TimeWithinBurst_S            : std_logic_vector (7 downto 0) := (others => '0');
+
+begin
+
+hammingdecoder : HammingDecode26_32 port map(
+		data_in      => SODA_data_S,
+		data_out     => data_hamming_S,
+		corrected    => data_hamming_corrected_S,
+		error        => data_hamming_error_S);
+		
+process16to32: process(clock)
+begin
+	if rising_edge(clock) then
+		if (reset_S='1') then
+			SODA_data_second16_S <= '0';
+		else
+			if SODA_data_second16_S='0' then
+				if (SODA_data_present='1') and (SODA_kchar='0') then
+					SODA_data_second16_S <= '1';
+					SODA_data_LSB_S <= SODA_data;
+				else
+					SODA_data_second16_S <= '0';
+				end if;
+				SODA_data_present_S <= '0';
+			else
+				if (SODA_data_present='1') and (SODA_kchar='0') then
+					SODA_data_S <=  SODA_data & SODA_data_LSB_S;
+					SODA_data_present_S <= '1';
+				else
+					SODA_data_present_S <= '0';
+				end if;
+				SODA_data_second16_S <= '0';
+			end if;
+		end if;
+		reset_S <= reset;
+	end if;
+end process;
+
+
+-- counter for number of hamming code corrections		
+hamming_correction_counter: process(clock)
+begin
+	if rising_edge(clock) then
+		if (reset_S='1') or (clear_hamming_corrections='1') then
+			hamming_corrections_S <= (others => '0');
+			hamming_correction <= '0';
+		else
+			if (SODA_data_present_S='1') and (enable='1') and (expectsecond_S='0')
+						and (data_hamming_corrected_S='1') then
+				if (hamming_corrections_S /= x"ffff") then
+					hamming_corrections_S <= hamming_corrections_S+1;
+				end if;
+				hamming_correction <= '1';
+			else
+				hamming_correction <= '0';
+			end if;
+		end if;
+	end if;
+end process;
+hamming_corrections <= hamming_corrections_S;		
+
+bitset32process: process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if (reset_S = '1') then 
+			JTAG_TMS <= '0';
+			JTAG_TCK <= '0';
+			JTAG_TDI <= '0';
+			TimeOffset <= "0000";
+		elsif SODA32_valid_S='1' then
+			JTAG_TMS <= SODA32_S(30);
+			JTAG_TCK <= SODA32_S(29);
+			JTAG_TDI <= SODA32_S(28);
+			TimeOffset <= SODA32_S(11 downto 8);
+		end if;
+	end if;
+end process;
+
+	DisableDataTaking <= SODA32_S(19) when SODA32_valid_S='1' else '0';
+	EnableDataTaking <= SODA32_S(18) when SODA32_valid_S='1' else '0';
+	StopRun <= SODA32_S(17) when SODA32_valid_S='1' else '0';
+	ResetToZero <= SODA32_S(16) when SODA32_valid_S='1' else '0';
+	GatedReadOut <= SODA32_S(14) when SODA32_valid_S='1' else '0';
+	NU <= SODA32_S(13) when SODA32_valid_S='1' else '0';
+	StartSuperburst <= SODA32_S(12) when SODA32_valid_S='1' else '0';
+	EndOfBurst <= SODA32_S(6) when SODA32_valid_S='1' else '0';
+	StartOfBurst <= SODA32_S(5) when SODA32_valid_S='1' else '0';
+	BufferReset <= SODA32_S(4) when SODA32_valid_S='1' else '0';
+	GlobalReset <= SODA32_S(2) when SODA32_valid_S='1' else '0';
+
+
+set64process: process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if (reset_S = '1') then 
+			JTAG_TMS <= '0';
+			JTAG_TCK <= '0';
+			JTAG_TDI <= '0';
+			TimeOffset <= "0000";
+		elsif SODA32_valid_S='1' then
+			JTAG_TMS <= SODA32_S(30);
+			JTAG_TCK <= SODA32_S(29);
+			JTAG_TDI <= SODA32_S(28);
+			TimeOffset <= SODA32_S(11 downto 8);
+		end if;
+	end if;
+end process;
+
+
+
+packetreceiveprocess: process(clock)
+variable expectsecondcounter_V : integer range 0 to 7; -- timeout counter for second word
+begin
+	if (rising_edge(clock)) then 
+		if (reset_S = '1') then 
+			SODA32_valid_S <= '0';
+			expectsecond_S <= '0';
+			error <= '0';
+		elsif enable='0' then
+			expectsecond_S <= '0';
+			SODA32_valid_S <= '0';
+			TimeTagValid <= '0';
+			error <= '0';
+		else
+			if SODA_data_present_S='1' then
+				if expectsecond_S = '0' then
+					TimeTagValid <= '0';
+					if data_hamming_error_S='1' then
+						SODA32_valid_S <= '0';
+						error <= '1';
+					else
+						if data_hamming_S(25 downto 24) = "00" then -- SODA32
+							SODA32_S <= data_hamming_S;
+							SODA32_valid_S <= '1';
+							error <= '0';
+						elsif data_hamming_S(25 downto 24) = "01" then -- SODA64
+							expectsecondcounter_V:=0; 
+							expectsecond_S <= '1';
+							TimeWithinBurst_S <= data_hamming_S(23 downto 16);
+							SODA32_valid_S <= '0';
+							error <= '0';
+						else
+							error <= '1';
+						end if;
+					end if;
+				else -- second word
+					SuperBurstNumber <= SODA_data_S(31 downto 8);
+					BurstNumber <= SODA_data_S(7 downto 0);
+					TimeWithinBurst <= TimeWithinBurst_S;
+					TimeTagValid <= '1';
+					SODA32_valid_S <= '0';
+					expectsecond_S <= '0';
+				end if;
+			else
+				TimeTagValid <= '0';
+				SODA32_valid_S <= '0';
+				if expectsecond_S='1' then
+					if expectsecondcounter_V<7 then
+						expectsecondcounter_V := expectsecondcounter_V+1;
+					else
+						error <= '1';
+						expectsecond_S <= '0';
+					end if;
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+end Behavioral;
diff --git a/data_concentrator/sources/blockmem.vhd b/data_concentrator/sources/blockmem.vhd
new file mode 100644
index 0000000..ed4a6f0
--- /dev/null
+++ b/data_concentrator/sources/blockmem.vhd
@@ -0,0 +1,69 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   31-01-2012
+-- Module Name:   blockmem
+-- Description:   Generic memory block
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+------------------------------------------------------------------------------------------------------
+-- blockmem
+--		Generic memory block with separated addresses for reading and writing
+--
+--
+-- generics
+--    ADDRESS_BITS : Number of bits for the address
+--    DATA_BITS : number of bits for data
+--		
+-- inputs
+--		clock : clock 
+--		write_enable : write to memory
+--		write_address : address to write to
+--		data_in : data to write into memory
+--		read_address : address to read from
+--			  
+-- outputs
+--		data_out : data from memory
+--
+-- components
+--
+------------------------------------------------------------------------------------------------------
+
+entity blockmem is
+	generic (
+		ADDRESS_BITS : natural := 8;
+		DATA_BITS  : natural := 18
+		);
+	port (
+		clock                   : in  std_logic; 
+		write_enable            : in std_logic;
+		write_address           : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_in                 : in std_logic_vector(DATA_BITS-1 downto 0);
+		read_address            : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_out                : out std_logic_vector(DATA_BITS-1 downto 0)
+	);
+end blockmem;
+
+architecture behavioral of blockmem is
+	type mem_type is array (2**ADDRESS_BITS-1 downto 0) of std_logic_vector (DATA_BITS-1 downto 0);
+	signal mem_S : mem_type := (others => (others => '0'));
+									 
+begin
+
+	process (clock)
+	begin
+		if (clock'event and clock = '1') then
+			if (write_enable = '1') then
+				mem_S(conv_integer(write_address)) <= data_in;
+			end if;
+			data_out <= mem_S(conv_integer(read_address));			
+		end if;
+	end process;
+	
+
+end architecture behavioral;
\ No newline at end of file
diff --git a/data_concentrator/sources/crc8_add_check32.vhd b/data_concentrator/sources/crc8_add_check32.vhd
new file mode 100644
index 0000000..9784525
--- /dev/null
+++ b/data_concentrator/sources/crc8_add_check32.vhd
@@ -0,0 +1,140 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   22-02-2011
+-- Module Name:   crc8_add_check32 
+-- Description:   Add and checks a CRC8 code to a stream of 32 bits data words
+----------------------------------------------------------------------------------
+                   
+LIBRARY IEEE ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+
+----------------------------------------------------------------------------------
+-- crc8_add_check32
+-- Checks and adds a CRC8 code to a stream of 32 bits data words.
+-- This module can be used to add a CRC8 code and/or checks the CRC8 code.
+-- 
+-- The last byte (that is LSB of the 32-bits word) filled with the CRC8 code,
+-- overwriting the original data, and this original data is compared with the
+-- CRC8 code. If they are not the same the crc_error output bit is high.
+-- The CRC8 is calculated on all 32-bits data words, with the LSB of the last word
+-- set to "00000000";
+-- The CRC8 code is calculated with initialize code "00000000".
+-- An explanation can be found at www.ElectronicDesignworks.com
+--
+-- Library:
+-- 
+-- Generics:
+-- 
+-- Inputs:
+--     clock : one clock is used
+--     reset : synchronous reset
+--     data_in : 32 bits data input, LSB last byte is CRC8 or becomes CRC8
+--     data_in_valid : data_in word is valid
+--     data_in_last : last data in the 32-bits stream; contains or will contain CRC8
+-- 
+-- Outputs:
+--     data_out : 32 bits data output, LSB last byte is CRC8
+--     data_out_valid : data_in word is valid
+--     data_out_last : last data in the 32-bits stream; contains CRC8
+--     crc_error : CRC8 code in original data_in was wrong, 
+--                 can be ignored if the module is used to add a CRC8
+-- 
+----------------------------------------------------------------------------------
+entity crc8_add_check32 is 
+   port(           
+		clock                   : in  std_logic; 
+		reset                   : in  std_logic; 
+		data_in                 : in  std_logic_vector(31 DOWNTO 0); 
+		data_in_valid           : in  std_logic; 
+		data_in_last            : in  std_logic; 
+		data_out                : out std_logic_vector(31 DOWNTO 0); 
+		data_out_valid          : out std_logic;
+		data_out_last           : out std_logic;
+		crc_error               : out std_logic
+	);
+end crc8_add_check32; 
+
+architecture behaviour OF crc8_add_check32 IS 
+	constant	CRC_INIT          : std_logic_vector(7 DOWNTO 0) := "00000000"; 
+	signal crc_S               : std_logic_vector(7 DOWNTO 0) := "00000000";
+	signal crc_aftr1clk_S      : std_logic_vector(7 DOWNTO 0) := "00000000";
+	signal crc_feedback_S      : std_logic_vector(7 DOWNTO 0) := "00000000";
+	signal start_on_next_S     : std_logic := '0'; 
+	signal din_S               : std_logic_vector(31 DOWNTO 0);
+	
+begin 
+
+crc_feedback_S <= CRC_INIT when ((start_on_next_S='1') and (data_in_valid='1')) else crc_aftr1clk_S;
+
+din_S(31 downto 8) <= data_in(31 downto 8);
+din_S(7 downto 0) <= data_in(7 downto 0) when data_in_last='0' else (others => '0');
+crc_S(0) <= din_S(0) XOR din_S(1) XOR din_S(9) XOR din_S(18) XOR din_S(27) XOR 
+		crc_feedback_S(3) XOR din_S(10) XOR din_S(19) XOR din_S(28) XOR crc_feedback_S(4); 
+crc_S(1) <= din_S(0) XOR din_S(2) XOR din_S(11) XOR din_S(20) XOR din_S(29) XOR crc_feedback_S(5) 
+		XOR din_S(9) XOR din_S(18) XOR din_S(27) XOR crc_feedback_S(3); 
+crc_S(2) <= din_S(0) XOR din_S(3) XOR din_S(12) XOR din_S(21) XOR din_S(30) XOR crc_feedback_S(6) 
+		XOR din_S(9) XOR din_S(18) XOR din_S(27) XOR crc_feedback_S(3); 
+crc_S(3) <= din_S(0) XOR din_S(4) XOR din_S(13) XOR din_S(22) XOR din_S(31) XOR crc_feedback_S(7) 
+		XOR din_S(9) XOR din_S(18) XOR din_S(27) XOR crc_feedback_S(3); 
+crc_S(4) <= din_S(0) XOR din_S(5) XOR din_S(14) XOR din_S(23) XOR din_S(9) XOR din_S(18) XOR din_S(27) 
+		XOR crc_feedback_S(3); 
+crc_S(5) <= din_S(0) XOR din_S(6) XOR din_S(15) XOR din_S(24) XOR crc_feedback_S(0) XOR din_S(9) 
+		XOR din_S(18) XOR din_S(27) XOR crc_feedback_S(3); 
+crc_S(6) <= din_S(0) XOR din_S(7) XOR din_S(16) XOR din_S(25) XOR crc_feedback_S(1) XOR din_S(9) 
+		XOR din_S(18) XOR din_S(27) XOR crc_feedback_S(3); 
+crc_S(7) <= din_S(0) XOR din_S(8) XOR din_S(17) XOR din_S(26) XOR crc_feedback_S(2) XOR din_S(9) 
+		XOR din_S(18) XOR din_S(27) XOR crc_feedback_S(3); 
+
+crc_process : process(clock, reset) 
+begin
+	if (rising_edge(clock)) then 
+		if (reset = '1') then 
+			crc_error <= '0';                             
+			start_on_next_S <= '1';
+			data_out_valid <= '0';
+			data_out_last <= '0';
+			crc_aftr1clk_S <= "00000000" ;
+		else
+			if (data_in_valid = '1') then
+				crc_aftr1clk_S <= crc_S;
+				data_out_valid <= '1';
+				if (data_in_last = '1') then 
+					start_on_next_S <= '1';
+					data_out_last <= '1';
+					data_out(31 downto 8) <= data_in(31 downto 8);
+					data_out(7 downto 0) <= crc_S;
+					if crc_S/=data_in(7 downto 0) then
+						crc_error <= '1';
+					else
+						crc_error <= '0';                             
+					end if;
+				else
+					data_out(31 downto 0) <= data_in(31 downto 0);
+					start_on_next_S <= '0';     
+					crc_error <= '0';                             
+					data_out_last <= '0';
+				end if;
+			else
+				crc_error <= '0';                             
+				data_out_valid <= '0';
+				data_out_last <= '0';
+			end if; 
+		end if;
+	end if;    
+end process crc_process; 
+
+
+end behaviour;
+                      
+
+
+
+
+
+ 
+
+
+
diff --git a/data_concentrator/sources/crc8_add_check64.vhd b/data_concentrator/sources/crc8_add_check64.vhd
new file mode 100644
index 0000000..b4be8f2
--- /dev/null
+++ b/data_concentrator/sources/crc8_add_check64.vhd
@@ -0,0 +1,152 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   22-02-2011
+-- Module Name:   crc8_add_check64 
+-- Description:   Add and checks a CRC8 code to a stream of 64 bits data words
+----------------------------------------------------------------------------------
+                   
+LIBRARY IEEE ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+
+----------------------------------------------------------------------------------
+-- crc8_add_check64
+-- Checks and adds a CRC8 code to a stream of 64 bits data words.
+-- This module can be used to add a CRC8 code and/or checks the CRC8 code.
+-- 
+-- The last byte (that is LSB of the 64-bits word) filled with the CRC8 code,
+-- overwriting the original data, and this original data is compared with the
+-- CRC8 code. If they are not the same the crc_error output bit is high.
+-- The CRC8 is calculated on all 64-bits data words, with the LSB of the last word
+-- set to "00000000";
+-- The CRC8 code is calculated with initialize code "00000000".
+-- An explanation can be found at www.ElectronicDesignworks.com
+--
+-- Library:
+-- 
+-- Generics:
+-- 
+-- Inputs:
+--     clock : one clock is used
+--     reset : synchronous reset
+--     data_in : 64 bits data input, LSB last byte is CRC8 or becomes CRC8
+--     data_in_valid : data_in word is valid
+--     data_in_last : last data in the 64-bits stream; contains or will contain CRC8
+-- 
+-- Outputs:
+--     data_out : 64 bits data output, LSB last byte is CRC8
+--     data_out_valid : data_in word is valid
+--     data_out_last : last data in the 64-bits stream; contains CRC8
+--     crc_error : CRC8 code in original data_in was wrong, 
+--                 can be ignored if the module is used to add a CRC8
+-- 
+----------------------------------------------------------------------------------
+entity crc8_add_check64 is 
+   port(           
+		clock                   : in  std_logic; 
+		reset                   : in  std_logic; 
+		data_in                 : in  std_logic_vector(63 downto 0); 
+		data_in_valid           : in  std_logic; 
+		data_in_last            : in  std_logic; 
+		data_out                : out std_logic_vector(63 downto 0); 
+		data_out_valid          : out std_logic;
+		data_out_last           : out std_logic;
+		crc_error               : out std_logic
+	);
+end crc8_add_check64; 
+
+architecture behaviour OF crc8_add_check64 IS 
+	constant	CRC_INIT          : std_logic_vector(7 downto 0) := "00000000"; 
+	signal crc_S               : std_logic_vector(7 downto 0) := "00000000";
+	signal crc_aftr1clk_S      : std_logic_vector(7 downto 0) := "00000000";
+	signal crc_feedback_S      : std_logic_vector(7 downto 0) := "00000000";
+	signal start_on_next_S     : std_logic := '0'; 
+	signal din_S               : std_logic_vector(63 downto 0);
+	
+begin 
+
+crc_feedback_S <= CRC_INIT when ((start_on_next_S='1') and (data_in_valid='1')) else crc_aftr1clk_S;
+
+din_S(63 downto 8) <= data_in(63 downto 8);
+din_S(7 downto 0) <= data_in(7 downto 0) when data_in_last='0' else (others => '0');
+
+
+
+crc_S(0) <= din_S(0) XOR din_S(1) XOR din_S(9) XOR din_S(18) XOR din_S(27) XOR din_S(36) XOR 
+	din_S(45) XOR din_S(54) XOR din_S(63) XOR crc_feedback_S(7) XOR din_S(10) XOR din_S(19) XOR 
+	din_S(28) XOR din_S(37) XOR din_S(46) XOR din_S(55); 
+crc_S(1) <= din_S(0) XOR din_S(2) XOR din_S(11) XOR din_S(20) XOR din_S(29) XOR din_S(38) XOR 
+	din_S(47) XOR din_S(56) XOR crc_feedback_S(0) XOR din_S(9) XOR din_S(18) XOR din_S(27) XOR 
+	din_S(36) XOR din_S(45) XOR din_S(54) XOR din_S(63) XOR crc_feedback_S(7); 
+crc_S(2) <= din_S(0) XOR din_S(3) XOR din_S(12) XOR din_S(21) XOR din_S(30) XOR din_S(39) XOR 
+	din_S(48) XOR din_S(57) XOR crc_feedback_S(1) XOR din_S(9) XOR din_S(18) XOR din_S(27) XOR 
+	din_S(36) XOR din_S(45) XOR din_S(54) XOR din_S(63) XOR crc_feedback_S(7); 
+crc_S(3) <= din_S(0) XOR din_S(4) XOR din_S(13) XOR din_S(22) XOR din_S(31) XOR din_S(40) XOR 
+	din_S(49) XOR din_S(58) XOR crc_feedback_S(2) XOR din_S(9) XOR din_S(18) XOR din_S(27) XOR 
+	din_S(36) XOR din_S(45) XOR din_S(54) XOR din_S(63) XOR crc_feedback_S(7); 
+crc_S(4) <= din_S(0) XOR din_S(5) XOR din_S(14) XOR din_S(23) XOR din_S(32) XOR din_S(41) XOR 
+	din_S(50) XOR din_S(59) XOR crc_feedback_S(3) XOR din_S(9) XOR din_S(18) XOR din_S(27) XOR 
+	din_S(36) XOR din_S(45) XOR din_S(54) XOR din_S(63) XOR crc_feedback_S(7); 
+crc_S(5) <= din_S(0) XOR din_S(6) XOR din_S(15) XOR din_S(24) XOR din_S(33) XOR din_S(42) XOR 
+	din_S(51) XOR din_S(60) XOR crc_feedback_S(4) XOR din_S(9) XOR din_S(18) XOR din_S(27) XOR 
+	din_S(36) XOR din_S(45) XOR din_S(54) XOR din_S(63) XOR crc_feedback_S(7); 
+crc_S(6) <= din_S(0) XOR din_S(7) XOR din_S(16) XOR din_S(25) XOR din_S(34) XOR din_S(43) XOR 
+	din_S(52) XOR din_S(61) XOR crc_feedback_S(5) XOR din_S(9) XOR din_S(18) XOR din_S(27) XOR 
+	din_S(36) XOR din_S(45) XOR din_S(54) XOR din_S(63) XOR crc_feedback_S(7); 
+crc_S(7) <= din_S(0) XOR din_S(8) XOR din_S(17) XOR din_S(26) XOR din_S(35) XOR din_S(44) XOR 
+	din_S(53) XOR din_S(62) XOR crc_feedback_S(6) XOR din_S(9) XOR din_S(18) XOR din_S(27) XOR 
+	din_S(36) XOR din_S(45) XOR din_S(54) XOR din_S(63) XOR crc_feedback_S(7); 
+
+
+crc_process : process(clock, reset) 
+begin
+	if (rising_edge(clock)) then 
+		if (reset = '1') then 
+			crc_error <= '0';                             
+			start_on_next_S <= '1';
+			data_out_valid <= '0';
+			data_out_last <= '0';
+			crc_aftr1clk_S <= "00000000" ;
+		else
+			if (data_in_valid = '1') then
+				crc_aftr1clk_S <= crc_S;
+				data_out_valid <= '1';
+				if (data_in_last = '1') then 
+					start_on_next_S <= '1';
+					data_out_last <= '1';
+					data_out(63 downto 8) <= data_in(63 downto 8);
+					data_out(7 downto 0) <= crc_S;
+					if crc_S/=data_in(7 downto 0) then
+						crc_error <= '1';
+					else
+						crc_error <= '0';                             
+					end if;
+				else
+					data_out(63 downto 0) <= data_in(63 downto 0);
+					start_on_next_S <= '0';     
+					crc_error <= '0';                             
+					data_out_last <= '0';
+				end if;
+			else
+				crc_error <= '0';                             
+				data_out_valid <= '0';
+				data_out_last <= '0';
+			end if; 
+		end if;
+	end if;    
+end process crc_process; 
+
+
+end behaviour;
+                      
+
+
+
+
+
+ 
+
+
+
diff --git a/data_concentrator/sources/dataconversion_for_serdes.vhd b/data_concentrator/sources/dataconversion_for_serdes.vhd
new file mode 100644
index 0000000..ca74dd5
--- /dev/null
+++ b/data_concentrator/sources/dataconversion_for_serdes.vhd
@@ -0,0 +1,294 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI-CART/RUG/Groningen University
+-- Engineer:      Oscar Kuiken
+-- Create Date:   04-feb-2014
+-- Module Name:   dataconversion_for_serdes
+-- Description:   Converts the 64-bits data from MUX to 8-bit data suitable for 
+--                SERDES communication. Control signals from MUX are transformed
+--                into k-characters.
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+
+entity dataconversion_for_serdes is
+  generic(
+    CREATE_OWN_STIMULI : BOOLEAN := FALSE);
+  port(
+    DATA_CLK        : in  std_logic;
+	CLK             : in  std_logic;
+    RESET           : in  std_logic;
+    TX_READY        : in  std_logic;
+    SFP_MOD0        : in  std_logic;
+    SFP_LOS         : in  std_logic;
+    TX_DATA         : out std_logic_vector(7 downto 0);
+    TX_K            : out std_logic;
+    DATA_IN_ALLOWED : out std_logic;
+    DATA_IN         : in  std_logic_vector(63 downto 0);
+    DATA_IN_WRITE   : in  std_logic;
+    DATA_IN_FIRST   : in  std_logic;
+    DATA_IN_LAST    : in  std_logic;
+    DATA_IN_ERROR   : in  std_logic);
+end dataconversion_for_serdes;
+
+architecture behaviour of dataconversion_for_serdes is
+
+component fifo_8x66
+port (
+		DATA    : in  std_logic_vector(65 downto 0);
+		CLOCK   : in  std_logic; 
+		WREN    : in  std_logic;
+		RDEN    : in  std_logic;
+		RESET   : in  std_logic;
+		Q       : out  std_logic_vector(65 downto 0);
+		EMPTY   : out  std_logic; 
+		FULL    : out  std_logic);
+end component;
+
+component async_fifo_256x66 is
+port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(65 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(65 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic
+	);
+end component;
+
+  signal fifo_rden                : std_logic;
+  signal fifo_rden_d1             : std_logic;
+  signal fifo_data_out            : std_logic_vector(65 downto 0);
+  signal fifo_data_out_d1         : std_logic_vector(65 downto 0);
+  signal fifo_empty               : std_logic;
+  signal fifo_full                : std_logic;
+  
+  signal word_cnt                 : integer range 0 to 15;
+  signal break_cnt                : integer range 0 to 16383;
+  signal no_packet_send           : std_logic;
+  signal stimuli                  : std_logic_vector(63 downto 0);
+  
+  signal data_in_generated        : std_logic_vector(63 downto 0);
+  signal data_in_first_generated  : std_logic;
+  signal data_in_last_generated   : std_logic;
+  signal data_in_write_generated  : std_logic;
+  
+  signal reset_everything         : std_logic;
+  signal reset_everything_dataclk : std_logic;
+  
+  
+  type state_type is (idle, send8b_1_or_send_firstflag, send8b_1, send8b_2, send8b_3, send8b_4, send8b_5, send8b_6, send8b_7, send8b_8, send_lastflag);
+  signal current_state, next_state : state_type;
+
+begin
+
+  reset_everything <= '1' when (RESET = '1') or (TX_READY = '0') or (SFP_MOD0 = '1') or (SFP_LOS = '1') else '0';
+
+  local_stimuli: if CREATE_OWN_STIMULI = TRUE generate
+  
+--    tx_fifo : fifo_8x66
+--      port map(
+--        DATA(65)           => data_in_first_generated,
+--        DATA(64)           => data_in_last_generated,
+--        DATA(63 downto 0)  => data_in_generated,
+--        CLOCK              => CLK,
+--        WREN               => data_in_write_generated,
+--        RDEN               => fifo_rden,
+--        RESET              => reset_everything,
+--        Q                  => fifo_data_out,
+--        EMPTY              => fifo_empty,
+--        FULL               => fifo_full);
+
+		  
+tx_fifo: async_fifo_256x66 
+	port map(
+		rst => reset_everything,
+		wr_clk => CLK,
+		rd_clk => CLK,
+		din(65) => data_in_first_generated,
+		din(64) => data_in_last_generated,
+		din(63 downto 0)  => data_in_generated,
+		wr_en => data_in_write_generated,
+		rd_en => fifo_rden,
+		dout => fifo_data_out,
+		full => fifo_full,
+		empty => fifo_empty);
+
+
+    process(reset_everything, CLK)
+    begin
+      if reset_everything = '1' then
+        word_cnt       <= 0;
+        break_cnt      <= 0;
+        no_packet_send <= '1';
+        stimuli(31 downto 0)  <= x"00000000";
+        stimuli(63 downto 32) <= x"FFFFFFFF";
+      elsif rising_edge(CLK) then
+        if not (stimuli(31 downto 0) = x"00000000" and no_packet_send = '0' and break_cnt = 500) then
+          -- If we haven't send every 32-bit number once, then we're not finished yet
+          if word_cnt < 8 then
+            word_cnt              <= word_cnt + 1;
+            stimuli(31 downto 0)  <= stimuli(31 downto 0)  + 1;
+            stimuli(63 downto 32) <= stimuli(63 downto 32) - 1;
+          elsif break_cnt < 500 then
+            break_cnt <= break_cnt + 1;
+          else
+            word_cnt  <= 0;
+            break_cnt <= 0;
+          end if;
+        end if;
+      end if;
+    end process;
+    
+    data_in_generated         <= stimuli;
+    data_in_first_generated   <= '1' when word_cnt = 0 else '0';
+    data_in_last_generated    <= '1' when word_cnt = 7 else '0';
+    data_in_write_generated   <= '1' when word_cnt < 8 else '0';
+    
+  end generate;
+  
+  external_stimuli: if CREATE_OWN_STIMULI = FALSE generate
+  
+	tx_fifo : async_fifo_256x66
+		port map (
+			rst => reset_everything,
+			wr_clk => DATA_CLK,
+			rd_clk => CLK,
+			din(65) => DATA_IN_FIRST,
+			din(64) => DATA_IN_LAST,
+			din(63 downto 0)  => DATA_IN,
+			wr_en => DATA_IN_WRITE,
+			rd_en => fifo_rden,
+			dout => fifo_data_out,
+			full => fifo_full,
+			empty => fifo_empty
+		);
+	
+   end generate;
+ 
+  DATA_IN_ALLOWED <= '1' when (fifo_full='0') and (reset_everything_dataclk='0') else '0';
+	process(DATA_CLK)
+    begin
+      if rising_edge(DATA_CLK) then
+		reset_everything_dataclk <= reset_everything;
+	  end if;
+	end process;
+		
+ 
+  process(reset_everything, CLK)
+  begin
+    if reset_everything = '1' then
+      fifo_data_out_d1 <= (others => '0');
+      fifo_rden_d1     <= '0';
+    elsif rising_edge(CLK) then
+      fifo_rden_d1 <= fifo_rden;
+      if fifo_rden_d1 = '1' then
+        fifo_data_out_d1 <= fifo_data_out;
+      end if;
+    end if;
+  end process;
+
+  process(reset_everything, CLK)
+  begin
+    if reset_everything = '1' then
+      current_state   <= idle;
+    elsif rising_edge(CLK) then
+      current_state <= next_state;
+    end if;
+  end process;
+  
+  process(current_state, fifo_empty, fifo_data_out, fifo_data_out_d1)
+  begin
+    --Default values for output signals
+    TX_DATA <= x"BC";
+    TX_K    <= '1';
+    fifo_rden   <= '0';
+    
+    case current_state is
+      when idle =>
+        if fifo_empty = '0' then
+          next_state <= send8b_1_or_send_firstflag;
+          fifo_rden <= '1';
+        else
+          next_state <= idle;
+        end if;
+        
+      when send8b_1_or_send_firstflag =>
+        if fifo_data_out(65) = '1' then
+          -- Before sending the first data of a set, k-character DC must be send
+          next_state <= send8b_1;
+          TX_DATA <= x"DC";
+          TX_K    <= '1';
+        else
+          next_state <= send8b_2;
+          TX_DATA <= fifo_data_out(63 downto 56);
+          TX_K    <= '0';
+        end if;
+        
+      when send8b_1 =>
+        next_state <= send8b_2;
+        TX_DATA <= fifo_data_out_d1(63 downto 56);
+        TX_K    <= '0';
+        
+      when send8b_2 =>
+        next_state <= send8b_3;
+        TX_DATA <= fifo_data_out_d1(55 downto 48);
+        TX_K    <= '0';
+        
+      when send8b_3 =>
+        next_state <= send8b_4;
+        TX_DATA <= fifo_data_out_d1(47 downto 40);
+        TX_K    <= '0';
+        
+      when send8b_4 =>
+        next_state <= send8b_5;
+        TX_DATA <= fifo_data_out_d1(39 downto 32);
+        TX_K    <= '0';
+        
+      when send8b_5 =>
+        next_state <= send8b_6;
+        TX_DATA <= fifo_data_out_d1(31 downto 24);
+        TX_K    <= '0';
+        
+      when send8b_6 =>
+        next_state <= send8b_7;
+        TX_DATA <= fifo_data_out_d1(23 downto 16);
+        TX_K    <= '0';
+        
+      when send8b_7 =>
+        next_state <= send8b_8;
+        TX_DATA <= fifo_data_out_d1(15 downto 8);
+        TX_K    <= '0';
+        
+      when send8b_8 =>
+        if fifo_data_out_d1(64) = '0' then -- Apparently this is not the last data of this set 
+          if fifo_empty = '1' then
+            next_state <= idle;
+          else
+            next_state <= send8b_1_or_send_firstflag;
+            fifo_rden <= '1';
+          end if;
+        else -- Apparently this is the last data of this set
+          next_state <= send_lastflag;
+        end if;
+        TX_DATA <= fifo_data_out_d1(7 downto 0);
+        TX_K    <= '0';
+        
+      when send_lastflag =>
+        if fifo_empty = '1' then
+          next_state <= idle;
+        else
+          next_state <= send8b_1_or_send_firstflag;
+          fifo_rden <= '1';
+        end if;
+        TX_DATA <= x"FC";
+        TX_K    <= '1';
+    end case;
+  end process;
+  
+end behaviour;
\ No newline at end of file
diff --git a/data_concentrator/sources/gtpBufLayerPackage.vhd b/data_concentrator/sources/gtpBufLayerPackage.vhd
new file mode 100644
index 0000000..791ca26
--- /dev/null
+++ b/data_concentrator/sources/gtpBufLayerPackage.vhd
@@ -0,0 +1,24 @@
+--	Package File Template
+--
+--	Purpose: This package defines supplemental types, subtypes, 
+--		 constants, and functions 
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package gtpBufLayer is
+
+constant KCHAR280        : std_logic_vector(7 downto 0) := "00011100"; -- 1C
+constant KCHAR281        : std_logic_vector(7 downto 0) := "00111100"; -- 3C
+constant KCHAR285        : std_logic_vector(7 downto 0) := "10111100"; -- BC
+--constant KCHAR277        : std_logic_vector(7 downto 0) := "11111011"; -- FB
+constant KCHAR286        : std_logic_vector(7 downto 0) := x"DC";
+
+constant KCHARIDLE       : std_logic_vector(15 downto 0) := KCHAR281 & KCHAR285;  -- 3CBC peter: bytes different for word sync
+constant KCHARSODASTART  : std_logic_vector(15 downto 0) := KCHAR280 & KCHAR280;  -- 1C1C
+constant KCHARSODASTOP   : std_logic_vector(15 downto 0) := KCHAR281 & KCHAR281;  -- 3C3C
+constant KCHARSODA       : std_logic_vector(7 downto 0) := KCHAR286;  -- DC
+
+
+end gtpBufLayer;
diff --git a/data_concentrator/sources/histogram.vhd b/data_concentrator/sources/histogram.vhd
new file mode 100644
index 0000000..872fa1d
--- /dev/null
+++ b/data_concentrator/sources/histogram.vhd
@@ -0,0 +1,212 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   05-04-2011
+-- Module Name:   histogram
+-- Description:   Puts values in a histogram
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+USE ieee.std_logic_1164.all ;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+----------------------------------------------------------------------------------
+-- histogram
+-- Module make a histogram of values. 
+-- Successive values must be separated by at least one clock cycle.
+-- Reading can be done when acquiring data is still in process.
+--
+-- Library
+--     work.panda_package : for type declarations and constants
+-- 
+-- Generics:
+--     HISTOGRAM_SIZEBITS : number of bits for the histogram x-axis, 2^HISTOGRAM_SIZEBITS=number of histogram channels
+--     RANGEBITS : number of bits for counts (y-axis)
+-- 
+-- Inputs:
+--     clock : clock
+--     clear : starts clearing the histogram. Clearing takes 2^HISTOGRAM_SIZEBITS clockcycles
+--     datain : values for the histogram
+--     writerequest : write for the datain values
+--     address : address (index in histogram) that has to be read
+--     readrequest : request the histogram value at address
+-- 
+-- Outputs:
+--     dataout : resulting histogram data, some time after the readrequest
+--     dataout_valid : valid signal for dataout
+-- 
+-- Components:
+--     blockram : memory for the histogram, located at the bottom of this vhdl-file
+--
+----------------------------------------------------------------------------------
+entity histogram is
+	generic (
+		HISTOGRAM_SIZEBITS      : natural := 12;
+		RANGEBITS               : natural := 32
+		);
+	port (
+		clock                   : in std_logic;
+		clear                   : in std_logic;
+		datain                  : in std_logic_vector(HISTOGRAM_SIZEBITS-1 downto 0);
+		writerequest            : in std_logic;
+		address                 : in std_logic_vector(HISTOGRAM_SIZEBITS-1 downto 0);
+		readrequest             : in std_logic;
+		dataout                 : out std_logic_vector(rangebits-1 downto 0);
+		dataout_valid           : out std_logic
+		);
+end histogram;
+
+architecture behavioral of histogram is
+
+component blockram is
+	generic (
+		WIDTH	: natural := HISTOGRAM_SIZEBITS;
+		RANGEBITS	: natural := RANGEBITS
+	);
+	port
+	(
+      reset : in  std_logic; 
+		clock : in std_logic;
+		write_enable : in std_logic;
+		address : in std_logic_vector(width-1 downto 0);
+		data_in : in std_logic_vector(rangebits-1 downto 0);
+		data_out : out std_logic_vector(rangebits-1 downto 0)
+	);
+end component;
+
+
+	signal ram_writeenable : std_logic;
+	signal ram_writeaddress : std_logic_vector(HISTOGRAM_SIZEBITS-1 downto 0);
+	signal ram_datain : std_logic_vector(rangebits-1 downto 0);
+	signal ram_dataout : std_logic_vector(rangebits-1 downto 0);
+	
+	signal write_onnextclk : std_logic := '0';
+	signal read_valid : std_logic := '0';
+	signal doclearing : std_logic := '0';
+
+begin
+
+block_ram: blockram port map(
+        reset => '0',
+        clock => clock,
+        write_enable => ram_writeenable,
+        address => ram_writeaddress,
+        data_in => ram_datain,
+        data_out => ram_dataout);
+
+ram_datain <= (others => '0') when doclearing='1' else ram_dataout+1;
+
+
+
+	process (clock)
+	variable clearcounter : integer range 0 to (2**HISTOGRAM_SIZEBITS-1);
+	variable readrequest_pending : std_logic := '0';
+	variable read_thedata : std_logic := '0';
+	begin
+		if (clock'event and clock = '1') then
+			if (clear='1') then
+				doclearing <= '1';
+				clearcounter := 2**HISTOGRAM_SIZEBITS-1;
+				ram_writeaddress <= (others => '0');
+				ram_writeenable <= '1';
+				write_onnextclk <= '0';
+				readrequest_pending := '0';
+				read_valid <= '0';
+				read_thedata := '0';
+				dataout_valid <= '0';
+				dataout_valid <= '0';
+				dataout <=  (others => '0');
+			elsif doclearing='1' then
+				ram_writeaddress <= conv_std_logic_vector(clearcounter,HISTOGRAM_SIZEBITS);
+				if clearcounter=0 then
+					ram_writeenable <= '0';
+					doclearing <= '0';
+				else
+					ram_writeenable <= '1';
+					clearcounter := clearcounter-1;
+				end if;
+				write_onnextclk <= '0';
+				readrequest_pending := '0';
+				read_valid <= '0';
+				read_thedata := '0';
+				dataout_valid <= '0';
+				dataout <=  (others => '0');
+			else
+				if read_thedata = '1' then
+					dataout <= ram_dataout;
+					dataout_valid <= '1';
+				end if;
+				if read_valid = '1' then
+					read_thedata := '1';
+					readrequest_pending := '0';
+				elsif readrequest = '1' then
+					dataout_valid <= '0';
+					read_thedata := '0';
+					readrequest_pending := '1';					
+				else 
+					read_thedata := '0';
+				end if;
+				
+				if write_onnextclk='1' then
+					ram_writeenable <= '1';
+					write_onnextclk <= '0';					
+					read_valid <= '0';
+				elsif (writerequest = '1') then
+					ram_writeenable <= '0';
+					ram_writeaddress <= datain;
+					read_valid <= '0';
+					write_onnextclk <= '1';
+				elsif (readrequest_pending = '1') and (read_valid = '0') then
+					ram_writeenable <= '0';
+					ram_writeaddress <= address;
+					read_valid <= '1';
+					write_onnextclk <= '0';
+				else
+					ram_writeenable <= '0';
+					read_valid <= '0';
+					write_onnextclk <= '0';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end architecture behavioral;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity blockram is
+	generic (
+		WIDTH	: natural := 16;
+		RANGEBITS	: natural := 24
+	);
+	port
+	(
+      reset : in  std_logic; 
+		clock : in std_logic;
+		write_enable : in std_logic;
+		address : in std_logic_vector(WIDTH-1 downto 0);
+		data_in : in std_logic_vector(RANGEBITS-1 downto 0);
+		data_out : out std_logic_vector(RANGEBITS-1 downto 0)
+	);
+end blockram;
+
+architecture behavioral of blockram is
+	type arrtype is array(0 TO 2**WIDTH - 1) of std_logic_vector(RANGEBITS-1 downto 0);
+	signal arr : arrtype;
+begin
+	process(clock)
+	begin
+		if rising_edge(clock) then
+			if (write_enable = '1') then
+			    arr(conv_integer(address)) <= data_in;
+			end if;
+			data_out <= arr(conv_integer(address));
+		end if;
+	end process;
+end behavioral;
\ No newline at end of file
diff --git a/data_concentrator/sources/lattice/async_fifo_16x32.vhd b/data_concentrator/sources/lattice/async_fifo_16x32.vhd
new file mode 100644
index 0000000..448ec06
--- /dev/null
+++ b/data_concentrator/sources/lattice/async_fifo_16x32.vhd
@@ -0,0 +1,51 @@
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+entity async_fifo_16x32 is
+port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(31 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(31 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic
+	);
+end async_fifo_16x32;
+
+architecture Behavioral of async_fifo_16x32 is
+
+component async_fifo_16x32_ecp3 is
+    port (
+        Data: in  std_logic_vector(31 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(31 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic);
+end component;
+
+begin
+
+async_fifo_16x32_ecp3_1: async_fifo_16x32_ecp3 port map(
+        Data => din,
+        WrClock => wr_clk,
+        RdClock => rd_clk,
+        WrEn => wr_en,
+        RdEn => rd_en,
+        Reset => rst,
+        RPReset => rst,
+        Q => dout,
+        Empty => empty,
+        Full => full);
+
+end Behavioral;
+
diff --git a/data_concentrator/sources/lattice/async_fifo_256x66.vhd b/data_concentrator/sources/lattice/async_fifo_256x66.vhd
new file mode 100644
index 0000000..ad05fbb
--- /dev/null
+++ b/data_concentrator/sources/lattice/async_fifo_256x66.vhd
@@ -0,0 +1,51 @@
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+entity async_fifo_256x66 is
+port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(65 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(65 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic
+	);
+end async_fifo_256x66;
+
+architecture Behavioral of async_fifo_256x66 is
+
+component async_fifo_256x66_ecp3 is
+    port (
+        Data: in  std_logic_vector(65 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(65 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic);
+end component;
+
+begin
+
+async_fifo_256x66_ecp3_1: async_fifo_256x66_ecp3 port map(
+        Data => din,
+        WrClock => wr_clk,
+        RdClock => rd_clk,
+        WrEn => wr_en,
+        RdEn => rd_en,
+        Reset => rst,
+        RPReset => rst,
+        Q => dout,
+        Empty => empty,
+        Full => full);
+
+end Behavioral;
+
diff --git a/data_concentrator/sources/lattice/async_fifo_512x32.vhd b/data_concentrator/sources/lattice/async_fifo_512x32.vhd
new file mode 100644
index 0000000..0bcb748
--- /dev/null
+++ b/data_concentrator/sources/lattice/async_fifo_512x32.vhd
@@ -0,0 +1,51 @@
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+entity async_fifo_512x32 is
+port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(31 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(31 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic
+	);
+end async_fifo_512x32;
+
+architecture Behavioral of async_fifo_512x32 is
+
+component async_fifo_512x32_ecp3 is
+    port (
+        Data: in  std_logic_vector(31 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(31 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic);
+end component;
+
+begin
+
+async_fifo_512x32_ecp3_1: async_fifo_512x32_ecp3 port map(
+        Data => din,
+        WrClock => wr_clk,
+        RdClock => rd_clk,
+        WrEn => wr_en,
+        RdEn => rd_en,
+        Reset => rst,
+        RPReset => rst,
+        Q => dout,
+        Empty => empty,
+        Full => full);
+
+end Behavioral;
+
diff --git a/data_concentrator/sources/lattice/async_fifo_512x99.vhd b/data_concentrator/sources/lattice/async_fifo_512x99.vhd
new file mode 100644
index 0000000..af81845
--- /dev/null
+++ b/data_concentrator/sources/lattice/async_fifo_512x99.vhd
@@ -0,0 +1,51 @@
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+entity async_fifo_512x99 is
+port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(98 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(98 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic
+	);
+end async_fifo_512x99;
+
+architecture Behavioral of async_fifo_512x99 is
+
+component async_fifo_512x99_ecp3 is
+    port (
+        Data: in  std_logic_vector(98 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(98 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic);
+end component;
+
+begin
+
+async_fifo_512x99_ecp3_1: async_fifo_512x99_ecp3 port map(
+        Data => din,
+        WrClock => wr_clk,
+        RdClock => rd_clk,
+        WrEn => wr_en,
+        RdEn => rd_en,
+        Reset => rst,
+        RPReset => rst,
+        Q => dout,
+        Empty => empty,
+        Full => full);
+
+end Behavioral;
+
diff --git a/data_concentrator/sources/lattice/async_fifo_FWFT_16x32.vhd b/data_concentrator/sources/lattice/async_fifo_FWFT_16x32.vhd
new file mode 100644
index 0000000..1967910
--- /dev/null
+++ b/data_concentrator/sources/lattice/async_fifo_FWFT_16x32.vhd
@@ -0,0 +1,109 @@
+-----------------------------------------------------------------------------------
+-- Wrapper for asynchronous FIFO : width 32, 8 deep
+-----------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY async_fifo_FWFT_16x32 IS
+	PORT
+	(
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(31 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(31 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic
+	);
+END async_fifo_FWFT_16x32;
+
+
+ARCHITECTURE Behavioral OF async_fifo_FWFT_16x32 IS
+component async_fifo_16x32_ecp3
+    port (
+        Data: in  std_logic_vector(31 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(31 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic);
+end component;
+
+signal fifo_dout                      : std_logic_vector (31 downto 0) := (others => '0');
+signal middle_dout                    : std_logic_vector (31 downto 0) := (others => '0');
+signal fifo_empty                     : std_logic := '0';
+signal will_update_middle             : std_logic := '0';
+signal will_update_dout               : std_logic := '0';
+signal middle_valid                   : std_logic := '0';
+signal fifo_valid                     : std_logic := '0';
+signal dout_valid                     : std_logic := '0';
+signal fifo_rd_en                     : std_logic := '0';
+
+
+begin
+
+async_fifo_FWFT_16x32_ecp3_1: async_fifo_16x32_ecp3 port map(
+		Data => din,
+		WrClock => wr_clk,
+		RdClock => rd_clk,
+		WrEn => wr_en,
+		RdEn => fifo_rd_en,
+		Reset => rst,
+        RPReset => rst,
+		Q => fifo_dout,
+		Empty => fifo_empty,
+		Full => full);
+
+		
+will_update_middle <= '1' when (fifo_valid='1') and  (middle_valid=will_update_dout) else '0';
+will_update_dout <= '1' when ((middle_valid='1') or  (fifo_valid='1')) and ((rd_en='1') or (dout_valid='0')) else '0';
+fifo_rd_en <= '1' when (fifo_empty='0') and (not ((middle_valid='1') and (dout_valid='1') and (fifo_valid='1'))) else '0';
+empty <= not dout_valid;
+	
+process (rd_clk)
+begin
+	if rising_edge(rd_clk) then
+		if rst='1' then
+			fifo_valid <= '0';
+			middle_valid <= '0';
+			dout_valid <= '0';
+			dout <= (others => '0');
+			middle_dout <= (others => '0');
+		else
+            if (will_update_middle='1') then
+               middle_dout <= fifo_dout;
+            end if;
+            if (will_update_dout='1') then
+				if middle_valid='1' then
+					dout <= middle_dout;
+				else
+					dout <= fifo_dout;
+				end if;
+            end if;
+            if (fifo_rd_en='1') then
+               fifo_valid <= '1';
+            elsif ((will_update_middle='1') or (will_update_dout='1')) then
+               fifo_valid <= '0';
+            end if;
+            if (will_update_middle='1') then
+               middle_valid <= '1';
+            elsif (will_update_dout='1') then
+               middle_valid <= '0';
+            end if;
+            if (will_update_dout='1') then
+               dout_valid <= '1';
+            elsif (rd_en='1') then
+               dout_valid <= '0';
+			end if;
+		end if;
+	end if;
+end process;
+
+end Behavioral;
diff --git a/data_concentrator/sources/lattice/async_fifo_FWFT_16x32_try1.vhd b/data_concentrator/sources/lattice/async_fifo_FWFT_16x32_try1.vhd
new file mode 100644
index 0000000..c0621a0
--- /dev/null
+++ b/data_concentrator/sources/lattice/async_fifo_FWFT_16x32_try1.vhd
@@ -0,0 +1,173 @@
+-----------------------------------------------------------------------------------
+-- Wrapper for asynchronous FIFO : width 32, 8 deep
+-----------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY async_fifo_FWFT_16x32 IS
+	PORT
+	(
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(31 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(31 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic
+	);
+END async_fifo_FWFT_16x32;
+
+
+ARCHITECTURE Behavioral OF async_fifo_FWFT_16x32 IS
+component async_fifo_16x32_ecp3
+    port (
+        Data: in  std_logic_vector(31 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(31 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic);
+end component;
+
+signal ff_data_out : std_logic_vector (31 DOWNTO 0) := (others => '0');
+signal ff_read_request : std_logic := '0';
+signal ff_read_request_i : std_logic := '0';
+signal ff_read_request_final : std_logic := '0';
+signal ff_empty : std_logic := '0';
+signal data_available_i : std_logic := '0';
+
+BEGIN
+-- data_available <= data_available_i;
+process (rd_clk)
+begin
+	if rising_edge(rd_clk) then
+		ff_read_request <= '0';
+		if rst='1' then
+			data_available_i <= '0';
+		else
+			if (ff_empty='0') and (data_available_i='0') and (rd_en='0') then
+				if ff_read_request_i='1' then
+					ff_read_request <= '0';
+					dout <= ff_data_out;
+					data_available_i <= '1';
+					empty <= '0';
+				else 
+					if ff_read_request='0' then
+						ff_read_request <= '1';
+					end if;
+					data_available_i <= '0';
+--					empty <= '0';
+				end if;
+			elsif (ff_empty='0') and (data_available_i='0') and (rd_en='1') then  -- ignore
+				if ff_read_request_i='1' then
+					ff_read_request <= '0';
+					dout <= ff_data_out;
+					data_available_i <= '1';
+					empty <= '0';
+				else 
+					ff_read_request <= '1';
+					data_available_i <= '0';
+--					empty <= '0';
+				end if;
+				
+			elsif (ff_empty='0') and (data_available_i='1') and (rd_en='0') then  
+				if ff_read_request_i='1' then -- should not occur
+					ff_read_request <= '0';
+					dout <= ff_data_out;
+					data_available_i <= '1';
+					empty <= '0';
+				else 
+					ff_read_request <= '0';
+					data_available_i <= '1';
+					empty <= '0';
+				end if;
+			elsif (ff_empty='0') and (data_available_i='1') and (rd_en='1') then  
+				if ff_read_request_i='1' then
+					ff_read_request <= '1';
+					dout <= ff_data_out;
+					data_available_i <= '1';
+					empty <= '0';
+				else 
+					ff_read_request <= '1';
+					data_available_i <= '0';
+					empty <= '0';
+				end if;
+
+			elsif (ff_empty='1') and (data_available_i='0') and (rd_en='0') then  
+				if ff_read_request_i='1' then
+					ff_read_request <= '0';
+					dout <= ff_data_out;
+					data_available_i <= '1';
+					empty <= '0';
+				else 
+					ff_read_request <= '0';
+					data_available_i <= '0';
+					empty <= '1';
+				end if;
+			elsif (ff_empty='1') and (data_available_i='0') and (rd_en='1') then -- ignore rd
+				if ff_read_request_i='1' then
+					ff_read_request <= '0';
+					dout <= ff_data_out;
+					data_available_i <= '1';
+					empty <= '0';
+				else 
+					ff_read_request <= '0';
+					data_available_i <= '0';
+					empty <= '1';
+				end if;
+
+			elsif (ff_empty='1') and (data_available_i='1') and (rd_en='0') then  
+				if ff_read_request_i='1' then
+					ff_read_request <= '0';
+					dout <= ff_data_out;
+					data_available_i <= '1';
+					empty <= '0';
+				else 
+					ff_read_request <= '0';
+					data_available_i <= '1';
+					empty <= '0';
+				end if;
+			elsif (ff_empty='1') and (data_available_i='1') and (rd_en='1') then  
+				if ff_read_request_i='1' then
+					ff_read_request <= '0';
+					dout <= ff_data_out;
+					data_available_i <= '1';
+					empty <= '0';
+				else 
+					ff_read_request <= '0';
+					data_available_i <= '0';
+					empty <= '1';
+				end if;
+			end if;
+		end if;
+		ff_read_request_i <= ff_read_request_final;
+	end if;
+end process;
+
+async_fifo_FWFT_16x32_ecp3_1: async_fifo_16x32_ecp3 port map(
+		Data => din,
+		WrClock => wr_clk,
+		RdClock => rd_clk,
+		WrEn => wr_en,
+		RdEn => ff_read_request_final,
+		Reset => rst,
+        RPReset => rst,
+		Q => ff_data_out,
+		Empty => ff_empty,
+		Full => full);
+
+ff_read_request_final <= '1' when
+	((rd_en='1') and (ff_empty='0') and (data_available_i='1')) or
+	((rd_en='0') and (ff_empty='0') and (data_available_i='0') and (ff_read_request_i='0'))
+	else '0';
+
+
+
+END Behavioral;
diff --git a/data_concentrator/sources/lattice/async_fifo_af_512x32.vhd b/data_concentrator/sources/lattice/async_fifo_af_512x32.vhd
new file mode 100644
index 0000000..68bb74e
--- /dev/null
+++ b/data_concentrator/sources/lattice/async_fifo_af_512x32.vhd
@@ -0,0 +1,54 @@
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+entity async_fifo_af_512x32 is
+port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(31 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(31 downto 0);
+		full                    : out std_logic;
+		almost_full             : out std_logic;
+		empty                   : out std_logic
+	);
+end async_fifo_af_512x32;
+
+architecture Behavioral of async_fifo_af_512x32 is
+
+component async_fifo_af_512x32_ecp3 is
+    port (
+        Data: in  std_logic_vector(31 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(31 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostFull: out  std_logic);
+end component;
+
+begin
+
+async_fifo_af_512x32_ecp3_1: async_fifo_af_512x32_ecp3 port map(
+        Data => din,
+        WrClock => wr_clk,
+        RdClock => rd_clk,
+        WrEn => wr_en,
+        RdEn => rd_en,
+        Reset => rst,
+        RPReset => rst,
+        Q => dout,
+        Empty => empty,
+        Full => full,
+        AlmostFull => almost_full);
+
+end Behavioral;
+
diff --git a/data_concentrator/sources/lattice/async_fifo_af_512x36.vhd b/data_concentrator/sources/lattice/async_fifo_af_512x36.vhd
new file mode 100644
index 0000000..1bca9ac
--- /dev/null
+++ b/data_concentrator/sources/lattice/async_fifo_af_512x36.vhd
@@ -0,0 +1,54 @@
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+entity async_fifo_af_512x36 is
+port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(35 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(35 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic;
+		prog_full               : out std_logic
+	);
+end async_fifo_af_512x36;
+
+architecture Behavioral of async_fifo_af_512x36 is
+
+component async_fifo_af_512x36_ecp3 is
+    port (
+        Data: in  std_logic_vector(35 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(35 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostFull: out  std_logic);
+end component;
+
+begin
+
+async_fifo_af_512x36_ecp3_1: async_fifo_af_512x36_ecp3 port map(
+        Data => din,
+        WrClock => wr_clk,
+        RdClock => rd_clk,
+        WrEn => wr_en,
+        RdEn => rd_en,
+        Reset => rst,
+        RPReset => rst,
+        Q => dout,
+        Empty => empty,
+        Full => full,
+        AlmostFull => prog_full);
+
+end Behavioral;
+
diff --git a/data_concentrator/sources/lattice/async_fifo_nn_16384x36.vhd b/data_concentrator/sources/lattice/async_fifo_nn_16384x36.vhd
new file mode 100644
index 0000000..5c4cfb2
--- /dev/null
+++ b/data_concentrator/sources/lattice/async_fifo_nn_16384x36.vhd
@@ -0,0 +1,55 @@
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+entity async_fifo_nn_16384x36 is
+port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(35 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(35 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic;
+		rd_data_count           : out std_logic_vector(13 downto 0)
+	);
+end async_fifo_nn_16384x36;
+
+architecture Behavioral of async_fifo_nn_16384x36 is
+
+component async_fifo_nn_16384x36_ecp3 is
+    port (
+        Data: in  std_logic_vector(35 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(35 downto 0); 
+        RCNT: out  std_logic_vector(14 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic);
+end component;
+signal rd_data_count_i : std_logic_vector(14 downto 0); 
+begin
+
+async_fifo_nn_16384x36_ecp3_1: async_fifo_nn_16384x36_ecp3 port map(
+        Data => din,
+        WrClock => wr_clk,
+        RdClock => rd_clk,
+        WrEn => wr_en,
+        RdEn => rd_en,
+        Reset => rst,
+        RPReset => rst,
+        Q => dout,
+        RCNT => rd_data_count_i,
+        Empty => empty,
+        Full => full);
+rd_data_count <= (others => '1') when rd_data_count_i(14)='1' else rd_data_count_i(13 downto 0);
+
+end Behavioral;
+
diff --git a/data_concentrator/sources/lattice/async_fifo_nn_4096x103.vhd b/data_concentrator/sources/lattice/async_fifo_nn_4096x103.vhd
new file mode 100644
index 0000000..861f29e
--- /dev/null
+++ b/data_concentrator/sources/lattice/async_fifo_nn_4096x103.vhd
@@ -0,0 +1,55 @@
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+entity async_fifo_nn_4096x103 is
+port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(102 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(102 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic;
+		rd_data_count           : out std_logic_vector(11 downto 0)
+	);
+end async_fifo_nn_4096x103;
+
+architecture Behavioral of async_fifo_nn_4096x103 is
+
+component async_fifo_nn_4096x103_ecp3 is
+    port (
+        Data: in  std_logic_vector(102 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(102 downto 0); 
+        WCNT: out  std_logic_vector(12 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic);
+end component;
+signal rd_data_count_i : std_logic_vector(12 downto 0); 
+begin
+
+async_fifo_nn_4096x103_ecp3_1: async_fifo_nn_4096x103_ecp3 port map(
+        Data => din,
+        WrClock => wr_clk,
+        RdClock => rd_clk,
+        WrEn => wr_en,
+        RdEn => rd_en,
+        Reset => rst,
+        RPReset => rst,
+        Q => dout,
+        WCNT => rd_data_count_i,
+        Empty => empty,
+        Full => full);
+rd_data_count <= (others => '1') when rd_data_count_i(12)='1' else rd_data_count_i(11 downto 0);
+
+end Behavioral;
+
diff --git a/data_concentrator/sources/lattice/async_fifo_nn_4096x36.vhd b/data_concentrator/sources/lattice/async_fifo_nn_4096x36.vhd
new file mode 100644
index 0000000..8f47b22
--- /dev/null
+++ b/data_concentrator/sources/lattice/async_fifo_nn_4096x36.vhd
@@ -0,0 +1,55 @@
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+entity async_fifo_nn_4096x36 is
+port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(35 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(35 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic;
+		rd_data_count           : out std_logic_vector(11 downto 0)
+	);
+end async_fifo_nn_4096x36;
+
+architecture Behavioral of async_fifo_nn_4096x36 is
+
+component async_fifo_nn_4096x36_ecp3 is
+    port (
+        Data: in  std_logic_vector(35 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(35 downto 0); 
+        WCNT: out  std_logic_vector(12 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic);
+end component;
+signal rd_data_count_i : std_logic_vector(12 downto 0); 
+begin
+
+async_fifo_nn_4096x36_ecp3_1: async_fifo_nn_4096x36_ecp3 port map(
+        Data => din,
+        WrClock => wr_clk,
+        RdClock => rd_clk,
+        WrEn => wr_en,
+        RdEn => rd_en,
+        Reset => rst,
+        RPReset => rst,
+        Q => dout,
+        WCNT => rd_data_count_i,
+        Empty => empty,
+        Full => full);
+rd_data_count <= (others => '1') when rd_data_count_i(12)='1' else rd_data_count_i(11 downto 0);
+
+end Behavioral;
+
diff --git a/data_concentrator/sources/lattice/async_fifo_nn_th_512x36.vhd b/data_concentrator/sources/lattice/async_fifo_nn_th_512x36.vhd
new file mode 100644
index 0000000..a0bedbf
--- /dev/null
+++ b/data_concentrator/sources/lattice/async_fifo_nn_th_512x36.vhd
@@ -0,0 +1,58 @@
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+entity async_fifo_nn_th_512x36 is
+port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(35 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(35 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic;
+		rd_data_count           : out std_logic_vector(8 downto 0);
+		prog_empty              : out std_logic
+	);
+end async_fifo_nn_th_512x36;
+
+architecture Behavioral of async_fifo_nn_th_512x36 is
+
+component async_fifo_nn_th_512x36_ecp3 is
+    port (
+        Data: in  std_logic_vector(35 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(35 downto 0); 
+        RCNT: out  std_logic_vector(9 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostEmpty: out  std_logic);
+end component;
+signal rd_data_count_i : std_logic_vector(9 downto 0); 
+begin
+
+async_fifo_nn_th_512x36_ecp3_1: async_fifo_nn_th_512x36_ecp3 port map(
+        Data => din,
+        WrClock => wr_clk,
+        RdClock => rd_clk,
+        WrEn => wr_en,
+        RdEn => rd_en,
+        Reset => rst,
+        RPReset => rst,
+        Q => dout,
+        RCNT => rd_data_count_i,
+        Empty => empty,
+        Full => full,
+        AlmostEmpty => prog_empty);
+rd_data_count <= (others => '1') when rd_data_count_i(9)='1' else rd_data_count_i(8 downto 0);
+
+end Behavioral;
+
diff --git a/data_concentrator/sources/lattice/async_fifo_nn_thfull_FWFT_512x36.vhd b/data_concentrator/sources/lattice/async_fifo_nn_thfull_FWFT_512x36.vhd
new file mode 100644
index 0000000..26fb356
--- /dev/null
+++ b/data_concentrator/sources/lattice/async_fifo_nn_thfull_FWFT_512x36.vhd
@@ -0,0 +1,116 @@
+-----------------------------------------------------------------------------------
+-- Wrapper for asynchronous FIFO : width 32, 8 deep
+-----------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY async_fifo_nn_thfull_FWFT_512x36 IS
+	PORT
+	(
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(35 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(35 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic;
+		rd_data_count           : out std_logic_vector(8 downto 0);
+		prog_full               : out std_logic
+	);
+END async_fifo_nn_thfull_FWFT_512x36;
+
+
+ARCHITECTURE Behavioral OF async_fifo_nn_thfull_FWFT_512x36 IS
+component async_fifo_nn_thfull_512x36_ecp3
+    port (
+        Data: in  std_logic_vector(35 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(35 downto 0); 
+        RCNT: out  std_logic_vector(9 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostFull: out  std_logic);
+end component;
+
+
+signal fifo_dout                      : std_logic_vector (35 downto 0) := (others => '0');
+signal middle_dout                    : std_logic_vector (35 downto 0) := (others => '0');
+signal rd_data_count_i                : std_logic_vector (9 downto 0) := (others => '0');
+signal fifo_empty                     : std_logic := '0';
+signal will_update_middle             : std_logic := '0';
+signal will_update_dout               : std_logic := '0';
+signal middle_valid                   : std_logic := '0';
+signal fifo_valid                     : std_logic := '0';
+signal dout_valid                     : std_logic := '0';
+signal fifo_rd_en                     : std_logic := '0';
+
+begin
+	
+async_fifo_nn_thfull_512x36_ecp3_1: async_fifo_nn_thfull_512x36_ecp3 port map(
+		Data => din,
+		WrClock => wr_clk,
+		RdClock => rd_clk,
+		WrEn => wr_en,
+		RdEn => fifo_rd_en,
+		Reset => rst,
+        RPReset => rst,
+		Q => fifo_dout,
+        RCNT => rd_data_count_i, 
+		Empty => fifo_empty,
+		Full => full,
+        AlmostFull => prog_full);
+rd_data_count <= (others => '1') when rd_data_count_i(9)='1' else rd_data_count_i(8 downto 0);
+ 
+will_update_middle <= '1' when (fifo_valid='1') and  (middle_valid=will_update_dout) else '0';
+will_update_dout <= '1' when ((middle_valid='1') or  (fifo_valid='1')) and ((rd_en='1') or (dout_valid='0')) else '0';
+fifo_rd_en <= '1' when (fifo_empty='0') and (not ((middle_valid='1') and (dout_valid='1') and (fifo_valid='1'))) else '0';
+empty <= not dout_valid;
+	
+process (rd_clk)
+begin
+	if rising_edge(rd_clk) then
+		if rst='1' then
+			fifo_valid <= '0';
+			middle_valid <= '0';
+			dout_valid <= '0';
+			dout <= (others => '0');
+			middle_dout <= (others => '0');
+		else
+            if (will_update_middle='1') then
+               middle_dout <= fifo_dout;
+            end if;
+            if (will_update_dout='1') then
+				if middle_valid='1' then
+					dout <= middle_dout;
+				else
+					dout <= fifo_dout;
+				end if;
+            end if;
+            if (fifo_rd_en='1') then
+               fifo_valid <= '1';
+            elsif ((will_update_middle='1') or (will_update_dout='1')) then
+               fifo_valid <= '0';
+            end if;
+            if (will_update_middle='1') then
+               middle_valid <= '1';
+            elsif (will_update_dout='1') then
+               middle_valid <= '0';
+            end if;
+            if (will_update_dout='1') then
+               dout_valid <= '1';
+            elsif (rd_en='1') then
+               dout_valid <= '0';
+			end if;
+		end if;
+	end if;
+end process;
+
+end Behavioral;
diff --git a/data_concentrator/sources/lattice/async_fifo_nn_thfull_FWFT_512x36_try1.vhd b/data_concentrator/sources/lattice/async_fifo_nn_thfull_FWFT_512x36_try1.vhd
new file mode 100644
index 0000000..c5b1f83
--- /dev/null
+++ b/data_concentrator/sources/lattice/async_fifo_nn_thfull_FWFT_512x36_try1.vhd
@@ -0,0 +1,181 @@
+-----------------------------------------------------------------------------------
+-- Wrapper for asynchronous FIFO : width 32, 8 deep
+-----------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY async_fifo_nn_thfull_FWFT_512x36 IS
+	PORT
+	(
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(35 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(35 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic;
+		rd_data_count           : out std_logic_vector(8 downto 0);
+		prog_full               : out std_logic
+	);
+END async_fifo_nn_thfull_FWFT_512x36;
+
+
+ARCHITECTURE Behavioral OF async_fifo_nn_thfull_FWFT_512x36 IS
+component async_fifo_nn_thfull_512x36_ecp3
+    port (
+        Data: in  std_logic_vector(35 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(35 downto 0); 
+        RCNT: out  std_logic_vector(9 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostFull: out  std_logic);
+end component;
+
+signal ff_data_out : std_logic_vector (35 DOWNTO 0) := (others => '0');
+signal ff_read_request : std_logic := '0';
+signal ff_read_request_i : std_logic := '0';
+signal ff_read_request_final : std_logic := '0';
+signal ff_empty : std_logic := '0';
+signal data_available_i : std_logic := '0';
+signal rd_data_count_i : std_logic_vector (9 DOWNTO 0) := (others => '0');
+
+BEGIN
+-- data_available <= data_available_i;
+process (rd_clk)
+begin
+	if rising_edge(rd_clk) then
+		ff_read_request <= '0';
+		if rst='1' then
+			data_available_i <= '0';
+		else
+			if (ff_empty='0') and (data_available_i='0') and (rd_en='0') then
+				if ff_read_request_i='1' then
+					ff_read_request <= '0';
+					dout <= ff_data_out;
+					data_available_i <= '1';
+					empty <= '0';
+				else 
+					if ff_read_request='0' then
+						ff_read_request <= '1';
+					end if;
+					data_available_i <= '0';
+--					empty <= '0';
+				end if;
+			elsif (ff_empty='0') and (data_available_i='0') and (rd_en='1') then  -- ignore
+				if ff_read_request_i='1' then
+					ff_read_request <= '0';
+					dout <= ff_data_out;
+					data_available_i <= '1';
+					empty <= '0';
+				else 
+					ff_read_request <= '1';
+					data_available_i <= '0';
+--					empty <= '0';
+				end if;
+				
+			elsif (ff_empty='0') and (data_available_i='1') and (rd_en='0') then  
+				if ff_read_request_i='1' then -- should not occur
+					ff_read_request <= '0';
+					dout <= ff_data_out;
+					data_available_i <= '1';
+					empty <= '0';
+				else 
+					ff_read_request <= '0';
+					data_available_i <= '1';
+					empty <= '0';
+				end if;
+			elsif (ff_empty='0') and (data_available_i='1') and (rd_en='1') then  
+				if ff_read_request_i='1' then
+					ff_read_request <= '1';
+					dout <= ff_data_out;
+					data_available_i <= '1';
+					empty <= '0';
+				else 
+					ff_read_request <= '1';
+					data_available_i <= '0';
+					empty <= '0';
+				end if;
+
+			elsif (ff_empty='1') and (data_available_i='0') and (rd_en='0') then  
+				if ff_read_request_i='1' then
+					ff_read_request <= '0';
+					dout <= ff_data_out;
+					data_available_i <= '1';
+					empty <= '0';
+				else 
+					ff_read_request <= '0';
+					data_available_i <= '0';
+					empty <= '1';
+				end if;
+			elsif (ff_empty='1') and (data_available_i='0') and (rd_en='1') then -- ignore rd
+				if ff_read_request_i='1' then
+					ff_read_request <= '0';
+					dout <= ff_data_out;
+					data_available_i <= '1';
+					empty <= '0';
+				else 
+					ff_read_request <= '0';
+					data_available_i <= '0';
+					empty <= '1';
+				end if;
+
+			elsif (ff_empty='1') and (data_available_i='1') and (rd_en='0') then  
+				if ff_read_request_i='1' then
+					ff_read_request <= '0';
+					dout <= ff_data_out;
+					data_available_i <= '1';
+					empty <= '0';
+				else 
+					ff_read_request <= '0';
+					data_available_i <= '1';
+					empty <= '0';
+				end if;
+			elsif (ff_empty='1') and (data_available_i='1') and (rd_en='1') then  
+				if ff_read_request_i='1' then
+					ff_read_request <= '0';
+					dout <= ff_data_out;
+					data_available_i <= '1';
+					empty <= '0';
+				else 
+					ff_read_request <= '0';
+					data_available_i <= '0';
+					empty <= '1';
+				end if;
+			end if;
+		end if;
+		ff_read_request_i <= ff_read_request_final;
+	end if;
+end process;
+
+async_fifo_nn_thfull_512x36_ecp3_1: async_fifo_nn_thfull_512x36_ecp3 port map(
+		Data => din,
+		WrClock => wr_clk,
+		RdClock => rd_clk,
+		WrEn => wr_en,
+		RdEn => ff_read_request_final,
+		Reset => rst,
+        RPReset => rst,
+		Q => ff_data_out,
+        RCNT => rd_data_count_i, 
+		Empty => ff_empty,
+		Full => full,
+        AlmostFull => prog_full);
+rd_data_count <= (others => '1') when rd_data_count_i(9)='1' else rd_data_count_i(8 downto 0);
+
+ff_read_request_final <= '1' when
+	((rd_en='1') and (ff_empty='0') and (data_available_i='1')) or
+	((rd_en='0') and (ff_empty='0') and (data_available_i='0') and (ff_read_request_i='0'))
+	else '0';
+
+
+
+END Behavioral;
diff --git a/data_concentrator/sources/lattice/async_fifo_nn_thfull_FWFT_512x36_try2.vhd b/data_concentrator/sources/lattice/async_fifo_nn_thfull_FWFT_512x36_try2.vhd
new file mode 100644
index 0000000..70597b1
--- /dev/null
+++ b/data_concentrator/sources/lattice/async_fifo_nn_thfull_FWFT_512x36_try2.vhd
@@ -0,0 +1,117 @@
+-----------------------------------------------------------------------------------
+-- Wrapper for asynchronous FIFO : width 32, 8 deep
+-----------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY async_fifo_nn_thfull_FWFT_512x36 IS
+	PORT
+	(
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(35 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(35 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic;
+		rd_data_count           : out std_logic_vector(8 downto 0);
+		prog_full               : out std_logic
+	);
+END async_fifo_nn_thfull_FWFT_512x36;
+
+
+ARCHITECTURE Behavioral OF async_fifo_nn_thfull_FWFT_512x36 IS
+component async_fifo_nn_thfull_512x36_ecp3
+    port (
+        Data: in  std_logic_vector(35 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(35 downto 0); 
+        RCNT: out  std_logic_vector(9 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostFull: out  std_logic);
+end component;
+
+
+signal fifo_dout                      : std_logic_vector (35 downto 0) := (others => '0');
+signal middle_dout                    : std_logic_vector (35 downto 0) := (others => '0');
+signal rd_data_count_i                : std_logic_vector (9 downto 0) := (others => '0');
+signal fifo_empty                     : std_logic := '0';
+signal will_update_middle             : std_logic := '0';
+signal will_update_dout               : std_logic := '0';
+signal middle_valid                   : std_logic := '0';
+signal fifo_valid                     : std_logic := '0';
+signal dout_valid                     : std_logic := '0';
+signal fifo_rd_en                     : std_logic := '0';
+
+
+BEGIN
+	   
+async_fifo_nn_thfull_512x36_ecp3_1: async_fifo_nn_thfull_512x36_ecp3 port map(
+		Data => din,
+		WrClock => wr_clk,
+		RdClock => rd_clk,
+		WrEn => wr_en,
+		RdEn => fifo_rd_en,
+		Reset => rst,
+        RPReset => rst,
+		Q => fifo_dout,
+        RCNT => rd_data_count_i, 
+		Empty => fifo_empty,
+		Full => full,
+        AlmostFull => prog_full);
+rd_data_count <= (others => '1') when rd_data_count_i(9)='1' else rd_data_count_i(8 downto 0);
+   
+will_update_middle <= '1' when (fifo_valid='1') and  (middle_valid=will_update_dout) else '0';
+will_update_dout <= '1' when ((middle_valid='1') or  (fifo_valid='1')) and ((rd_en='1') and (dout_valid='0')) else '0';
+fifo_rd_en <= '1' when (fifo_empty='0') and (not (((middle_valid='1') and (dout_valid='1') and (fifo_valid='1')))) else '0';
+empty <= not dout_valid;
+
+process (rd_clk)
+begin
+	if rising_edge(rd_clk) then
+		if rst='1' then
+			fifo_valid <= '0';
+			middle_valid <= '0';
+			dout_valid <= '0';
+			dout <= (others => '0');
+			middle_dout <= (others => '0');
+		else
+            if (will_update_middle='1') then
+               middle_dout <= fifo_dout;
+            end if;
+            if (will_update_dout='1') then
+				if middle_valid='1' then
+					dout <= middle_dout;
+				else
+					dout <= fifo_dout;
+				end if;
+            end if;
+            if (fifo_rd_en='1') then
+               fifo_valid <= '1';
+            elsif ((will_update_middle='1') or (will_update_dout='1')) then
+               fifo_valid <= '0';
+            end if;
+            if (will_update_middle='1') then
+               middle_valid <= '1';
+            elsif (will_update_dout='1') then
+               middle_valid <= '0';
+            end if;
+            if (will_update_dout='1') then
+               dout_valid <= '1';
+            elsif (rd_en='1') then
+               dout_valid <= '0';
+			end if;
+		end if;
+	end if;
+end process;
+
+END Behavioral;
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_16x32_ecp3.ipx b/data_concentrator/sources/lattice/ecp3/async_fifo_16x32_ecp3.ipx
new file mode 100644
index 0000000..850f529
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_16x32_ecp3.ipx
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="async_fifo_16x32_ecp3" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 07 10 08:38:34.140" version="5.5" type="Module" synthesis="" source_format="VHDL">
+  <Package>
+		<File name="async_fifo_16x32_ecp3.lpc" type="lpc" modified="2014 07 10 08:38:32.149"/>
+		<File name="async_fifo_16x32_ecp3.vhd" type="top_level_vhdl" modified="2014 07 10 08:38:32.245"/>
+		<File name="async_fifo_16x32_ecp3_tmpl.vhd" type="template_vhdl" modified="2014 07 10 08:38:32.246"/>
+		<File name="tb_async_fifo_16x32_ecp3_tmpl.vhd" type="testbench_vhdl" modified="2014 07 10 08:38:32.250"/>
+  </Package>
+</DiamondModule>
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_16x32_ecp3.lpc b/data_concentrator/sources/lattice/ecp3/async_fifo_16x32_ecp3.lpc
new file mode 100644
index 0000000..e72cd2c
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_16x32_ecp3.lpc
@@ -0,0 +1,47 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.5
+ModuleName=async_fifo_16x32_ecp3
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=07/10/2014
+Time=08:38:32
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=16
+Width=32
+RDepth=16
+RWidth=32
+regout=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=0
+WDataCount=0
+EnECC=0
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_16x32_ecp3.vhd b/data_concentrator/sources/lattice/ecp3/async_fifo_16x32_ecp3.vhd
new file mode 100644
index 0000000..6d1c3ff
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_16x32_ecp3.vhd
@@ -0,0 +1,748 @@
+-- VHDL netlist generated by SCUBA Diamond_2.2_Production (99)
+-- Module  Version: 5.5
+--C:\Lattice\diamond\2.2_x64\ispfpga\bin\nt64\scuba.exe -w -n async_fifo_16x32_ecp3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 16 -width 32 -depth 16 -rdata_width 32 -no_enable -pe -1 -pf -1 -e 
+
+-- Thu Jul 10 08:38:32 2014
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity async_fifo_16x32_ecp3 is
+    port (
+        Data: in  std_logic_vector(31 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(31 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic);
+end async_fifo_16x32_ecp3;
+
+architecture Structure of async_fifo_16x32_ecp3 is
+
+    -- internal signal declarations
+    signal invout_1: std_logic;
+    signal invout_0: std_logic;
+    signal w_gdata_0: std_logic;
+    signal w_gdata_1: std_logic;
+    signal w_gdata_2: std_logic;
+    signal w_gdata_3: std_logic;
+    signal wptr_0: std_logic;
+    signal wptr_1: std_logic;
+    signal wptr_2: std_logic;
+    signal wptr_3: std_logic;
+    signal wptr_4: std_logic;
+    signal r_gdata_0: std_logic;
+    signal r_gdata_1: std_logic;
+    signal r_gdata_2: std_logic;
+    signal r_gdata_3: std_logic;
+    signal rptr_0: std_logic;
+    signal rptr_1: std_logic;
+    signal rptr_2: std_logic;
+    signal rptr_3: std_logic;
+    signal rptr_4: std_logic;
+    signal w_gcount_0: std_logic;
+    signal w_gcount_1: std_logic;
+    signal w_gcount_2: std_logic;
+    signal w_gcount_3: std_logic;
+    signal w_gcount_4: std_logic;
+    signal r_gcount_0: std_logic;
+    signal r_gcount_1: std_logic;
+    signal r_gcount_2: std_logic;
+    signal r_gcount_3: std_logic;
+    signal r_gcount_4: std_logic;
+    signal w_gcount_r20: std_logic;
+    signal w_gcount_r0: std_logic;
+    signal w_gcount_r21: std_logic;
+    signal w_gcount_r1: std_logic;
+    signal w_gcount_r22: std_logic;
+    signal w_gcount_r2: std_logic;
+    signal w_gcount_r23: std_logic;
+    signal w_gcount_r3: std_logic;
+    signal w_gcount_r24: std_logic;
+    signal w_gcount_r4: std_logic;
+    signal r_gcount_w20: std_logic;
+    signal r_gcount_w0: std_logic;
+    signal r_gcount_w21: std_logic;
+    signal r_gcount_w1: std_logic;
+    signal r_gcount_w22: std_logic;
+    signal r_gcount_w2: std_logic;
+    signal r_gcount_w23: std_logic;
+    signal r_gcount_w3: std_logic;
+    signal r_gcount_w24: std_logic;
+    signal r_gcount_w4: std_logic;
+    signal empty_i: std_logic;
+    signal rRst: std_logic;
+    signal full_i: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_gctr_ci: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co0: std_logic;
+    signal iwcount_4: std_logic;
+    signal co2: std_logic;
+    signal co1: std_logic;
+    signal wcount_4: std_logic;
+    signal scuba_vhi: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_gctr_ci: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co0_1: std_logic;
+    signal ircount_4: std_logic;
+    signal co2_1: std_logic;
+    signal co1_1: std_logic;
+    signal rcount_4: std_logic;
+    signal rden_i: std_logic;
+    signal cmp_ci: std_logic;
+    signal wcount_r0: std_logic;
+    signal w_g2b_xor_cluster_0: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal co0_2: std_logic;
+    signal wcount_r2: std_logic;
+    signal wcount_r3: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal co1_2: std_logic;
+    signal empty_cmp_clr: std_logic;
+    signal empty_cmp_set: std_logic;
+    signal empty_d: std_logic;
+    signal empty_d_c: std_logic;
+    signal wren_i: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal rcount_w0: std_logic;
+    signal r_g2b_xor_cluster_0: std_logic;
+    signal wcount_0: std_logic;
+    signal wcount_1: std_logic;
+    signal co0_3: std_logic;
+    signal rcount_w2: std_logic;
+    signal rcount_w3: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_3: std_logic;
+    signal co1_3: std_logic;
+    signal full_cmp_clr: std_logic;
+    signal full_cmp_set: std_logic;
+    signal full_d: std_logic;
+    signal full_d_c: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component AGEB2
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; GE: out  std_logic);
+    end component;
+    component AND2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component CU2
+        port (CI: in  std_logic; PC0: in  std_logic; PC1: in  std_logic; 
+            CO: out  std_logic; NC0: out  std_logic; NC1: out  std_logic);
+    end component;
+    component FADD2B
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; COUT: out  std_logic; 
+            S0: out  std_logic; S1: out  std_logic);
+    end component;
+    component FD1P3BX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            PD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1P3DX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            CD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1S3BX
+        port (D: in  std_logic; CK: in  std_logic; PD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component FD1S3DX
+        port (D: in  std_logic; CK: in  std_logic; CD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component INV
+        port (A: in  std_logic; Z: out  std_logic);
+    end component;
+    component OR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component ROM16X1A
+        generic (INITVAL : in std_logic_vector(15 downto 0));
+        port (AD3: in  std_logic; AD2: in  std_logic; AD1: in  std_logic; 
+            AD0: in  std_logic; DO0: out  std_logic);
+    end component;
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component XOR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component PDPW16KC
+        generic (GSR : in String; CSDECODE_R : in String; 
+                CSDECODE_W : in String; REGMODE : in String; 
+                DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+        port (DI0: in  std_logic; DI1: in  std_logic; DI2: in  std_logic; 
+            DI3: in  std_logic; DI4: in  std_logic; DI5: in  std_logic; 
+            DI6: in  std_logic; DI7: in  std_logic; DI8: in  std_logic; 
+            DI9: in  std_logic; DI10: in  std_logic; DI11: in  std_logic; 
+            DI12: in  std_logic; DI13: in  std_logic; 
+            DI14: in  std_logic; DI15: in  std_logic; 
+            DI16: in  std_logic; DI17: in  std_logic; 
+            DI18: in  std_logic; DI19: in  std_logic; 
+            DI20: in  std_logic; DI21: in  std_logic; 
+            DI22: in  std_logic; DI23: in  std_logic; 
+            DI24: in  std_logic; DI25: in  std_logic; 
+            DI26: in  std_logic; DI27: in  std_logic; 
+            DI28: in  std_logic; DI29: in  std_logic; 
+            DI30: in  std_logic; DI31: in  std_logic; 
+            DI32: in  std_logic; DI33: in  std_logic; 
+            DI34: in  std_logic; DI35: in  std_logic; 
+            ADW0: in  std_logic; ADW1: in  std_logic; 
+            ADW2: in  std_logic; ADW3: in  std_logic; 
+            ADW4: in  std_logic; ADW5: in  std_logic; 
+            ADW6: in  std_logic; ADW7: in  std_logic; 
+            ADW8: in  std_logic; BE0: in  std_logic; BE1: in  std_logic; 
+            BE2: in  std_logic; BE3: in  std_logic; CEW: in  std_logic; 
+            CLKW: in  std_logic; CSW0: in  std_logic; 
+            CSW1: in  std_logic; CSW2: in  std_logic; 
+            ADR0: in  std_logic; ADR1: in  std_logic; 
+            ADR2: in  std_logic; ADR3: in  std_logic; 
+            ADR4: in  std_logic; ADR5: in  std_logic; 
+            ADR6: in  std_logic; ADR7: in  std_logic; 
+            ADR8: in  std_logic; ADR9: in  std_logic; 
+            ADR10: in  std_logic; ADR11: in  std_logic; 
+            ADR12: in  std_logic; ADR13: in  std_logic; 
+            CER: in  std_logic; CLKR: in  std_logic; CSR0: in  std_logic; 
+            CSR1: in  std_logic; CSR2: in  std_logic; RST: in  std_logic; 
+            DO0: out  std_logic; DO1: out  std_logic; 
+            DO2: out  std_logic; DO3: out  std_logic; 
+            DO4: out  std_logic; DO5: out  std_logic; 
+            DO6: out  std_logic; DO7: out  std_logic; 
+            DO8: out  std_logic; DO9: out  std_logic; 
+            DO10: out  std_logic; DO11: out  std_logic; 
+            DO12: out  std_logic; DO13: out  std_logic; 
+            DO14: out  std_logic; DO15: out  std_logic; 
+            DO16: out  std_logic; DO17: out  std_logic; 
+            DO18: out  std_logic; DO19: out  std_logic; 
+            DO20: out  std_logic; DO21: out  std_logic; 
+            DO22: out  std_logic; DO23: out  std_logic; 
+            DO24: out  std_logic; DO25: out  std_logic; 
+            DO26: out  std_logic; DO27: out  std_logic; 
+            DO28: out  std_logic; DO29: out  std_logic; 
+            DO30: out  std_logic; DO31: out  std_logic; 
+            DO32: out  std_logic; DO33: out  std_logic; 
+            DO34: out  std_logic; DO35: out  std_logic);
+    end component;
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute RESETMODE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "async_fifo_16x32_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+    attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
+    attribute GSR of FF_51 : label is "ENABLED";
+    attribute GSR of FF_50 : label is "ENABLED";
+    attribute GSR of FF_49 : label is "ENABLED";
+    attribute GSR of FF_48 : label is "ENABLED";
+    attribute GSR of FF_47 : label is "ENABLED";
+    attribute GSR of FF_46 : label is "ENABLED";
+    attribute GSR of FF_45 : label is "ENABLED";
+    attribute GSR of FF_44 : label is "ENABLED";
+    attribute GSR of FF_43 : label is "ENABLED";
+    attribute GSR of FF_42 : label is "ENABLED";
+    attribute GSR of FF_41 : label is "ENABLED";
+    attribute GSR of FF_40 : label is "ENABLED";
+    attribute GSR of FF_39 : label is "ENABLED";
+    attribute GSR of FF_38 : label is "ENABLED";
+    attribute GSR of FF_37 : label is "ENABLED";
+    attribute GSR of FF_36 : label is "ENABLED";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t10: AND2
+        port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+    INV_1: INV
+        port map (A=>full_i, Z=>invout_1);
+
+    AND2_t9: AND2
+        port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+    INV_0: INV
+        port map (A=>empty_i, Z=>invout_0);
+
+    OR2_t8: OR2
+        port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+    XOR2_t7: XOR2
+        port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+    XOR2_t6: XOR2
+        port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+    XOR2_t5: XOR2
+        port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+    XOR2_t4: XOR2
+        port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+    XOR2_t3: XOR2
+        port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+    XOR2_t2: XOR2
+        port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+    XOR2_t1: XOR2
+        port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+    XOR2_t0: XOR2
+        port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+    LUT4_11: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, 
+            AD1=>w_gcount_r23, AD0=>w_gcount_r24, 
+            DO0=>w_g2b_xor_cluster_0);
+
+    LUT4_10: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>wcount_r3);
+
+    LUT4_9: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, 
+            AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r2);
+
+    LUT4_8: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, 
+            AD1=>w_gcount_r22, AD0=>wcount_r3, DO0=>wcount_r0);
+
+    LUT4_7: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, 
+            AD1=>r_gcount_w23, AD0=>r_gcount_w24, 
+            DO0=>r_g2b_xor_cluster_0);
+
+    LUT4_6: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>rcount_w3);
+
+    LUT4_5: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, 
+            AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w2);
+
+    LUT4_4: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, 
+            AD1=>r_gcount_w22, AD0=>rcount_w3, DO0=>rcount_w0);
+
+    LUT4_3: ROM16X1A
+        generic map (initval=> X"0410")
+        port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+    LUT4_2: ROM16X1A
+        generic map (initval=> X"1004")
+        port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"0140")
+        port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24, 
+            AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"4001")
+        port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24, 
+            AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+    pdp_ram_0_0_0: PDPW16KC
+        generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", 
+        REGMODE=> "NOREG", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
+        port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), 
+            DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), 
+            DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), 
+            DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), 
+            DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), 
+            DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), 
+            DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), 
+            DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), 
+            DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), 
+            DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo, 
+            DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, 
+            ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, 
+            ADW4=>scuba_vlo, ADW5=>scuba_vlo, ADW6=>scuba_vlo, 
+            ADW7=>scuba_vlo, ADW8=>scuba_vlo, BE0=>scuba_vhi, 
+            BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, 
+            CLKW=>WrClock, CSW0=>scuba_vhi, CSW1=>scuba_vlo, 
+            CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo, 
+            ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo, 
+            ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, ADR8=>rptr_3, 
+            ADR9=>scuba_vlo, ADR10=>scuba_vlo, ADR11=>scuba_vlo, 
+            ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>rden_i, 
+            CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, 
+            CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19), 
+            DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), 
+            DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), 
+            DO12=>Q(30), DO13=>Q(31), DO14=>open, DO15=>open, DO16=>open, 
+            DO17=>open, DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), 
+            DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), 
+            DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), 
+            DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), 
+            DO35=>Q(17));
+
+    FF_51: FD1P3BX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>wcount_0);
+
+    FF_50: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_49: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_48: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_47: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_46: FD1P3DX
+        port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_0);
+
+    FF_45: FD1P3DX
+        port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_1);
+
+    FF_44: FD1P3DX
+        port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_2);
+
+    FF_43: FD1P3DX
+        port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_3);
+
+    FF_42: FD1P3DX
+        port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_4);
+
+    FF_41: FD1P3DX
+        port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_0);
+
+    FF_40: FD1P3DX
+        port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_1);
+
+    FF_39: FD1P3DX
+        port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_2);
+
+    FF_38: FD1P3DX
+        port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_3);
+
+    FF_37: FD1P3DX
+        port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_4);
+
+    FF_36: FD1P3BX
+        port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, 
+            Q=>rcount_0);
+
+    FF_35: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_1);
+
+    FF_34: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_2);
+
+    FF_33: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_3);
+
+    FF_32: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_4);
+
+    FF_31: FD1P3DX
+        port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_0);
+
+    FF_30: FD1P3DX
+        port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_1);
+
+    FF_29: FD1P3DX
+        port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_2);
+
+    FF_28: FD1P3DX
+        port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_3);
+
+    FF_27: FD1P3DX
+        port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_4);
+
+    FF_26: FD1P3DX
+        port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_0);
+
+    FF_25: FD1P3DX
+        port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_1);
+
+    FF_24: FD1P3DX
+        port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_2);
+
+    FF_23: FD1P3DX
+        port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_3);
+
+    FF_22: FD1P3DX
+        port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_4);
+
+    FF_21: FD1S3DX
+        port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+    FF_20: FD1S3DX
+        port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+    FF_19: FD1S3DX
+        port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+    FF_18: FD1S3DX
+        port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+    FF_17: FD1S3DX
+        port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+    FF_16: FD1S3DX
+        port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+    FF_15: FD1S3DX
+        port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+    FF_14: FD1S3DX
+        port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+    FF_13: FD1S3DX
+        port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+    FF_12: FD1S3DX
+        port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+    FF_11: FD1S3DX
+        port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r20);
+
+    FF_10: FD1S3DX
+        port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r21);
+
+    FF_9: FD1S3DX
+        port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r22);
+
+    FF_8: FD1S3DX
+        port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r23);
+
+    FF_7: FD1S3DX
+        port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r24);
+
+    FF_6: FD1S3DX
+        port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+    FF_5: FD1S3DX
+        port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+    FF_4: FD1S3DX
+        port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+    FF_3: FD1S3DX
+        port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+    FF_2: FD1S3DX
+        port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+    FF_1: FD1S3BX
+        port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+    FF_0: FD1S3DX
+        port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+    w_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, 
+            S1=>open);
+
+    w_gctr_0: CU2
+        port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, 
+            NC0=>iwcount_0, NC1=>iwcount_1);
+
+    w_gctr_1: CU2
+        port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, 
+            NC0=>iwcount_2, NC1=>iwcount_3);
+
+    w_gctr_2: CU2
+        port map (CI=>co1, PC0=>wcount_4, PC1=>scuba_vlo, CO=>co2, 
+            NC0=>iwcount_4, NC1=>open);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    r_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, 
+            S1=>open);
+
+    r_gctr_0: CU2
+        port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, 
+            NC0=>ircount_0, NC1=>ircount_1);
+
+    r_gctr_1: CU2
+        port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, 
+            NC0=>ircount_2, NC1=>ircount_3);
+
+    r_gctr_2: CU2
+        port map (CI=>co1_1, PC0=>rcount_4, PC1=>scuba_vlo, CO=>co2_1, 
+            NC0=>ircount_4, NC1=>open);
+
+    empty_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+    empty_cmp_0: AGEB2
+        port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, 
+            B1=>w_g2b_xor_cluster_0, CI=>cmp_ci, GE=>co0_2);
+
+    empty_cmp_1: AGEB2
+        port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, 
+            B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
+
+    empty_cmp_2: AGEB2
+        port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, 
+            B1=>scuba_vlo, CI=>co1_2, GE=>empty_d_c);
+
+    a0: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, 
+            S1=>open);
+
+    full_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+    full_cmp_0: AGEB2
+        port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, 
+            B1=>r_g2b_xor_cluster_0, CI=>cmp_ci_1, GE=>co0_3);
+
+    full_cmp_1: AGEB2
+        port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, 
+            B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
+
+    full_cmp_2: AGEB2
+        port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, 
+            B1=>scuba_vlo, CI=>co1_3, GE=>full_d_c);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    a1: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, 
+            S1=>open);
+
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of async_fifo_16x32_ecp3 is
+    for Structure
+        for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+        for all:AND2 use entity ecp3.AND2(V); end for;
+        for all:CU2 use entity ecp3.CU2(V); end for;
+        for all:FADD2B use entity ecp3.FADD2B(V); end for;
+        for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
+        for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+        for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+        for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+        for all:INV use entity ecp3.INV(V); end for;
+        for all:OR2 use entity ecp3.OR2(V); end for;
+        for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+        for all:VHI use entity ecp3.VHI(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+        for all:XOR2 use entity ecp3.XOR2(V); end for;
+        for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_16x32_ecp3_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/async_fifo_16x32_ecp3_tmpl.vhd
new file mode 100644
index 0000000..a3daa68
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_16x32_ecp3_tmpl.vhd
@@ -0,0 +1,18 @@
+-- VHDL module instantiation generated by SCUBA Diamond_2.2_Production (99)
+-- Module  Version: 5.5
+-- Thu Jul 10 08:38:32 2014
+
+-- parameterized module component declaration
+component async_fifo_16x32_ecp3
+    port (Data: in  std_logic_vector(31 downto 0); 
+        WrClock: in  std_logic; RdClock: in  std_logic; 
+        WrEn: in  std_logic; RdEn: in  std_logic; Reset: in  std_logic; 
+        RPReset: in  std_logic; Q: out  std_logic_vector(31 downto 0); 
+        Empty: out  std_logic; Full: out  std_logic);
+end component;
+
+-- parameterized module component instance
+__ : async_fifo_16x32_ecp3
+    port map (Data(31 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, 
+        RdEn=>__, Reset=>__, RPReset=>__, Q(31 downto 0)=>__, Empty=>__, 
+        Full=>__);
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_256x66_ecp3.ipx b/data_concentrator/sources/lattice/ecp3/async_fifo_256x66_ecp3.ipx
new file mode 100644
index 0000000..3ab229d
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_256x66_ecp3.ipx
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="async_fifo_256x66_ecp3" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 09 23 15:56:47.457" version="5.7" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="async_fifo_256x66_ecp3.lpc" type="lpc" modified="2014 09 23 15:56:44.661"/>
+		<File name="async_fifo_256x66_ecp3.vhd" type="top_level_vhdl" modified="2014 09 23 15:56:44.768"/>
+		<File name="async_fifo_256x66_ecp3_tmpl.vhd" type="template_vhdl" modified="2014 09 23 15:56:44.769"/>
+		<File name="tb_async_fifo_256x66_ecp3_tmpl.vhd" type="testbench_vhdl" modified="2014 09 23 15:56:44.780"/>
+  </Package>
+</DiamondModule>
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_256x66_ecp3.lpc b/data_concentrator/sources/lattice/ecp3/async_fifo_256x66_ecp3.lpc
new file mode 100644
index 0000000..d131714
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_256x66_ecp3.lpc
@@ -0,0 +1,50 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.7
+ModuleName=async_fifo_256x66_ecp3
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=09/23/2014
+Time=15:56:44
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=256
+Width=66
+RDepth=256
+RWidth=66
+regout=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=0
+WDataCount=0
+EnECC=0
+
+[Command]
+cmd_line= -w -n async_fifo_256x66_ecp3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 8 -data_width 66 -num_words 256 -rdata_width 66 -no_enable -pe -1 -pf -1
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_256x66_ecp3.vhd b/data_concentrator/sources/lattice/ecp3/async_fifo_256x66_ecp3.vhd
new file mode 100644
index 0000000..0068b8f
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_256x66_ecp3.vhd
@@ -0,0 +1,1155 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.7
+--C:\Lattice\diamond\3.2_x64\ispfpga\bin\nt64\scuba.exe -w -n async_fifo_256x66_ecp3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 256 -width 66 -depth 256 -rdata_width 66 -no_enable -pe -1 -pf -1 
+
+-- Tue Sep 23 15:56:44 2014
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity async_fifo_256x66_ecp3 is
+    port (
+        Data: in  std_logic_vector(65 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(65 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic);
+end async_fifo_256x66_ecp3;
+
+architecture Structure of async_fifo_256x66_ecp3 is
+
+    -- internal signal declarations
+    signal invout_1: std_logic;
+    signal invout_0: std_logic;
+    signal w_g2b_xor_cluster_1: std_logic;
+    signal r_g2b_xor_cluster_1: std_logic;
+    signal w_gdata_0: std_logic;
+    signal w_gdata_1: std_logic;
+    signal w_gdata_2: std_logic;
+    signal w_gdata_3: std_logic;
+    signal w_gdata_4: std_logic;
+    signal w_gdata_5: std_logic;
+    signal w_gdata_6: std_logic;
+    signal w_gdata_7: std_logic;
+    signal wptr_0: std_logic;
+    signal wptr_1: std_logic;
+    signal wptr_2: std_logic;
+    signal wptr_3: std_logic;
+    signal wptr_4: std_logic;
+    signal wptr_5: std_logic;
+    signal wptr_6: std_logic;
+    signal wptr_7: std_logic;
+    signal wptr_8: std_logic;
+    signal r_gdata_0: std_logic;
+    signal r_gdata_1: std_logic;
+    signal r_gdata_2: std_logic;
+    signal r_gdata_3: std_logic;
+    signal r_gdata_4: std_logic;
+    signal r_gdata_5: std_logic;
+    signal r_gdata_6: std_logic;
+    signal r_gdata_7: std_logic;
+    signal rptr_0: std_logic;
+    signal rptr_1: std_logic;
+    signal rptr_2: std_logic;
+    signal rptr_3: std_logic;
+    signal rptr_4: std_logic;
+    signal rptr_5: std_logic;
+    signal rptr_6: std_logic;
+    signal rptr_7: std_logic;
+    signal rptr_8: std_logic;
+    signal w_gcount_0: std_logic;
+    signal w_gcount_1: std_logic;
+    signal w_gcount_2: std_logic;
+    signal w_gcount_3: std_logic;
+    signal w_gcount_4: std_logic;
+    signal w_gcount_5: std_logic;
+    signal w_gcount_6: std_logic;
+    signal w_gcount_7: std_logic;
+    signal w_gcount_8: std_logic;
+    signal r_gcount_0: std_logic;
+    signal r_gcount_1: std_logic;
+    signal r_gcount_2: std_logic;
+    signal r_gcount_3: std_logic;
+    signal r_gcount_4: std_logic;
+    signal r_gcount_5: std_logic;
+    signal r_gcount_6: std_logic;
+    signal r_gcount_7: std_logic;
+    signal r_gcount_8: std_logic;
+    signal w_gcount_r20: std_logic;
+    signal w_gcount_r0: std_logic;
+    signal w_gcount_r21: std_logic;
+    signal w_gcount_r1: std_logic;
+    signal w_gcount_r22: std_logic;
+    signal w_gcount_r2: std_logic;
+    signal w_gcount_r23: std_logic;
+    signal w_gcount_r3: std_logic;
+    signal w_gcount_r24: std_logic;
+    signal w_gcount_r4: std_logic;
+    signal w_gcount_r25: std_logic;
+    signal w_gcount_r5: std_logic;
+    signal w_gcount_r26: std_logic;
+    signal w_gcount_r6: std_logic;
+    signal w_gcount_r27: std_logic;
+    signal w_gcount_r7: std_logic;
+    signal w_gcount_r28: std_logic;
+    signal w_gcount_r8: std_logic;
+    signal r_gcount_w20: std_logic;
+    signal r_gcount_w0: std_logic;
+    signal r_gcount_w21: std_logic;
+    signal r_gcount_w1: std_logic;
+    signal r_gcount_w22: std_logic;
+    signal r_gcount_w2: std_logic;
+    signal r_gcount_w23: std_logic;
+    signal r_gcount_w3: std_logic;
+    signal r_gcount_w24: std_logic;
+    signal r_gcount_w4: std_logic;
+    signal r_gcount_w25: std_logic;
+    signal r_gcount_w5: std_logic;
+    signal r_gcount_w26: std_logic;
+    signal r_gcount_w6: std_logic;
+    signal r_gcount_w27: std_logic;
+    signal r_gcount_w7: std_logic;
+    signal r_gcount_w28: std_logic;
+    signal r_gcount_w8: std_logic;
+    signal empty_i: std_logic;
+    signal rRst: std_logic;
+    signal full_i: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_gctr_ci: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co0: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal co1: std_logic;
+    signal iwcount_6: std_logic;
+    signal iwcount_7: std_logic;
+    signal co2: std_logic;
+    signal iwcount_8: std_logic;
+    signal co4: std_logic;
+    signal co3: std_logic;
+    signal wcount_8: std_logic;
+    signal scuba_vhi: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_gctr_ci: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co0_1: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal co1_1: std_logic;
+    signal ircount_6: std_logic;
+    signal ircount_7: std_logic;
+    signal co2_1: std_logic;
+    signal ircount_8: std_logic;
+    signal co4_1: std_logic;
+    signal co3_1: std_logic;
+    signal rcount_8: std_logic;
+    signal rden_i: std_logic;
+    signal cmp_ci: std_logic;
+    signal wcount_r0: std_logic;
+    signal wcount_r1: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal co0_2: std_logic;
+    signal wcount_r2: std_logic;
+    signal wcount_r3: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal co1_2: std_logic;
+    signal wcount_r4: std_logic;
+    signal w_g2b_xor_cluster_0: std_logic;
+    signal rcount_4: std_logic;
+    signal rcount_5: std_logic;
+    signal co2_2: std_logic;
+    signal wcount_r6: std_logic;
+    signal wcount_r7: std_logic;
+    signal rcount_6: std_logic;
+    signal rcount_7: std_logic;
+    signal co3_2: std_logic;
+    signal empty_cmp_clr: std_logic;
+    signal empty_cmp_set: std_logic;
+    signal empty_d: std_logic;
+    signal empty_d_c: std_logic;
+    signal wren_i: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal rcount_w0: std_logic;
+    signal rcount_w1: std_logic;
+    signal wcount_0: std_logic;
+    signal wcount_1: std_logic;
+    signal co0_3: std_logic;
+    signal rcount_w2: std_logic;
+    signal rcount_w3: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_3: std_logic;
+    signal co1_3: std_logic;
+    signal rcount_w4: std_logic;
+    signal r_g2b_xor_cluster_0: std_logic;
+    signal wcount_4: std_logic;
+    signal wcount_5: std_logic;
+    signal co2_3: std_logic;
+    signal rcount_w6: std_logic;
+    signal rcount_w7: std_logic;
+    signal wcount_6: std_logic;
+    signal wcount_7: std_logic;
+    signal co3_3: std_logic;
+    signal full_cmp_clr: std_logic;
+    signal full_cmp_set: std_logic;
+    signal full_d: std_logic;
+    signal full_d_c: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component AGEB2
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; GE: out  std_logic);
+    end component;
+    component AND2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component CU2
+        port (CI: in  std_logic; PC0: in  std_logic; PC1: in  std_logic; 
+            CO: out  std_logic; NC0: out  std_logic; NC1: out  std_logic);
+    end component;
+    component FADD2B
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; COUT: out  std_logic; 
+            S0: out  std_logic; S1: out  std_logic);
+    end component;
+    component FD1P3BX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            PD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1P3DX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            CD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1S3BX
+        port (D: in  std_logic; CK: in  std_logic; PD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component FD1S3DX
+        port (D: in  std_logic; CK: in  std_logic; CD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component INV
+        port (A: in  std_logic; Z: out  std_logic);
+    end component;
+    component OR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component ROM16X1A
+        generic (INITVAL : in std_logic_vector(15 downto 0));
+        port (AD3: in  std_logic; AD2: in  std_logic; AD1: in  std_logic; 
+            AD0: in  std_logic; DO0: out  std_logic);
+    end component;
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component XOR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component PDPW16KC
+        generic (GSR : in String; CSDECODE_R : in String; 
+                CSDECODE_W : in String; REGMODE : in String; 
+                DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+        port (DI0: in  std_logic; DI1: in  std_logic; DI2: in  std_logic; 
+            DI3: in  std_logic; DI4: in  std_logic; DI5: in  std_logic; 
+            DI6: in  std_logic; DI7: in  std_logic; DI8: in  std_logic; 
+            DI9: in  std_logic; DI10: in  std_logic; DI11: in  std_logic; 
+            DI12: in  std_logic; DI13: in  std_logic; 
+            DI14: in  std_logic; DI15: in  std_logic; 
+            DI16: in  std_logic; DI17: in  std_logic; 
+            DI18: in  std_logic; DI19: in  std_logic; 
+            DI20: in  std_logic; DI21: in  std_logic; 
+            DI22: in  std_logic; DI23: in  std_logic; 
+            DI24: in  std_logic; DI25: in  std_logic; 
+            DI26: in  std_logic; DI27: in  std_logic; 
+            DI28: in  std_logic; DI29: in  std_logic; 
+            DI30: in  std_logic; DI31: in  std_logic; 
+            DI32: in  std_logic; DI33: in  std_logic; 
+            DI34: in  std_logic; DI35: in  std_logic; 
+            ADW0: in  std_logic; ADW1: in  std_logic; 
+            ADW2: in  std_logic; ADW3: in  std_logic; 
+            ADW4: in  std_logic; ADW5: in  std_logic; 
+            ADW6: in  std_logic; ADW7: in  std_logic; 
+            ADW8: in  std_logic; BE0: in  std_logic; BE1: in  std_logic; 
+            BE2: in  std_logic; BE3: in  std_logic; CEW: in  std_logic; 
+            CLKW: in  std_logic; CSW0: in  std_logic; 
+            CSW1: in  std_logic; CSW2: in  std_logic; 
+            ADR0: in  std_logic; ADR1: in  std_logic; 
+            ADR2: in  std_logic; ADR3: in  std_logic; 
+            ADR4: in  std_logic; ADR5: in  std_logic; 
+            ADR6: in  std_logic; ADR7: in  std_logic; 
+            ADR8: in  std_logic; ADR9: in  std_logic; 
+            ADR10: in  std_logic; ADR11: in  std_logic; 
+            ADR12: in  std_logic; ADR13: in  std_logic; 
+            CER: in  std_logic; CLKR: in  std_logic; CSR0: in  std_logic; 
+            CSR1: in  std_logic; CSR2: in  std_logic; RST: in  std_logic; 
+            DO0: out  std_logic; DO1: out  std_logic; 
+            DO2: out  std_logic; DO3: out  std_logic; 
+            DO4: out  std_logic; DO5: out  std_logic; 
+            DO6: out  std_logic; DO7: out  std_logic; 
+            DO8: out  std_logic; DO9: out  std_logic; 
+            DO10: out  std_logic; DO11: out  std_logic; 
+            DO12: out  std_logic; DO13: out  std_logic; 
+            DO14: out  std_logic; DO15: out  std_logic; 
+            DO16: out  std_logic; DO17: out  std_logic; 
+            DO18: out  std_logic; DO19: out  std_logic; 
+            DO20: out  std_logic; DO21: out  std_logic; 
+            DO22: out  std_logic; DO23: out  std_logic; 
+            DO24: out  std_logic; DO25: out  std_logic; 
+            DO26: out  std_logic; DO27: out  std_logic; 
+            DO28: out  std_logic; DO29: out  std_logic; 
+            DO30: out  std_logic; DO31: out  std_logic; 
+            DO32: out  std_logic; DO33: out  std_logic; 
+            DO34: out  std_logic; DO35: out  std_logic);
+    end component;
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute RESETMODE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "async_fifo_256x66_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
+    attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "async_fifo_256x66_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
+    attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC";
+    attribute GSR of FF_91 : label is "ENABLED";
+    attribute GSR of FF_90 : label is "ENABLED";
+    attribute GSR of FF_89 : label is "ENABLED";
+    attribute GSR of FF_88 : label is "ENABLED";
+    attribute GSR of FF_87 : label is "ENABLED";
+    attribute GSR of FF_86 : label is "ENABLED";
+    attribute GSR of FF_85 : label is "ENABLED";
+    attribute GSR of FF_84 : label is "ENABLED";
+    attribute GSR of FF_83 : label is "ENABLED";
+    attribute GSR of FF_82 : label is "ENABLED";
+    attribute GSR of FF_81 : label is "ENABLED";
+    attribute GSR of FF_80 : label is "ENABLED";
+    attribute GSR of FF_79 : label is "ENABLED";
+    attribute GSR of FF_78 : label is "ENABLED";
+    attribute GSR of FF_77 : label is "ENABLED";
+    attribute GSR of FF_76 : label is "ENABLED";
+    attribute GSR of FF_75 : label is "ENABLED";
+    attribute GSR of FF_74 : label is "ENABLED";
+    attribute GSR of FF_73 : label is "ENABLED";
+    attribute GSR of FF_72 : label is "ENABLED";
+    attribute GSR of FF_71 : label is "ENABLED";
+    attribute GSR of FF_70 : label is "ENABLED";
+    attribute GSR of FF_69 : label is "ENABLED";
+    attribute GSR of FF_68 : label is "ENABLED";
+    attribute GSR of FF_67 : label is "ENABLED";
+    attribute GSR of FF_66 : label is "ENABLED";
+    attribute GSR of FF_65 : label is "ENABLED";
+    attribute GSR of FF_64 : label is "ENABLED";
+    attribute GSR of FF_63 : label is "ENABLED";
+    attribute GSR of FF_62 : label is "ENABLED";
+    attribute GSR of FF_61 : label is "ENABLED";
+    attribute GSR of FF_60 : label is "ENABLED";
+    attribute GSR of FF_59 : label is "ENABLED";
+    attribute GSR of FF_58 : label is "ENABLED";
+    attribute GSR of FF_57 : label is "ENABLED";
+    attribute GSR of FF_56 : label is "ENABLED";
+    attribute GSR of FF_55 : label is "ENABLED";
+    attribute GSR of FF_54 : label is "ENABLED";
+    attribute GSR of FF_53 : label is "ENABLED";
+    attribute GSR of FF_52 : label is "ENABLED";
+    attribute GSR of FF_51 : label is "ENABLED";
+    attribute GSR of FF_50 : label is "ENABLED";
+    attribute GSR of FF_49 : label is "ENABLED";
+    attribute GSR of FF_48 : label is "ENABLED";
+    attribute GSR of FF_47 : label is "ENABLED";
+    attribute GSR of FF_46 : label is "ENABLED";
+    attribute GSR of FF_45 : label is "ENABLED";
+    attribute GSR of FF_44 : label is "ENABLED";
+    attribute GSR of FF_43 : label is "ENABLED";
+    attribute GSR of FF_42 : label is "ENABLED";
+    attribute GSR of FF_41 : label is "ENABLED";
+    attribute GSR of FF_40 : label is "ENABLED";
+    attribute GSR of FF_39 : label is "ENABLED";
+    attribute GSR of FF_38 : label is "ENABLED";
+    attribute GSR of FF_37 : label is "ENABLED";
+    attribute GSR of FF_36 : label is "ENABLED";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t18: AND2
+        port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+    INV_1: INV
+        port map (A=>full_i, Z=>invout_1);
+
+    AND2_t17: AND2
+        port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+    INV_0: INV
+        port map (A=>empty_i, Z=>invout_0);
+
+    OR2_t16: OR2
+        port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+    XOR2_t15: XOR2
+        port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+    XOR2_t14: XOR2
+        port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+    XOR2_t13: XOR2
+        port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+    XOR2_t12: XOR2
+        port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+    XOR2_t11: XOR2
+        port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+    XOR2_t10: XOR2
+        port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
+
+    XOR2_t9: XOR2
+        port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
+
+    XOR2_t8: XOR2
+        port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
+
+    XOR2_t7: XOR2
+        port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+    XOR2_t6: XOR2
+        port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+    XOR2_t5: XOR2
+        port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+    XOR2_t4: XOR2
+        port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+    XOR2_t3: XOR2
+        port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+    XOR2_t2: XOR2
+        port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
+
+    XOR2_t1: XOR2
+        port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
+
+    XOR2_t0: XOR2
+        port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
+
+    LUT4_21: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, 
+            AD1=>w_gcount_r27, AD0=>w_gcount_r28, 
+            DO0=>w_g2b_xor_cluster_0);
+
+    LUT4_20: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, 
+            AD1=>w_gcount_r23, AD0=>w_gcount_r24, 
+            DO0=>w_g2b_xor_cluster_1);
+
+    LUT4_19: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>wcount_r7);
+
+    LUT4_18: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, 
+            AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r6);
+
+    LUT4_17: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, 
+            AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
+
+    LUT4_16: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, 
+            AD1=>w_gcount_r25, AD0=>wcount_r6, DO0=>wcount_r3);
+
+    LUT4_15: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, 
+            AD1=>w_gcount_r24, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r2);
+
+    LUT4_14: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r1);
+
+    LUT4_13: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_gcount_r20, AD0=>scuba_vlo, DO0=>wcount_r0);
+
+    LUT4_12: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, 
+            AD1=>r_gcount_w27, AD0=>r_gcount_w28, 
+            DO0=>r_g2b_xor_cluster_0);
+
+    LUT4_11: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, 
+            AD1=>r_gcount_w23, AD0=>r_gcount_w24, 
+            DO0=>r_g2b_xor_cluster_1);
+
+    LUT4_10: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>rcount_w7);
+
+    LUT4_9: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, 
+            AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w6);
+
+    LUT4_8: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, 
+            AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
+
+    LUT4_7: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, 
+            AD1=>r_gcount_w25, AD0=>rcount_w6, DO0=>rcount_w3);
+
+    LUT4_6: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, 
+            AD1=>r_gcount_w24, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w2);
+
+    LUT4_5: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w1);
+
+    LUT4_4: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_gcount_w20, AD0=>scuba_vlo, DO0=>rcount_w0);
+
+    LUT4_3: ROM16X1A
+        generic map (initval=> X"0410")
+        port map (AD3=>rptr_8, AD2=>rcount_8, AD1=>w_gcount_r28, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+    LUT4_2: ROM16X1A
+        generic map (initval=> X"1004")
+        port map (AD3=>rptr_8, AD2=>rcount_8, AD1=>w_gcount_r28, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"0140")
+        port map (AD3=>wptr_8, AD2=>wcount_8, AD1=>r_gcount_w28, 
+            AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"4001")
+        port map (AD3=>wptr_8, AD2=>wcount_8, AD1=>r_gcount_w28, 
+            AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+    pdp_ram_0_0_1: PDPW16KC
+        generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", 
+        REGMODE=> "NOREG", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
+        port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), 
+            DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), 
+            DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), 
+            DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), 
+            DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), 
+            DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), 
+            DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), 
+            DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), 
+            DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), 
+            DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), 
+            DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0, 
+            ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4, 
+            ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>scuba_vlo, 
+            BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, 
+            BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, 
+            CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, 
+            ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, 
+            ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, 
+            ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, 
+            ADR12=>rptr_7, ADR13=>scuba_vlo, CER=>rden_i, CLKR=>RdClock, 
+            CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, 
+            RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), 
+            DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), 
+            DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), 
+            DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), DO16=>Q(34), 
+            DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), 
+            DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), 
+            DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), 
+            DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), 
+            DO35=>Q(17));
+
+    pdp_ram_0_1_0: PDPW16KC
+        generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", 
+        REGMODE=> "NOREG", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
+        port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), 
+            DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42), 
+            DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46), 
+            DI11=>Data(47), DI12=>Data(48), DI13=>Data(49), 
+            DI14=>Data(50), DI15=>Data(51), DI16=>Data(52), 
+            DI17=>Data(53), DI18=>Data(54), DI19=>Data(55), 
+            DI20=>Data(56), DI21=>Data(57), DI22=>Data(58), 
+            DI23=>Data(59), DI24=>Data(60), DI25=>Data(61), 
+            DI26=>Data(62), DI27=>Data(63), DI28=>Data(64), 
+            DI29=>Data(65), DI30=>scuba_vlo, DI31=>scuba_vlo, 
+            DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo, 
+            DI35=>scuba_vlo, ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, 
+            ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, 
+            ADW7=>wptr_7, ADW8=>scuba_vlo, BE0=>scuba_vhi, 
+            BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, 
+            CLKW=>WrClock, CSW0=>scuba_vhi, CSW1=>scuba_vlo, 
+            CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo, 
+            ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo, 
+            ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, ADR8=>rptr_3, 
+            ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, ADR12=>rptr_7, 
+            ADR13=>scuba_vlo, CER=>rden_i, CLKR=>RdClock, 
+            CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, 
+            RST=>Reset, DO0=>Q(54), DO1=>Q(55), DO2=>Q(56), DO3=>Q(57), 
+            DO4=>Q(58), DO5=>Q(59), DO6=>Q(60), DO7=>Q(61), DO8=>Q(62), 
+            DO9=>Q(63), DO10=>Q(64), DO11=>Q(65), DO12=>open, DO13=>open, 
+            DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>Q(36), 
+            DO19=>Q(37), DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), 
+            DO23=>Q(41), DO24=>Q(42), DO25=>Q(43), DO26=>Q(44), 
+            DO27=>Q(45), DO28=>Q(46), DO29=>Q(47), DO30=>Q(48), 
+            DO31=>Q(49), DO32=>Q(50), DO33=>Q(51), DO34=>Q(52), 
+            DO35=>Q(53));
+
+    FF_91: FD1P3BX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>wcount_0);
+
+    FF_90: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_89: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_88: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_87: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_86: FD1P3DX
+        port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_85: FD1P3DX
+        port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_6);
+
+    FF_84: FD1P3DX
+        port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_7);
+
+    FF_83: FD1P3DX
+        port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_8);
+
+    FF_82: FD1P3DX
+        port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_0);
+
+    FF_81: FD1P3DX
+        port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_1);
+
+    FF_80: FD1P3DX
+        port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_2);
+
+    FF_79: FD1P3DX
+        port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_3);
+
+    FF_78: FD1P3DX
+        port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_4);
+
+    FF_77: FD1P3DX
+        port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_5);
+
+    FF_76: FD1P3DX
+        port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_6);
+
+    FF_75: FD1P3DX
+        port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_7);
+
+    FF_74: FD1P3DX
+        port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_8);
+
+    FF_73: FD1P3DX
+        port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_0);
+
+    FF_72: FD1P3DX
+        port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_1);
+
+    FF_71: FD1P3DX
+        port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_2);
+
+    FF_70: FD1P3DX
+        port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_3);
+
+    FF_69: FD1P3DX
+        port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_4);
+
+    FF_68: FD1P3DX
+        port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_5);
+
+    FF_67: FD1P3DX
+        port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_6);
+
+    FF_66: FD1P3DX
+        port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_7);
+
+    FF_65: FD1P3DX
+        port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_8);
+
+    FF_64: FD1P3BX
+        port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, 
+            Q=>rcount_0);
+
+    FF_63: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_1);
+
+    FF_62: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_2);
+
+    FF_61: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_3);
+
+    FF_60: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_4);
+
+    FF_59: FD1P3DX
+        port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_5);
+
+    FF_58: FD1P3DX
+        port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_6);
+
+    FF_57: FD1P3DX
+        port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_7);
+
+    FF_56: FD1P3DX
+        port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_8);
+
+    FF_55: FD1P3DX
+        port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_0);
+
+    FF_54: FD1P3DX
+        port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_1);
+
+    FF_53: FD1P3DX
+        port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_2);
+
+    FF_52: FD1P3DX
+        port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_3);
+
+    FF_51: FD1P3DX
+        port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_4);
+
+    FF_50: FD1P3DX
+        port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_5);
+
+    FF_49: FD1P3DX
+        port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_6);
+
+    FF_48: FD1P3DX
+        port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_7);
+
+    FF_47: FD1P3DX
+        port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_8);
+
+    FF_46: FD1P3DX
+        port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_0);
+
+    FF_45: FD1P3DX
+        port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_1);
+
+    FF_44: FD1P3DX
+        port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_2);
+
+    FF_43: FD1P3DX
+        port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_3);
+
+    FF_42: FD1P3DX
+        port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_4);
+
+    FF_41: FD1P3DX
+        port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_5);
+
+    FF_40: FD1P3DX
+        port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_6);
+
+    FF_39: FD1P3DX
+        port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_7);
+
+    FF_38: FD1P3DX
+        port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_8);
+
+    FF_37: FD1S3DX
+        port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+    FF_36: FD1S3DX
+        port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+    FF_35: FD1S3DX
+        port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+    FF_34: FD1S3DX
+        port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+    FF_33: FD1S3DX
+        port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+    FF_32: FD1S3DX
+        port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+    FF_31: FD1S3DX
+        port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
+
+    FF_30: FD1S3DX
+        port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
+
+    FF_29: FD1S3DX
+        port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
+
+    FF_28: FD1S3DX
+        port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+    FF_27: FD1S3DX
+        port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+    FF_26: FD1S3DX
+        port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+    FF_25: FD1S3DX
+        port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+    FF_24: FD1S3DX
+        port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+    FF_23: FD1S3DX
+        port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+    FF_22: FD1S3DX
+        port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+    FF_21: FD1S3DX
+        port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
+
+    FF_20: FD1S3DX
+        port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
+
+    FF_19: FD1S3DX
+        port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r20);
+
+    FF_18: FD1S3DX
+        port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r21);
+
+    FF_17: FD1S3DX
+        port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r22);
+
+    FF_16: FD1S3DX
+        port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r23);
+
+    FF_15: FD1S3DX
+        port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r24);
+
+    FF_14: FD1S3DX
+        port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r25);
+
+    FF_13: FD1S3DX
+        port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r26);
+
+    FF_12: FD1S3DX
+        port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r27);
+
+    FF_11: FD1S3DX
+        port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r28);
+
+    FF_10: FD1S3DX
+        port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+    FF_9: FD1S3DX
+        port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+    FF_8: FD1S3DX
+        port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+    FF_7: FD1S3DX
+        port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+    FF_6: FD1S3DX
+        port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+    FF_5: FD1S3DX
+        port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+    FF_4: FD1S3DX
+        port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
+
+    FF_3: FD1S3DX
+        port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
+
+    FF_2: FD1S3DX
+        port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
+
+    FF_1: FD1S3BX
+        port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+    FF_0: FD1S3DX
+        port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+    w_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, 
+            S1=>open);
+
+    w_gctr_0: CU2
+        port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, 
+            NC0=>iwcount_0, NC1=>iwcount_1);
+
+    w_gctr_1: CU2
+        port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, 
+            NC0=>iwcount_2, NC1=>iwcount_3);
+
+    w_gctr_2: CU2
+        port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, 
+            NC0=>iwcount_4, NC1=>iwcount_5);
+
+    w_gctr_3: CU2
+        port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, 
+            NC0=>iwcount_6, NC1=>iwcount_7);
+
+    w_gctr_4: CU2
+        port map (CI=>co3, PC0=>wcount_8, PC1=>scuba_vlo, CO=>co4, 
+            NC0=>iwcount_8, NC1=>open);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    r_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, 
+            S1=>open);
+
+    r_gctr_0: CU2
+        port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, 
+            NC0=>ircount_0, NC1=>ircount_1);
+
+    r_gctr_1: CU2
+        port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, 
+            NC0=>ircount_2, NC1=>ircount_3);
+
+    r_gctr_2: CU2
+        port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, 
+            NC0=>ircount_4, NC1=>ircount_5);
+
+    r_gctr_3: CU2
+        port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, 
+            NC0=>ircount_6, NC1=>ircount_7);
+
+    r_gctr_4: CU2
+        port map (CI=>co3_1, PC0=>rcount_8, PC1=>scuba_vlo, CO=>co4_1, 
+            NC0=>ircount_8, NC1=>open);
+
+    empty_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+    empty_cmp_0: AGEB2
+        port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, 
+            B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
+
+    empty_cmp_1: AGEB2
+        port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, 
+            B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
+
+    empty_cmp_2: AGEB2
+        port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, 
+            B1=>w_g2b_xor_cluster_0, CI=>co1_2, GE=>co2_2);
+
+    empty_cmp_3: AGEB2
+        port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, 
+            B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
+
+    empty_cmp_4: AGEB2
+        port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, 
+            B1=>scuba_vlo, CI=>co3_2, GE=>empty_d_c);
+
+    a0: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, 
+            S1=>open);
+
+    full_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+    full_cmp_0: AGEB2
+        port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, 
+            B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
+
+    full_cmp_1: AGEB2
+        port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, 
+            B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
+
+    full_cmp_2: AGEB2
+        port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, 
+            B1=>r_g2b_xor_cluster_0, CI=>co1_3, GE=>co2_3);
+
+    full_cmp_3: AGEB2
+        port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, 
+            B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
+
+    full_cmp_4: AGEB2
+        port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, 
+            B1=>scuba_vlo, CI=>co3_3, GE=>full_d_c);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    a1: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, 
+            S1=>open);
+
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of async_fifo_256x66_ecp3 is
+    for Structure
+        for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+        for all:AND2 use entity ecp3.AND2(V); end for;
+        for all:CU2 use entity ecp3.CU2(V); end for;
+        for all:FADD2B use entity ecp3.FADD2B(V); end for;
+        for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
+        for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+        for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+        for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+        for all:INV use entity ecp3.INV(V); end for;
+        for all:OR2 use entity ecp3.OR2(V); end for;
+        for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+        for all:VHI use entity ecp3.VHI(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+        for all:XOR2 use entity ecp3.XOR2(V); end for;
+        for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_256x66_ecp3_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/async_fifo_256x66_ecp3_tmpl.vhd
new file mode 100644
index 0000000..e428f64
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_256x66_ecp3_tmpl.vhd
@@ -0,0 +1,18 @@
+-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.7
+-- Tue Sep 23 15:56:44 2014
+
+-- parameterized module component declaration
+component async_fifo_256x66_ecp3
+    port (Data: in  std_logic_vector(65 downto 0); 
+        WrClock: in  std_logic; RdClock: in  std_logic; 
+        WrEn: in  std_logic; RdEn: in  std_logic; Reset: in  std_logic; 
+        RPReset: in  std_logic; Q: out  std_logic_vector(65 downto 0); 
+        Empty: out  std_logic; Full: out  std_logic);
+end component;
+
+-- parameterized module component instance
+__ : async_fifo_256x66_ecp3
+    port map (Data(65 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, 
+        RdEn=>__, Reset=>__, RPReset=>__, Q(65 downto 0)=>__, Empty=>__, 
+        Full=>__);
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_512x32_ecp3.ipx b/data_concentrator/sources/lattice/ecp3/async_fifo_512x32_ecp3.ipx
new file mode 100644
index 0000000..7a08132
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_512x32_ecp3.ipx
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="async_fifo_512x32_ecp3" module="async_fifo_512x32_ecp3" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 12 09 08:41:53.572" version="5.7" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="async_fifo_512x32_ecp3.lpc" type="lpc" modified="2014 12 09 08:41:50.622"/>
+		<File name="async_fifo_512x32_ecp3.vhd" type="top_level_vhdl" modified="2014 12 09 08:41:50.718"/>
+		<File name="async_fifo_512x32_ecp3_tmpl.vhd" type="template_vhdl" modified="2014 12 09 08:41:50.719"/>
+		<File name="tb_async_fifo_512x32_ecp3_tmpl.vhd" type="testbench_vhdl" modified="2014 12 09 08:41:50.731"/>
+  </Package>
+</DiamondModule>
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_512x32_ecp3.lpc b/data_concentrator/sources/lattice/ecp3/async_fifo_512x32_ecp3.lpc
new file mode 100644
index 0000000..7c5e840
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_512x32_ecp3.lpc
@@ -0,0 +1,50 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.7
+ModuleName=async_fifo_512x32_ecp3
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=12/09/2014
+Time=08:41:50
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=512
+Width=32
+RDepth=512
+RWidth=32
+regout=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=0
+WDataCount=0
+EnECC=0
+
+[Command]
+cmd_line= -w -n async_fifo_512x32_ecp3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 9 -data_width 32 -num_words 512 -rdata_width 32 -no_enable -pe -1 -pf -1
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_512x32_ecp3.vhd b/data_concentrator/sources/lattice/ecp3/async_fifo_512x32_ecp3.vhd
new file mode 100644
index 0000000..2ef9d02
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_512x32_ecp3.vhd
@@ -0,0 +1,1195 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.7
+--C:\Lattice\diamond\3.2_x64\ispfpga\bin\nt64\scuba.exe -w -n async_fifo_512x32_ecp3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 32 -depth 512 -rdata_width 32 -no_enable -pe -1 -pf -1 
+
+-- Tue Dec 09 08:41:50 2014
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity async_fifo_512x32_ecp3 is
+    port (
+        Data: in  std_logic_vector(31 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(31 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic);
+end async_fifo_512x32_ecp3;
+
+architecture Structure of async_fifo_512x32_ecp3 is
+
+    -- internal signal declarations
+    signal invout_1: std_logic;
+    signal invout_0: std_logic;
+    signal w_g2b_xor_cluster_1: std_logic;
+    signal r_g2b_xor_cluster_1: std_logic;
+    signal w_gdata_0: std_logic;
+    signal w_gdata_1: std_logic;
+    signal w_gdata_2: std_logic;
+    signal w_gdata_3: std_logic;
+    signal w_gdata_4: std_logic;
+    signal w_gdata_5: std_logic;
+    signal w_gdata_6: std_logic;
+    signal w_gdata_7: std_logic;
+    signal w_gdata_8: std_logic;
+    signal wptr_0: std_logic;
+    signal wptr_1: std_logic;
+    signal wptr_2: std_logic;
+    signal wptr_3: std_logic;
+    signal wptr_4: std_logic;
+    signal wptr_5: std_logic;
+    signal wptr_6: std_logic;
+    signal wptr_7: std_logic;
+    signal wptr_8: std_logic;
+    signal wptr_9: std_logic;
+    signal r_gdata_0: std_logic;
+    signal r_gdata_1: std_logic;
+    signal r_gdata_2: std_logic;
+    signal r_gdata_3: std_logic;
+    signal r_gdata_4: std_logic;
+    signal r_gdata_5: std_logic;
+    signal r_gdata_6: std_logic;
+    signal r_gdata_7: std_logic;
+    signal r_gdata_8: std_logic;
+    signal rptr_0: std_logic;
+    signal rptr_1: std_logic;
+    signal rptr_2: std_logic;
+    signal rptr_3: std_logic;
+    signal rptr_4: std_logic;
+    signal rptr_5: std_logic;
+    signal rptr_6: std_logic;
+    signal rptr_7: std_logic;
+    signal rptr_8: std_logic;
+    signal rptr_9: std_logic;
+    signal w_gcount_0: std_logic;
+    signal w_gcount_1: std_logic;
+    signal w_gcount_2: std_logic;
+    signal w_gcount_3: std_logic;
+    signal w_gcount_4: std_logic;
+    signal w_gcount_5: std_logic;
+    signal w_gcount_6: std_logic;
+    signal w_gcount_7: std_logic;
+    signal w_gcount_8: std_logic;
+    signal w_gcount_9: std_logic;
+    signal r_gcount_0: std_logic;
+    signal r_gcount_1: std_logic;
+    signal r_gcount_2: std_logic;
+    signal r_gcount_3: std_logic;
+    signal r_gcount_4: std_logic;
+    signal r_gcount_5: std_logic;
+    signal r_gcount_6: std_logic;
+    signal r_gcount_7: std_logic;
+    signal r_gcount_8: std_logic;
+    signal r_gcount_9: std_logic;
+    signal w_gcount_r20: std_logic;
+    signal w_gcount_r0: std_logic;
+    signal w_gcount_r21: std_logic;
+    signal w_gcount_r1: std_logic;
+    signal w_gcount_r22: std_logic;
+    signal w_gcount_r2: std_logic;
+    signal w_gcount_r23: std_logic;
+    signal w_gcount_r3: std_logic;
+    signal w_gcount_r24: std_logic;
+    signal w_gcount_r4: std_logic;
+    signal w_gcount_r25: std_logic;
+    signal w_gcount_r5: std_logic;
+    signal w_gcount_r26: std_logic;
+    signal w_gcount_r6: std_logic;
+    signal w_gcount_r27: std_logic;
+    signal w_gcount_r7: std_logic;
+    signal w_gcount_r28: std_logic;
+    signal w_gcount_r8: std_logic;
+    signal w_gcount_r29: std_logic;
+    signal w_gcount_r9: std_logic;
+    signal r_gcount_w20: std_logic;
+    signal r_gcount_w0: std_logic;
+    signal r_gcount_w21: std_logic;
+    signal r_gcount_w1: std_logic;
+    signal r_gcount_w22: std_logic;
+    signal r_gcount_w2: std_logic;
+    signal r_gcount_w23: std_logic;
+    signal r_gcount_w3: std_logic;
+    signal r_gcount_w24: std_logic;
+    signal r_gcount_w4: std_logic;
+    signal r_gcount_w25: std_logic;
+    signal r_gcount_w5: std_logic;
+    signal r_gcount_w26: std_logic;
+    signal r_gcount_w6: std_logic;
+    signal r_gcount_w27: std_logic;
+    signal r_gcount_w7: std_logic;
+    signal r_gcount_w28: std_logic;
+    signal r_gcount_w8: std_logic;
+    signal r_gcount_w29: std_logic;
+    signal r_gcount_w9: std_logic;
+    signal empty_i: std_logic;
+    signal rRst: std_logic;
+    signal full_i: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_gctr_ci: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co0: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal co1: std_logic;
+    signal iwcount_6: std_logic;
+    signal iwcount_7: std_logic;
+    signal co2: std_logic;
+    signal iwcount_8: std_logic;
+    signal iwcount_9: std_logic;
+    signal co4: std_logic;
+    signal co3: std_logic;
+    signal wcount_9: std_logic;
+    signal scuba_vhi: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_gctr_ci: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co0_1: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal co1_1: std_logic;
+    signal ircount_6: std_logic;
+    signal ircount_7: std_logic;
+    signal co2_1: std_logic;
+    signal ircount_8: std_logic;
+    signal ircount_9: std_logic;
+    signal co4_1: std_logic;
+    signal co3_1: std_logic;
+    signal rcount_9: std_logic;
+    signal rden_i: std_logic;
+    signal cmp_ci: std_logic;
+    signal wcount_r0: std_logic;
+    signal wcount_r1: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal co0_2: std_logic;
+    signal wcount_r2: std_logic;
+    signal wcount_r3: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal co1_2: std_logic;
+    signal wcount_r4: std_logic;
+    signal wcount_r5: std_logic;
+    signal rcount_4: std_logic;
+    signal rcount_5: std_logic;
+    signal co2_2: std_logic;
+    signal w_g2b_xor_cluster_0: std_logic;
+    signal wcount_r7: std_logic;
+    signal rcount_6: std_logic;
+    signal rcount_7: std_logic;
+    signal co3_2: std_logic;
+    signal wcount_r8: std_logic;
+    signal empty_cmp_clr: std_logic;
+    signal rcount_8: std_logic;
+    signal empty_cmp_set: std_logic;
+    signal empty_d: std_logic;
+    signal empty_d_c: std_logic;
+    signal wren_i: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal rcount_w0: std_logic;
+    signal rcount_w1: std_logic;
+    signal wcount_0: std_logic;
+    signal wcount_1: std_logic;
+    signal co0_3: std_logic;
+    signal rcount_w2: std_logic;
+    signal rcount_w3: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_3: std_logic;
+    signal co1_3: std_logic;
+    signal rcount_w4: std_logic;
+    signal rcount_w5: std_logic;
+    signal wcount_4: std_logic;
+    signal wcount_5: std_logic;
+    signal co2_3: std_logic;
+    signal r_g2b_xor_cluster_0: std_logic;
+    signal rcount_w7: std_logic;
+    signal wcount_6: std_logic;
+    signal wcount_7: std_logic;
+    signal co3_3: std_logic;
+    signal rcount_w8: std_logic;
+    signal full_cmp_clr: std_logic;
+    signal wcount_8: std_logic;
+    signal full_cmp_set: std_logic;
+    signal full_d: std_logic;
+    signal full_d_c: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component AGEB2
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; GE: out  std_logic);
+    end component;
+    component AND2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component CU2
+        port (CI: in  std_logic; PC0: in  std_logic; PC1: in  std_logic; 
+            CO: out  std_logic; NC0: out  std_logic; NC1: out  std_logic);
+    end component;
+    component FADD2B
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; COUT: out  std_logic; 
+            S0: out  std_logic; S1: out  std_logic);
+    end component;
+    component FD1P3BX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            PD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1P3DX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            CD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1S3BX
+        port (D: in  std_logic; CK: in  std_logic; PD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component FD1S3DX
+        port (D: in  std_logic; CK: in  std_logic; CD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component INV
+        port (A: in  std_logic; Z: out  std_logic);
+    end component;
+    component OR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component ROM16X1A
+        generic (INITVAL : in std_logic_vector(15 downto 0));
+        port (AD3: in  std_logic; AD2: in  std_logic; AD1: in  std_logic; 
+            AD0: in  std_logic; DO0: out  std_logic);
+    end component;
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component XOR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component PDPW16KC
+        generic (GSR : in String; CSDECODE_R : in String; 
+                CSDECODE_W : in String; REGMODE : in String; 
+                DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+        port (DI0: in  std_logic; DI1: in  std_logic; DI2: in  std_logic; 
+            DI3: in  std_logic; DI4: in  std_logic; DI5: in  std_logic; 
+            DI6: in  std_logic; DI7: in  std_logic; DI8: in  std_logic; 
+            DI9: in  std_logic; DI10: in  std_logic; DI11: in  std_logic; 
+            DI12: in  std_logic; DI13: in  std_logic; 
+            DI14: in  std_logic; DI15: in  std_logic; 
+            DI16: in  std_logic; DI17: in  std_logic; 
+            DI18: in  std_logic; DI19: in  std_logic; 
+            DI20: in  std_logic; DI21: in  std_logic; 
+            DI22: in  std_logic; DI23: in  std_logic; 
+            DI24: in  std_logic; DI25: in  std_logic; 
+            DI26: in  std_logic; DI27: in  std_logic; 
+            DI28: in  std_logic; DI29: in  std_logic; 
+            DI30: in  std_logic; DI31: in  std_logic; 
+            DI32: in  std_logic; DI33: in  std_logic; 
+            DI34: in  std_logic; DI35: in  std_logic; 
+            ADW0: in  std_logic; ADW1: in  std_logic; 
+            ADW2: in  std_logic; ADW3: in  std_logic; 
+            ADW4: in  std_logic; ADW5: in  std_logic; 
+            ADW6: in  std_logic; ADW7: in  std_logic; 
+            ADW8: in  std_logic; BE0: in  std_logic; BE1: in  std_logic; 
+            BE2: in  std_logic; BE3: in  std_logic; CEW: in  std_logic; 
+            CLKW: in  std_logic; CSW0: in  std_logic; 
+            CSW1: in  std_logic; CSW2: in  std_logic; 
+            ADR0: in  std_logic; ADR1: in  std_logic; 
+            ADR2: in  std_logic; ADR3: in  std_logic; 
+            ADR4: in  std_logic; ADR5: in  std_logic; 
+            ADR6: in  std_logic; ADR7: in  std_logic; 
+            ADR8: in  std_logic; ADR9: in  std_logic; 
+            ADR10: in  std_logic; ADR11: in  std_logic; 
+            ADR12: in  std_logic; ADR13: in  std_logic; 
+            CER: in  std_logic; CLKR: in  std_logic; CSR0: in  std_logic; 
+            CSR1: in  std_logic; CSR2: in  std_logic; RST: in  std_logic; 
+            DO0: out  std_logic; DO1: out  std_logic; 
+            DO2: out  std_logic; DO3: out  std_logic; 
+            DO4: out  std_logic; DO5: out  std_logic; 
+            DO6: out  std_logic; DO7: out  std_logic; 
+            DO8: out  std_logic; DO9: out  std_logic; 
+            DO10: out  std_logic; DO11: out  std_logic; 
+            DO12: out  std_logic; DO13: out  std_logic; 
+            DO14: out  std_logic; DO15: out  std_logic; 
+            DO16: out  std_logic; DO17: out  std_logic; 
+            DO18: out  std_logic; DO19: out  std_logic; 
+            DO20: out  std_logic; DO21: out  std_logic; 
+            DO22: out  std_logic; DO23: out  std_logic; 
+            DO24: out  std_logic; DO25: out  std_logic; 
+            DO26: out  std_logic; DO27: out  std_logic; 
+            DO28: out  std_logic; DO29: out  std_logic; 
+            DO30: out  std_logic; DO31: out  std_logic; 
+            DO32: out  std_logic; DO33: out  std_logic; 
+            DO34: out  std_logic; DO35: out  std_logic);
+    end component;
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute RESETMODE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "async_fifo_512x32_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+    attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
+    attribute GSR of FF_101 : label is "ENABLED";
+    attribute GSR of FF_100 : label is "ENABLED";
+    attribute GSR of FF_99 : label is "ENABLED";
+    attribute GSR of FF_98 : label is "ENABLED";
+    attribute GSR of FF_97 : label is "ENABLED";
+    attribute GSR of FF_96 : label is "ENABLED";
+    attribute GSR of FF_95 : label is "ENABLED";
+    attribute GSR of FF_94 : label is "ENABLED";
+    attribute GSR of FF_93 : label is "ENABLED";
+    attribute GSR of FF_92 : label is "ENABLED";
+    attribute GSR of FF_91 : label is "ENABLED";
+    attribute GSR of FF_90 : label is "ENABLED";
+    attribute GSR of FF_89 : label is "ENABLED";
+    attribute GSR of FF_88 : label is "ENABLED";
+    attribute GSR of FF_87 : label is "ENABLED";
+    attribute GSR of FF_86 : label is "ENABLED";
+    attribute GSR of FF_85 : label is "ENABLED";
+    attribute GSR of FF_84 : label is "ENABLED";
+    attribute GSR of FF_83 : label is "ENABLED";
+    attribute GSR of FF_82 : label is "ENABLED";
+    attribute GSR of FF_81 : label is "ENABLED";
+    attribute GSR of FF_80 : label is "ENABLED";
+    attribute GSR of FF_79 : label is "ENABLED";
+    attribute GSR of FF_78 : label is "ENABLED";
+    attribute GSR of FF_77 : label is "ENABLED";
+    attribute GSR of FF_76 : label is "ENABLED";
+    attribute GSR of FF_75 : label is "ENABLED";
+    attribute GSR of FF_74 : label is "ENABLED";
+    attribute GSR of FF_73 : label is "ENABLED";
+    attribute GSR of FF_72 : label is "ENABLED";
+    attribute GSR of FF_71 : label is "ENABLED";
+    attribute GSR of FF_70 : label is "ENABLED";
+    attribute GSR of FF_69 : label is "ENABLED";
+    attribute GSR of FF_68 : label is "ENABLED";
+    attribute GSR of FF_67 : label is "ENABLED";
+    attribute GSR of FF_66 : label is "ENABLED";
+    attribute GSR of FF_65 : label is "ENABLED";
+    attribute GSR of FF_64 : label is "ENABLED";
+    attribute GSR of FF_63 : label is "ENABLED";
+    attribute GSR of FF_62 : label is "ENABLED";
+    attribute GSR of FF_61 : label is "ENABLED";
+    attribute GSR of FF_60 : label is "ENABLED";
+    attribute GSR of FF_59 : label is "ENABLED";
+    attribute GSR of FF_58 : label is "ENABLED";
+    attribute GSR of FF_57 : label is "ENABLED";
+    attribute GSR of FF_56 : label is "ENABLED";
+    attribute GSR of FF_55 : label is "ENABLED";
+    attribute GSR of FF_54 : label is "ENABLED";
+    attribute GSR of FF_53 : label is "ENABLED";
+    attribute GSR of FF_52 : label is "ENABLED";
+    attribute GSR of FF_51 : label is "ENABLED";
+    attribute GSR of FF_50 : label is "ENABLED";
+    attribute GSR of FF_49 : label is "ENABLED";
+    attribute GSR of FF_48 : label is "ENABLED";
+    attribute GSR of FF_47 : label is "ENABLED";
+    attribute GSR of FF_46 : label is "ENABLED";
+    attribute GSR of FF_45 : label is "ENABLED";
+    attribute GSR of FF_44 : label is "ENABLED";
+    attribute GSR of FF_43 : label is "ENABLED";
+    attribute GSR of FF_42 : label is "ENABLED";
+    attribute GSR of FF_41 : label is "ENABLED";
+    attribute GSR of FF_40 : label is "ENABLED";
+    attribute GSR of FF_39 : label is "ENABLED";
+    attribute GSR of FF_38 : label is "ENABLED";
+    attribute GSR of FF_37 : label is "ENABLED";
+    attribute GSR of FF_36 : label is "ENABLED";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t20: AND2
+        port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+    INV_1: INV
+        port map (A=>full_i, Z=>invout_1);
+
+    AND2_t19: AND2
+        port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+    INV_0: INV
+        port map (A=>empty_i, Z=>invout_0);
+
+    OR2_t18: OR2
+        port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+    XOR2_t17: XOR2
+        port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+    XOR2_t16: XOR2
+        port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+    XOR2_t15: XOR2
+        port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+    XOR2_t14: XOR2
+        port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+    XOR2_t13: XOR2
+        port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+    XOR2_t12: XOR2
+        port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
+
+    XOR2_t11: XOR2
+        port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
+
+    XOR2_t10: XOR2
+        port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
+
+    XOR2_t9: XOR2
+        port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
+
+    XOR2_t8: XOR2
+        port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+    XOR2_t7: XOR2
+        port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+    XOR2_t6: XOR2
+        port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+    XOR2_t5: XOR2
+        port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+    XOR2_t4: XOR2
+        port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+    XOR2_t3: XOR2
+        port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
+
+    XOR2_t2: XOR2
+        port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
+
+    XOR2_t1: XOR2
+        port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
+
+    XOR2_t0: XOR2
+        port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
+
+    LUT4_23: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, 
+            AD1=>w_gcount_r28, AD0=>w_gcount_r29, 
+            DO0=>w_g2b_xor_cluster_0);
+
+    LUT4_22: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, 
+            AD1=>w_gcount_r24, AD0=>w_gcount_r25, 
+            DO0=>w_g2b_xor_cluster_1);
+
+    LUT4_21: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>wcount_r8);
+
+    LUT4_20: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, 
+            AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7);
+
+    LUT4_19: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, 
+            AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
+
+    LUT4_18: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, 
+            AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
+
+    LUT4_17: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, 
+            AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3);
+
+    LUT4_16: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2);
+
+    LUT4_15: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1);
+
+    LUT4_14: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0);
+
+    LUT4_13: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, 
+            AD1=>r_gcount_w28, AD0=>r_gcount_w29, 
+            DO0=>r_g2b_xor_cluster_0);
+
+    LUT4_12: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, 
+            AD1=>r_gcount_w24, AD0=>r_gcount_w25, 
+            DO0=>r_g2b_xor_cluster_1);
+
+    LUT4_11: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>rcount_w8);
+
+    LUT4_10: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, 
+            AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7);
+
+    LUT4_9: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, 
+            AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
+
+    LUT4_8: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, 
+            AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
+
+    LUT4_7: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, 
+            AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3);
+
+    LUT4_6: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2);
+
+    LUT4_5: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1);
+
+    LUT4_4: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0);
+
+    LUT4_3: ROM16X1A
+        generic map (initval=> X"0410")
+        port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+    LUT4_2: ROM16X1A
+        generic map (initval=> X"1004")
+        port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"0140")
+        port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, 
+            AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"4001")
+        port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, 
+            AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+    pdp_ram_0_0_0: PDPW16KC
+        generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", 
+        REGMODE=> "NOREG", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
+        port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), 
+            DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), 
+            DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), 
+            DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), 
+            DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), 
+            DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), 
+            DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), 
+            DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), 
+            DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), 
+            DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo, 
+            DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, 
+            ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, 
+            ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, 
+            ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, 
+            BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, 
+            CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, 
+            ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, 
+            ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, 
+            ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, 
+            ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock, 
+            CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, 
+            RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), 
+            DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), 
+            DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), 
+            DO13=>Q(31), DO14=>open, DO15=>open, DO16=>open, DO17=>open, 
+            DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), 
+            DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), 
+            DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), 
+            DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), DO35=>Q(17));
+
+    FF_101: FD1P3BX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>wcount_0);
+
+    FF_100: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_99: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_98: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_97: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_96: FD1P3DX
+        port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_95: FD1P3DX
+        port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_6);
+
+    FF_94: FD1P3DX
+        port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_7);
+
+    FF_93: FD1P3DX
+        port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_8);
+
+    FF_92: FD1P3DX
+        port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_9);
+
+    FF_91: FD1P3DX
+        port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_0);
+
+    FF_90: FD1P3DX
+        port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_1);
+
+    FF_89: FD1P3DX
+        port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_2);
+
+    FF_88: FD1P3DX
+        port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_3);
+
+    FF_87: FD1P3DX
+        port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_4);
+
+    FF_86: FD1P3DX
+        port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_5);
+
+    FF_85: FD1P3DX
+        port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_6);
+
+    FF_84: FD1P3DX
+        port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_7);
+
+    FF_83: FD1P3DX
+        port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_8);
+
+    FF_82: FD1P3DX
+        port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_9);
+
+    FF_81: FD1P3DX
+        port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_0);
+
+    FF_80: FD1P3DX
+        port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_1);
+
+    FF_79: FD1P3DX
+        port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_2);
+
+    FF_78: FD1P3DX
+        port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_3);
+
+    FF_77: FD1P3DX
+        port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_4);
+
+    FF_76: FD1P3DX
+        port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_5);
+
+    FF_75: FD1P3DX
+        port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_6);
+
+    FF_74: FD1P3DX
+        port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_7);
+
+    FF_73: FD1P3DX
+        port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_8);
+
+    FF_72: FD1P3DX
+        port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_9);
+
+    FF_71: FD1P3BX
+        port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, 
+            Q=>rcount_0);
+
+    FF_70: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_1);
+
+    FF_69: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_2);
+
+    FF_68: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_3);
+
+    FF_67: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_4);
+
+    FF_66: FD1P3DX
+        port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_5);
+
+    FF_65: FD1P3DX
+        port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_6);
+
+    FF_64: FD1P3DX
+        port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_7);
+
+    FF_63: FD1P3DX
+        port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_8);
+
+    FF_62: FD1P3DX
+        port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_9);
+
+    FF_61: FD1P3DX
+        port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_0);
+
+    FF_60: FD1P3DX
+        port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_1);
+
+    FF_59: FD1P3DX
+        port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_2);
+
+    FF_58: FD1P3DX
+        port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_3);
+
+    FF_57: FD1P3DX
+        port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_4);
+
+    FF_56: FD1P3DX
+        port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_5);
+
+    FF_55: FD1P3DX
+        port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_6);
+
+    FF_54: FD1P3DX
+        port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_7);
+
+    FF_53: FD1P3DX
+        port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_8);
+
+    FF_52: FD1P3DX
+        port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_9);
+
+    FF_51: FD1P3DX
+        port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_0);
+
+    FF_50: FD1P3DX
+        port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_1);
+
+    FF_49: FD1P3DX
+        port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_2);
+
+    FF_48: FD1P3DX
+        port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_3);
+
+    FF_47: FD1P3DX
+        port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_4);
+
+    FF_46: FD1P3DX
+        port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_5);
+
+    FF_45: FD1P3DX
+        port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_6);
+
+    FF_44: FD1P3DX
+        port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_7);
+
+    FF_43: FD1P3DX
+        port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_8);
+
+    FF_42: FD1P3DX
+        port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_9);
+
+    FF_41: FD1S3DX
+        port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+    FF_40: FD1S3DX
+        port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+    FF_39: FD1S3DX
+        port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+    FF_38: FD1S3DX
+        port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+    FF_37: FD1S3DX
+        port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+    FF_36: FD1S3DX
+        port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+    FF_35: FD1S3DX
+        port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
+
+    FF_34: FD1S3DX
+        port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
+
+    FF_33: FD1S3DX
+        port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
+
+    FF_32: FD1S3DX
+        port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
+
+    FF_31: FD1S3DX
+        port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+    FF_30: FD1S3DX
+        port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+    FF_29: FD1S3DX
+        port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+    FF_28: FD1S3DX
+        port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+    FF_27: FD1S3DX
+        port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+    FF_26: FD1S3DX
+        port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+    FF_25: FD1S3DX
+        port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+    FF_24: FD1S3DX
+        port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
+
+    FF_23: FD1S3DX
+        port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
+
+    FF_22: FD1S3DX
+        port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
+
+    FF_21: FD1S3DX
+        port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r20);
+
+    FF_20: FD1S3DX
+        port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r21);
+
+    FF_19: FD1S3DX
+        port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r22);
+
+    FF_18: FD1S3DX
+        port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r23);
+
+    FF_17: FD1S3DX
+        port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r24);
+
+    FF_16: FD1S3DX
+        port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r25);
+
+    FF_15: FD1S3DX
+        port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r26);
+
+    FF_14: FD1S3DX
+        port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r27);
+
+    FF_13: FD1S3DX
+        port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r28);
+
+    FF_12: FD1S3DX
+        port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r29);
+
+    FF_11: FD1S3DX
+        port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+    FF_10: FD1S3DX
+        port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+    FF_9: FD1S3DX
+        port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+    FF_8: FD1S3DX
+        port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+    FF_7: FD1S3DX
+        port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+    FF_6: FD1S3DX
+        port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+    FF_5: FD1S3DX
+        port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
+
+    FF_4: FD1S3DX
+        port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
+
+    FF_3: FD1S3DX
+        port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
+
+    FF_2: FD1S3DX
+        port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
+
+    FF_1: FD1S3BX
+        port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+    FF_0: FD1S3DX
+        port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+    w_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, 
+            S1=>open);
+
+    w_gctr_0: CU2
+        port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, 
+            NC0=>iwcount_0, NC1=>iwcount_1);
+
+    w_gctr_1: CU2
+        port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, 
+            NC0=>iwcount_2, NC1=>iwcount_3);
+
+    w_gctr_2: CU2
+        port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, 
+            NC0=>iwcount_4, NC1=>iwcount_5);
+
+    w_gctr_3: CU2
+        port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, 
+            NC0=>iwcount_6, NC1=>iwcount_7);
+
+    w_gctr_4: CU2
+        port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, 
+            NC0=>iwcount_8, NC1=>iwcount_9);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    r_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, 
+            S1=>open);
+
+    r_gctr_0: CU2
+        port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, 
+            NC0=>ircount_0, NC1=>ircount_1);
+
+    r_gctr_1: CU2
+        port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, 
+            NC0=>ircount_2, NC1=>ircount_3);
+
+    r_gctr_2: CU2
+        port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, 
+            NC0=>ircount_4, NC1=>ircount_5);
+
+    r_gctr_3: CU2
+        port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, 
+            NC0=>ircount_6, NC1=>ircount_7);
+
+    r_gctr_4: CU2
+        port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, 
+            NC0=>ircount_8, NC1=>ircount_9);
+
+    empty_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+    empty_cmp_0: AGEB2
+        port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, 
+            B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
+
+    empty_cmp_1: AGEB2
+        port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, 
+            B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
+
+    empty_cmp_2: AGEB2
+        port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, 
+            B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
+
+    empty_cmp_3: AGEB2
+        port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0, 
+            B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
+
+    empty_cmp_4: AGEB2
+        port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8, 
+            B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c);
+
+    a0: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, 
+            S1=>open);
+
+    full_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+    full_cmp_0: AGEB2
+        port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, 
+            B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
+
+    full_cmp_1: AGEB2
+        port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, 
+            B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
+
+    full_cmp_2: AGEB2
+        port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, 
+            B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
+
+    full_cmp_3: AGEB2
+        port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, 
+            B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
+
+    full_cmp_4: AGEB2
+        port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8, 
+            B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    a1: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, 
+            S1=>open);
+
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of async_fifo_512x32_ecp3 is
+    for Structure
+        for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+        for all:AND2 use entity ecp3.AND2(V); end for;
+        for all:CU2 use entity ecp3.CU2(V); end for;
+        for all:FADD2B use entity ecp3.FADD2B(V); end for;
+        for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
+        for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+        for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+        for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+        for all:INV use entity ecp3.INV(V); end for;
+        for all:OR2 use entity ecp3.OR2(V); end for;
+        for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+        for all:VHI use entity ecp3.VHI(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+        for all:XOR2 use entity ecp3.XOR2(V); end for;
+        for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_512x32_ecp3_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/async_fifo_512x32_ecp3_tmpl.vhd
new file mode 100644
index 0000000..c54727a
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_512x32_ecp3_tmpl.vhd
@@ -0,0 +1,18 @@
+-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.7
+-- Tue Dec 09 08:41:50 2014
+
+-- parameterized module component declaration
+component async_fifo_512x32_ecp3
+    port (Data: in  std_logic_vector(31 downto 0); 
+        WrClock: in  std_logic; RdClock: in  std_logic; 
+        WrEn: in  std_logic; RdEn: in  std_logic; Reset: in  std_logic; 
+        RPReset: in  std_logic; Q: out  std_logic_vector(31 downto 0); 
+        Empty: out  std_logic; Full: out  std_logic);
+end component;
+
+-- parameterized module component instance
+__ : async_fifo_512x32_ecp3
+    port map (Data(31 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, 
+        RdEn=>__, Reset=>__, RPReset=>__, Q(31 downto 0)=>__, Empty=>__, 
+        Full=>__);
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_512x99_ecp3.ipx b/data_concentrator/sources/lattice/ecp3/async_fifo_512x99_ecp3.ipx
new file mode 100644
index 0000000..346c080
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_512x99_ecp3.ipx
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="async_fifo_512x99_ecp3" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 10 27 14:17:34.819" version="5.7" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="async_fifo_512x99_ecp3.lpc" type="lpc" modified="2014 10 27 14:17:32.162"/>
+		<File name="async_fifo_512x99_ecp3.vhd" type="top_level_vhdl" modified="2014 10 27 14:17:32.277"/>
+		<File name="async_fifo_512x99_ecp3_tmpl.vhd" type="template_vhdl" modified="2014 10 27 14:17:32.278"/>
+		<File name="tb_async_fifo_512x99_ecp3_tmpl.vhd" type="testbench_vhdl" modified="2014 10 27 14:17:32.282"/>
+  </Package>
+</DiamondModule>
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_512x99_ecp3.lpc b/data_concentrator/sources/lattice/ecp3/async_fifo_512x99_ecp3.lpc
new file mode 100644
index 0000000..f0e612e
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_512x99_ecp3.lpc
@@ -0,0 +1,50 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.7
+ModuleName=async_fifo_512x99_ecp3
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=10/27/2014
+Time=14:17:32
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=512
+Width=99
+RDepth=512
+RWidth=99
+regout=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=0
+WDataCount=0
+EnECC=0
+
+[Command]
+cmd_line= -w -n async_fifo_512x99_ecp3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 9 -data_width 99 -num_words 512 -rdata_width 99 -no_enable -pe -1 -pf -1
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_512x99_ecp3.vhd b/data_concentrator/sources/lattice/ecp3/async_fifo_512x99_ecp3.vhd
new file mode 100644
index 0000000..ffcfd92
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_512x99_ecp3.vhd
@@ -0,0 +1,1270 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.7
+--C:\Lattice\diamond\3.2_x64\ispfpga\bin\nt64\scuba.exe -w -n async_fifo_512x99_ecp3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 99 -depth 512 -rdata_width 99 -no_enable -pe -1 -pf -1 
+
+-- Mon Oct 27 14:17:32 2014
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity async_fifo_512x99_ecp3 is
+    port (
+        Data: in  std_logic_vector(98 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(98 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic);
+end async_fifo_512x99_ecp3;
+
+architecture Structure of async_fifo_512x99_ecp3 is
+
+    -- internal signal declarations
+    signal invout_1: std_logic;
+    signal invout_0: std_logic;
+    signal w_g2b_xor_cluster_1: std_logic;
+    signal r_g2b_xor_cluster_1: std_logic;
+    signal w_gdata_0: std_logic;
+    signal w_gdata_1: std_logic;
+    signal w_gdata_2: std_logic;
+    signal w_gdata_3: std_logic;
+    signal w_gdata_4: std_logic;
+    signal w_gdata_5: std_logic;
+    signal w_gdata_6: std_logic;
+    signal w_gdata_7: std_logic;
+    signal w_gdata_8: std_logic;
+    signal wptr_0: std_logic;
+    signal wptr_1: std_logic;
+    signal wptr_2: std_logic;
+    signal wptr_3: std_logic;
+    signal wptr_4: std_logic;
+    signal wptr_5: std_logic;
+    signal wptr_6: std_logic;
+    signal wptr_7: std_logic;
+    signal wptr_8: std_logic;
+    signal wptr_9: std_logic;
+    signal r_gdata_0: std_logic;
+    signal r_gdata_1: std_logic;
+    signal r_gdata_2: std_logic;
+    signal r_gdata_3: std_logic;
+    signal r_gdata_4: std_logic;
+    signal r_gdata_5: std_logic;
+    signal r_gdata_6: std_logic;
+    signal r_gdata_7: std_logic;
+    signal r_gdata_8: std_logic;
+    signal rptr_0: std_logic;
+    signal rptr_1: std_logic;
+    signal rptr_2: std_logic;
+    signal rptr_3: std_logic;
+    signal rptr_4: std_logic;
+    signal rptr_5: std_logic;
+    signal rptr_6: std_logic;
+    signal rptr_7: std_logic;
+    signal rptr_8: std_logic;
+    signal rptr_9: std_logic;
+    signal w_gcount_0: std_logic;
+    signal w_gcount_1: std_logic;
+    signal w_gcount_2: std_logic;
+    signal w_gcount_3: std_logic;
+    signal w_gcount_4: std_logic;
+    signal w_gcount_5: std_logic;
+    signal w_gcount_6: std_logic;
+    signal w_gcount_7: std_logic;
+    signal w_gcount_8: std_logic;
+    signal w_gcount_9: std_logic;
+    signal r_gcount_0: std_logic;
+    signal r_gcount_1: std_logic;
+    signal r_gcount_2: std_logic;
+    signal r_gcount_3: std_logic;
+    signal r_gcount_4: std_logic;
+    signal r_gcount_5: std_logic;
+    signal r_gcount_6: std_logic;
+    signal r_gcount_7: std_logic;
+    signal r_gcount_8: std_logic;
+    signal r_gcount_9: std_logic;
+    signal w_gcount_r20: std_logic;
+    signal w_gcount_r0: std_logic;
+    signal w_gcount_r21: std_logic;
+    signal w_gcount_r1: std_logic;
+    signal w_gcount_r22: std_logic;
+    signal w_gcount_r2: std_logic;
+    signal w_gcount_r23: std_logic;
+    signal w_gcount_r3: std_logic;
+    signal w_gcount_r24: std_logic;
+    signal w_gcount_r4: std_logic;
+    signal w_gcount_r25: std_logic;
+    signal w_gcount_r5: std_logic;
+    signal w_gcount_r26: std_logic;
+    signal w_gcount_r6: std_logic;
+    signal w_gcount_r27: std_logic;
+    signal w_gcount_r7: std_logic;
+    signal w_gcount_r28: std_logic;
+    signal w_gcount_r8: std_logic;
+    signal w_gcount_r29: std_logic;
+    signal w_gcount_r9: std_logic;
+    signal r_gcount_w20: std_logic;
+    signal r_gcount_w0: std_logic;
+    signal r_gcount_w21: std_logic;
+    signal r_gcount_w1: std_logic;
+    signal r_gcount_w22: std_logic;
+    signal r_gcount_w2: std_logic;
+    signal r_gcount_w23: std_logic;
+    signal r_gcount_w3: std_logic;
+    signal r_gcount_w24: std_logic;
+    signal r_gcount_w4: std_logic;
+    signal r_gcount_w25: std_logic;
+    signal r_gcount_w5: std_logic;
+    signal r_gcount_w26: std_logic;
+    signal r_gcount_w6: std_logic;
+    signal r_gcount_w27: std_logic;
+    signal r_gcount_w7: std_logic;
+    signal r_gcount_w28: std_logic;
+    signal r_gcount_w8: std_logic;
+    signal r_gcount_w29: std_logic;
+    signal r_gcount_w9: std_logic;
+    signal empty_i: std_logic;
+    signal rRst: std_logic;
+    signal full_i: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_gctr_ci: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co0: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal co1: std_logic;
+    signal iwcount_6: std_logic;
+    signal iwcount_7: std_logic;
+    signal co2: std_logic;
+    signal iwcount_8: std_logic;
+    signal iwcount_9: std_logic;
+    signal co4: std_logic;
+    signal co3: std_logic;
+    signal wcount_9: std_logic;
+    signal scuba_vhi: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_gctr_ci: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co0_1: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal co1_1: std_logic;
+    signal ircount_6: std_logic;
+    signal ircount_7: std_logic;
+    signal co2_1: std_logic;
+    signal ircount_8: std_logic;
+    signal ircount_9: std_logic;
+    signal co4_1: std_logic;
+    signal co3_1: std_logic;
+    signal rcount_9: std_logic;
+    signal rden_i: std_logic;
+    signal cmp_ci: std_logic;
+    signal wcount_r0: std_logic;
+    signal wcount_r1: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal co0_2: std_logic;
+    signal wcount_r2: std_logic;
+    signal wcount_r3: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal co1_2: std_logic;
+    signal wcount_r4: std_logic;
+    signal wcount_r5: std_logic;
+    signal rcount_4: std_logic;
+    signal rcount_5: std_logic;
+    signal co2_2: std_logic;
+    signal w_g2b_xor_cluster_0: std_logic;
+    signal wcount_r7: std_logic;
+    signal rcount_6: std_logic;
+    signal rcount_7: std_logic;
+    signal co3_2: std_logic;
+    signal wcount_r8: std_logic;
+    signal empty_cmp_clr: std_logic;
+    signal rcount_8: std_logic;
+    signal empty_cmp_set: std_logic;
+    signal empty_d: std_logic;
+    signal empty_d_c: std_logic;
+    signal wren_i: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal rcount_w0: std_logic;
+    signal rcount_w1: std_logic;
+    signal wcount_0: std_logic;
+    signal wcount_1: std_logic;
+    signal co0_3: std_logic;
+    signal rcount_w2: std_logic;
+    signal rcount_w3: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_3: std_logic;
+    signal co1_3: std_logic;
+    signal rcount_w4: std_logic;
+    signal rcount_w5: std_logic;
+    signal wcount_4: std_logic;
+    signal wcount_5: std_logic;
+    signal co2_3: std_logic;
+    signal r_g2b_xor_cluster_0: std_logic;
+    signal rcount_w7: std_logic;
+    signal wcount_6: std_logic;
+    signal wcount_7: std_logic;
+    signal co3_3: std_logic;
+    signal rcount_w8: std_logic;
+    signal full_cmp_clr: std_logic;
+    signal wcount_8: std_logic;
+    signal full_cmp_set: std_logic;
+    signal full_d: std_logic;
+    signal full_d_c: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component AGEB2
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; GE: out  std_logic);
+    end component;
+    component AND2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component CU2
+        port (CI: in  std_logic; PC0: in  std_logic; PC1: in  std_logic; 
+            CO: out  std_logic; NC0: out  std_logic; NC1: out  std_logic);
+    end component;
+    component FADD2B
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; COUT: out  std_logic; 
+            S0: out  std_logic; S1: out  std_logic);
+    end component;
+    component FD1P3BX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            PD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1P3DX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            CD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1S3BX
+        port (D: in  std_logic; CK: in  std_logic; PD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component FD1S3DX
+        port (D: in  std_logic; CK: in  std_logic; CD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component INV
+        port (A: in  std_logic; Z: out  std_logic);
+    end component;
+    component OR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component ROM16X1A
+        generic (INITVAL : in std_logic_vector(15 downto 0));
+        port (AD3: in  std_logic; AD2: in  std_logic; AD1: in  std_logic; 
+            AD0: in  std_logic; DO0: out  std_logic);
+    end component;
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component XOR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component PDPW16KC
+        generic (GSR : in String; CSDECODE_R : in String; 
+                CSDECODE_W : in String; REGMODE : in String; 
+                DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+        port (DI0: in  std_logic; DI1: in  std_logic; DI2: in  std_logic; 
+            DI3: in  std_logic; DI4: in  std_logic; DI5: in  std_logic; 
+            DI6: in  std_logic; DI7: in  std_logic; DI8: in  std_logic; 
+            DI9: in  std_logic; DI10: in  std_logic; DI11: in  std_logic; 
+            DI12: in  std_logic; DI13: in  std_logic; 
+            DI14: in  std_logic; DI15: in  std_logic; 
+            DI16: in  std_logic; DI17: in  std_logic; 
+            DI18: in  std_logic; DI19: in  std_logic; 
+            DI20: in  std_logic; DI21: in  std_logic; 
+            DI22: in  std_logic; DI23: in  std_logic; 
+            DI24: in  std_logic; DI25: in  std_logic; 
+            DI26: in  std_logic; DI27: in  std_logic; 
+            DI28: in  std_logic; DI29: in  std_logic; 
+            DI30: in  std_logic; DI31: in  std_logic; 
+            DI32: in  std_logic; DI33: in  std_logic; 
+            DI34: in  std_logic; DI35: in  std_logic; 
+            ADW0: in  std_logic; ADW1: in  std_logic; 
+            ADW2: in  std_logic; ADW3: in  std_logic; 
+            ADW4: in  std_logic; ADW5: in  std_logic; 
+            ADW6: in  std_logic; ADW7: in  std_logic; 
+            ADW8: in  std_logic; BE0: in  std_logic; BE1: in  std_logic; 
+            BE2: in  std_logic; BE3: in  std_logic; CEW: in  std_logic; 
+            CLKW: in  std_logic; CSW0: in  std_logic; 
+            CSW1: in  std_logic; CSW2: in  std_logic; 
+            ADR0: in  std_logic; ADR1: in  std_logic; 
+            ADR2: in  std_logic; ADR3: in  std_logic; 
+            ADR4: in  std_logic; ADR5: in  std_logic; 
+            ADR6: in  std_logic; ADR7: in  std_logic; 
+            ADR8: in  std_logic; ADR9: in  std_logic; 
+            ADR10: in  std_logic; ADR11: in  std_logic; 
+            ADR12: in  std_logic; ADR13: in  std_logic; 
+            CER: in  std_logic; CLKR: in  std_logic; CSR0: in  std_logic; 
+            CSR1: in  std_logic; CSR2: in  std_logic; RST: in  std_logic; 
+            DO0: out  std_logic; DO1: out  std_logic; 
+            DO2: out  std_logic; DO3: out  std_logic; 
+            DO4: out  std_logic; DO5: out  std_logic; 
+            DO6: out  std_logic; DO7: out  std_logic; 
+            DO8: out  std_logic; DO9: out  std_logic; 
+            DO10: out  std_logic; DO11: out  std_logic; 
+            DO12: out  std_logic; DO13: out  std_logic; 
+            DO14: out  std_logic; DO15: out  std_logic; 
+            DO16: out  std_logic; DO17: out  std_logic; 
+            DO18: out  std_logic; DO19: out  std_logic; 
+            DO20: out  std_logic; DO21: out  std_logic; 
+            DO22: out  std_logic; DO23: out  std_logic; 
+            DO24: out  std_logic; DO25: out  std_logic; 
+            DO26: out  std_logic; DO27: out  std_logic; 
+            DO28: out  std_logic; DO29: out  std_logic; 
+            DO30: out  std_logic; DO31: out  std_logic; 
+            DO32: out  std_logic; DO33: out  std_logic; 
+            DO34: out  std_logic; DO35: out  std_logic);
+    end component;
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute RESETMODE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_2 : label is "async_fifo_512x99_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_2 : label is "";
+    attribute RESETMODE of pdp_ram_0_0_2 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_0_1_1 : label is "async_fifo_512x99_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_1_1 : label is "";
+    attribute RESETMODE of pdp_ram_0_1_1 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_0_2_0 : label is "async_fifo_512x99_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_2_0 : label is "";
+    attribute RESETMODE of pdp_ram_0_2_0 : label is "SYNC";
+    attribute GSR of FF_101 : label is "ENABLED";
+    attribute GSR of FF_100 : label is "ENABLED";
+    attribute GSR of FF_99 : label is "ENABLED";
+    attribute GSR of FF_98 : label is "ENABLED";
+    attribute GSR of FF_97 : label is "ENABLED";
+    attribute GSR of FF_96 : label is "ENABLED";
+    attribute GSR of FF_95 : label is "ENABLED";
+    attribute GSR of FF_94 : label is "ENABLED";
+    attribute GSR of FF_93 : label is "ENABLED";
+    attribute GSR of FF_92 : label is "ENABLED";
+    attribute GSR of FF_91 : label is "ENABLED";
+    attribute GSR of FF_90 : label is "ENABLED";
+    attribute GSR of FF_89 : label is "ENABLED";
+    attribute GSR of FF_88 : label is "ENABLED";
+    attribute GSR of FF_87 : label is "ENABLED";
+    attribute GSR of FF_86 : label is "ENABLED";
+    attribute GSR of FF_85 : label is "ENABLED";
+    attribute GSR of FF_84 : label is "ENABLED";
+    attribute GSR of FF_83 : label is "ENABLED";
+    attribute GSR of FF_82 : label is "ENABLED";
+    attribute GSR of FF_81 : label is "ENABLED";
+    attribute GSR of FF_80 : label is "ENABLED";
+    attribute GSR of FF_79 : label is "ENABLED";
+    attribute GSR of FF_78 : label is "ENABLED";
+    attribute GSR of FF_77 : label is "ENABLED";
+    attribute GSR of FF_76 : label is "ENABLED";
+    attribute GSR of FF_75 : label is "ENABLED";
+    attribute GSR of FF_74 : label is "ENABLED";
+    attribute GSR of FF_73 : label is "ENABLED";
+    attribute GSR of FF_72 : label is "ENABLED";
+    attribute GSR of FF_71 : label is "ENABLED";
+    attribute GSR of FF_70 : label is "ENABLED";
+    attribute GSR of FF_69 : label is "ENABLED";
+    attribute GSR of FF_68 : label is "ENABLED";
+    attribute GSR of FF_67 : label is "ENABLED";
+    attribute GSR of FF_66 : label is "ENABLED";
+    attribute GSR of FF_65 : label is "ENABLED";
+    attribute GSR of FF_64 : label is "ENABLED";
+    attribute GSR of FF_63 : label is "ENABLED";
+    attribute GSR of FF_62 : label is "ENABLED";
+    attribute GSR of FF_61 : label is "ENABLED";
+    attribute GSR of FF_60 : label is "ENABLED";
+    attribute GSR of FF_59 : label is "ENABLED";
+    attribute GSR of FF_58 : label is "ENABLED";
+    attribute GSR of FF_57 : label is "ENABLED";
+    attribute GSR of FF_56 : label is "ENABLED";
+    attribute GSR of FF_55 : label is "ENABLED";
+    attribute GSR of FF_54 : label is "ENABLED";
+    attribute GSR of FF_53 : label is "ENABLED";
+    attribute GSR of FF_52 : label is "ENABLED";
+    attribute GSR of FF_51 : label is "ENABLED";
+    attribute GSR of FF_50 : label is "ENABLED";
+    attribute GSR of FF_49 : label is "ENABLED";
+    attribute GSR of FF_48 : label is "ENABLED";
+    attribute GSR of FF_47 : label is "ENABLED";
+    attribute GSR of FF_46 : label is "ENABLED";
+    attribute GSR of FF_45 : label is "ENABLED";
+    attribute GSR of FF_44 : label is "ENABLED";
+    attribute GSR of FF_43 : label is "ENABLED";
+    attribute GSR of FF_42 : label is "ENABLED";
+    attribute GSR of FF_41 : label is "ENABLED";
+    attribute GSR of FF_40 : label is "ENABLED";
+    attribute GSR of FF_39 : label is "ENABLED";
+    attribute GSR of FF_38 : label is "ENABLED";
+    attribute GSR of FF_37 : label is "ENABLED";
+    attribute GSR of FF_36 : label is "ENABLED";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t20: AND2
+        port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+    INV_1: INV
+        port map (A=>full_i, Z=>invout_1);
+
+    AND2_t19: AND2
+        port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+    INV_0: INV
+        port map (A=>empty_i, Z=>invout_0);
+
+    OR2_t18: OR2
+        port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+    XOR2_t17: XOR2
+        port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+    XOR2_t16: XOR2
+        port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+    XOR2_t15: XOR2
+        port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+    XOR2_t14: XOR2
+        port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+    XOR2_t13: XOR2
+        port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+    XOR2_t12: XOR2
+        port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
+
+    XOR2_t11: XOR2
+        port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
+
+    XOR2_t10: XOR2
+        port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
+
+    XOR2_t9: XOR2
+        port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
+
+    XOR2_t8: XOR2
+        port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+    XOR2_t7: XOR2
+        port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+    XOR2_t6: XOR2
+        port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+    XOR2_t5: XOR2
+        port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+    XOR2_t4: XOR2
+        port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+    XOR2_t3: XOR2
+        port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
+
+    XOR2_t2: XOR2
+        port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
+
+    XOR2_t1: XOR2
+        port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
+
+    XOR2_t0: XOR2
+        port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
+
+    LUT4_23: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, 
+            AD1=>w_gcount_r28, AD0=>w_gcount_r29, 
+            DO0=>w_g2b_xor_cluster_0);
+
+    LUT4_22: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, 
+            AD1=>w_gcount_r24, AD0=>w_gcount_r25, 
+            DO0=>w_g2b_xor_cluster_1);
+
+    LUT4_21: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>wcount_r8);
+
+    LUT4_20: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, 
+            AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7);
+
+    LUT4_19: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, 
+            AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
+
+    LUT4_18: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, 
+            AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
+
+    LUT4_17: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, 
+            AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3);
+
+    LUT4_16: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2);
+
+    LUT4_15: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1);
+
+    LUT4_14: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0);
+
+    LUT4_13: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, 
+            AD1=>r_gcount_w28, AD0=>r_gcount_w29, 
+            DO0=>r_g2b_xor_cluster_0);
+
+    LUT4_12: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, 
+            AD1=>r_gcount_w24, AD0=>r_gcount_w25, 
+            DO0=>r_g2b_xor_cluster_1);
+
+    LUT4_11: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>rcount_w8);
+
+    LUT4_10: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, 
+            AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7);
+
+    LUT4_9: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, 
+            AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
+
+    LUT4_8: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, 
+            AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
+
+    LUT4_7: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, 
+            AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3);
+
+    LUT4_6: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2);
+
+    LUT4_5: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1);
+
+    LUT4_4: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0);
+
+    LUT4_3: ROM16X1A
+        generic map (initval=> X"0410")
+        port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+    LUT4_2: ROM16X1A
+        generic map (initval=> X"1004")
+        port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"0140")
+        port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, 
+            AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"4001")
+        port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, 
+            AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+    pdp_ram_0_0_2: PDPW16KC
+        generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", 
+        REGMODE=> "NOREG", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
+        port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), 
+            DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), 
+            DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), 
+            DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), 
+            DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), 
+            DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), 
+            DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), 
+            DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), 
+            DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), 
+            DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), 
+            DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0, 
+            ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4, 
+            ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>wptr_8, 
+            BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, 
+            BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, 
+            CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, 
+            ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, 
+            ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, 
+            ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, 
+            ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock, 
+            CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, 
+            RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), 
+            DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), 
+            DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), 
+            DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), DO16=>Q(34), 
+            DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), 
+            DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), 
+            DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), 
+            DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), 
+            DO35=>Q(17));
+
+    pdp_ram_0_1_1: PDPW16KC
+        generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", 
+        REGMODE=> "NOREG", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
+        port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), 
+            DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42), 
+            DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46), 
+            DI11=>Data(47), DI12=>Data(48), DI13=>Data(49), 
+            DI14=>Data(50), DI15=>Data(51), DI16=>Data(52), 
+            DI17=>Data(53), DI18=>Data(54), DI19=>Data(55), 
+            DI20=>Data(56), DI21=>Data(57), DI22=>Data(58), 
+            DI23=>Data(59), DI24=>Data(60), DI25=>Data(61), 
+            DI26=>Data(62), DI27=>Data(63), DI28=>Data(64), 
+            DI29=>Data(65), DI30=>Data(66), DI31=>Data(67), 
+            DI32=>Data(68), DI33=>Data(69), DI34=>Data(70), 
+            DI35=>Data(71), ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, 
+            ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, 
+            ADW7=>wptr_7, ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, 
+            BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, 
+            CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo, 
+            ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo, 
+            ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, 
+            ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, 
+            ADR11=>rptr_6, ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, 
+            CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, 
+            CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(54), DO1=>Q(55), 
+            DO2=>Q(56), DO3=>Q(57), DO4=>Q(58), DO5=>Q(59), DO6=>Q(60), 
+            DO7=>Q(61), DO8=>Q(62), DO9=>Q(63), DO10=>Q(64), DO11=>Q(65), 
+            DO12=>Q(66), DO13=>Q(67), DO14=>Q(68), DO15=>Q(69), 
+            DO16=>Q(70), DO17=>Q(71), DO18=>Q(36), DO19=>Q(37), 
+            DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41), 
+            DO24=>Q(42), DO25=>Q(43), DO26=>Q(44), DO27=>Q(45), 
+            DO28=>Q(46), DO29=>Q(47), DO30=>Q(48), DO31=>Q(49), 
+            DO32=>Q(50), DO33=>Q(51), DO34=>Q(52), DO35=>Q(53));
+
+    pdp_ram_0_2_0: PDPW16KC
+        generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", 
+        REGMODE=> "NOREG", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
+        port map (DI0=>Data(72), DI1=>Data(73), DI2=>Data(74), 
+            DI3=>Data(75), DI4=>Data(76), DI5=>Data(77), DI6=>Data(78), 
+            DI7=>Data(79), DI8=>Data(80), DI9=>Data(81), DI10=>Data(82), 
+            DI11=>Data(83), DI12=>Data(84), DI13=>Data(85), 
+            DI14=>Data(86), DI15=>Data(87), DI16=>Data(88), 
+            DI17=>Data(89), DI18=>Data(90), DI19=>Data(91), 
+            DI20=>Data(92), DI21=>Data(93), DI22=>Data(94), 
+            DI23=>Data(95), DI24=>Data(96), DI25=>Data(97), 
+            DI26=>Data(98), DI27=>scuba_vlo, DI28=>scuba_vlo, 
+            DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo, 
+            DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo, 
+            DI35=>scuba_vlo, ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, 
+            ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, 
+            ADW7=>wptr_7, ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, 
+            BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, 
+            CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo, 
+            ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo, 
+            ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, 
+            ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, 
+            ADR11=>rptr_6, ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, 
+            CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, 
+            CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(90), DO1=>Q(91), 
+            DO2=>Q(92), DO3=>Q(93), DO4=>Q(94), DO5=>Q(95), DO6=>Q(96), 
+            DO7=>Q(97), DO8=>Q(98), DO9=>open, DO10=>open, DO11=>open, 
+            DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open, 
+            DO17=>open, DO18=>Q(72), DO19=>Q(73), DO20=>Q(74), 
+            DO21=>Q(75), DO22=>Q(76), DO23=>Q(77), DO24=>Q(78), 
+            DO25=>Q(79), DO26=>Q(80), DO27=>Q(81), DO28=>Q(82), 
+            DO29=>Q(83), DO30=>Q(84), DO31=>Q(85), DO32=>Q(86), 
+            DO33=>Q(87), DO34=>Q(88), DO35=>Q(89));
+
+    FF_101: FD1P3BX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>wcount_0);
+
+    FF_100: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_99: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_98: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_97: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_96: FD1P3DX
+        port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_95: FD1P3DX
+        port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_6);
+
+    FF_94: FD1P3DX
+        port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_7);
+
+    FF_93: FD1P3DX
+        port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_8);
+
+    FF_92: FD1P3DX
+        port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_9);
+
+    FF_91: FD1P3DX
+        port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_0);
+
+    FF_90: FD1P3DX
+        port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_1);
+
+    FF_89: FD1P3DX
+        port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_2);
+
+    FF_88: FD1P3DX
+        port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_3);
+
+    FF_87: FD1P3DX
+        port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_4);
+
+    FF_86: FD1P3DX
+        port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_5);
+
+    FF_85: FD1P3DX
+        port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_6);
+
+    FF_84: FD1P3DX
+        port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_7);
+
+    FF_83: FD1P3DX
+        port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_8);
+
+    FF_82: FD1P3DX
+        port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_9);
+
+    FF_81: FD1P3DX
+        port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_0);
+
+    FF_80: FD1P3DX
+        port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_1);
+
+    FF_79: FD1P3DX
+        port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_2);
+
+    FF_78: FD1P3DX
+        port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_3);
+
+    FF_77: FD1P3DX
+        port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_4);
+
+    FF_76: FD1P3DX
+        port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_5);
+
+    FF_75: FD1P3DX
+        port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_6);
+
+    FF_74: FD1P3DX
+        port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_7);
+
+    FF_73: FD1P3DX
+        port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_8);
+
+    FF_72: FD1P3DX
+        port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_9);
+
+    FF_71: FD1P3BX
+        port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, 
+            Q=>rcount_0);
+
+    FF_70: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_1);
+
+    FF_69: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_2);
+
+    FF_68: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_3);
+
+    FF_67: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_4);
+
+    FF_66: FD1P3DX
+        port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_5);
+
+    FF_65: FD1P3DX
+        port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_6);
+
+    FF_64: FD1P3DX
+        port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_7);
+
+    FF_63: FD1P3DX
+        port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_8);
+
+    FF_62: FD1P3DX
+        port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_9);
+
+    FF_61: FD1P3DX
+        port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_0);
+
+    FF_60: FD1P3DX
+        port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_1);
+
+    FF_59: FD1P3DX
+        port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_2);
+
+    FF_58: FD1P3DX
+        port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_3);
+
+    FF_57: FD1P3DX
+        port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_4);
+
+    FF_56: FD1P3DX
+        port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_5);
+
+    FF_55: FD1P3DX
+        port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_6);
+
+    FF_54: FD1P3DX
+        port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_7);
+
+    FF_53: FD1P3DX
+        port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_8);
+
+    FF_52: FD1P3DX
+        port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_9);
+
+    FF_51: FD1P3DX
+        port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_0);
+
+    FF_50: FD1P3DX
+        port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_1);
+
+    FF_49: FD1P3DX
+        port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_2);
+
+    FF_48: FD1P3DX
+        port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_3);
+
+    FF_47: FD1P3DX
+        port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_4);
+
+    FF_46: FD1P3DX
+        port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_5);
+
+    FF_45: FD1P3DX
+        port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_6);
+
+    FF_44: FD1P3DX
+        port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_7);
+
+    FF_43: FD1P3DX
+        port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_8);
+
+    FF_42: FD1P3DX
+        port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_9);
+
+    FF_41: FD1S3DX
+        port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+    FF_40: FD1S3DX
+        port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+    FF_39: FD1S3DX
+        port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+    FF_38: FD1S3DX
+        port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+    FF_37: FD1S3DX
+        port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+    FF_36: FD1S3DX
+        port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+    FF_35: FD1S3DX
+        port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
+
+    FF_34: FD1S3DX
+        port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
+
+    FF_33: FD1S3DX
+        port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
+
+    FF_32: FD1S3DX
+        port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
+
+    FF_31: FD1S3DX
+        port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+    FF_30: FD1S3DX
+        port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+    FF_29: FD1S3DX
+        port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+    FF_28: FD1S3DX
+        port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+    FF_27: FD1S3DX
+        port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+    FF_26: FD1S3DX
+        port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+    FF_25: FD1S3DX
+        port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+    FF_24: FD1S3DX
+        port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
+
+    FF_23: FD1S3DX
+        port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
+
+    FF_22: FD1S3DX
+        port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
+
+    FF_21: FD1S3DX
+        port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r20);
+
+    FF_20: FD1S3DX
+        port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r21);
+
+    FF_19: FD1S3DX
+        port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r22);
+
+    FF_18: FD1S3DX
+        port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r23);
+
+    FF_17: FD1S3DX
+        port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r24);
+
+    FF_16: FD1S3DX
+        port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r25);
+
+    FF_15: FD1S3DX
+        port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r26);
+
+    FF_14: FD1S3DX
+        port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r27);
+
+    FF_13: FD1S3DX
+        port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r28);
+
+    FF_12: FD1S3DX
+        port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r29);
+
+    FF_11: FD1S3DX
+        port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+    FF_10: FD1S3DX
+        port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+    FF_9: FD1S3DX
+        port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+    FF_8: FD1S3DX
+        port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+    FF_7: FD1S3DX
+        port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+    FF_6: FD1S3DX
+        port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+    FF_5: FD1S3DX
+        port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
+
+    FF_4: FD1S3DX
+        port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
+
+    FF_3: FD1S3DX
+        port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
+
+    FF_2: FD1S3DX
+        port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
+
+    FF_1: FD1S3BX
+        port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+    FF_0: FD1S3DX
+        port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+    w_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, 
+            S1=>open);
+
+    w_gctr_0: CU2
+        port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, 
+            NC0=>iwcount_0, NC1=>iwcount_1);
+
+    w_gctr_1: CU2
+        port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, 
+            NC0=>iwcount_2, NC1=>iwcount_3);
+
+    w_gctr_2: CU2
+        port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, 
+            NC0=>iwcount_4, NC1=>iwcount_5);
+
+    w_gctr_3: CU2
+        port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, 
+            NC0=>iwcount_6, NC1=>iwcount_7);
+
+    w_gctr_4: CU2
+        port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, 
+            NC0=>iwcount_8, NC1=>iwcount_9);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    r_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, 
+            S1=>open);
+
+    r_gctr_0: CU2
+        port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, 
+            NC0=>ircount_0, NC1=>ircount_1);
+
+    r_gctr_1: CU2
+        port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, 
+            NC0=>ircount_2, NC1=>ircount_3);
+
+    r_gctr_2: CU2
+        port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, 
+            NC0=>ircount_4, NC1=>ircount_5);
+
+    r_gctr_3: CU2
+        port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, 
+            NC0=>ircount_6, NC1=>ircount_7);
+
+    r_gctr_4: CU2
+        port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, 
+            NC0=>ircount_8, NC1=>ircount_9);
+
+    empty_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+    empty_cmp_0: AGEB2
+        port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, 
+            B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
+
+    empty_cmp_1: AGEB2
+        port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, 
+            B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
+
+    empty_cmp_2: AGEB2
+        port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, 
+            B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
+
+    empty_cmp_3: AGEB2
+        port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0, 
+            B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
+
+    empty_cmp_4: AGEB2
+        port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8, 
+            B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c);
+
+    a0: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, 
+            S1=>open);
+
+    full_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+    full_cmp_0: AGEB2
+        port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, 
+            B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
+
+    full_cmp_1: AGEB2
+        port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, 
+            B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
+
+    full_cmp_2: AGEB2
+        port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, 
+            B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
+
+    full_cmp_3: AGEB2
+        port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, 
+            B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
+
+    full_cmp_4: AGEB2
+        port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8, 
+            B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    a1: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, 
+            S1=>open);
+
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of async_fifo_512x99_ecp3 is
+    for Structure
+        for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+        for all:AND2 use entity ecp3.AND2(V); end for;
+        for all:CU2 use entity ecp3.CU2(V); end for;
+        for all:FADD2B use entity ecp3.FADD2B(V); end for;
+        for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
+        for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+        for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+        for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+        for all:INV use entity ecp3.INV(V); end for;
+        for all:OR2 use entity ecp3.OR2(V); end for;
+        for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+        for all:VHI use entity ecp3.VHI(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+        for all:XOR2 use entity ecp3.XOR2(V); end for;
+        for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_512x99_ecp3_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/async_fifo_512x99_ecp3_tmpl.vhd
new file mode 100644
index 0000000..19b3aa0
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_512x99_ecp3_tmpl.vhd
@@ -0,0 +1,18 @@
+-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.7
+-- Mon Oct 27 14:17:32 2014
+
+-- parameterized module component declaration
+component async_fifo_512x99_ecp3
+    port (Data: in  std_logic_vector(98 downto 0); 
+        WrClock: in  std_logic; RdClock: in  std_logic; 
+        WrEn: in  std_logic; RdEn: in  std_logic; Reset: in  std_logic; 
+        RPReset: in  std_logic; Q: out  std_logic_vector(98 downto 0); 
+        Empty: out  std_logic; Full: out  std_logic);
+end component;
+
+-- parameterized module component instance
+__ : async_fifo_512x99_ecp3
+    port map (Data(98 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, 
+        RdEn=>__, Reset=>__, RPReset=>__, Q(98 downto 0)=>__, Empty=>__, 
+        Full=>__);
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_af_512x32_ecp3.ipx b/data_concentrator/sources/lattice/ecp3/async_fifo_af_512x32_ecp3.ipx
new file mode 100644
index 0000000..f078d0e
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_af_512x32_ecp3.ipx
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="async_fifo_af_512x32_ecp3" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 07 12 15:15:51.127" version="5.4" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="async_fifo_af_512x32_ecp3.lpc" type="lpc" modified="2013 07 12 15:15:48.465"/>
+		<File name="async_fifo_af_512x32_ecp3.vhd" type="top_level_vhdl" modified="2013 07 12 15:15:48.543"/>
+		<File name="async_fifo_af_512x32_ecp3_tmpl.vhd" type="template_vhdl" modified="2013 07 12 15:15:48.544"/>
+		<File name="tb_async_fifo_af_512x32_ecp3_tmpl.vhd" type="testbench_vhdl" modified="2013 07 12 15:15:48.548"/>
+  </Package>
+</DiamondModule>
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_af_512x32_ecp3.lpc b/data_concentrator/sources/lattice/ecp3/async_fifo_af_512x32_ecp3.lpc
new file mode 100644
index 0000000..2fb9e63
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_af_512x32_ecp3.lpc
@@ -0,0 +1,47 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.4
+ModuleName=async_fifo_af_512x32_ecp3
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=07/12/2013
+Time=15:15:48
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=512
+Width=32
+RDepth=512
+RWidth=32
+regout=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=0
+WDataCount=0
+EnECC=0
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_af_512x32_ecp3.vhd b/data_concentrator/sources/lattice/ecp3/async_fifo_af_512x32_ecp3.vhd
new file mode 100644
index 0000000..354c21c
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_af_512x32_ecp3.vhd
@@ -0,0 +1,1350 @@
+-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
+-- Module  Version: 5.4
+--C:\lscc\diamond\2.1_x64\ispfpga\bin\nt64\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 32 -depth 512 -rdata_width 32 -no_enable -pe -1 -pf 508 -e 
+
+-- Fri Jul 12 15:15:48 2013
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity async_fifo_af_512x32_ecp3 is
+    port (
+        Data: in  std_logic_vector(31 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(31 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostFull: out  std_logic);
+end async_fifo_af_512x32_ecp3;
+
+architecture Structure of async_fifo_af_512x32_ecp3 is
+
+    -- internal signal declarations
+    signal invout_1: std_logic;
+    signal invout_0: std_logic;
+    signal w_g2b_xor_cluster_1: std_logic;
+    signal r_g2b_xor_cluster_1: std_logic;
+    signal w_gdata_0: std_logic;
+    signal w_gdata_1: std_logic;
+    signal w_gdata_2: std_logic;
+    signal w_gdata_3: std_logic;
+    signal w_gdata_4: std_logic;
+    signal w_gdata_5: std_logic;
+    signal w_gdata_6: std_logic;
+    signal w_gdata_7: std_logic;
+    signal w_gdata_8: std_logic;
+    signal wptr_0: std_logic;
+    signal wptr_1: std_logic;
+    signal wptr_2: std_logic;
+    signal wptr_3: std_logic;
+    signal wptr_4: std_logic;
+    signal wptr_5: std_logic;
+    signal wptr_6: std_logic;
+    signal wptr_7: std_logic;
+    signal wptr_8: std_logic;
+    signal wptr_9: std_logic;
+    signal r_gdata_0: std_logic;
+    signal r_gdata_1: std_logic;
+    signal r_gdata_2: std_logic;
+    signal r_gdata_3: std_logic;
+    signal r_gdata_4: std_logic;
+    signal r_gdata_5: std_logic;
+    signal r_gdata_6: std_logic;
+    signal r_gdata_7: std_logic;
+    signal r_gdata_8: std_logic;
+    signal rptr_0: std_logic;
+    signal rptr_1: std_logic;
+    signal rptr_2: std_logic;
+    signal rptr_3: std_logic;
+    signal rptr_4: std_logic;
+    signal rptr_5: std_logic;
+    signal rptr_6: std_logic;
+    signal rptr_7: std_logic;
+    signal rptr_8: std_logic;
+    signal rptr_9: std_logic;
+    signal w_gcount_0: std_logic;
+    signal w_gcount_1: std_logic;
+    signal w_gcount_2: std_logic;
+    signal w_gcount_3: std_logic;
+    signal w_gcount_4: std_logic;
+    signal w_gcount_5: std_logic;
+    signal w_gcount_6: std_logic;
+    signal w_gcount_7: std_logic;
+    signal w_gcount_8: std_logic;
+    signal w_gcount_9: std_logic;
+    signal r_gcount_0: std_logic;
+    signal r_gcount_1: std_logic;
+    signal r_gcount_2: std_logic;
+    signal r_gcount_3: std_logic;
+    signal r_gcount_4: std_logic;
+    signal r_gcount_5: std_logic;
+    signal r_gcount_6: std_logic;
+    signal r_gcount_7: std_logic;
+    signal r_gcount_8: std_logic;
+    signal r_gcount_9: std_logic;
+    signal w_gcount_r20: std_logic;
+    signal w_gcount_r0: std_logic;
+    signal w_gcount_r21: std_logic;
+    signal w_gcount_r1: std_logic;
+    signal w_gcount_r22: std_logic;
+    signal w_gcount_r2: std_logic;
+    signal w_gcount_r23: std_logic;
+    signal w_gcount_r3: std_logic;
+    signal w_gcount_r24: std_logic;
+    signal w_gcount_r4: std_logic;
+    signal w_gcount_r25: std_logic;
+    signal w_gcount_r5: std_logic;
+    signal w_gcount_r26: std_logic;
+    signal w_gcount_r6: std_logic;
+    signal w_gcount_r27: std_logic;
+    signal w_gcount_r7: std_logic;
+    signal w_gcount_r28: std_logic;
+    signal w_gcount_r8: std_logic;
+    signal w_gcount_r29: std_logic;
+    signal w_gcount_r9: std_logic;
+    signal r_gcount_w20: std_logic;
+    signal r_gcount_w0: std_logic;
+    signal r_gcount_w21: std_logic;
+    signal r_gcount_w1: std_logic;
+    signal r_gcount_w22: std_logic;
+    signal r_gcount_w2: std_logic;
+    signal r_gcount_w23: std_logic;
+    signal r_gcount_w3: std_logic;
+    signal r_gcount_w24: std_logic;
+    signal r_gcount_w4: std_logic;
+    signal r_gcount_w25: std_logic;
+    signal r_gcount_w5: std_logic;
+    signal r_gcount_w26: std_logic;
+    signal r_gcount_w6: std_logic;
+    signal r_gcount_w27: std_logic;
+    signal r_gcount_w7: std_logic;
+    signal r_gcount_w28: std_logic;
+    signal r_gcount_w8: std_logic;
+    signal r_gcount_w29: std_logic;
+    signal r_gcount_w9: std_logic;
+    signal empty_i: std_logic;
+    signal rRst: std_logic;
+    signal full_i: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_gctr_ci: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co0: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal co1: std_logic;
+    signal iwcount_6: std_logic;
+    signal iwcount_7: std_logic;
+    signal co2: std_logic;
+    signal iwcount_8: std_logic;
+    signal iwcount_9: std_logic;
+    signal co4: std_logic;
+    signal wcount_9: std_logic;
+    signal co3: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_gctr_ci: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co0_1: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal co1_1: std_logic;
+    signal ircount_6: std_logic;
+    signal ircount_7: std_logic;
+    signal co2_1: std_logic;
+    signal ircount_8: std_logic;
+    signal ircount_9: std_logic;
+    signal co4_1: std_logic;
+    signal rcount_9: std_logic;
+    signal co3_1: std_logic;
+    signal rden_i: std_logic;
+    signal cmp_ci: std_logic;
+    signal wcount_r0: std_logic;
+    signal wcount_r1: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal co0_2: std_logic;
+    signal wcount_r2: std_logic;
+    signal wcount_r3: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal co1_2: std_logic;
+    signal wcount_r4: std_logic;
+    signal wcount_r5: std_logic;
+    signal rcount_4: std_logic;
+    signal rcount_5: std_logic;
+    signal co2_2: std_logic;
+    signal w_g2b_xor_cluster_0: std_logic;
+    signal wcount_r7: std_logic;
+    signal rcount_6: std_logic;
+    signal rcount_7: std_logic;
+    signal co3_2: std_logic;
+    signal wcount_r8: std_logic;
+    signal empty_cmp_clr: std_logic;
+    signal rcount_8: std_logic;
+    signal empty_cmp_set: std_logic;
+    signal empty_d: std_logic;
+    signal empty_d_c: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal wcount_0: std_logic;
+    signal wcount_1: std_logic;
+    signal co0_3: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_3: std_logic;
+    signal co1_3: std_logic;
+    signal wcount_4: std_logic;
+    signal wcount_5: std_logic;
+    signal co2_3: std_logic;
+    signal wcount_6: std_logic;
+    signal wcount_7: std_logic;
+    signal co3_3: std_logic;
+    signal full_cmp_clr: std_logic;
+    signal wcount_8: std_logic;
+    signal full_cmp_set: std_logic;
+    signal full_d: std_logic;
+    signal full_d_c: std_logic;
+    signal scuba_vhi: std_logic;
+    signal iaf_setcount_0: std_logic;
+    signal iaf_setcount_1: std_logic;
+    signal af_set_ctr_ci: std_logic;
+    signal iaf_setcount_2: std_logic;
+    signal iaf_setcount_3: std_logic;
+    signal co0_4: std_logic;
+    signal iaf_setcount_4: std_logic;
+    signal iaf_setcount_5: std_logic;
+    signal co1_4: std_logic;
+    signal iaf_setcount_6: std_logic;
+    signal iaf_setcount_7: std_logic;
+    signal co2_4: std_logic;
+    signal iaf_setcount_8: std_logic;
+    signal iaf_setcount_9: std_logic;
+    signal co4_2: std_logic;
+    signal af_setcount_9: std_logic;
+    signal co3_4: std_logic;
+    signal wren_i: std_logic;
+    signal cmp_ci_2: std_logic;
+    signal rcount_w0: std_logic;
+    signal rcount_w1: std_logic;
+    signal af_setcount_0: std_logic;
+    signal af_setcount_1: std_logic;
+    signal co0_5: std_logic;
+    signal rcount_w2: std_logic;
+    signal rcount_w3: std_logic;
+    signal af_setcount_2: std_logic;
+    signal af_setcount_3: std_logic;
+    signal co1_5: std_logic;
+    signal rcount_w4: std_logic;
+    signal rcount_w5: std_logic;
+    signal af_setcount_4: std_logic;
+    signal af_setcount_5: std_logic;
+    signal co2_5: std_logic;
+    signal r_g2b_xor_cluster_0: std_logic;
+    signal rcount_w7: std_logic;
+    signal af_setcount_6: std_logic;
+    signal af_setcount_7: std_logic;
+    signal co3_5: std_logic;
+    signal rcount_w8: std_logic;
+    signal af_set_cmp_clr: std_logic;
+    signal af_setcount_8: std_logic;
+    signal af_set_cmp_set: std_logic;
+    signal af_set: std_logic;
+    signal af_set_c: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component AGEB2
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; GE: out  std_logic);
+    end component;
+    component AND2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component CU2
+        port (CI: in  std_logic; PC0: in  std_logic; PC1: in  std_logic; 
+            CO: out  std_logic; NC0: out  std_logic; NC1: out  std_logic);
+    end component;
+    component FADD2B
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; COUT: out  std_logic; 
+            S0: out  std_logic; S1: out  std_logic);
+    end component;
+    component FD1P3BX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            PD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1P3DX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            CD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1S3BX
+        port (D: in  std_logic; CK: in  std_logic; PD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component FD1S3DX
+        port (D: in  std_logic; CK: in  std_logic; CD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component INV
+        port (A: in  std_logic; Z: out  std_logic);
+    end component;
+    component OR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component ROM16X1A
+        generic (INITVAL : in std_logic_vector(15 downto 0));
+        port (AD3: in  std_logic; AD2: in  std_logic; AD1: in  std_logic; 
+            AD0: in  std_logic; DO0: out  std_logic);
+    end component;
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component XOR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component PDPW16KC
+        generic (GSR : in String; CSDECODE_R : in String; 
+                CSDECODE_W : in String; REGMODE : in String; 
+                DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+        port (DI0: in  std_logic; DI1: in  std_logic; DI2: in  std_logic; 
+            DI3: in  std_logic; DI4: in  std_logic; DI5: in  std_logic; 
+            DI6: in  std_logic; DI7: in  std_logic; DI8: in  std_logic; 
+            DI9: in  std_logic; DI10: in  std_logic; DI11: in  std_logic; 
+            DI12: in  std_logic; DI13: in  std_logic; 
+            DI14: in  std_logic; DI15: in  std_logic; 
+            DI16: in  std_logic; DI17: in  std_logic; 
+            DI18: in  std_logic; DI19: in  std_logic; 
+            DI20: in  std_logic; DI21: in  std_logic; 
+            DI22: in  std_logic; DI23: in  std_logic; 
+            DI24: in  std_logic; DI25: in  std_logic; 
+            DI26: in  std_logic; DI27: in  std_logic; 
+            DI28: in  std_logic; DI29: in  std_logic; 
+            DI30: in  std_logic; DI31: in  std_logic; 
+            DI32: in  std_logic; DI33: in  std_logic; 
+            DI34: in  std_logic; DI35: in  std_logic; 
+            ADW0: in  std_logic; ADW1: in  std_logic; 
+            ADW2: in  std_logic; ADW3: in  std_logic; 
+            ADW4: in  std_logic; ADW5: in  std_logic; 
+            ADW6: in  std_logic; ADW7: in  std_logic; 
+            ADW8: in  std_logic; BE0: in  std_logic; BE1: in  std_logic; 
+            BE2: in  std_logic; BE3: in  std_logic; CEW: in  std_logic; 
+            CLKW: in  std_logic; CSW0: in  std_logic; 
+            CSW1: in  std_logic; CSW2: in  std_logic; 
+            ADR0: in  std_logic; ADR1: in  std_logic; 
+            ADR2: in  std_logic; ADR3: in  std_logic; 
+            ADR4: in  std_logic; ADR5: in  std_logic; 
+            ADR6: in  std_logic; ADR7: in  std_logic; 
+            ADR8: in  std_logic; ADR9: in  std_logic; 
+            ADR10: in  std_logic; ADR11: in  std_logic; 
+            ADR12: in  std_logic; ADR13: in  std_logic; 
+            CER: in  std_logic; CLKR: in  std_logic; CSR0: in  std_logic; 
+            CSR1: in  std_logic; CSR2: in  std_logic; RST: in  std_logic; 
+            DO0: out  std_logic; DO1: out  std_logic; 
+            DO2: out  std_logic; DO3: out  std_logic; 
+            DO4: out  std_logic; DO5: out  std_logic; 
+            DO6: out  std_logic; DO7: out  std_logic; 
+            DO8: out  std_logic; DO9: out  std_logic; 
+            DO10: out  std_logic; DO11: out  std_logic; 
+            DO12: out  std_logic; DO13: out  std_logic; 
+            DO14: out  std_logic; DO15: out  std_logic; 
+            DO16: out  std_logic; DO17: out  std_logic; 
+            DO18: out  std_logic; DO19: out  std_logic; 
+            DO20: out  std_logic; DO21: out  std_logic; 
+            DO22: out  std_logic; DO23: out  std_logic; 
+            DO24: out  std_logic; DO25: out  std_logic; 
+            DO26: out  std_logic; DO27: out  std_logic; 
+            DO28: out  std_logic; DO29: out  std_logic; 
+            DO30: out  std_logic; DO31: out  std_logic; 
+            DO32: out  std_logic; DO33: out  std_logic; 
+            DO34: out  std_logic; DO35: out  std_logic);
+    end component;
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute RESETMODE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "async_fifo_af_512x32_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+    attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
+    attribute GSR of FF_112 : label is "ENABLED";
+    attribute GSR of FF_111 : label is "ENABLED";
+    attribute GSR of FF_110 : label is "ENABLED";
+    attribute GSR of FF_109 : label is "ENABLED";
+    attribute GSR of FF_108 : label is "ENABLED";
+    attribute GSR of FF_107 : label is "ENABLED";
+    attribute GSR of FF_106 : label is "ENABLED";
+    attribute GSR of FF_105 : label is "ENABLED";
+    attribute GSR of FF_104 : label is "ENABLED";
+    attribute GSR of FF_103 : label is "ENABLED";
+    attribute GSR of FF_102 : label is "ENABLED";
+    attribute GSR of FF_101 : label is "ENABLED";
+    attribute GSR of FF_100 : label is "ENABLED";
+    attribute GSR of FF_99 : label is "ENABLED";
+    attribute GSR of FF_98 : label is "ENABLED";
+    attribute GSR of FF_97 : label is "ENABLED";
+    attribute GSR of FF_96 : label is "ENABLED";
+    attribute GSR of FF_95 : label is "ENABLED";
+    attribute GSR of FF_94 : label is "ENABLED";
+    attribute GSR of FF_93 : label is "ENABLED";
+    attribute GSR of FF_92 : label is "ENABLED";
+    attribute GSR of FF_91 : label is "ENABLED";
+    attribute GSR of FF_90 : label is "ENABLED";
+    attribute GSR of FF_89 : label is "ENABLED";
+    attribute GSR of FF_88 : label is "ENABLED";
+    attribute GSR of FF_87 : label is "ENABLED";
+    attribute GSR of FF_86 : label is "ENABLED";
+    attribute GSR of FF_85 : label is "ENABLED";
+    attribute GSR of FF_84 : label is "ENABLED";
+    attribute GSR of FF_83 : label is "ENABLED";
+    attribute GSR of FF_82 : label is "ENABLED";
+    attribute GSR of FF_81 : label is "ENABLED";
+    attribute GSR of FF_80 : label is "ENABLED";
+    attribute GSR of FF_79 : label is "ENABLED";
+    attribute GSR of FF_78 : label is "ENABLED";
+    attribute GSR of FF_77 : label is "ENABLED";
+    attribute GSR of FF_76 : label is "ENABLED";
+    attribute GSR of FF_75 : label is "ENABLED";
+    attribute GSR of FF_74 : label is "ENABLED";
+    attribute GSR of FF_73 : label is "ENABLED";
+    attribute GSR of FF_72 : label is "ENABLED";
+    attribute GSR of FF_71 : label is "ENABLED";
+    attribute GSR of FF_70 : label is "ENABLED";
+    attribute GSR of FF_69 : label is "ENABLED";
+    attribute GSR of FF_68 : label is "ENABLED";
+    attribute GSR of FF_67 : label is "ENABLED";
+    attribute GSR of FF_66 : label is "ENABLED";
+    attribute GSR of FF_65 : label is "ENABLED";
+    attribute GSR of FF_64 : label is "ENABLED";
+    attribute GSR of FF_63 : label is "ENABLED";
+    attribute GSR of FF_62 : label is "ENABLED";
+    attribute GSR of FF_61 : label is "ENABLED";
+    attribute GSR of FF_60 : label is "ENABLED";
+    attribute GSR of FF_59 : label is "ENABLED";
+    attribute GSR of FF_58 : label is "ENABLED";
+    attribute GSR of FF_57 : label is "ENABLED";
+    attribute GSR of FF_56 : label is "ENABLED";
+    attribute GSR of FF_55 : label is "ENABLED";
+    attribute GSR of FF_54 : label is "ENABLED";
+    attribute GSR of FF_53 : label is "ENABLED";
+    attribute GSR of FF_52 : label is "ENABLED";
+    attribute GSR of FF_51 : label is "ENABLED";
+    attribute GSR of FF_50 : label is "ENABLED";
+    attribute GSR of FF_49 : label is "ENABLED";
+    attribute GSR of FF_48 : label is "ENABLED";
+    attribute GSR of FF_47 : label is "ENABLED";
+    attribute GSR of FF_46 : label is "ENABLED";
+    attribute GSR of FF_45 : label is "ENABLED";
+    attribute GSR of FF_44 : label is "ENABLED";
+    attribute GSR of FF_43 : label is "ENABLED";
+    attribute GSR of FF_42 : label is "ENABLED";
+    attribute GSR of FF_41 : label is "ENABLED";
+    attribute GSR of FF_40 : label is "ENABLED";
+    attribute GSR of FF_39 : label is "ENABLED";
+    attribute GSR of FF_38 : label is "ENABLED";
+    attribute GSR of FF_37 : label is "ENABLED";
+    attribute GSR of FF_36 : label is "ENABLED";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t20: AND2
+        port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+    INV_1: INV
+        port map (A=>full_i, Z=>invout_1);
+
+    AND2_t19: AND2
+        port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+    INV_0: INV
+        port map (A=>empty_i, Z=>invout_0);
+
+    OR2_t18: OR2
+        port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+    XOR2_t17: XOR2
+        port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+    XOR2_t16: XOR2
+        port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+    XOR2_t15: XOR2
+        port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+    XOR2_t14: XOR2
+        port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+    XOR2_t13: XOR2
+        port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+    XOR2_t12: XOR2
+        port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
+
+    XOR2_t11: XOR2
+        port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
+
+    XOR2_t10: XOR2
+        port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
+
+    XOR2_t9: XOR2
+        port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
+
+    XOR2_t8: XOR2
+        port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+    XOR2_t7: XOR2
+        port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+    XOR2_t6: XOR2
+        port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+    XOR2_t5: XOR2
+        port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+    XOR2_t4: XOR2
+        port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+    XOR2_t3: XOR2
+        port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
+
+    XOR2_t2: XOR2
+        port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
+
+    XOR2_t1: XOR2
+        port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
+
+    XOR2_t0: XOR2
+        port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
+
+    LUT4_25: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, 
+            AD1=>w_gcount_r28, AD0=>w_gcount_r29, 
+            DO0=>w_g2b_xor_cluster_0);
+
+    LUT4_24: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, 
+            AD1=>w_gcount_r24, AD0=>w_gcount_r25, 
+            DO0=>w_g2b_xor_cluster_1);
+
+    LUT4_23: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>wcount_r8);
+
+    LUT4_22: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, 
+            AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7);
+
+    LUT4_21: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, 
+            AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
+
+    LUT4_20: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, 
+            AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
+
+    LUT4_19: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, 
+            AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3);
+
+    LUT4_18: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2);
+
+    LUT4_17: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1);
+
+    LUT4_16: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0);
+
+    LUT4_15: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, 
+            AD1=>r_gcount_w28, AD0=>r_gcount_w29, 
+            DO0=>r_g2b_xor_cluster_0);
+
+    LUT4_14: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, 
+            AD1=>r_gcount_w24, AD0=>r_gcount_w25, 
+            DO0=>r_g2b_xor_cluster_1);
+
+    LUT4_13: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>rcount_w8);
+
+    LUT4_12: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, 
+            AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7);
+
+    LUT4_11: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, 
+            AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
+
+    LUT4_10: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, 
+            AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
+
+    LUT4_9: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, 
+            AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3);
+
+    LUT4_8: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2);
+
+    LUT4_7: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1);
+
+    LUT4_6: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0);
+
+    LUT4_5: ROM16X1A
+        generic map (initval=> X"0410")
+        port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+    LUT4_4: ROM16X1A
+        generic map (initval=> X"1004")
+        port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+    LUT4_3: ROM16X1A
+        generic map (initval=> X"0140")
+        port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, 
+            AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+    LUT4_2: ROM16X1A
+        generic map (initval=> X"4001")
+        port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, 
+            AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"4c32")
+        port map (AD3=>af_setcount_9, AD2=>wcount_9, AD1=>r_gcount_w29, 
+            AD0=>wptr_9, DO0=>af_set_cmp_set);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"8001")
+        port map (AD3=>af_setcount_9, AD2=>wcount_9, AD1=>r_gcount_w29, 
+            AD0=>wptr_9, DO0=>af_set_cmp_clr);
+
+    pdp_ram_0_0_0: PDPW16KC
+        generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", 
+        REGMODE=> "NOREG", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
+        port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), 
+            DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), 
+            DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), 
+            DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), 
+            DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), 
+            DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), 
+            DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), 
+            DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), 
+            DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), 
+            DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo, 
+            DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, 
+            ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, 
+            ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, 
+            ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, 
+            BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, 
+            CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, 
+            ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, 
+            ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, 
+            ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, 
+            ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock, 
+            CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, 
+            RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), 
+            DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), 
+            DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), 
+            DO13=>Q(31), DO14=>open, DO15=>open, DO16=>open, DO17=>open, 
+            DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), 
+            DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), 
+            DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), 
+            DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), DO35=>Q(17));
+
+    FF_112: FD1P3BX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>wcount_0);
+
+    FF_111: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_110: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_109: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_108: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_107: FD1P3DX
+        port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_106: FD1P3DX
+        port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_6);
+
+    FF_105: FD1P3DX
+        port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_7);
+
+    FF_104: FD1P3DX
+        port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_8);
+
+    FF_103: FD1P3DX
+        port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_9);
+
+    FF_102: FD1P3DX
+        port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_0);
+
+    FF_101: FD1P3DX
+        port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_1);
+
+    FF_100: FD1P3DX
+        port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_2);
+
+    FF_99: FD1P3DX
+        port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_3);
+
+    FF_98: FD1P3DX
+        port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_4);
+
+    FF_97: FD1P3DX
+        port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_5);
+
+    FF_96: FD1P3DX
+        port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_6);
+
+    FF_95: FD1P3DX
+        port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_7);
+
+    FF_94: FD1P3DX
+        port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_8);
+
+    FF_93: FD1P3DX
+        port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_9);
+
+    FF_92: FD1P3DX
+        port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_0);
+
+    FF_91: FD1P3DX
+        port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_1);
+
+    FF_90: FD1P3DX
+        port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_2);
+
+    FF_89: FD1P3DX
+        port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_3);
+
+    FF_88: FD1P3DX
+        port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_4);
+
+    FF_87: FD1P3DX
+        port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_5);
+
+    FF_86: FD1P3DX
+        port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_6);
+
+    FF_85: FD1P3DX
+        port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_7);
+
+    FF_84: FD1P3DX
+        port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_8);
+
+    FF_83: FD1P3DX
+        port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_9);
+
+    FF_82: FD1P3BX
+        port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, 
+            Q=>rcount_0);
+
+    FF_81: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_1);
+
+    FF_80: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_2);
+
+    FF_79: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_3);
+
+    FF_78: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_4);
+
+    FF_77: FD1P3DX
+        port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_5);
+
+    FF_76: FD1P3DX
+        port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_6);
+
+    FF_75: FD1P3DX
+        port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_7);
+
+    FF_74: FD1P3DX
+        port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_8);
+
+    FF_73: FD1P3DX
+        port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_9);
+
+    FF_72: FD1P3DX
+        port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_0);
+
+    FF_71: FD1P3DX
+        port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_1);
+
+    FF_70: FD1P3DX
+        port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_2);
+
+    FF_69: FD1P3DX
+        port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_3);
+
+    FF_68: FD1P3DX
+        port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_4);
+
+    FF_67: FD1P3DX
+        port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_5);
+
+    FF_66: FD1P3DX
+        port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_6);
+
+    FF_65: FD1P3DX
+        port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_7);
+
+    FF_64: FD1P3DX
+        port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_8);
+
+    FF_63: FD1P3DX
+        port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_9);
+
+    FF_62: FD1P3DX
+        port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_0);
+
+    FF_61: FD1P3DX
+        port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_1);
+
+    FF_60: FD1P3DX
+        port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_2);
+
+    FF_59: FD1P3DX
+        port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_3);
+
+    FF_58: FD1P3DX
+        port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_4);
+
+    FF_57: FD1P3DX
+        port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_5);
+
+    FF_56: FD1P3DX
+        port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_6);
+
+    FF_55: FD1P3DX
+        port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_7);
+
+    FF_54: FD1P3DX
+        port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_8);
+
+    FF_53: FD1P3DX
+        port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_9);
+
+    FF_52: FD1S3DX
+        port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+    FF_51: FD1S3DX
+        port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+    FF_50: FD1S3DX
+        port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+    FF_49: FD1S3DX
+        port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+    FF_48: FD1S3DX
+        port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+    FF_47: FD1S3DX
+        port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+    FF_46: FD1S3DX
+        port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
+
+    FF_45: FD1S3DX
+        port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
+
+    FF_44: FD1S3DX
+        port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
+
+    FF_43: FD1S3DX
+        port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
+
+    FF_42: FD1S3DX
+        port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+    FF_41: FD1S3DX
+        port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+    FF_40: FD1S3DX
+        port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+    FF_39: FD1S3DX
+        port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+    FF_38: FD1S3DX
+        port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+    FF_37: FD1S3DX
+        port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+    FF_36: FD1S3DX
+        port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+    FF_35: FD1S3DX
+        port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
+
+    FF_34: FD1S3DX
+        port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
+
+    FF_33: FD1S3DX
+        port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
+
+    FF_32: FD1S3DX
+        port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r20);
+
+    FF_31: FD1S3DX
+        port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r21);
+
+    FF_30: FD1S3DX
+        port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r22);
+
+    FF_29: FD1S3DX
+        port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r23);
+
+    FF_28: FD1S3DX
+        port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r24);
+
+    FF_27: FD1S3DX
+        port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r25);
+
+    FF_26: FD1S3DX
+        port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r26);
+
+    FF_25: FD1S3DX
+        port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r27);
+
+    FF_24: FD1S3DX
+        port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r28);
+
+    FF_23: FD1S3DX
+        port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r29);
+
+    FF_22: FD1S3DX
+        port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+    FF_21: FD1S3DX
+        port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+    FF_20: FD1S3DX
+        port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+    FF_19: FD1S3DX
+        port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+    FF_18: FD1S3DX
+        port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+    FF_17: FD1S3DX
+        port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+    FF_16: FD1S3DX
+        port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
+
+    FF_15: FD1S3DX
+        port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
+
+    FF_14: FD1S3DX
+        port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
+
+    FF_13: FD1S3DX
+        port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
+
+    FF_12: FD1S3BX
+        port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+    FF_11: FD1S3DX
+        port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+    FF_10: FD1P3BX
+        port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>af_setcount_0);
+
+    FF_9: FD1P3DX
+        port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_1);
+
+    FF_8: FD1P3BX
+        port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>af_setcount_2);
+
+    FF_7: FD1P3DX
+        port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_3);
+
+    FF_6: FD1P3DX
+        port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_4);
+
+    FF_5: FD1P3DX
+        port map (D=>iaf_setcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_5);
+
+    FF_4: FD1P3DX
+        port map (D=>iaf_setcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_6);
+
+    FF_3: FD1P3DX
+        port map (D=>iaf_setcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_7);
+
+    FF_2: FD1P3DX
+        port map (D=>iaf_setcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_8);
+
+    FF_1: FD1P3DX
+        port map (D=>iaf_setcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_9);
+
+    FF_0: FD1S3DX
+        port map (D=>af_set, CK=>WrClock, CD=>Reset, Q=>AlmostFull);
+
+    w_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, 
+            S1=>open);
+
+    w_gctr_0: CU2
+        port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, 
+            NC0=>iwcount_0, NC1=>iwcount_1);
+
+    w_gctr_1: CU2
+        port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, 
+            NC0=>iwcount_2, NC1=>iwcount_3);
+
+    w_gctr_2: CU2
+        port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, 
+            NC0=>iwcount_4, NC1=>iwcount_5);
+
+    w_gctr_3: CU2
+        port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, 
+            NC0=>iwcount_6, NC1=>iwcount_7);
+
+    w_gctr_4: CU2
+        port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, 
+            NC0=>iwcount_8, NC1=>iwcount_9);
+
+    r_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, 
+            S1=>open);
+
+    r_gctr_0: CU2
+        port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, 
+            NC0=>ircount_0, NC1=>ircount_1);
+
+    r_gctr_1: CU2
+        port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, 
+            NC0=>ircount_2, NC1=>ircount_3);
+
+    r_gctr_2: CU2
+        port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, 
+            NC0=>ircount_4, NC1=>ircount_5);
+
+    r_gctr_3: CU2
+        port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, 
+            NC0=>ircount_6, NC1=>ircount_7);
+
+    r_gctr_4: CU2
+        port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, 
+            NC0=>ircount_8, NC1=>ircount_9);
+
+    empty_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+    empty_cmp_0: AGEB2
+        port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, 
+            B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
+
+    empty_cmp_1: AGEB2
+        port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, 
+            B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
+
+    empty_cmp_2: AGEB2
+        port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, 
+            B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
+
+    empty_cmp_3: AGEB2
+        port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0, 
+            B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
+
+    empty_cmp_4: AGEB2
+        port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8, 
+            B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c);
+
+    a0: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, 
+            S1=>open);
+
+    full_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+    full_cmp_0: AGEB2
+        port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, 
+            B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
+
+    full_cmp_1: AGEB2
+        port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, 
+            B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
+
+    full_cmp_2: AGEB2
+        port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, 
+            B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
+
+    full_cmp_3: AGEB2
+        port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, 
+            B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
+
+    full_cmp_4: AGEB2
+        port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8, 
+            B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c);
+
+    a1: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, 
+            S1=>open);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    af_set_ctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_set_ctr_ci, S0=>open, 
+            S1=>open);
+
+    af_set_ctr_0: CU2
+        port map (CI=>af_set_ctr_ci, PC0=>af_setcount_0, 
+            PC1=>af_setcount_1, CO=>co0_4, NC0=>iaf_setcount_0, 
+            NC1=>iaf_setcount_1);
+
+    af_set_ctr_1: CU2
+        port map (CI=>co0_4, PC0=>af_setcount_2, PC1=>af_setcount_3, 
+            CO=>co1_4, NC0=>iaf_setcount_2, NC1=>iaf_setcount_3);
+
+    af_set_ctr_2: CU2
+        port map (CI=>co1_4, PC0=>af_setcount_4, PC1=>af_setcount_5, 
+            CO=>co2_4, NC0=>iaf_setcount_4, NC1=>iaf_setcount_5);
+
+    af_set_ctr_3: CU2
+        port map (CI=>co2_4, PC0=>af_setcount_6, PC1=>af_setcount_7, 
+            CO=>co3_4, NC0=>iaf_setcount_6, NC1=>iaf_setcount_7);
+
+    af_set_ctr_4: CU2
+        port map (CI=>co3_4, PC0=>af_setcount_8, PC1=>af_setcount_9, 
+            CO=>co4_2, NC0=>iaf_setcount_8, NC1=>iaf_setcount_9);
+
+    af_set_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
+
+    af_set_cmp_0: AGEB2
+        port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0, 
+            B1=>rcount_w1, CI=>cmp_ci_2, GE=>co0_5);
+
+    af_set_cmp_1: AGEB2
+        port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>rcount_w2, 
+            B1=>rcount_w3, CI=>co0_5, GE=>co1_5);
+
+    af_set_cmp_2: AGEB2
+        port map (A0=>af_setcount_4, A1=>af_setcount_5, B0=>rcount_w4, 
+            B1=>rcount_w5, CI=>co1_5, GE=>co2_5);
+
+    af_set_cmp_3: AGEB2
+        port map (A0=>af_setcount_6, A1=>af_setcount_7, 
+            B0=>r_g2b_xor_cluster_0, B1=>rcount_w7, CI=>co2_5, GE=>co3_5);
+
+    af_set_cmp_4: AGEB2
+        port map (A0=>af_setcount_8, A1=>af_set_cmp_set, B0=>rcount_w8, 
+            B1=>af_set_cmp_clr, CI=>co3_5, GE=>af_set_c);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    a2: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set, 
+            S1=>open);
+
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of async_fifo_af_512x32_ecp3 is
+    for Structure
+        for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+        for all:AND2 use entity ecp3.AND2(V); end for;
+        for all:CU2 use entity ecp3.CU2(V); end for;
+        for all:FADD2B use entity ecp3.FADD2B(V); end for;
+        for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
+        for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+        for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+        for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+        for all:INV use entity ecp3.INV(V); end for;
+        for all:OR2 use entity ecp3.OR2(V); end for;
+        for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+        for all:VHI use entity ecp3.VHI(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+        for all:XOR2 use entity ecp3.XOR2(V); end for;
+        for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_af_512x32_ecp3_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/async_fifo_af_512x32_ecp3_tmpl.vhd
new file mode 100644
index 0000000..ca06621
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_af_512x32_ecp3_tmpl.vhd
@@ -0,0 +1,19 @@
+-- VHDL module instantiation generated by SCUBA Diamond_2.1_Production (100)
+-- Module  Version: 5.4
+-- Fri Jul 12 15:15:48 2013
+
+-- parameterized module component declaration
+component async_fifo_af_512x32_ecp3
+    port (Data: in  std_logic_vector(31 downto 0); 
+        WrClock: in  std_logic; RdClock: in  std_logic; 
+        WrEn: in  std_logic; RdEn: in  std_logic; Reset: in  std_logic; 
+        RPReset: in  std_logic; Q: out  std_logic_vector(31 downto 0); 
+        Empty: out  std_logic; Full: out  std_logic; 
+        AlmostFull: out  std_logic);
+end component;
+
+-- parameterized module component instance
+__ : async_fifo_af_512x32_ecp3
+    port map (Data(31 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, 
+        RdEn=>__, Reset=>__, RPReset=>__, Q(31 downto 0)=>__, Empty=>__, 
+        Full=>__, AlmostFull=>__);
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_af_512x36_ecp3.ipx b/data_concentrator/sources/lattice/ecp3/async_fifo_af_512x36_ecp3.ipx
new file mode 100644
index 0000000..ae3445c
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_af_512x36_ecp3.ipx
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="async_fifo_af_512x36_ecp3" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 07 12 14:50:31.921" version="5.4" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="async_fifo_af_512x36_ecp3.lpc" type="lpc" modified="2013 07 12 14:50:28.587"/>
+		<File name="async_fifo_af_512x36_ecp3.vhd" type="top_level_vhdl" modified="2013 07 12 14:50:28.676"/>
+		<File name="async_fifo_af_512x36_ecp3_tmpl.vhd" type="template_vhdl" modified="2013 07 12 14:50:28.677"/>
+		<File name="tb_async_fifo_af_512x36_ecp3_tmpl.vhd" type="testbench_vhdl" modified="2013 07 12 14:50:28.681"/>
+  </Package>
+</DiamondModule>
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_af_512x36_ecp3.lpc b/data_concentrator/sources/lattice/ecp3/async_fifo_af_512x36_ecp3.lpc
new file mode 100644
index 0000000..75535b9
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_af_512x36_ecp3.lpc
@@ -0,0 +1,47 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.4
+ModuleName=async_fifo_af_512x36_ecp3
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=07/12/2013
+Time=14:50:28
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=512
+Width=36
+RDepth=512
+RWidth=36
+regout=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=503
+PfDeassert=506
+RDataCount=0
+WDataCount=0
+EnECC=0
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_af_512x36_ecp3.vhd b/data_concentrator/sources/lattice/ecp3/async_fifo_af_512x36_ecp3.vhd
new file mode 100644
index 0000000..8f4edb5
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_af_512x36_ecp3.vhd
@@ -0,0 +1,1351 @@
+-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
+-- Module  Version: 5.4
+--C:\lscc\diamond\2.1_x64\ispfpga\bin\nt64\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 36 -depth 512 -rdata_width 36 -no_enable -pe -1 -pf 503 -e 
+
+-- Fri Jul 12 14:50:28 2013
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity async_fifo_af_512x36_ecp3 is
+    port (
+        Data: in  std_logic_vector(35 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(35 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostFull: out  std_logic);
+end async_fifo_af_512x36_ecp3;
+
+architecture Structure of async_fifo_af_512x36_ecp3 is
+
+    -- internal signal declarations
+    signal invout_1: std_logic;
+    signal invout_0: std_logic;
+    signal w_g2b_xor_cluster_1: std_logic;
+    signal r_g2b_xor_cluster_1: std_logic;
+    signal w_gdata_0: std_logic;
+    signal w_gdata_1: std_logic;
+    signal w_gdata_2: std_logic;
+    signal w_gdata_3: std_logic;
+    signal w_gdata_4: std_logic;
+    signal w_gdata_5: std_logic;
+    signal w_gdata_6: std_logic;
+    signal w_gdata_7: std_logic;
+    signal w_gdata_8: std_logic;
+    signal wptr_0: std_logic;
+    signal wptr_1: std_logic;
+    signal wptr_2: std_logic;
+    signal wptr_3: std_logic;
+    signal wptr_4: std_logic;
+    signal wptr_5: std_logic;
+    signal wptr_6: std_logic;
+    signal wptr_7: std_logic;
+    signal wptr_8: std_logic;
+    signal wptr_9: std_logic;
+    signal r_gdata_0: std_logic;
+    signal r_gdata_1: std_logic;
+    signal r_gdata_2: std_logic;
+    signal r_gdata_3: std_logic;
+    signal r_gdata_4: std_logic;
+    signal r_gdata_5: std_logic;
+    signal r_gdata_6: std_logic;
+    signal r_gdata_7: std_logic;
+    signal r_gdata_8: std_logic;
+    signal rptr_0: std_logic;
+    signal rptr_1: std_logic;
+    signal rptr_2: std_logic;
+    signal rptr_3: std_logic;
+    signal rptr_4: std_logic;
+    signal rptr_5: std_logic;
+    signal rptr_6: std_logic;
+    signal rptr_7: std_logic;
+    signal rptr_8: std_logic;
+    signal rptr_9: std_logic;
+    signal w_gcount_0: std_logic;
+    signal w_gcount_1: std_logic;
+    signal w_gcount_2: std_logic;
+    signal w_gcount_3: std_logic;
+    signal w_gcount_4: std_logic;
+    signal w_gcount_5: std_logic;
+    signal w_gcount_6: std_logic;
+    signal w_gcount_7: std_logic;
+    signal w_gcount_8: std_logic;
+    signal w_gcount_9: std_logic;
+    signal r_gcount_0: std_logic;
+    signal r_gcount_1: std_logic;
+    signal r_gcount_2: std_logic;
+    signal r_gcount_3: std_logic;
+    signal r_gcount_4: std_logic;
+    signal r_gcount_5: std_logic;
+    signal r_gcount_6: std_logic;
+    signal r_gcount_7: std_logic;
+    signal r_gcount_8: std_logic;
+    signal r_gcount_9: std_logic;
+    signal w_gcount_r20: std_logic;
+    signal w_gcount_r0: std_logic;
+    signal w_gcount_r21: std_logic;
+    signal w_gcount_r1: std_logic;
+    signal w_gcount_r22: std_logic;
+    signal w_gcount_r2: std_logic;
+    signal w_gcount_r23: std_logic;
+    signal w_gcount_r3: std_logic;
+    signal w_gcount_r24: std_logic;
+    signal w_gcount_r4: std_logic;
+    signal w_gcount_r25: std_logic;
+    signal w_gcount_r5: std_logic;
+    signal w_gcount_r26: std_logic;
+    signal w_gcount_r6: std_logic;
+    signal w_gcount_r27: std_logic;
+    signal w_gcount_r7: std_logic;
+    signal w_gcount_r28: std_logic;
+    signal w_gcount_r8: std_logic;
+    signal w_gcount_r29: std_logic;
+    signal w_gcount_r9: std_logic;
+    signal r_gcount_w20: std_logic;
+    signal r_gcount_w0: std_logic;
+    signal r_gcount_w21: std_logic;
+    signal r_gcount_w1: std_logic;
+    signal r_gcount_w22: std_logic;
+    signal r_gcount_w2: std_logic;
+    signal r_gcount_w23: std_logic;
+    signal r_gcount_w3: std_logic;
+    signal r_gcount_w24: std_logic;
+    signal r_gcount_w4: std_logic;
+    signal r_gcount_w25: std_logic;
+    signal r_gcount_w5: std_logic;
+    signal r_gcount_w26: std_logic;
+    signal r_gcount_w6: std_logic;
+    signal r_gcount_w27: std_logic;
+    signal r_gcount_w7: std_logic;
+    signal r_gcount_w28: std_logic;
+    signal r_gcount_w8: std_logic;
+    signal r_gcount_w29: std_logic;
+    signal r_gcount_w9: std_logic;
+    signal empty_i: std_logic;
+    signal rRst: std_logic;
+    signal full_i: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_gctr_ci: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co0: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal co1: std_logic;
+    signal iwcount_6: std_logic;
+    signal iwcount_7: std_logic;
+    signal co2: std_logic;
+    signal iwcount_8: std_logic;
+    signal iwcount_9: std_logic;
+    signal co4: std_logic;
+    signal wcount_9: std_logic;
+    signal co3: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_gctr_ci: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co0_1: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal co1_1: std_logic;
+    signal ircount_6: std_logic;
+    signal ircount_7: std_logic;
+    signal co2_1: std_logic;
+    signal ircount_8: std_logic;
+    signal ircount_9: std_logic;
+    signal co4_1: std_logic;
+    signal rcount_9: std_logic;
+    signal co3_1: std_logic;
+    signal rden_i: std_logic;
+    signal cmp_ci: std_logic;
+    signal wcount_r0: std_logic;
+    signal wcount_r1: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal co0_2: std_logic;
+    signal wcount_r2: std_logic;
+    signal wcount_r3: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal co1_2: std_logic;
+    signal wcount_r4: std_logic;
+    signal wcount_r5: std_logic;
+    signal rcount_4: std_logic;
+    signal rcount_5: std_logic;
+    signal co2_2: std_logic;
+    signal w_g2b_xor_cluster_0: std_logic;
+    signal wcount_r7: std_logic;
+    signal rcount_6: std_logic;
+    signal rcount_7: std_logic;
+    signal co3_2: std_logic;
+    signal wcount_r8: std_logic;
+    signal empty_cmp_clr: std_logic;
+    signal rcount_8: std_logic;
+    signal empty_cmp_set: std_logic;
+    signal empty_d: std_logic;
+    signal empty_d_c: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal wcount_0: std_logic;
+    signal wcount_1: std_logic;
+    signal co0_3: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_3: std_logic;
+    signal co1_3: std_logic;
+    signal wcount_4: std_logic;
+    signal wcount_5: std_logic;
+    signal co2_3: std_logic;
+    signal wcount_6: std_logic;
+    signal wcount_7: std_logic;
+    signal co3_3: std_logic;
+    signal full_cmp_clr: std_logic;
+    signal wcount_8: std_logic;
+    signal full_cmp_set: std_logic;
+    signal full_d: std_logic;
+    signal full_d_c: std_logic;
+    signal scuba_vhi: std_logic;
+    signal iaf_setcount_0: std_logic;
+    signal iaf_setcount_1: std_logic;
+    signal af_set_ctr_ci: std_logic;
+    signal iaf_setcount_2: std_logic;
+    signal iaf_setcount_3: std_logic;
+    signal co0_4: std_logic;
+    signal iaf_setcount_4: std_logic;
+    signal iaf_setcount_5: std_logic;
+    signal co1_4: std_logic;
+    signal iaf_setcount_6: std_logic;
+    signal iaf_setcount_7: std_logic;
+    signal co2_4: std_logic;
+    signal iaf_setcount_8: std_logic;
+    signal iaf_setcount_9: std_logic;
+    signal co4_2: std_logic;
+    signal af_setcount_9: std_logic;
+    signal co3_4: std_logic;
+    signal wren_i: std_logic;
+    signal cmp_ci_2: std_logic;
+    signal rcount_w0: std_logic;
+    signal rcount_w1: std_logic;
+    signal af_setcount_0: std_logic;
+    signal af_setcount_1: std_logic;
+    signal co0_5: std_logic;
+    signal rcount_w2: std_logic;
+    signal rcount_w3: std_logic;
+    signal af_setcount_2: std_logic;
+    signal af_setcount_3: std_logic;
+    signal co1_5: std_logic;
+    signal rcount_w4: std_logic;
+    signal rcount_w5: std_logic;
+    signal af_setcount_4: std_logic;
+    signal af_setcount_5: std_logic;
+    signal co2_5: std_logic;
+    signal r_g2b_xor_cluster_0: std_logic;
+    signal rcount_w7: std_logic;
+    signal af_setcount_6: std_logic;
+    signal af_setcount_7: std_logic;
+    signal co3_5: std_logic;
+    signal rcount_w8: std_logic;
+    signal af_set_cmp_clr: std_logic;
+    signal af_setcount_8: std_logic;
+    signal af_set_cmp_set: std_logic;
+    signal af_set: std_logic;
+    signal af_set_c: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component AGEB2
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; GE: out  std_logic);
+    end component;
+    component AND2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component CU2
+        port (CI: in  std_logic; PC0: in  std_logic; PC1: in  std_logic; 
+            CO: out  std_logic; NC0: out  std_logic; NC1: out  std_logic);
+    end component;
+    component FADD2B
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; COUT: out  std_logic; 
+            S0: out  std_logic; S1: out  std_logic);
+    end component;
+    component FD1P3BX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            PD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1P3DX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            CD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1S3BX
+        port (D: in  std_logic; CK: in  std_logic; PD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component FD1S3DX
+        port (D: in  std_logic; CK: in  std_logic; CD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component INV
+        port (A: in  std_logic; Z: out  std_logic);
+    end component;
+    component OR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component ROM16X1A
+        generic (INITVAL : in std_logic_vector(15 downto 0));
+        port (AD3: in  std_logic; AD2: in  std_logic; AD1: in  std_logic; 
+            AD0: in  std_logic; DO0: out  std_logic);
+    end component;
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component XOR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component PDPW16KC
+        generic (GSR : in String; CSDECODE_R : in String; 
+                CSDECODE_W : in String; REGMODE : in String; 
+                DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+        port (DI0: in  std_logic; DI1: in  std_logic; DI2: in  std_logic; 
+            DI3: in  std_logic; DI4: in  std_logic; DI5: in  std_logic; 
+            DI6: in  std_logic; DI7: in  std_logic; DI8: in  std_logic; 
+            DI9: in  std_logic; DI10: in  std_logic; DI11: in  std_logic; 
+            DI12: in  std_logic; DI13: in  std_logic; 
+            DI14: in  std_logic; DI15: in  std_logic; 
+            DI16: in  std_logic; DI17: in  std_logic; 
+            DI18: in  std_logic; DI19: in  std_logic; 
+            DI20: in  std_logic; DI21: in  std_logic; 
+            DI22: in  std_logic; DI23: in  std_logic; 
+            DI24: in  std_logic; DI25: in  std_logic; 
+            DI26: in  std_logic; DI27: in  std_logic; 
+            DI28: in  std_logic; DI29: in  std_logic; 
+            DI30: in  std_logic; DI31: in  std_logic; 
+            DI32: in  std_logic; DI33: in  std_logic; 
+            DI34: in  std_logic; DI35: in  std_logic; 
+            ADW0: in  std_logic; ADW1: in  std_logic; 
+            ADW2: in  std_logic; ADW3: in  std_logic; 
+            ADW4: in  std_logic; ADW5: in  std_logic; 
+            ADW6: in  std_logic; ADW7: in  std_logic; 
+            ADW8: in  std_logic; BE0: in  std_logic; BE1: in  std_logic; 
+            BE2: in  std_logic; BE3: in  std_logic; CEW: in  std_logic; 
+            CLKW: in  std_logic; CSW0: in  std_logic; 
+            CSW1: in  std_logic; CSW2: in  std_logic; 
+            ADR0: in  std_logic; ADR1: in  std_logic; 
+            ADR2: in  std_logic; ADR3: in  std_logic; 
+            ADR4: in  std_logic; ADR5: in  std_logic; 
+            ADR6: in  std_logic; ADR7: in  std_logic; 
+            ADR8: in  std_logic; ADR9: in  std_logic; 
+            ADR10: in  std_logic; ADR11: in  std_logic; 
+            ADR12: in  std_logic; ADR13: in  std_logic; 
+            CER: in  std_logic; CLKR: in  std_logic; CSR0: in  std_logic; 
+            CSR1: in  std_logic; CSR2: in  std_logic; RST: in  std_logic; 
+            DO0: out  std_logic; DO1: out  std_logic; 
+            DO2: out  std_logic; DO3: out  std_logic; 
+            DO4: out  std_logic; DO5: out  std_logic; 
+            DO6: out  std_logic; DO7: out  std_logic; 
+            DO8: out  std_logic; DO9: out  std_logic; 
+            DO10: out  std_logic; DO11: out  std_logic; 
+            DO12: out  std_logic; DO13: out  std_logic; 
+            DO14: out  std_logic; DO15: out  std_logic; 
+            DO16: out  std_logic; DO17: out  std_logic; 
+            DO18: out  std_logic; DO19: out  std_logic; 
+            DO20: out  std_logic; DO21: out  std_logic; 
+            DO22: out  std_logic; DO23: out  std_logic; 
+            DO24: out  std_logic; DO25: out  std_logic; 
+            DO26: out  std_logic; DO27: out  std_logic; 
+            DO28: out  std_logic; DO29: out  std_logic; 
+            DO30: out  std_logic; DO31: out  std_logic; 
+            DO32: out  std_logic; DO33: out  std_logic; 
+            DO34: out  std_logic; DO35: out  std_logic);
+    end component;
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute RESETMODE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "async_fifo_af_512x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+    attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
+    attribute GSR of FF_112 : label is "ENABLED";
+    attribute GSR of FF_111 : label is "ENABLED";
+    attribute GSR of FF_110 : label is "ENABLED";
+    attribute GSR of FF_109 : label is "ENABLED";
+    attribute GSR of FF_108 : label is "ENABLED";
+    attribute GSR of FF_107 : label is "ENABLED";
+    attribute GSR of FF_106 : label is "ENABLED";
+    attribute GSR of FF_105 : label is "ENABLED";
+    attribute GSR of FF_104 : label is "ENABLED";
+    attribute GSR of FF_103 : label is "ENABLED";
+    attribute GSR of FF_102 : label is "ENABLED";
+    attribute GSR of FF_101 : label is "ENABLED";
+    attribute GSR of FF_100 : label is "ENABLED";
+    attribute GSR of FF_99 : label is "ENABLED";
+    attribute GSR of FF_98 : label is "ENABLED";
+    attribute GSR of FF_97 : label is "ENABLED";
+    attribute GSR of FF_96 : label is "ENABLED";
+    attribute GSR of FF_95 : label is "ENABLED";
+    attribute GSR of FF_94 : label is "ENABLED";
+    attribute GSR of FF_93 : label is "ENABLED";
+    attribute GSR of FF_92 : label is "ENABLED";
+    attribute GSR of FF_91 : label is "ENABLED";
+    attribute GSR of FF_90 : label is "ENABLED";
+    attribute GSR of FF_89 : label is "ENABLED";
+    attribute GSR of FF_88 : label is "ENABLED";
+    attribute GSR of FF_87 : label is "ENABLED";
+    attribute GSR of FF_86 : label is "ENABLED";
+    attribute GSR of FF_85 : label is "ENABLED";
+    attribute GSR of FF_84 : label is "ENABLED";
+    attribute GSR of FF_83 : label is "ENABLED";
+    attribute GSR of FF_82 : label is "ENABLED";
+    attribute GSR of FF_81 : label is "ENABLED";
+    attribute GSR of FF_80 : label is "ENABLED";
+    attribute GSR of FF_79 : label is "ENABLED";
+    attribute GSR of FF_78 : label is "ENABLED";
+    attribute GSR of FF_77 : label is "ENABLED";
+    attribute GSR of FF_76 : label is "ENABLED";
+    attribute GSR of FF_75 : label is "ENABLED";
+    attribute GSR of FF_74 : label is "ENABLED";
+    attribute GSR of FF_73 : label is "ENABLED";
+    attribute GSR of FF_72 : label is "ENABLED";
+    attribute GSR of FF_71 : label is "ENABLED";
+    attribute GSR of FF_70 : label is "ENABLED";
+    attribute GSR of FF_69 : label is "ENABLED";
+    attribute GSR of FF_68 : label is "ENABLED";
+    attribute GSR of FF_67 : label is "ENABLED";
+    attribute GSR of FF_66 : label is "ENABLED";
+    attribute GSR of FF_65 : label is "ENABLED";
+    attribute GSR of FF_64 : label is "ENABLED";
+    attribute GSR of FF_63 : label is "ENABLED";
+    attribute GSR of FF_62 : label is "ENABLED";
+    attribute GSR of FF_61 : label is "ENABLED";
+    attribute GSR of FF_60 : label is "ENABLED";
+    attribute GSR of FF_59 : label is "ENABLED";
+    attribute GSR of FF_58 : label is "ENABLED";
+    attribute GSR of FF_57 : label is "ENABLED";
+    attribute GSR of FF_56 : label is "ENABLED";
+    attribute GSR of FF_55 : label is "ENABLED";
+    attribute GSR of FF_54 : label is "ENABLED";
+    attribute GSR of FF_53 : label is "ENABLED";
+    attribute GSR of FF_52 : label is "ENABLED";
+    attribute GSR of FF_51 : label is "ENABLED";
+    attribute GSR of FF_50 : label is "ENABLED";
+    attribute GSR of FF_49 : label is "ENABLED";
+    attribute GSR of FF_48 : label is "ENABLED";
+    attribute GSR of FF_47 : label is "ENABLED";
+    attribute GSR of FF_46 : label is "ENABLED";
+    attribute GSR of FF_45 : label is "ENABLED";
+    attribute GSR of FF_44 : label is "ENABLED";
+    attribute GSR of FF_43 : label is "ENABLED";
+    attribute GSR of FF_42 : label is "ENABLED";
+    attribute GSR of FF_41 : label is "ENABLED";
+    attribute GSR of FF_40 : label is "ENABLED";
+    attribute GSR of FF_39 : label is "ENABLED";
+    attribute GSR of FF_38 : label is "ENABLED";
+    attribute GSR of FF_37 : label is "ENABLED";
+    attribute GSR of FF_36 : label is "ENABLED";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t20: AND2
+        port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+    INV_1: INV
+        port map (A=>full_i, Z=>invout_1);
+
+    AND2_t19: AND2
+        port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+    INV_0: INV
+        port map (A=>empty_i, Z=>invout_0);
+
+    OR2_t18: OR2
+        port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+    XOR2_t17: XOR2
+        port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+    XOR2_t16: XOR2
+        port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+    XOR2_t15: XOR2
+        port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+    XOR2_t14: XOR2
+        port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+    XOR2_t13: XOR2
+        port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+    XOR2_t12: XOR2
+        port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
+
+    XOR2_t11: XOR2
+        port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
+
+    XOR2_t10: XOR2
+        port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
+
+    XOR2_t9: XOR2
+        port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
+
+    XOR2_t8: XOR2
+        port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+    XOR2_t7: XOR2
+        port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+    XOR2_t6: XOR2
+        port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+    XOR2_t5: XOR2
+        port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+    XOR2_t4: XOR2
+        port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+    XOR2_t3: XOR2
+        port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
+
+    XOR2_t2: XOR2
+        port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
+
+    XOR2_t1: XOR2
+        port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
+
+    XOR2_t0: XOR2
+        port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
+
+    LUT4_25: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, 
+            AD1=>w_gcount_r28, AD0=>w_gcount_r29, 
+            DO0=>w_g2b_xor_cluster_0);
+
+    LUT4_24: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, 
+            AD1=>w_gcount_r24, AD0=>w_gcount_r25, 
+            DO0=>w_g2b_xor_cluster_1);
+
+    LUT4_23: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>wcount_r8);
+
+    LUT4_22: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, 
+            AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7);
+
+    LUT4_21: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, 
+            AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
+
+    LUT4_20: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, 
+            AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
+
+    LUT4_19: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, 
+            AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3);
+
+    LUT4_18: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2);
+
+    LUT4_17: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1);
+
+    LUT4_16: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0);
+
+    LUT4_15: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, 
+            AD1=>r_gcount_w28, AD0=>r_gcount_w29, 
+            DO0=>r_g2b_xor_cluster_0);
+
+    LUT4_14: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, 
+            AD1=>r_gcount_w24, AD0=>r_gcount_w25, 
+            DO0=>r_g2b_xor_cluster_1);
+
+    LUT4_13: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>rcount_w8);
+
+    LUT4_12: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, 
+            AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7);
+
+    LUT4_11: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, 
+            AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
+
+    LUT4_10: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, 
+            AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
+
+    LUT4_9: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, 
+            AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3);
+
+    LUT4_8: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2);
+
+    LUT4_7: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1);
+
+    LUT4_6: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0);
+
+    LUT4_5: ROM16X1A
+        generic map (initval=> X"0410")
+        port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+    LUT4_4: ROM16X1A
+        generic map (initval=> X"1004")
+        port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+    LUT4_3: ROM16X1A
+        generic map (initval=> X"0140")
+        port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, 
+            AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+    LUT4_2: ROM16X1A
+        generic map (initval=> X"4001")
+        port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, 
+            AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"4c32")
+        port map (AD3=>af_setcount_9, AD2=>wcount_9, AD1=>r_gcount_w29, 
+            AD0=>wptr_9, DO0=>af_set_cmp_set);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"8001")
+        port map (AD3=>af_setcount_9, AD2=>wcount_9, AD1=>r_gcount_w29, 
+            AD0=>wptr_9, DO0=>af_set_cmp_clr);
+
+    pdp_ram_0_0_0: PDPW16KC
+        generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", 
+        REGMODE=> "NOREG", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
+        port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), 
+            DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), 
+            DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), 
+            DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), 
+            DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), 
+            DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), 
+            DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), 
+            DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), 
+            DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), 
+            DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), 
+            DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0, 
+            ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4, 
+            ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>wptr_8, 
+            BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, 
+            BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, 
+            CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, 
+            ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, 
+            ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, 
+            ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, 
+            ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock, 
+            CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, 
+            RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), 
+            DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), 
+            DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), 
+            DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), DO16=>Q(34), 
+            DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), 
+            DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), 
+            DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), 
+            DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), 
+            DO35=>Q(17));
+
+    FF_112: FD1P3BX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>wcount_0);
+
+    FF_111: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_110: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_109: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_108: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_107: FD1P3DX
+        port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_106: FD1P3DX
+        port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_6);
+
+    FF_105: FD1P3DX
+        port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_7);
+
+    FF_104: FD1P3DX
+        port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_8);
+
+    FF_103: FD1P3DX
+        port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_9);
+
+    FF_102: FD1P3DX
+        port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_0);
+
+    FF_101: FD1P3DX
+        port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_1);
+
+    FF_100: FD1P3DX
+        port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_2);
+
+    FF_99: FD1P3DX
+        port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_3);
+
+    FF_98: FD1P3DX
+        port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_4);
+
+    FF_97: FD1P3DX
+        port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_5);
+
+    FF_96: FD1P3DX
+        port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_6);
+
+    FF_95: FD1P3DX
+        port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_7);
+
+    FF_94: FD1P3DX
+        port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_8);
+
+    FF_93: FD1P3DX
+        port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_9);
+
+    FF_92: FD1P3DX
+        port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_0);
+
+    FF_91: FD1P3DX
+        port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_1);
+
+    FF_90: FD1P3DX
+        port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_2);
+
+    FF_89: FD1P3DX
+        port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_3);
+
+    FF_88: FD1P3DX
+        port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_4);
+
+    FF_87: FD1P3DX
+        port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_5);
+
+    FF_86: FD1P3DX
+        port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_6);
+
+    FF_85: FD1P3DX
+        port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_7);
+
+    FF_84: FD1P3DX
+        port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_8);
+
+    FF_83: FD1P3DX
+        port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_9);
+
+    FF_82: FD1P3BX
+        port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, 
+            Q=>rcount_0);
+
+    FF_81: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_1);
+
+    FF_80: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_2);
+
+    FF_79: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_3);
+
+    FF_78: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_4);
+
+    FF_77: FD1P3DX
+        port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_5);
+
+    FF_76: FD1P3DX
+        port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_6);
+
+    FF_75: FD1P3DX
+        port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_7);
+
+    FF_74: FD1P3DX
+        port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_8);
+
+    FF_73: FD1P3DX
+        port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_9);
+
+    FF_72: FD1P3DX
+        port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_0);
+
+    FF_71: FD1P3DX
+        port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_1);
+
+    FF_70: FD1P3DX
+        port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_2);
+
+    FF_69: FD1P3DX
+        port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_3);
+
+    FF_68: FD1P3DX
+        port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_4);
+
+    FF_67: FD1P3DX
+        port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_5);
+
+    FF_66: FD1P3DX
+        port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_6);
+
+    FF_65: FD1P3DX
+        port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_7);
+
+    FF_64: FD1P3DX
+        port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_8);
+
+    FF_63: FD1P3DX
+        port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_9);
+
+    FF_62: FD1P3DX
+        port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_0);
+
+    FF_61: FD1P3DX
+        port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_1);
+
+    FF_60: FD1P3DX
+        port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_2);
+
+    FF_59: FD1P3DX
+        port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_3);
+
+    FF_58: FD1P3DX
+        port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_4);
+
+    FF_57: FD1P3DX
+        port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_5);
+
+    FF_56: FD1P3DX
+        port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_6);
+
+    FF_55: FD1P3DX
+        port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_7);
+
+    FF_54: FD1P3DX
+        port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_8);
+
+    FF_53: FD1P3DX
+        port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_9);
+
+    FF_52: FD1S3DX
+        port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+    FF_51: FD1S3DX
+        port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+    FF_50: FD1S3DX
+        port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+    FF_49: FD1S3DX
+        port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+    FF_48: FD1S3DX
+        port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+    FF_47: FD1S3DX
+        port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+    FF_46: FD1S3DX
+        port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
+
+    FF_45: FD1S3DX
+        port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
+
+    FF_44: FD1S3DX
+        port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
+
+    FF_43: FD1S3DX
+        port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
+
+    FF_42: FD1S3DX
+        port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+    FF_41: FD1S3DX
+        port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+    FF_40: FD1S3DX
+        port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+    FF_39: FD1S3DX
+        port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+    FF_38: FD1S3DX
+        port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+    FF_37: FD1S3DX
+        port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+    FF_36: FD1S3DX
+        port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+    FF_35: FD1S3DX
+        port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
+
+    FF_34: FD1S3DX
+        port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
+
+    FF_33: FD1S3DX
+        port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
+
+    FF_32: FD1S3DX
+        port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r20);
+
+    FF_31: FD1S3DX
+        port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r21);
+
+    FF_30: FD1S3DX
+        port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r22);
+
+    FF_29: FD1S3DX
+        port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r23);
+
+    FF_28: FD1S3DX
+        port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r24);
+
+    FF_27: FD1S3DX
+        port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r25);
+
+    FF_26: FD1S3DX
+        port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r26);
+
+    FF_25: FD1S3DX
+        port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r27);
+
+    FF_24: FD1S3DX
+        port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r28);
+
+    FF_23: FD1S3DX
+        port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r29);
+
+    FF_22: FD1S3DX
+        port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+    FF_21: FD1S3DX
+        port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+    FF_20: FD1S3DX
+        port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+    FF_19: FD1S3DX
+        port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+    FF_18: FD1S3DX
+        port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+    FF_17: FD1S3DX
+        port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+    FF_16: FD1S3DX
+        port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
+
+    FF_15: FD1S3DX
+        port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
+
+    FF_14: FD1S3DX
+        port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
+
+    FF_13: FD1S3DX
+        port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
+
+    FF_12: FD1S3BX
+        port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+    FF_11: FD1S3DX
+        port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+    FF_10: FD1P3DX
+        port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_0);
+
+    FF_9: FD1P3BX
+        port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>af_setcount_1);
+
+    FF_8: FD1P3DX
+        port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_2);
+
+    FF_7: FD1P3BX
+        port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>af_setcount_3);
+
+    FF_6: FD1P3DX
+        port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_4);
+
+    FF_5: FD1P3DX
+        port map (D=>iaf_setcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_5);
+
+    FF_4: FD1P3DX
+        port map (D=>iaf_setcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_6);
+
+    FF_3: FD1P3DX
+        port map (D=>iaf_setcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_7);
+
+    FF_2: FD1P3DX
+        port map (D=>iaf_setcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_8);
+
+    FF_1: FD1P3DX
+        port map (D=>iaf_setcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_9);
+
+    FF_0: FD1S3DX
+        port map (D=>af_set, CK=>WrClock, CD=>Reset, Q=>AlmostFull);
+
+    w_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, 
+            S1=>open);
+
+    w_gctr_0: CU2
+        port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, 
+            NC0=>iwcount_0, NC1=>iwcount_1);
+
+    w_gctr_1: CU2
+        port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, 
+            NC0=>iwcount_2, NC1=>iwcount_3);
+
+    w_gctr_2: CU2
+        port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, 
+            NC0=>iwcount_4, NC1=>iwcount_5);
+
+    w_gctr_3: CU2
+        port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, 
+            NC0=>iwcount_6, NC1=>iwcount_7);
+
+    w_gctr_4: CU2
+        port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, 
+            NC0=>iwcount_8, NC1=>iwcount_9);
+
+    r_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, 
+            S1=>open);
+
+    r_gctr_0: CU2
+        port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, 
+            NC0=>ircount_0, NC1=>ircount_1);
+
+    r_gctr_1: CU2
+        port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, 
+            NC0=>ircount_2, NC1=>ircount_3);
+
+    r_gctr_2: CU2
+        port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, 
+            NC0=>ircount_4, NC1=>ircount_5);
+
+    r_gctr_3: CU2
+        port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, 
+            NC0=>ircount_6, NC1=>ircount_7);
+
+    r_gctr_4: CU2
+        port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, 
+            NC0=>ircount_8, NC1=>ircount_9);
+
+    empty_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+    empty_cmp_0: AGEB2
+        port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, 
+            B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
+
+    empty_cmp_1: AGEB2
+        port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, 
+            B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
+
+    empty_cmp_2: AGEB2
+        port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, 
+            B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
+
+    empty_cmp_3: AGEB2
+        port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0, 
+            B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
+
+    empty_cmp_4: AGEB2
+        port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8, 
+            B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c);
+
+    a0: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, 
+            S1=>open);
+
+    full_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+    full_cmp_0: AGEB2
+        port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, 
+            B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
+
+    full_cmp_1: AGEB2
+        port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, 
+            B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
+
+    full_cmp_2: AGEB2
+        port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, 
+            B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
+
+    full_cmp_3: AGEB2
+        port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, 
+            B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
+
+    full_cmp_4: AGEB2
+        port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8, 
+            B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c);
+
+    a1: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, 
+            S1=>open);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    af_set_ctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_set_ctr_ci, S0=>open, 
+            S1=>open);
+
+    af_set_ctr_0: CU2
+        port map (CI=>af_set_ctr_ci, PC0=>af_setcount_0, 
+            PC1=>af_setcount_1, CO=>co0_4, NC0=>iaf_setcount_0, 
+            NC1=>iaf_setcount_1);
+
+    af_set_ctr_1: CU2
+        port map (CI=>co0_4, PC0=>af_setcount_2, PC1=>af_setcount_3, 
+            CO=>co1_4, NC0=>iaf_setcount_2, NC1=>iaf_setcount_3);
+
+    af_set_ctr_2: CU2
+        port map (CI=>co1_4, PC0=>af_setcount_4, PC1=>af_setcount_5, 
+            CO=>co2_4, NC0=>iaf_setcount_4, NC1=>iaf_setcount_5);
+
+    af_set_ctr_3: CU2
+        port map (CI=>co2_4, PC0=>af_setcount_6, PC1=>af_setcount_7, 
+            CO=>co3_4, NC0=>iaf_setcount_6, NC1=>iaf_setcount_7);
+
+    af_set_ctr_4: CU2
+        port map (CI=>co3_4, PC0=>af_setcount_8, PC1=>af_setcount_9, 
+            CO=>co4_2, NC0=>iaf_setcount_8, NC1=>iaf_setcount_9);
+
+    af_set_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
+
+    af_set_cmp_0: AGEB2
+        port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0, 
+            B1=>rcount_w1, CI=>cmp_ci_2, GE=>co0_5);
+
+    af_set_cmp_1: AGEB2
+        port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>rcount_w2, 
+            B1=>rcount_w3, CI=>co0_5, GE=>co1_5);
+
+    af_set_cmp_2: AGEB2
+        port map (A0=>af_setcount_4, A1=>af_setcount_5, B0=>rcount_w4, 
+            B1=>rcount_w5, CI=>co1_5, GE=>co2_5);
+
+    af_set_cmp_3: AGEB2
+        port map (A0=>af_setcount_6, A1=>af_setcount_7, 
+            B0=>r_g2b_xor_cluster_0, B1=>rcount_w7, CI=>co2_5, GE=>co3_5);
+
+    af_set_cmp_4: AGEB2
+        port map (A0=>af_setcount_8, A1=>af_set_cmp_set, B0=>rcount_w8, 
+            B1=>af_set_cmp_clr, CI=>co3_5, GE=>af_set_c);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    a2: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set, 
+            S1=>open);
+
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of async_fifo_af_512x36_ecp3 is
+    for Structure
+        for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+        for all:AND2 use entity ecp3.AND2(V); end for;
+        for all:CU2 use entity ecp3.CU2(V); end for;
+        for all:FADD2B use entity ecp3.FADD2B(V); end for;
+        for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
+        for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+        for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+        for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+        for all:INV use entity ecp3.INV(V); end for;
+        for all:OR2 use entity ecp3.OR2(V); end for;
+        for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+        for all:VHI use entity ecp3.VHI(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+        for all:XOR2 use entity ecp3.XOR2(V); end for;
+        for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_af_512x36_ecp3_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/async_fifo_af_512x36_ecp3_tmpl.vhd
new file mode 100644
index 0000000..7af1ab6
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_af_512x36_ecp3_tmpl.vhd
@@ -0,0 +1,19 @@
+-- VHDL module instantiation generated by SCUBA Diamond_2.1_Production (100)
+-- Module  Version: 5.4
+-- Fri Jul 12 14:50:28 2013
+
+-- parameterized module component declaration
+component async_fifo_af_512x36_ecp3
+    port (Data: in  std_logic_vector(35 downto 0); 
+        WrClock: in  std_logic; RdClock: in  std_logic; 
+        WrEn: in  std_logic; RdEn: in  std_logic; Reset: in  std_logic; 
+        RPReset: in  std_logic; Q: out  std_logic_vector(35 downto 0); 
+        Empty: out  std_logic; Full: out  std_logic; 
+        AlmostFull: out  std_logic);
+end component;
+
+-- parameterized module component instance
+__ : async_fifo_af_512x36_ecp3
+    port map (Data(35 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, 
+        RdEn=>__, Reset=>__, RPReset=>__, Q(35 downto 0)=>__, Empty=>__, 
+        Full=>__, AlmostFull=>__);
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_nn_16384x36_ecp3.ipx b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_16384x36_ecp3.ipx
new file mode 100644
index 0000000..290f8d7
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_16384x36_ecp3.ipx
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="async_fifo_nn_16384x36_ecp3" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 07 12 15:53:20.606" version="5.4" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="async_fifo_nn_16384x36_ecp3.lpc" type="lpc" modified="2013 07 12 15:53:18.166"/>
+		<File name="async_fifo_nn_16384x36_ecp3.vhd" type="top_level_vhdl" modified="2013 07 12 15:53:18.264"/>
+		<File name="async_fifo_nn_16384x36_ecp3_tmpl.vhd" type="template_vhdl" modified="2013 07 12 15:53:18.264"/>
+		<File name="tb_async_fifo_nn_16384x36_ecp3_tmpl.vhd" type="testbench_vhdl" modified="2013 07 12 15:53:18.270"/>
+  </Package>
+</DiamondModule>
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_nn_16384x36_ecp3.lpc b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_16384x36_ecp3.lpc
new file mode 100644
index 0000000..48ee80f
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_16384x36_ecp3.lpc
@@ -0,0 +1,47 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.4
+ModuleName=async_fifo_nn_16384x36_ecp3
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=07/12/2013
+Time=15:53:18
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=16384
+Width=36
+RDepth=16384
+RWidth=36
+regout=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=1
+WDataCount=0
+EnECC=0
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_nn_16384x36_ecp3.vhd b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_16384x36_ecp3.vhd
new file mode 100644
index 0000000..fdeda3e
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_16384x36_ecp3.vhd
@@ -0,0 +1,3696 @@
+-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
+-- Module  Version: 5.4
+--C:\lscc\diamond\2.1_x64\ispfpga\bin\nt64\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 16384 -width 36 -depth 16384 -rdata_width 36 -no_enable -pe -1 -pf -1 -rfill -e 
+
+-- Fri Jul 12 15:53:18 2013
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity async_fifo_nn_16384x36_ecp3 is
+    port (
+        Data: in  std_logic_vector(35 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(35 downto 0); 
+        RCNT: out  std_logic_vector(14 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic);
+end async_fifo_nn_16384x36_ecp3;
+
+architecture Structure of async_fifo_nn_16384x36_ecp3 is
+
+    -- internal signal declarations
+    signal invout_1: std_logic;
+    signal invout_0: std_logic;
+    signal w_g2b_xor_cluster_2_1: std_logic;
+    signal w_g2b_xor_cluster_3: std_logic;
+    signal w_g2b_xor_cluster_3_1: std_logic;
+    signal w_g2b_xor_cluster_2: std_logic;
+    signal w_g2b_xor_cluster_1: std_logic;
+    signal r_g2b_xor_cluster_2_1: std_logic;
+    signal r_g2b_xor_cluster_3: std_logic;
+    signal r_g2b_xor_cluster_3_1: std_logic;
+    signal r_g2b_xor_cluster_2: std_logic;
+    signal r_g2b_xor_cluster_1: std_logic;
+    signal w_gdata_0: std_logic;
+    signal w_gdata_1: std_logic;
+    signal w_gdata_2: std_logic;
+    signal w_gdata_3: std_logic;
+    signal w_gdata_4: std_logic;
+    signal w_gdata_5: std_logic;
+    signal w_gdata_6: std_logic;
+    signal w_gdata_7: std_logic;
+    signal w_gdata_8: std_logic;
+    signal w_gdata_9: std_logic;
+    signal w_gdata_10: std_logic;
+    signal w_gdata_11: std_logic;
+    signal w_gdata_12: std_logic;
+    signal w_gdata_13: std_logic;
+    signal wptr_0: std_logic;
+    signal wptr_1: std_logic;
+    signal wptr_2: std_logic;
+    signal wptr_3: std_logic;
+    signal wptr_4: std_logic;
+    signal wptr_5: std_logic;
+    signal wptr_6: std_logic;
+    signal wptr_7: std_logic;
+    signal wptr_8: std_logic;
+    signal wptr_9: std_logic;
+    signal wptr_10: std_logic;
+    signal wptr_11: std_logic;
+    signal wptr_12: std_logic;
+    signal wptr_13: std_logic;
+    signal wptr_14: std_logic;
+    signal r_gdata_0: std_logic;
+    signal r_gdata_1: std_logic;
+    signal r_gdata_2: std_logic;
+    signal r_gdata_3: std_logic;
+    signal r_gdata_4: std_logic;
+    signal r_gdata_5: std_logic;
+    signal r_gdata_6: std_logic;
+    signal r_gdata_7: std_logic;
+    signal r_gdata_8: std_logic;
+    signal r_gdata_9: std_logic;
+    signal r_gdata_10: std_logic;
+    signal r_gdata_11: std_logic;
+    signal r_gdata_12: std_logic;
+    signal r_gdata_13: std_logic;
+    signal rptr_14: std_logic;
+    signal w_gcount_0: std_logic;
+    signal w_gcount_1: std_logic;
+    signal w_gcount_2: std_logic;
+    signal w_gcount_3: std_logic;
+    signal w_gcount_4: std_logic;
+    signal w_gcount_5: std_logic;
+    signal w_gcount_6: std_logic;
+    signal w_gcount_7: std_logic;
+    signal w_gcount_8: std_logic;
+    signal w_gcount_9: std_logic;
+    signal w_gcount_10: std_logic;
+    signal w_gcount_11: std_logic;
+    signal w_gcount_12: std_logic;
+    signal w_gcount_13: std_logic;
+    signal w_gcount_14: std_logic;
+    signal r_gcount_0: std_logic;
+    signal r_gcount_1: std_logic;
+    signal r_gcount_2: std_logic;
+    signal r_gcount_3: std_logic;
+    signal r_gcount_4: std_logic;
+    signal r_gcount_5: std_logic;
+    signal r_gcount_6: std_logic;
+    signal r_gcount_7: std_logic;
+    signal r_gcount_8: std_logic;
+    signal r_gcount_9: std_logic;
+    signal r_gcount_10: std_logic;
+    signal r_gcount_11: std_logic;
+    signal r_gcount_12: std_logic;
+    signal r_gcount_13: std_logic;
+    signal r_gcount_14: std_logic;
+    signal w_gcount_r20: std_logic;
+    signal w_gcount_r0: std_logic;
+    signal w_gcount_r21: std_logic;
+    signal w_gcount_r1: std_logic;
+    signal w_gcount_r22: std_logic;
+    signal w_gcount_r2: std_logic;
+    signal w_gcount_r23: std_logic;
+    signal w_gcount_r3: std_logic;
+    signal w_gcount_r24: std_logic;
+    signal w_gcount_r4: std_logic;
+    signal w_gcount_r25: std_logic;
+    signal w_gcount_r5: std_logic;
+    signal w_gcount_r26: std_logic;
+    signal w_gcount_r6: std_logic;
+    signal w_gcount_r27: std_logic;
+    signal w_gcount_r7: std_logic;
+    signal w_gcount_r28: std_logic;
+    signal w_gcount_r8: std_logic;
+    signal w_gcount_r29: std_logic;
+    signal w_gcount_r9: std_logic;
+    signal w_gcount_r210: std_logic;
+    signal w_gcount_r10: std_logic;
+    signal w_gcount_r211: std_logic;
+    signal w_gcount_r11: std_logic;
+    signal w_gcount_r212: std_logic;
+    signal w_gcount_r12: std_logic;
+    signal w_gcount_r213: std_logic;
+    signal w_gcount_r13: std_logic;
+    signal w_gcount_r214: std_logic;
+    signal w_gcount_r14: std_logic;
+    signal r_gcount_w20: std_logic;
+    signal r_gcount_w0: std_logic;
+    signal r_gcount_w21: std_logic;
+    signal r_gcount_w1: std_logic;
+    signal r_gcount_w22: std_logic;
+    signal r_gcount_w2: std_logic;
+    signal r_gcount_w23: std_logic;
+    signal r_gcount_w3: std_logic;
+    signal r_gcount_w24: std_logic;
+    signal r_gcount_w4: std_logic;
+    signal r_gcount_w25: std_logic;
+    signal r_gcount_w5: std_logic;
+    signal r_gcount_w26: std_logic;
+    signal r_gcount_w6: std_logic;
+    signal r_gcount_w27: std_logic;
+    signal r_gcount_w7: std_logic;
+    signal r_gcount_w28: std_logic;
+    signal r_gcount_w8: std_logic;
+    signal r_gcount_w29: std_logic;
+    signal r_gcount_w9: std_logic;
+    signal r_gcount_w210: std_logic;
+    signal r_gcount_w10: std_logic;
+    signal r_gcount_w211: std_logic;
+    signal r_gcount_w11: std_logic;
+    signal r_gcount_w212: std_logic;
+    signal r_gcount_w12: std_logic;
+    signal r_gcount_w213: std_logic;
+    signal r_gcount_w13: std_logic;
+    signal r_gcount_w214: std_logic;
+    signal r_gcount_w14: std_logic;
+    signal empty_i: std_logic;
+    signal rRst: std_logic;
+    signal full_i: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_gctr_ci: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co0: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal co1: std_logic;
+    signal iwcount_6: std_logic;
+    signal iwcount_7: std_logic;
+    signal co2: std_logic;
+    signal iwcount_8: std_logic;
+    signal iwcount_9: std_logic;
+    signal co3: std_logic;
+    signal iwcount_10: std_logic;
+    signal iwcount_11: std_logic;
+    signal co4: std_logic;
+    signal iwcount_12: std_logic;
+    signal iwcount_13: std_logic;
+    signal co5: std_logic;
+    signal iwcount_14: std_logic;
+    signal co7: std_logic;
+    signal wcount_14: std_logic;
+    signal co6: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_gctr_ci: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co0_1: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal co1_1: std_logic;
+    signal ircount_6: std_logic;
+    signal ircount_7: std_logic;
+    signal co2_1: std_logic;
+    signal ircount_8: std_logic;
+    signal ircount_9: std_logic;
+    signal co3_1: std_logic;
+    signal ircount_10: std_logic;
+    signal ircount_11: std_logic;
+    signal co4_1: std_logic;
+    signal ircount_12: std_logic;
+    signal ircount_13: std_logic;
+    signal co5_1: std_logic;
+    signal ircount_14: std_logic;
+    signal co7_1: std_logic;
+    signal rcount_14: std_logic;
+    signal co6_1: std_logic;
+    signal mdout1_7_0: std_logic;
+    signal mdout1_6_0: std_logic;
+    signal mdout1_5_0: std_logic;
+    signal mdout1_4_0: std_logic;
+    signal mdout1_3_0: std_logic;
+    signal mdout1_2_0: std_logic;
+    signal mdout1_1_0: std_logic;
+    signal mdout1_0_0: std_logic;
+    signal mdout1_7_1: std_logic;
+    signal mdout1_6_1: std_logic;
+    signal mdout1_5_1: std_logic;
+    signal mdout1_4_1: std_logic;
+    signal mdout1_3_1: std_logic;
+    signal mdout1_2_1: std_logic;
+    signal mdout1_1_1: std_logic;
+    signal mdout1_0_1: std_logic;
+    signal mdout1_7_2: std_logic;
+    signal mdout1_6_2: std_logic;
+    signal mdout1_5_2: std_logic;
+    signal mdout1_4_2: std_logic;
+    signal mdout1_3_2: std_logic;
+    signal mdout1_2_2: std_logic;
+    signal mdout1_1_2: std_logic;
+    signal mdout1_0_2: std_logic;
+    signal mdout1_7_3: std_logic;
+    signal mdout1_6_3: std_logic;
+    signal mdout1_5_3: std_logic;
+    signal mdout1_4_3: std_logic;
+    signal mdout1_3_3: std_logic;
+    signal mdout1_2_3: std_logic;
+    signal mdout1_1_3: std_logic;
+    signal mdout1_0_3: std_logic;
+    signal mdout1_7_4: std_logic;
+    signal mdout1_6_4: std_logic;
+    signal mdout1_5_4: std_logic;
+    signal mdout1_4_4: std_logic;
+    signal mdout1_3_4: std_logic;
+    signal mdout1_2_4: std_logic;
+    signal mdout1_1_4: std_logic;
+    signal mdout1_0_4: std_logic;
+    signal mdout1_7_5: std_logic;
+    signal mdout1_6_5: std_logic;
+    signal mdout1_5_5: std_logic;
+    signal mdout1_4_5: std_logic;
+    signal mdout1_3_5: std_logic;
+    signal mdout1_2_5: std_logic;
+    signal mdout1_1_5: std_logic;
+    signal mdout1_0_5: std_logic;
+    signal mdout1_7_6: std_logic;
+    signal mdout1_6_6: std_logic;
+    signal mdout1_5_6: std_logic;
+    signal mdout1_4_6: std_logic;
+    signal mdout1_3_6: std_logic;
+    signal mdout1_2_6: std_logic;
+    signal mdout1_1_6: std_logic;
+    signal mdout1_0_6: std_logic;
+    signal mdout1_7_7: std_logic;
+    signal mdout1_6_7: std_logic;
+    signal mdout1_5_7: std_logic;
+    signal mdout1_4_7: std_logic;
+    signal mdout1_3_7: std_logic;
+    signal mdout1_2_7: std_logic;
+    signal mdout1_1_7: std_logic;
+    signal mdout1_0_7: std_logic;
+    signal mdout1_7_8: std_logic;
+    signal mdout1_6_8: std_logic;
+    signal mdout1_5_8: std_logic;
+    signal mdout1_4_8: std_logic;
+    signal mdout1_3_8: std_logic;
+    signal mdout1_2_8: std_logic;
+    signal mdout1_1_8: std_logic;
+    signal mdout1_0_8: std_logic;
+    signal mdout1_7_9: std_logic;
+    signal mdout1_6_9: std_logic;
+    signal mdout1_5_9: std_logic;
+    signal mdout1_4_9: std_logic;
+    signal mdout1_3_9: std_logic;
+    signal mdout1_2_9: std_logic;
+    signal mdout1_1_9: std_logic;
+    signal mdout1_0_9: std_logic;
+    signal mdout1_7_10: std_logic;
+    signal mdout1_6_10: std_logic;
+    signal mdout1_5_10: std_logic;
+    signal mdout1_4_10: std_logic;
+    signal mdout1_3_10: std_logic;
+    signal mdout1_2_10: std_logic;
+    signal mdout1_1_10: std_logic;
+    signal mdout1_0_10: std_logic;
+    signal mdout1_7_11: std_logic;
+    signal mdout1_6_11: std_logic;
+    signal mdout1_5_11: std_logic;
+    signal mdout1_4_11: std_logic;
+    signal mdout1_3_11: std_logic;
+    signal mdout1_2_11: std_logic;
+    signal mdout1_1_11: std_logic;
+    signal mdout1_0_11: std_logic;
+    signal mdout1_7_12: std_logic;
+    signal mdout1_6_12: std_logic;
+    signal mdout1_5_12: std_logic;
+    signal mdout1_4_12: std_logic;
+    signal mdout1_3_12: std_logic;
+    signal mdout1_2_12: std_logic;
+    signal mdout1_1_12: std_logic;
+    signal mdout1_0_12: std_logic;
+    signal mdout1_7_13: std_logic;
+    signal mdout1_6_13: std_logic;
+    signal mdout1_5_13: std_logic;
+    signal mdout1_4_13: std_logic;
+    signal mdout1_3_13: std_logic;
+    signal mdout1_2_13: std_logic;
+    signal mdout1_1_13: std_logic;
+    signal mdout1_0_13: std_logic;
+    signal mdout1_7_14: std_logic;
+    signal mdout1_6_14: std_logic;
+    signal mdout1_5_14: std_logic;
+    signal mdout1_4_14: std_logic;
+    signal mdout1_3_14: std_logic;
+    signal mdout1_2_14: std_logic;
+    signal mdout1_1_14: std_logic;
+    signal mdout1_0_14: std_logic;
+    signal mdout1_7_15: std_logic;
+    signal mdout1_6_15: std_logic;
+    signal mdout1_5_15: std_logic;
+    signal mdout1_4_15: std_logic;
+    signal mdout1_3_15: std_logic;
+    signal mdout1_2_15: std_logic;
+    signal mdout1_1_15: std_logic;
+    signal mdout1_0_15: std_logic;
+    signal mdout1_7_16: std_logic;
+    signal mdout1_6_16: std_logic;
+    signal mdout1_5_16: std_logic;
+    signal mdout1_4_16: std_logic;
+    signal mdout1_3_16: std_logic;
+    signal mdout1_2_16: std_logic;
+    signal mdout1_1_16: std_logic;
+    signal mdout1_0_16: std_logic;
+    signal mdout1_7_17: std_logic;
+    signal mdout1_6_17: std_logic;
+    signal mdout1_5_17: std_logic;
+    signal mdout1_4_17: std_logic;
+    signal mdout1_3_17: std_logic;
+    signal mdout1_2_17: std_logic;
+    signal mdout1_1_17: std_logic;
+    signal mdout1_0_17: std_logic;
+    signal mdout1_7_18: std_logic;
+    signal mdout1_6_18: std_logic;
+    signal mdout1_5_18: std_logic;
+    signal mdout1_4_18: std_logic;
+    signal mdout1_3_18: std_logic;
+    signal mdout1_2_18: std_logic;
+    signal mdout1_1_18: std_logic;
+    signal mdout1_0_18: std_logic;
+    signal mdout1_7_19: std_logic;
+    signal mdout1_6_19: std_logic;
+    signal mdout1_5_19: std_logic;
+    signal mdout1_4_19: std_logic;
+    signal mdout1_3_19: std_logic;
+    signal mdout1_2_19: std_logic;
+    signal mdout1_1_19: std_logic;
+    signal mdout1_0_19: std_logic;
+    signal mdout1_7_20: std_logic;
+    signal mdout1_6_20: std_logic;
+    signal mdout1_5_20: std_logic;
+    signal mdout1_4_20: std_logic;
+    signal mdout1_3_20: std_logic;
+    signal mdout1_2_20: std_logic;
+    signal mdout1_1_20: std_logic;
+    signal mdout1_0_20: std_logic;
+    signal mdout1_7_21: std_logic;
+    signal mdout1_6_21: std_logic;
+    signal mdout1_5_21: std_logic;
+    signal mdout1_4_21: std_logic;
+    signal mdout1_3_21: std_logic;
+    signal mdout1_2_21: std_logic;
+    signal mdout1_1_21: std_logic;
+    signal mdout1_0_21: std_logic;
+    signal mdout1_7_22: std_logic;
+    signal mdout1_6_22: std_logic;
+    signal mdout1_5_22: std_logic;
+    signal mdout1_4_22: std_logic;
+    signal mdout1_3_22: std_logic;
+    signal mdout1_2_22: std_logic;
+    signal mdout1_1_22: std_logic;
+    signal mdout1_0_22: std_logic;
+    signal mdout1_7_23: std_logic;
+    signal mdout1_6_23: std_logic;
+    signal mdout1_5_23: std_logic;
+    signal mdout1_4_23: std_logic;
+    signal mdout1_3_23: std_logic;
+    signal mdout1_2_23: std_logic;
+    signal mdout1_1_23: std_logic;
+    signal mdout1_0_23: std_logic;
+    signal mdout1_7_24: std_logic;
+    signal mdout1_6_24: std_logic;
+    signal mdout1_5_24: std_logic;
+    signal mdout1_4_24: std_logic;
+    signal mdout1_3_24: std_logic;
+    signal mdout1_2_24: std_logic;
+    signal mdout1_1_24: std_logic;
+    signal mdout1_0_24: std_logic;
+    signal mdout1_7_25: std_logic;
+    signal mdout1_6_25: std_logic;
+    signal mdout1_5_25: std_logic;
+    signal mdout1_4_25: std_logic;
+    signal mdout1_3_25: std_logic;
+    signal mdout1_2_25: std_logic;
+    signal mdout1_1_25: std_logic;
+    signal mdout1_0_25: std_logic;
+    signal mdout1_7_26: std_logic;
+    signal mdout1_6_26: std_logic;
+    signal mdout1_5_26: std_logic;
+    signal mdout1_4_26: std_logic;
+    signal mdout1_3_26: std_logic;
+    signal mdout1_2_26: std_logic;
+    signal mdout1_1_26: std_logic;
+    signal mdout1_0_26: std_logic;
+    signal mdout1_7_27: std_logic;
+    signal mdout1_6_27: std_logic;
+    signal mdout1_5_27: std_logic;
+    signal mdout1_4_27: std_logic;
+    signal mdout1_3_27: std_logic;
+    signal mdout1_2_27: std_logic;
+    signal mdout1_1_27: std_logic;
+    signal mdout1_0_27: std_logic;
+    signal mdout1_7_28: std_logic;
+    signal mdout1_6_28: std_logic;
+    signal mdout1_5_28: std_logic;
+    signal mdout1_4_28: std_logic;
+    signal mdout1_3_28: std_logic;
+    signal mdout1_2_28: std_logic;
+    signal mdout1_1_28: std_logic;
+    signal mdout1_0_28: std_logic;
+    signal mdout1_7_29: std_logic;
+    signal mdout1_6_29: std_logic;
+    signal mdout1_5_29: std_logic;
+    signal mdout1_4_29: std_logic;
+    signal mdout1_3_29: std_logic;
+    signal mdout1_2_29: std_logic;
+    signal mdout1_1_29: std_logic;
+    signal mdout1_0_29: std_logic;
+    signal mdout1_7_30: std_logic;
+    signal mdout1_6_30: std_logic;
+    signal mdout1_5_30: std_logic;
+    signal mdout1_4_30: std_logic;
+    signal mdout1_3_30: std_logic;
+    signal mdout1_2_30: std_logic;
+    signal mdout1_1_30: std_logic;
+    signal mdout1_0_30: std_logic;
+    signal mdout1_7_31: std_logic;
+    signal mdout1_6_31: std_logic;
+    signal mdout1_5_31: std_logic;
+    signal mdout1_4_31: std_logic;
+    signal mdout1_3_31: std_logic;
+    signal mdout1_2_31: std_logic;
+    signal mdout1_1_31: std_logic;
+    signal mdout1_0_31: std_logic;
+    signal mdout1_7_32: std_logic;
+    signal mdout1_6_32: std_logic;
+    signal mdout1_5_32: std_logic;
+    signal mdout1_4_32: std_logic;
+    signal mdout1_3_32: std_logic;
+    signal mdout1_2_32: std_logic;
+    signal mdout1_1_32: std_logic;
+    signal mdout1_0_32: std_logic;
+    signal mdout1_7_33: std_logic;
+    signal mdout1_6_33: std_logic;
+    signal mdout1_5_33: std_logic;
+    signal mdout1_4_33: std_logic;
+    signal mdout1_3_33: std_logic;
+    signal mdout1_2_33: std_logic;
+    signal mdout1_1_33: std_logic;
+    signal mdout1_0_33: std_logic;
+    signal mdout1_7_34: std_logic;
+    signal mdout1_6_34: std_logic;
+    signal mdout1_5_34: std_logic;
+    signal mdout1_4_34: std_logic;
+    signal mdout1_3_34: std_logic;
+    signal mdout1_2_34: std_logic;
+    signal mdout1_1_34: std_logic;
+    signal mdout1_0_34: std_logic;
+    signal rptr_13_ff: std_logic;
+    signal rptr_12_ff: std_logic;
+    signal rptr_11_ff: std_logic;
+    signal mdout1_7_35: std_logic;
+    signal mdout1_6_35: std_logic;
+    signal mdout1_5_35: std_logic;
+    signal mdout1_4_35: std_logic;
+    signal mdout1_3_35: std_logic;
+    signal mdout1_2_35: std_logic;
+    signal mdout1_1_35: std_logic;
+    signal mdout1_0_35: std_logic;
+    signal rfill_sub_0: std_logic;
+    signal rptr_0: std_logic;
+    signal scuba_vhi: std_logic;
+    signal rfill_sub_1: std_logic;
+    signal rfill_sub_2: std_logic;
+    signal co0_2: std_logic;
+    signal rptr_1: std_logic;
+    signal rptr_2: std_logic;
+    signal rfill_sub_3: std_logic;
+    signal rfill_sub_4: std_logic;
+    signal co1_2: std_logic;
+    signal rptr_3: std_logic;
+    signal rptr_4: std_logic;
+    signal rfill_sub_5: std_logic;
+    signal rfill_sub_6: std_logic;
+    signal co2_2: std_logic;
+    signal rptr_5: std_logic;
+    signal rptr_6: std_logic;
+    signal rfill_sub_7: std_logic;
+    signal rfill_sub_8: std_logic;
+    signal co3_2: std_logic;
+    signal rptr_7: std_logic;
+    signal rptr_8: std_logic;
+    signal rfill_sub_9: std_logic;
+    signal rfill_sub_10: std_logic;
+    signal co4_2: std_logic;
+    signal rptr_9: std_logic;
+    signal rptr_10: std_logic;
+    signal rfill_sub_11: std_logic;
+    signal rfill_sub_12: std_logic;
+    signal co5_2: std_logic;
+    signal rptr_11: std_logic;
+    signal rptr_12: std_logic;
+    signal rfill_sub_13: std_logic;
+    signal rfill_sub_14: std_logic;
+    signal co6_2: std_logic;
+    signal rptr_13: std_logic;
+    signal rfill_sub_msb: std_logic;
+    signal co7_2d: std_logic;
+    signal co7_2: std_logic;
+    signal rden_i: std_logic;
+    signal cmp_ci: std_logic;
+    signal wcount_r0: std_logic;
+    signal wcount_r1: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal co0_3: std_logic;
+    signal wcount_r2: std_logic;
+    signal wcount_r3: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal co1_3: std_logic;
+    signal wcount_r4: std_logic;
+    signal wcount_r5: std_logic;
+    signal rcount_4: std_logic;
+    signal rcount_5: std_logic;
+    signal co2_3: std_logic;
+    signal wcount_r6: std_logic;
+    signal wcount_r7: std_logic;
+    signal rcount_6: std_logic;
+    signal rcount_7: std_logic;
+    signal co3_3: std_logic;
+    signal wcount_r8: std_logic;
+    signal wcount_r9: std_logic;
+    signal rcount_8: std_logic;
+    signal rcount_9: std_logic;
+    signal co4_3: std_logic;
+    signal wcount_r10: std_logic;
+    signal w_g2b_xor_cluster_0: std_logic;
+    signal rcount_10: std_logic;
+    signal rcount_11: std_logic;
+    signal co5_3: std_logic;
+    signal wcount_r12: std_logic;
+    signal wcount_r13: std_logic;
+    signal rcount_12: std_logic;
+    signal rcount_13: std_logic;
+    signal co6_3: std_logic;
+    signal empty_cmp_clr: std_logic;
+    signal empty_cmp_set: std_logic;
+    signal empty_d: std_logic;
+    signal empty_d_c: std_logic;
+    signal wren_i: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal rcount_w0: std_logic;
+    signal rcount_w1: std_logic;
+    signal wcount_0: std_logic;
+    signal wcount_1: std_logic;
+    signal co0_4: std_logic;
+    signal rcount_w2: std_logic;
+    signal rcount_w3: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_3: std_logic;
+    signal co1_4: std_logic;
+    signal rcount_w4: std_logic;
+    signal rcount_w5: std_logic;
+    signal wcount_4: std_logic;
+    signal wcount_5: std_logic;
+    signal co2_4: std_logic;
+    signal rcount_w6: std_logic;
+    signal rcount_w7: std_logic;
+    signal wcount_6: std_logic;
+    signal wcount_7: std_logic;
+    signal co3_4: std_logic;
+    signal rcount_w8: std_logic;
+    signal rcount_w9: std_logic;
+    signal wcount_8: std_logic;
+    signal wcount_9: std_logic;
+    signal co4_4: std_logic;
+    signal rcount_w10: std_logic;
+    signal r_g2b_xor_cluster_0: std_logic;
+    signal wcount_10: std_logic;
+    signal wcount_11: std_logic;
+    signal co5_4: std_logic;
+    signal rcount_w12: std_logic;
+    signal rcount_w13: std_logic;
+    signal wcount_12: std_logic;
+    signal wcount_13: std_logic;
+    signal co6_4: std_logic;
+    signal full_cmp_clr: std_logic;
+    signal full_cmp_set: std_logic;
+    signal full_d: std_logic;
+    signal full_d_c: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component AGEB2
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; GE: out  std_logic);
+    end component;
+    component AND2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component CU2
+        port (CI: in  std_logic; PC0: in  std_logic; PC1: in  std_logic; 
+            CO: out  std_logic; NC0: out  std_logic; NC1: out  std_logic);
+    end component;
+    component FADD2B
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; COUT: out  std_logic; 
+            S0: out  std_logic; S1: out  std_logic);
+    end component;
+    component FSUB2B
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; BI: in  std_logic; BOUT: out  std_logic; 
+            S0: out  std_logic; S1: out  std_logic);
+    end component;
+    component FD1P3BX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            PD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1P3DX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            CD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1S3BX
+        port (D: in  std_logic; CK: in  std_logic; PD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component FD1S3DX
+        port (D: in  std_logic; CK: in  std_logic; CD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component INV
+        port (A: in  std_logic; Z: out  std_logic);
+    end component;
+    component MUX81
+        port (D0: in  std_logic; D1: in  std_logic; D2: in  std_logic; 
+            D3: in  std_logic; D4: in  std_logic; D5: in  std_logic; 
+            D6: in  std_logic; D7: in  std_logic; SD1: in  std_logic; 
+            SD2: in  std_logic; SD3: in  std_logic; Z: out  std_logic);
+    end component;
+    component OR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component ROM16X1A
+        generic (INITVAL : in std_logic_vector(15 downto 0));
+        port (AD3: in  std_logic; AD2: in  std_logic; AD1: in  std_logic; 
+            AD0: in  std_logic; DO0: out  std_logic);
+    end component;
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component XOR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component DP16KC
+        generic (GSR : in String; WRITEMODE_B : in String; 
+                WRITEMODE_A : in String; CSDECODE_B : in String; 
+                CSDECODE_A : in String; REGMODE_B : in String; 
+                REGMODE_A : in String; DATA_WIDTH_B : in Integer; 
+                DATA_WIDTH_A : in Integer);
+        port (DIA0: in  std_logic; DIA1: in  std_logic; 
+            DIA2: in  std_logic; DIA3: in  std_logic; 
+            DIA4: in  std_logic; DIA5: in  std_logic; 
+            DIA6: in  std_logic; DIA7: in  std_logic; 
+            DIA8: in  std_logic; DIA9: in  std_logic; 
+            DIA10: in  std_logic; DIA11: in  std_logic; 
+            DIA12: in  std_logic; DIA13: in  std_logic; 
+            DIA14: in  std_logic; DIA15: in  std_logic; 
+            DIA16: in  std_logic; DIA17: in  std_logic; 
+            ADA0: in  std_logic; ADA1: in  std_logic; 
+            ADA2: in  std_logic; ADA3: in  std_logic; 
+            ADA4: in  std_logic; ADA5: in  std_logic; 
+            ADA6: in  std_logic; ADA7: in  std_logic; 
+            ADA8: in  std_logic; ADA9: in  std_logic; 
+            ADA10: in  std_logic; ADA11: in  std_logic; 
+            ADA12: in  std_logic; ADA13: in  std_logic; 
+            CEA: in  std_logic; CLKA: in  std_logic; OCEA: in  std_logic; 
+            WEA: in  std_logic; CSA0: in  std_logic; CSA1: in  std_logic; 
+            CSA2: in  std_logic; RSTA: in  std_logic; 
+            DIB0: in  std_logic; DIB1: in  std_logic; 
+            DIB2: in  std_logic; DIB3: in  std_logic; 
+            DIB4: in  std_logic; DIB5: in  std_logic; 
+            DIB6: in  std_logic; DIB7: in  std_logic; 
+            DIB8: in  std_logic; DIB9: in  std_logic; 
+            DIB10: in  std_logic; DIB11: in  std_logic; 
+            DIB12: in  std_logic; DIB13: in  std_logic; 
+            DIB14: in  std_logic; DIB15: in  std_logic; 
+            DIB16: in  std_logic; DIB17: in  std_logic; 
+            ADB0: in  std_logic; ADB1: in  std_logic; 
+            ADB2: in  std_logic; ADB3: in  std_logic; 
+            ADB4: in  std_logic; ADB5: in  std_logic; 
+            ADB6: in  std_logic; ADB7: in  std_logic; 
+            ADB8: in  std_logic; ADB9: in  std_logic; 
+            ADB10: in  std_logic; ADB11: in  std_logic; 
+            ADB12: in  std_logic; ADB13: in  std_logic; 
+            CEB: in  std_logic; CLKB: in  std_logic; OCEB: in  std_logic; 
+            WEB: in  std_logic; CSB0: in  std_logic; CSB1: in  std_logic; 
+            CSB2: in  std_logic; RSTB: in  std_logic; 
+            DOA0: out  std_logic; DOA1: out  std_logic; 
+            DOA2: out  std_logic; DOA3: out  std_logic; 
+            DOA4: out  std_logic; DOA5: out  std_logic; 
+            DOA6: out  std_logic; DOA7: out  std_logic; 
+            DOA8: out  std_logic; DOA9: out  std_logic; 
+            DOA10: out  std_logic; DOA11: out  std_logic; 
+            DOA12: out  std_logic; DOA13: out  std_logic; 
+            DOA14: out  std_logic; DOA15: out  std_logic; 
+            DOA16: out  std_logic; DOA17: out  std_logic; 
+            DOB0: out  std_logic; DOB1: out  std_logic; 
+            DOB2: out  std_logic; DOB3: out  std_logic; 
+            DOB4: out  std_logic; DOB5: out  std_logic; 
+            DOB6: out  std_logic; DOB7: out  std_logic; 
+            DOB8: out  std_logic; DOB9: out  std_logic; 
+            DOB10: out  std_logic; DOB11: out  std_logic; 
+            DOB12: out  std_logic; DOB13: out  std_logic; 
+            DOB14: out  std_logic; DOB15: out  std_logic; 
+            DOB16: out  std_logic; DOB17: out  std_logic);
+    end component;
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute RESETMODE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is "";
+    attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_0_1_30 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_1_30 : label is "";
+    attribute RESETMODE of pdp_ram_0_1_30 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_0_2_29 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_2_29 : label is "";
+    attribute RESETMODE of pdp_ram_0_2_29 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_0_3_28 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_3_28 : label is "";
+    attribute RESETMODE of pdp_ram_0_3_28 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_1_0_27 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_0_27 : label is "";
+    attribute RESETMODE of pdp_ram_1_0_27 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_1_1_26 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_1_26 : label is "";
+    attribute RESETMODE of pdp_ram_1_1_26 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_1_2_25 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_2_25 : label is "";
+    attribute RESETMODE of pdp_ram_1_2_25 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_1_3_24 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_3_24 : label is "";
+    attribute RESETMODE of pdp_ram_1_3_24 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_2_0_23 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_2_0_23 : label is "";
+    attribute RESETMODE of pdp_ram_2_0_23 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_2_1_22 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_2_1_22 : label is "";
+    attribute RESETMODE of pdp_ram_2_1_22 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_2_2_21 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_2_2_21 : label is "";
+    attribute RESETMODE of pdp_ram_2_2_21 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_2_3_20 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_2_3_20 : label is "";
+    attribute RESETMODE of pdp_ram_2_3_20 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_3_0_19 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_3_0_19 : label is "";
+    attribute RESETMODE of pdp_ram_3_0_19 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_3_1_18 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_3_1_18 : label is "";
+    attribute RESETMODE of pdp_ram_3_1_18 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_3_2_17 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_3_2_17 : label is "";
+    attribute RESETMODE of pdp_ram_3_2_17 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_3_3_16 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_3_3_16 : label is "";
+    attribute RESETMODE of pdp_ram_3_3_16 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_4_0_15 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_4_0_15 : label is "";
+    attribute RESETMODE of pdp_ram_4_0_15 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_4_1_14 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_4_1_14 : label is "";
+    attribute RESETMODE of pdp_ram_4_1_14 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_4_2_13 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_4_2_13 : label is "";
+    attribute RESETMODE of pdp_ram_4_2_13 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_4_3_12 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_4_3_12 : label is "";
+    attribute RESETMODE of pdp_ram_4_3_12 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_5_0_11 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_5_0_11 : label is "";
+    attribute RESETMODE of pdp_ram_5_0_11 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_5_1_10 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_5_1_10 : label is "";
+    attribute RESETMODE of pdp_ram_5_1_10 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_5_2_9 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_5_2_9 : label is "";
+    attribute RESETMODE of pdp_ram_5_2_9 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_5_3_8 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_5_3_8 : label is "";
+    attribute RESETMODE of pdp_ram_5_3_8 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_6_0_7 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_6_0_7 : label is "";
+    attribute RESETMODE of pdp_ram_6_0_7 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_6_1_6 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_6_1_6 : label is "";
+    attribute RESETMODE of pdp_ram_6_1_6 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_6_2_5 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_6_2_5 : label is "";
+    attribute RESETMODE of pdp_ram_6_2_5 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_6_3_4 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_6_3_4 : label is "";
+    attribute RESETMODE of pdp_ram_6_3_4 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_7_0_3 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_7_0_3 : label is "";
+    attribute RESETMODE of pdp_ram_7_0_3 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_7_1_2 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_7_1_2 : label is "";
+    attribute RESETMODE of pdp_ram_7_1_2 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_7_2_1 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_7_2_1 : label is "";
+    attribute RESETMODE of pdp_ram_7_2_1 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_7_3_0 : label is "async_fifo_nn_16384x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_7_3_0 : label is "";
+    attribute RESETMODE of pdp_ram_7_3_0 : label is "SYNC";
+    attribute GSR of FF_169 : label is "ENABLED";
+    attribute GSR of FF_168 : label is "ENABLED";
+    attribute GSR of FF_167 : label is "ENABLED";
+    attribute GSR of FF_166 : label is "ENABLED";
+    attribute GSR of FF_165 : label is "ENABLED";
+    attribute GSR of FF_164 : label is "ENABLED";
+    attribute GSR of FF_163 : label is "ENABLED";
+    attribute GSR of FF_162 : label is "ENABLED";
+    attribute GSR of FF_161 : label is "ENABLED";
+    attribute GSR of FF_160 : label is "ENABLED";
+    attribute GSR of FF_159 : label is "ENABLED";
+    attribute GSR of FF_158 : label is "ENABLED";
+    attribute GSR of FF_157 : label is "ENABLED";
+    attribute GSR of FF_156 : label is "ENABLED";
+    attribute GSR of FF_155 : label is "ENABLED";
+    attribute GSR of FF_154 : label is "ENABLED";
+    attribute GSR of FF_153 : label is "ENABLED";
+    attribute GSR of FF_152 : label is "ENABLED";
+    attribute GSR of FF_151 : label is "ENABLED";
+    attribute GSR of FF_150 : label is "ENABLED";
+    attribute GSR of FF_149 : label is "ENABLED";
+    attribute GSR of FF_148 : label is "ENABLED";
+    attribute GSR of FF_147 : label is "ENABLED";
+    attribute GSR of FF_146 : label is "ENABLED";
+    attribute GSR of FF_145 : label is "ENABLED";
+    attribute GSR of FF_144 : label is "ENABLED";
+    attribute GSR of FF_143 : label is "ENABLED";
+    attribute GSR of FF_142 : label is "ENABLED";
+    attribute GSR of FF_141 : label is "ENABLED";
+    attribute GSR of FF_140 : label is "ENABLED";
+    attribute GSR of FF_139 : label is "ENABLED";
+    attribute GSR of FF_138 : label is "ENABLED";
+    attribute GSR of FF_137 : label is "ENABLED";
+    attribute GSR of FF_136 : label is "ENABLED";
+    attribute GSR of FF_135 : label is "ENABLED";
+    attribute GSR of FF_134 : label is "ENABLED";
+    attribute GSR of FF_133 : label is "ENABLED";
+    attribute GSR of FF_132 : label is "ENABLED";
+    attribute GSR of FF_131 : label is "ENABLED";
+    attribute GSR of FF_130 : label is "ENABLED";
+    attribute GSR of FF_129 : label is "ENABLED";
+    attribute GSR of FF_128 : label is "ENABLED";
+    attribute GSR of FF_127 : label is "ENABLED";
+    attribute GSR of FF_126 : label is "ENABLED";
+    attribute GSR of FF_125 : label is "ENABLED";
+    attribute GSR of FF_124 : label is "ENABLED";
+    attribute GSR of FF_123 : label is "ENABLED";
+    attribute GSR of FF_122 : label is "ENABLED";
+    attribute GSR of FF_121 : label is "ENABLED";
+    attribute GSR of FF_120 : label is "ENABLED";
+    attribute GSR of FF_119 : label is "ENABLED";
+    attribute GSR of FF_118 : label is "ENABLED";
+    attribute GSR of FF_117 : label is "ENABLED";
+    attribute GSR of FF_116 : label is "ENABLED";
+    attribute GSR of FF_115 : label is "ENABLED";
+    attribute GSR of FF_114 : label is "ENABLED";
+    attribute GSR of FF_113 : label is "ENABLED";
+    attribute GSR of FF_112 : label is "ENABLED";
+    attribute GSR of FF_111 : label is "ENABLED";
+    attribute GSR of FF_110 : label is "ENABLED";
+    attribute GSR of FF_109 : label is "ENABLED";
+    attribute GSR of FF_108 : label is "ENABLED";
+    attribute GSR of FF_107 : label is "ENABLED";
+    attribute GSR of FF_106 : label is "ENABLED";
+    attribute GSR of FF_105 : label is "ENABLED";
+    attribute GSR of FF_104 : label is "ENABLED";
+    attribute GSR of FF_103 : label is "ENABLED";
+    attribute GSR of FF_102 : label is "ENABLED";
+    attribute GSR of FF_101 : label is "ENABLED";
+    attribute GSR of FF_100 : label is "ENABLED";
+    attribute GSR of FF_99 : label is "ENABLED";
+    attribute GSR of FF_98 : label is "ENABLED";
+    attribute GSR of FF_97 : label is "ENABLED";
+    attribute GSR of FF_96 : label is "ENABLED";
+    attribute GSR of FF_95 : label is "ENABLED";
+    attribute GSR of FF_94 : label is "ENABLED";
+    attribute GSR of FF_93 : label is "ENABLED";
+    attribute GSR of FF_92 : label is "ENABLED";
+    attribute GSR of FF_91 : label is "ENABLED";
+    attribute GSR of FF_90 : label is "ENABLED";
+    attribute GSR of FF_89 : label is "ENABLED";
+    attribute GSR of FF_88 : label is "ENABLED";
+    attribute GSR of FF_87 : label is "ENABLED";
+    attribute GSR of FF_86 : label is "ENABLED";
+    attribute GSR of FF_85 : label is "ENABLED";
+    attribute GSR of FF_84 : label is "ENABLED";
+    attribute GSR of FF_83 : label is "ENABLED";
+    attribute GSR of FF_82 : label is "ENABLED";
+    attribute GSR of FF_81 : label is "ENABLED";
+    attribute GSR of FF_80 : label is "ENABLED";
+    attribute GSR of FF_79 : label is "ENABLED";
+    attribute GSR of FF_78 : label is "ENABLED";
+    attribute GSR of FF_77 : label is "ENABLED";
+    attribute GSR of FF_76 : label is "ENABLED";
+    attribute GSR of FF_75 : label is "ENABLED";
+    attribute GSR of FF_74 : label is "ENABLED";
+    attribute GSR of FF_73 : label is "ENABLED";
+    attribute GSR of FF_72 : label is "ENABLED";
+    attribute GSR of FF_71 : label is "ENABLED";
+    attribute GSR of FF_70 : label is "ENABLED";
+    attribute GSR of FF_69 : label is "ENABLED";
+    attribute GSR of FF_68 : label is "ENABLED";
+    attribute GSR of FF_67 : label is "ENABLED";
+    attribute GSR of FF_66 : label is "ENABLED";
+    attribute GSR of FF_65 : label is "ENABLED";
+    attribute GSR of FF_64 : label is "ENABLED";
+    attribute GSR of FF_63 : label is "ENABLED";
+    attribute GSR of FF_62 : label is "ENABLED";
+    attribute GSR of FF_61 : label is "ENABLED";
+    attribute GSR of FF_60 : label is "ENABLED";
+    attribute GSR of FF_59 : label is "ENABLED";
+    attribute GSR of FF_58 : label is "ENABLED";
+    attribute GSR of FF_57 : label is "ENABLED";
+    attribute GSR of FF_56 : label is "ENABLED";
+    attribute GSR of FF_55 : label is "ENABLED";
+    attribute GSR of FF_54 : label is "ENABLED";
+    attribute GSR of FF_53 : label is "ENABLED";
+    attribute GSR of FF_52 : label is "ENABLED";
+    attribute GSR of FF_51 : label is "ENABLED";
+    attribute GSR of FF_50 : label is "ENABLED";
+    attribute GSR of FF_49 : label is "ENABLED";
+    attribute GSR of FF_48 : label is "ENABLED";
+    attribute GSR of FF_47 : label is "ENABLED";
+    attribute GSR of FF_46 : label is "ENABLED";
+    attribute GSR of FF_45 : label is "ENABLED";
+    attribute GSR of FF_44 : label is "ENABLED";
+    attribute GSR of FF_43 : label is "ENABLED";
+    attribute GSR of FF_42 : label is "ENABLED";
+    attribute GSR of FF_41 : label is "ENABLED";
+    attribute GSR of FF_40 : label is "ENABLED";
+    attribute GSR of FF_39 : label is "ENABLED";
+    attribute GSR of FF_38 : label is "ENABLED";
+    attribute GSR of FF_37 : label is "ENABLED";
+    attribute GSR of FF_36 : label is "ENABLED";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t31: AND2
+        port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+    INV_1: INV
+        port map (A=>full_i, Z=>invout_1);
+
+    AND2_t30: AND2
+        port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+    INV_0: INV
+        port map (A=>empty_i, Z=>invout_0);
+
+    OR2_t29: OR2
+        port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+    XOR2_t28: XOR2
+        port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+    XOR2_t27: XOR2
+        port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+    XOR2_t26: XOR2
+        port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+    XOR2_t25: XOR2
+        port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+    XOR2_t24: XOR2
+        port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+    XOR2_t23: XOR2
+        port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
+
+    XOR2_t22: XOR2
+        port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
+
+    XOR2_t21: XOR2
+        port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
+
+    XOR2_t20: XOR2
+        port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
+
+    XOR2_t19: XOR2
+        port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
+
+    XOR2_t18: XOR2
+        port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
+
+    XOR2_t17: XOR2
+        port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
+
+    XOR2_t16: XOR2
+        port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12);
+
+    XOR2_t15: XOR2
+        port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13);
+
+    XOR2_t14: XOR2
+        port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+    XOR2_t13: XOR2
+        port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+    XOR2_t12: XOR2
+        port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+    XOR2_t11: XOR2
+        port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+    XOR2_t10: XOR2
+        port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+    XOR2_t9: XOR2
+        port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
+
+    XOR2_t8: XOR2
+        port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
+
+    XOR2_t7: XOR2
+        port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
+
+    XOR2_t6: XOR2
+        port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
+
+    XOR2_t5: XOR2
+        port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
+
+    XOR2_t4: XOR2
+        port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
+
+    XOR2_t3: XOR2
+        port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
+
+    XOR2_t2: XOR2
+        port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12);
+
+    XOR2_t1: XOR2
+        port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13);
+
+    LUT4_41: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, 
+            AD1=>w_gcount_r213, AD0=>w_gcount_r214, 
+            DO0=>w_g2b_xor_cluster_0);
+
+    LUT4_40: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, 
+            AD1=>w_gcount_r29, AD0=>w_gcount_r210, 
+            DO0=>w_g2b_xor_cluster_1);
+
+    LUT4_39: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, 
+            AD1=>w_gcount_r25, AD0=>w_gcount_r26, 
+            DO0=>w_g2b_xor_cluster_2);
+
+    LUT4_38: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>wcount_r13);
+
+    LUT4_37: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, 
+            AD1=>w_gcount_r214, AD0=>scuba_vlo, DO0=>wcount_r12);
+
+    LUT4_36: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, 
+            AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10);
+
+    LUT4_35: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, 
+            AD1=>w_gcount_r211, AD0=>wcount_r12, DO0=>wcount_r9);
+
+    LUT4_34: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, 
+            AD1=>w_gcount_r210, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r8);
+
+    LUT4_33: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r7);
+
+    LUT4_32: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_gcount_r26, AD0=>scuba_vlo, DO0=>wcount_r6);
+
+    LUT4_31: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_gcount_r25, AD0=>w_gcount_r26, DO0=>wcount_r5);
+
+    LUT4_30: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, 
+            AD1=>w_gcount_r26, AD0=>scuba_vlo, 
+            DO0=>w_g2b_xor_cluster_2_1);
+
+    LUT4_29: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r4);
+
+    LUT4_28: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r3);
+
+    LUT4_27: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r22, DO0=>wcount_r2);
+
+    LUT4_26: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3);
+
+    LUT4_25: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, 
+            DO0=>wcount_r1);
+
+    LUT4_24: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, 
+            AD1=>w_gcount_r22, AD0=>scuba_vlo, 
+            DO0=>w_g2b_xor_cluster_3_1);
+
+    LUT4_23: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, 
+            DO0=>wcount_r0);
+
+    LUT4_22: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, 
+            AD1=>r_gcount_w213, AD0=>r_gcount_w214, 
+            DO0=>r_g2b_xor_cluster_0);
+
+    LUT4_21: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, 
+            AD1=>r_gcount_w29, AD0=>r_gcount_w210, 
+            DO0=>r_g2b_xor_cluster_1);
+
+    LUT4_20: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, 
+            AD1=>r_gcount_w25, AD0=>r_gcount_w26, 
+            DO0=>r_g2b_xor_cluster_2);
+
+    LUT4_19: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>rcount_w13);
+
+    LUT4_18: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, 
+            AD1=>r_gcount_w214, AD0=>scuba_vlo, DO0=>rcount_w12);
+
+    LUT4_17: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, 
+            AD1=>r_gcount_w212, AD0=>rcount_w13, DO0=>rcount_w10);
+
+    LUT4_16: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, 
+            AD1=>r_gcount_w211, AD0=>rcount_w12, DO0=>rcount_w9);
+
+    LUT4_15: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, 
+            AD1=>r_gcount_w210, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w8);
+
+    LUT4_14: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w7);
+
+    LUT4_13: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_gcount_w26, AD0=>scuba_vlo, DO0=>rcount_w6);
+
+    LUT4_12: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_gcount_w25, AD0=>r_gcount_w26, DO0=>rcount_w5);
+
+    LUT4_11: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, 
+            AD1=>r_gcount_w26, AD0=>scuba_vlo, 
+            DO0=>r_g2b_xor_cluster_2_1);
+
+    LUT4_10: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w4);
+
+    LUT4_9: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w3);
+
+    LUT4_8: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w22, DO0=>rcount_w2);
+
+    LUT4_7: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3);
+
+    LUT4_6: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, 
+            DO0=>rcount_w1);
+
+    LUT4_5: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, 
+            AD1=>r_gcount_w22, AD0=>scuba_vlo, 
+            DO0=>r_g2b_xor_cluster_3_1);
+
+    LUT4_4: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, 
+            DO0=>rcount_w0);
+
+    XOR2_t0: XOR2
+        port map (A=>w_gcount_r214, B=>rptr_14, Z=>rfill_sub_msb);
+
+    LUT4_3: ROM16X1A
+        generic map (initval=> X"0410")
+        port map (AD3=>rptr_14, AD2=>rcount_14, AD1=>w_gcount_r214, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+    LUT4_2: ROM16X1A
+        generic map (initval=> X"1004")
+        port map (AD3=>rptr_14, AD2=>rcount_14, AD1=>w_gcount_r214, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"0140")
+        port map (AD3=>wptr_14, AD2=>wcount_14, AD1=>r_gcount_w214, 
+            AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"4001")
+        port map (AD3=>wptr_14, AD2=>wcount_14, AD1=>r_gcount_w214, 
+            AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+    pdp_ram_0_0_31: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), 
+            DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), 
+            DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, 
+            DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, 
+            ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, 
+            ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, 
+            ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, 
+            WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>wptr_13, 
+            RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, 
+            ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, 
+            ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, 
+            CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, 
+            CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset, 
+            DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, 
+            DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, 
+            DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, 
+            DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, 
+            DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, DOB2=>mdout1_0_2, 
+            DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, DOB5=>mdout1_0_5, 
+            DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, DOB8=>mdout1_0_8, 
+            DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, 
+            DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, 
+            DOB17=>open);
+
+    pdp_ram_0_1_30: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), 
+            DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), 
+            DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>mdout1_0_9, DOB1=>mdout1_0_10, 
+            DOB2=>mdout1_0_11, DOB3=>mdout1_0_12, DOB4=>mdout1_0_13, 
+            DOB5=>mdout1_0_14, DOB6=>mdout1_0_15, DOB7=>mdout1_0_16, 
+            DOB8=>mdout1_0_17, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_0_2_29: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20), 
+            DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23), 
+            DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>mdout1_0_18, DOB1=>mdout1_0_19, 
+            DOB2=>mdout1_0_20, DOB3=>mdout1_0_21, DOB4=>mdout1_0_22, 
+            DOB5=>mdout1_0_23, DOB6=>mdout1_0_24, DOB7=>mdout1_0_25, 
+            DOB8=>mdout1_0_26, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_0_3_28: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29), 
+            DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32), 
+            DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>mdout1_0_27, DOB1=>mdout1_0_28, 
+            DOB2=>mdout1_0_29, DOB3=>mdout1_0_30, DOB4=>mdout1_0_31, 
+            DOB5=>mdout1_0_32, DOB6=>mdout1_0_33, DOB7=>mdout1_0_34, 
+            DOB8=>mdout1_0_35, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_1_0_27: DP16KC
+        generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), 
+            DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), 
+            DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, 
+            DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, 
+            ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, 
+            ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, 
+            ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, 
+            WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>wptr_13, 
+            RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, 
+            ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, 
+            ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, 
+            CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, 
+            CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset, 
+            DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, 
+            DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, 
+            DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, 
+            DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, 
+            DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, DOB2=>mdout1_1_2, 
+            DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, DOB5=>mdout1_1_5, 
+            DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, DOB8=>mdout1_1_8, 
+            DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, 
+            DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, 
+            DOB17=>open);
+
+    pdp_ram_1_1_26: DP16KC
+        generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), 
+            DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), 
+            DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>mdout1_1_9, DOB1=>mdout1_1_10, 
+            DOB2=>mdout1_1_11, DOB3=>mdout1_1_12, DOB4=>mdout1_1_13, 
+            DOB5=>mdout1_1_14, DOB6=>mdout1_1_15, DOB7=>mdout1_1_16, 
+            DOB8=>mdout1_1_17, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_1_2_25: DP16KC
+        generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20), 
+            DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23), 
+            DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>mdout1_1_18, DOB1=>mdout1_1_19, 
+            DOB2=>mdout1_1_20, DOB3=>mdout1_1_21, DOB4=>mdout1_1_22, 
+            DOB5=>mdout1_1_23, DOB6=>mdout1_1_24, DOB7=>mdout1_1_25, 
+            DOB8=>mdout1_1_26, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_1_3_24: DP16KC
+        generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29), 
+            DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32), 
+            DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>mdout1_1_27, DOB1=>mdout1_1_28, 
+            DOB2=>mdout1_1_29, DOB3=>mdout1_1_30, DOB4=>mdout1_1_31, 
+            DOB5=>mdout1_1_32, DOB6=>mdout1_1_33, DOB7=>mdout1_1_34, 
+            DOB8=>mdout1_1_35, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_2_0_23: DP16KC
+        generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), 
+            DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), 
+            DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, 
+            DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, 
+            ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, 
+            ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, 
+            ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, 
+            WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>wptr_13, 
+            RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, 
+            ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, 
+            ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, 
+            CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, 
+            CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset, 
+            DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, 
+            DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, 
+            DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, 
+            DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, 
+            DOB0=>mdout1_2_0, DOB1=>mdout1_2_1, DOB2=>mdout1_2_2, 
+            DOB3=>mdout1_2_3, DOB4=>mdout1_2_4, DOB5=>mdout1_2_5, 
+            DOB6=>mdout1_2_6, DOB7=>mdout1_2_7, DOB8=>mdout1_2_8, 
+            DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, 
+            DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, 
+            DOB17=>open);
+
+    pdp_ram_2_1_22: DP16KC
+        generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), 
+            DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), 
+            DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>mdout1_2_9, DOB1=>mdout1_2_10, 
+            DOB2=>mdout1_2_11, DOB3=>mdout1_2_12, DOB4=>mdout1_2_13, 
+            DOB5=>mdout1_2_14, DOB6=>mdout1_2_15, DOB7=>mdout1_2_16, 
+            DOB8=>mdout1_2_17, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_2_2_21: DP16KC
+        generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20), 
+            DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23), 
+            DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>mdout1_2_18, DOB1=>mdout1_2_19, 
+            DOB2=>mdout1_2_20, DOB3=>mdout1_2_21, DOB4=>mdout1_2_22, 
+            DOB5=>mdout1_2_23, DOB6=>mdout1_2_24, DOB7=>mdout1_2_25, 
+            DOB8=>mdout1_2_26, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_2_3_20: DP16KC
+        generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29), 
+            DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32), 
+            DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>mdout1_2_27, DOB1=>mdout1_2_28, 
+            DOB2=>mdout1_2_29, DOB3=>mdout1_2_30, DOB4=>mdout1_2_31, 
+            DOB5=>mdout1_2_32, DOB6=>mdout1_2_33, DOB7=>mdout1_2_34, 
+            DOB8=>mdout1_2_35, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_3_0_19: DP16KC
+        generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), 
+            DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), 
+            DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, 
+            DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, 
+            ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, 
+            ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, 
+            ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, 
+            WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>wptr_13, 
+            RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, 
+            ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, 
+            ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, 
+            CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, 
+            CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset, 
+            DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, 
+            DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, 
+            DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, 
+            DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, 
+            DOB0=>mdout1_3_0, DOB1=>mdout1_3_1, DOB2=>mdout1_3_2, 
+            DOB3=>mdout1_3_3, DOB4=>mdout1_3_4, DOB5=>mdout1_3_5, 
+            DOB6=>mdout1_3_6, DOB7=>mdout1_3_7, DOB8=>mdout1_3_8, 
+            DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, 
+            DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, 
+            DOB17=>open);
+
+    pdp_ram_3_1_18: DP16KC
+        generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), 
+            DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), 
+            DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>mdout1_3_9, DOB1=>mdout1_3_10, 
+            DOB2=>mdout1_3_11, DOB3=>mdout1_3_12, DOB4=>mdout1_3_13, 
+            DOB5=>mdout1_3_14, DOB6=>mdout1_3_15, DOB7=>mdout1_3_16, 
+            DOB8=>mdout1_3_17, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_3_2_17: DP16KC
+        generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20), 
+            DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23), 
+            DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>mdout1_3_18, DOB1=>mdout1_3_19, 
+            DOB2=>mdout1_3_20, DOB3=>mdout1_3_21, DOB4=>mdout1_3_22, 
+            DOB5=>mdout1_3_23, DOB6=>mdout1_3_24, DOB7=>mdout1_3_25, 
+            DOB8=>mdout1_3_26, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_3_3_16: DP16KC
+        generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29), 
+            DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32), 
+            DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>mdout1_3_27, DOB1=>mdout1_3_28, 
+            DOB2=>mdout1_3_29, DOB3=>mdout1_3_30, DOB4=>mdout1_3_31, 
+            DOB5=>mdout1_3_32, DOB6=>mdout1_3_33, DOB7=>mdout1_3_34, 
+            DOB8=>mdout1_3_35, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_4_0_15: DP16KC
+        generic map (CSDECODE_B=> "0b100", CSDECODE_A=> "0b100", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), 
+            DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), 
+            DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, 
+            DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, 
+            ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, 
+            ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, 
+            ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, 
+            WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>wptr_13, 
+            RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, 
+            ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, 
+            ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, 
+            CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, 
+            CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset, 
+            DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, 
+            DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, 
+            DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, 
+            DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, 
+            DOB0=>mdout1_4_0, DOB1=>mdout1_4_1, DOB2=>mdout1_4_2, 
+            DOB3=>mdout1_4_3, DOB4=>mdout1_4_4, DOB5=>mdout1_4_5, 
+            DOB6=>mdout1_4_6, DOB7=>mdout1_4_7, DOB8=>mdout1_4_8, 
+            DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, 
+            DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, 
+            DOB17=>open);
+
+    pdp_ram_4_1_14: DP16KC
+        generic map (CSDECODE_B=> "0b100", CSDECODE_A=> "0b100", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), 
+            DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), 
+            DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>mdout1_4_9, DOB1=>mdout1_4_10, 
+            DOB2=>mdout1_4_11, DOB3=>mdout1_4_12, DOB4=>mdout1_4_13, 
+            DOB5=>mdout1_4_14, DOB6=>mdout1_4_15, DOB7=>mdout1_4_16, 
+            DOB8=>mdout1_4_17, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_4_2_13: DP16KC
+        generic map (CSDECODE_B=> "0b100", CSDECODE_A=> "0b100", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20), 
+            DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23), 
+            DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>mdout1_4_18, DOB1=>mdout1_4_19, 
+            DOB2=>mdout1_4_20, DOB3=>mdout1_4_21, DOB4=>mdout1_4_22, 
+            DOB5=>mdout1_4_23, DOB6=>mdout1_4_24, DOB7=>mdout1_4_25, 
+            DOB8=>mdout1_4_26, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_4_3_12: DP16KC
+        generic map (CSDECODE_B=> "0b100", CSDECODE_A=> "0b100", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29), 
+            DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32), 
+            DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>mdout1_4_27, DOB1=>mdout1_4_28, 
+            DOB2=>mdout1_4_29, DOB3=>mdout1_4_30, DOB4=>mdout1_4_31, 
+            DOB5=>mdout1_4_32, DOB6=>mdout1_4_33, DOB7=>mdout1_4_34, 
+            DOB8=>mdout1_4_35, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_5_0_11: DP16KC
+        generic map (CSDECODE_B=> "0b101", CSDECODE_A=> "0b101", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), 
+            DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), 
+            DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, 
+            DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, 
+            ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, 
+            ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, 
+            ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, 
+            WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>wptr_13, 
+            RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, 
+            ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, 
+            ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, 
+            CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, 
+            CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset, 
+            DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, 
+            DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, 
+            DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, 
+            DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, 
+            DOB0=>mdout1_5_0, DOB1=>mdout1_5_1, DOB2=>mdout1_5_2, 
+            DOB3=>mdout1_5_3, DOB4=>mdout1_5_4, DOB5=>mdout1_5_5, 
+            DOB6=>mdout1_5_6, DOB7=>mdout1_5_7, DOB8=>mdout1_5_8, 
+            DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, 
+            DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, 
+            DOB17=>open);
+
+    pdp_ram_5_1_10: DP16KC
+        generic map (CSDECODE_B=> "0b101", CSDECODE_A=> "0b101", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), 
+            DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), 
+            DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>mdout1_5_9, DOB1=>mdout1_5_10, 
+            DOB2=>mdout1_5_11, DOB3=>mdout1_5_12, DOB4=>mdout1_5_13, 
+            DOB5=>mdout1_5_14, DOB6=>mdout1_5_15, DOB7=>mdout1_5_16, 
+            DOB8=>mdout1_5_17, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_5_2_9: DP16KC
+        generic map (CSDECODE_B=> "0b101", CSDECODE_A=> "0b101", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20), 
+            DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23), 
+            DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>mdout1_5_18, DOB1=>mdout1_5_19, 
+            DOB2=>mdout1_5_20, DOB3=>mdout1_5_21, DOB4=>mdout1_5_22, 
+            DOB5=>mdout1_5_23, DOB6=>mdout1_5_24, DOB7=>mdout1_5_25, 
+            DOB8=>mdout1_5_26, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_5_3_8: DP16KC
+        generic map (CSDECODE_B=> "0b101", CSDECODE_A=> "0b101", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29), 
+            DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32), 
+            DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>mdout1_5_27, DOB1=>mdout1_5_28, 
+            DOB2=>mdout1_5_29, DOB3=>mdout1_5_30, DOB4=>mdout1_5_31, 
+            DOB5=>mdout1_5_32, DOB6=>mdout1_5_33, DOB7=>mdout1_5_34, 
+            DOB8=>mdout1_5_35, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_6_0_7: DP16KC
+        generic map (CSDECODE_B=> "0b110", CSDECODE_A=> "0b110", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), 
+            DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), 
+            DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, 
+            DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, 
+            ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, 
+            ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, 
+            ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, 
+            WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>wptr_13, 
+            RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, 
+            ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, 
+            ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, 
+            CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, 
+            CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset, 
+            DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, 
+            DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, 
+            DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, 
+            DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, 
+            DOB0=>mdout1_6_0, DOB1=>mdout1_6_1, DOB2=>mdout1_6_2, 
+            DOB3=>mdout1_6_3, DOB4=>mdout1_6_4, DOB5=>mdout1_6_5, 
+            DOB6=>mdout1_6_6, DOB7=>mdout1_6_7, DOB8=>mdout1_6_8, 
+            DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, 
+            DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, 
+            DOB17=>open);
+
+    pdp_ram_6_1_6: DP16KC
+        generic map (CSDECODE_B=> "0b110", CSDECODE_A=> "0b110", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), 
+            DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), 
+            DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>mdout1_6_9, DOB1=>mdout1_6_10, 
+            DOB2=>mdout1_6_11, DOB3=>mdout1_6_12, DOB4=>mdout1_6_13, 
+            DOB5=>mdout1_6_14, DOB6=>mdout1_6_15, DOB7=>mdout1_6_16, 
+            DOB8=>mdout1_6_17, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_6_2_5: DP16KC
+        generic map (CSDECODE_B=> "0b110", CSDECODE_A=> "0b110", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20), 
+            DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23), 
+            DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>mdout1_6_18, DOB1=>mdout1_6_19, 
+            DOB2=>mdout1_6_20, DOB3=>mdout1_6_21, DOB4=>mdout1_6_22, 
+            DOB5=>mdout1_6_23, DOB6=>mdout1_6_24, DOB7=>mdout1_6_25, 
+            DOB8=>mdout1_6_26, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_6_3_4: DP16KC
+        generic map (CSDECODE_B=> "0b110", CSDECODE_A=> "0b110", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29), 
+            DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32), 
+            DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>mdout1_6_27, DOB1=>mdout1_6_28, 
+            DOB2=>mdout1_6_29, DOB3=>mdout1_6_30, DOB4=>mdout1_6_31, 
+            DOB5=>mdout1_6_32, DOB6=>mdout1_6_33, DOB7=>mdout1_6_34, 
+            DOB8=>mdout1_6_35, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_7_0_3: DP16KC
+        generic map (CSDECODE_B=> "0b111", CSDECODE_A=> "0b111", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), 
+            DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), 
+            DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, 
+            DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, 
+            ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, 
+            ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, 
+            ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, 
+            WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>wptr_13, 
+            RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, 
+            DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, 
+            DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, 
+            DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, 
+            DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, 
+            DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, 
+            DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, 
+            ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, 
+            ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, 
+            ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, 
+            CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, 
+            CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset, 
+            DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, 
+            DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, 
+            DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, 
+            DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, 
+            DOB0=>mdout1_7_0, DOB1=>mdout1_7_1, DOB2=>mdout1_7_2, 
+            DOB3=>mdout1_7_3, DOB4=>mdout1_7_4, DOB5=>mdout1_7_5, 
+            DOB6=>mdout1_7_6, DOB7=>mdout1_7_7, DOB8=>mdout1_7_8, 
+            DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, 
+            DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, 
+            DOB17=>open);
+
+    pdp_ram_7_1_2: DP16KC
+        generic map (CSDECODE_B=> "0b111", CSDECODE_A=> "0b111", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), 
+            DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), 
+            DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>mdout1_7_9, DOB1=>mdout1_7_10, 
+            DOB2=>mdout1_7_11, DOB3=>mdout1_7_12, DOB4=>mdout1_7_13, 
+            DOB5=>mdout1_7_14, DOB6=>mdout1_7_15, DOB7=>mdout1_7_16, 
+            DOB8=>mdout1_7_17, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_7_2_1: DP16KC
+        generic map (CSDECODE_B=> "0b111", CSDECODE_A=> "0b111", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20), 
+            DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23), 
+            DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>mdout1_7_18, DOB1=>mdout1_7_19, 
+            DOB2=>mdout1_7_20, DOB3=>mdout1_7_21, DOB4=>mdout1_7_22, 
+            DOB5=>mdout1_7_23, DOB6=>mdout1_7_24, DOB7=>mdout1_7_25, 
+            DOB8=>mdout1_7_26, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_7_3_0: DP16KC
+        generic map (CSDECODE_B=> "0b111", CSDECODE_A=> "0b111", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29), 
+            DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32), 
+            DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rptr_13, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>mdout1_7_27, DOB1=>mdout1_7_28, 
+            DOB2=>mdout1_7_29, DOB3=>mdout1_7_30, DOB4=>mdout1_7_31, 
+            DOB5=>mdout1_7_32, DOB6=>mdout1_7_33, DOB7=>mdout1_7_34, 
+            DOB8=>mdout1_7_35, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    FF_169: FD1P3BX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>wcount_0);
+
+    FF_168: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_167: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_166: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_165: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_164: FD1P3DX
+        port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_163: FD1P3DX
+        port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_6);
+
+    FF_162: FD1P3DX
+        port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_7);
+
+    FF_161: FD1P3DX
+        port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_8);
+
+    FF_160: FD1P3DX
+        port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_9);
+
+    FF_159: FD1P3DX
+        port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_10);
+
+    FF_158: FD1P3DX
+        port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_11);
+
+    FF_157: FD1P3DX
+        port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_12);
+
+    FF_156: FD1P3DX
+        port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_13);
+
+    FF_155: FD1P3DX
+        port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_14);
+
+    FF_154: FD1P3DX
+        port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_0);
+
+    FF_153: FD1P3DX
+        port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_1);
+
+    FF_152: FD1P3DX
+        port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_2);
+
+    FF_151: FD1P3DX
+        port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_3);
+
+    FF_150: FD1P3DX
+        port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_4);
+
+    FF_149: FD1P3DX
+        port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_5);
+
+    FF_148: FD1P3DX
+        port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_6);
+
+    FF_147: FD1P3DX
+        port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_7);
+
+    FF_146: FD1P3DX
+        port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_8);
+
+    FF_145: FD1P3DX
+        port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_9);
+
+    FF_144: FD1P3DX
+        port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_10);
+
+    FF_143: FD1P3DX
+        port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_11);
+
+    FF_142: FD1P3DX
+        port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_12);
+
+    FF_141: FD1P3DX
+        port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_13);
+
+    FF_140: FD1P3DX
+        port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_14);
+
+    FF_139: FD1P3DX
+        port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_0);
+
+    FF_138: FD1P3DX
+        port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_1);
+
+    FF_137: FD1P3DX
+        port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_2);
+
+    FF_136: FD1P3DX
+        port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_3);
+
+    FF_135: FD1P3DX
+        port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_4);
+
+    FF_134: FD1P3DX
+        port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_5);
+
+    FF_133: FD1P3DX
+        port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_6);
+
+    FF_132: FD1P3DX
+        port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_7);
+
+    FF_131: FD1P3DX
+        port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_8);
+
+    FF_130: FD1P3DX
+        port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_9);
+
+    FF_129: FD1P3DX
+        port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_10);
+
+    FF_128: FD1P3DX
+        port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_11);
+
+    FF_127: FD1P3DX
+        port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_12);
+
+    FF_126: FD1P3DX
+        port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_13);
+
+    FF_125: FD1P3DX
+        port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_14);
+
+    FF_124: FD1P3BX
+        port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, 
+            Q=>rcount_0);
+
+    FF_123: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_1);
+
+    FF_122: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_2);
+
+    FF_121: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_3);
+
+    FF_120: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_4);
+
+    FF_119: FD1P3DX
+        port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_5);
+
+    FF_118: FD1P3DX
+        port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_6);
+
+    FF_117: FD1P3DX
+        port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_7);
+
+    FF_116: FD1P3DX
+        port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_8);
+
+    FF_115: FD1P3DX
+        port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_9);
+
+    FF_114: FD1P3DX
+        port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_10);
+
+    FF_113: FD1P3DX
+        port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_11);
+
+    FF_112: FD1P3DX
+        port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_12);
+
+    FF_111: FD1P3DX
+        port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_13);
+
+    FF_110: FD1P3DX
+        port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_14);
+
+    FF_109: FD1P3DX
+        port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_0);
+
+    FF_108: FD1P3DX
+        port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_1);
+
+    FF_107: FD1P3DX
+        port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_2);
+
+    FF_106: FD1P3DX
+        port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_3);
+
+    FF_105: FD1P3DX
+        port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_4);
+
+    FF_104: FD1P3DX
+        port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_5);
+
+    FF_103: FD1P3DX
+        port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_6);
+
+    FF_102: FD1P3DX
+        port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_7);
+
+    FF_101: FD1P3DX
+        port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_8);
+
+    FF_100: FD1P3DX
+        port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_9);
+
+    FF_99: FD1P3DX
+        port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_10);
+
+    FF_98: FD1P3DX
+        port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_11);
+
+    FF_97: FD1P3DX
+        port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_12);
+
+    FF_96: FD1P3DX
+        port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_13);
+
+    FF_95: FD1P3DX
+        port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_14);
+
+    FF_94: FD1P3DX
+        port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_0);
+
+    FF_93: FD1P3DX
+        port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_1);
+
+    FF_92: FD1P3DX
+        port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_2);
+
+    FF_91: FD1P3DX
+        port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_3);
+
+    FF_90: FD1P3DX
+        port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_4);
+
+    FF_89: FD1P3DX
+        port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_5);
+
+    FF_88: FD1P3DX
+        port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_6);
+
+    FF_87: FD1P3DX
+        port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_7);
+
+    FF_86: FD1P3DX
+        port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_8);
+
+    FF_85: FD1P3DX
+        port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_9);
+
+    FF_84: FD1P3DX
+        port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_10);
+
+    FF_83: FD1P3DX
+        port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_11);
+
+    FF_82: FD1P3DX
+        port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_12);
+
+    FF_81: FD1P3DX
+        port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_13);
+
+    FF_80: FD1P3DX
+        port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_14);
+
+    FF_79: FD1P3DX
+        port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, 
+            Q=>rptr_11_ff);
+
+    FF_78: FD1P3DX
+        port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, 
+            Q=>rptr_12_ff);
+
+    FF_77: FD1P3DX
+        port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, 
+            Q=>rptr_13_ff);
+
+    FF_76: FD1S3DX
+        port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+    FF_75: FD1S3DX
+        port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+    FF_74: FD1S3DX
+        port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+    FF_73: FD1S3DX
+        port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+    FF_72: FD1S3DX
+        port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+    FF_71: FD1S3DX
+        port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+    FF_70: FD1S3DX
+        port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
+
+    FF_69: FD1S3DX
+        port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
+
+    FF_68: FD1S3DX
+        port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
+
+    FF_67: FD1S3DX
+        port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
+
+    FF_66: FD1S3DX
+        port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r10);
+
+    FF_65: FD1S3DX
+        port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r11);
+
+    FF_64: FD1S3DX
+        port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r12);
+
+    FF_63: FD1S3DX
+        port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r13);
+
+    FF_62: FD1S3DX
+        port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r14);
+
+    FF_61: FD1S3DX
+        port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+    FF_60: FD1S3DX
+        port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+    FF_59: FD1S3DX
+        port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+    FF_58: FD1S3DX
+        port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+    FF_57: FD1S3DX
+        port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+    FF_56: FD1S3DX
+        port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+    FF_55: FD1S3DX
+        port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+    FF_54: FD1S3DX
+        port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
+
+    FF_53: FD1S3DX
+        port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
+
+    FF_52: FD1S3DX
+        port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
+
+    FF_51: FD1S3DX
+        port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
+
+    FF_50: FD1S3DX
+        port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
+
+    FF_49: FD1S3DX
+        port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
+
+    FF_48: FD1S3DX
+        port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13);
+
+    FF_47: FD1S3DX
+        port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14);
+
+    FF_46: FD1S3DX
+        port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r20);
+
+    FF_45: FD1S3DX
+        port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r21);
+
+    FF_44: FD1S3DX
+        port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r22);
+
+    FF_43: FD1S3DX
+        port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r23);
+
+    FF_42: FD1S3DX
+        port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r24);
+
+    FF_41: FD1S3DX
+        port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r25);
+
+    FF_40: FD1S3DX
+        port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r26);
+
+    FF_39: FD1S3DX
+        port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r27);
+
+    FF_38: FD1S3DX
+        port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r28);
+
+    FF_37: FD1S3DX
+        port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r29);
+
+    FF_36: FD1S3DX
+        port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r210);
+
+    FF_35: FD1S3DX
+        port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r211);
+
+    FF_34: FD1S3DX
+        port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r212);
+
+    FF_33: FD1S3DX
+        port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r213);
+
+    FF_32: FD1S3DX
+        port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r214);
+
+    FF_31: FD1S3DX
+        port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+    FF_30: FD1S3DX
+        port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+    FF_29: FD1S3DX
+        port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+    FF_28: FD1S3DX
+        port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+    FF_27: FD1S3DX
+        port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+    FF_26: FD1S3DX
+        port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+    FF_25: FD1S3DX
+        port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
+
+    FF_24: FD1S3DX
+        port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
+
+    FF_23: FD1S3DX
+        port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
+
+    FF_22: FD1S3DX
+        port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
+
+    FF_21: FD1S3DX
+        port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, 
+            Q=>r_gcount_w210);
+
+    FF_20: FD1S3DX
+        port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, 
+            Q=>r_gcount_w211);
+
+    FF_19: FD1S3DX
+        port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, 
+            Q=>r_gcount_w212);
+
+    FF_18: FD1S3DX
+        port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, 
+            Q=>r_gcount_w213);
+
+    FF_17: FD1S3DX
+        port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, 
+            Q=>r_gcount_w214);
+
+    FF_16: FD1S3DX
+        port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0));
+
+    FF_15: FD1S3DX
+        port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1));
+
+    FF_14: FD1S3DX
+        port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2));
+
+    FF_13: FD1S3DX
+        port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3));
+
+    FF_12: FD1S3DX
+        port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4));
+
+    FF_11: FD1S3DX
+        port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5));
+
+    FF_10: FD1S3DX
+        port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6));
+
+    FF_9: FD1S3DX
+        port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7));
+
+    FF_8: FD1S3DX
+        port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8));
+
+    FF_7: FD1S3DX
+        port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9));
+
+    FF_6: FD1S3DX
+        port map (D=>rfill_sub_10, CK=>RdClock, CD=>rRst, Q=>RCNT(10));
+
+    FF_5: FD1S3DX
+        port map (D=>rfill_sub_11, CK=>RdClock, CD=>rRst, Q=>RCNT(11));
+
+    FF_4: FD1S3DX
+        port map (D=>rfill_sub_12, CK=>RdClock, CD=>rRst, Q=>RCNT(12));
+
+    FF_3: FD1S3DX
+        port map (D=>rfill_sub_13, CK=>RdClock, CD=>rRst, Q=>RCNT(13));
+
+    FF_2: FD1S3DX
+        port map (D=>rfill_sub_14, CK=>RdClock, CD=>rRst, Q=>RCNT(14));
+
+    FF_1: FD1S3BX
+        port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+    FF_0: FD1S3DX
+        port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+    w_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, 
+            S1=>open);
+
+    w_gctr_0: CU2
+        port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, 
+            NC0=>iwcount_0, NC1=>iwcount_1);
+
+    w_gctr_1: CU2
+        port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, 
+            NC0=>iwcount_2, NC1=>iwcount_3);
+
+    w_gctr_2: CU2
+        port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, 
+            NC0=>iwcount_4, NC1=>iwcount_5);
+
+    w_gctr_3: CU2
+        port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, 
+            NC0=>iwcount_6, NC1=>iwcount_7);
+
+    w_gctr_4: CU2
+        port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, 
+            NC0=>iwcount_8, NC1=>iwcount_9);
+
+    w_gctr_5: CU2
+        port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, 
+            NC0=>iwcount_10, NC1=>iwcount_11);
+
+    w_gctr_6: CU2
+        port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, 
+            NC0=>iwcount_12, NC1=>iwcount_13);
+
+    w_gctr_7: CU2
+        port map (CI=>co6, PC0=>wcount_14, PC1=>scuba_vlo, CO=>co7, 
+            NC0=>iwcount_14, NC1=>open);
+
+    r_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, 
+            S1=>open);
+
+    r_gctr_0: CU2
+        port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, 
+            NC0=>ircount_0, NC1=>ircount_1);
+
+    r_gctr_1: CU2
+        port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, 
+            NC0=>ircount_2, NC1=>ircount_3);
+
+    r_gctr_2: CU2
+        port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, 
+            NC0=>ircount_4, NC1=>ircount_5);
+
+    r_gctr_3: CU2
+        port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, 
+            NC0=>ircount_6, NC1=>ircount_7);
+
+    r_gctr_4: CU2
+        port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, 
+            NC0=>ircount_8, NC1=>ircount_9);
+
+    r_gctr_5: CU2
+        port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, 
+            NC0=>ircount_10, NC1=>ircount_11);
+
+    r_gctr_6: CU2
+        port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, 
+            NC0=>ircount_12, NC1=>ircount_13);
+
+    r_gctr_7: CU2
+        port map (CI=>co6_1, PC0=>rcount_14, PC1=>scuba_vlo, CO=>co7_1, 
+            NC0=>ircount_14, NC1=>open);
+
+    mux_35: MUX81
+        port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, 
+            D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0, 
+            D6=>mdout1_6_0, D7=>mdout1_7_0, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(0));
+
+    mux_34: MUX81
+        port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, 
+            D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1, 
+            D6=>mdout1_6_1, D7=>mdout1_7_1, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(1));
+
+    mux_33: MUX81
+        port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, 
+            D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2, 
+            D6=>mdout1_6_2, D7=>mdout1_7_2, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(2));
+
+    mux_32: MUX81
+        port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, 
+            D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3, 
+            D6=>mdout1_6_3, D7=>mdout1_7_3, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(3));
+
+    mux_31: MUX81
+        port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, 
+            D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4, 
+            D6=>mdout1_6_4, D7=>mdout1_7_4, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(4));
+
+    mux_30: MUX81
+        port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, 
+            D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5, 
+            D6=>mdout1_6_5, D7=>mdout1_7_5, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(5));
+
+    mux_29: MUX81
+        port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, 
+            D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6, 
+            D6=>mdout1_6_6, D7=>mdout1_7_6, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(6));
+
+    mux_28: MUX81
+        port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, 
+            D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7, 
+            D6=>mdout1_6_7, D7=>mdout1_7_7, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(7));
+
+    mux_27: MUX81
+        port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, 
+            D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8, 
+            D6=>mdout1_6_8, D7=>mdout1_7_8, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(8));
+
+    mux_26: MUX81
+        port map (D0=>mdout1_0_9, D1=>mdout1_1_9, D2=>mdout1_2_9, 
+            D3=>mdout1_3_9, D4=>mdout1_4_9, D5=>mdout1_5_9, 
+            D6=>mdout1_6_9, D7=>mdout1_7_9, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(9));
+
+    mux_25: MUX81
+        port map (D0=>mdout1_0_10, D1=>mdout1_1_10, D2=>mdout1_2_10, 
+            D3=>mdout1_3_10, D4=>mdout1_4_10, D5=>mdout1_5_10, 
+            D6=>mdout1_6_10, D7=>mdout1_7_10, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(10));
+
+    mux_24: MUX81
+        port map (D0=>mdout1_0_11, D1=>mdout1_1_11, D2=>mdout1_2_11, 
+            D3=>mdout1_3_11, D4=>mdout1_4_11, D5=>mdout1_5_11, 
+            D6=>mdout1_6_11, D7=>mdout1_7_11, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(11));
+
+    mux_23: MUX81
+        port map (D0=>mdout1_0_12, D1=>mdout1_1_12, D2=>mdout1_2_12, 
+            D3=>mdout1_3_12, D4=>mdout1_4_12, D5=>mdout1_5_12, 
+            D6=>mdout1_6_12, D7=>mdout1_7_12, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(12));
+
+    mux_22: MUX81
+        port map (D0=>mdout1_0_13, D1=>mdout1_1_13, D2=>mdout1_2_13, 
+            D3=>mdout1_3_13, D4=>mdout1_4_13, D5=>mdout1_5_13, 
+            D6=>mdout1_6_13, D7=>mdout1_7_13, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(13));
+
+    mux_21: MUX81
+        port map (D0=>mdout1_0_14, D1=>mdout1_1_14, D2=>mdout1_2_14, 
+            D3=>mdout1_3_14, D4=>mdout1_4_14, D5=>mdout1_5_14, 
+            D6=>mdout1_6_14, D7=>mdout1_7_14, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(14));
+
+    mux_20: MUX81
+        port map (D0=>mdout1_0_15, D1=>mdout1_1_15, D2=>mdout1_2_15, 
+            D3=>mdout1_3_15, D4=>mdout1_4_15, D5=>mdout1_5_15, 
+            D6=>mdout1_6_15, D7=>mdout1_7_15, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(15));
+
+    mux_19: MUX81
+        port map (D0=>mdout1_0_16, D1=>mdout1_1_16, D2=>mdout1_2_16, 
+            D3=>mdout1_3_16, D4=>mdout1_4_16, D5=>mdout1_5_16, 
+            D6=>mdout1_6_16, D7=>mdout1_7_16, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(16));
+
+    mux_18: MUX81
+        port map (D0=>mdout1_0_17, D1=>mdout1_1_17, D2=>mdout1_2_17, 
+            D3=>mdout1_3_17, D4=>mdout1_4_17, D5=>mdout1_5_17, 
+            D6=>mdout1_6_17, D7=>mdout1_7_17, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(17));
+
+    mux_17: MUX81
+        port map (D0=>mdout1_0_18, D1=>mdout1_1_18, D2=>mdout1_2_18, 
+            D3=>mdout1_3_18, D4=>mdout1_4_18, D5=>mdout1_5_18, 
+            D6=>mdout1_6_18, D7=>mdout1_7_18, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(18));
+
+    mux_16: MUX81
+        port map (D0=>mdout1_0_19, D1=>mdout1_1_19, D2=>mdout1_2_19, 
+            D3=>mdout1_3_19, D4=>mdout1_4_19, D5=>mdout1_5_19, 
+            D6=>mdout1_6_19, D7=>mdout1_7_19, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(19));
+
+    mux_15: MUX81
+        port map (D0=>mdout1_0_20, D1=>mdout1_1_20, D2=>mdout1_2_20, 
+            D3=>mdout1_3_20, D4=>mdout1_4_20, D5=>mdout1_5_20, 
+            D6=>mdout1_6_20, D7=>mdout1_7_20, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(20));
+
+    mux_14: MUX81
+        port map (D0=>mdout1_0_21, D1=>mdout1_1_21, D2=>mdout1_2_21, 
+            D3=>mdout1_3_21, D4=>mdout1_4_21, D5=>mdout1_5_21, 
+            D6=>mdout1_6_21, D7=>mdout1_7_21, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(21));
+
+    mux_13: MUX81
+        port map (D0=>mdout1_0_22, D1=>mdout1_1_22, D2=>mdout1_2_22, 
+            D3=>mdout1_3_22, D4=>mdout1_4_22, D5=>mdout1_5_22, 
+            D6=>mdout1_6_22, D7=>mdout1_7_22, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(22));
+
+    mux_12: MUX81
+        port map (D0=>mdout1_0_23, D1=>mdout1_1_23, D2=>mdout1_2_23, 
+            D3=>mdout1_3_23, D4=>mdout1_4_23, D5=>mdout1_5_23, 
+            D6=>mdout1_6_23, D7=>mdout1_7_23, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(23));
+
+    mux_11: MUX81
+        port map (D0=>mdout1_0_24, D1=>mdout1_1_24, D2=>mdout1_2_24, 
+            D3=>mdout1_3_24, D4=>mdout1_4_24, D5=>mdout1_5_24, 
+            D6=>mdout1_6_24, D7=>mdout1_7_24, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(24));
+
+    mux_10: MUX81
+        port map (D0=>mdout1_0_25, D1=>mdout1_1_25, D2=>mdout1_2_25, 
+            D3=>mdout1_3_25, D4=>mdout1_4_25, D5=>mdout1_5_25, 
+            D6=>mdout1_6_25, D7=>mdout1_7_25, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(25));
+
+    mux_9: MUX81
+        port map (D0=>mdout1_0_26, D1=>mdout1_1_26, D2=>mdout1_2_26, 
+            D3=>mdout1_3_26, D4=>mdout1_4_26, D5=>mdout1_5_26, 
+            D6=>mdout1_6_26, D7=>mdout1_7_26, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(26));
+
+    mux_8: MUX81
+        port map (D0=>mdout1_0_27, D1=>mdout1_1_27, D2=>mdout1_2_27, 
+            D3=>mdout1_3_27, D4=>mdout1_4_27, D5=>mdout1_5_27, 
+            D6=>mdout1_6_27, D7=>mdout1_7_27, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(27));
+
+    mux_7: MUX81
+        port map (D0=>mdout1_0_28, D1=>mdout1_1_28, D2=>mdout1_2_28, 
+            D3=>mdout1_3_28, D4=>mdout1_4_28, D5=>mdout1_5_28, 
+            D6=>mdout1_6_28, D7=>mdout1_7_28, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(28));
+
+    mux_6: MUX81
+        port map (D0=>mdout1_0_29, D1=>mdout1_1_29, D2=>mdout1_2_29, 
+            D3=>mdout1_3_29, D4=>mdout1_4_29, D5=>mdout1_5_29, 
+            D6=>mdout1_6_29, D7=>mdout1_7_29, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(29));
+
+    mux_5: MUX81
+        port map (D0=>mdout1_0_30, D1=>mdout1_1_30, D2=>mdout1_2_30, 
+            D3=>mdout1_3_30, D4=>mdout1_4_30, D5=>mdout1_5_30, 
+            D6=>mdout1_6_30, D7=>mdout1_7_30, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(30));
+
+    mux_4: MUX81
+        port map (D0=>mdout1_0_31, D1=>mdout1_1_31, D2=>mdout1_2_31, 
+            D3=>mdout1_3_31, D4=>mdout1_4_31, D5=>mdout1_5_31, 
+            D6=>mdout1_6_31, D7=>mdout1_7_31, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(31));
+
+    mux_3: MUX81
+        port map (D0=>mdout1_0_32, D1=>mdout1_1_32, D2=>mdout1_2_32, 
+            D3=>mdout1_3_32, D4=>mdout1_4_32, D5=>mdout1_5_32, 
+            D6=>mdout1_6_32, D7=>mdout1_7_32, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(32));
+
+    mux_2: MUX81
+        port map (D0=>mdout1_0_33, D1=>mdout1_1_33, D2=>mdout1_2_33, 
+            D3=>mdout1_3_33, D4=>mdout1_4_33, D5=>mdout1_5_33, 
+            D6=>mdout1_6_33, D7=>mdout1_7_33, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(33));
+
+    mux_1: MUX81
+        port map (D0=>mdout1_0_34, D1=>mdout1_1_34, D2=>mdout1_2_34, 
+            D3=>mdout1_3_34, D4=>mdout1_4_34, D5=>mdout1_5_34, 
+            D6=>mdout1_6_34, D7=>mdout1_7_34, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(34));
+
+    mux_0: MUX81
+        port map (D0=>mdout1_0_35, D1=>mdout1_1_35, D2=>mdout1_2_35, 
+            D3=>mdout1_3_35, D4=>mdout1_4_35, D5=>mdout1_5_35, 
+            D6=>mdout1_6_35, D7=>mdout1_7_35, SD1=>rptr_11_ff, 
+            SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(35));
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    rfill_0: FSUB2B
+        port map (A0=>scuba_vhi, A1=>wcount_r0, B0=>scuba_vlo, 
+            B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_2, S0=>open, 
+            S1=>rfill_sub_0);
+
+    rfill_1: FSUB2B
+        port map (A0=>wcount_r1, A1=>wcount_r2, B0=>rptr_1, B1=>rptr_2, 
+            BI=>co0_2, BOUT=>co1_2, S0=>rfill_sub_1, S1=>rfill_sub_2);
+
+    rfill_2: FSUB2B
+        port map (A0=>wcount_r3, A1=>wcount_r4, B0=>rptr_3, B1=>rptr_4, 
+            BI=>co1_2, BOUT=>co2_2, S0=>rfill_sub_3, S1=>rfill_sub_4);
+
+    rfill_3: FSUB2B
+        port map (A0=>wcount_r5, A1=>wcount_r6, B0=>rptr_5, B1=>rptr_6, 
+            BI=>co2_2, BOUT=>co3_2, S0=>rfill_sub_5, S1=>rfill_sub_6);
+
+    rfill_4: FSUB2B
+        port map (A0=>wcount_r7, A1=>wcount_r8, B0=>rptr_7, B1=>rptr_8, 
+            BI=>co3_2, BOUT=>co4_2, S0=>rfill_sub_7, S1=>rfill_sub_8);
+
+    rfill_5: FSUB2B
+        port map (A0=>wcount_r9, A1=>wcount_r10, B0=>rptr_9, B1=>rptr_10, 
+            BI=>co4_2, BOUT=>co5_2, S0=>rfill_sub_9, S1=>rfill_sub_10);
+
+    rfill_6: FSUB2B
+        port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r12, B0=>rptr_11, 
+            B1=>rptr_12, BI=>co5_2, BOUT=>co6_2, S0=>rfill_sub_11, 
+            S1=>rfill_sub_12);
+
+    rfill_7: FSUB2B
+        port map (A0=>wcount_r13, A1=>rfill_sub_msb, B0=>rptr_13, 
+            B1=>scuba_vlo, BI=>co6_2, BOUT=>co7_2, S0=>rfill_sub_13, 
+            S1=>rfill_sub_14);
+
+    rfilld: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>co7_2, COUT=>open, S0=>co7_2d, S1=>open);
+
+    empty_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+    empty_cmp_0: AGEB2
+        port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, 
+            B1=>wcount_r1, CI=>cmp_ci, GE=>co0_3);
+
+    empty_cmp_1: AGEB2
+        port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, 
+            B1=>wcount_r3, CI=>co0_3, GE=>co1_3);
+
+    empty_cmp_2: AGEB2
+        port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, 
+            B1=>wcount_r5, CI=>co1_3, GE=>co2_3);
+
+    empty_cmp_3: AGEB2
+        port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, 
+            B1=>wcount_r7, CI=>co2_3, GE=>co3_3);
+
+    empty_cmp_4: AGEB2
+        port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, 
+            B1=>wcount_r9, CI=>co3_3, GE=>co4_3);
+
+    empty_cmp_5: AGEB2
+        port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, 
+            B1=>w_g2b_xor_cluster_0, CI=>co4_3, GE=>co5_3);
+
+    empty_cmp_6: AGEB2
+        port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12, 
+            B1=>wcount_r13, CI=>co5_3, GE=>co6_3);
+
+    empty_cmp_7: AGEB2
+        port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, 
+            B1=>scuba_vlo, CI=>co6_3, GE=>empty_d_c);
+
+    a0: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, 
+            S1=>open);
+
+    full_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+    full_cmp_0: AGEB2
+        port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, 
+            B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_4);
+
+    full_cmp_1: AGEB2
+        port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, 
+            B1=>rcount_w3, CI=>co0_4, GE=>co1_4);
+
+    full_cmp_2: AGEB2
+        port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, 
+            B1=>rcount_w5, CI=>co1_4, GE=>co2_4);
+
+    full_cmp_3: AGEB2
+        port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, 
+            B1=>rcount_w7, CI=>co2_4, GE=>co3_4);
+
+    full_cmp_4: AGEB2
+        port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, 
+            B1=>rcount_w9, CI=>co3_4, GE=>co4_4);
+
+    full_cmp_5: AGEB2
+        port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, 
+            B1=>r_g2b_xor_cluster_0, CI=>co4_4, GE=>co5_4);
+
+    full_cmp_6: AGEB2
+        port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12, 
+            B1=>rcount_w13, CI=>co5_4, GE=>co6_4);
+
+    full_cmp_7: AGEB2
+        port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, 
+            B1=>scuba_vlo, CI=>co6_4, GE=>full_d_c);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    a1: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, 
+            S1=>open);
+
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of async_fifo_nn_16384x36_ecp3 is
+    for Structure
+        for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+        for all:AND2 use entity ecp3.AND2(V); end for;
+        for all:CU2 use entity ecp3.CU2(V); end for;
+        for all:FADD2B use entity ecp3.FADD2B(V); end for;
+        for all:FSUB2B use entity ecp3.FSUB2B(V); end for;
+        for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
+        for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+        for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+        for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+        for all:INV use entity ecp3.INV(V); end for;
+        for all:MUX81 use entity ecp3.MUX81(V); end for;
+        for all:OR2 use entity ecp3.OR2(V); end for;
+        for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+        for all:VHI use entity ecp3.VHI(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+        for all:XOR2 use entity ecp3.XOR2(V); end for;
+        for all:DP16KC use entity ecp3.DP16KC(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_nn_16384x36_ecp3_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_16384x36_ecp3_tmpl.vhd
new file mode 100644
index 0000000..0f97373
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_16384x36_ecp3_tmpl.vhd
@@ -0,0 +1,19 @@
+-- VHDL module instantiation generated by SCUBA Diamond_2.1_Production (100)
+-- Module  Version: 5.4
+-- Fri Jul 12 15:53:18 2013
+
+-- parameterized module component declaration
+component async_fifo_nn_16384x36_ecp3
+    port (Data: in  std_logic_vector(35 downto 0); 
+        WrClock: in  std_logic; RdClock: in  std_logic; 
+        WrEn: in  std_logic; RdEn: in  std_logic; Reset: in  std_logic; 
+        RPReset: in  std_logic; Q: out  std_logic_vector(35 downto 0); 
+        RCNT: out  std_logic_vector(14 downto 0); Empty: out  std_logic; 
+        Full: out  std_logic);
+end component;
+
+-- parameterized module component instance
+__ : async_fifo_nn_16384x36_ecp3
+    port map (Data(35 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, 
+        RdEn=>__, Reset=>__, RPReset=>__, Q(35 downto 0)=>__, RCNT(14 downto 0)=>__, 
+        Empty=>__, Full=>__);
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x103_ecp3.ipx b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x103_ecp3.ipx
new file mode 100644
index 0000000..2d7dc11
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x103_ecp3.ipx
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="async_fifo_nn_4096x103_ecp3" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 09 18 09:50:13.983" version="5.7" type="Module" synthesis="" source_format="VHDL">
+  <Package>
+		<File name="async_fifo_nn_4096x103_ecp3.lpc" type="lpc" modified="2014 09 18 09:50:09.953"/>
+		<File name="async_fifo_nn_4096x103_ecp3.vhd" type="top_level_vhdl" modified="2014 09 18 09:50:10.083"/>
+		<File name="async_fifo_nn_4096x103_ecp3_tmpl.vhd" type="template_vhdl" modified="2014 09 18 09:50:10.084"/>
+		<File name="tb_async_fifo_nn_4096x103_ecp3_tmpl.vhd" type="testbench_vhdl" modified="2014 09 18 09:50:10.101"/>
+  </Package>
+</DiamondModule>
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x103_ecp3.lpc b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x103_ecp3.lpc
new file mode 100644
index 0000000..dcdeb59
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x103_ecp3.lpc
@@ -0,0 +1,50 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.7
+ModuleName=async_fifo_nn_4096x103_ecp3
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=09/18/2014
+Time=09:50:09
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=4096
+Width=103
+RDepth=4096
+RWidth=103
+regout=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=0
+WDataCount=1
+EnECC=0
+
+[Command]
+cmd_line= -w -n async_fifo_nn_4096x103_ecp3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 12 -data_width 103 -num_words 4096 -rdata_width 103 -no_enable -pe -1 -pf -1 -fill
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x103_ecp3.vhd b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x103_ecp3.vhd
new file mode 100644
index 0000000..941b717
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x103_ecp3.vhd
@@ -0,0 +1,3239 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.7
+--C:\Lattice\diamond\3.2_x64\ispfpga\bin\nt64\scuba.exe -w -n async_fifo_nn_4096x103_ecp3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4096 -width 103 -depth 4096 -rdata_width 103 -no_enable -pe -1 -pf -1 -fill 
+
+-- Thu Sep 18 09:50:10 2014
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity async_fifo_nn_4096x103_ecp3 is
+    port (
+        Data: in  std_logic_vector(102 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(102 downto 0); 
+        WCNT: out  std_logic_vector(12 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic);
+end async_fifo_nn_4096x103_ecp3;
+
+architecture Structure of async_fifo_nn_4096x103_ecp3 is
+
+    -- internal signal declarations
+    signal invout_1: std_logic;
+    signal invout_0: std_logic;
+    signal w_g2b_xor_cluster_2_1: std_logic;
+    signal w_g2b_xor_cluster_2: std_logic;
+    signal w_g2b_xor_cluster_1: std_logic;
+    signal r_g2b_xor_cluster_2_1: std_logic;
+    signal r_g2b_xor_cluster_2: std_logic;
+    signal r_g2b_xor_cluster_1: std_logic;
+    signal w_gdata_0: std_logic;
+    signal w_gdata_1: std_logic;
+    signal w_gdata_2: std_logic;
+    signal w_gdata_3: std_logic;
+    signal w_gdata_4: std_logic;
+    signal w_gdata_5: std_logic;
+    signal w_gdata_6: std_logic;
+    signal w_gdata_7: std_logic;
+    signal w_gdata_8: std_logic;
+    signal w_gdata_9: std_logic;
+    signal w_gdata_10: std_logic;
+    signal w_gdata_11: std_logic;
+    signal wptr_12: std_logic;
+    signal r_gdata_0: std_logic;
+    signal r_gdata_1: std_logic;
+    signal r_gdata_2: std_logic;
+    signal r_gdata_3: std_logic;
+    signal r_gdata_4: std_logic;
+    signal r_gdata_5: std_logic;
+    signal r_gdata_6: std_logic;
+    signal r_gdata_7: std_logic;
+    signal r_gdata_8: std_logic;
+    signal r_gdata_9: std_logic;
+    signal r_gdata_10: std_logic;
+    signal r_gdata_11: std_logic;
+    signal rptr_0: std_logic;
+    signal rptr_1: std_logic;
+    signal rptr_2: std_logic;
+    signal rptr_3: std_logic;
+    signal rptr_4: std_logic;
+    signal rptr_5: std_logic;
+    signal rptr_6: std_logic;
+    signal rptr_7: std_logic;
+    signal rptr_8: std_logic;
+    signal rptr_9: std_logic;
+    signal rptr_10: std_logic;
+    signal rptr_12: std_logic;
+    signal rptr_11: std_logic;
+    signal w_gcount_0: std_logic;
+    signal w_gcount_1: std_logic;
+    signal w_gcount_2: std_logic;
+    signal w_gcount_3: std_logic;
+    signal w_gcount_4: std_logic;
+    signal w_gcount_5: std_logic;
+    signal w_gcount_6: std_logic;
+    signal w_gcount_7: std_logic;
+    signal w_gcount_8: std_logic;
+    signal w_gcount_9: std_logic;
+    signal w_gcount_10: std_logic;
+    signal w_gcount_11: std_logic;
+    signal w_gcount_12: std_logic;
+    signal r_gcount_0: std_logic;
+    signal r_gcount_1: std_logic;
+    signal r_gcount_2: std_logic;
+    signal r_gcount_3: std_logic;
+    signal r_gcount_4: std_logic;
+    signal r_gcount_5: std_logic;
+    signal r_gcount_6: std_logic;
+    signal r_gcount_7: std_logic;
+    signal r_gcount_8: std_logic;
+    signal r_gcount_9: std_logic;
+    signal r_gcount_10: std_logic;
+    signal r_gcount_11: std_logic;
+    signal r_gcount_12: std_logic;
+    signal w_gcount_r20: std_logic;
+    signal w_gcount_r0: std_logic;
+    signal w_gcount_r21: std_logic;
+    signal w_gcount_r1: std_logic;
+    signal w_gcount_r22: std_logic;
+    signal w_gcount_r2: std_logic;
+    signal w_gcount_r23: std_logic;
+    signal w_gcount_r3: std_logic;
+    signal w_gcount_r24: std_logic;
+    signal w_gcount_r4: std_logic;
+    signal w_gcount_r25: std_logic;
+    signal w_gcount_r5: std_logic;
+    signal w_gcount_r26: std_logic;
+    signal w_gcount_r6: std_logic;
+    signal w_gcount_r27: std_logic;
+    signal w_gcount_r7: std_logic;
+    signal w_gcount_r28: std_logic;
+    signal w_gcount_r8: std_logic;
+    signal w_gcount_r29: std_logic;
+    signal w_gcount_r9: std_logic;
+    signal w_gcount_r210: std_logic;
+    signal w_gcount_r10: std_logic;
+    signal w_gcount_r211: std_logic;
+    signal w_gcount_r11: std_logic;
+    signal w_gcount_r212: std_logic;
+    signal w_gcount_r12: std_logic;
+    signal r_gcount_w20: std_logic;
+    signal r_gcount_w0: std_logic;
+    signal r_gcount_w21: std_logic;
+    signal r_gcount_w1: std_logic;
+    signal r_gcount_w22: std_logic;
+    signal r_gcount_w2: std_logic;
+    signal r_gcount_w23: std_logic;
+    signal r_gcount_w3: std_logic;
+    signal r_gcount_w24: std_logic;
+    signal r_gcount_w4: std_logic;
+    signal r_gcount_w25: std_logic;
+    signal r_gcount_w5: std_logic;
+    signal r_gcount_w26: std_logic;
+    signal r_gcount_w6: std_logic;
+    signal r_gcount_w27: std_logic;
+    signal r_gcount_w7: std_logic;
+    signal r_gcount_w28: std_logic;
+    signal r_gcount_w8: std_logic;
+    signal r_gcount_w29: std_logic;
+    signal r_gcount_w9: std_logic;
+    signal r_gcount_w210: std_logic;
+    signal r_gcount_w10: std_logic;
+    signal r_gcount_w211: std_logic;
+    signal r_gcount_w11: std_logic;
+    signal r_gcount_w212: std_logic;
+    signal r_gcount_w12: std_logic;
+    signal empty_i: std_logic;
+    signal rRst: std_logic;
+    signal full_i: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_gctr_ci: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co0: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal co1: std_logic;
+    signal iwcount_6: std_logic;
+    signal iwcount_7: std_logic;
+    signal co2: std_logic;
+    signal iwcount_8: std_logic;
+    signal iwcount_9: std_logic;
+    signal co3: std_logic;
+    signal iwcount_10: std_logic;
+    signal iwcount_11: std_logic;
+    signal co4: std_logic;
+    signal iwcount_12: std_logic;
+    signal co6: std_logic;
+    signal co5: std_logic;
+    signal wcount_12: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_gctr_ci: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co0_1: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal co1_1: std_logic;
+    signal ircount_6: std_logic;
+    signal ircount_7: std_logic;
+    signal co2_1: std_logic;
+    signal ircount_8: std_logic;
+    signal ircount_9: std_logic;
+    signal co3_1: std_logic;
+    signal ircount_10: std_logic;
+    signal ircount_11: std_logic;
+    signal co4_1: std_logic;
+    signal ircount_12: std_logic;
+    signal co6_1: std_logic;
+    signal co5_1: std_logic;
+    signal rcount_12: std_logic;
+    signal mdout1_1_0: std_logic;
+    signal mdout1_0_0: std_logic;
+    signal mdout1_1_1: std_logic;
+    signal mdout1_0_1: std_logic;
+    signal mdout1_1_2: std_logic;
+    signal mdout1_0_2: std_logic;
+    signal mdout1_1_3: std_logic;
+    signal mdout1_0_3: std_logic;
+    signal mdout1_1_4: std_logic;
+    signal mdout1_0_4: std_logic;
+    signal mdout1_1_5: std_logic;
+    signal mdout1_0_5: std_logic;
+    signal mdout1_1_6: std_logic;
+    signal mdout1_0_6: std_logic;
+    signal mdout1_1_7: std_logic;
+    signal mdout1_0_7: std_logic;
+    signal mdout1_1_8: std_logic;
+    signal mdout1_0_8: std_logic;
+    signal mdout1_1_9: std_logic;
+    signal mdout1_0_9: std_logic;
+    signal mdout1_1_10: std_logic;
+    signal mdout1_0_10: std_logic;
+    signal mdout1_1_11: std_logic;
+    signal mdout1_0_11: std_logic;
+    signal mdout1_1_12: std_logic;
+    signal mdout1_0_12: std_logic;
+    signal mdout1_1_13: std_logic;
+    signal mdout1_0_13: std_logic;
+    signal mdout1_1_14: std_logic;
+    signal mdout1_0_14: std_logic;
+    signal mdout1_1_15: std_logic;
+    signal mdout1_0_15: std_logic;
+    signal mdout1_1_16: std_logic;
+    signal mdout1_0_16: std_logic;
+    signal mdout1_1_17: std_logic;
+    signal mdout1_0_17: std_logic;
+    signal mdout1_1_18: std_logic;
+    signal mdout1_0_18: std_logic;
+    signal mdout1_1_19: std_logic;
+    signal mdout1_0_19: std_logic;
+    signal mdout1_1_20: std_logic;
+    signal mdout1_0_20: std_logic;
+    signal mdout1_1_21: std_logic;
+    signal mdout1_0_21: std_logic;
+    signal mdout1_1_22: std_logic;
+    signal mdout1_0_22: std_logic;
+    signal mdout1_1_23: std_logic;
+    signal mdout1_0_23: std_logic;
+    signal mdout1_1_24: std_logic;
+    signal mdout1_0_24: std_logic;
+    signal mdout1_1_25: std_logic;
+    signal mdout1_0_25: std_logic;
+    signal mdout1_1_26: std_logic;
+    signal mdout1_0_26: std_logic;
+    signal mdout1_1_27: std_logic;
+    signal mdout1_0_27: std_logic;
+    signal mdout1_1_28: std_logic;
+    signal mdout1_0_28: std_logic;
+    signal mdout1_1_29: std_logic;
+    signal mdout1_0_29: std_logic;
+    signal mdout1_1_30: std_logic;
+    signal mdout1_0_30: std_logic;
+    signal mdout1_1_31: std_logic;
+    signal mdout1_0_31: std_logic;
+    signal mdout1_1_32: std_logic;
+    signal mdout1_0_32: std_logic;
+    signal mdout1_1_33: std_logic;
+    signal mdout1_0_33: std_logic;
+    signal mdout1_1_34: std_logic;
+    signal mdout1_0_34: std_logic;
+    signal mdout1_1_35: std_logic;
+    signal mdout1_0_35: std_logic;
+    signal mdout1_1_36: std_logic;
+    signal mdout1_0_36: std_logic;
+    signal mdout1_1_37: std_logic;
+    signal mdout1_0_37: std_logic;
+    signal mdout1_1_38: std_logic;
+    signal mdout1_0_38: std_logic;
+    signal mdout1_1_39: std_logic;
+    signal mdout1_0_39: std_logic;
+    signal mdout1_1_40: std_logic;
+    signal mdout1_0_40: std_logic;
+    signal mdout1_1_41: std_logic;
+    signal mdout1_0_41: std_logic;
+    signal mdout1_1_42: std_logic;
+    signal mdout1_0_42: std_logic;
+    signal mdout1_1_43: std_logic;
+    signal mdout1_0_43: std_logic;
+    signal mdout1_1_44: std_logic;
+    signal mdout1_0_44: std_logic;
+    signal mdout1_1_45: std_logic;
+    signal mdout1_0_45: std_logic;
+    signal mdout1_1_46: std_logic;
+    signal mdout1_0_46: std_logic;
+    signal mdout1_1_47: std_logic;
+    signal mdout1_0_47: std_logic;
+    signal mdout1_1_48: std_logic;
+    signal mdout1_0_48: std_logic;
+    signal mdout1_1_49: std_logic;
+    signal mdout1_0_49: std_logic;
+    signal mdout1_1_50: std_logic;
+    signal mdout1_0_50: std_logic;
+    signal mdout1_1_51: std_logic;
+    signal mdout1_0_51: std_logic;
+    signal mdout1_1_52: std_logic;
+    signal mdout1_0_52: std_logic;
+    signal mdout1_1_53: std_logic;
+    signal mdout1_0_53: std_logic;
+    signal mdout1_1_54: std_logic;
+    signal mdout1_0_54: std_logic;
+    signal mdout1_1_55: std_logic;
+    signal mdout1_0_55: std_logic;
+    signal mdout1_1_56: std_logic;
+    signal mdout1_0_56: std_logic;
+    signal mdout1_1_57: std_logic;
+    signal mdout1_0_57: std_logic;
+    signal mdout1_1_58: std_logic;
+    signal mdout1_0_58: std_logic;
+    signal mdout1_1_59: std_logic;
+    signal mdout1_0_59: std_logic;
+    signal mdout1_1_60: std_logic;
+    signal mdout1_0_60: std_logic;
+    signal mdout1_1_61: std_logic;
+    signal mdout1_0_61: std_logic;
+    signal mdout1_1_62: std_logic;
+    signal mdout1_0_62: std_logic;
+    signal mdout1_1_63: std_logic;
+    signal mdout1_0_63: std_logic;
+    signal mdout1_1_64: std_logic;
+    signal mdout1_0_64: std_logic;
+    signal mdout1_1_65: std_logic;
+    signal mdout1_0_65: std_logic;
+    signal mdout1_1_66: std_logic;
+    signal mdout1_0_66: std_logic;
+    signal mdout1_1_67: std_logic;
+    signal mdout1_0_67: std_logic;
+    signal mdout1_1_68: std_logic;
+    signal mdout1_0_68: std_logic;
+    signal mdout1_1_69: std_logic;
+    signal mdout1_0_69: std_logic;
+    signal mdout1_1_70: std_logic;
+    signal mdout1_0_70: std_logic;
+    signal mdout1_1_71: std_logic;
+    signal mdout1_0_71: std_logic;
+    signal mdout1_1_72: std_logic;
+    signal mdout1_0_72: std_logic;
+    signal mdout1_1_73: std_logic;
+    signal mdout1_0_73: std_logic;
+    signal mdout1_1_74: std_logic;
+    signal mdout1_0_74: std_logic;
+    signal mdout1_1_75: std_logic;
+    signal mdout1_0_75: std_logic;
+    signal mdout1_1_76: std_logic;
+    signal mdout1_0_76: std_logic;
+    signal mdout1_1_77: std_logic;
+    signal mdout1_0_77: std_logic;
+    signal mdout1_1_78: std_logic;
+    signal mdout1_0_78: std_logic;
+    signal mdout1_1_79: std_logic;
+    signal mdout1_0_79: std_logic;
+    signal mdout1_1_80: std_logic;
+    signal mdout1_0_80: std_logic;
+    signal mdout1_1_81: std_logic;
+    signal mdout1_0_81: std_logic;
+    signal mdout1_1_82: std_logic;
+    signal mdout1_0_82: std_logic;
+    signal mdout1_1_83: std_logic;
+    signal mdout1_0_83: std_logic;
+    signal mdout1_1_84: std_logic;
+    signal mdout1_0_84: std_logic;
+    signal mdout1_1_85: std_logic;
+    signal mdout1_0_85: std_logic;
+    signal mdout1_1_86: std_logic;
+    signal mdout1_0_86: std_logic;
+    signal mdout1_1_87: std_logic;
+    signal mdout1_0_87: std_logic;
+    signal mdout1_1_88: std_logic;
+    signal mdout1_0_88: std_logic;
+    signal mdout1_1_89: std_logic;
+    signal mdout1_0_89: std_logic;
+    signal mdout1_1_90: std_logic;
+    signal mdout1_0_90: std_logic;
+    signal mdout1_1_91: std_logic;
+    signal mdout1_0_91: std_logic;
+    signal mdout1_1_92: std_logic;
+    signal mdout1_0_92: std_logic;
+    signal mdout1_1_93: std_logic;
+    signal mdout1_0_93: std_logic;
+    signal mdout1_1_94: std_logic;
+    signal mdout1_0_94: std_logic;
+    signal mdout1_1_95: std_logic;
+    signal mdout1_0_95: std_logic;
+    signal mdout1_1_96: std_logic;
+    signal mdout1_0_96: std_logic;
+    signal mdout1_1_97: std_logic;
+    signal mdout1_0_97: std_logic;
+    signal mdout1_1_98: std_logic;
+    signal mdout1_0_98: std_logic;
+    signal mdout1_1_99: std_logic;
+    signal mdout1_0_99: std_logic;
+    signal mdout1_1_100: std_logic;
+    signal mdout1_0_100: std_logic;
+    signal mdout1_1_101: std_logic;
+    signal mdout1_0_101: std_logic;
+    signal rptr_11_ff: std_logic;
+    signal mdout1_1_102: std_logic;
+    signal mdout1_0_102: std_logic;
+    signal wfill_sub_0: std_logic;
+    signal precin: std_logic;
+    signal scuba_vhi: std_logic;
+    signal wptr_0: std_logic;
+    signal wfill_sub_1: std_logic;
+    signal wfill_sub_2: std_logic;
+    signal co0_2: std_logic;
+    signal wptr_1: std_logic;
+    signal wptr_2: std_logic;
+    signal wfill_sub_3: std_logic;
+    signal wfill_sub_4: std_logic;
+    signal co1_2: std_logic;
+    signal wptr_3: std_logic;
+    signal wptr_4: std_logic;
+    signal wfill_sub_5: std_logic;
+    signal wfill_sub_6: std_logic;
+    signal co2_2: std_logic;
+    signal wptr_5: std_logic;
+    signal wptr_6: std_logic;
+    signal wfill_sub_7: std_logic;
+    signal wfill_sub_8: std_logic;
+    signal co3_2: std_logic;
+    signal wptr_7: std_logic;
+    signal wptr_8: std_logic;
+    signal wfill_sub_9: std_logic;
+    signal wfill_sub_10: std_logic;
+    signal co4_2: std_logic;
+    signal wptr_9: std_logic;
+    signal wptr_10: std_logic;
+    signal wfill_sub_11: std_logic;
+    signal wfill_sub_12: std_logic;
+    signal co5_2: std_logic;
+    signal wptr_11: std_logic;
+    signal wfill_sub_msb: std_logic;
+    signal co6_2d: std_logic;
+    signal co6_2: std_logic;
+    signal rden_i: std_logic;
+    signal cmp_ci: std_logic;
+    signal wcount_r0: std_logic;
+    signal wcount_r1: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal co0_3: std_logic;
+    signal wcount_r2: std_logic;
+    signal wcount_r3: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal co1_3: std_logic;
+    signal wcount_r4: std_logic;
+    signal wcount_r5: std_logic;
+    signal rcount_4: std_logic;
+    signal rcount_5: std_logic;
+    signal co2_3: std_logic;
+    signal wcount_r6: std_logic;
+    signal wcount_r7: std_logic;
+    signal rcount_6: std_logic;
+    signal rcount_7: std_logic;
+    signal co3_3: std_logic;
+    signal wcount_r8: std_logic;
+    signal w_g2b_xor_cluster_0: std_logic;
+    signal rcount_8: std_logic;
+    signal rcount_9: std_logic;
+    signal co4_3: std_logic;
+    signal wcount_r10: std_logic;
+    signal wcount_r11: std_logic;
+    signal rcount_10: std_logic;
+    signal rcount_11: std_logic;
+    signal co5_3: std_logic;
+    signal empty_cmp_clr: std_logic;
+    signal empty_cmp_set: std_logic;
+    signal empty_d: std_logic;
+    signal empty_d_c: std_logic;
+    signal wren_i: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal rcount_w0: std_logic;
+    signal rcount_w1: std_logic;
+    signal wcount_0: std_logic;
+    signal wcount_1: std_logic;
+    signal co0_4: std_logic;
+    signal rcount_w2: std_logic;
+    signal rcount_w3: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_3: std_logic;
+    signal co1_4: std_logic;
+    signal rcount_w4: std_logic;
+    signal rcount_w5: std_logic;
+    signal wcount_4: std_logic;
+    signal wcount_5: std_logic;
+    signal co2_4: std_logic;
+    signal rcount_w6: std_logic;
+    signal rcount_w7: std_logic;
+    signal wcount_6: std_logic;
+    signal wcount_7: std_logic;
+    signal co3_4: std_logic;
+    signal rcount_w8: std_logic;
+    signal r_g2b_xor_cluster_0: std_logic;
+    signal wcount_8: std_logic;
+    signal wcount_9: std_logic;
+    signal co4_4: std_logic;
+    signal rcount_w10: std_logic;
+    signal rcount_w11: std_logic;
+    signal wcount_10: std_logic;
+    signal wcount_11: std_logic;
+    signal co5_4: std_logic;
+    signal full_cmp_clr: std_logic;
+    signal full_cmp_set: std_logic;
+    signal full_d: std_logic;
+    signal full_d_c: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component AGEB2
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; GE: out  std_logic);
+    end component;
+    component AND2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component CU2
+        port (CI: in  std_logic; PC0: in  std_logic; PC1: in  std_logic; 
+            CO: out  std_logic; NC0: out  std_logic; NC1: out  std_logic);
+    end component;
+    component FADD2B
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; COUT: out  std_logic; 
+            S0: out  std_logic; S1: out  std_logic);
+    end component;
+    component FSUB2B
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; BI: in  std_logic; BOUT: out  std_logic; 
+            S0: out  std_logic; S1: out  std_logic);
+    end component;
+    component FD1P3BX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            PD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1P3DX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            CD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1S3BX
+        port (D: in  std_logic; CK: in  std_logic; PD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component FD1S3DX
+        port (D: in  std_logic; CK: in  std_logic; CD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component INV
+        port (A: in  std_logic; Z: out  std_logic);
+    end component;
+    component MUX21
+        port (D0: in  std_logic; D1: in  std_logic; SD: in  std_logic; 
+            Z: out  std_logic);
+    end component;
+    component OR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component ROM16X1A
+        generic (INITVAL : in std_logic_vector(15 downto 0));
+        port (AD3: in  std_logic; AD2: in  std_logic; AD1: in  std_logic; 
+            AD0: in  std_logic; DO0: out  std_logic);
+    end component;
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component XOR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component DP16KC
+        generic (GSR : in String; WRITEMODE_B : in String; 
+                WRITEMODE_A : in String; CSDECODE_B : in String; 
+                CSDECODE_A : in String; REGMODE_B : in String; 
+                REGMODE_A : in String; DATA_WIDTH_B : in Integer; 
+                DATA_WIDTH_A : in Integer);
+        port (DIA0: in  std_logic; DIA1: in  std_logic; 
+            DIA2: in  std_logic; DIA3: in  std_logic; 
+            DIA4: in  std_logic; DIA5: in  std_logic; 
+            DIA6: in  std_logic; DIA7: in  std_logic; 
+            DIA8: in  std_logic; DIA9: in  std_logic; 
+            DIA10: in  std_logic; DIA11: in  std_logic; 
+            DIA12: in  std_logic; DIA13: in  std_logic; 
+            DIA14: in  std_logic; DIA15: in  std_logic; 
+            DIA16: in  std_logic; DIA17: in  std_logic; 
+            ADA0: in  std_logic; ADA1: in  std_logic; 
+            ADA2: in  std_logic; ADA3: in  std_logic; 
+            ADA4: in  std_logic; ADA5: in  std_logic; 
+            ADA6: in  std_logic; ADA7: in  std_logic; 
+            ADA8: in  std_logic; ADA9: in  std_logic; 
+            ADA10: in  std_logic; ADA11: in  std_logic; 
+            ADA12: in  std_logic; ADA13: in  std_logic; 
+            CEA: in  std_logic; CLKA: in  std_logic; OCEA: in  std_logic; 
+            WEA: in  std_logic; CSA0: in  std_logic; CSA1: in  std_logic; 
+            CSA2: in  std_logic; RSTA: in  std_logic; 
+            DIB0: in  std_logic; DIB1: in  std_logic; 
+            DIB2: in  std_logic; DIB3: in  std_logic; 
+            DIB4: in  std_logic; DIB5: in  std_logic; 
+            DIB6: in  std_logic; DIB7: in  std_logic; 
+            DIB8: in  std_logic; DIB9: in  std_logic; 
+            DIB10: in  std_logic; DIB11: in  std_logic; 
+            DIB12: in  std_logic; DIB13: in  std_logic; 
+            DIB14: in  std_logic; DIB15: in  std_logic; 
+            DIB16: in  std_logic; DIB17: in  std_logic; 
+            ADB0: in  std_logic; ADB1: in  std_logic; 
+            ADB2: in  std_logic; ADB3: in  std_logic; 
+            ADB4: in  std_logic; ADB5: in  std_logic; 
+            ADB6: in  std_logic; ADB7: in  std_logic; 
+            ADB8: in  std_logic; ADB9: in  std_logic; 
+            ADB10: in  std_logic; ADB11: in  std_logic; 
+            ADB12: in  std_logic; ADB13: in  std_logic; 
+            CEB: in  std_logic; CLKB: in  std_logic; OCEB: in  std_logic; 
+            WEB: in  std_logic; CSB0: in  std_logic; CSB1: in  std_logic; 
+            CSB2: in  std_logic; RSTB: in  std_logic; 
+            DOA0: out  std_logic; DOA1: out  std_logic; 
+            DOA2: out  std_logic; DOA3: out  std_logic; 
+            DOA4: out  std_logic; DOA5: out  std_logic; 
+            DOA6: out  std_logic; DOA7: out  std_logic; 
+            DOA8: out  std_logic; DOA9: out  std_logic; 
+            DOA10: out  std_logic; DOA11: out  std_logic; 
+            DOA12: out  std_logic; DOA13: out  std_logic; 
+            DOA14: out  std_logic; DOA15: out  std_logic; 
+            DOA16: out  std_logic; DOA17: out  std_logic; 
+            DOB0: out  std_logic; DOB1: out  std_logic; 
+            DOB2: out  std_logic; DOB3: out  std_logic; 
+            DOB4: out  std_logic; DOB5: out  std_logic; 
+            DOB6: out  std_logic; DOB7: out  std_logic; 
+            DOB8: out  std_logic; DOB9: out  std_logic; 
+            DOB10: out  std_logic; DOB11: out  std_logic; 
+            DOB12: out  std_logic; DOB13: out  std_logic; 
+            DOB14: out  std_logic; DOB15: out  std_logic; 
+            DOB16: out  std_logic; DOB17: out  std_logic);
+    end component;
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute RESETMODE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_23 : label is "async_fifo_nn_4096x103_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_23 : label is "";
+    attribute RESETMODE of pdp_ram_0_0_23 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_0_1_22 : label is "async_fifo_nn_4096x103_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_1_22 : label is "";
+    attribute RESETMODE of pdp_ram_0_1_22 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_0_2_21 : label is "async_fifo_nn_4096x103_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_2_21 : label is "";
+    attribute RESETMODE of pdp_ram_0_2_21 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_0_3_20 : label is "async_fifo_nn_4096x103_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_3_20 : label is "";
+    attribute RESETMODE of pdp_ram_0_3_20 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_0_4_19 : label is "async_fifo_nn_4096x103_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_4_19 : label is "";
+    attribute RESETMODE of pdp_ram_0_4_19 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_0_5_18 : label is "async_fifo_nn_4096x103_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_5_18 : label is "";
+    attribute RESETMODE of pdp_ram_0_5_18 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_0_6_17 : label is "async_fifo_nn_4096x103_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_6_17 : label is "";
+    attribute RESETMODE of pdp_ram_0_6_17 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_0_7_16 : label is "async_fifo_nn_4096x103_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_7_16 : label is "";
+    attribute RESETMODE of pdp_ram_0_7_16 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_0_8_15 : label is "async_fifo_nn_4096x103_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_8_15 : label is "";
+    attribute RESETMODE of pdp_ram_0_8_15 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_0_9_14 : label is "async_fifo_nn_4096x103_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_9_14 : label is "";
+    attribute RESETMODE of pdp_ram_0_9_14 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_0_10_13 : label is "async_fifo_nn_4096x103_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_10_13 : label is "";
+    attribute RESETMODE of pdp_ram_0_10_13 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_0_11_12 : label is "async_fifo_nn_4096x103_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_11_12 : label is "";
+    attribute RESETMODE of pdp_ram_0_11_12 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_1_0_11 : label is "async_fifo_nn_4096x103_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_0_11 : label is "";
+    attribute RESETMODE of pdp_ram_1_0_11 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_1_1_10 : label is "async_fifo_nn_4096x103_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_1_10 : label is "";
+    attribute RESETMODE of pdp_ram_1_1_10 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_1_2_9 : label is "async_fifo_nn_4096x103_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_2_9 : label is "";
+    attribute RESETMODE of pdp_ram_1_2_9 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_1_3_8 : label is "async_fifo_nn_4096x103_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_3_8 : label is "";
+    attribute RESETMODE of pdp_ram_1_3_8 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_1_4_7 : label is "async_fifo_nn_4096x103_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_4_7 : label is "";
+    attribute RESETMODE of pdp_ram_1_4_7 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_1_5_6 : label is "async_fifo_nn_4096x103_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_5_6 : label is "";
+    attribute RESETMODE of pdp_ram_1_5_6 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_1_6_5 : label is "async_fifo_nn_4096x103_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_6_5 : label is "";
+    attribute RESETMODE of pdp_ram_1_6_5 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_1_7_4 : label is "async_fifo_nn_4096x103_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_7_4 : label is "";
+    attribute RESETMODE of pdp_ram_1_7_4 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_1_8_3 : label is "async_fifo_nn_4096x103_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_8_3 : label is "";
+    attribute RESETMODE of pdp_ram_1_8_3 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_1_9_2 : label is "async_fifo_nn_4096x103_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_9_2 : label is "";
+    attribute RESETMODE of pdp_ram_1_9_2 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_1_10_1 : label is "async_fifo_nn_4096x103_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_10_1 : label is "";
+    attribute RESETMODE of pdp_ram_1_10_1 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_1_11_0 : label is "async_fifo_nn_4096x103_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_11_0 : label is "";
+    attribute RESETMODE of pdp_ram_1_11_0 : label is "SYNC";
+    attribute GSR of FF_145 : label is "ENABLED";
+    attribute GSR of FF_144 : label is "ENABLED";
+    attribute GSR of FF_143 : label is "ENABLED";
+    attribute GSR of FF_142 : label is "ENABLED";
+    attribute GSR of FF_141 : label is "ENABLED";
+    attribute GSR of FF_140 : label is "ENABLED";
+    attribute GSR of FF_139 : label is "ENABLED";
+    attribute GSR of FF_138 : label is "ENABLED";
+    attribute GSR of FF_137 : label is "ENABLED";
+    attribute GSR of FF_136 : label is "ENABLED";
+    attribute GSR of FF_135 : label is "ENABLED";
+    attribute GSR of FF_134 : label is "ENABLED";
+    attribute GSR of FF_133 : label is "ENABLED";
+    attribute GSR of FF_132 : label is "ENABLED";
+    attribute GSR of FF_131 : label is "ENABLED";
+    attribute GSR of FF_130 : label is "ENABLED";
+    attribute GSR of FF_129 : label is "ENABLED";
+    attribute GSR of FF_128 : label is "ENABLED";
+    attribute GSR of FF_127 : label is "ENABLED";
+    attribute GSR of FF_126 : label is "ENABLED";
+    attribute GSR of FF_125 : label is "ENABLED";
+    attribute GSR of FF_124 : label is "ENABLED";
+    attribute GSR of FF_123 : label is "ENABLED";
+    attribute GSR of FF_122 : label is "ENABLED";
+    attribute GSR of FF_121 : label is "ENABLED";
+    attribute GSR of FF_120 : label is "ENABLED";
+    attribute GSR of FF_119 : label is "ENABLED";
+    attribute GSR of FF_118 : label is "ENABLED";
+    attribute GSR of FF_117 : label is "ENABLED";
+    attribute GSR of FF_116 : label is "ENABLED";
+    attribute GSR of FF_115 : label is "ENABLED";
+    attribute GSR of FF_114 : label is "ENABLED";
+    attribute GSR of FF_113 : label is "ENABLED";
+    attribute GSR of FF_112 : label is "ENABLED";
+    attribute GSR of FF_111 : label is "ENABLED";
+    attribute GSR of FF_110 : label is "ENABLED";
+    attribute GSR of FF_109 : label is "ENABLED";
+    attribute GSR of FF_108 : label is "ENABLED";
+    attribute GSR of FF_107 : label is "ENABLED";
+    attribute GSR of FF_106 : label is "ENABLED";
+    attribute GSR of FF_105 : label is "ENABLED";
+    attribute GSR of FF_104 : label is "ENABLED";
+    attribute GSR of FF_103 : label is "ENABLED";
+    attribute GSR of FF_102 : label is "ENABLED";
+    attribute GSR of FF_101 : label is "ENABLED";
+    attribute GSR of FF_100 : label is "ENABLED";
+    attribute GSR of FF_99 : label is "ENABLED";
+    attribute GSR of FF_98 : label is "ENABLED";
+    attribute GSR of FF_97 : label is "ENABLED";
+    attribute GSR of FF_96 : label is "ENABLED";
+    attribute GSR of FF_95 : label is "ENABLED";
+    attribute GSR of FF_94 : label is "ENABLED";
+    attribute GSR of FF_93 : label is "ENABLED";
+    attribute GSR of FF_92 : label is "ENABLED";
+    attribute GSR of FF_91 : label is "ENABLED";
+    attribute GSR of FF_90 : label is "ENABLED";
+    attribute GSR of FF_89 : label is "ENABLED";
+    attribute GSR of FF_88 : label is "ENABLED";
+    attribute GSR of FF_87 : label is "ENABLED";
+    attribute GSR of FF_86 : label is "ENABLED";
+    attribute GSR of FF_85 : label is "ENABLED";
+    attribute GSR of FF_84 : label is "ENABLED";
+    attribute GSR of FF_83 : label is "ENABLED";
+    attribute GSR of FF_82 : label is "ENABLED";
+    attribute GSR of FF_81 : label is "ENABLED";
+    attribute GSR of FF_80 : label is "ENABLED";
+    attribute GSR of FF_79 : label is "ENABLED";
+    attribute GSR of FF_78 : label is "ENABLED";
+    attribute GSR of FF_77 : label is "ENABLED";
+    attribute GSR of FF_76 : label is "ENABLED";
+    attribute GSR of FF_75 : label is "ENABLED";
+    attribute GSR of FF_74 : label is "ENABLED";
+    attribute GSR of FF_73 : label is "ENABLED";
+    attribute GSR of FF_72 : label is "ENABLED";
+    attribute GSR of FF_71 : label is "ENABLED";
+    attribute GSR of FF_70 : label is "ENABLED";
+    attribute GSR of FF_69 : label is "ENABLED";
+    attribute GSR of FF_68 : label is "ENABLED";
+    attribute GSR of FF_67 : label is "ENABLED";
+    attribute GSR of FF_66 : label is "ENABLED";
+    attribute GSR of FF_65 : label is "ENABLED";
+    attribute GSR of FF_64 : label is "ENABLED";
+    attribute GSR of FF_63 : label is "ENABLED";
+    attribute GSR of FF_62 : label is "ENABLED";
+    attribute GSR of FF_61 : label is "ENABLED";
+    attribute GSR of FF_60 : label is "ENABLED";
+    attribute GSR of FF_59 : label is "ENABLED";
+    attribute GSR of FF_58 : label is "ENABLED";
+    attribute GSR of FF_57 : label is "ENABLED";
+    attribute GSR of FF_56 : label is "ENABLED";
+    attribute GSR of FF_55 : label is "ENABLED";
+    attribute GSR of FF_54 : label is "ENABLED";
+    attribute GSR of FF_53 : label is "ENABLED";
+    attribute GSR of FF_52 : label is "ENABLED";
+    attribute GSR of FF_51 : label is "ENABLED";
+    attribute GSR of FF_50 : label is "ENABLED";
+    attribute GSR of FF_49 : label is "ENABLED";
+    attribute GSR of FF_48 : label is "ENABLED";
+    attribute GSR of FF_47 : label is "ENABLED";
+    attribute GSR of FF_46 : label is "ENABLED";
+    attribute GSR of FF_45 : label is "ENABLED";
+    attribute GSR of FF_44 : label is "ENABLED";
+    attribute GSR of FF_43 : label is "ENABLED";
+    attribute GSR of FF_42 : label is "ENABLED";
+    attribute GSR of FF_41 : label is "ENABLED";
+    attribute GSR of FF_40 : label is "ENABLED";
+    attribute GSR of FF_39 : label is "ENABLED";
+    attribute GSR of FF_38 : label is "ENABLED";
+    attribute GSR of FF_37 : label is "ENABLED";
+    attribute GSR of FF_36 : label is "ENABLED";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t27: AND2
+        port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+    INV_1: INV
+        port map (A=>full_i, Z=>invout_1);
+
+    AND2_t26: AND2
+        port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+    INV_0: INV
+        port map (A=>empty_i, Z=>invout_0);
+
+    OR2_t25: OR2
+        port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+    XOR2_t24: XOR2
+        port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+    XOR2_t23: XOR2
+        port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+    XOR2_t22: XOR2
+        port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+    XOR2_t21: XOR2
+        port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+    XOR2_t20: XOR2
+        port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+    XOR2_t19: XOR2
+        port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
+
+    XOR2_t18: XOR2
+        port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
+
+    XOR2_t17: XOR2
+        port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
+
+    XOR2_t16: XOR2
+        port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
+
+    XOR2_t15: XOR2
+        port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
+
+    XOR2_t14: XOR2
+        port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
+
+    XOR2_t13: XOR2
+        port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
+
+    XOR2_t12: XOR2
+        port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+    XOR2_t11: XOR2
+        port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+    XOR2_t10: XOR2
+        port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+    XOR2_t9: XOR2
+        port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+    XOR2_t8: XOR2
+        port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+    XOR2_t7: XOR2
+        port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
+
+    XOR2_t6: XOR2
+        port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
+
+    XOR2_t5: XOR2
+        port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
+
+    XOR2_t4: XOR2
+        port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
+
+    XOR2_t3: XOR2
+        port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
+
+    XOR2_t2: XOR2
+        port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
+
+    XOR2_t1: XOR2
+        port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
+
+    LUT4_33: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, 
+            AD1=>w_gcount_r211, AD0=>w_gcount_r212, 
+            DO0=>w_g2b_xor_cluster_0);
+
+    LUT4_32: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, 
+            AD1=>w_gcount_r27, AD0=>w_gcount_r28, 
+            DO0=>w_g2b_xor_cluster_1);
+
+    LUT4_31: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, 
+            AD1=>w_gcount_r23, AD0=>w_gcount_r24, 
+            DO0=>w_g2b_xor_cluster_2);
+
+    LUT4_30: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>wcount_r11);
+
+    LUT4_29: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, 
+            AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10);
+
+    LUT4_28: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, 
+            AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8);
+
+    LUT4_27: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, 
+            AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7);
+
+    LUT4_26: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, 
+            AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6);
+
+    LUT4_25: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5);
+
+    LUT4_24: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4);
+
+    LUT4_23: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3);
+
+    LUT4_22: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, 
+            AD1=>w_gcount_r24, AD0=>scuba_vlo, 
+            DO0=>w_g2b_xor_cluster_2_1);
+
+    LUT4_21: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2);
+
+    LUT4_20: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1);
+
+    LUT4_19: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0);
+
+    LUT4_18: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, 
+            AD1=>r_gcount_w211, AD0=>r_gcount_w212, 
+            DO0=>r_g2b_xor_cluster_0);
+
+    LUT4_17: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, 
+            AD1=>r_gcount_w27, AD0=>r_gcount_w28, 
+            DO0=>r_g2b_xor_cluster_1);
+
+    LUT4_16: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, 
+            AD1=>r_gcount_w23, AD0=>r_gcount_w24, 
+            DO0=>r_g2b_xor_cluster_2);
+
+    LUT4_15: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>rcount_w11);
+
+    LUT4_14: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, 
+            AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10);
+
+    LUT4_13: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, 
+            AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8);
+
+    LUT4_12: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, 
+            AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7);
+
+    LUT4_11: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, 
+            AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6);
+
+    LUT4_10: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5);
+
+    LUT4_9: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4);
+
+    LUT4_8: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3);
+
+    LUT4_7: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, 
+            AD1=>r_gcount_w24, AD0=>scuba_vlo, 
+            DO0=>r_g2b_xor_cluster_2_1);
+
+    LUT4_6: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2);
+
+    LUT4_5: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1);
+
+    LUT4_4: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0);
+
+    XOR2_t0: XOR2
+        port map (A=>wptr_12, B=>r_gcount_w212, Z=>wfill_sub_msb);
+
+    LUT4_3: ROM16X1A
+        generic map (initval=> X"0410")
+        port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+    LUT4_2: ROM16X1A
+        generic map (initval=> X"1004")
+        port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"0140")
+        port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, 
+            AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"4001")
+        port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, 
+            AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+    pdp_ram_0_0_23: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), 
+            DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), 
+            DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, 
+            DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, 
+            ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, 
+            ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, 
+            ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, 
+            WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>scuba_vlo, 
+            CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>scuba_vlo, 
+            CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, 
+            DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, 
+            DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, 
+            DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, 
+            DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, 
+            DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, 
+            DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, 
+            DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_0_1_22: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), 
+            DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), 
+            DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_9, 
+            DOB1=>mdout1_0_10, DOB2=>mdout1_0_11, DOB3=>mdout1_0_12, 
+            DOB4=>mdout1_0_13, DOB5=>mdout1_0_14, DOB6=>mdout1_0_15, 
+            DOB7=>mdout1_0_16, DOB8=>mdout1_0_17, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    pdp_ram_0_2_21: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20), 
+            DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23), 
+            DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_18, 
+            DOB1=>mdout1_0_19, DOB2=>mdout1_0_20, DOB3=>mdout1_0_21, 
+            DOB4=>mdout1_0_22, DOB5=>mdout1_0_23, DOB6=>mdout1_0_24, 
+            DOB7=>mdout1_0_25, DOB8=>mdout1_0_26, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    pdp_ram_0_3_20: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29), 
+            DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32), 
+            DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_27, 
+            DOB1=>mdout1_0_28, DOB2=>mdout1_0_29, DOB3=>mdout1_0_30, 
+            DOB4=>mdout1_0_31, DOB5=>mdout1_0_32, DOB6=>mdout1_0_33, 
+            DOB7=>mdout1_0_34, DOB8=>mdout1_0_35, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    pdp_ram_0_4_19: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(36), DIA1=>Data(37), DIA2=>Data(38), 
+            DIA3=>Data(39), DIA4=>Data(40), DIA5=>Data(41), 
+            DIA6=>Data(42), DIA7=>Data(43), DIA8=>Data(44), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_36, 
+            DOB1=>mdout1_0_37, DOB2=>mdout1_0_38, DOB3=>mdout1_0_39, 
+            DOB4=>mdout1_0_40, DOB5=>mdout1_0_41, DOB6=>mdout1_0_42, 
+            DOB7=>mdout1_0_43, DOB8=>mdout1_0_44, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    pdp_ram_0_5_18: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(45), DIA1=>Data(46), DIA2=>Data(47), 
+            DIA3=>Data(48), DIA4=>Data(49), DIA5=>Data(50), 
+            DIA6=>Data(51), DIA7=>Data(52), DIA8=>Data(53), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_45, 
+            DOB1=>mdout1_0_46, DOB2=>mdout1_0_47, DOB3=>mdout1_0_48, 
+            DOB4=>mdout1_0_49, DOB5=>mdout1_0_50, DOB6=>mdout1_0_51, 
+            DOB7=>mdout1_0_52, DOB8=>mdout1_0_53, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    pdp_ram_0_6_17: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(54), DIA1=>Data(55), DIA2=>Data(56), 
+            DIA3=>Data(57), DIA4=>Data(58), DIA5=>Data(59), 
+            DIA6=>Data(60), DIA7=>Data(61), DIA8=>Data(62), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_54, 
+            DOB1=>mdout1_0_55, DOB2=>mdout1_0_56, DOB3=>mdout1_0_57, 
+            DOB4=>mdout1_0_58, DOB5=>mdout1_0_59, DOB6=>mdout1_0_60, 
+            DOB7=>mdout1_0_61, DOB8=>mdout1_0_62, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    pdp_ram_0_7_16: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(63), DIA1=>Data(64), DIA2=>Data(65), 
+            DIA3=>Data(66), DIA4=>Data(67), DIA5=>Data(68), 
+            DIA6=>Data(69), DIA7=>Data(70), DIA8=>Data(71), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_63, 
+            DOB1=>mdout1_0_64, DOB2=>mdout1_0_65, DOB3=>mdout1_0_66, 
+            DOB4=>mdout1_0_67, DOB5=>mdout1_0_68, DOB6=>mdout1_0_69, 
+            DOB7=>mdout1_0_70, DOB8=>mdout1_0_71, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    pdp_ram_0_8_15: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(72), DIA1=>Data(73), DIA2=>Data(74), 
+            DIA3=>Data(75), DIA4=>Data(76), DIA5=>Data(77), 
+            DIA6=>Data(78), DIA7=>Data(79), DIA8=>Data(80), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_72, 
+            DOB1=>mdout1_0_73, DOB2=>mdout1_0_74, DOB3=>mdout1_0_75, 
+            DOB4=>mdout1_0_76, DOB5=>mdout1_0_77, DOB6=>mdout1_0_78, 
+            DOB7=>mdout1_0_79, DOB8=>mdout1_0_80, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    pdp_ram_0_9_14: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(81), DIA1=>Data(82), DIA2=>Data(83), 
+            DIA3=>Data(84), DIA4=>Data(85), DIA5=>Data(86), 
+            DIA6=>Data(87), DIA7=>Data(88), DIA8=>Data(89), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_81, 
+            DOB1=>mdout1_0_82, DOB2=>mdout1_0_83, DOB3=>mdout1_0_84, 
+            DOB4=>mdout1_0_85, DOB5=>mdout1_0_86, DOB6=>mdout1_0_87, 
+            DOB7=>mdout1_0_88, DOB8=>mdout1_0_89, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    pdp_ram_0_10_13: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(90), DIA1=>Data(91), DIA2=>Data(92), 
+            DIA3=>Data(93), DIA4=>Data(94), DIA5=>Data(95), 
+            DIA6=>Data(96), DIA7=>Data(97), DIA8=>Data(98), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_90, 
+            DOB1=>mdout1_0_91, DOB2=>mdout1_0_92, DOB3=>mdout1_0_93, 
+            DOB4=>mdout1_0_94, DOB5=>mdout1_0_95, DOB6=>mdout1_0_96, 
+            DOB7=>mdout1_0_97, DOB8=>mdout1_0_98, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    pdp_ram_0_11_12: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(99), DIA1=>Data(100), DIA2=>Data(101), 
+            DIA3=>Data(102), DIA4=>scuba_vlo, DIA5=>scuba_vlo, 
+            DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_99, 
+            DOB1=>mdout1_0_100, DOB2=>mdout1_0_101, DOB3=>mdout1_0_102, 
+            DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, 
+            DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, 
+            DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, 
+            DOB17=>open);
+
+    pdp_ram_1_0_11: DP16KC
+        generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), 
+            DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), 
+            DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, 
+            DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, 
+            ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, 
+            ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, 
+            ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, 
+            WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>scuba_vlo, 
+            CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>scuba_vlo, 
+            CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, 
+            DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, 
+            DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, 
+            DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, 
+            DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, 
+            DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, 
+            DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, 
+            DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_1_1_10: DP16KC
+        generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), 
+            DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), 
+            DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_9, 
+            DOB1=>mdout1_1_10, DOB2=>mdout1_1_11, DOB3=>mdout1_1_12, 
+            DOB4=>mdout1_1_13, DOB5=>mdout1_1_14, DOB6=>mdout1_1_15, 
+            DOB7=>mdout1_1_16, DOB8=>mdout1_1_17, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    pdp_ram_1_2_9: DP16KC
+        generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20), 
+            DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23), 
+            DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_18, 
+            DOB1=>mdout1_1_19, DOB2=>mdout1_1_20, DOB3=>mdout1_1_21, 
+            DOB4=>mdout1_1_22, DOB5=>mdout1_1_23, DOB6=>mdout1_1_24, 
+            DOB7=>mdout1_1_25, DOB8=>mdout1_1_26, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    pdp_ram_1_3_8: DP16KC
+        generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29), 
+            DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32), 
+            DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_27, 
+            DOB1=>mdout1_1_28, DOB2=>mdout1_1_29, DOB3=>mdout1_1_30, 
+            DOB4=>mdout1_1_31, DOB5=>mdout1_1_32, DOB6=>mdout1_1_33, 
+            DOB7=>mdout1_1_34, DOB8=>mdout1_1_35, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    pdp_ram_1_4_7: DP16KC
+        generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(36), DIA1=>Data(37), DIA2=>Data(38), 
+            DIA3=>Data(39), DIA4=>Data(40), DIA5=>Data(41), 
+            DIA6=>Data(42), DIA7=>Data(43), DIA8=>Data(44), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_36, 
+            DOB1=>mdout1_1_37, DOB2=>mdout1_1_38, DOB3=>mdout1_1_39, 
+            DOB4=>mdout1_1_40, DOB5=>mdout1_1_41, DOB6=>mdout1_1_42, 
+            DOB7=>mdout1_1_43, DOB8=>mdout1_1_44, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    pdp_ram_1_5_6: DP16KC
+        generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(45), DIA1=>Data(46), DIA2=>Data(47), 
+            DIA3=>Data(48), DIA4=>Data(49), DIA5=>Data(50), 
+            DIA6=>Data(51), DIA7=>Data(52), DIA8=>Data(53), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_45, 
+            DOB1=>mdout1_1_46, DOB2=>mdout1_1_47, DOB3=>mdout1_1_48, 
+            DOB4=>mdout1_1_49, DOB5=>mdout1_1_50, DOB6=>mdout1_1_51, 
+            DOB7=>mdout1_1_52, DOB8=>mdout1_1_53, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    pdp_ram_1_6_5: DP16KC
+        generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(54), DIA1=>Data(55), DIA2=>Data(56), 
+            DIA3=>Data(57), DIA4=>Data(58), DIA5=>Data(59), 
+            DIA6=>Data(60), DIA7=>Data(61), DIA8=>Data(62), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_54, 
+            DOB1=>mdout1_1_55, DOB2=>mdout1_1_56, DOB3=>mdout1_1_57, 
+            DOB4=>mdout1_1_58, DOB5=>mdout1_1_59, DOB6=>mdout1_1_60, 
+            DOB7=>mdout1_1_61, DOB8=>mdout1_1_62, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    pdp_ram_1_7_4: DP16KC
+        generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(63), DIA1=>Data(64), DIA2=>Data(65), 
+            DIA3=>Data(66), DIA4=>Data(67), DIA5=>Data(68), 
+            DIA6=>Data(69), DIA7=>Data(70), DIA8=>Data(71), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_63, 
+            DOB1=>mdout1_1_64, DOB2=>mdout1_1_65, DOB3=>mdout1_1_66, 
+            DOB4=>mdout1_1_67, DOB5=>mdout1_1_68, DOB6=>mdout1_1_69, 
+            DOB7=>mdout1_1_70, DOB8=>mdout1_1_71, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    pdp_ram_1_8_3: DP16KC
+        generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(72), DIA1=>Data(73), DIA2=>Data(74), 
+            DIA3=>Data(75), DIA4=>Data(76), DIA5=>Data(77), 
+            DIA6=>Data(78), DIA7=>Data(79), DIA8=>Data(80), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_72, 
+            DOB1=>mdout1_1_73, DOB2=>mdout1_1_74, DOB3=>mdout1_1_75, 
+            DOB4=>mdout1_1_76, DOB5=>mdout1_1_77, DOB6=>mdout1_1_78, 
+            DOB7=>mdout1_1_79, DOB8=>mdout1_1_80, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    pdp_ram_1_9_2: DP16KC
+        generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(81), DIA1=>Data(82), DIA2=>Data(83), 
+            DIA3=>Data(84), DIA4=>Data(85), DIA5=>Data(86), 
+            DIA6=>Data(87), DIA7=>Data(88), DIA8=>Data(89), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_81, 
+            DOB1=>mdout1_1_82, DOB2=>mdout1_1_83, DOB3=>mdout1_1_84, 
+            DOB4=>mdout1_1_85, DOB5=>mdout1_1_86, DOB6=>mdout1_1_87, 
+            DOB7=>mdout1_1_88, DOB8=>mdout1_1_89, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    pdp_ram_1_10_1: DP16KC
+        generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(90), DIA1=>Data(91), DIA2=>Data(92), 
+            DIA3=>Data(93), DIA4=>Data(94), DIA5=>Data(95), 
+            DIA6=>Data(96), DIA7=>Data(97), DIA8=>Data(98), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_90, 
+            DOB1=>mdout1_1_91, DOB2=>mdout1_1_92, DOB3=>mdout1_1_93, 
+            DOB4=>mdout1_1_94, DOB5=>mdout1_1_95, DOB6=>mdout1_1_96, 
+            DOB7=>mdout1_1_97, DOB8=>mdout1_1_98, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    pdp_ram_1_11_0: DP16KC
+        generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(99), DIA1=>Data(100), DIA2=>Data(101), 
+            DIA3=>Data(102), DIA4=>scuba_vlo, DIA5=>scuba_vlo, 
+            DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_99, 
+            DOB1=>mdout1_1_100, DOB2=>mdout1_1_101, DOB3=>mdout1_1_102, 
+            DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, 
+            DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, 
+            DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, 
+            DOB17=>open);
+
+    FF_145: FD1P3BX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>wcount_0);
+
+    FF_144: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_143: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_142: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_141: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_140: FD1P3DX
+        port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_139: FD1P3DX
+        port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_6);
+
+    FF_138: FD1P3DX
+        port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_7);
+
+    FF_137: FD1P3DX
+        port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_8);
+
+    FF_136: FD1P3DX
+        port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_9);
+
+    FF_135: FD1P3DX
+        port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_10);
+
+    FF_134: FD1P3DX
+        port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_11);
+
+    FF_133: FD1P3DX
+        port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_12);
+
+    FF_132: FD1P3DX
+        port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_0);
+
+    FF_131: FD1P3DX
+        port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_1);
+
+    FF_130: FD1P3DX
+        port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_2);
+
+    FF_129: FD1P3DX
+        port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_3);
+
+    FF_128: FD1P3DX
+        port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_4);
+
+    FF_127: FD1P3DX
+        port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_5);
+
+    FF_126: FD1P3DX
+        port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_6);
+
+    FF_125: FD1P3DX
+        port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_7);
+
+    FF_124: FD1P3DX
+        port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_8);
+
+    FF_123: FD1P3DX
+        port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_9);
+
+    FF_122: FD1P3DX
+        port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_10);
+
+    FF_121: FD1P3DX
+        port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_11);
+
+    FF_120: FD1P3DX
+        port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_12);
+
+    FF_119: FD1P3DX
+        port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_0);
+
+    FF_118: FD1P3DX
+        port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_1);
+
+    FF_117: FD1P3DX
+        port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_2);
+
+    FF_116: FD1P3DX
+        port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_3);
+
+    FF_115: FD1P3DX
+        port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_4);
+
+    FF_114: FD1P3DX
+        port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_5);
+
+    FF_113: FD1P3DX
+        port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_6);
+
+    FF_112: FD1P3DX
+        port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_7);
+
+    FF_111: FD1P3DX
+        port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_8);
+
+    FF_110: FD1P3DX
+        port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_9);
+
+    FF_109: FD1P3DX
+        port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_10);
+
+    FF_108: FD1P3DX
+        port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_11);
+
+    FF_107: FD1P3DX
+        port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_12);
+
+    FF_106: FD1P3BX
+        port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, 
+            Q=>rcount_0);
+
+    FF_105: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_1);
+
+    FF_104: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_2);
+
+    FF_103: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_3);
+
+    FF_102: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_4);
+
+    FF_101: FD1P3DX
+        port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_5);
+
+    FF_100: FD1P3DX
+        port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_6);
+
+    FF_99: FD1P3DX
+        port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_7);
+
+    FF_98: FD1P3DX
+        port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_8);
+
+    FF_97: FD1P3DX
+        port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_9);
+
+    FF_96: FD1P3DX
+        port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_10);
+
+    FF_95: FD1P3DX
+        port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_11);
+
+    FF_94: FD1P3DX
+        port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_12);
+
+    FF_93: FD1P3DX
+        port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_0);
+
+    FF_92: FD1P3DX
+        port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_1);
+
+    FF_91: FD1P3DX
+        port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_2);
+
+    FF_90: FD1P3DX
+        port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_3);
+
+    FF_89: FD1P3DX
+        port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_4);
+
+    FF_88: FD1P3DX
+        port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_5);
+
+    FF_87: FD1P3DX
+        port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_6);
+
+    FF_86: FD1P3DX
+        port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_7);
+
+    FF_85: FD1P3DX
+        port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_8);
+
+    FF_84: FD1P3DX
+        port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_9);
+
+    FF_83: FD1P3DX
+        port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_10);
+
+    FF_82: FD1P3DX
+        port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_11);
+
+    FF_81: FD1P3DX
+        port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_12);
+
+    FF_80: FD1P3DX
+        port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_0);
+
+    FF_79: FD1P3DX
+        port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_1);
+
+    FF_78: FD1P3DX
+        port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_2);
+
+    FF_77: FD1P3DX
+        port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_3);
+
+    FF_76: FD1P3DX
+        port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_4);
+
+    FF_75: FD1P3DX
+        port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_5);
+
+    FF_74: FD1P3DX
+        port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_6);
+
+    FF_73: FD1P3DX
+        port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_7);
+
+    FF_72: FD1P3DX
+        port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_8);
+
+    FF_71: FD1P3DX
+        port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_9);
+
+    FF_70: FD1P3DX
+        port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_10);
+
+    FF_69: FD1P3DX
+        port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_11);
+
+    FF_68: FD1P3DX
+        port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_12);
+
+    FF_67: FD1P3DX
+        port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, 
+            Q=>rptr_11_ff);
+
+    FF_66: FD1S3DX
+        port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+    FF_65: FD1S3DX
+        port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+    FF_64: FD1S3DX
+        port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+    FF_63: FD1S3DX
+        port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+    FF_62: FD1S3DX
+        port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+    FF_61: FD1S3DX
+        port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+    FF_60: FD1S3DX
+        port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
+
+    FF_59: FD1S3DX
+        port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
+
+    FF_58: FD1S3DX
+        port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
+
+    FF_57: FD1S3DX
+        port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
+
+    FF_56: FD1S3DX
+        port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r10);
+
+    FF_55: FD1S3DX
+        port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r11);
+
+    FF_54: FD1S3DX
+        port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r12);
+
+    FF_53: FD1S3DX
+        port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+    FF_52: FD1S3DX
+        port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+    FF_51: FD1S3DX
+        port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+    FF_50: FD1S3DX
+        port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+    FF_49: FD1S3DX
+        port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+    FF_48: FD1S3DX
+        port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+    FF_47: FD1S3DX
+        port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+    FF_46: FD1S3DX
+        port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
+
+    FF_45: FD1S3DX
+        port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
+
+    FF_44: FD1S3DX
+        port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
+
+    FF_43: FD1S3DX
+        port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
+
+    FF_42: FD1S3DX
+        port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
+
+    FF_41: FD1S3DX
+        port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
+
+    FF_40: FD1S3DX
+        port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r20);
+
+    FF_39: FD1S3DX
+        port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r21);
+
+    FF_38: FD1S3DX
+        port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r22);
+
+    FF_37: FD1S3DX
+        port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r23);
+
+    FF_36: FD1S3DX
+        port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r24);
+
+    FF_35: FD1S3DX
+        port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r25);
+
+    FF_34: FD1S3DX
+        port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r26);
+
+    FF_33: FD1S3DX
+        port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r27);
+
+    FF_32: FD1S3DX
+        port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r28);
+
+    FF_31: FD1S3DX
+        port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r29);
+
+    FF_30: FD1S3DX
+        port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r210);
+
+    FF_29: FD1S3DX
+        port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r211);
+
+    FF_28: FD1S3DX
+        port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r212);
+
+    FF_27: FD1S3DX
+        port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+    FF_26: FD1S3DX
+        port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+    FF_25: FD1S3DX
+        port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+    FF_24: FD1S3DX
+        port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+    FF_23: FD1S3DX
+        port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+    FF_22: FD1S3DX
+        port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+    FF_21: FD1S3DX
+        port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
+
+    FF_20: FD1S3DX
+        port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
+
+    FF_19: FD1S3DX
+        port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
+
+    FF_18: FD1S3DX
+        port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
+
+    FF_17: FD1S3DX
+        port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, 
+            Q=>r_gcount_w210);
+
+    FF_16: FD1S3DX
+        port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, 
+            Q=>r_gcount_w211);
+
+    FF_15: FD1S3DX
+        port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, 
+            Q=>r_gcount_w212);
+
+    FF_14: FD1S3DX
+        port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0));
+
+    FF_13: FD1S3DX
+        port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1));
+
+    FF_12: FD1S3DX
+        port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2));
+
+    FF_11: FD1S3DX
+        port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3));
+
+    FF_10: FD1S3DX
+        port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4));
+
+    FF_9: FD1S3DX
+        port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5));
+
+    FF_8: FD1S3DX
+        port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6));
+
+    FF_7: FD1S3DX
+        port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7));
+
+    FF_6: FD1S3DX
+        port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8));
+
+    FF_5: FD1S3DX
+        port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9));
+
+    FF_4: FD1S3DX
+        port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10));
+
+    FF_3: FD1S3DX
+        port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11));
+
+    FF_2: FD1S3DX
+        port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12));
+
+    FF_1: FD1S3BX
+        port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+    FF_0: FD1S3DX
+        port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+    w_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, 
+            S1=>open);
+
+    w_gctr_0: CU2
+        port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, 
+            NC0=>iwcount_0, NC1=>iwcount_1);
+
+    w_gctr_1: CU2
+        port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, 
+            NC0=>iwcount_2, NC1=>iwcount_3);
+
+    w_gctr_2: CU2
+        port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, 
+            NC0=>iwcount_4, NC1=>iwcount_5);
+
+    w_gctr_3: CU2
+        port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, 
+            NC0=>iwcount_6, NC1=>iwcount_7);
+
+    w_gctr_4: CU2
+        port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, 
+            NC0=>iwcount_8, NC1=>iwcount_9);
+
+    w_gctr_5: CU2
+        port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, 
+            NC0=>iwcount_10, NC1=>iwcount_11);
+
+    w_gctr_6: CU2
+        port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6, 
+            NC0=>iwcount_12, NC1=>open);
+
+    r_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, 
+            S1=>open);
+
+    r_gctr_0: CU2
+        port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, 
+            NC0=>ircount_0, NC1=>ircount_1);
+
+    r_gctr_1: CU2
+        port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, 
+            NC0=>ircount_2, NC1=>ircount_3);
+
+    r_gctr_2: CU2
+        port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, 
+            NC0=>ircount_4, NC1=>ircount_5);
+
+    r_gctr_3: CU2
+        port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, 
+            NC0=>ircount_6, NC1=>ircount_7);
+
+    r_gctr_4: CU2
+        port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, 
+            NC0=>ircount_8, NC1=>ircount_9);
+
+    r_gctr_5: CU2
+        port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, 
+            NC0=>ircount_10, NC1=>ircount_11);
+
+    r_gctr_6: CU2
+        port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1, 
+            NC0=>ircount_12, NC1=>open);
+
+    mux_102: MUX21
+        port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>rptr_11_ff, 
+            Z=>Q(0));
+
+    mux_101: MUX21
+        port map (D0=>mdout1_0_1, D1=>mdout1_1_1, SD=>rptr_11_ff, 
+            Z=>Q(1));
+
+    mux_100: MUX21
+        port map (D0=>mdout1_0_2, D1=>mdout1_1_2, SD=>rptr_11_ff, 
+            Z=>Q(2));
+
+    mux_99: MUX21
+        port map (D0=>mdout1_0_3, D1=>mdout1_1_3, SD=>rptr_11_ff, 
+            Z=>Q(3));
+
+    mux_98: MUX21
+        port map (D0=>mdout1_0_4, D1=>mdout1_1_4, SD=>rptr_11_ff, 
+            Z=>Q(4));
+
+    mux_97: MUX21
+        port map (D0=>mdout1_0_5, D1=>mdout1_1_5, SD=>rptr_11_ff, 
+            Z=>Q(5));
+
+    mux_96: MUX21
+        port map (D0=>mdout1_0_6, D1=>mdout1_1_6, SD=>rptr_11_ff, 
+            Z=>Q(6));
+
+    mux_95: MUX21
+        port map (D0=>mdout1_0_7, D1=>mdout1_1_7, SD=>rptr_11_ff, 
+            Z=>Q(7));
+
+    mux_94: MUX21
+        port map (D0=>mdout1_0_8, D1=>mdout1_1_8, SD=>rptr_11_ff, 
+            Z=>Q(8));
+
+    mux_93: MUX21
+        port map (D0=>mdout1_0_9, D1=>mdout1_1_9, SD=>rptr_11_ff, 
+            Z=>Q(9));
+
+    mux_92: MUX21
+        port map (D0=>mdout1_0_10, D1=>mdout1_1_10, SD=>rptr_11_ff, 
+            Z=>Q(10));
+
+    mux_91: MUX21
+        port map (D0=>mdout1_0_11, D1=>mdout1_1_11, SD=>rptr_11_ff, 
+            Z=>Q(11));
+
+    mux_90: MUX21
+        port map (D0=>mdout1_0_12, D1=>mdout1_1_12, SD=>rptr_11_ff, 
+            Z=>Q(12));
+
+    mux_89: MUX21
+        port map (D0=>mdout1_0_13, D1=>mdout1_1_13, SD=>rptr_11_ff, 
+            Z=>Q(13));
+
+    mux_88: MUX21
+        port map (D0=>mdout1_0_14, D1=>mdout1_1_14, SD=>rptr_11_ff, 
+            Z=>Q(14));
+
+    mux_87: MUX21
+        port map (D0=>mdout1_0_15, D1=>mdout1_1_15, SD=>rptr_11_ff, 
+            Z=>Q(15));
+
+    mux_86: MUX21
+        port map (D0=>mdout1_0_16, D1=>mdout1_1_16, SD=>rptr_11_ff, 
+            Z=>Q(16));
+
+    mux_85: MUX21
+        port map (D0=>mdout1_0_17, D1=>mdout1_1_17, SD=>rptr_11_ff, 
+            Z=>Q(17));
+
+    mux_84: MUX21
+        port map (D0=>mdout1_0_18, D1=>mdout1_1_18, SD=>rptr_11_ff, 
+            Z=>Q(18));
+
+    mux_83: MUX21
+        port map (D0=>mdout1_0_19, D1=>mdout1_1_19, SD=>rptr_11_ff, 
+            Z=>Q(19));
+
+    mux_82: MUX21
+        port map (D0=>mdout1_0_20, D1=>mdout1_1_20, SD=>rptr_11_ff, 
+            Z=>Q(20));
+
+    mux_81: MUX21
+        port map (D0=>mdout1_0_21, D1=>mdout1_1_21, SD=>rptr_11_ff, 
+            Z=>Q(21));
+
+    mux_80: MUX21
+        port map (D0=>mdout1_0_22, D1=>mdout1_1_22, SD=>rptr_11_ff, 
+            Z=>Q(22));
+
+    mux_79: MUX21
+        port map (D0=>mdout1_0_23, D1=>mdout1_1_23, SD=>rptr_11_ff, 
+            Z=>Q(23));
+
+    mux_78: MUX21
+        port map (D0=>mdout1_0_24, D1=>mdout1_1_24, SD=>rptr_11_ff, 
+            Z=>Q(24));
+
+    mux_77: MUX21
+        port map (D0=>mdout1_0_25, D1=>mdout1_1_25, SD=>rptr_11_ff, 
+            Z=>Q(25));
+
+    mux_76: MUX21
+        port map (D0=>mdout1_0_26, D1=>mdout1_1_26, SD=>rptr_11_ff, 
+            Z=>Q(26));
+
+    mux_75: MUX21
+        port map (D0=>mdout1_0_27, D1=>mdout1_1_27, SD=>rptr_11_ff, 
+            Z=>Q(27));
+
+    mux_74: MUX21
+        port map (D0=>mdout1_0_28, D1=>mdout1_1_28, SD=>rptr_11_ff, 
+            Z=>Q(28));
+
+    mux_73: MUX21
+        port map (D0=>mdout1_0_29, D1=>mdout1_1_29, SD=>rptr_11_ff, 
+            Z=>Q(29));
+
+    mux_72: MUX21
+        port map (D0=>mdout1_0_30, D1=>mdout1_1_30, SD=>rptr_11_ff, 
+            Z=>Q(30));
+
+    mux_71: MUX21
+        port map (D0=>mdout1_0_31, D1=>mdout1_1_31, SD=>rptr_11_ff, 
+            Z=>Q(31));
+
+    mux_70: MUX21
+        port map (D0=>mdout1_0_32, D1=>mdout1_1_32, SD=>rptr_11_ff, 
+            Z=>Q(32));
+
+    mux_69: MUX21
+        port map (D0=>mdout1_0_33, D1=>mdout1_1_33, SD=>rptr_11_ff, 
+            Z=>Q(33));
+
+    mux_68: MUX21
+        port map (D0=>mdout1_0_34, D1=>mdout1_1_34, SD=>rptr_11_ff, 
+            Z=>Q(34));
+
+    mux_67: MUX21
+        port map (D0=>mdout1_0_35, D1=>mdout1_1_35, SD=>rptr_11_ff, 
+            Z=>Q(35));
+
+    mux_66: MUX21
+        port map (D0=>mdout1_0_36, D1=>mdout1_1_36, SD=>rptr_11_ff, 
+            Z=>Q(36));
+
+    mux_65: MUX21
+        port map (D0=>mdout1_0_37, D1=>mdout1_1_37, SD=>rptr_11_ff, 
+            Z=>Q(37));
+
+    mux_64: MUX21
+        port map (D0=>mdout1_0_38, D1=>mdout1_1_38, SD=>rptr_11_ff, 
+            Z=>Q(38));
+
+    mux_63: MUX21
+        port map (D0=>mdout1_0_39, D1=>mdout1_1_39, SD=>rptr_11_ff, 
+            Z=>Q(39));
+
+    mux_62: MUX21
+        port map (D0=>mdout1_0_40, D1=>mdout1_1_40, SD=>rptr_11_ff, 
+            Z=>Q(40));
+
+    mux_61: MUX21
+        port map (D0=>mdout1_0_41, D1=>mdout1_1_41, SD=>rptr_11_ff, 
+            Z=>Q(41));
+
+    mux_60: MUX21
+        port map (D0=>mdout1_0_42, D1=>mdout1_1_42, SD=>rptr_11_ff, 
+            Z=>Q(42));
+
+    mux_59: MUX21
+        port map (D0=>mdout1_0_43, D1=>mdout1_1_43, SD=>rptr_11_ff, 
+            Z=>Q(43));
+
+    mux_58: MUX21
+        port map (D0=>mdout1_0_44, D1=>mdout1_1_44, SD=>rptr_11_ff, 
+            Z=>Q(44));
+
+    mux_57: MUX21
+        port map (D0=>mdout1_0_45, D1=>mdout1_1_45, SD=>rptr_11_ff, 
+            Z=>Q(45));
+
+    mux_56: MUX21
+        port map (D0=>mdout1_0_46, D1=>mdout1_1_46, SD=>rptr_11_ff, 
+            Z=>Q(46));
+
+    mux_55: MUX21
+        port map (D0=>mdout1_0_47, D1=>mdout1_1_47, SD=>rptr_11_ff, 
+            Z=>Q(47));
+
+    mux_54: MUX21
+        port map (D0=>mdout1_0_48, D1=>mdout1_1_48, SD=>rptr_11_ff, 
+            Z=>Q(48));
+
+    mux_53: MUX21
+        port map (D0=>mdout1_0_49, D1=>mdout1_1_49, SD=>rptr_11_ff, 
+            Z=>Q(49));
+
+    mux_52: MUX21
+        port map (D0=>mdout1_0_50, D1=>mdout1_1_50, SD=>rptr_11_ff, 
+            Z=>Q(50));
+
+    mux_51: MUX21
+        port map (D0=>mdout1_0_51, D1=>mdout1_1_51, SD=>rptr_11_ff, 
+            Z=>Q(51));
+
+    mux_50: MUX21
+        port map (D0=>mdout1_0_52, D1=>mdout1_1_52, SD=>rptr_11_ff, 
+            Z=>Q(52));
+
+    mux_49: MUX21
+        port map (D0=>mdout1_0_53, D1=>mdout1_1_53, SD=>rptr_11_ff, 
+            Z=>Q(53));
+
+    mux_48: MUX21
+        port map (D0=>mdout1_0_54, D1=>mdout1_1_54, SD=>rptr_11_ff, 
+            Z=>Q(54));
+
+    mux_47: MUX21
+        port map (D0=>mdout1_0_55, D1=>mdout1_1_55, SD=>rptr_11_ff, 
+            Z=>Q(55));
+
+    mux_46: MUX21
+        port map (D0=>mdout1_0_56, D1=>mdout1_1_56, SD=>rptr_11_ff, 
+            Z=>Q(56));
+
+    mux_45: MUX21
+        port map (D0=>mdout1_0_57, D1=>mdout1_1_57, SD=>rptr_11_ff, 
+            Z=>Q(57));
+
+    mux_44: MUX21
+        port map (D0=>mdout1_0_58, D1=>mdout1_1_58, SD=>rptr_11_ff, 
+            Z=>Q(58));
+
+    mux_43: MUX21
+        port map (D0=>mdout1_0_59, D1=>mdout1_1_59, SD=>rptr_11_ff, 
+            Z=>Q(59));
+
+    mux_42: MUX21
+        port map (D0=>mdout1_0_60, D1=>mdout1_1_60, SD=>rptr_11_ff, 
+            Z=>Q(60));
+
+    mux_41: MUX21
+        port map (D0=>mdout1_0_61, D1=>mdout1_1_61, SD=>rptr_11_ff, 
+            Z=>Q(61));
+
+    mux_40: MUX21
+        port map (D0=>mdout1_0_62, D1=>mdout1_1_62, SD=>rptr_11_ff, 
+            Z=>Q(62));
+
+    mux_39: MUX21
+        port map (D0=>mdout1_0_63, D1=>mdout1_1_63, SD=>rptr_11_ff, 
+            Z=>Q(63));
+
+    mux_38: MUX21
+        port map (D0=>mdout1_0_64, D1=>mdout1_1_64, SD=>rptr_11_ff, 
+            Z=>Q(64));
+
+    mux_37: MUX21
+        port map (D0=>mdout1_0_65, D1=>mdout1_1_65, SD=>rptr_11_ff, 
+            Z=>Q(65));
+
+    mux_36: MUX21
+        port map (D0=>mdout1_0_66, D1=>mdout1_1_66, SD=>rptr_11_ff, 
+            Z=>Q(66));
+
+    mux_35: MUX21
+        port map (D0=>mdout1_0_67, D1=>mdout1_1_67, SD=>rptr_11_ff, 
+            Z=>Q(67));
+
+    mux_34: MUX21
+        port map (D0=>mdout1_0_68, D1=>mdout1_1_68, SD=>rptr_11_ff, 
+            Z=>Q(68));
+
+    mux_33: MUX21
+        port map (D0=>mdout1_0_69, D1=>mdout1_1_69, SD=>rptr_11_ff, 
+            Z=>Q(69));
+
+    mux_32: MUX21
+        port map (D0=>mdout1_0_70, D1=>mdout1_1_70, SD=>rptr_11_ff, 
+            Z=>Q(70));
+
+    mux_31: MUX21
+        port map (D0=>mdout1_0_71, D1=>mdout1_1_71, SD=>rptr_11_ff, 
+            Z=>Q(71));
+
+    mux_30: MUX21
+        port map (D0=>mdout1_0_72, D1=>mdout1_1_72, SD=>rptr_11_ff, 
+            Z=>Q(72));
+
+    mux_29: MUX21
+        port map (D0=>mdout1_0_73, D1=>mdout1_1_73, SD=>rptr_11_ff, 
+            Z=>Q(73));
+
+    mux_28: MUX21
+        port map (D0=>mdout1_0_74, D1=>mdout1_1_74, SD=>rptr_11_ff, 
+            Z=>Q(74));
+
+    mux_27: MUX21
+        port map (D0=>mdout1_0_75, D1=>mdout1_1_75, SD=>rptr_11_ff, 
+            Z=>Q(75));
+
+    mux_26: MUX21
+        port map (D0=>mdout1_0_76, D1=>mdout1_1_76, SD=>rptr_11_ff, 
+            Z=>Q(76));
+
+    mux_25: MUX21
+        port map (D0=>mdout1_0_77, D1=>mdout1_1_77, SD=>rptr_11_ff, 
+            Z=>Q(77));
+
+    mux_24: MUX21
+        port map (D0=>mdout1_0_78, D1=>mdout1_1_78, SD=>rptr_11_ff, 
+            Z=>Q(78));
+
+    mux_23: MUX21
+        port map (D0=>mdout1_0_79, D1=>mdout1_1_79, SD=>rptr_11_ff, 
+            Z=>Q(79));
+
+    mux_22: MUX21
+        port map (D0=>mdout1_0_80, D1=>mdout1_1_80, SD=>rptr_11_ff, 
+            Z=>Q(80));
+
+    mux_21: MUX21
+        port map (D0=>mdout1_0_81, D1=>mdout1_1_81, SD=>rptr_11_ff, 
+            Z=>Q(81));
+
+    mux_20: MUX21
+        port map (D0=>mdout1_0_82, D1=>mdout1_1_82, SD=>rptr_11_ff, 
+            Z=>Q(82));
+
+    mux_19: MUX21
+        port map (D0=>mdout1_0_83, D1=>mdout1_1_83, SD=>rptr_11_ff, 
+            Z=>Q(83));
+
+    mux_18: MUX21
+        port map (D0=>mdout1_0_84, D1=>mdout1_1_84, SD=>rptr_11_ff, 
+            Z=>Q(84));
+
+    mux_17: MUX21
+        port map (D0=>mdout1_0_85, D1=>mdout1_1_85, SD=>rptr_11_ff, 
+            Z=>Q(85));
+
+    mux_16: MUX21
+        port map (D0=>mdout1_0_86, D1=>mdout1_1_86, SD=>rptr_11_ff, 
+            Z=>Q(86));
+
+    mux_15: MUX21
+        port map (D0=>mdout1_0_87, D1=>mdout1_1_87, SD=>rptr_11_ff, 
+            Z=>Q(87));
+
+    mux_14: MUX21
+        port map (D0=>mdout1_0_88, D1=>mdout1_1_88, SD=>rptr_11_ff, 
+            Z=>Q(88));
+
+    mux_13: MUX21
+        port map (D0=>mdout1_0_89, D1=>mdout1_1_89, SD=>rptr_11_ff, 
+            Z=>Q(89));
+
+    mux_12: MUX21
+        port map (D0=>mdout1_0_90, D1=>mdout1_1_90, SD=>rptr_11_ff, 
+            Z=>Q(90));
+
+    mux_11: MUX21
+        port map (D0=>mdout1_0_91, D1=>mdout1_1_91, SD=>rptr_11_ff, 
+            Z=>Q(91));
+
+    mux_10: MUX21
+        port map (D0=>mdout1_0_92, D1=>mdout1_1_92, SD=>rptr_11_ff, 
+            Z=>Q(92));
+
+    mux_9: MUX21
+        port map (D0=>mdout1_0_93, D1=>mdout1_1_93, SD=>rptr_11_ff, 
+            Z=>Q(93));
+
+    mux_8: MUX21
+        port map (D0=>mdout1_0_94, D1=>mdout1_1_94, SD=>rptr_11_ff, 
+            Z=>Q(94));
+
+    mux_7: MUX21
+        port map (D0=>mdout1_0_95, D1=>mdout1_1_95, SD=>rptr_11_ff, 
+            Z=>Q(95));
+
+    mux_6: MUX21
+        port map (D0=>mdout1_0_96, D1=>mdout1_1_96, SD=>rptr_11_ff, 
+            Z=>Q(96));
+
+    mux_5: MUX21
+        port map (D0=>mdout1_0_97, D1=>mdout1_1_97, SD=>rptr_11_ff, 
+            Z=>Q(97));
+
+    mux_4: MUX21
+        port map (D0=>mdout1_0_98, D1=>mdout1_1_98, SD=>rptr_11_ff, 
+            Z=>Q(98));
+
+    mux_3: MUX21
+        port map (D0=>mdout1_0_99, D1=>mdout1_1_99, SD=>rptr_11_ff, 
+            Z=>Q(99));
+
+    mux_2: MUX21
+        port map (D0=>mdout1_0_100, D1=>mdout1_1_100, SD=>rptr_11_ff, 
+            Z=>Q(100));
+
+    mux_1: MUX21
+        port map (D0=>mdout1_0_101, D1=>mdout1_1_101, SD=>rptr_11_ff, 
+            Z=>Q(101));
+
+    mux_0: MUX21
+        port map (D0=>mdout1_0_102, D1=>mdout1_1_102, SD=>rptr_11_ff, 
+            Z=>Q(102));
+
+    precin_inst690: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin, S0=>open, 
+            S1=>open);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    wfill_0: FSUB2B
+        port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo, 
+            B1=>rcount_w0, BI=>precin, BOUT=>co0_2, S0=>open, 
+            S1=>wfill_sub_0);
+
+    wfill_1: FSUB2B
+        port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w1, B1=>rcount_w2, 
+            BI=>co0_2, BOUT=>co1_2, S0=>wfill_sub_1, S1=>wfill_sub_2);
+
+    wfill_2: FSUB2B
+        port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w3, B1=>rcount_w4, 
+            BI=>co1_2, BOUT=>co2_2, S0=>wfill_sub_3, S1=>wfill_sub_4);
+
+    wfill_3: FSUB2B
+        port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w5, B1=>rcount_w6, 
+            BI=>co2_2, BOUT=>co3_2, S0=>wfill_sub_5, S1=>wfill_sub_6);
+
+    wfill_4: FSUB2B
+        port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w7, B1=>rcount_w8, 
+            BI=>co3_2, BOUT=>co4_2, S0=>wfill_sub_7, S1=>wfill_sub_8);
+
+    wfill_5: FSUB2B
+        port map (A0=>wptr_9, A1=>wptr_10, B0=>r_g2b_xor_cluster_0, 
+            B1=>rcount_w10, BI=>co4_2, BOUT=>co5_2, S0=>wfill_sub_9, 
+            S1=>wfill_sub_10);
+
+    wfill_6: FSUB2B
+        port map (A0=>wptr_11, A1=>wfill_sub_msb, B0=>rcount_w11, 
+            B1=>scuba_vlo, BI=>co5_2, BOUT=>co6_2, S0=>wfill_sub_11, 
+            S1=>wfill_sub_12);
+
+    wfilld: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>co6_2, COUT=>open, S0=>co6_2d, S1=>open);
+
+    empty_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+    empty_cmp_0: AGEB2
+        port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, 
+            B1=>wcount_r1, CI=>cmp_ci, GE=>co0_3);
+
+    empty_cmp_1: AGEB2
+        port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, 
+            B1=>wcount_r3, CI=>co0_3, GE=>co1_3);
+
+    empty_cmp_2: AGEB2
+        port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, 
+            B1=>wcount_r5, CI=>co1_3, GE=>co2_3);
+
+    empty_cmp_3: AGEB2
+        port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, 
+            B1=>wcount_r7, CI=>co2_3, GE=>co3_3);
+
+    empty_cmp_4: AGEB2
+        port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, 
+            B1=>w_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3);
+
+    empty_cmp_5: AGEB2
+        port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, 
+            B1=>wcount_r11, CI=>co4_3, GE=>co5_3);
+
+    empty_cmp_6: AGEB2
+        port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, 
+            B1=>scuba_vlo, CI=>co5_3, GE=>empty_d_c);
+
+    a0: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, 
+            S1=>open);
+
+    full_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+    full_cmp_0: AGEB2
+        port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, 
+            B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_4);
+
+    full_cmp_1: AGEB2
+        port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, 
+            B1=>rcount_w3, CI=>co0_4, GE=>co1_4);
+
+    full_cmp_2: AGEB2
+        port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, 
+            B1=>rcount_w5, CI=>co1_4, GE=>co2_4);
+
+    full_cmp_3: AGEB2
+        port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, 
+            B1=>rcount_w7, CI=>co2_4, GE=>co3_4);
+
+    full_cmp_4: AGEB2
+        port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, 
+            B1=>r_g2b_xor_cluster_0, CI=>co3_4, GE=>co4_4);
+
+    full_cmp_5: AGEB2
+        port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, 
+            B1=>rcount_w11, CI=>co4_4, GE=>co5_4);
+
+    full_cmp_6: AGEB2
+        port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, 
+            B1=>scuba_vlo, CI=>co5_4, GE=>full_d_c);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    a1: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, 
+            S1=>open);
+
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of async_fifo_nn_4096x103_ecp3 is
+    for Structure
+        for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+        for all:AND2 use entity ecp3.AND2(V); end for;
+        for all:CU2 use entity ecp3.CU2(V); end for;
+        for all:FADD2B use entity ecp3.FADD2B(V); end for;
+        for all:FSUB2B use entity ecp3.FSUB2B(V); end for;
+        for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
+        for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+        for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+        for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+        for all:INV use entity ecp3.INV(V); end for;
+        for all:MUX21 use entity ecp3.MUX21(V); end for;
+        for all:OR2 use entity ecp3.OR2(V); end for;
+        for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+        for all:VHI use entity ecp3.VHI(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+        for all:XOR2 use entity ecp3.XOR2(V); end for;
+        for all:DP16KC use entity ecp3.DP16KC(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x103_ecp3_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x103_ecp3_tmpl.vhd
new file mode 100644
index 0000000..0b25835
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x103_ecp3_tmpl.vhd
@@ -0,0 +1,19 @@
+-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.7
+-- Thu Sep 18 09:50:10 2014
+
+-- parameterized module component declaration
+component async_fifo_nn_4096x103_ecp3
+    port (Data: in  std_logic_vector(102 downto 0); 
+        WrClock: in  std_logic; RdClock: in  std_logic; 
+        WrEn: in  std_logic; RdEn: in  std_logic; Reset: in  std_logic; 
+        RPReset: in  std_logic; Q: out  std_logic_vector(102 downto 0); 
+        WCNT: out  std_logic_vector(12 downto 0); Empty: out  std_logic; 
+        Full: out  std_logic);
+end component;
+
+-- parameterized module component instance
+__ : async_fifo_nn_4096x103_ecp3
+    port map (Data(102 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, 
+        RdEn=>__, Reset=>__, RPReset=>__, Q(102 downto 0)=>__, WCNT(12 downto 0)=>__, 
+        Empty=>__, Full=>__);
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x36_ecp3.ipx b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x36_ecp3.ipx
new file mode 100644
index 0000000..220dc75
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x36_ecp3.ipx
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="async_fifo_nn_4096x36_ecp3" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 09 18 10:10:38.550" version="5.7" type="Module" synthesis="" source_format="VHDL">
+  <Package>
+		<File name="async_fifo_nn_4096x36_ecp3.lpc" type="lpc" modified="2014 09 18 10:10:35.709"/>
+		<File name="async_fifo_nn_4096x36_ecp3.vhd" type="top_level_vhdl" modified="2014 09 18 10:10:35.821"/>
+		<File name="async_fifo_nn_4096x36_ecp3_tmpl.vhd" type="template_vhdl" modified="2014 09 18 10:10:35.821"/>
+		<File name="tb_async_fifo_nn_4096x36_ecp3_tmpl.vhd" type="testbench_vhdl" modified="2014 09 18 10:10:35.826"/>
+  </Package>
+</DiamondModule>
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x36_ecp3.lpc b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x36_ecp3.lpc
new file mode 100644
index 0000000..25803b4
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x36_ecp3.lpc
@@ -0,0 +1,50 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.7
+ModuleName=async_fifo_nn_4096x36_ecp3
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=09/18/2014
+Time=10:10:35
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=4096
+Width=36
+RDepth=4096
+RWidth=36
+regout=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=0
+WDataCount=1
+EnECC=0
+
+[Command]
+cmd_line= -w -n async_fifo_nn_4096x36_ecp3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 12 -data_width 36 -num_words 4096 -rdata_width 36 -no_enable -pe -1 -pf -1 -fill
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x36_ecp3.vhd b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x36_ecp3.vhd
new file mode 100644
index 0000000..a0f8782
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x36_ecp3.vhd
@@ -0,0 +1,2165 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.7
+--C:\Lattice\diamond\3.2_x64\ispfpga\bin\nt64\scuba.exe -w -n async_fifo_nn_4096x36_ecp3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4096 -width 36 -depth 4096 -rdata_width 36 -no_enable -pe -1 -pf -1 -fill 
+
+-- Thu Sep 18 10:10:35 2014
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity async_fifo_nn_4096x36_ecp3 is
+    port (
+        Data: in  std_logic_vector(35 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(35 downto 0); 
+        WCNT: out  std_logic_vector(12 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic);
+end async_fifo_nn_4096x36_ecp3;
+
+architecture Structure of async_fifo_nn_4096x36_ecp3 is
+
+    -- internal signal declarations
+    signal invout_1: std_logic;
+    signal invout_0: std_logic;
+    signal w_g2b_xor_cluster_2_1: std_logic;
+    signal w_g2b_xor_cluster_2: std_logic;
+    signal w_g2b_xor_cluster_1: std_logic;
+    signal r_g2b_xor_cluster_2_1: std_logic;
+    signal r_g2b_xor_cluster_2: std_logic;
+    signal r_g2b_xor_cluster_1: std_logic;
+    signal w_gdata_0: std_logic;
+    signal w_gdata_1: std_logic;
+    signal w_gdata_2: std_logic;
+    signal w_gdata_3: std_logic;
+    signal w_gdata_4: std_logic;
+    signal w_gdata_5: std_logic;
+    signal w_gdata_6: std_logic;
+    signal w_gdata_7: std_logic;
+    signal w_gdata_8: std_logic;
+    signal w_gdata_9: std_logic;
+    signal w_gdata_10: std_logic;
+    signal w_gdata_11: std_logic;
+    signal wptr_12: std_logic;
+    signal r_gdata_0: std_logic;
+    signal r_gdata_1: std_logic;
+    signal r_gdata_2: std_logic;
+    signal r_gdata_3: std_logic;
+    signal r_gdata_4: std_logic;
+    signal r_gdata_5: std_logic;
+    signal r_gdata_6: std_logic;
+    signal r_gdata_7: std_logic;
+    signal r_gdata_8: std_logic;
+    signal r_gdata_9: std_logic;
+    signal r_gdata_10: std_logic;
+    signal r_gdata_11: std_logic;
+    signal rptr_0: std_logic;
+    signal rptr_1: std_logic;
+    signal rptr_2: std_logic;
+    signal rptr_3: std_logic;
+    signal rptr_4: std_logic;
+    signal rptr_5: std_logic;
+    signal rptr_6: std_logic;
+    signal rptr_7: std_logic;
+    signal rptr_8: std_logic;
+    signal rptr_9: std_logic;
+    signal rptr_10: std_logic;
+    signal rptr_12: std_logic;
+    signal rptr_11: std_logic;
+    signal w_gcount_0: std_logic;
+    signal w_gcount_1: std_logic;
+    signal w_gcount_2: std_logic;
+    signal w_gcount_3: std_logic;
+    signal w_gcount_4: std_logic;
+    signal w_gcount_5: std_logic;
+    signal w_gcount_6: std_logic;
+    signal w_gcount_7: std_logic;
+    signal w_gcount_8: std_logic;
+    signal w_gcount_9: std_logic;
+    signal w_gcount_10: std_logic;
+    signal w_gcount_11: std_logic;
+    signal w_gcount_12: std_logic;
+    signal r_gcount_0: std_logic;
+    signal r_gcount_1: std_logic;
+    signal r_gcount_2: std_logic;
+    signal r_gcount_3: std_logic;
+    signal r_gcount_4: std_logic;
+    signal r_gcount_5: std_logic;
+    signal r_gcount_6: std_logic;
+    signal r_gcount_7: std_logic;
+    signal r_gcount_8: std_logic;
+    signal r_gcount_9: std_logic;
+    signal r_gcount_10: std_logic;
+    signal r_gcount_11: std_logic;
+    signal r_gcount_12: std_logic;
+    signal w_gcount_r20: std_logic;
+    signal w_gcount_r0: std_logic;
+    signal w_gcount_r21: std_logic;
+    signal w_gcount_r1: std_logic;
+    signal w_gcount_r22: std_logic;
+    signal w_gcount_r2: std_logic;
+    signal w_gcount_r23: std_logic;
+    signal w_gcount_r3: std_logic;
+    signal w_gcount_r24: std_logic;
+    signal w_gcount_r4: std_logic;
+    signal w_gcount_r25: std_logic;
+    signal w_gcount_r5: std_logic;
+    signal w_gcount_r26: std_logic;
+    signal w_gcount_r6: std_logic;
+    signal w_gcount_r27: std_logic;
+    signal w_gcount_r7: std_logic;
+    signal w_gcount_r28: std_logic;
+    signal w_gcount_r8: std_logic;
+    signal w_gcount_r29: std_logic;
+    signal w_gcount_r9: std_logic;
+    signal w_gcount_r210: std_logic;
+    signal w_gcount_r10: std_logic;
+    signal w_gcount_r211: std_logic;
+    signal w_gcount_r11: std_logic;
+    signal w_gcount_r212: std_logic;
+    signal w_gcount_r12: std_logic;
+    signal r_gcount_w20: std_logic;
+    signal r_gcount_w0: std_logic;
+    signal r_gcount_w21: std_logic;
+    signal r_gcount_w1: std_logic;
+    signal r_gcount_w22: std_logic;
+    signal r_gcount_w2: std_logic;
+    signal r_gcount_w23: std_logic;
+    signal r_gcount_w3: std_logic;
+    signal r_gcount_w24: std_logic;
+    signal r_gcount_w4: std_logic;
+    signal r_gcount_w25: std_logic;
+    signal r_gcount_w5: std_logic;
+    signal r_gcount_w26: std_logic;
+    signal r_gcount_w6: std_logic;
+    signal r_gcount_w27: std_logic;
+    signal r_gcount_w7: std_logic;
+    signal r_gcount_w28: std_logic;
+    signal r_gcount_w8: std_logic;
+    signal r_gcount_w29: std_logic;
+    signal r_gcount_w9: std_logic;
+    signal r_gcount_w210: std_logic;
+    signal r_gcount_w10: std_logic;
+    signal r_gcount_w211: std_logic;
+    signal r_gcount_w11: std_logic;
+    signal r_gcount_w212: std_logic;
+    signal r_gcount_w12: std_logic;
+    signal empty_i: std_logic;
+    signal rRst: std_logic;
+    signal full_i: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_gctr_ci: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co0: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal co1: std_logic;
+    signal iwcount_6: std_logic;
+    signal iwcount_7: std_logic;
+    signal co2: std_logic;
+    signal iwcount_8: std_logic;
+    signal iwcount_9: std_logic;
+    signal co3: std_logic;
+    signal iwcount_10: std_logic;
+    signal iwcount_11: std_logic;
+    signal co4: std_logic;
+    signal iwcount_12: std_logic;
+    signal co6: std_logic;
+    signal co5: std_logic;
+    signal wcount_12: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_gctr_ci: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co0_1: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal co1_1: std_logic;
+    signal ircount_6: std_logic;
+    signal ircount_7: std_logic;
+    signal co2_1: std_logic;
+    signal ircount_8: std_logic;
+    signal ircount_9: std_logic;
+    signal co3_1: std_logic;
+    signal ircount_10: std_logic;
+    signal ircount_11: std_logic;
+    signal co4_1: std_logic;
+    signal ircount_12: std_logic;
+    signal co6_1: std_logic;
+    signal co5_1: std_logic;
+    signal rcount_12: std_logic;
+    signal mdout1_1_0: std_logic;
+    signal mdout1_0_0: std_logic;
+    signal mdout1_1_1: std_logic;
+    signal mdout1_0_1: std_logic;
+    signal mdout1_1_2: std_logic;
+    signal mdout1_0_2: std_logic;
+    signal mdout1_1_3: std_logic;
+    signal mdout1_0_3: std_logic;
+    signal mdout1_1_4: std_logic;
+    signal mdout1_0_4: std_logic;
+    signal mdout1_1_5: std_logic;
+    signal mdout1_0_5: std_logic;
+    signal mdout1_1_6: std_logic;
+    signal mdout1_0_6: std_logic;
+    signal mdout1_1_7: std_logic;
+    signal mdout1_0_7: std_logic;
+    signal mdout1_1_8: std_logic;
+    signal mdout1_0_8: std_logic;
+    signal mdout1_1_9: std_logic;
+    signal mdout1_0_9: std_logic;
+    signal mdout1_1_10: std_logic;
+    signal mdout1_0_10: std_logic;
+    signal mdout1_1_11: std_logic;
+    signal mdout1_0_11: std_logic;
+    signal mdout1_1_12: std_logic;
+    signal mdout1_0_12: std_logic;
+    signal mdout1_1_13: std_logic;
+    signal mdout1_0_13: std_logic;
+    signal mdout1_1_14: std_logic;
+    signal mdout1_0_14: std_logic;
+    signal mdout1_1_15: std_logic;
+    signal mdout1_0_15: std_logic;
+    signal mdout1_1_16: std_logic;
+    signal mdout1_0_16: std_logic;
+    signal mdout1_1_17: std_logic;
+    signal mdout1_0_17: std_logic;
+    signal mdout1_1_18: std_logic;
+    signal mdout1_0_18: std_logic;
+    signal mdout1_1_19: std_logic;
+    signal mdout1_0_19: std_logic;
+    signal mdout1_1_20: std_logic;
+    signal mdout1_0_20: std_logic;
+    signal mdout1_1_21: std_logic;
+    signal mdout1_0_21: std_logic;
+    signal mdout1_1_22: std_logic;
+    signal mdout1_0_22: std_logic;
+    signal mdout1_1_23: std_logic;
+    signal mdout1_0_23: std_logic;
+    signal mdout1_1_24: std_logic;
+    signal mdout1_0_24: std_logic;
+    signal mdout1_1_25: std_logic;
+    signal mdout1_0_25: std_logic;
+    signal mdout1_1_26: std_logic;
+    signal mdout1_0_26: std_logic;
+    signal mdout1_1_27: std_logic;
+    signal mdout1_0_27: std_logic;
+    signal mdout1_1_28: std_logic;
+    signal mdout1_0_28: std_logic;
+    signal mdout1_1_29: std_logic;
+    signal mdout1_0_29: std_logic;
+    signal mdout1_1_30: std_logic;
+    signal mdout1_0_30: std_logic;
+    signal mdout1_1_31: std_logic;
+    signal mdout1_0_31: std_logic;
+    signal mdout1_1_32: std_logic;
+    signal mdout1_0_32: std_logic;
+    signal mdout1_1_33: std_logic;
+    signal mdout1_0_33: std_logic;
+    signal mdout1_1_34: std_logic;
+    signal mdout1_0_34: std_logic;
+    signal rptr_11_ff: std_logic;
+    signal mdout1_1_35: std_logic;
+    signal mdout1_0_35: std_logic;
+    signal wfill_sub_0: std_logic;
+    signal precin: std_logic;
+    signal scuba_vhi: std_logic;
+    signal wptr_0: std_logic;
+    signal wfill_sub_1: std_logic;
+    signal wfill_sub_2: std_logic;
+    signal co0_2: std_logic;
+    signal wptr_1: std_logic;
+    signal wptr_2: std_logic;
+    signal wfill_sub_3: std_logic;
+    signal wfill_sub_4: std_logic;
+    signal co1_2: std_logic;
+    signal wptr_3: std_logic;
+    signal wptr_4: std_logic;
+    signal wfill_sub_5: std_logic;
+    signal wfill_sub_6: std_logic;
+    signal co2_2: std_logic;
+    signal wptr_5: std_logic;
+    signal wptr_6: std_logic;
+    signal wfill_sub_7: std_logic;
+    signal wfill_sub_8: std_logic;
+    signal co3_2: std_logic;
+    signal wptr_7: std_logic;
+    signal wptr_8: std_logic;
+    signal wfill_sub_9: std_logic;
+    signal wfill_sub_10: std_logic;
+    signal co4_2: std_logic;
+    signal wptr_9: std_logic;
+    signal wptr_10: std_logic;
+    signal wfill_sub_11: std_logic;
+    signal wfill_sub_12: std_logic;
+    signal co5_2: std_logic;
+    signal wptr_11: std_logic;
+    signal wfill_sub_msb: std_logic;
+    signal co6_2d: std_logic;
+    signal co6_2: std_logic;
+    signal rden_i: std_logic;
+    signal cmp_ci: std_logic;
+    signal wcount_r0: std_logic;
+    signal wcount_r1: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal co0_3: std_logic;
+    signal wcount_r2: std_logic;
+    signal wcount_r3: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal co1_3: std_logic;
+    signal wcount_r4: std_logic;
+    signal wcount_r5: std_logic;
+    signal rcount_4: std_logic;
+    signal rcount_5: std_logic;
+    signal co2_3: std_logic;
+    signal wcount_r6: std_logic;
+    signal wcount_r7: std_logic;
+    signal rcount_6: std_logic;
+    signal rcount_7: std_logic;
+    signal co3_3: std_logic;
+    signal wcount_r8: std_logic;
+    signal w_g2b_xor_cluster_0: std_logic;
+    signal rcount_8: std_logic;
+    signal rcount_9: std_logic;
+    signal co4_3: std_logic;
+    signal wcount_r10: std_logic;
+    signal wcount_r11: std_logic;
+    signal rcount_10: std_logic;
+    signal rcount_11: std_logic;
+    signal co5_3: std_logic;
+    signal empty_cmp_clr: std_logic;
+    signal empty_cmp_set: std_logic;
+    signal empty_d: std_logic;
+    signal empty_d_c: std_logic;
+    signal wren_i: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal rcount_w0: std_logic;
+    signal rcount_w1: std_logic;
+    signal wcount_0: std_logic;
+    signal wcount_1: std_logic;
+    signal co0_4: std_logic;
+    signal rcount_w2: std_logic;
+    signal rcount_w3: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_3: std_logic;
+    signal co1_4: std_logic;
+    signal rcount_w4: std_logic;
+    signal rcount_w5: std_logic;
+    signal wcount_4: std_logic;
+    signal wcount_5: std_logic;
+    signal co2_4: std_logic;
+    signal rcount_w6: std_logic;
+    signal rcount_w7: std_logic;
+    signal wcount_6: std_logic;
+    signal wcount_7: std_logic;
+    signal co3_4: std_logic;
+    signal rcount_w8: std_logic;
+    signal r_g2b_xor_cluster_0: std_logic;
+    signal wcount_8: std_logic;
+    signal wcount_9: std_logic;
+    signal co4_4: std_logic;
+    signal rcount_w10: std_logic;
+    signal rcount_w11: std_logic;
+    signal wcount_10: std_logic;
+    signal wcount_11: std_logic;
+    signal co5_4: std_logic;
+    signal full_cmp_clr: std_logic;
+    signal full_cmp_set: std_logic;
+    signal full_d: std_logic;
+    signal full_d_c: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component AGEB2
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; GE: out  std_logic);
+    end component;
+    component AND2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component CU2
+        port (CI: in  std_logic; PC0: in  std_logic; PC1: in  std_logic; 
+            CO: out  std_logic; NC0: out  std_logic; NC1: out  std_logic);
+    end component;
+    component FADD2B
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; COUT: out  std_logic; 
+            S0: out  std_logic; S1: out  std_logic);
+    end component;
+    component FSUB2B
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; BI: in  std_logic; BOUT: out  std_logic; 
+            S0: out  std_logic; S1: out  std_logic);
+    end component;
+    component FD1P3BX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            PD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1P3DX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            CD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1S3BX
+        port (D: in  std_logic; CK: in  std_logic; PD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component FD1S3DX
+        port (D: in  std_logic; CK: in  std_logic; CD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component INV
+        port (A: in  std_logic; Z: out  std_logic);
+    end component;
+    component MUX21
+        port (D0: in  std_logic; D1: in  std_logic; SD: in  std_logic; 
+            Z: out  std_logic);
+    end component;
+    component OR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component ROM16X1A
+        generic (INITVAL : in std_logic_vector(15 downto 0));
+        port (AD3: in  std_logic; AD2: in  std_logic; AD1: in  std_logic; 
+            AD0: in  std_logic; DO0: out  std_logic);
+    end component;
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component XOR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component DP16KC
+        generic (GSR : in String; WRITEMODE_B : in String; 
+                WRITEMODE_A : in String; CSDECODE_B : in String; 
+                CSDECODE_A : in String; REGMODE_B : in String; 
+                REGMODE_A : in String; DATA_WIDTH_B : in Integer; 
+                DATA_WIDTH_A : in Integer);
+        port (DIA0: in  std_logic; DIA1: in  std_logic; 
+            DIA2: in  std_logic; DIA3: in  std_logic; 
+            DIA4: in  std_logic; DIA5: in  std_logic; 
+            DIA6: in  std_logic; DIA7: in  std_logic; 
+            DIA8: in  std_logic; DIA9: in  std_logic; 
+            DIA10: in  std_logic; DIA11: in  std_logic; 
+            DIA12: in  std_logic; DIA13: in  std_logic; 
+            DIA14: in  std_logic; DIA15: in  std_logic; 
+            DIA16: in  std_logic; DIA17: in  std_logic; 
+            ADA0: in  std_logic; ADA1: in  std_logic; 
+            ADA2: in  std_logic; ADA3: in  std_logic; 
+            ADA4: in  std_logic; ADA5: in  std_logic; 
+            ADA6: in  std_logic; ADA7: in  std_logic; 
+            ADA8: in  std_logic; ADA9: in  std_logic; 
+            ADA10: in  std_logic; ADA11: in  std_logic; 
+            ADA12: in  std_logic; ADA13: in  std_logic; 
+            CEA: in  std_logic; CLKA: in  std_logic; OCEA: in  std_logic; 
+            WEA: in  std_logic; CSA0: in  std_logic; CSA1: in  std_logic; 
+            CSA2: in  std_logic; RSTA: in  std_logic; 
+            DIB0: in  std_logic; DIB1: in  std_logic; 
+            DIB2: in  std_logic; DIB3: in  std_logic; 
+            DIB4: in  std_logic; DIB5: in  std_logic; 
+            DIB6: in  std_logic; DIB7: in  std_logic; 
+            DIB8: in  std_logic; DIB9: in  std_logic; 
+            DIB10: in  std_logic; DIB11: in  std_logic; 
+            DIB12: in  std_logic; DIB13: in  std_logic; 
+            DIB14: in  std_logic; DIB15: in  std_logic; 
+            DIB16: in  std_logic; DIB17: in  std_logic; 
+            ADB0: in  std_logic; ADB1: in  std_logic; 
+            ADB2: in  std_logic; ADB3: in  std_logic; 
+            ADB4: in  std_logic; ADB5: in  std_logic; 
+            ADB6: in  std_logic; ADB7: in  std_logic; 
+            ADB8: in  std_logic; ADB9: in  std_logic; 
+            ADB10: in  std_logic; ADB11: in  std_logic; 
+            ADB12: in  std_logic; ADB13: in  std_logic; 
+            CEB: in  std_logic; CLKB: in  std_logic; OCEB: in  std_logic; 
+            WEB: in  std_logic; CSB0: in  std_logic; CSB1: in  std_logic; 
+            CSB2: in  std_logic; RSTB: in  std_logic; 
+            DOA0: out  std_logic; DOA1: out  std_logic; 
+            DOA2: out  std_logic; DOA3: out  std_logic; 
+            DOA4: out  std_logic; DOA5: out  std_logic; 
+            DOA6: out  std_logic; DOA7: out  std_logic; 
+            DOA8: out  std_logic; DOA9: out  std_logic; 
+            DOA10: out  std_logic; DOA11: out  std_logic; 
+            DOA12: out  std_logic; DOA13: out  std_logic; 
+            DOA14: out  std_logic; DOA15: out  std_logic; 
+            DOA16: out  std_logic; DOA17: out  std_logic; 
+            DOB0: out  std_logic; DOB1: out  std_logic; 
+            DOB2: out  std_logic; DOB3: out  std_logic; 
+            DOB4: out  std_logic; DOB5: out  std_logic; 
+            DOB6: out  std_logic; DOB7: out  std_logic; 
+            DOB8: out  std_logic; DOB9: out  std_logic; 
+            DOB10: out  std_logic; DOB11: out  std_logic; 
+            DOB12: out  std_logic; DOB13: out  std_logic; 
+            DOB14: out  std_logic; DOB15: out  std_logic; 
+            DOB16: out  std_logic; DOB17: out  std_logic);
+    end component;
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute RESETMODE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_7 : label is "async_fifo_nn_4096x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_7 : label is "";
+    attribute RESETMODE of pdp_ram_0_0_7 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_0_1_6 : label is "async_fifo_nn_4096x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_1_6 : label is "";
+    attribute RESETMODE of pdp_ram_0_1_6 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_0_2_5 : label is "async_fifo_nn_4096x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_2_5 : label is "";
+    attribute RESETMODE of pdp_ram_0_2_5 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_0_3_4 : label is "async_fifo_nn_4096x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_3_4 : label is "";
+    attribute RESETMODE of pdp_ram_0_3_4 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_1_0_3 : label is "async_fifo_nn_4096x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_0_3 : label is "";
+    attribute RESETMODE of pdp_ram_1_0_3 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_1_1_2 : label is "async_fifo_nn_4096x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_1_2 : label is "";
+    attribute RESETMODE of pdp_ram_1_1_2 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_1_2_1 : label is "async_fifo_nn_4096x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_2_1 : label is "";
+    attribute RESETMODE of pdp_ram_1_2_1 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_1_3_0 : label is "async_fifo_nn_4096x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_1_3_0 : label is "";
+    attribute RESETMODE of pdp_ram_1_3_0 : label is "SYNC";
+    attribute GSR of FF_145 : label is "ENABLED";
+    attribute GSR of FF_144 : label is "ENABLED";
+    attribute GSR of FF_143 : label is "ENABLED";
+    attribute GSR of FF_142 : label is "ENABLED";
+    attribute GSR of FF_141 : label is "ENABLED";
+    attribute GSR of FF_140 : label is "ENABLED";
+    attribute GSR of FF_139 : label is "ENABLED";
+    attribute GSR of FF_138 : label is "ENABLED";
+    attribute GSR of FF_137 : label is "ENABLED";
+    attribute GSR of FF_136 : label is "ENABLED";
+    attribute GSR of FF_135 : label is "ENABLED";
+    attribute GSR of FF_134 : label is "ENABLED";
+    attribute GSR of FF_133 : label is "ENABLED";
+    attribute GSR of FF_132 : label is "ENABLED";
+    attribute GSR of FF_131 : label is "ENABLED";
+    attribute GSR of FF_130 : label is "ENABLED";
+    attribute GSR of FF_129 : label is "ENABLED";
+    attribute GSR of FF_128 : label is "ENABLED";
+    attribute GSR of FF_127 : label is "ENABLED";
+    attribute GSR of FF_126 : label is "ENABLED";
+    attribute GSR of FF_125 : label is "ENABLED";
+    attribute GSR of FF_124 : label is "ENABLED";
+    attribute GSR of FF_123 : label is "ENABLED";
+    attribute GSR of FF_122 : label is "ENABLED";
+    attribute GSR of FF_121 : label is "ENABLED";
+    attribute GSR of FF_120 : label is "ENABLED";
+    attribute GSR of FF_119 : label is "ENABLED";
+    attribute GSR of FF_118 : label is "ENABLED";
+    attribute GSR of FF_117 : label is "ENABLED";
+    attribute GSR of FF_116 : label is "ENABLED";
+    attribute GSR of FF_115 : label is "ENABLED";
+    attribute GSR of FF_114 : label is "ENABLED";
+    attribute GSR of FF_113 : label is "ENABLED";
+    attribute GSR of FF_112 : label is "ENABLED";
+    attribute GSR of FF_111 : label is "ENABLED";
+    attribute GSR of FF_110 : label is "ENABLED";
+    attribute GSR of FF_109 : label is "ENABLED";
+    attribute GSR of FF_108 : label is "ENABLED";
+    attribute GSR of FF_107 : label is "ENABLED";
+    attribute GSR of FF_106 : label is "ENABLED";
+    attribute GSR of FF_105 : label is "ENABLED";
+    attribute GSR of FF_104 : label is "ENABLED";
+    attribute GSR of FF_103 : label is "ENABLED";
+    attribute GSR of FF_102 : label is "ENABLED";
+    attribute GSR of FF_101 : label is "ENABLED";
+    attribute GSR of FF_100 : label is "ENABLED";
+    attribute GSR of FF_99 : label is "ENABLED";
+    attribute GSR of FF_98 : label is "ENABLED";
+    attribute GSR of FF_97 : label is "ENABLED";
+    attribute GSR of FF_96 : label is "ENABLED";
+    attribute GSR of FF_95 : label is "ENABLED";
+    attribute GSR of FF_94 : label is "ENABLED";
+    attribute GSR of FF_93 : label is "ENABLED";
+    attribute GSR of FF_92 : label is "ENABLED";
+    attribute GSR of FF_91 : label is "ENABLED";
+    attribute GSR of FF_90 : label is "ENABLED";
+    attribute GSR of FF_89 : label is "ENABLED";
+    attribute GSR of FF_88 : label is "ENABLED";
+    attribute GSR of FF_87 : label is "ENABLED";
+    attribute GSR of FF_86 : label is "ENABLED";
+    attribute GSR of FF_85 : label is "ENABLED";
+    attribute GSR of FF_84 : label is "ENABLED";
+    attribute GSR of FF_83 : label is "ENABLED";
+    attribute GSR of FF_82 : label is "ENABLED";
+    attribute GSR of FF_81 : label is "ENABLED";
+    attribute GSR of FF_80 : label is "ENABLED";
+    attribute GSR of FF_79 : label is "ENABLED";
+    attribute GSR of FF_78 : label is "ENABLED";
+    attribute GSR of FF_77 : label is "ENABLED";
+    attribute GSR of FF_76 : label is "ENABLED";
+    attribute GSR of FF_75 : label is "ENABLED";
+    attribute GSR of FF_74 : label is "ENABLED";
+    attribute GSR of FF_73 : label is "ENABLED";
+    attribute GSR of FF_72 : label is "ENABLED";
+    attribute GSR of FF_71 : label is "ENABLED";
+    attribute GSR of FF_70 : label is "ENABLED";
+    attribute GSR of FF_69 : label is "ENABLED";
+    attribute GSR of FF_68 : label is "ENABLED";
+    attribute GSR of FF_67 : label is "ENABLED";
+    attribute GSR of FF_66 : label is "ENABLED";
+    attribute GSR of FF_65 : label is "ENABLED";
+    attribute GSR of FF_64 : label is "ENABLED";
+    attribute GSR of FF_63 : label is "ENABLED";
+    attribute GSR of FF_62 : label is "ENABLED";
+    attribute GSR of FF_61 : label is "ENABLED";
+    attribute GSR of FF_60 : label is "ENABLED";
+    attribute GSR of FF_59 : label is "ENABLED";
+    attribute GSR of FF_58 : label is "ENABLED";
+    attribute GSR of FF_57 : label is "ENABLED";
+    attribute GSR of FF_56 : label is "ENABLED";
+    attribute GSR of FF_55 : label is "ENABLED";
+    attribute GSR of FF_54 : label is "ENABLED";
+    attribute GSR of FF_53 : label is "ENABLED";
+    attribute GSR of FF_52 : label is "ENABLED";
+    attribute GSR of FF_51 : label is "ENABLED";
+    attribute GSR of FF_50 : label is "ENABLED";
+    attribute GSR of FF_49 : label is "ENABLED";
+    attribute GSR of FF_48 : label is "ENABLED";
+    attribute GSR of FF_47 : label is "ENABLED";
+    attribute GSR of FF_46 : label is "ENABLED";
+    attribute GSR of FF_45 : label is "ENABLED";
+    attribute GSR of FF_44 : label is "ENABLED";
+    attribute GSR of FF_43 : label is "ENABLED";
+    attribute GSR of FF_42 : label is "ENABLED";
+    attribute GSR of FF_41 : label is "ENABLED";
+    attribute GSR of FF_40 : label is "ENABLED";
+    attribute GSR of FF_39 : label is "ENABLED";
+    attribute GSR of FF_38 : label is "ENABLED";
+    attribute GSR of FF_37 : label is "ENABLED";
+    attribute GSR of FF_36 : label is "ENABLED";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t27: AND2
+        port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+    INV_1: INV
+        port map (A=>full_i, Z=>invout_1);
+
+    AND2_t26: AND2
+        port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+    INV_0: INV
+        port map (A=>empty_i, Z=>invout_0);
+
+    OR2_t25: OR2
+        port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+    XOR2_t24: XOR2
+        port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+    XOR2_t23: XOR2
+        port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+    XOR2_t22: XOR2
+        port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+    XOR2_t21: XOR2
+        port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+    XOR2_t20: XOR2
+        port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+    XOR2_t19: XOR2
+        port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
+
+    XOR2_t18: XOR2
+        port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
+
+    XOR2_t17: XOR2
+        port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
+
+    XOR2_t16: XOR2
+        port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
+
+    XOR2_t15: XOR2
+        port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
+
+    XOR2_t14: XOR2
+        port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
+
+    XOR2_t13: XOR2
+        port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
+
+    XOR2_t12: XOR2
+        port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+    XOR2_t11: XOR2
+        port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+    XOR2_t10: XOR2
+        port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+    XOR2_t9: XOR2
+        port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+    XOR2_t8: XOR2
+        port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+    XOR2_t7: XOR2
+        port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
+
+    XOR2_t6: XOR2
+        port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
+
+    XOR2_t5: XOR2
+        port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
+
+    XOR2_t4: XOR2
+        port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
+
+    XOR2_t3: XOR2
+        port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
+
+    XOR2_t2: XOR2
+        port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
+
+    XOR2_t1: XOR2
+        port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
+
+    LUT4_33: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, 
+            AD1=>w_gcount_r211, AD0=>w_gcount_r212, 
+            DO0=>w_g2b_xor_cluster_0);
+
+    LUT4_32: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, 
+            AD1=>w_gcount_r27, AD0=>w_gcount_r28, 
+            DO0=>w_g2b_xor_cluster_1);
+
+    LUT4_31: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, 
+            AD1=>w_gcount_r23, AD0=>w_gcount_r24, 
+            DO0=>w_g2b_xor_cluster_2);
+
+    LUT4_30: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>wcount_r11);
+
+    LUT4_29: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, 
+            AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10);
+
+    LUT4_28: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, 
+            AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8);
+
+    LUT4_27: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, 
+            AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7);
+
+    LUT4_26: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, 
+            AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6);
+
+    LUT4_25: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5);
+
+    LUT4_24: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4);
+
+    LUT4_23: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3);
+
+    LUT4_22: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, 
+            AD1=>w_gcount_r24, AD0=>scuba_vlo, 
+            DO0=>w_g2b_xor_cluster_2_1);
+
+    LUT4_21: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2);
+
+    LUT4_20: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1);
+
+    LUT4_19: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0);
+
+    LUT4_18: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, 
+            AD1=>r_gcount_w211, AD0=>r_gcount_w212, 
+            DO0=>r_g2b_xor_cluster_0);
+
+    LUT4_17: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, 
+            AD1=>r_gcount_w27, AD0=>r_gcount_w28, 
+            DO0=>r_g2b_xor_cluster_1);
+
+    LUT4_16: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, 
+            AD1=>r_gcount_w23, AD0=>r_gcount_w24, 
+            DO0=>r_g2b_xor_cluster_2);
+
+    LUT4_15: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>rcount_w11);
+
+    LUT4_14: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, 
+            AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10);
+
+    LUT4_13: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, 
+            AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8);
+
+    LUT4_12: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, 
+            AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7);
+
+    LUT4_11: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, 
+            AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6);
+
+    LUT4_10: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5);
+
+    LUT4_9: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4);
+
+    LUT4_8: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3);
+
+    LUT4_7: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, 
+            AD1=>r_gcount_w24, AD0=>scuba_vlo, 
+            DO0=>r_g2b_xor_cluster_2_1);
+
+    LUT4_6: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2);
+
+    LUT4_5: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1);
+
+    LUT4_4: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0);
+
+    XOR2_t0: XOR2
+        port map (A=>wptr_12, B=>r_gcount_w212, Z=>wfill_sub_msb);
+
+    LUT4_3: ROM16X1A
+        generic map (initval=> X"0410")
+        port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+    LUT4_2: ROM16X1A
+        generic map (initval=> X"1004")
+        port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"0140")
+        port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, 
+            AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"4001")
+        port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, 
+            AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+    pdp_ram_0_0_7: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), 
+            DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), 
+            DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, 
+            DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, 
+            ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, 
+            ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, 
+            ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, 
+            WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>scuba_vlo, 
+            CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>scuba_vlo, 
+            CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, 
+            DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, 
+            DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, 
+            DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, 
+            DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, 
+            DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, 
+            DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, 
+            DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_0_1_6: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), 
+            DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), 
+            DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_9, 
+            DOB1=>mdout1_0_10, DOB2=>mdout1_0_11, DOB3=>mdout1_0_12, 
+            DOB4=>mdout1_0_13, DOB5=>mdout1_0_14, DOB6=>mdout1_0_15, 
+            DOB7=>mdout1_0_16, DOB8=>mdout1_0_17, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    pdp_ram_0_2_5: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20), 
+            DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23), 
+            DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_18, 
+            DOB1=>mdout1_0_19, DOB2=>mdout1_0_20, DOB3=>mdout1_0_21, 
+            DOB4=>mdout1_0_22, DOB5=>mdout1_0_23, DOB6=>mdout1_0_24, 
+            DOB7=>mdout1_0_25, DOB8=>mdout1_0_26, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    pdp_ram_0_3_4: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29), 
+            DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32), 
+            DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_27, 
+            DOB1=>mdout1_0_28, DOB2=>mdout1_0_29, DOB3=>mdout1_0_30, 
+            DOB4=>mdout1_0_31, DOB5=>mdout1_0_32, DOB6=>mdout1_0_33, 
+            DOB7=>mdout1_0_34, DOB8=>mdout1_0_35, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    pdp_ram_1_0_3: DP16KC
+        generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), 
+            DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), 
+            DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, 
+            DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, 
+            ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, 
+            ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, 
+            ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, 
+            WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>scuba_vlo, 
+            CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, 
+            ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, 
+            ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, 
+            ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, 
+            WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>scuba_vlo, 
+            CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, 
+            DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, 
+            DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, 
+            DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, 
+            DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, 
+            DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, 
+            DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, 
+            DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    pdp_ram_1_1_2: DP16KC
+        generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), 
+            DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), 
+            DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_9, 
+            DOB1=>mdout1_1_10, DOB2=>mdout1_1_11, DOB3=>mdout1_1_12, 
+            DOB4=>mdout1_1_13, DOB5=>mdout1_1_14, DOB6=>mdout1_1_15, 
+            DOB7=>mdout1_1_16, DOB8=>mdout1_1_17, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    pdp_ram_1_2_1: DP16KC
+        generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20), 
+            DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23), 
+            DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_18, 
+            DOB1=>mdout1_1_19, DOB2=>mdout1_1_20, DOB3=>mdout1_1_21, 
+            DOB4=>mdout1_1_22, DOB5=>mdout1_1_23, DOB6=>mdout1_1_24, 
+            DOB7=>mdout1_1_25, DOB8=>mdout1_1_26, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    pdp_ram_1_3_0: DP16KC
+        generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29), 
+            DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32), 
+            DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35), 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, 
+            ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, 
+            ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, 
+            ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, 
+            CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_11, 
+            CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, 
+            DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, 
+            DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, 
+            DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, 
+            DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, 
+            DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, 
+            DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, 
+            ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, 
+            ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, 
+            ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, 
+            ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, 
+            CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, 
+            CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, 
+            DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, 
+            DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, 
+            DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, 
+            DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_27, 
+            DOB1=>mdout1_1_28, DOB2=>mdout1_1_29, DOB3=>mdout1_1_30, 
+            DOB4=>mdout1_1_31, DOB5=>mdout1_1_32, DOB6=>mdout1_1_33, 
+            DOB7=>mdout1_1_34, DOB8=>mdout1_1_35, DOB9=>open, 
+            DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, 
+            DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+    FF_145: FD1P3BX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>wcount_0);
+
+    FF_144: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_143: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_142: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_141: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_140: FD1P3DX
+        port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_139: FD1P3DX
+        port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_6);
+
+    FF_138: FD1P3DX
+        port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_7);
+
+    FF_137: FD1P3DX
+        port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_8);
+
+    FF_136: FD1P3DX
+        port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_9);
+
+    FF_135: FD1P3DX
+        port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_10);
+
+    FF_134: FD1P3DX
+        port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_11);
+
+    FF_133: FD1P3DX
+        port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_12);
+
+    FF_132: FD1P3DX
+        port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_0);
+
+    FF_131: FD1P3DX
+        port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_1);
+
+    FF_130: FD1P3DX
+        port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_2);
+
+    FF_129: FD1P3DX
+        port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_3);
+
+    FF_128: FD1P3DX
+        port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_4);
+
+    FF_127: FD1P3DX
+        port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_5);
+
+    FF_126: FD1P3DX
+        port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_6);
+
+    FF_125: FD1P3DX
+        port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_7);
+
+    FF_124: FD1P3DX
+        port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_8);
+
+    FF_123: FD1P3DX
+        port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_9);
+
+    FF_122: FD1P3DX
+        port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_10);
+
+    FF_121: FD1P3DX
+        port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_11);
+
+    FF_120: FD1P3DX
+        port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_12);
+
+    FF_119: FD1P3DX
+        port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_0);
+
+    FF_118: FD1P3DX
+        port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_1);
+
+    FF_117: FD1P3DX
+        port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_2);
+
+    FF_116: FD1P3DX
+        port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_3);
+
+    FF_115: FD1P3DX
+        port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_4);
+
+    FF_114: FD1P3DX
+        port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_5);
+
+    FF_113: FD1P3DX
+        port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_6);
+
+    FF_112: FD1P3DX
+        port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_7);
+
+    FF_111: FD1P3DX
+        port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_8);
+
+    FF_110: FD1P3DX
+        port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_9);
+
+    FF_109: FD1P3DX
+        port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_10);
+
+    FF_108: FD1P3DX
+        port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_11);
+
+    FF_107: FD1P3DX
+        port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_12);
+
+    FF_106: FD1P3BX
+        port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, 
+            Q=>rcount_0);
+
+    FF_105: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_1);
+
+    FF_104: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_2);
+
+    FF_103: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_3);
+
+    FF_102: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_4);
+
+    FF_101: FD1P3DX
+        port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_5);
+
+    FF_100: FD1P3DX
+        port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_6);
+
+    FF_99: FD1P3DX
+        port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_7);
+
+    FF_98: FD1P3DX
+        port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_8);
+
+    FF_97: FD1P3DX
+        port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_9);
+
+    FF_96: FD1P3DX
+        port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_10);
+
+    FF_95: FD1P3DX
+        port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_11);
+
+    FF_94: FD1P3DX
+        port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_12);
+
+    FF_93: FD1P3DX
+        port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_0);
+
+    FF_92: FD1P3DX
+        port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_1);
+
+    FF_91: FD1P3DX
+        port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_2);
+
+    FF_90: FD1P3DX
+        port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_3);
+
+    FF_89: FD1P3DX
+        port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_4);
+
+    FF_88: FD1P3DX
+        port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_5);
+
+    FF_87: FD1P3DX
+        port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_6);
+
+    FF_86: FD1P3DX
+        port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_7);
+
+    FF_85: FD1P3DX
+        port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_8);
+
+    FF_84: FD1P3DX
+        port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_9);
+
+    FF_83: FD1P3DX
+        port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_10);
+
+    FF_82: FD1P3DX
+        port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_11);
+
+    FF_81: FD1P3DX
+        port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_12);
+
+    FF_80: FD1P3DX
+        port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_0);
+
+    FF_79: FD1P3DX
+        port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_1);
+
+    FF_78: FD1P3DX
+        port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_2);
+
+    FF_77: FD1P3DX
+        port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_3);
+
+    FF_76: FD1P3DX
+        port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_4);
+
+    FF_75: FD1P3DX
+        port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_5);
+
+    FF_74: FD1P3DX
+        port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_6);
+
+    FF_73: FD1P3DX
+        port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_7);
+
+    FF_72: FD1P3DX
+        port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_8);
+
+    FF_71: FD1P3DX
+        port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_9);
+
+    FF_70: FD1P3DX
+        port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_10);
+
+    FF_69: FD1P3DX
+        port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_11);
+
+    FF_68: FD1P3DX
+        port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_12);
+
+    FF_67: FD1P3DX
+        port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, 
+            Q=>rptr_11_ff);
+
+    FF_66: FD1S3DX
+        port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+    FF_65: FD1S3DX
+        port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+    FF_64: FD1S3DX
+        port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+    FF_63: FD1S3DX
+        port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+    FF_62: FD1S3DX
+        port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+    FF_61: FD1S3DX
+        port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+    FF_60: FD1S3DX
+        port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
+
+    FF_59: FD1S3DX
+        port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
+
+    FF_58: FD1S3DX
+        port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
+
+    FF_57: FD1S3DX
+        port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
+
+    FF_56: FD1S3DX
+        port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r10);
+
+    FF_55: FD1S3DX
+        port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r11);
+
+    FF_54: FD1S3DX
+        port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r12);
+
+    FF_53: FD1S3DX
+        port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+    FF_52: FD1S3DX
+        port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+    FF_51: FD1S3DX
+        port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+    FF_50: FD1S3DX
+        port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+    FF_49: FD1S3DX
+        port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+    FF_48: FD1S3DX
+        port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+    FF_47: FD1S3DX
+        port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+    FF_46: FD1S3DX
+        port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
+
+    FF_45: FD1S3DX
+        port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
+
+    FF_44: FD1S3DX
+        port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
+
+    FF_43: FD1S3DX
+        port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
+
+    FF_42: FD1S3DX
+        port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
+
+    FF_41: FD1S3DX
+        port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
+
+    FF_40: FD1S3DX
+        port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r20);
+
+    FF_39: FD1S3DX
+        port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r21);
+
+    FF_38: FD1S3DX
+        port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r22);
+
+    FF_37: FD1S3DX
+        port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r23);
+
+    FF_36: FD1S3DX
+        port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r24);
+
+    FF_35: FD1S3DX
+        port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r25);
+
+    FF_34: FD1S3DX
+        port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r26);
+
+    FF_33: FD1S3DX
+        port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r27);
+
+    FF_32: FD1S3DX
+        port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r28);
+
+    FF_31: FD1S3DX
+        port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r29);
+
+    FF_30: FD1S3DX
+        port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r210);
+
+    FF_29: FD1S3DX
+        port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r211);
+
+    FF_28: FD1S3DX
+        port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r212);
+
+    FF_27: FD1S3DX
+        port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+    FF_26: FD1S3DX
+        port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+    FF_25: FD1S3DX
+        port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+    FF_24: FD1S3DX
+        port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+    FF_23: FD1S3DX
+        port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+    FF_22: FD1S3DX
+        port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+    FF_21: FD1S3DX
+        port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
+
+    FF_20: FD1S3DX
+        port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
+
+    FF_19: FD1S3DX
+        port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
+
+    FF_18: FD1S3DX
+        port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
+
+    FF_17: FD1S3DX
+        port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, 
+            Q=>r_gcount_w210);
+
+    FF_16: FD1S3DX
+        port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, 
+            Q=>r_gcount_w211);
+
+    FF_15: FD1S3DX
+        port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, 
+            Q=>r_gcount_w212);
+
+    FF_14: FD1S3DX
+        port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0));
+
+    FF_13: FD1S3DX
+        port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1));
+
+    FF_12: FD1S3DX
+        port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2));
+
+    FF_11: FD1S3DX
+        port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3));
+
+    FF_10: FD1S3DX
+        port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4));
+
+    FF_9: FD1S3DX
+        port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5));
+
+    FF_8: FD1S3DX
+        port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6));
+
+    FF_7: FD1S3DX
+        port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7));
+
+    FF_6: FD1S3DX
+        port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8));
+
+    FF_5: FD1S3DX
+        port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9));
+
+    FF_4: FD1S3DX
+        port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10));
+
+    FF_3: FD1S3DX
+        port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11));
+
+    FF_2: FD1S3DX
+        port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12));
+
+    FF_1: FD1S3BX
+        port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+    FF_0: FD1S3DX
+        port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+    w_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, 
+            S1=>open);
+
+    w_gctr_0: CU2
+        port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, 
+            NC0=>iwcount_0, NC1=>iwcount_1);
+
+    w_gctr_1: CU2
+        port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, 
+            NC0=>iwcount_2, NC1=>iwcount_3);
+
+    w_gctr_2: CU2
+        port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, 
+            NC0=>iwcount_4, NC1=>iwcount_5);
+
+    w_gctr_3: CU2
+        port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, 
+            NC0=>iwcount_6, NC1=>iwcount_7);
+
+    w_gctr_4: CU2
+        port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, 
+            NC0=>iwcount_8, NC1=>iwcount_9);
+
+    w_gctr_5: CU2
+        port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, 
+            NC0=>iwcount_10, NC1=>iwcount_11);
+
+    w_gctr_6: CU2
+        port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6, 
+            NC0=>iwcount_12, NC1=>open);
+
+    r_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, 
+            S1=>open);
+
+    r_gctr_0: CU2
+        port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, 
+            NC0=>ircount_0, NC1=>ircount_1);
+
+    r_gctr_1: CU2
+        port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, 
+            NC0=>ircount_2, NC1=>ircount_3);
+
+    r_gctr_2: CU2
+        port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, 
+            NC0=>ircount_4, NC1=>ircount_5);
+
+    r_gctr_3: CU2
+        port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, 
+            NC0=>ircount_6, NC1=>ircount_7);
+
+    r_gctr_4: CU2
+        port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, 
+            NC0=>ircount_8, NC1=>ircount_9);
+
+    r_gctr_5: CU2
+        port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, 
+            NC0=>ircount_10, NC1=>ircount_11);
+
+    r_gctr_6: CU2
+        port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1, 
+            NC0=>ircount_12, NC1=>open);
+
+    mux_35: MUX21
+        port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>rptr_11_ff, 
+            Z=>Q(0));
+
+    mux_34: MUX21
+        port map (D0=>mdout1_0_1, D1=>mdout1_1_1, SD=>rptr_11_ff, 
+            Z=>Q(1));
+
+    mux_33: MUX21
+        port map (D0=>mdout1_0_2, D1=>mdout1_1_2, SD=>rptr_11_ff, 
+            Z=>Q(2));
+
+    mux_32: MUX21
+        port map (D0=>mdout1_0_3, D1=>mdout1_1_3, SD=>rptr_11_ff, 
+            Z=>Q(3));
+
+    mux_31: MUX21
+        port map (D0=>mdout1_0_4, D1=>mdout1_1_4, SD=>rptr_11_ff, 
+            Z=>Q(4));
+
+    mux_30: MUX21
+        port map (D0=>mdout1_0_5, D1=>mdout1_1_5, SD=>rptr_11_ff, 
+            Z=>Q(5));
+
+    mux_29: MUX21
+        port map (D0=>mdout1_0_6, D1=>mdout1_1_6, SD=>rptr_11_ff, 
+            Z=>Q(6));
+
+    mux_28: MUX21
+        port map (D0=>mdout1_0_7, D1=>mdout1_1_7, SD=>rptr_11_ff, 
+            Z=>Q(7));
+
+    mux_27: MUX21
+        port map (D0=>mdout1_0_8, D1=>mdout1_1_8, SD=>rptr_11_ff, 
+            Z=>Q(8));
+
+    mux_26: MUX21
+        port map (D0=>mdout1_0_9, D1=>mdout1_1_9, SD=>rptr_11_ff, 
+            Z=>Q(9));
+
+    mux_25: MUX21
+        port map (D0=>mdout1_0_10, D1=>mdout1_1_10, SD=>rptr_11_ff, 
+            Z=>Q(10));
+
+    mux_24: MUX21
+        port map (D0=>mdout1_0_11, D1=>mdout1_1_11, SD=>rptr_11_ff, 
+            Z=>Q(11));
+
+    mux_23: MUX21
+        port map (D0=>mdout1_0_12, D1=>mdout1_1_12, SD=>rptr_11_ff, 
+            Z=>Q(12));
+
+    mux_22: MUX21
+        port map (D0=>mdout1_0_13, D1=>mdout1_1_13, SD=>rptr_11_ff, 
+            Z=>Q(13));
+
+    mux_21: MUX21
+        port map (D0=>mdout1_0_14, D1=>mdout1_1_14, SD=>rptr_11_ff, 
+            Z=>Q(14));
+
+    mux_20: MUX21
+        port map (D0=>mdout1_0_15, D1=>mdout1_1_15, SD=>rptr_11_ff, 
+            Z=>Q(15));
+
+    mux_19: MUX21
+        port map (D0=>mdout1_0_16, D1=>mdout1_1_16, SD=>rptr_11_ff, 
+            Z=>Q(16));
+
+    mux_18: MUX21
+        port map (D0=>mdout1_0_17, D1=>mdout1_1_17, SD=>rptr_11_ff, 
+            Z=>Q(17));
+
+    mux_17: MUX21
+        port map (D0=>mdout1_0_18, D1=>mdout1_1_18, SD=>rptr_11_ff, 
+            Z=>Q(18));
+
+    mux_16: MUX21
+        port map (D0=>mdout1_0_19, D1=>mdout1_1_19, SD=>rptr_11_ff, 
+            Z=>Q(19));
+
+    mux_15: MUX21
+        port map (D0=>mdout1_0_20, D1=>mdout1_1_20, SD=>rptr_11_ff, 
+            Z=>Q(20));
+
+    mux_14: MUX21
+        port map (D0=>mdout1_0_21, D1=>mdout1_1_21, SD=>rptr_11_ff, 
+            Z=>Q(21));
+
+    mux_13: MUX21
+        port map (D0=>mdout1_0_22, D1=>mdout1_1_22, SD=>rptr_11_ff, 
+            Z=>Q(22));
+
+    mux_12: MUX21
+        port map (D0=>mdout1_0_23, D1=>mdout1_1_23, SD=>rptr_11_ff, 
+            Z=>Q(23));
+
+    mux_11: MUX21
+        port map (D0=>mdout1_0_24, D1=>mdout1_1_24, SD=>rptr_11_ff, 
+            Z=>Q(24));
+
+    mux_10: MUX21
+        port map (D0=>mdout1_0_25, D1=>mdout1_1_25, SD=>rptr_11_ff, 
+            Z=>Q(25));
+
+    mux_9: MUX21
+        port map (D0=>mdout1_0_26, D1=>mdout1_1_26, SD=>rptr_11_ff, 
+            Z=>Q(26));
+
+    mux_8: MUX21
+        port map (D0=>mdout1_0_27, D1=>mdout1_1_27, SD=>rptr_11_ff, 
+            Z=>Q(27));
+
+    mux_7: MUX21
+        port map (D0=>mdout1_0_28, D1=>mdout1_1_28, SD=>rptr_11_ff, 
+            Z=>Q(28));
+
+    mux_6: MUX21
+        port map (D0=>mdout1_0_29, D1=>mdout1_1_29, SD=>rptr_11_ff, 
+            Z=>Q(29));
+
+    mux_5: MUX21
+        port map (D0=>mdout1_0_30, D1=>mdout1_1_30, SD=>rptr_11_ff, 
+            Z=>Q(30));
+
+    mux_4: MUX21
+        port map (D0=>mdout1_0_31, D1=>mdout1_1_31, SD=>rptr_11_ff, 
+            Z=>Q(31));
+
+    mux_3: MUX21
+        port map (D0=>mdout1_0_32, D1=>mdout1_1_32, SD=>rptr_11_ff, 
+            Z=>Q(32));
+
+    mux_2: MUX21
+        port map (D0=>mdout1_0_33, D1=>mdout1_1_33, SD=>rptr_11_ff, 
+            Z=>Q(33));
+
+    mux_1: MUX21
+        port map (D0=>mdout1_0_34, D1=>mdout1_1_34, SD=>rptr_11_ff, 
+            Z=>Q(34));
+
+    mux_0: MUX21
+        port map (D0=>mdout1_0_35, D1=>mdout1_1_35, SD=>rptr_11_ff, 
+            Z=>Q(35));
+
+    precin_inst422: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin, S0=>open, 
+            S1=>open);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    wfill_0: FSUB2B
+        port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo, 
+            B1=>rcount_w0, BI=>precin, BOUT=>co0_2, S0=>open, 
+            S1=>wfill_sub_0);
+
+    wfill_1: FSUB2B
+        port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w1, B1=>rcount_w2, 
+            BI=>co0_2, BOUT=>co1_2, S0=>wfill_sub_1, S1=>wfill_sub_2);
+
+    wfill_2: FSUB2B
+        port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w3, B1=>rcount_w4, 
+            BI=>co1_2, BOUT=>co2_2, S0=>wfill_sub_3, S1=>wfill_sub_4);
+
+    wfill_3: FSUB2B
+        port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w5, B1=>rcount_w6, 
+            BI=>co2_2, BOUT=>co3_2, S0=>wfill_sub_5, S1=>wfill_sub_6);
+
+    wfill_4: FSUB2B
+        port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w7, B1=>rcount_w8, 
+            BI=>co3_2, BOUT=>co4_2, S0=>wfill_sub_7, S1=>wfill_sub_8);
+
+    wfill_5: FSUB2B
+        port map (A0=>wptr_9, A1=>wptr_10, B0=>r_g2b_xor_cluster_0, 
+            B1=>rcount_w10, BI=>co4_2, BOUT=>co5_2, S0=>wfill_sub_9, 
+            S1=>wfill_sub_10);
+
+    wfill_6: FSUB2B
+        port map (A0=>wptr_11, A1=>wfill_sub_msb, B0=>rcount_w11, 
+            B1=>scuba_vlo, BI=>co5_2, BOUT=>co6_2, S0=>wfill_sub_11, 
+            S1=>wfill_sub_12);
+
+    wfilld: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>co6_2, COUT=>open, S0=>co6_2d, S1=>open);
+
+    empty_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+    empty_cmp_0: AGEB2
+        port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, 
+            B1=>wcount_r1, CI=>cmp_ci, GE=>co0_3);
+
+    empty_cmp_1: AGEB2
+        port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, 
+            B1=>wcount_r3, CI=>co0_3, GE=>co1_3);
+
+    empty_cmp_2: AGEB2
+        port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, 
+            B1=>wcount_r5, CI=>co1_3, GE=>co2_3);
+
+    empty_cmp_3: AGEB2
+        port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, 
+            B1=>wcount_r7, CI=>co2_3, GE=>co3_3);
+
+    empty_cmp_4: AGEB2
+        port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, 
+            B1=>w_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3);
+
+    empty_cmp_5: AGEB2
+        port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, 
+            B1=>wcount_r11, CI=>co4_3, GE=>co5_3);
+
+    empty_cmp_6: AGEB2
+        port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, 
+            B1=>scuba_vlo, CI=>co5_3, GE=>empty_d_c);
+
+    a0: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, 
+            S1=>open);
+
+    full_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+    full_cmp_0: AGEB2
+        port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, 
+            B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_4);
+
+    full_cmp_1: AGEB2
+        port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, 
+            B1=>rcount_w3, CI=>co0_4, GE=>co1_4);
+
+    full_cmp_2: AGEB2
+        port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, 
+            B1=>rcount_w5, CI=>co1_4, GE=>co2_4);
+
+    full_cmp_3: AGEB2
+        port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, 
+            B1=>rcount_w7, CI=>co2_4, GE=>co3_4);
+
+    full_cmp_4: AGEB2
+        port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, 
+            B1=>r_g2b_xor_cluster_0, CI=>co3_4, GE=>co4_4);
+
+    full_cmp_5: AGEB2
+        port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, 
+            B1=>rcount_w11, CI=>co4_4, GE=>co5_4);
+
+    full_cmp_6: AGEB2
+        port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, 
+            B1=>scuba_vlo, CI=>co5_4, GE=>full_d_c);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    a1: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, 
+            S1=>open);
+
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of async_fifo_nn_4096x36_ecp3 is
+    for Structure
+        for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+        for all:AND2 use entity ecp3.AND2(V); end for;
+        for all:CU2 use entity ecp3.CU2(V); end for;
+        for all:FADD2B use entity ecp3.FADD2B(V); end for;
+        for all:FSUB2B use entity ecp3.FSUB2B(V); end for;
+        for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
+        for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+        for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+        for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+        for all:INV use entity ecp3.INV(V); end for;
+        for all:MUX21 use entity ecp3.MUX21(V); end for;
+        for all:OR2 use entity ecp3.OR2(V); end for;
+        for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+        for all:VHI use entity ecp3.VHI(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+        for all:XOR2 use entity ecp3.XOR2(V); end for;
+        for all:DP16KC use entity ecp3.DP16KC(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x36_ecp3_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x36_ecp3_tmpl.vhd
new file mode 100644
index 0000000..28f62b5
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_4096x36_ecp3_tmpl.vhd
@@ -0,0 +1,19 @@
+-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.7
+-- Thu Sep 18 10:10:35 2014
+
+-- parameterized module component declaration
+component async_fifo_nn_4096x36_ecp3
+    port (Data: in  std_logic_vector(35 downto 0); 
+        WrClock: in  std_logic; RdClock: in  std_logic; 
+        WrEn: in  std_logic; RdEn: in  std_logic; Reset: in  std_logic; 
+        RPReset: in  std_logic; Q: out  std_logic_vector(35 downto 0); 
+        WCNT: out  std_logic_vector(12 downto 0); Empty: out  std_logic; 
+        Full: out  std_logic);
+end component;
+
+-- parameterized module component instance
+__ : async_fifo_nn_4096x36_ecp3
+    port map (Data(35 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, 
+        RdEn=>__, Reset=>__, RPReset=>__, Q(35 downto 0)=>__, WCNT(12 downto 0)=>__, 
+        Empty=>__, Full=>__);
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_nn_th_512x36_ecp3.ipx b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_th_512x36_ecp3.ipx
new file mode 100644
index 0000000..535788b
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_th_512x36_ecp3.ipx
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="async_fifo_nn_th_512x36_ecp3" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 07 12 14:33:54.121" version="5.4" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="async_fifo_nn_th_512x36_ecp3.lpc" type="lpc" modified="2013 07 12 14:33:50.205"/>
+		<File name="async_fifo_nn_th_512x36_ecp3.vhd" type="top_level_vhdl" modified="2013 07 12 14:33:50.284"/>
+		<File name="async_fifo_nn_th_512x36_ecp3_tmpl.vhd" type="template_vhdl" modified="2013 07 12 14:33:50.285"/>
+		<File name="tb_async_fifo_nn_th_512x36_ecp3_tmpl.vhd" type="testbench_vhdl" modified="2013 07 12 14:33:50.335"/>
+  </Package>
+</DiamondModule>
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_nn_th_512x36_ecp3.lpc b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_th_512x36_ecp3.lpc
new file mode 100644
index 0000000..c19b7cf
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_th_512x36_ecp3.lpc
@@ -0,0 +1,47 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.4
+ModuleName=async_fifo_nn_th_512x36_ecp3
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=07/12/2013
+Time=14:33:50
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=512
+Width=36
+RDepth=512
+RWidth=36
+regout=0
+CtrlByRdEn=0
+EmpFlg=1
+PeMode=Static - Single Threshold
+PeAssert=128
+PeDeassert=130
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=1
+WDataCount=0
+EnECC=0
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_nn_th_512x36_ecp3.vhd b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_th_512x36_ecp3.vhd
new file mode 100644
index 0000000..7a24b4c
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_th_512x36_ecp3.vhd
@@ -0,0 +1,1444 @@
+-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
+-- Module  Version: 5.4
+--C:\lscc\diamond\2.1_x64\ispfpga\bin\nt64\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 36 -depth 512 -rdata_width 36 -no_enable -pe 128 -pf -1 -rfill -e 
+
+-- Fri Jul 12 14:33:50 2013
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity async_fifo_nn_th_512x36_ecp3 is
+    port (
+        Data: in  std_logic_vector(35 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(35 downto 0); 
+        RCNT: out  std_logic_vector(9 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostEmpty: out  std_logic);
+end async_fifo_nn_th_512x36_ecp3;
+
+architecture Structure of async_fifo_nn_th_512x36_ecp3 is
+
+    -- internal signal declarations
+    signal invout_1: std_logic;
+    signal invout_0: std_logic;
+    signal w_g2b_xor_cluster_1: std_logic;
+    signal r_g2b_xor_cluster_1: std_logic;
+    signal w_gdata_0: std_logic;
+    signal w_gdata_1: std_logic;
+    signal w_gdata_2: std_logic;
+    signal w_gdata_3: std_logic;
+    signal w_gdata_4: std_logic;
+    signal w_gdata_5: std_logic;
+    signal w_gdata_6: std_logic;
+    signal w_gdata_7: std_logic;
+    signal w_gdata_8: std_logic;
+    signal wptr_0: std_logic;
+    signal wptr_1: std_logic;
+    signal wptr_2: std_logic;
+    signal wptr_3: std_logic;
+    signal wptr_4: std_logic;
+    signal wptr_5: std_logic;
+    signal wptr_6: std_logic;
+    signal wptr_7: std_logic;
+    signal wptr_8: std_logic;
+    signal wptr_9: std_logic;
+    signal r_gdata_0: std_logic;
+    signal r_gdata_1: std_logic;
+    signal r_gdata_2: std_logic;
+    signal r_gdata_3: std_logic;
+    signal r_gdata_4: std_logic;
+    signal r_gdata_5: std_logic;
+    signal r_gdata_6: std_logic;
+    signal r_gdata_7: std_logic;
+    signal r_gdata_8: std_logic;
+    signal rptr_9: std_logic;
+    signal w_gcount_0: std_logic;
+    signal w_gcount_1: std_logic;
+    signal w_gcount_2: std_logic;
+    signal w_gcount_3: std_logic;
+    signal w_gcount_4: std_logic;
+    signal w_gcount_5: std_logic;
+    signal w_gcount_6: std_logic;
+    signal w_gcount_7: std_logic;
+    signal w_gcount_8: std_logic;
+    signal w_gcount_9: std_logic;
+    signal r_gcount_0: std_logic;
+    signal r_gcount_1: std_logic;
+    signal r_gcount_2: std_logic;
+    signal r_gcount_3: std_logic;
+    signal r_gcount_4: std_logic;
+    signal r_gcount_5: std_logic;
+    signal r_gcount_6: std_logic;
+    signal r_gcount_7: std_logic;
+    signal r_gcount_8: std_logic;
+    signal r_gcount_9: std_logic;
+    signal w_gcount_r20: std_logic;
+    signal w_gcount_r0: std_logic;
+    signal w_gcount_r21: std_logic;
+    signal w_gcount_r1: std_logic;
+    signal w_gcount_r22: std_logic;
+    signal w_gcount_r2: std_logic;
+    signal w_gcount_r23: std_logic;
+    signal w_gcount_r3: std_logic;
+    signal w_gcount_r24: std_logic;
+    signal w_gcount_r4: std_logic;
+    signal w_gcount_r25: std_logic;
+    signal w_gcount_r5: std_logic;
+    signal w_gcount_r26: std_logic;
+    signal w_gcount_r6: std_logic;
+    signal w_gcount_r27: std_logic;
+    signal w_gcount_r7: std_logic;
+    signal w_gcount_r28: std_logic;
+    signal w_gcount_r8: std_logic;
+    signal w_gcount_r29: std_logic;
+    signal w_gcount_r9: std_logic;
+    signal r_gcount_w20: std_logic;
+    signal r_gcount_w0: std_logic;
+    signal r_gcount_w21: std_logic;
+    signal r_gcount_w1: std_logic;
+    signal r_gcount_w22: std_logic;
+    signal r_gcount_w2: std_logic;
+    signal r_gcount_w23: std_logic;
+    signal r_gcount_w3: std_logic;
+    signal r_gcount_w24: std_logic;
+    signal r_gcount_w4: std_logic;
+    signal r_gcount_w25: std_logic;
+    signal r_gcount_w5: std_logic;
+    signal r_gcount_w26: std_logic;
+    signal r_gcount_w6: std_logic;
+    signal r_gcount_w27: std_logic;
+    signal r_gcount_w7: std_logic;
+    signal r_gcount_w28: std_logic;
+    signal r_gcount_w8: std_logic;
+    signal r_gcount_w29: std_logic;
+    signal r_gcount_w9: std_logic;
+    signal empty_i: std_logic;
+    signal full_i: std_logic;
+    signal rRst: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_gctr_ci: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co0: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal co1: std_logic;
+    signal iwcount_6: std_logic;
+    signal iwcount_7: std_logic;
+    signal co2: std_logic;
+    signal iwcount_8: std_logic;
+    signal iwcount_9: std_logic;
+    signal co4: std_logic;
+    signal wcount_9: std_logic;
+    signal co3: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_gctr_ci: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co0_1: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal co1_1: std_logic;
+    signal ircount_6: std_logic;
+    signal ircount_7: std_logic;
+    signal co2_1: std_logic;
+    signal ircount_8: std_logic;
+    signal ircount_9: std_logic;
+    signal co4_1: std_logic;
+    signal rcount_9: std_logic;
+    signal co3_1: std_logic;
+    signal rfill_sub_0: std_logic;
+    signal rptr_0: std_logic;
+    signal rfill_sub_1: std_logic;
+    signal rfill_sub_2: std_logic;
+    signal co0_2: std_logic;
+    signal rptr_1: std_logic;
+    signal rptr_2: std_logic;
+    signal rfill_sub_3: std_logic;
+    signal rfill_sub_4: std_logic;
+    signal co1_2: std_logic;
+    signal rptr_3: std_logic;
+    signal rptr_4: std_logic;
+    signal rfill_sub_5: std_logic;
+    signal rfill_sub_6: std_logic;
+    signal co2_2: std_logic;
+    signal rptr_5: std_logic;
+    signal rptr_6: std_logic;
+    signal rfill_sub_7: std_logic;
+    signal rfill_sub_8: std_logic;
+    signal co3_2: std_logic;
+    signal rptr_7: std_logic;
+    signal rptr_8: std_logic;
+    signal rfill_sub_9: std_logic;
+    signal co4_2: std_logic;
+    signal rfill_sub_msb: std_logic;
+    signal cmp_ci: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal co0_3: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal co1_3: std_logic;
+    signal rcount_4: std_logic;
+    signal rcount_5: std_logic;
+    signal co2_3: std_logic;
+    signal rcount_6: std_logic;
+    signal rcount_7: std_logic;
+    signal co3_3: std_logic;
+    signal empty_cmp_clr: std_logic;
+    signal rcount_8: std_logic;
+    signal empty_cmp_set: std_logic;
+    signal empty_d: std_logic;
+    signal empty_d_c: std_logic;
+    signal wren_i: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal rcount_w0: std_logic;
+    signal rcount_w1: std_logic;
+    signal wcount_0: std_logic;
+    signal wcount_1: std_logic;
+    signal co0_4: std_logic;
+    signal rcount_w2: std_logic;
+    signal rcount_w3: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_3: std_logic;
+    signal co1_4: std_logic;
+    signal rcount_w4: std_logic;
+    signal rcount_w5: std_logic;
+    signal wcount_4: std_logic;
+    signal wcount_5: std_logic;
+    signal co2_4: std_logic;
+    signal r_g2b_xor_cluster_0: std_logic;
+    signal rcount_w7: std_logic;
+    signal wcount_6: std_logic;
+    signal wcount_7: std_logic;
+    signal co3_4: std_logic;
+    signal rcount_w8: std_logic;
+    signal full_cmp_clr: std_logic;
+    signal wcount_8: std_logic;
+    signal full_cmp_set: std_logic;
+    signal full_d: std_logic;
+    signal full_d_c: std_logic;
+    signal scuba_vhi: std_logic;
+    signal iae_setcount_0: std_logic;
+    signal iae_setcount_1: std_logic;
+    signal ae_set_ctr_ci: std_logic;
+    signal iae_setcount_2: std_logic;
+    signal iae_setcount_3: std_logic;
+    signal co0_5: std_logic;
+    signal iae_setcount_4: std_logic;
+    signal iae_setcount_5: std_logic;
+    signal co1_5: std_logic;
+    signal iae_setcount_6: std_logic;
+    signal iae_setcount_7: std_logic;
+    signal co2_5: std_logic;
+    signal iae_setcount_8: std_logic;
+    signal iae_setcount_9: std_logic;
+    signal co4_3: std_logic;
+    signal ae_setcount_9: std_logic;
+    signal co3_5: std_logic;
+    signal rden_i: std_logic;
+    signal cmp_ci_2: std_logic;
+    signal wcount_r0: std_logic;
+    signal wcount_r1: std_logic;
+    signal ae_setcount_0: std_logic;
+    signal ae_setcount_1: std_logic;
+    signal co0_6: std_logic;
+    signal wcount_r2: std_logic;
+    signal wcount_r3: std_logic;
+    signal ae_setcount_2: std_logic;
+    signal ae_setcount_3: std_logic;
+    signal co1_6: std_logic;
+    signal wcount_r4: std_logic;
+    signal wcount_r5: std_logic;
+    signal ae_setcount_4: std_logic;
+    signal ae_setcount_5: std_logic;
+    signal co2_6: std_logic;
+    signal w_g2b_xor_cluster_0: std_logic;
+    signal wcount_r7: std_logic;
+    signal ae_setcount_6: std_logic;
+    signal ae_setcount_7: std_logic;
+    signal co3_6: std_logic;
+    signal wcount_r8: std_logic;
+    signal ae_set_cmp_clr: std_logic;
+    signal ae_setcount_8: std_logic;
+    signal ae_set_cmp_set: std_logic;
+    signal ae_set_d: std_logic;
+    signal ae_set_d_c: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component AGEB2
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; GE: out  std_logic);
+    end component;
+    component AND2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component CU2
+        port (CI: in  std_logic; PC0: in  std_logic; PC1: in  std_logic; 
+            CO: out  std_logic; NC0: out  std_logic; NC1: out  std_logic);
+    end component;
+    component FADD2B
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; COUT: out  std_logic; 
+            S0: out  std_logic; S1: out  std_logic);
+    end component;
+    component FSUB2B
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; BI: in  std_logic; BOUT: out  std_logic; 
+            S0: out  std_logic; S1: out  std_logic);
+    end component;
+    component FD1P3BX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            PD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1P3DX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            CD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1S3BX
+        port (D: in  std_logic; CK: in  std_logic; PD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component FD1S3DX
+        port (D: in  std_logic; CK: in  std_logic; CD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component INV
+        port (A: in  std_logic; Z: out  std_logic);
+    end component;
+    component OR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component ROM16X1A
+        generic (INITVAL : in std_logic_vector(15 downto 0));
+        port (AD3: in  std_logic; AD2: in  std_logic; AD1: in  std_logic; 
+            AD0: in  std_logic; DO0: out  std_logic);
+    end component;
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component XOR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component PDPW16KC
+        generic (GSR : in String; CSDECODE_R : in String; 
+                CSDECODE_W : in String; REGMODE : in String; 
+                DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+        port (DI0: in  std_logic; DI1: in  std_logic; DI2: in  std_logic; 
+            DI3: in  std_logic; DI4: in  std_logic; DI5: in  std_logic; 
+            DI6: in  std_logic; DI7: in  std_logic; DI8: in  std_logic; 
+            DI9: in  std_logic; DI10: in  std_logic; DI11: in  std_logic; 
+            DI12: in  std_logic; DI13: in  std_logic; 
+            DI14: in  std_logic; DI15: in  std_logic; 
+            DI16: in  std_logic; DI17: in  std_logic; 
+            DI18: in  std_logic; DI19: in  std_logic; 
+            DI20: in  std_logic; DI21: in  std_logic; 
+            DI22: in  std_logic; DI23: in  std_logic; 
+            DI24: in  std_logic; DI25: in  std_logic; 
+            DI26: in  std_logic; DI27: in  std_logic; 
+            DI28: in  std_logic; DI29: in  std_logic; 
+            DI30: in  std_logic; DI31: in  std_logic; 
+            DI32: in  std_logic; DI33: in  std_logic; 
+            DI34: in  std_logic; DI35: in  std_logic; 
+            ADW0: in  std_logic; ADW1: in  std_logic; 
+            ADW2: in  std_logic; ADW3: in  std_logic; 
+            ADW4: in  std_logic; ADW5: in  std_logic; 
+            ADW6: in  std_logic; ADW7: in  std_logic; 
+            ADW8: in  std_logic; BE0: in  std_logic; BE1: in  std_logic; 
+            BE2: in  std_logic; BE3: in  std_logic; CEW: in  std_logic; 
+            CLKW: in  std_logic; CSW0: in  std_logic; 
+            CSW1: in  std_logic; CSW2: in  std_logic; 
+            ADR0: in  std_logic; ADR1: in  std_logic; 
+            ADR2: in  std_logic; ADR3: in  std_logic; 
+            ADR4: in  std_logic; ADR5: in  std_logic; 
+            ADR6: in  std_logic; ADR7: in  std_logic; 
+            ADR8: in  std_logic; ADR9: in  std_logic; 
+            ADR10: in  std_logic; ADR11: in  std_logic; 
+            ADR12: in  std_logic; ADR13: in  std_logic; 
+            CER: in  std_logic; CLKR: in  std_logic; CSR0: in  std_logic; 
+            CSR1: in  std_logic; CSR2: in  std_logic; RST: in  std_logic; 
+            DO0: out  std_logic; DO1: out  std_logic; 
+            DO2: out  std_logic; DO3: out  std_logic; 
+            DO4: out  std_logic; DO5: out  std_logic; 
+            DO6: out  std_logic; DO7: out  std_logic; 
+            DO8: out  std_logic; DO9: out  std_logic; 
+            DO10: out  std_logic; DO11: out  std_logic; 
+            DO12: out  std_logic; DO13: out  std_logic; 
+            DO14: out  std_logic; DO15: out  std_logic; 
+            DO16: out  std_logic; DO17: out  std_logic; 
+            DO18: out  std_logic; DO19: out  std_logic; 
+            DO20: out  std_logic; DO21: out  std_logic; 
+            DO22: out  std_logic; DO23: out  std_logic; 
+            DO24: out  std_logic; DO25: out  std_logic; 
+            DO26: out  std_logic; DO27: out  std_logic; 
+            DO28: out  std_logic; DO29: out  std_logic; 
+            DO30: out  std_logic; DO31: out  std_logic; 
+            DO32: out  std_logic; DO33: out  std_logic; 
+            DO34: out  std_logic; DO35: out  std_logic);
+    end component;
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute RESETMODE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "async_fifo_nn_th_512x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+    attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
+    attribute GSR of FF_122 : label is "ENABLED";
+    attribute GSR of FF_121 : label is "ENABLED";
+    attribute GSR of FF_120 : label is "ENABLED";
+    attribute GSR of FF_119 : label is "ENABLED";
+    attribute GSR of FF_118 : label is "ENABLED";
+    attribute GSR of FF_117 : label is "ENABLED";
+    attribute GSR of FF_116 : label is "ENABLED";
+    attribute GSR of FF_115 : label is "ENABLED";
+    attribute GSR of FF_114 : label is "ENABLED";
+    attribute GSR of FF_113 : label is "ENABLED";
+    attribute GSR of FF_112 : label is "ENABLED";
+    attribute GSR of FF_111 : label is "ENABLED";
+    attribute GSR of FF_110 : label is "ENABLED";
+    attribute GSR of FF_109 : label is "ENABLED";
+    attribute GSR of FF_108 : label is "ENABLED";
+    attribute GSR of FF_107 : label is "ENABLED";
+    attribute GSR of FF_106 : label is "ENABLED";
+    attribute GSR of FF_105 : label is "ENABLED";
+    attribute GSR of FF_104 : label is "ENABLED";
+    attribute GSR of FF_103 : label is "ENABLED";
+    attribute GSR of FF_102 : label is "ENABLED";
+    attribute GSR of FF_101 : label is "ENABLED";
+    attribute GSR of FF_100 : label is "ENABLED";
+    attribute GSR of FF_99 : label is "ENABLED";
+    attribute GSR of FF_98 : label is "ENABLED";
+    attribute GSR of FF_97 : label is "ENABLED";
+    attribute GSR of FF_96 : label is "ENABLED";
+    attribute GSR of FF_95 : label is "ENABLED";
+    attribute GSR of FF_94 : label is "ENABLED";
+    attribute GSR of FF_93 : label is "ENABLED";
+    attribute GSR of FF_92 : label is "ENABLED";
+    attribute GSR of FF_91 : label is "ENABLED";
+    attribute GSR of FF_90 : label is "ENABLED";
+    attribute GSR of FF_89 : label is "ENABLED";
+    attribute GSR of FF_88 : label is "ENABLED";
+    attribute GSR of FF_87 : label is "ENABLED";
+    attribute GSR of FF_86 : label is "ENABLED";
+    attribute GSR of FF_85 : label is "ENABLED";
+    attribute GSR of FF_84 : label is "ENABLED";
+    attribute GSR of FF_83 : label is "ENABLED";
+    attribute GSR of FF_82 : label is "ENABLED";
+    attribute GSR of FF_81 : label is "ENABLED";
+    attribute GSR of FF_80 : label is "ENABLED";
+    attribute GSR of FF_79 : label is "ENABLED";
+    attribute GSR of FF_78 : label is "ENABLED";
+    attribute GSR of FF_77 : label is "ENABLED";
+    attribute GSR of FF_76 : label is "ENABLED";
+    attribute GSR of FF_75 : label is "ENABLED";
+    attribute GSR of FF_74 : label is "ENABLED";
+    attribute GSR of FF_73 : label is "ENABLED";
+    attribute GSR of FF_72 : label is "ENABLED";
+    attribute GSR of FF_71 : label is "ENABLED";
+    attribute GSR of FF_70 : label is "ENABLED";
+    attribute GSR of FF_69 : label is "ENABLED";
+    attribute GSR of FF_68 : label is "ENABLED";
+    attribute GSR of FF_67 : label is "ENABLED";
+    attribute GSR of FF_66 : label is "ENABLED";
+    attribute GSR of FF_65 : label is "ENABLED";
+    attribute GSR of FF_64 : label is "ENABLED";
+    attribute GSR of FF_63 : label is "ENABLED";
+    attribute GSR of FF_62 : label is "ENABLED";
+    attribute GSR of FF_61 : label is "ENABLED";
+    attribute GSR of FF_60 : label is "ENABLED";
+    attribute GSR of FF_59 : label is "ENABLED";
+    attribute GSR of FF_58 : label is "ENABLED";
+    attribute GSR of FF_57 : label is "ENABLED";
+    attribute GSR of FF_56 : label is "ENABLED";
+    attribute GSR of FF_55 : label is "ENABLED";
+    attribute GSR of FF_54 : label is "ENABLED";
+    attribute GSR of FF_53 : label is "ENABLED";
+    attribute GSR of FF_52 : label is "ENABLED";
+    attribute GSR of FF_51 : label is "ENABLED";
+    attribute GSR of FF_50 : label is "ENABLED";
+    attribute GSR of FF_49 : label is "ENABLED";
+    attribute GSR of FF_48 : label is "ENABLED";
+    attribute GSR of FF_47 : label is "ENABLED";
+    attribute GSR of FF_46 : label is "ENABLED";
+    attribute GSR of FF_45 : label is "ENABLED";
+    attribute GSR of FF_44 : label is "ENABLED";
+    attribute GSR of FF_43 : label is "ENABLED";
+    attribute GSR of FF_42 : label is "ENABLED";
+    attribute GSR of FF_41 : label is "ENABLED";
+    attribute GSR of FF_40 : label is "ENABLED";
+    attribute GSR of FF_39 : label is "ENABLED";
+    attribute GSR of FF_38 : label is "ENABLED";
+    attribute GSR of FF_37 : label is "ENABLED";
+    attribute GSR of FF_36 : label is "ENABLED";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t21: AND2
+        port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+    INV_1: INV
+        port map (A=>full_i, Z=>invout_1);
+
+    AND2_t20: AND2
+        port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+    INV_0: INV
+        port map (A=>empty_i, Z=>invout_0);
+
+    OR2_t19: OR2
+        port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+    XOR2_t18: XOR2
+        port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+    XOR2_t17: XOR2
+        port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+    XOR2_t16: XOR2
+        port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+    XOR2_t15: XOR2
+        port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+    XOR2_t14: XOR2
+        port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+    XOR2_t13: XOR2
+        port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
+
+    XOR2_t12: XOR2
+        port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
+
+    XOR2_t11: XOR2
+        port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
+
+    XOR2_t10: XOR2
+        port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
+
+    XOR2_t9: XOR2
+        port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+    XOR2_t8: XOR2
+        port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+    XOR2_t7: XOR2
+        port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+    XOR2_t6: XOR2
+        port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+    XOR2_t5: XOR2
+        port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+    XOR2_t4: XOR2
+        port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
+
+    XOR2_t3: XOR2
+        port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
+
+    XOR2_t2: XOR2
+        port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
+
+    XOR2_t1: XOR2
+        port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
+
+    LUT4_25: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, 
+            AD1=>w_gcount_r28, AD0=>w_gcount_r29, 
+            DO0=>w_g2b_xor_cluster_0);
+
+    LUT4_24: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, 
+            AD1=>w_gcount_r24, AD0=>w_gcount_r25, 
+            DO0=>w_g2b_xor_cluster_1);
+
+    LUT4_23: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>wcount_r8);
+
+    LUT4_22: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, 
+            AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7);
+
+    LUT4_21: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, 
+            AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
+
+    LUT4_20: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, 
+            AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
+
+    LUT4_19: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, 
+            AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3);
+
+    LUT4_18: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2);
+
+    LUT4_17: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1);
+
+    LUT4_16: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0);
+
+    LUT4_15: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, 
+            AD1=>r_gcount_w28, AD0=>r_gcount_w29, 
+            DO0=>r_g2b_xor_cluster_0);
+
+    LUT4_14: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, 
+            AD1=>r_gcount_w24, AD0=>r_gcount_w25, 
+            DO0=>r_g2b_xor_cluster_1);
+
+    LUT4_13: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>rcount_w8);
+
+    LUT4_12: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, 
+            AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7);
+
+    LUT4_11: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, 
+            AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
+
+    LUT4_10: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, 
+            AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
+
+    LUT4_9: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, 
+            AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3);
+
+    LUT4_8: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2);
+
+    LUT4_7: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1);
+
+    LUT4_6: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0);
+
+    XOR2_t0: XOR2
+        port map (A=>w_gcount_r29, B=>rptr_9, Z=>rfill_sub_msb);
+
+    LUT4_5: ROM16X1A
+        generic map (initval=> X"0410")
+        port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+    LUT4_4: ROM16X1A
+        generic map (initval=> X"1004")
+        port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+    LUT4_3: ROM16X1A
+        generic map (initval=> X"0140")
+        port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, 
+            AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+    LUT4_2: ROM16X1A
+        generic map (initval=> X"4001")
+        port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, 
+            AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"13c8")
+        port map (AD3=>ae_setcount_9, AD2=>rcount_9, AD1=>w_gcount_r29, 
+            AD0=>rptr_9, DO0=>ae_set_cmp_set);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"2004")
+        port map (AD3=>ae_setcount_9, AD2=>rcount_9, AD1=>w_gcount_r29, 
+            AD0=>rptr_9, DO0=>ae_set_cmp_clr);
+
+    pdp_ram_0_0_0: PDPW16KC
+        generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", 
+        REGMODE=> "NOREG", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
+        port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), 
+            DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), 
+            DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), 
+            DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), 
+            DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), 
+            DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), 
+            DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), 
+            DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), 
+            DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), 
+            DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), 
+            DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0, 
+            ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4, 
+            ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>wptr_8, 
+            BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, 
+            BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, 
+            CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, 
+            ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, 
+            ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, 
+            ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, 
+            ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock, 
+            CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, 
+            RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), 
+            DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), 
+            DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), 
+            DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), DO16=>Q(34), 
+            DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), 
+            DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), 
+            DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), 
+            DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), 
+            DO35=>Q(17));
+
+    FF_122: FD1P3BX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>wcount_0);
+
+    FF_121: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_120: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_119: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_118: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_117: FD1P3DX
+        port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_116: FD1P3DX
+        port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_6);
+
+    FF_115: FD1P3DX
+        port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_7);
+
+    FF_114: FD1P3DX
+        port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_8);
+
+    FF_113: FD1P3DX
+        port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_9);
+
+    FF_112: FD1P3DX
+        port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_0);
+
+    FF_111: FD1P3DX
+        port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_1);
+
+    FF_110: FD1P3DX
+        port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_2);
+
+    FF_109: FD1P3DX
+        port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_3);
+
+    FF_108: FD1P3DX
+        port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_4);
+
+    FF_107: FD1P3DX
+        port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_5);
+
+    FF_106: FD1P3DX
+        port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_6);
+
+    FF_105: FD1P3DX
+        port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_7);
+
+    FF_104: FD1P3DX
+        port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_8);
+
+    FF_103: FD1P3DX
+        port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_9);
+
+    FF_102: FD1P3DX
+        port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_0);
+
+    FF_101: FD1P3DX
+        port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_1);
+
+    FF_100: FD1P3DX
+        port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_2);
+
+    FF_99: FD1P3DX
+        port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_3);
+
+    FF_98: FD1P3DX
+        port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_4);
+
+    FF_97: FD1P3DX
+        port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_5);
+
+    FF_96: FD1P3DX
+        port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_6);
+
+    FF_95: FD1P3DX
+        port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_7);
+
+    FF_94: FD1P3DX
+        port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_8);
+
+    FF_93: FD1P3DX
+        port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_9);
+
+    FF_92: FD1P3BX
+        port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, 
+            Q=>rcount_0);
+
+    FF_91: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_1);
+
+    FF_90: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_2);
+
+    FF_89: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_3);
+
+    FF_88: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_4);
+
+    FF_87: FD1P3DX
+        port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_5);
+
+    FF_86: FD1P3DX
+        port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_6);
+
+    FF_85: FD1P3DX
+        port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_7);
+
+    FF_84: FD1P3DX
+        port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_8);
+
+    FF_83: FD1P3DX
+        port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_9);
+
+    FF_82: FD1P3DX
+        port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_0);
+
+    FF_81: FD1P3DX
+        port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_1);
+
+    FF_80: FD1P3DX
+        port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_2);
+
+    FF_79: FD1P3DX
+        port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_3);
+
+    FF_78: FD1P3DX
+        port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_4);
+
+    FF_77: FD1P3DX
+        port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_5);
+
+    FF_76: FD1P3DX
+        port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_6);
+
+    FF_75: FD1P3DX
+        port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_7);
+
+    FF_74: FD1P3DX
+        port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_8);
+
+    FF_73: FD1P3DX
+        port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_9);
+
+    FF_72: FD1P3DX
+        port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_0);
+
+    FF_71: FD1P3DX
+        port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_1);
+
+    FF_70: FD1P3DX
+        port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_2);
+
+    FF_69: FD1P3DX
+        port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_3);
+
+    FF_68: FD1P3DX
+        port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_4);
+
+    FF_67: FD1P3DX
+        port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_5);
+
+    FF_66: FD1P3DX
+        port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_6);
+
+    FF_65: FD1P3DX
+        port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_7);
+
+    FF_64: FD1P3DX
+        port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_8);
+
+    FF_63: FD1P3DX
+        port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_9);
+
+    FF_62: FD1S3DX
+        port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+    FF_61: FD1S3DX
+        port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+    FF_60: FD1S3DX
+        port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+    FF_59: FD1S3DX
+        port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+    FF_58: FD1S3DX
+        port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+    FF_57: FD1S3DX
+        port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+    FF_56: FD1S3DX
+        port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
+
+    FF_55: FD1S3DX
+        port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
+
+    FF_54: FD1S3DX
+        port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
+
+    FF_53: FD1S3DX
+        port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
+
+    FF_52: FD1S3DX
+        port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+    FF_51: FD1S3DX
+        port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+    FF_50: FD1S3DX
+        port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+    FF_49: FD1S3DX
+        port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+    FF_48: FD1S3DX
+        port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+    FF_47: FD1S3DX
+        port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+    FF_46: FD1S3DX
+        port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+    FF_45: FD1S3DX
+        port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
+
+    FF_44: FD1S3DX
+        port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
+
+    FF_43: FD1S3DX
+        port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
+
+    FF_42: FD1S3DX
+        port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r20);
+
+    FF_41: FD1S3DX
+        port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r21);
+
+    FF_40: FD1S3DX
+        port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r22);
+
+    FF_39: FD1S3DX
+        port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r23);
+
+    FF_38: FD1S3DX
+        port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r24);
+
+    FF_37: FD1S3DX
+        port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r25);
+
+    FF_36: FD1S3DX
+        port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r26);
+
+    FF_35: FD1S3DX
+        port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r27);
+
+    FF_34: FD1S3DX
+        port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r28);
+
+    FF_33: FD1S3DX
+        port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r29);
+
+    FF_32: FD1S3DX
+        port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+    FF_31: FD1S3DX
+        port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+    FF_30: FD1S3DX
+        port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+    FF_29: FD1S3DX
+        port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+    FF_28: FD1S3DX
+        port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+    FF_27: FD1S3DX
+        port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+    FF_26: FD1S3DX
+        port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
+
+    FF_25: FD1S3DX
+        port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
+
+    FF_24: FD1S3DX
+        port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
+
+    FF_23: FD1S3DX
+        port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
+
+    FF_22: FD1S3DX
+        port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0));
+
+    FF_21: FD1S3DX
+        port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1));
+
+    FF_20: FD1S3DX
+        port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2));
+
+    FF_19: FD1S3DX
+        port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3));
+
+    FF_18: FD1S3DX
+        port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4));
+
+    FF_17: FD1S3DX
+        port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5));
+
+    FF_16: FD1S3DX
+        port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6));
+
+    FF_15: FD1S3DX
+        port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7));
+
+    FF_14: FD1S3DX
+        port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8));
+
+    FF_13: FD1S3DX
+        port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9));
+
+    FF_12: FD1S3BX
+        port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+    FF_11: FD1S3DX
+        port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+    FF_10: FD1P3BX
+        port map (D=>iae_setcount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, 
+            Q=>ae_setcount_0);
+
+    FF_9: FD1P3DX
+        port map (D=>iae_setcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>ae_setcount_1);
+
+    FF_8: FD1P3DX
+        port map (D=>iae_setcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>ae_setcount_2);
+
+    FF_7: FD1P3DX
+        port map (D=>iae_setcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>ae_setcount_3);
+
+    FF_6: FD1P3DX
+        port map (D=>iae_setcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>ae_setcount_4);
+
+    FF_5: FD1P3DX
+        port map (D=>iae_setcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>ae_setcount_5);
+
+    FF_4: FD1P3DX
+        port map (D=>iae_setcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>ae_setcount_6);
+
+    FF_3: FD1P3BX
+        port map (D=>iae_setcount_7, SP=>rden_i, CK=>RdClock, PD=>rRst, 
+            Q=>ae_setcount_7);
+
+    FF_2: FD1P3DX
+        port map (D=>iae_setcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>ae_setcount_8);
+
+    FF_1: FD1P3DX
+        port map (D=>iae_setcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>ae_setcount_9);
+
+    FF_0: FD1S3BX
+        port map (D=>ae_set_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty);
+
+    w_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, 
+            S1=>open);
+
+    w_gctr_0: CU2
+        port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, 
+            NC0=>iwcount_0, NC1=>iwcount_1);
+
+    w_gctr_1: CU2
+        port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, 
+            NC0=>iwcount_2, NC1=>iwcount_3);
+
+    w_gctr_2: CU2
+        port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, 
+            NC0=>iwcount_4, NC1=>iwcount_5);
+
+    w_gctr_3: CU2
+        port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, 
+            NC0=>iwcount_6, NC1=>iwcount_7);
+
+    w_gctr_4: CU2
+        port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, 
+            NC0=>iwcount_8, NC1=>iwcount_9);
+
+    r_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, 
+            S1=>open);
+
+    r_gctr_0: CU2
+        port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, 
+            NC0=>ircount_0, NC1=>ircount_1);
+
+    r_gctr_1: CU2
+        port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, 
+            NC0=>ircount_2, NC1=>ircount_3);
+
+    r_gctr_2: CU2
+        port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, 
+            NC0=>ircount_4, NC1=>ircount_5);
+
+    r_gctr_3: CU2
+        port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, 
+            NC0=>ircount_6, NC1=>ircount_7);
+
+    r_gctr_4: CU2
+        port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, 
+            NC0=>ircount_8, NC1=>ircount_9);
+
+    rfill_0: FSUB2B
+        port map (A0=>scuba_vhi, A1=>wcount_r0, B0=>scuba_vlo, 
+            B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_2, S0=>open, 
+            S1=>rfill_sub_0);
+
+    rfill_1: FSUB2B
+        port map (A0=>wcount_r1, A1=>wcount_r2, B0=>rptr_1, B1=>rptr_2, 
+            BI=>co0_2, BOUT=>co1_2, S0=>rfill_sub_1, S1=>rfill_sub_2);
+
+    rfill_2: FSUB2B
+        port map (A0=>wcount_r3, A1=>wcount_r4, B0=>rptr_3, B1=>rptr_4, 
+            BI=>co1_2, BOUT=>co2_2, S0=>rfill_sub_3, S1=>rfill_sub_4);
+
+    rfill_3: FSUB2B
+        port map (A0=>wcount_r5, A1=>w_g2b_xor_cluster_0, B0=>rptr_5, 
+            B1=>rptr_6, BI=>co2_2, BOUT=>co3_2, S0=>rfill_sub_5, 
+            S1=>rfill_sub_6);
+
+    rfill_4: FSUB2B
+        port map (A0=>wcount_r7, A1=>wcount_r8, B0=>rptr_7, B1=>rptr_8, 
+            BI=>co3_2, BOUT=>co4_2, S0=>rfill_sub_7, S1=>rfill_sub_8);
+
+    rfill_5: FSUB2B
+        port map (A0=>rfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, BI=>co4_2, BOUT=>open, S0=>rfill_sub_9, 
+            S1=>open);
+
+    empty_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+    empty_cmp_0: AGEB2
+        port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, 
+            B1=>wcount_r1, CI=>cmp_ci, GE=>co0_3);
+
+    empty_cmp_1: AGEB2
+        port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, 
+            B1=>wcount_r3, CI=>co0_3, GE=>co1_3);
+
+    empty_cmp_2: AGEB2
+        port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, 
+            B1=>wcount_r5, CI=>co1_3, GE=>co2_3);
+
+    empty_cmp_3: AGEB2
+        port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0, 
+            B1=>wcount_r7, CI=>co2_3, GE=>co3_3);
+
+    empty_cmp_4: AGEB2
+        port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8, 
+            B1=>empty_cmp_clr, CI=>co3_3, GE=>empty_d_c);
+
+    a0: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, 
+            S1=>open);
+
+    full_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+    full_cmp_0: AGEB2
+        port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, 
+            B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_4);
+
+    full_cmp_1: AGEB2
+        port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, 
+            B1=>rcount_w3, CI=>co0_4, GE=>co1_4);
+
+    full_cmp_2: AGEB2
+        port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, 
+            B1=>rcount_w5, CI=>co1_4, GE=>co2_4);
+
+    full_cmp_3: AGEB2
+        port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, 
+            B1=>rcount_w7, CI=>co2_4, GE=>co3_4);
+
+    full_cmp_4: AGEB2
+        port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8, 
+            B1=>full_cmp_clr, CI=>co3_4, GE=>full_d_c);
+
+    a1: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, 
+            S1=>open);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    ae_set_ctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>ae_set_ctr_ci, S0=>open, 
+            S1=>open);
+
+    ae_set_ctr_0: CU2
+        port map (CI=>ae_set_ctr_ci, PC0=>ae_setcount_0, 
+            PC1=>ae_setcount_1, CO=>co0_5, NC0=>iae_setcount_0, 
+            NC1=>iae_setcount_1);
+
+    ae_set_ctr_1: CU2
+        port map (CI=>co0_5, PC0=>ae_setcount_2, PC1=>ae_setcount_3, 
+            CO=>co1_5, NC0=>iae_setcount_2, NC1=>iae_setcount_3);
+
+    ae_set_ctr_2: CU2
+        port map (CI=>co1_5, PC0=>ae_setcount_4, PC1=>ae_setcount_5, 
+            CO=>co2_5, NC0=>iae_setcount_4, NC1=>iae_setcount_5);
+
+    ae_set_ctr_3: CU2
+        port map (CI=>co2_5, PC0=>ae_setcount_6, PC1=>ae_setcount_7, 
+            CO=>co3_5, NC0=>iae_setcount_6, NC1=>iae_setcount_7);
+
+    ae_set_ctr_4: CU2
+        port map (CI=>co3_5, PC0=>ae_setcount_8, PC1=>ae_setcount_9, 
+            CO=>co4_3, NC0=>iae_setcount_8, NC1=>iae_setcount_9);
+
+    ae_set_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
+
+    ae_set_cmp_0: AGEB2
+        port map (A0=>ae_setcount_0, A1=>ae_setcount_1, B0=>wcount_r0, 
+            B1=>wcount_r1, CI=>cmp_ci_2, GE=>co0_6);
+
+    ae_set_cmp_1: AGEB2
+        port map (A0=>ae_setcount_2, A1=>ae_setcount_3, B0=>wcount_r2, 
+            B1=>wcount_r3, CI=>co0_6, GE=>co1_6);
+
+    ae_set_cmp_2: AGEB2
+        port map (A0=>ae_setcount_4, A1=>ae_setcount_5, B0=>wcount_r4, 
+            B1=>wcount_r5, CI=>co1_6, GE=>co2_6);
+
+    ae_set_cmp_3: AGEB2
+        port map (A0=>ae_setcount_6, A1=>ae_setcount_7, 
+            B0=>w_g2b_xor_cluster_0, B1=>wcount_r7, CI=>co2_6, GE=>co3_6);
+
+    ae_set_cmp_4: AGEB2
+        port map (A0=>ae_setcount_8, A1=>ae_set_cmp_set, B0=>wcount_r8, 
+            B1=>ae_set_cmp_clr, CI=>co3_6, GE=>ae_set_d_c);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    a2: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>ae_set_d_c, COUT=>open, S0=>ae_set_d, 
+            S1=>open);
+
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of async_fifo_nn_th_512x36_ecp3 is
+    for Structure
+        for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+        for all:AND2 use entity ecp3.AND2(V); end for;
+        for all:CU2 use entity ecp3.CU2(V); end for;
+        for all:FADD2B use entity ecp3.FADD2B(V); end for;
+        for all:FSUB2B use entity ecp3.FSUB2B(V); end for;
+        for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
+        for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+        for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+        for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+        for all:INV use entity ecp3.INV(V); end for;
+        for all:OR2 use entity ecp3.OR2(V); end for;
+        for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+        for all:VHI use entity ecp3.VHI(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+        for all:XOR2 use entity ecp3.XOR2(V); end for;
+        for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_nn_th_512x36_ecp3_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_th_512x36_ecp3_tmpl.vhd
new file mode 100644
index 0000000..c3c0fd1
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_th_512x36_ecp3_tmpl.vhd
@@ -0,0 +1,19 @@
+-- VHDL module instantiation generated by SCUBA Diamond_2.1_Production (100)
+-- Module  Version: 5.4
+-- Fri Jul 12 14:33:50 2013
+
+-- parameterized module component declaration
+component async_fifo_nn_th_512x36_ecp3
+    port (Data: in  std_logic_vector(35 downto 0); 
+        WrClock: in  std_logic; RdClock: in  std_logic; 
+        WrEn: in  std_logic; RdEn: in  std_logic; Reset: in  std_logic; 
+        RPReset: in  std_logic; Q: out  std_logic_vector(35 downto 0); 
+        RCNT: out  std_logic_vector(9 downto 0); Empty: out  std_logic; 
+        Full: out  std_logic; AlmostEmpty: out  std_logic);
+end component;
+
+-- parameterized module component instance
+__ : async_fifo_nn_th_512x36_ecp3
+    port map (Data(35 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, 
+        RdEn=>__, Reset=>__, RPReset=>__, Q(35 downto 0)=>__, RCNT(9 downto 0)=>__, 
+        Empty=>__, Full=>__, AlmostEmpty=>__);
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_nn_thfull_512x36_ecp3.ipx b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_thfull_512x36_ecp3.ipx
new file mode 100644
index 0000000..1e441e9
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_thfull_512x36_ecp3.ipx
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="async_fifo_nn_thfull_512x36_ecp3" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 09 24 15:27:31.187" version="5.7" type="Module" synthesis="" source_format="VHDL">
+  <Package>
+		<File name="async_fifo_nn_thfull_512x36_ecp3.lpc" type="lpc" modified="2014 09 24 15:27:28.711"/>
+		<File name="async_fifo_nn_thfull_512x36_ecp3.vhd" type="top_level_vhdl" modified="2014 09 24 15:27:28.822"/>
+		<File name="async_fifo_nn_thfull_512x36_ecp3_tmpl.vhd" type="template_vhdl" modified="2014 09 24 15:27:28.822"/>
+		<File name="tb_async_fifo_nn_thfull_512x36_ecp3_tmpl.vhd" type="testbench_vhdl" modified="2014 09 24 15:27:28.842"/>
+  </Package>
+</DiamondModule>
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_nn_thfull_512x36_ecp3.lpc b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_thfull_512x36_ecp3.lpc
new file mode 100644
index 0000000..50e7c0f
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_thfull_512x36_ecp3.lpc
@@ -0,0 +1,50 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.7
+ModuleName=async_fifo_nn_thfull_512x36_ecp3
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=09/24/2014
+Time=15:27:28
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=512
+Width=36
+RDepth=512
+RWidth=36
+regout=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=378
+PfDeassert=506
+RDataCount=1
+WDataCount=0
+EnECC=0
+
+[Command]
+cmd_line= -w -n async_fifo_nn_thfull_512x36_ecp3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 9 -data_width 36 -num_words 512 -rdata_width 36 -no_enable -pe -1 -pf 378 -rfill
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_nn_thfull_512x36_ecp3.vhd b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_thfull_512x36_ecp3.vhd
new file mode 100644
index 0000000..0f74e1f
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_thfull_512x36_ecp3.vhd
@@ -0,0 +1,1450 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.7
+--C:\Lattice\diamond\3.2_x64\ispfpga\bin\nt64\scuba.exe -w -n async_fifo_nn_thfull_512x36_ecp3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 36 -depth 512 -rdata_width 36 -no_enable -pe -1 -pf 378 -rfill 
+
+-- Wed Sep 24 15:27:28 2014
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity async_fifo_nn_thfull_512x36_ecp3 is
+    port (
+        Data: in  std_logic_vector(35 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(35 downto 0); 
+        RCNT: out  std_logic_vector(9 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostFull: out  std_logic);
+end async_fifo_nn_thfull_512x36_ecp3;
+
+architecture Structure of async_fifo_nn_thfull_512x36_ecp3 is
+
+    -- internal signal declarations
+    signal invout_1: std_logic;
+    signal invout_0: std_logic;
+    signal w_g2b_xor_cluster_1: std_logic;
+    signal r_g2b_xor_cluster_1: std_logic;
+    signal w_gdata_0: std_logic;
+    signal w_gdata_1: std_logic;
+    signal w_gdata_2: std_logic;
+    signal w_gdata_3: std_logic;
+    signal w_gdata_4: std_logic;
+    signal w_gdata_5: std_logic;
+    signal w_gdata_6: std_logic;
+    signal w_gdata_7: std_logic;
+    signal w_gdata_8: std_logic;
+    signal wptr_0: std_logic;
+    signal wptr_1: std_logic;
+    signal wptr_2: std_logic;
+    signal wptr_3: std_logic;
+    signal wptr_4: std_logic;
+    signal wptr_5: std_logic;
+    signal wptr_6: std_logic;
+    signal wptr_7: std_logic;
+    signal wptr_8: std_logic;
+    signal wptr_9: std_logic;
+    signal r_gdata_0: std_logic;
+    signal r_gdata_1: std_logic;
+    signal r_gdata_2: std_logic;
+    signal r_gdata_3: std_logic;
+    signal r_gdata_4: std_logic;
+    signal r_gdata_5: std_logic;
+    signal r_gdata_6: std_logic;
+    signal r_gdata_7: std_logic;
+    signal r_gdata_8: std_logic;
+    signal rptr_9: std_logic;
+    signal w_gcount_0: std_logic;
+    signal w_gcount_1: std_logic;
+    signal w_gcount_2: std_logic;
+    signal w_gcount_3: std_logic;
+    signal w_gcount_4: std_logic;
+    signal w_gcount_5: std_logic;
+    signal w_gcount_6: std_logic;
+    signal w_gcount_7: std_logic;
+    signal w_gcount_8: std_logic;
+    signal w_gcount_9: std_logic;
+    signal r_gcount_0: std_logic;
+    signal r_gcount_1: std_logic;
+    signal r_gcount_2: std_logic;
+    signal r_gcount_3: std_logic;
+    signal r_gcount_4: std_logic;
+    signal r_gcount_5: std_logic;
+    signal r_gcount_6: std_logic;
+    signal r_gcount_7: std_logic;
+    signal r_gcount_8: std_logic;
+    signal r_gcount_9: std_logic;
+    signal w_gcount_r20: std_logic;
+    signal w_gcount_r0: std_logic;
+    signal w_gcount_r21: std_logic;
+    signal w_gcount_r1: std_logic;
+    signal w_gcount_r22: std_logic;
+    signal w_gcount_r2: std_logic;
+    signal w_gcount_r23: std_logic;
+    signal w_gcount_r3: std_logic;
+    signal w_gcount_r24: std_logic;
+    signal w_gcount_r4: std_logic;
+    signal w_gcount_r25: std_logic;
+    signal w_gcount_r5: std_logic;
+    signal w_gcount_r26: std_logic;
+    signal w_gcount_r6: std_logic;
+    signal w_gcount_r27: std_logic;
+    signal w_gcount_r7: std_logic;
+    signal w_gcount_r28: std_logic;
+    signal w_gcount_r8: std_logic;
+    signal w_gcount_r29: std_logic;
+    signal w_gcount_r9: std_logic;
+    signal r_gcount_w20: std_logic;
+    signal r_gcount_w0: std_logic;
+    signal r_gcount_w21: std_logic;
+    signal r_gcount_w1: std_logic;
+    signal r_gcount_w22: std_logic;
+    signal r_gcount_w2: std_logic;
+    signal r_gcount_w23: std_logic;
+    signal r_gcount_w3: std_logic;
+    signal r_gcount_w24: std_logic;
+    signal r_gcount_w4: std_logic;
+    signal r_gcount_w25: std_logic;
+    signal r_gcount_w5: std_logic;
+    signal r_gcount_w26: std_logic;
+    signal r_gcount_w6: std_logic;
+    signal r_gcount_w27: std_logic;
+    signal r_gcount_w7: std_logic;
+    signal r_gcount_w28: std_logic;
+    signal r_gcount_w8: std_logic;
+    signal r_gcount_w29: std_logic;
+    signal r_gcount_w9: std_logic;
+    signal empty_i: std_logic;
+    signal rRst: std_logic;
+    signal full_i: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_gctr_ci: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co0: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal co1: std_logic;
+    signal iwcount_6: std_logic;
+    signal iwcount_7: std_logic;
+    signal co2: std_logic;
+    signal iwcount_8: std_logic;
+    signal iwcount_9: std_logic;
+    signal co4: std_logic;
+    signal co3: std_logic;
+    signal wcount_9: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_gctr_ci: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co0_1: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal co1_1: std_logic;
+    signal ircount_6: std_logic;
+    signal ircount_7: std_logic;
+    signal co2_1: std_logic;
+    signal ircount_8: std_logic;
+    signal ircount_9: std_logic;
+    signal co4_1: std_logic;
+    signal co3_1: std_logic;
+    signal rcount_9: std_logic;
+    signal rfill_sub_0: std_logic;
+    signal precin: std_logic;
+    signal rptr_0: std_logic;
+    signal rfill_sub_1: std_logic;
+    signal rfill_sub_2: std_logic;
+    signal co0_2: std_logic;
+    signal rptr_1: std_logic;
+    signal rptr_2: std_logic;
+    signal rfill_sub_3: std_logic;
+    signal rfill_sub_4: std_logic;
+    signal co1_2: std_logic;
+    signal rptr_3: std_logic;
+    signal rptr_4: std_logic;
+    signal rfill_sub_5: std_logic;
+    signal rfill_sub_6: std_logic;
+    signal co2_2: std_logic;
+    signal rptr_5: std_logic;
+    signal rptr_6: std_logic;
+    signal rfill_sub_7: std_logic;
+    signal rfill_sub_8: std_logic;
+    signal co3_2: std_logic;
+    signal rptr_7: std_logic;
+    signal rptr_8: std_logic;
+    signal rfill_sub_9: std_logic;
+    signal co4_2: std_logic;
+    signal rfill_sub_msb: std_logic;
+    signal rden_i: std_logic;
+    signal cmp_ci: std_logic;
+    signal wcount_r0: std_logic;
+    signal wcount_r1: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal co0_3: std_logic;
+    signal wcount_r2: std_logic;
+    signal wcount_r3: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal co1_3: std_logic;
+    signal wcount_r4: std_logic;
+    signal wcount_r5: std_logic;
+    signal rcount_4: std_logic;
+    signal rcount_5: std_logic;
+    signal co2_3: std_logic;
+    signal w_g2b_xor_cluster_0: std_logic;
+    signal wcount_r7: std_logic;
+    signal rcount_6: std_logic;
+    signal rcount_7: std_logic;
+    signal co3_3: std_logic;
+    signal wcount_r8: std_logic;
+    signal empty_cmp_clr: std_logic;
+    signal rcount_8: std_logic;
+    signal empty_cmp_set: std_logic;
+    signal empty_d: std_logic;
+    signal empty_d_c: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal wcount_0: std_logic;
+    signal wcount_1: std_logic;
+    signal co0_4: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_3: std_logic;
+    signal co1_4: std_logic;
+    signal wcount_4: std_logic;
+    signal wcount_5: std_logic;
+    signal co2_4: std_logic;
+    signal wcount_6: std_logic;
+    signal wcount_7: std_logic;
+    signal co3_4: std_logic;
+    signal full_cmp_clr: std_logic;
+    signal wcount_8: std_logic;
+    signal full_cmp_set: std_logic;
+    signal full_d: std_logic;
+    signal full_d_c: std_logic;
+    signal scuba_vhi: std_logic;
+    signal iaf_setcount_0: std_logic;
+    signal iaf_setcount_1: std_logic;
+    signal af_set_ctr_ci: std_logic;
+    signal iaf_setcount_2: std_logic;
+    signal iaf_setcount_3: std_logic;
+    signal co0_5: std_logic;
+    signal iaf_setcount_4: std_logic;
+    signal iaf_setcount_5: std_logic;
+    signal co1_5: std_logic;
+    signal iaf_setcount_6: std_logic;
+    signal iaf_setcount_7: std_logic;
+    signal co2_5: std_logic;
+    signal iaf_setcount_8: std_logic;
+    signal iaf_setcount_9: std_logic;
+    signal co4_3: std_logic;
+    signal co3_5: std_logic;
+    signal af_setcount_9: std_logic;
+    signal wren_i: std_logic;
+    signal cmp_ci_2: std_logic;
+    signal rcount_w0: std_logic;
+    signal rcount_w1: std_logic;
+    signal af_setcount_0: std_logic;
+    signal af_setcount_1: std_logic;
+    signal co0_6: std_logic;
+    signal rcount_w2: std_logic;
+    signal rcount_w3: std_logic;
+    signal af_setcount_2: std_logic;
+    signal af_setcount_3: std_logic;
+    signal co1_6: std_logic;
+    signal rcount_w4: std_logic;
+    signal rcount_w5: std_logic;
+    signal af_setcount_4: std_logic;
+    signal af_setcount_5: std_logic;
+    signal co2_6: std_logic;
+    signal r_g2b_xor_cluster_0: std_logic;
+    signal rcount_w7: std_logic;
+    signal af_setcount_6: std_logic;
+    signal af_setcount_7: std_logic;
+    signal co3_6: std_logic;
+    signal rcount_w8: std_logic;
+    signal af_set_cmp_clr: std_logic;
+    signal af_setcount_8: std_logic;
+    signal af_set_cmp_set: std_logic;
+    signal af_set: std_logic;
+    signal af_set_c: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component AGEB2
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; GE: out  std_logic);
+    end component;
+    component AND2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component CU2
+        port (CI: in  std_logic; PC0: in  std_logic; PC1: in  std_logic; 
+            CO: out  std_logic; NC0: out  std_logic; NC1: out  std_logic);
+    end component;
+    component FADD2B
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; COUT: out  std_logic; 
+            S0: out  std_logic; S1: out  std_logic);
+    end component;
+    component FSUB2B
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; BI: in  std_logic; BOUT: out  std_logic; 
+            S0: out  std_logic; S1: out  std_logic);
+    end component;
+    component FD1P3BX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            PD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1P3DX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            CD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1S3BX
+        port (D: in  std_logic; CK: in  std_logic; PD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component FD1S3DX
+        port (D: in  std_logic; CK: in  std_logic; CD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component INV
+        port (A: in  std_logic; Z: out  std_logic);
+    end component;
+    component OR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component ROM16X1A
+        generic (INITVAL : in std_logic_vector(15 downto 0));
+        port (AD3: in  std_logic; AD2: in  std_logic; AD1: in  std_logic; 
+            AD0: in  std_logic; DO0: out  std_logic);
+    end component;
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component XOR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component PDPW16KC
+        generic (GSR : in String; CSDECODE_R : in String; 
+                CSDECODE_W : in String; REGMODE : in String; 
+                DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+        port (DI0: in  std_logic; DI1: in  std_logic; DI2: in  std_logic; 
+            DI3: in  std_logic; DI4: in  std_logic; DI5: in  std_logic; 
+            DI6: in  std_logic; DI7: in  std_logic; DI8: in  std_logic; 
+            DI9: in  std_logic; DI10: in  std_logic; DI11: in  std_logic; 
+            DI12: in  std_logic; DI13: in  std_logic; 
+            DI14: in  std_logic; DI15: in  std_logic; 
+            DI16: in  std_logic; DI17: in  std_logic; 
+            DI18: in  std_logic; DI19: in  std_logic; 
+            DI20: in  std_logic; DI21: in  std_logic; 
+            DI22: in  std_logic; DI23: in  std_logic; 
+            DI24: in  std_logic; DI25: in  std_logic; 
+            DI26: in  std_logic; DI27: in  std_logic; 
+            DI28: in  std_logic; DI29: in  std_logic; 
+            DI30: in  std_logic; DI31: in  std_logic; 
+            DI32: in  std_logic; DI33: in  std_logic; 
+            DI34: in  std_logic; DI35: in  std_logic; 
+            ADW0: in  std_logic; ADW1: in  std_logic; 
+            ADW2: in  std_logic; ADW3: in  std_logic; 
+            ADW4: in  std_logic; ADW5: in  std_logic; 
+            ADW6: in  std_logic; ADW7: in  std_logic; 
+            ADW8: in  std_logic; BE0: in  std_logic; BE1: in  std_logic; 
+            BE2: in  std_logic; BE3: in  std_logic; CEW: in  std_logic; 
+            CLKW: in  std_logic; CSW0: in  std_logic; 
+            CSW1: in  std_logic; CSW2: in  std_logic; 
+            ADR0: in  std_logic; ADR1: in  std_logic; 
+            ADR2: in  std_logic; ADR3: in  std_logic; 
+            ADR4: in  std_logic; ADR5: in  std_logic; 
+            ADR6: in  std_logic; ADR7: in  std_logic; 
+            ADR8: in  std_logic; ADR9: in  std_logic; 
+            ADR10: in  std_logic; ADR11: in  std_logic; 
+            ADR12: in  std_logic; ADR13: in  std_logic; 
+            CER: in  std_logic; CLKR: in  std_logic; CSR0: in  std_logic; 
+            CSR1: in  std_logic; CSR2: in  std_logic; RST: in  std_logic; 
+            DO0: out  std_logic; DO1: out  std_logic; 
+            DO2: out  std_logic; DO3: out  std_logic; 
+            DO4: out  std_logic; DO5: out  std_logic; 
+            DO6: out  std_logic; DO7: out  std_logic; 
+            DO8: out  std_logic; DO9: out  std_logic; 
+            DO10: out  std_logic; DO11: out  std_logic; 
+            DO12: out  std_logic; DO13: out  std_logic; 
+            DO14: out  std_logic; DO15: out  std_logic; 
+            DO16: out  std_logic; DO17: out  std_logic; 
+            DO18: out  std_logic; DO19: out  std_logic; 
+            DO20: out  std_logic; DO21: out  std_logic; 
+            DO22: out  std_logic; DO23: out  std_logic; 
+            DO24: out  std_logic; DO25: out  std_logic; 
+            DO26: out  std_logic; DO27: out  std_logic; 
+            DO28: out  std_logic; DO29: out  std_logic; 
+            DO30: out  std_logic; DO31: out  std_logic; 
+            DO32: out  std_logic; DO33: out  std_logic; 
+            DO34: out  std_logic; DO35: out  std_logic);
+    end component;
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute RESETMODE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "async_fifo_nn_thfull_512x36_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+    attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
+    attribute GSR of FF_122 : label is "ENABLED";
+    attribute GSR of FF_121 : label is "ENABLED";
+    attribute GSR of FF_120 : label is "ENABLED";
+    attribute GSR of FF_119 : label is "ENABLED";
+    attribute GSR of FF_118 : label is "ENABLED";
+    attribute GSR of FF_117 : label is "ENABLED";
+    attribute GSR of FF_116 : label is "ENABLED";
+    attribute GSR of FF_115 : label is "ENABLED";
+    attribute GSR of FF_114 : label is "ENABLED";
+    attribute GSR of FF_113 : label is "ENABLED";
+    attribute GSR of FF_112 : label is "ENABLED";
+    attribute GSR of FF_111 : label is "ENABLED";
+    attribute GSR of FF_110 : label is "ENABLED";
+    attribute GSR of FF_109 : label is "ENABLED";
+    attribute GSR of FF_108 : label is "ENABLED";
+    attribute GSR of FF_107 : label is "ENABLED";
+    attribute GSR of FF_106 : label is "ENABLED";
+    attribute GSR of FF_105 : label is "ENABLED";
+    attribute GSR of FF_104 : label is "ENABLED";
+    attribute GSR of FF_103 : label is "ENABLED";
+    attribute GSR of FF_102 : label is "ENABLED";
+    attribute GSR of FF_101 : label is "ENABLED";
+    attribute GSR of FF_100 : label is "ENABLED";
+    attribute GSR of FF_99 : label is "ENABLED";
+    attribute GSR of FF_98 : label is "ENABLED";
+    attribute GSR of FF_97 : label is "ENABLED";
+    attribute GSR of FF_96 : label is "ENABLED";
+    attribute GSR of FF_95 : label is "ENABLED";
+    attribute GSR of FF_94 : label is "ENABLED";
+    attribute GSR of FF_93 : label is "ENABLED";
+    attribute GSR of FF_92 : label is "ENABLED";
+    attribute GSR of FF_91 : label is "ENABLED";
+    attribute GSR of FF_90 : label is "ENABLED";
+    attribute GSR of FF_89 : label is "ENABLED";
+    attribute GSR of FF_88 : label is "ENABLED";
+    attribute GSR of FF_87 : label is "ENABLED";
+    attribute GSR of FF_86 : label is "ENABLED";
+    attribute GSR of FF_85 : label is "ENABLED";
+    attribute GSR of FF_84 : label is "ENABLED";
+    attribute GSR of FF_83 : label is "ENABLED";
+    attribute GSR of FF_82 : label is "ENABLED";
+    attribute GSR of FF_81 : label is "ENABLED";
+    attribute GSR of FF_80 : label is "ENABLED";
+    attribute GSR of FF_79 : label is "ENABLED";
+    attribute GSR of FF_78 : label is "ENABLED";
+    attribute GSR of FF_77 : label is "ENABLED";
+    attribute GSR of FF_76 : label is "ENABLED";
+    attribute GSR of FF_75 : label is "ENABLED";
+    attribute GSR of FF_74 : label is "ENABLED";
+    attribute GSR of FF_73 : label is "ENABLED";
+    attribute GSR of FF_72 : label is "ENABLED";
+    attribute GSR of FF_71 : label is "ENABLED";
+    attribute GSR of FF_70 : label is "ENABLED";
+    attribute GSR of FF_69 : label is "ENABLED";
+    attribute GSR of FF_68 : label is "ENABLED";
+    attribute GSR of FF_67 : label is "ENABLED";
+    attribute GSR of FF_66 : label is "ENABLED";
+    attribute GSR of FF_65 : label is "ENABLED";
+    attribute GSR of FF_64 : label is "ENABLED";
+    attribute GSR of FF_63 : label is "ENABLED";
+    attribute GSR of FF_62 : label is "ENABLED";
+    attribute GSR of FF_61 : label is "ENABLED";
+    attribute GSR of FF_60 : label is "ENABLED";
+    attribute GSR of FF_59 : label is "ENABLED";
+    attribute GSR of FF_58 : label is "ENABLED";
+    attribute GSR of FF_57 : label is "ENABLED";
+    attribute GSR of FF_56 : label is "ENABLED";
+    attribute GSR of FF_55 : label is "ENABLED";
+    attribute GSR of FF_54 : label is "ENABLED";
+    attribute GSR of FF_53 : label is "ENABLED";
+    attribute GSR of FF_52 : label is "ENABLED";
+    attribute GSR of FF_51 : label is "ENABLED";
+    attribute GSR of FF_50 : label is "ENABLED";
+    attribute GSR of FF_49 : label is "ENABLED";
+    attribute GSR of FF_48 : label is "ENABLED";
+    attribute GSR of FF_47 : label is "ENABLED";
+    attribute GSR of FF_46 : label is "ENABLED";
+    attribute GSR of FF_45 : label is "ENABLED";
+    attribute GSR of FF_44 : label is "ENABLED";
+    attribute GSR of FF_43 : label is "ENABLED";
+    attribute GSR of FF_42 : label is "ENABLED";
+    attribute GSR of FF_41 : label is "ENABLED";
+    attribute GSR of FF_40 : label is "ENABLED";
+    attribute GSR of FF_39 : label is "ENABLED";
+    attribute GSR of FF_38 : label is "ENABLED";
+    attribute GSR of FF_37 : label is "ENABLED";
+    attribute GSR of FF_36 : label is "ENABLED";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t21: AND2
+        port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+    INV_1: INV
+        port map (A=>full_i, Z=>invout_1);
+
+    AND2_t20: AND2
+        port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+    INV_0: INV
+        port map (A=>empty_i, Z=>invout_0);
+
+    OR2_t19: OR2
+        port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+    XOR2_t18: XOR2
+        port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+    XOR2_t17: XOR2
+        port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+    XOR2_t16: XOR2
+        port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+    XOR2_t15: XOR2
+        port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+    XOR2_t14: XOR2
+        port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+    XOR2_t13: XOR2
+        port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
+
+    XOR2_t12: XOR2
+        port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
+
+    XOR2_t11: XOR2
+        port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
+
+    XOR2_t10: XOR2
+        port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
+
+    XOR2_t9: XOR2
+        port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+    XOR2_t8: XOR2
+        port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+    XOR2_t7: XOR2
+        port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+    XOR2_t6: XOR2
+        port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+    XOR2_t5: XOR2
+        port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+    XOR2_t4: XOR2
+        port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
+
+    XOR2_t3: XOR2
+        port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
+
+    XOR2_t2: XOR2
+        port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
+
+    XOR2_t1: XOR2
+        port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
+
+    LUT4_25: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, 
+            AD1=>w_gcount_r28, AD0=>w_gcount_r29, 
+            DO0=>w_g2b_xor_cluster_0);
+
+    LUT4_24: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, 
+            AD1=>w_gcount_r24, AD0=>w_gcount_r25, 
+            DO0=>w_g2b_xor_cluster_1);
+
+    LUT4_23: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>wcount_r8);
+
+    LUT4_22: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, 
+            AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7);
+
+    LUT4_21: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, 
+            AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
+
+    LUT4_20: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, 
+            AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
+
+    LUT4_19: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, 
+            AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3);
+
+    LUT4_18: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2);
+
+    LUT4_17: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1);
+
+    LUT4_16: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
+            AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0);
+
+    LUT4_15: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, 
+            AD1=>r_gcount_w28, AD0=>r_gcount_w29, 
+            DO0=>r_g2b_xor_cluster_0);
+
+    LUT4_14: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, 
+            AD1=>r_gcount_w24, AD0=>r_gcount_w25, 
+            DO0=>r_g2b_xor_cluster_1);
+
+    LUT4_13: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>rcount_w8);
+
+    LUT4_12: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, 
+            AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7);
+
+    LUT4_11: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, 
+            AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
+
+    LUT4_10: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, 
+            AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
+
+    LUT4_9: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, 
+            AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3);
+
+    LUT4_8: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2);
+
+    LUT4_7: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1);
+
+    LUT4_6: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
+            AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0);
+
+    XOR2_t0: XOR2
+        port map (A=>w_gcount_r29, B=>rptr_9, Z=>rfill_sub_msb);
+
+    LUT4_5: ROM16X1A
+        generic map (initval=> X"0410")
+        port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+    LUT4_4: ROM16X1A
+        generic map (initval=> X"1004")
+        port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+    LUT4_3: ROM16X1A
+        generic map (initval=> X"0140")
+        port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, 
+            AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+    LUT4_2: ROM16X1A
+        generic map (initval=> X"4001")
+        port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, 
+            AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"4c32")
+        port map (AD3=>af_setcount_9, AD2=>wcount_9, AD1=>r_gcount_w29, 
+            AD0=>wptr_9, DO0=>af_set_cmp_set);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"8001")
+        port map (AD3=>af_setcount_9, AD2=>wcount_9, AD1=>r_gcount_w29, 
+            AD0=>wptr_9, DO0=>af_set_cmp_clr);
+
+    pdp_ram_0_0_0: PDPW16KC
+        generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", 
+        REGMODE=> "NOREG", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
+        port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), 
+            DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), 
+            DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), 
+            DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), 
+            DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), 
+            DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), 
+            DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), 
+            DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), 
+            DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), 
+            DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), 
+            DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0, 
+            ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4, 
+            ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>wptr_8, 
+            BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, 
+            BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, 
+            CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, 
+            ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, 
+            ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, 
+            ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, 
+            ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock, 
+            CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, 
+            RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), 
+            DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), 
+            DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), 
+            DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), DO16=>Q(34), 
+            DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), 
+            DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), 
+            DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), 
+            DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), 
+            DO35=>Q(17));
+
+    FF_122: FD1P3BX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>wcount_0);
+
+    FF_121: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_120: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_119: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_118: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_117: FD1P3DX
+        port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_116: FD1P3DX
+        port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_6);
+
+    FF_115: FD1P3DX
+        port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_7);
+
+    FF_114: FD1P3DX
+        port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_8);
+
+    FF_113: FD1P3DX
+        port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_9);
+
+    FF_112: FD1P3DX
+        port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_0);
+
+    FF_111: FD1P3DX
+        port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_1);
+
+    FF_110: FD1P3DX
+        port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_2);
+
+    FF_109: FD1P3DX
+        port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_3);
+
+    FF_108: FD1P3DX
+        port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_4);
+
+    FF_107: FD1P3DX
+        port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_5);
+
+    FF_106: FD1P3DX
+        port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_6);
+
+    FF_105: FD1P3DX
+        port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_7);
+
+    FF_104: FD1P3DX
+        port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_8);
+
+    FF_103: FD1P3DX
+        port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_9);
+
+    FF_102: FD1P3DX
+        port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_0);
+
+    FF_101: FD1P3DX
+        port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_1);
+
+    FF_100: FD1P3DX
+        port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_2);
+
+    FF_99: FD1P3DX
+        port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_3);
+
+    FF_98: FD1P3DX
+        port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_4);
+
+    FF_97: FD1P3DX
+        port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_5);
+
+    FF_96: FD1P3DX
+        port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_6);
+
+    FF_95: FD1P3DX
+        port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_7);
+
+    FF_94: FD1P3DX
+        port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_8);
+
+    FF_93: FD1P3DX
+        port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_9);
+
+    FF_92: FD1P3BX
+        port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, 
+            Q=>rcount_0);
+
+    FF_91: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_1);
+
+    FF_90: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_2);
+
+    FF_89: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_3);
+
+    FF_88: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_4);
+
+    FF_87: FD1P3DX
+        port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_5);
+
+    FF_86: FD1P3DX
+        port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_6);
+
+    FF_85: FD1P3DX
+        port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_7);
+
+    FF_84: FD1P3DX
+        port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_8);
+
+    FF_83: FD1P3DX
+        port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_9);
+
+    FF_82: FD1P3DX
+        port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_0);
+
+    FF_81: FD1P3DX
+        port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_1);
+
+    FF_80: FD1P3DX
+        port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_2);
+
+    FF_79: FD1P3DX
+        port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_3);
+
+    FF_78: FD1P3DX
+        port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_4);
+
+    FF_77: FD1P3DX
+        port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_5);
+
+    FF_76: FD1P3DX
+        port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_6);
+
+    FF_75: FD1P3DX
+        port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_7);
+
+    FF_74: FD1P3DX
+        port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_8);
+
+    FF_73: FD1P3DX
+        port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_9);
+
+    FF_72: FD1P3DX
+        port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_0);
+
+    FF_71: FD1P3DX
+        port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_1);
+
+    FF_70: FD1P3DX
+        port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_2);
+
+    FF_69: FD1P3DX
+        port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_3);
+
+    FF_68: FD1P3DX
+        port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_4);
+
+    FF_67: FD1P3DX
+        port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_5);
+
+    FF_66: FD1P3DX
+        port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_6);
+
+    FF_65: FD1P3DX
+        port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_7);
+
+    FF_64: FD1P3DX
+        port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_8);
+
+    FF_63: FD1P3DX
+        port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_9);
+
+    FF_62: FD1S3DX
+        port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+    FF_61: FD1S3DX
+        port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+    FF_60: FD1S3DX
+        port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+    FF_59: FD1S3DX
+        port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+    FF_58: FD1S3DX
+        port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+    FF_57: FD1S3DX
+        port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+    FF_56: FD1S3DX
+        port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
+
+    FF_55: FD1S3DX
+        port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
+
+    FF_54: FD1S3DX
+        port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
+
+    FF_53: FD1S3DX
+        port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
+
+    FF_52: FD1S3DX
+        port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+    FF_51: FD1S3DX
+        port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+    FF_50: FD1S3DX
+        port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+    FF_49: FD1S3DX
+        port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+    FF_48: FD1S3DX
+        port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+    FF_47: FD1S3DX
+        port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+    FF_46: FD1S3DX
+        port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+    FF_45: FD1S3DX
+        port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
+
+    FF_44: FD1S3DX
+        port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
+
+    FF_43: FD1S3DX
+        port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
+
+    FF_42: FD1S3DX
+        port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r20);
+
+    FF_41: FD1S3DX
+        port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r21);
+
+    FF_40: FD1S3DX
+        port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r22);
+
+    FF_39: FD1S3DX
+        port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r23);
+
+    FF_38: FD1S3DX
+        port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r24);
+
+    FF_37: FD1S3DX
+        port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r25);
+
+    FF_36: FD1S3DX
+        port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r26);
+
+    FF_35: FD1S3DX
+        port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r27);
+
+    FF_34: FD1S3DX
+        port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r28);
+
+    FF_33: FD1S3DX
+        port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r29);
+
+    FF_32: FD1S3DX
+        port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+    FF_31: FD1S3DX
+        port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+    FF_30: FD1S3DX
+        port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+    FF_29: FD1S3DX
+        port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+    FF_28: FD1S3DX
+        port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+    FF_27: FD1S3DX
+        port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+    FF_26: FD1S3DX
+        port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
+
+    FF_25: FD1S3DX
+        port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
+
+    FF_24: FD1S3DX
+        port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
+
+    FF_23: FD1S3DX
+        port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
+
+    FF_22: FD1S3DX
+        port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0));
+
+    FF_21: FD1S3DX
+        port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1));
+
+    FF_20: FD1S3DX
+        port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2));
+
+    FF_19: FD1S3DX
+        port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3));
+
+    FF_18: FD1S3DX
+        port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4));
+
+    FF_17: FD1S3DX
+        port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5));
+
+    FF_16: FD1S3DX
+        port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6));
+
+    FF_15: FD1S3DX
+        port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7));
+
+    FF_14: FD1S3DX
+        port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8));
+
+    FF_13: FD1S3DX
+        port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9));
+
+    FF_12: FD1S3BX
+        port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+    FF_11: FD1S3DX
+        port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+    FF_10: FD1P3BX
+        port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>af_setcount_0);
+
+    FF_9: FD1P3BX
+        port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>af_setcount_1);
+
+    FF_8: FD1P3BX
+        port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>af_setcount_2);
+
+    FF_7: FD1P3DX
+        port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_3);
+
+    FF_6: FD1P3DX
+        port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_4);
+
+    FF_5: FD1P3DX
+        port map (D=>iaf_setcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_5);
+
+    FF_4: FD1P3DX
+        port map (D=>iaf_setcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_6);
+
+    FF_3: FD1P3BX
+        port map (D=>iaf_setcount_7, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>af_setcount_7);
+
+    FF_2: FD1P3DX
+        port map (D=>iaf_setcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_8);
+
+    FF_1: FD1P3DX
+        port map (D=>iaf_setcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>af_setcount_9);
+
+    FF_0: FD1S3DX
+        port map (D=>af_set, CK=>WrClock, CD=>Reset, Q=>AlmostFull);
+
+    w_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, 
+            S1=>open);
+
+    w_gctr_0: CU2
+        port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, 
+            NC0=>iwcount_0, NC1=>iwcount_1);
+
+    w_gctr_1: CU2
+        port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, 
+            NC0=>iwcount_2, NC1=>iwcount_3);
+
+    w_gctr_2: CU2
+        port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, 
+            NC0=>iwcount_4, NC1=>iwcount_5);
+
+    w_gctr_3: CU2
+        port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, 
+            NC0=>iwcount_6, NC1=>iwcount_7);
+
+    w_gctr_4: CU2
+        port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, 
+            NC0=>iwcount_8, NC1=>iwcount_9);
+
+    r_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, 
+            S1=>open);
+
+    r_gctr_0: CU2
+        port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, 
+            NC0=>ircount_0, NC1=>ircount_1);
+
+    r_gctr_1: CU2
+        port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, 
+            NC0=>ircount_2, NC1=>ircount_3);
+
+    r_gctr_2: CU2
+        port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, 
+            NC0=>ircount_4, NC1=>ircount_5);
+
+    r_gctr_3: CU2
+        port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, 
+            NC0=>ircount_6, NC1=>ircount_7);
+
+    r_gctr_4: CU2
+        port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, 
+            NC0=>ircount_8, NC1=>ircount_9);
+
+    precin_inst287: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin, S0=>open, 
+            S1=>open);
+
+    rfill_0: FSUB2B
+        port map (A0=>scuba_vhi, A1=>wcount_r0, B0=>scuba_vlo, 
+            B1=>rptr_0, BI=>precin, BOUT=>co0_2, S0=>open, 
+            S1=>rfill_sub_0);
+
+    rfill_1: FSUB2B
+        port map (A0=>wcount_r1, A1=>wcount_r2, B0=>rptr_1, B1=>rptr_2, 
+            BI=>co0_2, BOUT=>co1_2, S0=>rfill_sub_1, S1=>rfill_sub_2);
+
+    rfill_2: FSUB2B
+        port map (A0=>wcount_r3, A1=>wcount_r4, B0=>rptr_3, B1=>rptr_4, 
+            BI=>co1_2, BOUT=>co2_2, S0=>rfill_sub_3, S1=>rfill_sub_4);
+
+    rfill_3: FSUB2B
+        port map (A0=>wcount_r5, A1=>w_g2b_xor_cluster_0, B0=>rptr_5, 
+            B1=>rptr_6, BI=>co2_2, BOUT=>co3_2, S0=>rfill_sub_5, 
+            S1=>rfill_sub_6);
+
+    rfill_4: FSUB2B
+        port map (A0=>wcount_r7, A1=>wcount_r8, B0=>rptr_7, B1=>rptr_8, 
+            BI=>co3_2, BOUT=>co4_2, S0=>rfill_sub_7, S1=>rfill_sub_8);
+
+    rfill_5: FSUB2B
+        port map (A0=>rfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, BI=>co4_2, BOUT=>open, S0=>rfill_sub_9, 
+            S1=>open);
+
+    empty_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+    empty_cmp_0: AGEB2
+        port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, 
+            B1=>wcount_r1, CI=>cmp_ci, GE=>co0_3);
+
+    empty_cmp_1: AGEB2
+        port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, 
+            B1=>wcount_r3, CI=>co0_3, GE=>co1_3);
+
+    empty_cmp_2: AGEB2
+        port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, 
+            B1=>wcount_r5, CI=>co1_3, GE=>co2_3);
+
+    empty_cmp_3: AGEB2
+        port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0, 
+            B1=>wcount_r7, CI=>co2_3, GE=>co3_3);
+
+    empty_cmp_4: AGEB2
+        port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8, 
+            B1=>empty_cmp_clr, CI=>co3_3, GE=>empty_d_c);
+
+    a0: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, 
+            S1=>open);
+
+    full_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+    full_cmp_0: AGEB2
+        port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, 
+            B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_4);
+
+    full_cmp_1: AGEB2
+        port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, 
+            B1=>rcount_w3, CI=>co0_4, GE=>co1_4);
+
+    full_cmp_2: AGEB2
+        port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, 
+            B1=>rcount_w5, CI=>co1_4, GE=>co2_4);
+
+    full_cmp_3: AGEB2
+        port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, 
+            B1=>rcount_w7, CI=>co2_4, GE=>co3_4);
+
+    full_cmp_4: AGEB2
+        port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8, 
+            B1=>full_cmp_clr, CI=>co3_4, GE=>full_d_c);
+
+    a1: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, 
+            S1=>open);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    af_set_ctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_set_ctr_ci, S0=>open, 
+            S1=>open);
+
+    af_set_ctr_0: CU2
+        port map (CI=>af_set_ctr_ci, PC0=>af_setcount_0, 
+            PC1=>af_setcount_1, CO=>co0_5, NC0=>iaf_setcount_0, 
+            NC1=>iaf_setcount_1);
+
+    af_set_ctr_1: CU2
+        port map (CI=>co0_5, PC0=>af_setcount_2, PC1=>af_setcount_3, 
+            CO=>co1_5, NC0=>iaf_setcount_2, NC1=>iaf_setcount_3);
+
+    af_set_ctr_2: CU2
+        port map (CI=>co1_5, PC0=>af_setcount_4, PC1=>af_setcount_5, 
+            CO=>co2_5, NC0=>iaf_setcount_4, NC1=>iaf_setcount_5);
+
+    af_set_ctr_3: CU2
+        port map (CI=>co2_5, PC0=>af_setcount_6, PC1=>af_setcount_7, 
+            CO=>co3_5, NC0=>iaf_setcount_6, NC1=>iaf_setcount_7);
+
+    af_set_ctr_4: CU2
+        port map (CI=>co3_5, PC0=>af_setcount_8, PC1=>af_setcount_9, 
+            CO=>co4_3, NC0=>iaf_setcount_8, NC1=>iaf_setcount_9);
+
+    af_set_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
+
+    af_set_cmp_0: AGEB2
+        port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0, 
+            B1=>rcount_w1, CI=>cmp_ci_2, GE=>co0_6);
+
+    af_set_cmp_1: AGEB2
+        port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>rcount_w2, 
+            B1=>rcount_w3, CI=>co0_6, GE=>co1_6);
+
+    af_set_cmp_2: AGEB2
+        port map (A0=>af_setcount_4, A1=>af_setcount_5, B0=>rcount_w4, 
+            B1=>rcount_w5, CI=>co1_6, GE=>co2_6);
+
+    af_set_cmp_3: AGEB2
+        port map (A0=>af_setcount_6, A1=>af_setcount_7, 
+            B0=>r_g2b_xor_cluster_0, B1=>rcount_w7, CI=>co2_6, GE=>co3_6);
+
+    af_set_cmp_4: AGEB2
+        port map (A0=>af_setcount_8, A1=>af_set_cmp_set, B0=>rcount_w8, 
+            B1=>af_set_cmp_clr, CI=>co3_6, GE=>af_set_c);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    a2: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set, 
+            S1=>open);
+
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of async_fifo_nn_thfull_512x36_ecp3 is
+    for Structure
+        for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+        for all:AND2 use entity ecp3.AND2(V); end for;
+        for all:CU2 use entity ecp3.CU2(V); end for;
+        for all:FADD2B use entity ecp3.FADD2B(V); end for;
+        for all:FSUB2B use entity ecp3.FSUB2B(V); end for;
+        for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
+        for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+        for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+        for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+        for all:INV use entity ecp3.INV(V); end for;
+        for all:OR2 use entity ecp3.OR2(V); end for;
+        for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+        for all:VHI use entity ecp3.VHI(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+        for all:XOR2 use entity ecp3.XOR2(V); end for;
+        for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_nn_thfull_512x36_ecp3_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_thfull_512x36_ecp3_tmpl.vhd
new file mode 100644
index 0000000..059e655
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_thfull_512x36_ecp3_tmpl.vhd
@@ -0,0 +1,19 @@
+-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.7
+-- Wed Sep 24 15:27:28 2014
+
+-- parameterized module component declaration
+component async_fifo_nn_thfull_512x36_ecp3
+    port (Data: in  std_logic_vector(35 downto 0); 
+        WrClock: in  std_logic; RdClock: in  std_logic; 
+        WrEn: in  std_logic; RdEn: in  std_logic; Reset: in  std_logic; 
+        RPReset: in  std_logic; Q: out  std_logic_vector(35 downto 0); 
+        RCNT: out  std_logic_vector(9 downto 0); Empty: out  std_logic; 
+        Full: out  std_logic; AlmostFull: out  std_logic);
+end component;
+
+-- parameterized module component instance
+__ : async_fifo_nn_thfull_512x36_ecp3
+    port map (Data(35 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, 
+        RdEn=>__, Reset=>__, RPReset=>__, Q(35 downto 0)=>__, RCNT(9 downto 0)=>__, 
+        Empty=>__, Full=>__, AlmostFull=>__);
diff --git a/data_concentrator/sources/lattice/ecp3/async_fifo_nn_thfull_512x36_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_thfull_512x36_tmpl.vhd
new file mode 100644
index 0000000..d0bda1c
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/async_fifo_nn_thfull_512x36_tmpl.vhd
@@ -0,0 +1,19 @@
+-- VHDL module instantiation generated by SCUBA Diamond_2.1_Production (100)
+-- Module  Version: 5.4
+-- Fri Jul 12 15:20:53 2013
+
+-- parameterized module component declaration
+component async_fifo_nn_thfull_512x36
+    port (Data: in  std_logic_vector(35 downto 0); 
+        WrClock: in  std_logic; RdClock: in  std_logic; 
+        WrEn: in  std_logic; RdEn: in  std_logic; Reset: in  std_logic; 
+        RPReset: in  std_logic; Q: out  std_logic_vector(35 downto 0); 
+        RCNT: out  std_logic_vector(9 downto 0); Empty: out  std_logic; 
+        Full: out  std_logic; AlmostFull: out  std_logic);
+end component;
+
+-- parameterized module component instance
+__ : async_fifo_nn_thfull_512x36
+    port map (Data(35 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, 
+        RdEn=>__, Reset=>__, RPReset=>__, Q(35 downto 0)=>__, RCNT(9 downto 0)=>__, 
+        Empty=>__, Full=>__, AlmostFull=>__);
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in100_out80M.ipx b/data_concentrator/sources/lattice/ecp3/pll_in100_out80M.ipx
new file mode 100644
index 0000000..f6bdf36
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in100_out80M.ipx
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_in100_out80M" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 11 20 10:46:31.774" version="5.6" type="IP" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="pll_in100_out80M.lpc" type="lpc" modified="2014 11 20 10:46:29.847"/>
+  </Package>
+</DiamondModule>
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in100_out80M.lpc b/data_concentrator/sources/lattice/ecp3/pll_in100_out80M.lpc
new file mode 100644
index 0000000..199976c
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in100_out80M.lpc
@@ -0,0 +1,69 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.6
+ModuleName=pll_in100_out80M
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=11/20/2014
+Time=10:46:29
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=100
+Div=5
+ClkOPBp=0
+Post=4
+U_OFrq=160
+OP_Tol=0.0
+OFrq=160.000000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=CLKOP
+Mult=8
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Static
+CLKOK_INPUT=CLKOP
+SecD=2
+U_KFrq=80
+OK_Tol=0.0
+KFrq=80.000000
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=3.424318
+;DelayControl=No
+EnCLKOS=0
+ClkOSBp=0
+EnCLKOK=1
+ClkOKBp=0
+enClkOK2=1
+
+[Command]
+cmd_line= -w -n pll_in100_out80M -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 100 -phase_cntl STATIC -fclkop 160 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -fclkok 80 -fclkok_tol 0.0 -clkoki 0 -norst -bw
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in100_out80M.vhd b/data_concentrator/sources/lattice/ecp3/pll_in100_out80M.vhd
new file mode 100644
index 0000000..3b64233
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in100_out80M.vhd
@@ -0,0 +1,105 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.6
+--C:\Lattice\diamond\3.2_x64\ispfpga\bin\nt64\scuba.exe -w -n pll_in100_out80M -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 100 -phase_cntl STATIC -fclkop 160 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -fclkok 80 -fclkok_tol 0.0 -clkoki 0 -norst -bw 
+
+-- Thu Nov 20 10:46:29 2014
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity pll_in100_out80M is
+    port (
+        CLK: in std_logic; 
+        CLKOP: out std_logic; 
+        CLKOK: out std_logic; 
+        CLKOK2: out std_logic; 
+        LOCK: out std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of pll_in100_out80M : entity is true;
+end pll_in100_out80M;
+
+architecture Structure of pll_in100_out80M is
+
+    -- internal signal declarations
+    signal CLKOP_t: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component EHXPLLF
+        generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; 
+                DELAY_PWD : in String; DELAY_VAL : in Integer; 
+                CLKOS_TRIM_DELAY : in Integer; 
+                CLKOS_TRIM_POL : in String; 
+                CLKOP_TRIM_DELAY : in Integer; 
+                CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; 
+                CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; 
+                PHASE_DELAY_CNTL : in String; DUTY : in Integer; 
+                PHASEADJ : in String; CLKOK_DIV : in Integer; 
+                CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; 
+                CLKI_DIV : in Integer; FIN : in String);
+        port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; 
+            RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; 
+            DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; 
+            DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; 
+            DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; 
+            FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; 
+            CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; 
+            LOCK: out std_logic; CLKINTFB: out std_logic);
+    end component;
+    component VLO
+        port (Z: out std_logic);
+    end component;
+    attribute FREQUENCY_PIN_CLKOK2 : string; 
+    attribute FREQUENCY_PIN_CLKOP : string; 
+    attribute FREQUENCY_PIN_CLKI : string; 
+    attribute FREQUENCY_PIN_CLKOK : string; 
+    attribute FREQUENCY_PIN_CLKOK2 of PLLInst_0 : label is "53.333333";
+    attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "160.000000";
+    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000";
+    attribute FREQUENCY_PIN_CLKOK of PLLInst_0 : label is "80.000000";
+    attribute syn_keep : boolean;
+    attribute syn_noprune : boolean;
+    attribute syn_noprune of Structure : architecture is true;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    PLLInst_0: EHXPLLF
+        generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", 
+        CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", 
+        CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=>  0, 
+        CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "RISING", 
+        CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "RISING", 
+        PHASE_DELAY_CNTL=> "STATIC", DUTY=>  8, PHASEADJ=> "0.0", 
+        CLKOK_DIV=>  2, CLKOP_DIV=>  4, CLKFB_DIV=>  8, CLKI_DIV=>  5, 
+        FIN=> "100.000000")
+        port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, 
+            RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, 
+            DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, 
+            DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, 
+            DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, 
+            FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, 
+            CLKOS=>open, CLKOK=>CLKOK, CLKOK2=>CLKOK2, LOCK=>LOCK, 
+            CLKINTFB=>open);
+
+    CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of pll_in100_out80M is
+    for Structure
+        for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in100_out80M_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/pll_in100_out80M_tmpl.vhd
new file mode 100644
index 0000000..9d7622e
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in100_out80M_tmpl.vhd
@@ -0,0 +1,13 @@
+-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.6
+-- Thu Nov 20 10:46:29 2014
+
+-- parameterized module component declaration
+component pll_in100_out80M
+    port (CLK: in std_logic; CLKOP: out std_logic; CLKOK: out std_logic; 
+        CLKOK2: out std_logic; LOCK: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : pll_in100_out80M
+    port map (CLK=>__, CLKOP=>__, CLKOK=>__, CLKOK2=>__, LOCK=>__);
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in125_out125_62M5.ipx b/data_concentrator/sources/lattice/ecp3/pll_in125_out125_62M5.ipx
new file mode 100644
index 0000000..73ea605
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in125_out125_62M5.ipx
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_in125_out125_62M5" module="pll_in125_out125_62M5" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 08 29 10:45:48.914" version="5.6" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="pll_in125_out125_62M5.lpc" type="lpc" modified="2014 08 29 10:45:47.201"/>
+		<File name="pll_in125_out125_62M5.vhd" type="top_level_vhdl" modified="2014 08 29 10:45:47.262"/>
+		<File name="pll_in125_out125_62M5_tmpl.vhd" type="template_vhdl" modified="2014 08 29 10:45:47.263"/>
+  </Package>
+</DiamondModule>
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in125_out125_62M5.lpc b/data_concentrator/sources/lattice/ecp3/pll_in125_out125_62M5.lpc
new file mode 100644
index 0000000..52d1e70
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in125_out125_62M5.lpc
@@ -0,0 +1,69 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.6
+ModuleName=pll_in125_out125_62M5
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=08/29/2014
+Time=10:45:47
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=125
+Div=1
+ClkOPBp=0
+Post=8
+U_OFrq=125
+OP_Tol=0.0
+OFrq=125.000000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=Internal
+Mult=1
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Static
+CLKOK_INPUT=CLKOP
+SecD=2
+U_KFrq=62.5
+OK_Tol=0.0
+KFrq=62.500000
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=1.485393
+;DelayControl=No
+EnCLKOS=0
+ClkOSBp=0
+EnCLKOK=1
+ClkOKBp=0
+enClkOK2=0
+
+[Command]
+cmd_line= -w -n pll_in125_out125_62M5 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 125 -fclkop_tol 0.0 -fb_mode INTERNAL -noclkos -fclkok 62.5 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in125_out125_62M5.vhd b/data_concentrator/sources/lattice/ecp3/pll_in125_out125_62M5.vhd
new file mode 100644
index 0000000..55ade2d
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in125_out125_62M5.vhd
@@ -0,0 +1,103 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.6
+--C:\Lattice\diamond\3.2_x64\ispfpga\bin\nt64\scuba.exe -w -n pll_in125_out125_62M5 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 125 -fclkop_tol 0.0 -fb_mode INTERNAL -noclkos -fclkok 62.5 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw 
+
+-- Fri Aug 29 10:45:47 2014
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity pll_in125_out125_62M5 is
+    port (
+        CLK: in std_logic; 
+        CLKOP: out std_logic; 
+        CLKOK: out std_logic; 
+        LOCK: out std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of pll_in125_out125_62M5 : entity is true;
+end pll_in125_out125_62M5;
+
+architecture Structure of pll_in125_out125_62M5 is
+
+    -- internal signal declarations
+    signal CLKOP_t: std_logic;
+    signal CLKFB_t: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component EHXPLLF
+        generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; 
+                DELAY_PWD : in String; DELAY_VAL : in Integer; 
+                CLKOS_TRIM_DELAY : in Integer; 
+                CLKOS_TRIM_POL : in String; 
+                CLKOP_TRIM_DELAY : in Integer; 
+                CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; 
+                CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; 
+                PHASE_DELAY_CNTL : in String; DUTY : in Integer; 
+                PHASEADJ : in String; CLKOK_DIV : in Integer; 
+                CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; 
+                CLKI_DIV : in Integer; FIN : in String);
+        port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; 
+            RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; 
+            DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; 
+            DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; 
+            DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; 
+            FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; 
+            CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; 
+            LOCK: out std_logic; CLKINTFB: out std_logic);
+    end component;
+    component VLO
+        port (Z: out std_logic);
+    end component;
+    attribute FREQUENCY_PIN_CLKOP : string; 
+    attribute FREQUENCY_PIN_CLKI : string; 
+    attribute FREQUENCY_PIN_CLKOK : string; 
+    attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "125.000000";
+    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "125.000000";
+    attribute FREQUENCY_PIN_CLKOK of PLLInst_0 : label is "62.500000";
+    attribute syn_keep : boolean;
+    attribute syn_noprune : boolean;
+    attribute syn_noprune of Structure : architecture is true;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    PLLInst_0: EHXPLLF
+        generic map (FEEDBK_PATH=> "INTERNAL", CLKOK_BYPASS=> "DISABLED", 
+        CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", 
+        CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=>  0, 
+        CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "RISING", 
+        CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "RISING", 
+        PHASE_DELAY_CNTL=> "STATIC", DUTY=>  8, PHASEADJ=> "0.0", 
+        CLKOK_DIV=>  2, CLKOP_DIV=>  8, CLKFB_DIV=>  1, CLKI_DIV=>  1, 
+        FIN=> "125.000000")
+        port map (CLKI=>CLK, CLKFB=>CLKFB_t, RST=>scuba_vlo, 
+            RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, 
+            DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, 
+            DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, 
+            DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, 
+            FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, 
+            CLKOS=>open, CLKOK=>CLKOK, CLKOK2=>open, LOCK=>LOCK, 
+            CLKINTFB=>CLKFB_t);
+
+    CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of pll_in125_out125_62M5 is
+    for Structure
+        for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in125_out125_62M5_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/pll_in125_out125_62M5_tmpl.vhd
new file mode 100644
index 0000000..485313f
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in125_out125_62M5_tmpl.vhd
@@ -0,0 +1,13 @@
+-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.6
+-- Fri Aug 29 10:45:47 2014
+
+-- parameterized module component declaration
+component pll_in125_out125_62M5
+    port (CLK: in std_logic; CLKOP: out std_logic; CLKOK: out std_logic; 
+        LOCK: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : pll_in125_out125_62M5
+    port map (CLK=>__, CLKOP=>__, CLKOK=>__, LOCK=>__);
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in125_outshift.ipx b/data_concentrator/sources/lattice/ecp3/pll_in125_outshift.ipx
new file mode 100644
index 0000000..48531ae
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in125_outshift.ipx
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_in125_outshift" module="pll_in125_outshift" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 08 22 15:55:38.787" version="5.6" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="pll_in125_outshift.lpc" type="lpc" modified="2014 08 22 15:55:24.227"/>
+		<File name="pll_in125_outshift.vhd" type="top_level_vhdl" modified="2014 08 22 15:55:24.301"/>
+		<File name="pll_in125_outshift_tmpl.vhd" type="template_vhdl" modified="2014 08 22 15:55:24.301"/>
+  </Package>
+</DiamondModule>
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in125_outshift.lpc b/data_concentrator/sources/lattice/ecp3/pll_in125_outshift.lpc
new file mode 100644
index 0000000..e9ca23d
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in125_outshift.lpc
@@ -0,0 +1,69 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.6
+ModuleName=pll_in125_outshift
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=08/22/2014
+Time=15:55:24
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=125
+Div=1
+ClkOPBp=0
+Post=8
+U_OFrq=125
+OP_Tol=0.0
+OFrq=125.000000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=CLKOP
+Mult=1
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Dynamic
+CLKOK_INPUT=CLKOP
+SecD=2
+U_KFrq=50
+OK_Tol=0.0
+KFrq=
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=1.485393
+;DelayControl=No
+EnCLKOS=1
+ClkOSBp=0
+EnCLKOK=0
+ClkOKBp=0
+enClkOK2=0
+
+[Command]
+cmd_line= -w -n pll_in125_outshift -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl DYNAMIC -fclkop 125 -fclkop_tol 0.0 -fb_mode CLOCKTREE -duty50 -noclkok -norst -noclkok2 -bw
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in125_outshift.vhd b/data_concentrator/sources/lattice/ecp3/pll_in125_outshift.vhd
new file mode 100644
index 0000000..f321025
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in125_outshift.vhd
@@ -0,0 +1,120 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.6
+--C:\Lattice\diamond\3.2_x64\ispfpga\bin\nt64\scuba.exe -w -n pll_in125_outshift -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl DYNAMIC -fclkop 125 -fclkop_tol 0.0 -fb_mode CLOCKTREE -duty50 -noclkok -norst -noclkok2 -bw 
+
+-- Fri Aug 22 15:55:24 2014
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity pll_in125_outshift is
+    port (
+        CLK: in std_logic; 
+        FINEDELB0: in std_logic; 
+        FINEDELB1: in std_logic; 
+        FINEDELB2: in std_logic; 
+        FINEDELB3: in std_logic; 
+        DPHASE0: in std_logic; 
+        DPHASE1: in std_logic; 
+        DPHASE2: in std_logic; 
+        DPHASE3: in std_logic; 
+        CLKOP: out std_logic; 
+        CLKOS: out std_logic; 
+        LOCK: out std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of pll_in125_outshift : entity is true;
+end pll_in125_outshift;
+
+architecture Structure of pll_in125_outshift is
+
+    -- internal signal declarations
+    signal CLKOS_t: std_logic;
+    signal DPHASE3_inv: std_logic;
+    signal CLKOP_t: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component EHXPLLF
+        generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; 
+                DELAY_PWD : in String; DELAY_VAL : in Integer; 
+                CLKOS_TRIM_DELAY : in Integer; 
+                CLKOS_TRIM_POL : in String; 
+                CLKOP_TRIM_DELAY : in Integer; 
+                CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; 
+                CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; 
+                PHASE_DELAY_CNTL : in String; DUTY : in Integer; 
+                PHASEADJ : in String; CLKOK_DIV : in Integer; 
+                CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; 
+                CLKI_DIV : in Integer; FIN : in String);
+        port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; 
+            RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; 
+            DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; 
+            DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; 
+            DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; 
+            FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; 
+            CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; 
+            LOCK: out std_logic; CLKINTFB: out std_logic);
+    end component;
+    component INV
+        port (A: in std_logic; Z: out std_logic);
+    end component;
+    component VLO
+        port (Z: out std_logic);
+    end component;
+    attribute FREQUENCY_PIN_CLKOP : string; 
+    attribute FREQUENCY_PIN_CLKOS : string; 
+    attribute FREQUENCY_PIN_CLKI : string; 
+    attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "125.000000";
+    attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "125.000000";
+    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "125.000000";
+    attribute syn_keep : boolean;
+    attribute syn_noprune : boolean;
+    attribute syn_noprune of Structure : architecture is true;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    INV_0: INV
+        port map (A=>DPHASE3, Z=>DPHASE3_inv);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    PLLInst_0: EHXPLLF
+        generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", 
+        CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", 
+        CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=>  0, 
+        CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "RISING", 
+        CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "RISING", 
+        PHASE_DELAY_CNTL=> "DYNAMIC", DUTY=>  8, PHASEADJ=> "0.0", 
+        CLKOK_DIV=>  2, CLKOP_DIV=>  8, CLKFB_DIV=>  1, CLKI_DIV=>  1, 
+        FIN=> "125.000000")
+        port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, 
+            RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>DPHASE3, 
+            DRPAI2=>DPHASE2, DRPAI1=>DPHASE1, DRPAI0=>DPHASE0, 
+            DFPAI3=>DPHASE3_inv, DFPAI2=>DPHASE2, DFPAI1=>DPHASE1, 
+            DFPAI0=>DPHASE0, FDA3=>FINEDELB3, FDA2=>FINEDELB2, 
+            FDA1=>FINEDELB1, FDA0=>FINEDELB0, CLKOP=>CLKOP_t, 
+            CLKOS=>CLKOS_t, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, 
+            CLKINTFB=>open);
+
+    CLKOS <= CLKOS_t;
+    CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of pll_in125_outshift is
+    for Structure
+        for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+        for all:INV use entity ecp3.INV(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in125_outshift_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/pll_in125_outshift_tmpl.vhd
new file mode 100644
index 0000000..d060d10
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in125_outshift_tmpl.vhd
@@ -0,0 +1,17 @@
+-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.6
+-- Fri Aug 22 15:55:24 2014
+
+-- parameterized module component declaration
+component pll_in125_outshift
+    port (CLK: in std_logic; FINEDELB0: in std_logic; FINEDELB1: in std_logic; 
+        FINEDELB2: in std_logic; FINEDELB3: in std_logic; DPHASE0: in std_logic; 
+        DPHASE1: in std_logic; DPHASE2: in std_logic; DPHASE3: in std_logic; 
+        CLKOP: out std_logic; CLKOS: out std_logic; LOCK: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : pll_in125_outshift
+    port map (CLK=>__, FINEDELB0=>__, FINEDELB1=>__, FINEDELB2=>__, 
+        FINEDELB3=>__, DPHASE0=>__, DPHASE1=>__, DPHASE2=>__, DPHASE3=>__, 
+        CLKOP=>__, CLKOS=>__, LOCK=>__);
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in200_out125_62M5.ipx b/data_concentrator/sources/lattice/ecp3/pll_in200_out125_62M5.ipx
new file mode 100644
index 0000000..da25712
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in200_out125_62M5.ipx
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_in200_out125_62M5" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 07 18 16:49:45.352" version="5.3" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="pll_in200_out125_62M5.lpc" type="lpc" modified="2013 07 18 16:49:41.833"/>
+		<File name="pll_in200_out125_62M5.vhd" type="top_level_vhdl" modified="2013 07 18 16:49:41.905"/>
+		<File name="pll_in200_out125_62M5_tmpl.vhd" type="template_vhdl" modified="2013 07 18 16:49:41.928"/>
+  </Package>
+</DiamondModule>
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in200_out125_62M5.lpc b/data_concentrator/sources/lattice/ecp3/pll_in200_out125_62M5.lpc
new file mode 100644
index 0000000..050433c
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in200_out125_62M5.lpc
@@ -0,0 +1,66 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.3
+ModuleName=pll_in200_out125_62M5
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=07/18/2013
+Time=16:49:41
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=200
+Div=8
+ClkOPBp=0
+Post=8
+U_OFrq=125
+OP_Tol=0.0
+OFrq=125.000000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=CLKOP
+Mult=5
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Static
+CLKOK_INPUT=CLKOP
+SecD=2
+U_KFrq=62.5
+OK_Tol=0.0
+KFrq=62.500000
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=2.739454
+;DelayControl=No
+EnCLKOS=1
+ClkOSBp=1
+EnCLKOK=1
+ClkOKBp=0
+enClkOK2=0
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in200_out125_62M5.vhd b/data_concentrator/sources/lattice/ecp3/pll_in200_out125_62M5.vhd
new file mode 100644
index 0000000..82d1c20
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in200_out125_62M5.vhd
@@ -0,0 +1,106 @@
+-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
+-- Module  Version: 5.3
+--C:\lscc\diamond\2.1_x64\ispfpga\bin\nt64\scuba.exe -w -n pll_in200_out125_62M5 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypasss -fclkop 125 -fclkop_tol 0.0 -fb_mode CLOCKTREE -phaseadj 0.0 -duty 8 -fclkok 62.5 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw -e 
+
+-- Thu Jul 18 16:49:41 2013
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity pll_in200_out125_62M5 is
+    port (
+        CLK: in std_logic; 
+        CLKOP: out std_logic; 
+        CLKOS: out std_logic; 
+        CLKOK: out std_logic; 
+        LOCK: out std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of pll_in200_out125_62M5 : entity is true;
+end pll_in200_out125_62M5;
+
+architecture Structure of pll_in200_out125_62M5 is
+
+    -- internal signal declarations
+    signal CLKOS_t: std_logic;
+    signal CLKOP_t: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component EHXPLLF
+        generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; 
+                DELAY_PWD : in String; DELAY_VAL : in Integer; 
+                CLKOS_TRIM_DELAY : in Integer; 
+                CLKOS_TRIM_POL : in String; 
+                CLKOP_TRIM_DELAY : in Integer; 
+                CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; 
+                CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; 
+                PHASE_DELAY_CNTL : in String; DUTY : in Integer; 
+                PHASEADJ : in String; CLKOK_DIV : in Integer; 
+                CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; 
+                CLKI_DIV : in Integer; FIN : in String);
+        port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; 
+            RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; 
+            DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; 
+            DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; 
+            DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; 
+            FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; 
+            CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; 
+            LOCK: out std_logic; CLKINTFB: out std_logic);
+    end component;
+    component VLO
+        port (Z: out std_logic);
+    end component;
+    attribute FREQUENCY_PIN_CLKOP : string; 
+    attribute FREQUENCY_PIN_CLKOS : string; 
+    attribute FREQUENCY_PIN_CLKI : string; 
+    attribute FREQUENCY_PIN_CLKOK : string; 
+    attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "125.000000";
+    attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "200.000000";
+    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+    attribute FREQUENCY_PIN_CLKOK of PLLInst_0 : label is "62.500000";
+    attribute syn_keep : boolean;
+    attribute syn_noprune : boolean;
+    attribute syn_noprune of Structure : architecture is true;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    PLLInst_0: EHXPLLF
+        generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", 
+        CLKOS_BYPASS=> "ENABLED", CLKOP_BYPASS=> "DISABLED", CLKOK_INPUT=> "CLKOP", 
+        DELAY_PWD=> "DISABLED", DELAY_VAL=>  0, CLKOS_TRIM_DELAY=>  0, 
+        CLKOS_TRIM_POL=> "RISING", CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "RISING", 
+        PHASE_DELAY_CNTL=> "STATIC", DUTY=>  8, PHASEADJ=> "0.0", 
+        CLKOK_DIV=>  2, CLKOP_DIV=>  8, CLKFB_DIV=>  5, CLKI_DIV=>  8, 
+        FIN=> "200.000000")
+        port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, 
+            RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, 
+            DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, 
+            DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, 
+            DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, 
+            FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, 
+            CLKOS=>CLKOS_t, CLKOK=>CLKOK, CLKOK2=>open, LOCK=>LOCK, 
+            CLKINTFB=>open);
+
+    CLKOS <= CLKOS_t;
+    CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of pll_in200_out125_62M5 is
+    for Structure
+        for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in200_out125_62M5_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/pll_in200_out125_62M5_tmpl.vhd
new file mode 100644
index 0000000..4a852af
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in200_out125_62M5_tmpl.vhd
@@ -0,0 +1,13 @@
+-- VHDL module instantiation generated by SCUBA Diamond_2.1_Production (100)
+-- Module  Version: 5.3
+-- Thu Jul 18 16:49:41 2013
+
+-- parameterized module component declaration
+component pll_in200_out125_62M5
+    port (CLK: in std_logic; CLKOP: out std_logic; CLKOS: out std_logic; 
+        CLKOK: out std_logic; LOCK: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : pll_in200_out125_62M5
+    port map (CLK=>__, CLKOP=>__, CLKOS=>__, CLKOK=>__, LOCK=>__);
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in200_out160M_80M.ipx b/data_concentrator/sources/lattice/ecp3/pll_in200_out160M_80M.ipx
new file mode 100644
index 0000000..38a2d35
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in200_out160M_80M.ipx
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_in200_out160M_80M" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 08 29 09:14:51.694" version="5.6" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="pll_in200_out160M_80M.lpc" type="lpc" modified="2014 08 29 09:14:47.886"/>
+		<File name="pll_in200_out160M_80M.vhd" type="top_level_vhdl" modified="2014 08 29 09:14:47.965"/>
+		<File name="pll_in200_out160M_80M_tmpl.vhd" type="template_vhdl" modified="2014 08 29 09:14:47.966"/>
+  </Package>
+</DiamondModule>
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in200_out160M_80M.lpc b/data_concentrator/sources/lattice/ecp3/pll_in200_out160M_80M.lpc
new file mode 100644
index 0000000..0d90c8b
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in200_out160M_80M.lpc
@@ -0,0 +1,69 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.6
+ModuleName=pll_in200_out160M_80M
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=08/29/2014
+Time=09:14:47
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=200
+Div=5
+ClkOPBp=0
+Post=4
+U_OFrq=160
+OP_Tol=0.0
+OFrq=160.000000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=CLKOP
+Mult=4
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Static
+CLKOK_INPUT=CLKOP
+SecD=2
+U_KFrq=80
+OK_Tol=0.0
+KFrq=80.000000
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=2.191564
+;DelayControl=No
+EnCLKOS=0
+ClkOSBp=0
+EnCLKOK=1
+ClkOKBp=0
+enClkOK2=0
+
+[Command]
+cmd_line= -w -n pll_in200_out160M_80M -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 160 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -fclkok 80 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in200_out160M_80M.vhd b/data_concentrator/sources/lattice/ecp3/pll_in200_out160M_80M.vhd
new file mode 100644
index 0000000..10c027d
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in200_out160M_80M.vhd
@@ -0,0 +1,102 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.6
+--C:\Lattice\diamond\3.2_x64\ispfpga\bin\nt64\scuba.exe -w -n pll_in200_out160M_80M -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 160 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -fclkok 80 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw 
+
+-- Fri Aug 29 09:14:47 2014
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity pll_in200_out160M_80M is
+    port (
+        CLK: in std_logic; 
+        CLKOP: out std_logic; 
+        CLKOK: out std_logic; 
+        LOCK: out std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of pll_in200_out160M_80M : entity is true;
+end pll_in200_out160M_80M;
+
+architecture Structure of pll_in200_out160M_80M is
+
+    -- internal signal declarations
+    signal CLKOP_t: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component EHXPLLF
+        generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; 
+                DELAY_PWD : in String; DELAY_VAL : in Integer; 
+                CLKOS_TRIM_DELAY : in Integer; 
+                CLKOS_TRIM_POL : in String; 
+                CLKOP_TRIM_DELAY : in Integer; 
+                CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; 
+                CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; 
+                PHASE_DELAY_CNTL : in String; DUTY : in Integer; 
+                PHASEADJ : in String; CLKOK_DIV : in Integer; 
+                CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; 
+                CLKI_DIV : in Integer; FIN : in String);
+        port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; 
+            RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; 
+            DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; 
+            DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; 
+            DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; 
+            FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; 
+            CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; 
+            LOCK: out std_logic; CLKINTFB: out std_logic);
+    end component;
+    component VLO
+        port (Z: out std_logic);
+    end component;
+    attribute FREQUENCY_PIN_CLKOP : string; 
+    attribute FREQUENCY_PIN_CLKI : string; 
+    attribute FREQUENCY_PIN_CLKOK : string; 
+    attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "160.000000";
+    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+    attribute FREQUENCY_PIN_CLKOK of PLLInst_0 : label is "80.000000";
+    attribute syn_keep : boolean;
+    attribute syn_noprune : boolean;
+    attribute syn_noprune of Structure : architecture is true;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    PLLInst_0: EHXPLLF
+        generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", 
+        CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", 
+        CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=>  0, 
+        CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "RISING", 
+        CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "RISING", 
+        PHASE_DELAY_CNTL=> "STATIC", DUTY=>  8, PHASEADJ=> "0.0", 
+        CLKOK_DIV=>  2, CLKOP_DIV=>  4, CLKFB_DIV=>  4, CLKI_DIV=>  5, 
+        FIN=> "200.000000")
+        port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, 
+            RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, 
+            DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, 
+            DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, 
+            DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, 
+            FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, 
+            CLKOS=>open, CLKOK=>CLKOK, CLKOK2=>open, LOCK=>LOCK, 
+            CLKINTFB=>open);
+
+    CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of pll_in200_out160M_80M is
+    for Structure
+        for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in200_out160M_80M_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/pll_in200_out160M_80M_tmpl.vhd
new file mode 100644
index 0000000..1f6c9d3
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in200_out160M_80M_tmpl.vhd
@@ -0,0 +1,13 @@
+-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.6
+-- Fri Aug 29 09:14:47 2014
+
+-- parameterized module component declaration
+component pll_in200_out160M_80M
+    port (CLK: in std_logic; CLKOP: out std_logic; CLKOK: out std_logic; 
+        LOCK: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : pll_in200_out160M_80M
+    port map (CLK=>__, CLKOP=>__, CLKOK=>__, LOCK=>__);
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in200_out200M_100M.ipx b/data_concentrator/sources/lattice/ecp3/pll_in200_out200M_100M.ipx
new file mode 100644
index 0000000..142775e
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in200_out200M_100M.ipx
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_in200_out200M_100M" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 11 20 10:10:32.936" version="5.6" type="IP" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="pll_in200_out200M_100M.lpc" type="lpc" modified="2014 11 20 10:10:30.972"/>
+  </Package>
+</DiamondModule>
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in200_out200M_100M.lpc b/data_concentrator/sources/lattice/ecp3/pll_in200_out200M_100M.lpc
new file mode 100644
index 0000000..0caf1c6
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in200_out200M_100M.lpc
@@ -0,0 +1,69 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.6
+ModuleName=pll_in200_out200M_100M
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=11/20/2014
+Time=10:10:30
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=200
+Div=2
+ClkOPBp=0
+Post=8
+U_OFrq=100
+OP_Tol=0.0
+OFrq=100.000000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=CLKOP
+Mult=1
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Static
+CLKOK_INPUT=CLKOP
+SecD=2
+U_KFrq=80
+OK_Tol=0.0
+KFrq=40.000000
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=1.485393
+;DelayControl=No
+EnCLKOS=1
+ClkOSBp=1
+EnCLKOK=0
+ClkOKBp=0
+enClkOK2=0
+
+[Command]
+cmd_line= -w -n pll_in200_out200M_100M -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypasss -fclkop 100 -fclkop_tol 0.0 -fb_mode CLOCKTREE -phaseadj 0.0 -duty 8 -noclkok -norst -noclkok2 -bw
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in200_out200M_100M.vhd b/data_concentrator/sources/lattice/ecp3/pll_in200_out200M_100M.vhd
new file mode 100644
index 0000000..414063f
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in200_out200M_100M.vhd
@@ -0,0 +1,103 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.6
+--C:\Lattice\diamond\3.2_x64\ispfpga\bin\nt64\scuba.exe -w -n pll_in200_out200M_100M -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypasss -fclkop 100 -fclkop_tol 0.0 -fb_mode CLOCKTREE -phaseadj 0.0 -duty 8 -noclkok -norst -noclkok2 -bw 
+
+-- Thu Nov 20 10:10:31 2014
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity pll_in200_out200M_100M is
+    port (
+        CLK: in std_logic; 
+        CLKOP: out std_logic; 
+        CLKOS: out std_logic; 
+        LOCK: out std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of pll_in200_out200M_100M : entity is true;
+end pll_in200_out200M_100M;
+
+architecture Structure of pll_in200_out200M_100M is
+
+    -- internal signal declarations
+    signal CLKOS_t: std_logic;
+    signal CLKOP_t: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component EHXPLLF
+        generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; 
+                DELAY_PWD : in String; DELAY_VAL : in Integer; 
+                CLKOS_TRIM_DELAY : in Integer; 
+                CLKOS_TRIM_POL : in String; 
+                CLKOP_TRIM_DELAY : in Integer; 
+                CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; 
+                CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; 
+                PHASE_DELAY_CNTL : in String; DUTY : in Integer; 
+                PHASEADJ : in String; CLKOK_DIV : in Integer; 
+                CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; 
+                CLKI_DIV : in Integer; FIN : in String);
+        port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; 
+            RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; 
+            DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; 
+            DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; 
+            DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; 
+            FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; 
+            CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; 
+            LOCK: out std_logic; CLKINTFB: out std_logic);
+    end component;
+    component VLO
+        port (Z: out std_logic);
+    end component;
+    attribute FREQUENCY_PIN_CLKOP : string; 
+    attribute FREQUENCY_PIN_CLKOS : string; 
+    attribute FREQUENCY_PIN_CLKI : string; 
+    attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "100.000000";
+    attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "200.000000";
+    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+    attribute syn_keep : boolean;
+    attribute syn_noprune : boolean;
+    attribute syn_noprune of Structure : architecture is true;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    PLLInst_0: EHXPLLF
+        generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", 
+        CLKOS_BYPASS=> "ENABLED", CLKOP_BYPASS=> "DISABLED", CLKOK_INPUT=> "CLKOP", 
+        DELAY_PWD=> "DISABLED", DELAY_VAL=>  0, CLKOS_TRIM_DELAY=>  0, 
+        CLKOS_TRIM_POL=> "RISING", CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "RISING", 
+        PHASE_DELAY_CNTL=> "STATIC", DUTY=>  8, PHASEADJ=> "0.0", 
+        CLKOK_DIV=>  2, CLKOP_DIV=>  8, CLKFB_DIV=>  1, CLKI_DIV=>  2, 
+        FIN=> "200.000000")
+        port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, 
+            RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, 
+            DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, 
+            DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, 
+            DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, 
+            FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, 
+            CLKOS=>CLKOS_t, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, 
+            CLKINTFB=>open);
+
+    CLKOS <= CLKOS_t;
+    CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of pll_in200_out200M_100M is
+    for Structure
+        for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in200_out200M_100M_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/pll_in200_out200M_100M_tmpl.vhd
new file mode 100644
index 0000000..b3c4578
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in200_out200M_100M_tmpl.vhd
@@ -0,0 +1,13 @@
+-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.6
+-- Thu Nov 20 10:10:31 2014
+
+-- parameterized module component declaration
+component pll_in200_out200M_100M
+    port (CLK: in std_logic; CLKOP: out std_logic; CLKOS: out std_logic; 
+        LOCK: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : pll_in200_out200M_100M
+    port map (CLK=>__, CLKOP=>__, CLKOS=>__, LOCK=>__);
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in62M5_outshift.ipx b/data_concentrator/sources/lattice/ecp3/pll_in62M5_outshift.ipx
new file mode 100644
index 0000000..c5a2a8f
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in62M5_outshift.ipx
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_in62M5_outshift" module="pll_in62M5_outshift" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 08 25 13:34:55.469" version="5.6" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="pll_in62M5_outshift.lpc" type="lpc" modified="2014 08 25 13:34:53.138"/>
+		<File name="pll_in62M5_outshift.vhd" type="top_level_vhdl" modified="2014 08 25 13:34:53.209"/>
+		<File name="pll_in62M5_outshift_tmpl.vhd" type="template_vhdl" modified="2014 08 25 13:34:53.210"/>
+  </Package>
+</DiamondModule>
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in62M5_outshift.lpc b/data_concentrator/sources/lattice/ecp3/pll_in62M5_outshift.lpc
new file mode 100644
index 0000000..0a312f4
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in62M5_outshift.lpc
@@ -0,0 +1,69 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.6
+ModuleName=pll_in62M5_outshift
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=08/25/2014
+Time=13:34:53
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=62.5
+Div=1
+ClkOPBp=0
+Post=16
+U_OFrq=62.5
+OP_Tol=0.0
+OFrq=62.500000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=CLKOP
+Mult=1
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Dynamic
+CLKOK_INPUT=CLKOS
+SecD=2
+U_KFrq=50
+OK_Tol=0.0
+KFrq=
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=2.191564
+;DelayControl=No
+EnCLKOS=1
+ClkOSBp=0
+EnCLKOK=0
+ClkOKBp=0
+enClkOK2=0
+
+[Command]
+cmd_line= -w -n pll_in62M5_outshift -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 62.5 -phase_cntl DYNAMIC -fclkop 62.5 -fclkop_tol 0.0 -fb_mode CLOCKTREE -duty50 -noclkok -norst -noclkok2 -bw
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in62M5_outshift.vhd b/data_concentrator/sources/lattice/ecp3/pll_in62M5_outshift.vhd
new file mode 100644
index 0000000..2d2407c
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in62M5_outshift.vhd
@@ -0,0 +1,120 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.6
+--C:\Lattice\diamond\3.2_x64\ispfpga\bin\nt64\scuba.exe -w -n pll_in62M5_outshift -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 62.5 -phase_cntl DYNAMIC -fclkop 62.5 -fclkop_tol 0.0 -fb_mode CLOCKTREE -duty50 -noclkok -norst -noclkok2 -bw 
+
+-- Mon Aug 25 13:34:53 2014
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity pll_in62M5_outshift is
+    port (
+        CLK: in std_logic; 
+        FINEDELB0: in std_logic; 
+        FINEDELB1: in std_logic; 
+        FINEDELB2: in std_logic; 
+        FINEDELB3: in std_logic; 
+        DPHASE0: in std_logic; 
+        DPHASE1: in std_logic; 
+        DPHASE2: in std_logic; 
+        DPHASE3: in std_logic; 
+        CLKOP: out std_logic; 
+        CLKOS: out std_logic; 
+        LOCK: out std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of pll_in62M5_outshift : entity is true;
+end pll_in62M5_outshift;
+
+architecture Structure of pll_in62M5_outshift is
+
+    -- internal signal declarations
+    signal CLKOS_t: std_logic;
+    signal DPHASE3_inv: std_logic;
+    signal CLKOP_t: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component EHXPLLF
+        generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; 
+                DELAY_PWD : in String; DELAY_VAL : in Integer; 
+                CLKOS_TRIM_DELAY : in Integer; 
+                CLKOS_TRIM_POL : in String; 
+                CLKOP_TRIM_DELAY : in Integer; 
+                CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; 
+                CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; 
+                PHASE_DELAY_CNTL : in String; DUTY : in Integer; 
+                PHASEADJ : in String; CLKOK_DIV : in Integer; 
+                CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; 
+                CLKI_DIV : in Integer; FIN : in String);
+        port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; 
+            RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; 
+            DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; 
+            DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; 
+            DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; 
+            FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; 
+            CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; 
+            LOCK: out std_logic; CLKINTFB: out std_logic);
+    end component;
+    component INV
+        port (A: in std_logic; Z: out std_logic);
+    end component;
+    component VLO
+        port (Z: out std_logic);
+    end component;
+    attribute FREQUENCY_PIN_CLKOP : string; 
+    attribute FREQUENCY_PIN_CLKOS : string; 
+    attribute FREQUENCY_PIN_CLKI : string; 
+    attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "62.500000";
+    attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "62.500000";
+    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "62.500000";
+    attribute syn_keep : boolean;
+    attribute syn_noprune : boolean;
+    attribute syn_noprune of Structure : architecture is true;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    INV_0: INV
+        port map (A=>DPHASE3, Z=>DPHASE3_inv);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    PLLInst_0: EHXPLLF
+        generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", 
+        CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", 
+        CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=>  0, 
+        CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "RISING", 
+        CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "RISING", 
+        PHASE_DELAY_CNTL=> "DYNAMIC", DUTY=>  8, PHASEADJ=> "0.0", 
+        CLKOK_DIV=>  2, CLKOP_DIV=>  16, CLKFB_DIV=>  1, CLKI_DIV=>  1, 
+        FIN=> "62.500000")
+        port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, 
+            RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>DPHASE3, 
+            DRPAI2=>DPHASE2, DRPAI1=>DPHASE1, DRPAI0=>DPHASE0, 
+            DFPAI3=>DPHASE3_inv, DFPAI2=>DPHASE2, DFPAI1=>DPHASE1, 
+            DFPAI0=>DPHASE0, FDA3=>FINEDELB3, FDA2=>FINEDELB2, 
+            FDA1=>FINEDELB1, FDA0=>FINEDELB0, CLKOP=>CLKOP_t, 
+            CLKOS=>CLKOS_t, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, 
+            CLKINTFB=>open);
+
+    CLKOS <= CLKOS_t;
+    CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of pll_in62M5_outshift is
+    for Structure
+        for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+        for all:INV use entity ecp3.INV(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/data_concentrator/sources/lattice/ecp3/pll_in62M5_outshift_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/pll_in62M5_outshift_tmpl.vhd
new file mode 100644
index 0000000..18f551a
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/pll_in62M5_outshift_tmpl.vhd
@@ -0,0 +1,17 @@
+-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.6
+-- Mon Aug 25 13:34:53 2014
+
+-- parameterized module component declaration
+component pll_in62M5_outshift
+    port (CLK: in std_logic; FINEDELB0: in std_logic; FINEDELB1: in std_logic; 
+        FINEDELB2: in std_logic; FINEDELB3: in std_logic; DPHASE0: in std_logic; 
+        DPHASE1: in std_logic; DPHASE2: in std_logic; DPHASE3: in std_logic; 
+        CLKOP: out std_logic; CLKOS: out std_logic; LOCK: out std_logic);
+end component;
+
+-- parameterized module component instance
+__ : pll_in62M5_outshift
+    port map (CLK=>__, FINEDELB0=>__, FINEDELB1=>__, FINEDELB2=>__, 
+        FINEDELB3=>__, DPHASE0=>__, DPHASE1=>__, DPHASE2=>__, DPHASE3=>__, 
+        CLKOP=>__, CLKOS=>__, LOCK=>__);
diff --git a/data_concentrator/sources/lattice/ecp3/serdes_sync_125_full.ipx b/data_concentrator/sources/lattice/ecp3/serdes_sync_125_full.ipx
new file mode 100644
index 0000000..995ce7c
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/serdes_sync_125_full.ipx
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="serdes_sync_125_full" module="serdes_sync_125_full" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 08 29 11:18:27.591" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="serdes_sync_125_full.lpc" type="lpc" modified="2014 08 29 11:18:24.808"/>
+		<File name="serdes_sync_125_full.pp" type="pp" modified="2014 08 29 11:18:24.811"/>
+		<File name="serdes_sync_125_full.sym" type="sym" modified="2014 08 29 11:18:25.049"/>
+		<File name="serdes_sync_125_full.tft" type="tft" modified="2013 08 27 13:37:32.629"/>
+		<File name="serdes_sync_125_full.txt" type="pcs_module" modified="2014 08 29 11:18:24.827"/>
+		<File name="serdes_sync_125_full.vhd" type="top_level_vhdl" modified="2013 08 27 13:37:32.621"/>
+  </Package>
+</DiamondModule>
diff --git a/data_concentrator/sources/lattice/ecp3/serdes_sync_125_full.lpc b/data_concentrator/sources/lattice/ecp3/serdes_sync_125_full.lpc
new file mode 100644
index 0000000..f488ddf
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/serdes_sync_125_full.lpc
@@ -0,0 +1,258 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PCS
+CoreRevision=8.2
+ModuleName=serdes_sync_125_full
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=08/29/2014
+Time=11:18:24
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+_mode0=RXTX
+_mode1=RXTX
+_mode2=RXTX
+_mode3=RXTX
+_protocol0=G8B10B
+_protocol1=G8B10B
+_protocol2=G8B10B
+_protocol3=G8B10B
+_ldr0=DISABLED
+_ldr1=DISABLED
+_ldr2=DISABLED
+_ldr3=DISABLED
+_datarange=1.25
+_pll_txsrc=INTERNAL
+_refclk_mult=10X
+_refclk_rate=125.0
+_tx_protocol0=G8B10B
+_tx_protocol1=G8B10B
+_tx_protocol2=G8B10B
+_tx_protocol3=G8B10B
+_tx_data_rate0=FULL
+_tx_data_rate1=FULL
+_tx_data_rate2=FULL
+_tx_data_rate3=FULL
+_tx_data_width0=8
+_tx_data_width1=8
+_tx_data_width2=8
+_tx_data_width3=8
+_tx_fifo0=DISABLED
+_tx_fifo1=DISABLED
+_tx_fifo2=DISABLED
+_tx_fifo3=DISABLED
+_tx_ficlk_rate0=125.0
+_tx_ficlk_rate1=125.0
+_tx_ficlk_rate2=125.0
+_tx_ficlk_rate3=125.0
+_pll_rxsrc0=INTERNAL
+_pll_rxsrc1=INTERNAL
+_pll_rxsrc2=INTERNAL
+_pll_rxsrc3=INTERNAL
+Multiplier0=
+Multiplier1=
+Multiplier2=
+Multiplier3=
+_rx_datarange0=1.25
+_rx_datarange1=1.25
+_rx_datarange2=1.25
+_rx_datarange3=1.25
+_rx_protocol0=G8B10B
+_rx_protocol1=G8B10B
+_rx_protocol2=G8B10B
+_rx_protocol3=G8B10B
+_rx_data_rate0=FULL
+_rx_data_rate1=FULL
+_rx_data_rate2=FULL
+_rx_data_rate3=FULL
+_rxrefclk_rate0=125.0
+_rxrefclk_rate1=125.0
+_rxrefclk_rate2=125.0
+_rxrefclk_rate3=125.0
+_rx_data_width0=8
+_rx_data_width1=8
+_rx_data_width2=8
+_rx_data_width3=8
+_rx_fifo0=ENABLED
+_rx_fifo1=ENABLED
+_rx_fifo2=ENABLED
+_rx_fifo3=ENABLED
+_rx_ficlk_rate0=125.0
+_rx_ficlk_rate1=125.0
+_rx_ficlk_rate2=125.0
+_rx_ficlk_rate3=125.0
+_tdrv_ch0=1
+_tdrv_ch1=1
+_tdrv_ch2=1
+_tdrv_ch3=1
+_tx_pre0=DISABLED
+_tx_pre1=DISABLED
+_tx_pre2=DISABLED
+_tx_pre3=DISABLED
+_rterm_tx0=50
+_rterm_tx1=50
+_rterm_tx2=50
+_rterm_tx3=50
+_rx_eq0=DISABLED
+_rx_eq1=DISABLED
+_rx_eq2=DISABLED
+_rx_eq3=DISABLED
+_rterm_rx0=50
+_rterm_rx1=50
+_rterm_rx2=50
+_rterm_rx3=50
+_rx_dcc0=DC
+_rx_dcc1=DC
+_rx_dcc2=DC
+_rx_dcc3=DC
+_los_threshold_mode0=LOS_E
+_los_threshold_mode1=LOS_E
+_los_threshold_mode2=LOS_E
+_los_threshold_mode3=LOS_E
+_los_threshold_lo0=2
+_los_threshold_lo1=2
+_los_threshold_lo2=2
+_los_threshold_lo3=2
+_los_threshold_hi0=7
+_los_threshold_hi1=7
+_los_threshold_hi2=7
+_los_threshold_hi3=7
+_pll_term=50
+_pll_dcc=AC
+_pll_lol_set=1
+_tx_sb0=DISABLED
+_tx_sb1=DISABLED
+_tx_sb2=DISABLED
+_tx_sb3=DISABLED
+_tx_8b10b0=ENABLED
+_tx_8b10b1=ENABLED
+_tx_8b10b2=ENABLED
+_tx_8b10b3=ENABLED
+_rx_sb0=DISABLED
+_rx_sb1=DISABLED
+_rx_sb2=DISABLED
+_rx_sb3=DISABLED
+_ird0=DISABLED
+_ird1=DISABLED
+_ird2=DISABLED
+_ird3=DISABLED
+_rx_8b10b0=ENABLED
+_rx_8b10b1=ENABLED
+_rx_8b10b2=ENABLED
+_rx_8b10b3=ENABLED
+_rxwa0=ENABLED
+_rxwa1=ENABLED
+_rxwa2=ENABLED
+_rxwa3=ENABLED
+_ilsm0=ENABLED
+_ilsm1=ENABLED
+_ilsm2=ENABLED
+_ilsm3=ENABLED
+_scomma0=User Defined
+_scomma1=User Defined
+_scomma2=User Defined
+_scomma3=User Defined
+_comma_a0=1100000101
+_comma_a1=1100000101
+_comma_a2=1100000101
+_comma_a3=1100000101
+_comma_b0=0011111010
+_comma_b1=0011111010
+_comma_b2=0011111010
+_comma_b3=0011111010
+_comma_m0=1111111111
+_comma_m1=1111111111
+_comma_m2=1111111111
+_comma_m3=1111111111
+_ctc0=DISABLED
+_ctc1=DISABLED
+_ctc2=DISABLED
+_ctc3=DISABLED
+_cc_match_mode0=1
+_cc_match_mode1=1
+_cc_match_mode2=1
+_cc_match_mode3=1
+_k00=01
+_k01=01
+_k02=01
+_k03=01
+_k10=00
+_k11=00
+_k12=00
+_k13=00
+_k20=01
+_k21=01
+_k22=01
+_k23=01
+_k30=01
+_k31=01
+_k32=01
+_k33=01
+_byten00=00011100
+_byten01=00011100
+_byten02=00011100
+_byten03=00011100
+_byten10=00000000
+_byten11=00000000
+_byten12=00000000
+_byten13=00000000
+_byten20=00011100
+_byten21=00011100
+_byten22=00011100
+_byten23=00011100
+_byten30=00011100
+_byten31=00011100
+_byten32=00011100
+_byten33=00011100
+_cc_min_ipg0=3
+_cc_min_ipg1=3
+_cc_min_ipg2=3
+_cc_min_ipg3=3
+_cchmark=9
+_cclmark=7
+_loopback=DISABLED
+_lbtype0=DISABLED
+_lbtype1=DISABLED
+_lbtype2=DISABLED
+_lbtype3=DISABLED
+_teidle_ch0=DISABLED
+_teidle_ch1=DISABLED
+_teidle_ch2=DISABLED
+_teidle_ch3=DISABLED
+_rst_gen=DISABLED
+_rx_los_port0=Internal
+_rx_los_port1=Internal
+_rx_los_port2=Internal
+_rx_los_port3=Internal
+_sci_ports=ENABLED
+_sci_int_port=DISABLED
+_refck2core=DISABLED
+Regen=auto
+PAR1=0
+PARTrace1=0
+PAR3=0
+PARTrace3=0
+
+[FilesGenerated]
+serdes_sync_125_full.pp=pp
+serdes_sync_125_full.tft=tft
+serdes_sync_125_full.txt=pcs_module
+serdes_sync_125_full.sym=sym
diff --git a/data_concentrator/sources/lattice/ecp3/serdes_sync_125_full.vhd b/data_concentrator/sources/lattice/ecp3/serdes_sync_125_full.vhd
new file mode 100644
index 0000000..451ee88
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/serdes_sync_125_full.vhd
@@ -0,0 +1,2810 @@
+
+                                                                                                         
+
+--synopsys translate_off
+
+library pcsd_work;
+use pcsd_work.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity PCSD is
+GENERIC(
+  CONFIG_FILE : String;
+  QUAD_MODE : String;
+  CH0_CDR_SRC   : String := "REFCLK_EXT";
+  CH1_CDR_SRC   : String := "REFCLK_EXT";
+  CH2_CDR_SRC   : String := "REFCLK_EXT";
+  CH3_CDR_SRC   : String := "REFCLK_EXT";
+  PLL_SRC   : String
+--  CONFIG_FILE : String  := "serdes_sync_125_full.txt";
+--  QUAD_MODE : String := "SINGLE";
+--  CH0_CDR_SRC   : String := "REFCLK_CORE";
+--  CH1_CDR_SRC   : String := "REFCLK_CORE";
+--  CH2_CDR_SRC   : String := "REFCLK_CORE";
+--  CH3_CDR_SRC   : String := "REFCLK_CORE";
+--  PLL_SRC   : String := "REFCLK_CORE"
+  );
+port (
+  HDINN0             : in std_logic;
+  HDINN1             : in std_logic;
+  HDINN2             : in std_logic;
+  HDINN3             : in std_logic;
+  HDINP0             : in std_logic;
+  HDINP1             : in std_logic;
+  HDINP2             : in std_logic;
+  HDINP3             : in std_logic;
+  REFCLKN             : in std_logic;
+  REFCLKP             : in std_logic;
+  CIN0             : in std_logic;
+  CIN1             : in std_logic;
+  CIN2             : in std_logic;
+  CIN3             : in std_logic;
+  CIN4             : in std_logic;
+  CIN5             : in std_logic;
+  CIN6             : in std_logic;
+  CIN7             : in std_logic;
+  CIN8             : in std_logic;
+  CIN9             : in std_logic;
+  CIN10             : in std_logic;
+  CIN11             : in std_logic;
+  CYAWSTN             : in std_logic;
+  FF_EBRD_CLK_0             : in std_logic;
+  FF_EBRD_CLK_1             : in std_logic;
+  FF_EBRD_CLK_2             : in std_logic;
+  FF_EBRD_CLK_3             : in std_logic;
+  FF_RXI_CLK_0             : in std_logic;
+  FF_RXI_CLK_1             : in std_logic;
+  FF_RXI_CLK_2             : in std_logic;
+  FF_RXI_CLK_3             : in std_logic;
+  FF_TX_D_0_0             : in std_logic;
+  FF_TX_D_0_1             : in std_logic;
+  FF_TX_D_0_2             : in std_logic;
+  FF_TX_D_0_3             : in std_logic;
+  FF_TX_D_0_4             : in std_logic;
+  FF_TX_D_0_5             : in std_logic;
+  FF_TX_D_0_6             : in std_logic;
+  FF_TX_D_0_7             : in std_logic;
+  FF_TX_D_0_8             : in std_logic;
+  FF_TX_D_0_9             : in std_logic;
+  FF_TX_D_0_10             : in std_logic;
+  FF_TX_D_0_11             : in std_logic;
+  FF_TX_D_0_12             : in std_logic;
+  FF_TX_D_0_13             : in std_logic;
+  FF_TX_D_0_14             : in std_logic;
+  FF_TX_D_0_15             : in std_logic;
+  FF_TX_D_0_16             : in std_logic;
+  FF_TX_D_0_17             : in std_logic;
+  FF_TX_D_0_18             : in std_logic;
+  FF_TX_D_0_19             : in std_logic;
+  FF_TX_D_0_20             : in std_logic;
+  FF_TX_D_0_21             : in std_logic;
+  FF_TX_D_0_22             : in std_logic;
+  FF_TX_D_0_23             : in std_logic;
+  FF_TX_D_1_0             : in std_logic;
+  FF_TX_D_1_1             : in std_logic;
+  FF_TX_D_1_2             : in std_logic;
+  FF_TX_D_1_3             : in std_logic;
+  FF_TX_D_1_4             : in std_logic;
+  FF_TX_D_1_5             : in std_logic;
+  FF_TX_D_1_6             : in std_logic;
+  FF_TX_D_1_7             : in std_logic;
+  FF_TX_D_1_8             : in std_logic;
+  FF_TX_D_1_9             : in std_logic;
+  FF_TX_D_1_10             : in std_logic;
+  FF_TX_D_1_11             : in std_logic;
+  FF_TX_D_1_12             : in std_logic;
+  FF_TX_D_1_13             : in std_logic;
+  FF_TX_D_1_14             : in std_logic;
+  FF_TX_D_1_15             : in std_logic;
+  FF_TX_D_1_16             : in std_logic;
+  FF_TX_D_1_17             : in std_logic;
+  FF_TX_D_1_18             : in std_logic;
+  FF_TX_D_1_19             : in std_logic;
+  FF_TX_D_1_20             : in std_logic;
+  FF_TX_D_1_21             : in std_logic;
+  FF_TX_D_1_22             : in std_logic;
+  FF_TX_D_1_23             : in std_logic;
+  FF_TX_D_2_0             : in std_logic;
+  FF_TX_D_2_1             : in std_logic;
+  FF_TX_D_2_2             : in std_logic;
+  FF_TX_D_2_3             : in std_logic;
+  FF_TX_D_2_4             : in std_logic;
+  FF_TX_D_2_5             : in std_logic;
+  FF_TX_D_2_6             : in std_logic;
+  FF_TX_D_2_7             : in std_logic;
+  FF_TX_D_2_8             : in std_logic;
+  FF_TX_D_2_9             : in std_logic;
+  FF_TX_D_2_10             : in std_logic;
+  FF_TX_D_2_11             : in std_logic;
+  FF_TX_D_2_12             : in std_logic;
+  FF_TX_D_2_13             : in std_logic;
+  FF_TX_D_2_14             : in std_logic;
+  FF_TX_D_2_15             : in std_logic;
+  FF_TX_D_2_16             : in std_logic;
+  FF_TX_D_2_17             : in std_logic;
+  FF_TX_D_2_18             : in std_logic;
+  FF_TX_D_2_19             : in std_logic;
+  FF_TX_D_2_20             : in std_logic;
+  FF_TX_D_2_21             : in std_logic;
+  FF_TX_D_2_22             : in std_logic;
+  FF_TX_D_2_23             : in std_logic;
+  FF_TX_D_3_0             : in std_logic;
+  FF_TX_D_3_1             : in std_logic;
+  FF_TX_D_3_2             : in std_logic;
+  FF_TX_D_3_3             : in std_logic;
+  FF_TX_D_3_4             : in std_logic;
+  FF_TX_D_3_5             : in std_logic;
+  FF_TX_D_3_6             : in std_logic;
+  FF_TX_D_3_7             : in std_logic;
+  FF_TX_D_3_8             : in std_logic;
+  FF_TX_D_3_9             : in std_logic;
+  FF_TX_D_3_10             : in std_logic;
+  FF_TX_D_3_11             : in std_logic;
+  FF_TX_D_3_12             : in std_logic;
+  FF_TX_D_3_13             : in std_logic;
+  FF_TX_D_3_14             : in std_logic;
+  FF_TX_D_3_15             : in std_logic;
+  FF_TX_D_3_16             : in std_logic;
+  FF_TX_D_3_17             : in std_logic;
+  FF_TX_D_3_18             : in std_logic;
+  FF_TX_D_3_19             : in std_logic;
+  FF_TX_D_3_20             : in std_logic;
+  FF_TX_D_3_21             : in std_logic;
+  FF_TX_D_3_22             : in std_logic;
+  FF_TX_D_3_23             : in std_logic;
+  FF_TXI_CLK_0             : in std_logic;
+  FF_TXI_CLK_1             : in std_logic;
+  FF_TXI_CLK_2             : in std_logic;
+  FF_TXI_CLK_3             : in std_logic;
+  FFC_CK_CORE_RX_0         : in std_logic;
+  FFC_CK_CORE_RX_1         : in std_logic;
+  FFC_CK_CORE_RX_2         : in std_logic;
+  FFC_CK_CORE_RX_3         : in std_logic;
+  FFC_CK_CORE_TX           : in std_logic;
+  FFC_EI_EN_0             : in std_logic;
+  FFC_EI_EN_1             : in std_logic;
+  FFC_EI_EN_2             : in std_logic;
+  FFC_EI_EN_3             : in std_logic;
+  FFC_ENABLE_CGALIGN_0             : in std_logic;
+  FFC_ENABLE_CGALIGN_1             : in std_logic;
+  FFC_ENABLE_CGALIGN_2             : in std_logic;
+  FFC_ENABLE_CGALIGN_3             : in std_logic;
+  FFC_FB_LOOPBACK_0             : in std_logic;
+  FFC_FB_LOOPBACK_1             : in std_logic;
+  FFC_FB_LOOPBACK_2             : in std_logic;
+  FFC_FB_LOOPBACK_3             : in std_logic;
+  FFC_LANE_RX_RST_0             : in std_logic;
+  FFC_LANE_RX_RST_1             : in std_logic;
+  FFC_LANE_RX_RST_2             : in std_logic;
+  FFC_LANE_RX_RST_3             : in std_logic;
+  FFC_LANE_TX_RST_0             : in std_logic;
+  FFC_LANE_TX_RST_1             : in std_logic;
+  FFC_LANE_TX_RST_2             : in std_logic;
+  FFC_LANE_TX_RST_3             : in std_logic;
+  FFC_MACRO_RST             : in std_logic;
+  FFC_PCI_DET_EN_0             : in std_logic;
+  FFC_PCI_DET_EN_1             : in std_logic;
+  FFC_PCI_DET_EN_2             : in std_logic;
+  FFC_PCI_DET_EN_3             : in std_logic;
+  FFC_PCIE_CT_0             : in std_logic;
+  FFC_PCIE_CT_1             : in std_logic;
+  FFC_PCIE_CT_2             : in std_logic;
+  FFC_PCIE_CT_3             : in std_logic;
+  FFC_PFIFO_CLR_0             : in std_logic;
+  FFC_PFIFO_CLR_1             : in std_logic;
+  FFC_PFIFO_CLR_2             : in std_logic;
+  FFC_PFIFO_CLR_3             : in std_logic;
+  FFC_QUAD_RST             : in std_logic;
+  FFC_RRST_0             : in std_logic;
+  FFC_RRST_1             : in std_logic;
+  FFC_RRST_2             : in std_logic;
+  FFC_RRST_3             : in std_logic;
+  FFC_RXPWDNB_0             : in std_logic;
+  FFC_RXPWDNB_1             : in std_logic;
+  FFC_RXPWDNB_2             : in std_logic;
+  FFC_RXPWDNB_3             : in std_logic;
+  FFC_SB_INV_RX_0             : in std_logic;
+  FFC_SB_INV_RX_1             : in std_logic;
+  FFC_SB_INV_RX_2             : in std_logic;
+  FFC_SB_INV_RX_3             : in std_logic;
+  FFC_SB_PFIFO_LP_0             : in std_logic;
+  FFC_SB_PFIFO_LP_1             : in std_logic;
+  FFC_SB_PFIFO_LP_2             : in std_logic;
+  FFC_SB_PFIFO_LP_3             : in std_logic;
+  FFC_SIGNAL_DETECT_0             : in std_logic;
+  FFC_SIGNAL_DETECT_1             : in std_logic;
+  FFC_SIGNAL_DETECT_2             : in std_logic;
+  FFC_SIGNAL_DETECT_3             : in std_logic;
+  FFC_SYNC_TOGGLE             : in std_logic;
+  FFC_TRST             : in std_logic;
+  FFC_TXPWDNB_0             : in std_logic;
+  FFC_TXPWDNB_1             : in std_logic;
+  FFC_TXPWDNB_2             : in std_logic;
+  FFC_TXPWDNB_3             : in std_logic;
+  FFC_RATE_MODE_RX_0        : in std_logic;
+  FFC_RATE_MODE_RX_1        : in std_logic;
+  FFC_RATE_MODE_RX_2        : in std_logic;
+  FFC_RATE_MODE_RX_3        : in std_logic;
+  FFC_RATE_MODE_TX_0        : in std_logic;
+  FFC_RATE_MODE_TX_1        : in std_logic;
+  FFC_RATE_MODE_TX_2        : in std_logic;
+  FFC_RATE_MODE_TX_3        : in std_logic;
+  FFC_DIV11_MODE_RX_0       : in std_logic;
+  FFC_DIV11_MODE_RX_1       : in std_logic;
+  FFC_DIV11_MODE_RX_2       : in std_logic;
+  FFC_DIV11_MODE_RX_3       : in std_logic;
+  FFC_DIV11_MODE_TX_0       : in std_logic;
+  FFC_DIV11_MODE_TX_1       : in std_logic;
+  FFC_DIV11_MODE_TX_2       : in std_logic;
+  FFC_DIV11_MODE_TX_3       : in std_logic;
+  LDR_CORE2TX_0             : in std_logic;
+  LDR_CORE2TX_1             : in std_logic;
+  LDR_CORE2TX_2             : in std_logic;
+  LDR_CORE2TX_3             : in std_logic;
+  FFC_LDR_CORE2TX_EN_0      : in std_logic;
+  FFC_LDR_CORE2TX_EN_1      : in std_logic;
+  FFC_LDR_CORE2TX_EN_2      : in std_logic;
+  FFC_LDR_CORE2TX_EN_3      : in std_logic;
+  PCIE_POWERDOWN_0_0      : in std_logic;
+  PCIE_POWERDOWN_0_1      : in std_logic;
+  PCIE_POWERDOWN_1_0      : in std_logic;
+  PCIE_POWERDOWN_1_1      : in std_logic;
+  PCIE_POWERDOWN_2_0      : in std_logic;
+  PCIE_POWERDOWN_2_1      : in std_logic;
+  PCIE_POWERDOWN_3_0      : in std_logic;
+  PCIE_POWERDOWN_3_1      : in std_logic;
+  PCIE_RXPOLARITY_0         : in std_logic;
+  PCIE_RXPOLARITY_1         : in std_logic;
+  PCIE_RXPOLARITY_2         : in std_logic;
+  PCIE_RXPOLARITY_3         : in std_logic;
+  PCIE_TXCOMPLIANCE_0       : in std_logic;
+  PCIE_TXCOMPLIANCE_1       : in std_logic;
+  PCIE_TXCOMPLIANCE_2       : in std_logic;
+  PCIE_TXCOMPLIANCE_3       : in std_logic;
+  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
+  SCIADDR0             : in std_logic;
+  SCIADDR1             : in std_logic;
+  SCIADDR2             : in std_logic;
+  SCIADDR3             : in std_logic;
+  SCIADDR4             : in std_logic;
+  SCIADDR5             : in std_logic;
+  SCIENAUX             : in std_logic;
+  SCIENCH0             : in std_logic;
+  SCIENCH1             : in std_logic;
+  SCIENCH2             : in std_logic;
+  SCIENCH3             : in std_logic;
+  SCIRD                : in std_logic;
+  SCISELAUX             : in std_logic;
+  SCISELCH0             : in std_logic;
+  SCISELCH1             : in std_logic;
+  SCISELCH2             : in std_logic;
+  SCISELCH3             : in std_logic;
+  SCIWDATA0             : in std_logic;
+  SCIWDATA1             : in std_logic;
+  SCIWDATA2             : in std_logic;
+  SCIWDATA3             : in std_logic;
+  SCIWDATA4             : in std_logic;
+  SCIWDATA5             : in std_logic;
+  SCIWDATA6             : in std_logic;
+  SCIWDATA7             : in std_logic;
+  SCIWSTN               : in std_logic;
+  REFCLK_FROM_NQ        : in std_logic;
+
+  HDOUTN0             : out std_logic;
+  HDOUTN1             : out std_logic;
+  HDOUTN2             : out std_logic;
+  HDOUTN3             : out std_logic;
+  HDOUTP0             : out std_logic;
+  HDOUTP1             : out std_logic;
+  HDOUTP2             : out std_logic;
+  HDOUTP3             : out std_logic;
+  COUT0             : out std_logic;
+  COUT1             : out std_logic;
+  COUT2             : out std_logic;
+  COUT3             : out std_logic;
+  COUT4             : out std_logic;
+  COUT5             : out std_logic;
+  COUT6             : out std_logic;
+  COUT7             : out std_logic;
+  COUT8             : out std_logic;
+  COUT9             : out std_logic;
+  COUT10             : out std_logic;
+  COUT11             : out std_logic;
+  COUT12             : out std_logic;
+  COUT13             : out std_logic;
+  COUT14             : out std_logic;
+  COUT15             : out std_logic;
+  COUT16             : out std_logic;
+  COUT17             : out std_logic;
+  COUT18             : out std_logic;
+  COUT19             : out std_logic;
+  FF_RX_D_0_0             : out std_logic;
+  FF_RX_D_0_1             : out std_logic;
+  FF_RX_D_0_2             : out std_logic;
+  FF_RX_D_0_3             : out std_logic;
+  FF_RX_D_0_4             : out std_logic;
+  FF_RX_D_0_5             : out std_logic;
+  FF_RX_D_0_6             : out std_logic;
+  FF_RX_D_0_7             : out std_logic;
+  FF_RX_D_0_8             : out std_logic;
+  FF_RX_D_0_9             : out std_logic;
+  FF_RX_D_0_10             : out std_logic;
+  FF_RX_D_0_11             : out std_logic;
+  FF_RX_D_0_12             : out std_logic;
+  FF_RX_D_0_13             : out std_logic;
+  FF_RX_D_0_14             : out std_logic;
+  FF_RX_D_0_15             : out std_logic;
+  FF_RX_D_0_16             : out std_logic;
+  FF_RX_D_0_17             : out std_logic;
+  FF_RX_D_0_18             : out std_logic;
+  FF_RX_D_0_19             : out std_logic;
+  FF_RX_D_0_20             : out std_logic;
+  FF_RX_D_0_21             : out std_logic;
+  FF_RX_D_0_22             : out std_logic;
+  FF_RX_D_0_23             : out std_logic;
+  FF_RX_D_1_0             : out std_logic;
+  FF_RX_D_1_1             : out std_logic;
+  FF_RX_D_1_2             : out std_logic;
+  FF_RX_D_1_3             : out std_logic;
+  FF_RX_D_1_4             : out std_logic;
+  FF_RX_D_1_5             : out std_logic;
+  FF_RX_D_1_6             : out std_logic;
+  FF_RX_D_1_7             : out std_logic;
+  FF_RX_D_1_8             : out std_logic;
+  FF_RX_D_1_9             : out std_logic;
+  FF_RX_D_1_10             : out std_logic;
+  FF_RX_D_1_11             : out std_logic;
+  FF_RX_D_1_12             : out std_logic;
+  FF_RX_D_1_13             : out std_logic;
+  FF_RX_D_1_14             : out std_logic;
+  FF_RX_D_1_15             : out std_logic;
+  FF_RX_D_1_16             : out std_logic;
+  FF_RX_D_1_17             : out std_logic;
+  FF_RX_D_1_18             : out std_logic;
+  FF_RX_D_1_19             : out std_logic;
+  FF_RX_D_1_20             : out std_logic;
+  FF_RX_D_1_21             : out std_logic;
+  FF_RX_D_1_22             : out std_logic;
+  FF_RX_D_1_23             : out std_logic;
+  FF_RX_D_2_0             : out std_logic;
+  FF_RX_D_2_1             : out std_logic;
+  FF_RX_D_2_2             : out std_logic;
+  FF_RX_D_2_3             : out std_logic;
+  FF_RX_D_2_4             : out std_logic;
+  FF_RX_D_2_5             : out std_logic;
+  FF_RX_D_2_6             : out std_logic;
+  FF_RX_D_2_7             : out std_logic;
+  FF_RX_D_2_8             : out std_logic;
+  FF_RX_D_2_9             : out std_logic;
+  FF_RX_D_2_10             : out std_logic;
+  FF_RX_D_2_11             : out std_logic;
+  FF_RX_D_2_12             : out std_logic;
+  FF_RX_D_2_13             : out std_logic;
+  FF_RX_D_2_14             : out std_logic;
+  FF_RX_D_2_15             : out std_logic;
+  FF_RX_D_2_16             : out std_logic;
+  FF_RX_D_2_17             : out std_logic;
+  FF_RX_D_2_18             : out std_logic;
+  FF_RX_D_2_19             : out std_logic;
+  FF_RX_D_2_20             : out std_logic;
+  FF_RX_D_2_21             : out std_logic;
+  FF_RX_D_2_22             : out std_logic;
+  FF_RX_D_2_23             : out std_logic;
+  FF_RX_D_3_0             : out std_logic;
+  FF_RX_D_3_1             : out std_logic;
+  FF_RX_D_3_2             : out std_logic;
+  FF_RX_D_3_3             : out std_logic;
+  FF_RX_D_3_4             : out std_logic;
+  FF_RX_D_3_5             : out std_logic;
+  FF_RX_D_3_6             : out std_logic;
+  FF_RX_D_3_7             : out std_logic;
+  FF_RX_D_3_8             : out std_logic;
+  FF_RX_D_3_9             : out std_logic;
+  FF_RX_D_3_10             : out std_logic;
+  FF_RX_D_3_11             : out std_logic;
+  FF_RX_D_3_12             : out std_logic;
+  FF_RX_D_3_13             : out std_logic;
+  FF_RX_D_3_14             : out std_logic;
+  FF_RX_D_3_15             : out std_logic;
+  FF_RX_D_3_16             : out std_logic;
+  FF_RX_D_3_17             : out std_logic;
+  FF_RX_D_3_18             : out std_logic;
+  FF_RX_D_3_19             : out std_logic;
+  FF_RX_D_3_20             : out std_logic;
+  FF_RX_D_3_21             : out std_logic;
+  FF_RX_D_3_22             : out std_logic;
+  FF_RX_D_3_23             : out std_logic;
+  FF_RX_F_CLK_0             : out std_logic;
+  FF_RX_F_CLK_1             : out std_logic;
+  FF_RX_F_CLK_2             : out std_logic;
+  FF_RX_F_CLK_3             : out std_logic;
+  FF_RX_H_CLK_0             : out std_logic;
+  FF_RX_H_CLK_1             : out std_logic;
+  FF_RX_H_CLK_2             : out std_logic;
+  FF_RX_H_CLK_3             : out std_logic;
+  FF_TX_F_CLK_0             : out std_logic;
+  FF_TX_F_CLK_1             : out std_logic;
+  FF_TX_F_CLK_2             : out std_logic;
+  FF_TX_F_CLK_3             : out std_logic;
+  FF_TX_H_CLK_0             : out std_logic;
+  FF_TX_H_CLK_1             : out std_logic;
+  FF_TX_H_CLK_2             : out std_logic;
+  FF_TX_H_CLK_3             : out std_logic;
+  FFS_CC_OVERRUN_0             : out std_logic;
+  FFS_CC_OVERRUN_1             : out std_logic;
+  FFS_CC_OVERRUN_2             : out std_logic;
+  FFS_CC_OVERRUN_3             : out std_logic;
+  FFS_CC_UNDERRUN_0             : out std_logic;
+  FFS_CC_UNDERRUN_1             : out std_logic;
+  FFS_CC_UNDERRUN_2             : out std_logic;
+  FFS_CC_UNDERRUN_3             : out std_logic;
+  FFS_LS_SYNC_STATUS_0             : out std_logic;
+  FFS_LS_SYNC_STATUS_1             : out std_logic;
+  FFS_LS_SYNC_STATUS_2             : out std_logic;
+  FFS_LS_SYNC_STATUS_3             : out std_logic;
+  FFS_CDR_TRAIN_DONE_0             : out std_logic;
+  FFS_CDR_TRAIN_DONE_1             : out std_logic;
+  FFS_CDR_TRAIN_DONE_2             : out std_logic;
+  FFS_CDR_TRAIN_DONE_3             : out std_logic;
+  FFS_PCIE_CON_0             : out std_logic;
+  FFS_PCIE_CON_1             : out std_logic;
+  FFS_PCIE_CON_2             : out std_logic;
+  FFS_PCIE_CON_3             : out std_logic;
+  FFS_PCIE_DONE_0             : out std_logic;
+  FFS_PCIE_DONE_1             : out std_logic;
+  FFS_PCIE_DONE_2             : out std_logic;
+  FFS_PCIE_DONE_3             : out std_logic;
+  FFS_PLOL             : out std_logic;
+  FFS_RLOL_0             : out std_logic;
+  FFS_RLOL_1             : out std_logic;
+  FFS_RLOL_2             : out std_logic;
+  FFS_RLOL_3             : out std_logic;
+  FFS_RLOS_HI_0             : out std_logic;
+  FFS_RLOS_HI_1             : out std_logic;
+  FFS_RLOS_HI_2             : out std_logic;
+  FFS_RLOS_HI_3             : out std_logic;
+  FFS_RLOS_LO_0             : out std_logic;
+  FFS_RLOS_LO_1             : out std_logic;
+  FFS_RLOS_LO_2             : out std_logic;
+  FFS_RLOS_LO_3             : out std_logic;
+  FFS_RXFBFIFO_ERROR_0             : out std_logic;
+  FFS_RXFBFIFO_ERROR_1             : out std_logic;
+  FFS_RXFBFIFO_ERROR_2             : out std_logic;
+  FFS_RXFBFIFO_ERROR_3             : out std_logic;
+  FFS_TXFBFIFO_ERROR_0             : out std_logic;
+  FFS_TXFBFIFO_ERROR_1             : out std_logic;
+  FFS_TXFBFIFO_ERROR_2             : out std_logic;
+  FFS_TXFBFIFO_ERROR_3             : out std_logic;
+  PCIE_PHYSTATUS_0             : out std_logic;
+  PCIE_PHYSTATUS_1             : out std_logic;
+  PCIE_PHYSTATUS_2             : out std_logic;
+  PCIE_PHYSTATUS_3             : out std_logic;
+  PCIE_RXVALID_0               : out std_logic;
+  PCIE_RXVALID_1               : out std_logic;
+  PCIE_RXVALID_2               : out std_logic;
+  PCIE_RXVALID_3               : out std_logic;
+  FFS_SKP_ADDED_0                  : out std_logic;
+  FFS_SKP_ADDED_1                  : out std_logic;
+  FFS_SKP_ADDED_2                  : out std_logic;
+  FFS_SKP_ADDED_3                  : out std_logic;
+  FFS_SKP_DELETED_0                : out std_logic;
+  FFS_SKP_DELETED_1                : out std_logic;
+  FFS_SKP_DELETED_2                : out std_logic;
+  FFS_SKP_DELETED_3                : out std_logic;
+  LDR_RX2CORE_0                    : out std_logic;
+  LDR_RX2CORE_1                    : out std_logic;
+  LDR_RX2CORE_2                    : out std_logic;
+  LDR_RX2CORE_3                    : out std_logic;
+  REFCK2CORE             : out std_logic;
+  SCIINT                : out std_logic;
+  SCIRDATA0             : out std_logic;
+  SCIRDATA1             : out std_logic;
+  SCIRDATA2             : out std_logic;
+  SCIRDATA3             : out std_logic;
+  SCIRDATA4             : out std_logic;
+  SCIRDATA5             : out std_logic;
+  SCIRDATA6             : out std_logic;
+  SCIRDATA7             : out std_logic;
+  REFCLK_TO_NQ          : out std_logic
+);
+
+end PCSD;
+
+architecture PCSD_arch of PCSD is
+
+
+component PCSD_sim
+GENERIC(
+  CONFIG_FILE : String;
+  QUAD_MODE : String;
+  CH0_CDR_SRC   : String;
+  CH1_CDR_SRC   : String;
+  CH2_CDR_SRC   : String;
+  CH3_CDR_SRC   : String;
+  PLL_SRC   : String
+  );
+port (
+  HDINN0             : in std_logic;
+  HDINN1             : in std_logic;
+  HDINN2             : in std_logic;
+  HDINN3             : in std_logic;
+  HDINP0             : in std_logic;
+  HDINP1             : in std_logic;
+  HDINP2             : in std_logic;
+  HDINP3             : in std_logic;
+  REFCLKN             : in std_logic;
+  REFCLKP             : in std_logic;
+  CIN0             : in std_logic;
+  CIN1             : in std_logic;
+  CIN2             : in std_logic;
+  CIN3             : in std_logic;
+  CIN4             : in std_logic;
+  CIN5             : in std_logic;
+  CIN6             : in std_logic;
+  CIN7             : in std_logic;
+  CIN8             : in std_logic;
+  CIN9             : in std_logic;
+  CIN10             : in std_logic;
+  CIN11             : in std_logic;
+  CYAWSTN             : in std_logic;
+  FF_EBRD_CLK_0             : in std_logic;
+  FF_EBRD_CLK_1             : in std_logic;
+  FF_EBRD_CLK_2             : in std_logic;
+  FF_EBRD_CLK_3             : in std_logic;
+  FF_RXI_CLK_0             : in std_logic;
+  FF_RXI_CLK_1             : in std_logic;
+  FF_RXI_CLK_2             : in std_logic;
+  FF_RXI_CLK_3             : in std_logic;
+  FF_TX_D_0_0             : in std_logic;
+  FF_TX_D_0_1             : in std_logic;
+  FF_TX_D_0_2             : in std_logic;
+  FF_TX_D_0_3             : in std_logic;
+  FF_TX_D_0_4             : in std_logic;
+  FF_TX_D_0_5             : in std_logic;
+  FF_TX_D_0_6             : in std_logic;
+  FF_TX_D_0_7             : in std_logic;
+  FF_TX_D_0_8             : in std_logic;
+  FF_TX_D_0_9             : in std_logic;
+  FF_TX_D_0_10             : in std_logic;
+  FF_TX_D_0_11             : in std_logic;
+  FF_TX_D_0_12             : in std_logic;
+  FF_TX_D_0_13             : in std_logic;
+  FF_TX_D_0_14             : in std_logic;
+  FF_TX_D_0_15             : in std_logic;
+  FF_TX_D_0_16             : in std_logic;
+  FF_TX_D_0_17             : in std_logic;
+  FF_TX_D_0_18             : in std_logic;
+  FF_TX_D_0_19             : in std_logic;
+  FF_TX_D_0_20             : in std_logic;
+  FF_TX_D_0_21             : in std_logic;
+  FF_TX_D_0_22             : in std_logic;
+  FF_TX_D_0_23             : in std_logic;
+  FF_TX_D_1_0             : in std_logic;
+  FF_TX_D_1_1             : in std_logic;
+  FF_TX_D_1_2             : in std_logic;
+  FF_TX_D_1_3             : in std_logic;
+  FF_TX_D_1_4             : in std_logic;
+  FF_TX_D_1_5             : in std_logic;
+  FF_TX_D_1_6             : in std_logic;
+  FF_TX_D_1_7             : in std_logic;
+  FF_TX_D_1_8             : in std_logic;
+  FF_TX_D_1_9             : in std_logic;
+  FF_TX_D_1_10             : in std_logic;
+  FF_TX_D_1_11             : in std_logic;
+  FF_TX_D_1_12             : in std_logic;
+  FF_TX_D_1_13             : in std_logic;
+  FF_TX_D_1_14             : in std_logic;
+  FF_TX_D_1_15             : in std_logic;
+  FF_TX_D_1_16             : in std_logic;
+  FF_TX_D_1_17             : in std_logic;
+  FF_TX_D_1_18             : in std_logic;
+  FF_TX_D_1_19             : in std_logic;
+  FF_TX_D_1_20             : in std_logic;
+  FF_TX_D_1_21             : in std_logic;
+  FF_TX_D_1_22             : in std_logic;
+  FF_TX_D_1_23             : in std_logic;
+  FF_TX_D_2_0             : in std_logic;
+  FF_TX_D_2_1             : in std_logic;
+  FF_TX_D_2_2             : in std_logic;
+  FF_TX_D_2_3             : in std_logic;
+  FF_TX_D_2_4             : in std_logic;
+  FF_TX_D_2_5             : in std_logic;
+  FF_TX_D_2_6             : in std_logic;
+  FF_TX_D_2_7             : in std_logic;
+  FF_TX_D_2_8             : in std_logic;
+  FF_TX_D_2_9             : in std_logic;
+  FF_TX_D_2_10             : in std_logic;
+  FF_TX_D_2_11             : in std_logic;
+  FF_TX_D_2_12             : in std_logic;
+  FF_TX_D_2_13             : in std_logic;
+  FF_TX_D_2_14             : in std_logic;
+  FF_TX_D_2_15             : in std_logic;
+  FF_TX_D_2_16             : in std_logic;
+  FF_TX_D_2_17             : in std_logic;
+  FF_TX_D_2_18             : in std_logic;
+  FF_TX_D_2_19             : in std_logic;
+  FF_TX_D_2_20             : in std_logic;
+  FF_TX_D_2_21             : in std_logic;
+  FF_TX_D_2_22             : in std_logic;
+  FF_TX_D_2_23             : in std_logic;
+  FF_TX_D_3_0             : in std_logic;
+  FF_TX_D_3_1             : in std_logic;
+  FF_TX_D_3_2             : in std_logic;
+  FF_TX_D_3_3             : in std_logic;
+  FF_TX_D_3_4             : in std_logic;
+  FF_TX_D_3_5             : in std_logic;
+  FF_TX_D_3_6             : in std_logic;
+  FF_TX_D_3_7             : in std_logic;
+  FF_TX_D_3_8             : in std_logic;
+  FF_TX_D_3_9             : in std_logic;
+  FF_TX_D_3_10             : in std_logic;
+  FF_TX_D_3_11             : in std_logic;
+  FF_TX_D_3_12             : in std_logic;
+  FF_TX_D_3_13             : in std_logic;
+  FF_TX_D_3_14             : in std_logic;
+  FF_TX_D_3_15             : in std_logic;
+  FF_TX_D_3_16             : in std_logic;
+  FF_TX_D_3_17             : in std_logic;
+  FF_TX_D_3_18             : in std_logic;
+  FF_TX_D_3_19             : in std_logic;
+  FF_TX_D_3_20             : in std_logic;
+  FF_TX_D_3_21             : in std_logic;
+  FF_TX_D_3_22             : in std_logic;
+  FF_TX_D_3_23             : in std_logic;
+  FF_TXI_CLK_0             : in std_logic;
+  FF_TXI_CLK_1             : in std_logic;
+  FF_TXI_CLK_2             : in std_logic;
+  FF_TXI_CLK_3             : in std_logic;
+  FFC_CK_CORE_RX_0         : in std_logic;
+  FFC_CK_CORE_RX_1         : in std_logic;
+  FFC_CK_CORE_RX_2         : in std_logic;
+  FFC_CK_CORE_RX_3         : in std_logic;
+  FFC_CK_CORE_TX           : in std_logic;
+  FFC_EI_EN_0             : in std_logic;
+  FFC_EI_EN_1             : in std_logic;
+  FFC_EI_EN_2             : in std_logic;
+  FFC_EI_EN_3             : in std_logic;
+  FFC_ENABLE_CGALIGN_0             : in std_logic;
+  FFC_ENABLE_CGALIGN_1             : in std_logic;
+  FFC_ENABLE_CGALIGN_2             : in std_logic;
+  FFC_ENABLE_CGALIGN_3             : in std_logic;
+  FFC_FB_LOOPBACK_0             : in std_logic;
+  FFC_FB_LOOPBACK_1             : in std_logic;
+  FFC_FB_LOOPBACK_2             : in std_logic;
+  FFC_FB_LOOPBACK_3             : in std_logic;
+  FFC_LANE_RX_RST_0             : in std_logic;
+  FFC_LANE_RX_RST_1             : in std_logic;
+  FFC_LANE_RX_RST_2             : in std_logic;
+  FFC_LANE_RX_RST_3             : in std_logic;
+  FFC_LANE_TX_RST_0             : in std_logic;
+  FFC_LANE_TX_RST_1             : in std_logic;
+  FFC_LANE_TX_RST_2             : in std_logic;
+  FFC_LANE_TX_RST_3             : in std_logic;
+  FFC_MACRO_RST             : in std_logic;
+  FFC_PCI_DET_EN_0             : in std_logic;
+  FFC_PCI_DET_EN_1             : in std_logic;
+  FFC_PCI_DET_EN_2             : in std_logic;
+  FFC_PCI_DET_EN_3             : in std_logic;
+  FFC_PCIE_CT_0             : in std_logic;
+  FFC_PCIE_CT_1             : in std_logic;
+  FFC_PCIE_CT_2             : in std_logic;
+  FFC_PCIE_CT_3             : in std_logic;
+  FFC_PFIFO_CLR_0             : in std_logic;
+  FFC_PFIFO_CLR_1             : in std_logic;
+  FFC_PFIFO_CLR_2             : in std_logic;
+  FFC_PFIFO_CLR_3             : in std_logic;
+  FFC_QUAD_RST             : in std_logic;
+  FFC_RRST_0             : in std_logic;
+  FFC_RRST_1             : in std_logic;
+  FFC_RRST_2             : in std_logic;
+  FFC_RRST_3             : in std_logic;
+  FFC_RXPWDNB_0             : in std_logic;
+  FFC_RXPWDNB_1             : in std_logic;
+  FFC_RXPWDNB_2             : in std_logic;
+  FFC_RXPWDNB_3             : in std_logic;
+  FFC_SB_INV_RX_0             : in std_logic;
+  FFC_SB_INV_RX_1             : in std_logic;
+  FFC_SB_INV_RX_2             : in std_logic;
+  FFC_SB_INV_RX_3             : in std_logic;
+  FFC_SB_PFIFO_LP_0             : in std_logic;
+  FFC_SB_PFIFO_LP_1             : in std_logic;
+  FFC_SB_PFIFO_LP_2             : in std_logic;
+  FFC_SB_PFIFO_LP_3             : in std_logic;
+  FFC_SIGNAL_DETECT_0             : in std_logic;
+  FFC_SIGNAL_DETECT_1             : in std_logic;
+  FFC_SIGNAL_DETECT_2             : in std_logic;
+  FFC_SIGNAL_DETECT_3             : in std_logic;
+  FFC_SYNC_TOGGLE             : in std_logic;
+  FFC_TRST             : in std_logic;
+  FFC_TXPWDNB_0             : in std_logic;
+  FFC_TXPWDNB_1             : in std_logic;
+  FFC_TXPWDNB_2             : in std_logic;
+  FFC_TXPWDNB_3             : in std_logic;
+  FFC_RATE_MODE_RX_0        : in std_logic;
+  FFC_RATE_MODE_RX_1        : in std_logic;
+  FFC_RATE_MODE_RX_2        : in std_logic;
+  FFC_RATE_MODE_RX_3        : in std_logic;
+  FFC_RATE_MODE_TX_0        : in std_logic;
+  FFC_RATE_MODE_TX_1        : in std_logic;
+  FFC_RATE_MODE_TX_2        : in std_logic;
+  FFC_RATE_MODE_TX_3        : in std_logic;
+  FFC_DIV11_MODE_RX_0       : in std_logic;
+  FFC_DIV11_MODE_RX_1       : in std_logic;
+  FFC_DIV11_MODE_RX_2       : in std_logic;
+  FFC_DIV11_MODE_RX_3       : in std_logic;
+  FFC_DIV11_MODE_TX_0       : in std_logic;
+  FFC_DIV11_MODE_TX_1       : in std_logic;
+  FFC_DIV11_MODE_TX_2       : in std_logic;
+  FFC_DIV11_MODE_TX_3       : in std_logic;
+  LDR_CORE2TX_0             : in std_logic;
+  LDR_CORE2TX_1             : in std_logic;
+  LDR_CORE2TX_2             : in std_logic;
+  LDR_CORE2TX_3             : in std_logic;
+  FFC_LDR_CORE2TX_EN_0      : in std_logic;
+  FFC_LDR_CORE2TX_EN_1      : in std_logic;
+  FFC_LDR_CORE2TX_EN_2      : in std_logic;
+  FFC_LDR_CORE2TX_EN_3      : in std_logic;
+  PCIE_POWERDOWN_0_0      : in std_logic;
+  PCIE_POWERDOWN_0_1      : in std_logic;
+  PCIE_POWERDOWN_1_0      : in std_logic;
+  PCIE_POWERDOWN_1_1      : in std_logic;
+  PCIE_POWERDOWN_2_0      : in std_logic;
+  PCIE_POWERDOWN_2_1      : in std_logic;
+  PCIE_POWERDOWN_3_0      : in std_logic;
+  PCIE_POWERDOWN_3_1      : in std_logic;
+  PCIE_RXPOLARITY_0         : in std_logic;
+  PCIE_RXPOLARITY_1         : in std_logic;
+  PCIE_RXPOLARITY_2         : in std_logic;
+  PCIE_RXPOLARITY_3         : in std_logic;
+  PCIE_TXCOMPLIANCE_0       : in std_logic;
+  PCIE_TXCOMPLIANCE_1       : in std_logic;
+  PCIE_TXCOMPLIANCE_2       : in std_logic;
+  PCIE_TXCOMPLIANCE_3       : in std_logic;
+  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
+  SCIADDR0             : in std_logic;
+  SCIADDR1             : in std_logic;
+  SCIADDR2             : in std_logic;
+  SCIADDR3             : in std_logic;
+  SCIADDR4             : in std_logic;
+  SCIADDR5             : in std_logic;
+  SCIENAUX             : in std_logic;
+  SCIENCH0             : in std_logic;
+  SCIENCH1             : in std_logic;
+  SCIENCH2             : in std_logic;
+  SCIENCH3             : in std_logic;
+  SCIRD                : in std_logic;
+  SCISELAUX             : in std_logic;
+  SCISELCH0             : in std_logic;
+  SCISELCH1             : in std_logic;
+  SCISELCH2             : in std_logic;
+  SCISELCH3             : in std_logic;
+  SCIWDATA0             : in std_logic;
+  SCIWDATA1             : in std_logic;
+  SCIWDATA2             : in std_logic;
+  SCIWDATA3             : in std_logic;
+  SCIWDATA4             : in std_logic;
+  SCIWDATA5             : in std_logic;
+  SCIWDATA6             : in std_logic;
+  SCIWDATA7             : in std_logic;
+  SCIWSTN               : in std_logic;
+  REFCLK_FROM_NQ        : in std_logic;
+
+  HDOUTN0             : out std_logic;
+  HDOUTN1             : out std_logic;
+  HDOUTN2             : out std_logic;
+  HDOUTN3             : out std_logic;
+  HDOUTP0             : out std_logic;
+  HDOUTP1             : out std_logic;
+  HDOUTP2             : out std_logic;
+  HDOUTP3             : out std_logic;
+  COUT0             : out std_logic;
+  COUT1             : out std_logic;
+  COUT2             : out std_logic;
+  COUT3             : out std_logic;
+  COUT4             : out std_logic;
+  COUT5             : out std_logic;
+  COUT6             : out std_logic;
+  COUT7             : out std_logic;
+  COUT8             : out std_logic;
+  COUT9             : out std_logic;
+  COUT10             : out std_logic;
+  COUT11             : out std_logic;
+  COUT12             : out std_logic;
+  COUT13             : out std_logic;
+  COUT14             : out std_logic;
+  COUT15             : out std_logic;
+  COUT16             : out std_logic;
+  COUT17             : out std_logic;
+  COUT18             : out std_logic;
+  COUT19             : out std_logic;
+  FF_RX_D_0_0             : out std_logic;
+  FF_RX_D_0_1             : out std_logic;
+  FF_RX_D_0_2             : out std_logic;
+  FF_RX_D_0_3             : out std_logic;
+  FF_RX_D_0_4             : out std_logic;
+  FF_RX_D_0_5             : out std_logic;
+  FF_RX_D_0_6             : out std_logic;
+  FF_RX_D_0_7             : out std_logic;
+  FF_RX_D_0_8             : out std_logic;
+  FF_RX_D_0_9             : out std_logic;
+  FF_RX_D_0_10             : out std_logic;
+  FF_RX_D_0_11             : out std_logic;
+  FF_RX_D_0_12             : out std_logic;
+  FF_RX_D_0_13             : out std_logic;
+  FF_RX_D_0_14             : out std_logic;
+  FF_RX_D_0_15             : out std_logic;
+  FF_RX_D_0_16             : out std_logic;
+  FF_RX_D_0_17             : out std_logic;
+  FF_RX_D_0_18             : out std_logic;
+  FF_RX_D_0_19             : out std_logic;
+  FF_RX_D_0_20             : out std_logic;
+  FF_RX_D_0_21             : out std_logic;
+  FF_RX_D_0_22             : out std_logic;
+  FF_RX_D_0_23             : out std_logic;
+  FF_RX_D_1_0             : out std_logic;
+  FF_RX_D_1_1             : out std_logic;
+  FF_RX_D_1_2             : out std_logic;
+  FF_RX_D_1_3             : out std_logic;
+  FF_RX_D_1_4             : out std_logic;
+  FF_RX_D_1_5             : out std_logic;
+  FF_RX_D_1_6             : out std_logic;
+  FF_RX_D_1_7             : out std_logic;
+  FF_RX_D_1_8             : out std_logic;
+  FF_RX_D_1_9             : out std_logic;
+  FF_RX_D_1_10             : out std_logic;
+  FF_RX_D_1_11             : out std_logic;
+  FF_RX_D_1_12             : out std_logic;
+  FF_RX_D_1_13             : out std_logic;
+  FF_RX_D_1_14             : out std_logic;
+  FF_RX_D_1_15             : out std_logic;
+  FF_RX_D_1_16             : out std_logic;
+  FF_RX_D_1_17             : out std_logic;
+  FF_RX_D_1_18             : out std_logic;
+  FF_RX_D_1_19             : out std_logic;
+  FF_RX_D_1_20             : out std_logic;
+  FF_RX_D_1_21             : out std_logic;
+  FF_RX_D_1_22             : out std_logic;
+  FF_RX_D_1_23             : out std_logic;
+  FF_RX_D_2_0             : out std_logic;
+  FF_RX_D_2_1             : out std_logic;
+  FF_RX_D_2_2             : out std_logic;
+  FF_RX_D_2_3             : out std_logic;
+  FF_RX_D_2_4             : out std_logic;
+  FF_RX_D_2_5             : out std_logic;
+  FF_RX_D_2_6             : out std_logic;
+  FF_RX_D_2_7             : out std_logic;
+  FF_RX_D_2_8             : out std_logic;
+  FF_RX_D_2_9             : out std_logic;
+  FF_RX_D_2_10             : out std_logic;
+  FF_RX_D_2_11             : out std_logic;
+  FF_RX_D_2_12             : out std_logic;
+  FF_RX_D_2_13             : out std_logic;
+  FF_RX_D_2_14             : out std_logic;
+  FF_RX_D_2_15             : out std_logic;
+  FF_RX_D_2_16             : out std_logic;
+  FF_RX_D_2_17             : out std_logic;
+  FF_RX_D_2_18             : out std_logic;
+  FF_RX_D_2_19             : out std_logic;
+  FF_RX_D_2_20             : out std_logic;
+  FF_RX_D_2_21             : out std_logic;
+  FF_RX_D_2_22             : out std_logic;
+  FF_RX_D_2_23             : out std_logic;
+  FF_RX_D_3_0             : out std_logic;
+  FF_RX_D_3_1             : out std_logic;
+  FF_RX_D_3_2             : out std_logic;
+  FF_RX_D_3_3             : out std_logic;
+  FF_RX_D_3_4             : out std_logic;
+  FF_RX_D_3_5             : out std_logic;
+  FF_RX_D_3_6             : out std_logic;
+  FF_RX_D_3_7             : out std_logic;
+  FF_RX_D_3_8             : out std_logic;
+  FF_RX_D_3_9             : out std_logic;
+  FF_RX_D_3_10             : out std_logic;
+  FF_RX_D_3_11             : out std_logic;
+  FF_RX_D_3_12             : out std_logic;
+  FF_RX_D_3_13             : out std_logic;
+  FF_RX_D_3_14             : out std_logic;
+  FF_RX_D_3_15             : out std_logic;
+  FF_RX_D_3_16             : out std_logic;
+  FF_RX_D_3_17             : out std_logic;
+  FF_RX_D_3_18             : out std_logic;
+  FF_RX_D_3_19             : out std_logic;
+  FF_RX_D_3_20             : out std_logic;
+  FF_RX_D_3_21             : out std_logic;
+  FF_RX_D_3_22             : out std_logic;
+  FF_RX_D_3_23             : out std_logic;
+  FF_RX_F_CLK_0             : out std_logic;
+  FF_RX_F_CLK_1             : out std_logic;
+  FF_RX_F_CLK_2             : out std_logic;
+  FF_RX_F_CLK_3             : out std_logic;
+  FF_RX_H_CLK_0             : out std_logic;
+  FF_RX_H_CLK_1             : out std_logic;
+  FF_RX_H_CLK_2             : out std_logic;
+  FF_RX_H_CLK_3             : out std_logic;
+  FF_TX_F_CLK_0             : out std_logic;
+  FF_TX_F_CLK_1             : out std_logic;
+  FF_TX_F_CLK_2             : out std_logic;
+  FF_TX_F_CLK_3             : out std_logic;
+  FF_TX_H_CLK_0             : out std_logic;
+  FF_TX_H_CLK_1             : out std_logic;
+  FF_TX_H_CLK_2             : out std_logic;
+  FF_TX_H_CLK_3             : out std_logic;
+  FFS_CC_OVERRUN_0             : out std_logic;
+  FFS_CC_OVERRUN_1             : out std_logic;
+  FFS_CC_OVERRUN_2             : out std_logic;
+  FFS_CC_OVERRUN_3             : out std_logic;
+  FFS_CC_UNDERRUN_0             : out std_logic;
+  FFS_CC_UNDERRUN_1             : out std_logic;
+  FFS_CC_UNDERRUN_2             : out std_logic;
+  FFS_CC_UNDERRUN_3             : out std_logic;
+  FFS_LS_SYNC_STATUS_0             : out std_logic;
+  FFS_LS_SYNC_STATUS_1             : out std_logic;
+  FFS_LS_SYNC_STATUS_2             : out std_logic;
+  FFS_LS_SYNC_STATUS_3             : out std_logic;
+  FFS_CDR_TRAIN_DONE_0             : out std_logic;
+  FFS_CDR_TRAIN_DONE_1             : out std_logic;
+  FFS_CDR_TRAIN_DONE_2             : out std_logic;
+  FFS_CDR_TRAIN_DONE_3             : out std_logic;
+  FFS_PCIE_CON_0             : out std_logic;
+  FFS_PCIE_CON_1             : out std_logic;
+  FFS_PCIE_CON_2             : out std_logic;
+  FFS_PCIE_CON_3             : out std_logic;
+  FFS_PCIE_DONE_0             : out std_logic;
+  FFS_PCIE_DONE_1             : out std_logic;
+  FFS_PCIE_DONE_2             : out std_logic;
+  FFS_PCIE_DONE_3             : out std_logic;
+  FFS_PLOL             : out std_logic;
+  FFS_RLOL_0             : out std_logic;
+  FFS_RLOL_1             : out std_logic;
+  FFS_RLOL_2             : out std_logic;
+  FFS_RLOL_3             : out std_logic;
+  FFS_RLOS_HI_0             : out std_logic;
+  FFS_RLOS_HI_1             : out std_logic;
+  FFS_RLOS_HI_2             : out std_logic;
+  FFS_RLOS_HI_3             : out std_logic;
+  FFS_RLOS_LO_0             : out std_logic;
+  FFS_RLOS_LO_1             : out std_logic;
+  FFS_RLOS_LO_2             : out std_logic;
+  FFS_RLOS_LO_3             : out std_logic;
+  FFS_RXFBFIFO_ERROR_0             : out std_logic;
+  FFS_RXFBFIFO_ERROR_1             : out std_logic;
+  FFS_RXFBFIFO_ERROR_2             : out std_logic;
+  FFS_RXFBFIFO_ERROR_3             : out std_logic;
+  FFS_TXFBFIFO_ERROR_0             : out std_logic;
+  FFS_TXFBFIFO_ERROR_1             : out std_logic;
+  FFS_TXFBFIFO_ERROR_2             : out std_logic;
+  FFS_TXFBFIFO_ERROR_3             : out std_logic;
+  PCIE_PHYSTATUS_0             : out std_logic;
+  PCIE_PHYSTATUS_1             : out std_logic;
+  PCIE_PHYSTATUS_2             : out std_logic;
+  PCIE_PHYSTATUS_3             : out std_logic;
+  PCIE_RXVALID_0               : out std_logic;
+  PCIE_RXVALID_1               : out std_logic;
+  PCIE_RXVALID_2               : out std_logic;
+  PCIE_RXVALID_3               : out std_logic;
+  FFS_SKP_ADDED_0                  : out std_logic;
+  FFS_SKP_ADDED_1                  : out std_logic;
+  FFS_SKP_ADDED_2                  : out std_logic;
+  FFS_SKP_ADDED_3                  : out std_logic;
+  FFS_SKP_DELETED_0                : out std_logic;
+  FFS_SKP_DELETED_1                : out std_logic;
+  FFS_SKP_DELETED_2                : out std_logic;
+  FFS_SKP_DELETED_3                : out std_logic;
+  LDR_RX2CORE_0                    : out std_logic;
+  LDR_RX2CORE_1                    : out std_logic;
+  LDR_RX2CORE_2                    : out std_logic;
+  LDR_RX2CORE_3                    : out std_logic;
+  REFCK2CORE             : out std_logic;
+  SCIINT                : out std_logic;
+  SCIRDATA0             : out std_logic;
+  SCIRDATA1             : out std_logic;
+  SCIRDATA2             : out std_logic;
+  SCIRDATA3             : out std_logic;
+  SCIRDATA4             : out std_logic;
+  SCIRDATA5             : out std_logic;
+  SCIRDATA6             : out std_logic;
+  SCIRDATA7             : out std_logic;
+  REFCLK_TO_NQ          : out std_logic
+);
+end component;
+
+begin
+
+PCSD_sim_inst : PCSD_sim
+generic map (
+  CONFIG_FILE => CONFIG_FILE,
+  QUAD_MODE => QUAD_MODE,
+  CH0_CDR_SRC => CH0_CDR_SRC,
+  CH1_CDR_SRC => CH1_CDR_SRC,
+  CH2_CDR_SRC => CH2_CDR_SRC,
+  CH3_CDR_SRC => CH3_CDR_SRC,
+  PLL_SRC => PLL_SRC
+  )
+port map (
+   HDINN0 => HDINN0,
+   HDINN1 => HDINN1,
+   HDINN2 => HDINN2,
+   HDINN3 => HDINN3,
+   HDINP0 => HDINP0,
+   HDINP1 => HDINP1,
+   HDINP2 => HDINP2,
+   HDINP3 => HDINP3,
+   REFCLKN => REFCLKN,
+   REFCLKP => REFCLKP,
+   CIN11 => CIN11,
+   CIN10 => CIN10,
+   CIN9 => CIN9,
+   CIN8 => CIN8,
+   CIN7 => CIN7,
+   CIN6 => CIN6,
+   CIN5 => CIN5,
+   CIN4 => CIN4,
+   CIN3 => CIN3,
+   CIN2 => CIN2,
+   CIN1 => CIN1,
+   CIN0 => CIN0,
+   CYAWSTN => CYAWSTN,
+   FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
+   FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
+   FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
+   FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
+   FF_RXI_CLK_3 => FF_RXI_CLK_3,
+   FF_RXI_CLK_2 => FF_RXI_CLK_2,
+   FF_RXI_CLK_1 => FF_RXI_CLK_1,
+   FF_RXI_CLK_0 => FF_RXI_CLK_0,
+   FF_TX_D_0_0 => FF_TX_D_0_0,
+   FF_TX_D_0_1 => FF_TX_D_0_1,
+   FF_TX_D_0_2 => FF_TX_D_0_2,
+   FF_TX_D_0_3 => FF_TX_D_0_3,
+   FF_TX_D_0_4 => FF_TX_D_0_4,
+   FF_TX_D_0_5 => FF_TX_D_0_5,
+   FF_TX_D_0_6 => FF_TX_D_0_6,
+   FF_TX_D_0_7 => FF_TX_D_0_7,
+   FF_TX_D_0_8 => FF_TX_D_0_8,
+   FF_TX_D_0_9 => FF_TX_D_0_9,
+   FF_TX_D_0_10 => FF_TX_D_0_10,
+   FF_TX_D_0_11 => FF_TX_D_0_11,
+   FF_TX_D_0_12 => FF_TX_D_0_12,
+   FF_TX_D_0_13 => FF_TX_D_0_13,
+   FF_TX_D_0_14 => FF_TX_D_0_14,
+   FF_TX_D_0_15 => FF_TX_D_0_15,
+   FF_TX_D_0_16 => FF_TX_D_0_16,
+   FF_TX_D_0_17 => FF_TX_D_0_17,
+   FF_TX_D_0_18 => FF_TX_D_0_18,
+   FF_TX_D_0_19 => FF_TX_D_0_19,
+   FF_TX_D_0_20 => FF_TX_D_0_20,
+   FF_TX_D_0_21 => FF_TX_D_0_21,
+   FF_TX_D_0_22 => FF_TX_D_0_22,
+   FF_TX_D_0_23 => FF_TX_D_0_23,
+   FF_TX_D_1_0 => FF_TX_D_1_0,
+   FF_TX_D_1_1 => FF_TX_D_1_1,
+   FF_TX_D_1_2 => FF_TX_D_1_2,
+   FF_TX_D_1_3 => FF_TX_D_1_3,
+   FF_TX_D_1_4 => FF_TX_D_1_4,
+   FF_TX_D_1_5 => FF_TX_D_1_5,
+   FF_TX_D_1_6 => FF_TX_D_1_6,
+   FF_TX_D_1_7 => FF_TX_D_1_7,
+   FF_TX_D_1_8 => FF_TX_D_1_8,
+   FF_TX_D_1_9 => FF_TX_D_1_9,
+   FF_TX_D_1_10 => FF_TX_D_1_10,
+   FF_TX_D_1_11 => FF_TX_D_1_11,
+   FF_TX_D_1_12 => FF_TX_D_1_12,
+   FF_TX_D_1_13 => FF_TX_D_1_13,
+   FF_TX_D_1_14 => FF_TX_D_1_14,
+   FF_TX_D_1_15 => FF_TX_D_1_15,
+   FF_TX_D_1_16 => FF_TX_D_1_16,
+   FF_TX_D_1_17 => FF_TX_D_1_17,
+   FF_TX_D_1_18 => FF_TX_D_1_18,
+   FF_TX_D_1_19 => FF_TX_D_1_19,
+   FF_TX_D_1_20 => FF_TX_D_1_20,
+   FF_TX_D_1_21 => FF_TX_D_1_21,
+   FF_TX_D_1_22 => FF_TX_D_1_22,
+   FF_TX_D_1_23 => FF_TX_D_1_23,
+   FF_TX_D_2_0 => FF_TX_D_2_0,
+   FF_TX_D_2_1 => FF_TX_D_2_1,
+   FF_TX_D_2_2 => FF_TX_D_2_2,
+   FF_TX_D_2_3 => FF_TX_D_2_3,
+   FF_TX_D_2_4 => FF_TX_D_2_4,
+   FF_TX_D_2_5 => FF_TX_D_2_5,
+   FF_TX_D_2_6 => FF_TX_D_2_6,
+   FF_TX_D_2_7 => FF_TX_D_2_7,
+   FF_TX_D_2_8 => FF_TX_D_2_8,
+   FF_TX_D_2_9 => FF_TX_D_2_9,
+   FF_TX_D_2_10 => FF_TX_D_2_10,
+   FF_TX_D_2_11 => FF_TX_D_2_11,
+   FF_TX_D_2_12 => FF_TX_D_2_12,
+   FF_TX_D_2_13 => FF_TX_D_2_13,
+   FF_TX_D_2_14 => FF_TX_D_2_14,
+   FF_TX_D_2_15 => FF_TX_D_2_15,
+   FF_TX_D_2_16 => FF_TX_D_2_16,
+   FF_TX_D_2_17 => FF_TX_D_2_17,
+   FF_TX_D_2_18 => FF_TX_D_2_18,
+   FF_TX_D_2_19 => FF_TX_D_2_19,
+   FF_TX_D_2_20 => FF_TX_D_2_20,
+   FF_TX_D_2_21 => FF_TX_D_2_21,
+   FF_TX_D_2_22 => FF_TX_D_2_22,
+   FF_TX_D_2_23 => FF_TX_D_2_23,
+   FF_TX_D_3_0 => FF_TX_D_3_0,
+   FF_TX_D_3_1 => FF_TX_D_3_1,
+   FF_TX_D_3_2 => FF_TX_D_3_2,
+   FF_TX_D_3_3 => FF_TX_D_3_3,
+   FF_TX_D_3_4 => FF_TX_D_3_4,
+   FF_TX_D_3_5 => FF_TX_D_3_5,
+   FF_TX_D_3_6 => FF_TX_D_3_6,
+   FF_TX_D_3_7 => FF_TX_D_3_7,
+   FF_TX_D_3_8 => FF_TX_D_3_8,
+   FF_TX_D_3_9 => FF_TX_D_3_9,
+   FF_TX_D_3_10 => FF_TX_D_3_10,
+   FF_TX_D_3_11 => FF_TX_D_3_11,
+   FF_TX_D_3_12 => FF_TX_D_3_12,
+   FF_TX_D_3_13 => FF_TX_D_3_13,
+   FF_TX_D_3_14 => FF_TX_D_3_14,
+   FF_TX_D_3_15 => FF_TX_D_3_15,
+   FF_TX_D_3_16 => FF_TX_D_3_16,
+   FF_TX_D_3_17 => FF_TX_D_3_17,
+   FF_TX_D_3_18 => FF_TX_D_3_18,
+   FF_TX_D_3_19 => FF_TX_D_3_19,
+   FF_TX_D_3_20 => FF_TX_D_3_20,
+   FF_TX_D_3_21 => FF_TX_D_3_21,
+   FF_TX_D_3_22 => FF_TX_D_3_22,
+   FF_TX_D_3_23 => FF_TX_D_3_23,
+   FF_TXI_CLK_0 => FF_TXI_CLK_0,
+   FF_TXI_CLK_1 => FF_TXI_CLK_1,
+   FF_TXI_CLK_2 => FF_TXI_CLK_2,
+   FF_TXI_CLK_3 => FF_TXI_CLK_3,
+   FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
+   FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
+   FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
+   FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
+   FFC_CK_CORE_TX => FFC_CK_CORE_TX,
+   FFC_EI_EN_0 => FFC_EI_EN_0,
+   FFC_EI_EN_1 => FFC_EI_EN_1,
+   FFC_EI_EN_2 => FFC_EI_EN_2,
+   FFC_EI_EN_3 => FFC_EI_EN_3,
+   FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
+   FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
+   FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
+   FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
+   FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
+   FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
+   FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
+   FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
+   FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
+   FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
+   FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
+   FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
+   FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
+   FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
+   FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
+   FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
+   FFC_MACRO_RST => FFC_MACRO_RST,
+   FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
+   FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
+   FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
+   FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
+   FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
+   FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
+   FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
+   FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
+   FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
+   FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
+   FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
+   FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
+   FFC_QUAD_RST => FFC_QUAD_RST,
+   FFC_RRST_0 => FFC_RRST_0,
+   FFC_RRST_1 => FFC_RRST_1,
+   FFC_RRST_2 => FFC_RRST_2,
+   FFC_RRST_3 => FFC_RRST_3,
+   FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
+   FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
+   FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
+   FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
+   FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
+   FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
+   FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
+   FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
+   FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
+   FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
+   FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
+   FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
+   FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
+   FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
+   FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
+   FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
+   FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
+   FFC_TRST => FFC_TRST,
+   FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
+   FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
+   FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
+   FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
+   FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
+   FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
+   FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
+   FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
+   FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
+   FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
+   FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
+   FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
+   FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
+   FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
+   FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
+   FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
+   FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
+   FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
+   FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
+   FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
+   LDR_CORE2TX_0 => LDR_CORE2TX_0,
+   LDR_CORE2TX_1 => LDR_CORE2TX_1,
+   LDR_CORE2TX_2 => LDR_CORE2TX_2,
+   LDR_CORE2TX_3 => LDR_CORE2TX_3,
+   FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
+   FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
+   FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
+   FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
+   PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
+   PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
+   PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
+   PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
+   PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
+   PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
+   PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
+   PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
+   PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
+   PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
+   PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
+   PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
+   PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
+   PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
+   PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
+   PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
+   PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
+   PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
+   PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
+   PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
+   SCIADDR0 => SCIADDR0,
+   SCIADDR1 => SCIADDR1,
+   SCIADDR2 => SCIADDR2,
+   SCIADDR3 => SCIADDR3,
+   SCIADDR4 => SCIADDR4,
+   SCIADDR5 => SCIADDR5,
+   SCIENAUX => SCIENAUX,
+   SCIENCH0 => SCIENCH0,
+   SCIENCH1 => SCIENCH1,
+   SCIENCH2 => SCIENCH2,
+   SCIENCH3 => SCIENCH3,
+   SCIRD => SCIRD,
+   SCISELAUX => SCISELAUX,
+   SCISELCH0 => SCISELCH0,
+   SCISELCH1 => SCISELCH1,
+   SCISELCH2 => SCISELCH2,
+   SCISELCH3 => SCISELCH3,
+   SCIWDATA0 => SCIWDATA0,
+   SCIWDATA1 => SCIWDATA1,
+   SCIWDATA2 => SCIWDATA2,
+   SCIWDATA3 => SCIWDATA3,
+   SCIWDATA4 => SCIWDATA4,
+   SCIWDATA5 => SCIWDATA5,
+   SCIWDATA6 => SCIWDATA6,
+   SCIWDATA7 => SCIWDATA7,
+   SCIWSTN => SCIWSTN,
+   HDOUTN0 => HDOUTN0,
+   HDOUTN1 => HDOUTN1,
+   HDOUTN2 => HDOUTN2,
+   HDOUTN3 => HDOUTN3,
+   HDOUTP0 => HDOUTP0,
+   HDOUTP1 => HDOUTP1,
+   HDOUTP2 => HDOUTP2,
+   HDOUTP3 => HDOUTP3,
+   COUT19 => COUT19,
+   COUT18 => COUT18,
+   COUT17 => COUT17,
+   COUT16 => COUT16,
+   COUT15 => COUT15,
+   COUT14 => COUT14,
+   COUT13 => COUT13,
+   COUT12 => COUT12,
+   COUT11 => COUT11,
+   COUT10 => COUT10,
+   COUT9 => COUT9,
+   COUT8 => COUT8,
+   COUT7 => COUT7,
+   COUT6 => COUT6,
+   COUT5 => COUT5,
+   COUT4 => COUT4,
+   COUT3 => COUT3,
+   COUT2 => COUT2,
+   COUT1 => COUT1,
+   COUT0 => COUT0,
+   FF_RX_D_0_0 => FF_RX_D_0_0,
+   FF_RX_D_0_1 => FF_RX_D_0_1,
+   FF_RX_D_0_2 => FF_RX_D_0_2,
+   FF_RX_D_0_3 => FF_RX_D_0_3,
+   FF_RX_D_0_4 => FF_RX_D_0_4,
+   FF_RX_D_0_5 => FF_RX_D_0_5,
+   FF_RX_D_0_6 => FF_RX_D_0_6,
+   FF_RX_D_0_7 => FF_RX_D_0_7,
+   FF_RX_D_0_8 => FF_RX_D_0_8,
+   FF_RX_D_0_9 => FF_RX_D_0_9,
+   FF_RX_D_0_10 => FF_RX_D_0_10,
+   FF_RX_D_0_11 => FF_RX_D_0_11,
+   FF_RX_D_0_12 => FF_RX_D_0_12,
+   FF_RX_D_0_13 => FF_RX_D_0_13,
+   FF_RX_D_0_14 => FF_RX_D_0_14,
+   FF_RX_D_0_15 => FF_RX_D_0_15,
+   FF_RX_D_0_16 => FF_RX_D_0_16,
+   FF_RX_D_0_17 => FF_RX_D_0_17,
+   FF_RX_D_0_18 => FF_RX_D_0_18,
+   FF_RX_D_0_19 => FF_RX_D_0_19,
+   FF_RX_D_0_20 => FF_RX_D_0_20,
+   FF_RX_D_0_21 => FF_RX_D_0_21,
+   FF_RX_D_0_22 => FF_RX_D_0_22,
+   FF_RX_D_0_23 => FF_RX_D_0_23,
+   FF_RX_D_1_0 => FF_RX_D_1_0,
+   FF_RX_D_1_1 => FF_RX_D_1_1,
+   FF_RX_D_1_2 => FF_RX_D_1_2,
+   FF_RX_D_1_3 => FF_RX_D_1_3,
+   FF_RX_D_1_4 => FF_RX_D_1_4,
+   FF_RX_D_1_5 => FF_RX_D_1_5,
+   FF_RX_D_1_6 => FF_RX_D_1_6,
+   FF_RX_D_1_7 => FF_RX_D_1_7,
+   FF_RX_D_1_8 => FF_RX_D_1_8,
+   FF_RX_D_1_9 => FF_RX_D_1_9,
+   FF_RX_D_1_10 => FF_RX_D_1_10,
+   FF_RX_D_1_11 => FF_RX_D_1_11,
+   FF_RX_D_1_12 => FF_RX_D_1_12,
+   FF_RX_D_1_13 => FF_RX_D_1_13,
+   FF_RX_D_1_14 => FF_RX_D_1_14,
+   FF_RX_D_1_15 => FF_RX_D_1_15,
+   FF_RX_D_1_16 => FF_RX_D_1_16,
+   FF_RX_D_1_17 => FF_RX_D_1_17,
+   FF_RX_D_1_18 => FF_RX_D_1_18,
+   FF_RX_D_1_19 => FF_RX_D_1_19,
+   FF_RX_D_1_20 => FF_RX_D_1_20,
+   FF_RX_D_1_21 => FF_RX_D_1_21,
+   FF_RX_D_1_22 => FF_RX_D_1_22,
+   FF_RX_D_1_23 => FF_RX_D_1_23,
+   FF_RX_D_2_0 => FF_RX_D_2_0,
+   FF_RX_D_2_1 => FF_RX_D_2_1,
+   FF_RX_D_2_2 => FF_RX_D_2_2,
+   FF_RX_D_2_3 => FF_RX_D_2_3,
+   FF_RX_D_2_4 => FF_RX_D_2_4,
+   FF_RX_D_2_5 => FF_RX_D_2_5,
+   FF_RX_D_2_6 => FF_RX_D_2_6,
+   FF_RX_D_2_7 => FF_RX_D_2_7,
+   FF_RX_D_2_8 => FF_RX_D_2_8,
+   FF_RX_D_2_9 => FF_RX_D_2_9,
+   FF_RX_D_2_10 => FF_RX_D_2_10,
+   FF_RX_D_2_11 => FF_RX_D_2_11,
+   FF_RX_D_2_12 => FF_RX_D_2_12,
+   FF_RX_D_2_13 => FF_RX_D_2_13,
+   FF_RX_D_2_14 => FF_RX_D_2_14,
+   FF_RX_D_2_15 => FF_RX_D_2_15,
+   FF_RX_D_2_16 => FF_RX_D_2_16,
+   FF_RX_D_2_17 => FF_RX_D_2_17,
+   FF_RX_D_2_18 => FF_RX_D_2_18,
+   FF_RX_D_2_19 => FF_RX_D_2_19,
+   FF_RX_D_2_20 => FF_RX_D_2_20,
+   FF_RX_D_2_21 => FF_RX_D_2_21,
+   FF_RX_D_2_22 => FF_RX_D_2_22,
+   FF_RX_D_2_23 => FF_RX_D_2_23,
+   FF_RX_D_3_0 => FF_RX_D_3_0,
+   FF_RX_D_3_1 => FF_RX_D_3_1,
+   FF_RX_D_3_2 => FF_RX_D_3_2,
+   FF_RX_D_3_3 => FF_RX_D_3_3,
+   FF_RX_D_3_4 => FF_RX_D_3_4,
+   FF_RX_D_3_5 => FF_RX_D_3_5,
+   FF_RX_D_3_6 => FF_RX_D_3_6,
+   FF_RX_D_3_7 => FF_RX_D_3_7,
+   FF_RX_D_3_8 => FF_RX_D_3_8,
+   FF_RX_D_3_9 => FF_RX_D_3_9,
+   FF_RX_D_3_10 => FF_RX_D_3_10,
+   FF_RX_D_3_11 => FF_RX_D_3_11,
+   FF_RX_D_3_12 => FF_RX_D_3_12,
+   FF_RX_D_3_13 => FF_RX_D_3_13,
+   FF_RX_D_3_14 => FF_RX_D_3_14,
+   FF_RX_D_3_15 => FF_RX_D_3_15,
+   FF_RX_D_3_16 => FF_RX_D_3_16,
+   FF_RX_D_3_17 => FF_RX_D_3_17,
+   FF_RX_D_3_18 => FF_RX_D_3_18,
+   FF_RX_D_3_19 => FF_RX_D_3_19,
+   FF_RX_D_3_20 => FF_RX_D_3_20,
+   FF_RX_D_3_21 => FF_RX_D_3_21,
+   FF_RX_D_3_22 => FF_RX_D_3_22,
+   FF_RX_D_3_23 => FF_RX_D_3_23,
+   FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
+   FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
+   FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
+   FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
+   FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
+   FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
+   FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
+   FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
+   FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
+   FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
+   FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
+   FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
+   FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
+   FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
+   FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
+   FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
+   FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
+   FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
+   FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
+   FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
+   FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
+   FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
+   FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
+   FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
+   FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
+   FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
+   FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
+   FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
+   FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
+   FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
+   FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
+   FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
+   FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
+   FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
+   FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
+   FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
+   FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
+   FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
+   FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
+   FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
+   FFS_PLOL => FFS_PLOL,
+   FFS_RLOL_0 => FFS_RLOL_0,
+   FFS_RLOL_1 => FFS_RLOL_1,
+   FFS_RLOL_2 => FFS_RLOL_2,
+   FFS_RLOL_3 => FFS_RLOL_3,
+   FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
+   FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
+   FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
+   FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
+   FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
+   FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
+   FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
+   FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
+   FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
+   FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
+   FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
+   FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
+   FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
+   FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
+   FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
+   FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
+   PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
+   PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
+   PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
+   PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
+   PCIE_RXVALID_0 => PCIE_RXVALID_0,
+   PCIE_RXVALID_1 => PCIE_RXVALID_1,
+   PCIE_RXVALID_2 => PCIE_RXVALID_2,
+   PCIE_RXVALID_3 => PCIE_RXVALID_3,
+   FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
+   FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
+   FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
+   FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
+   FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
+   FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
+   FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
+   FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
+   LDR_RX2CORE_0 => LDR_RX2CORE_0,
+   LDR_RX2CORE_1 => LDR_RX2CORE_1,
+   LDR_RX2CORE_2 => LDR_RX2CORE_2,
+   LDR_RX2CORE_3 => LDR_RX2CORE_3,
+   REFCK2CORE => REFCK2CORE,
+   SCIINT => SCIINT,
+   SCIRDATA0 => SCIRDATA0,
+   SCIRDATA1 => SCIRDATA1,
+   SCIRDATA2 => SCIRDATA2,
+   SCIRDATA3 => SCIRDATA3,
+   SCIRDATA4 => SCIRDATA4,
+   SCIRDATA5 => SCIRDATA5,
+   SCIRDATA6 => SCIRDATA6,
+   SCIRDATA7 => SCIRDATA7,
+   REFCLK_FROM_NQ => REFCLK_FROM_NQ,
+   REFCLK_TO_NQ => REFCLK_TO_NQ
+   );
+
+end PCSD_arch;
+
+--synopsys translate_on
+
+
+
+
+--synopsys translate_off
+library ECP3;
+use ECP3.components.all;
+--synopsys translate_on
+
+
+library IEEE, STD;
+use IEEE.std_logic_1164.all;
+use STD.TEXTIO.all;
+
+entity serdes_sync_125_full is
+   GENERIC (USER_CONFIG_FILE    :  String := "serdes_sync_125_full.txt");
+ port (
+------------------
+-- CH0 --
+    hdinp_ch0, hdinn_ch0    :   in std_logic;
+    hdoutp_ch0, hdoutn_ch0   :   out std_logic;
+    sci_sel_ch0    :   in std_logic;
+    rxiclk_ch0    :   in std_logic;
+    txiclk_ch0    :   in std_logic;
+    rx_full_clk_ch0   :   out std_logic;
+    rx_half_clk_ch0   :   out std_logic;
+    tx_full_clk_ch0   :   out std_logic;
+    tx_half_clk_ch0   :   out std_logic;
+    fpga_rxrefclk_ch0    :   in std_logic;
+    txdata_ch0    :   in std_logic_vector (7 downto 0);
+    tx_k_ch0    :   in std_logic;
+    tx_force_disp_ch0    :   in std_logic;
+    tx_disp_sel_ch0    :   in std_logic;
+    rxdata_ch0   :   out std_logic_vector (7 downto 0);
+    rx_k_ch0   :   out std_logic;
+    rx_disp_err_ch0   :   out std_logic;
+    rx_cv_err_ch0   :   out std_logic;
+    rx_serdes_rst_ch0_c    :   in std_logic;
+    sb_felb_ch0_c    :   in std_logic;
+    sb_felb_rst_ch0_c    :   in std_logic;
+    tx_pcs_rst_ch0_c    :   in std_logic;
+    tx_pwrup_ch0_c    :   in std_logic;
+    rx_pcs_rst_ch0_c    :   in std_logic;
+    rx_pwrup_ch0_c    :   in std_logic;
+    rx_los_low_ch0_s   :   out std_logic;
+    lsm_status_ch0_s   :   out std_logic;
+    rx_cdr_lol_ch0_s   :   out std_logic;
+    tx_div2_mode_ch0_c   : in std_logic;
+    rx_div2_mode_ch0_c   : in std_logic;
+-- CH1 --
+    hdinp_ch1, hdinn_ch1    :   in std_logic;
+    hdoutp_ch1, hdoutn_ch1   :   out std_logic;
+    sci_sel_ch1    :   in std_logic;
+    rxiclk_ch1    :   in std_logic;
+    txiclk_ch1    :   in std_logic;
+    rx_full_clk_ch1   :   out std_logic;
+    rx_half_clk_ch1   :   out std_logic;
+    tx_full_clk_ch1   :   out std_logic;
+    tx_half_clk_ch1   :   out std_logic;
+    fpga_rxrefclk_ch1    :   in std_logic;
+    txdata_ch1    :   in std_logic_vector (7 downto 0);
+    tx_k_ch1    :   in std_logic;
+    tx_force_disp_ch1    :   in std_logic;
+    tx_disp_sel_ch1    :   in std_logic;
+    rxdata_ch1   :   out std_logic_vector (7 downto 0);
+    rx_k_ch1   :   out std_logic;
+    rx_disp_err_ch1   :   out std_logic;
+    rx_cv_err_ch1   :   out std_logic;
+    rx_serdes_rst_ch1_c    :   in std_logic;
+    sb_felb_ch1_c    :   in std_logic;
+    sb_felb_rst_ch1_c    :   in std_logic;
+    tx_pcs_rst_ch1_c    :   in std_logic;
+    tx_pwrup_ch1_c    :   in std_logic;
+    rx_pcs_rst_ch1_c    :   in std_logic;
+    rx_pwrup_ch1_c    :   in std_logic;
+    rx_los_low_ch1_s   :   out std_logic;
+    lsm_status_ch1_s   :   out std_logic;
+    rx_cdr_lol_ch1_s   :   out std_logic;
+    tx_div2_mode_ch1_c   : in std_logic;
+    rx_div2_mode_ch1_c   : in std_logic;
+-- CH2 --
+    hdinp_ch2, hdinn_ch2    :   in std_logic;
+    hdoutp_ch2, hdoutn_ch2   :   out std_logic;
+    sci_sel_ch2    :   in std_logic;
+    rxiclk_ch2    :   in std_logic;
+    txiclk_ch2    :   in std_logic;
+    rx_full_clk_ch2   :   out std_logic;
+    rx_half_clk_ch2   :   out std_logic;
+    tx_full_clk_ch2   :   out std_logic;
+    tx_half_clk_ch2   :   out std_logic;
+    fpga_rxrefclk_ch2    :   in std_logic;
+    txdata_ch2    :   in std_logic_vector (7 downto 0);
+    tx_k_ch2    :   in std_logic;
+    tx_force_disp_ch2    :   in std_logic;
+    tx_disp_sel_ch2    :   in std_logic;
+    rxdata_ch2   :   out std_logic_vector (7 downto 0);
+    rx_k_ch2   :   out std_logic;
+    rx_disp_err_ch2   :   out std_logic;
+    rx_cv_err_ch2   :   out std_logic;
+    rx_serdes_rst_ch2_c    :   in std_logic;
+    sb_felb_ch2_c    :   in std_logic;
+    sb_felb_rst_ch2_c    :   in std_logic;
+    tx_pcs_rst_ch2_c    :   in std_logic;
+    tx_pwrup_ch2_c    :   in std_logic;
+    rx_pcs_rst_ch2_c    :   in std_logic;
+    rx_pwrup_ch2_c    :   in std_logic;
+    rx_los_low_ch2_s   :   out std_logic;
+    lsm_status_ch2_s   :   out std_logic;
+    rx_cdr_lol_ch2_s   :   out std_logic;
+    tx_div2_mode_ch2_c   : in std_logic;
+    rx_div2_mode_ch2_c   : in std_logic;
+-- CH3 --
+    hdinp_ch3, hdinn_ch3    :   in std_logic;
+    hdoutp_ch3, hdoutn_ch3   :   out std_logic;
+    sci_sel_ch3    :   in std_logic;
+    rxiclk_ch3    :   in std_logic;
+    txiclk_ch3    :   in std_logic;
+    rx_full_clk_ch3   :   out std_logic;
+    rx_half_clk_ch3   :   out std_logic;
+    tx_full_clk_ch3   :   out std_logic;
+    tx_half_clk_ch3   :   out std_logic;
+    fpga_rxrefclk_ch3    :   in std_logic;
+    txdata_ch3    :   in std_logic_vector (7 downto 0);
+    tx_k_ch3    :   in std_logic;
+    tx_force_disp_ch3    :   in std_logic;
+    tx_disp_sel_ch3    :   in std_logic;
+    rxdata_ch3   :   out std_logic_vector (7 downto 0);
+    rx_k_ch3   :   out std_logic;
+    rx_disp_err_ch3   :   out std_logic;
+    rx_cv_err_ch3   :   out std_logic;
+    rx_serdes_rst_ch3_c    :   in std_logic;
+    sb_felb_ch3_c    :   in std_logic;
+    sb_felb_rst_ch3_c    :   in std_logic;
+    tx_pcs_rst_ch3_c    :   in std_logic;
+    tx_pwrup_ch3_c    :   in std_logic;
+    rx_pcs_rst_ch3_c    :   in std_logic;
+    rx_pwrup_ch3_c    :   in std_logic;
+    rx_los_low_ch3_s   :   out std_logic;
+    lsm_status_ch3_s   :   out std_logic;
+    rx_cdr_lol_ch3_s   :   out std_logic;
+    tx_div2_mode_ch3_c   : in std_logic;
+    rx_div2_mode_ch3_c   : in std_logic;
+---- Miscillaneous ports
+    sci_wrdata    :   in std_logic_vector (7 downto 0);
+    sci_addr    :   in std_logic_vector (5 downto 0);
+    sci_rddata   :   out std_logic_vector (7 downto 0);
+    sci_sel_quad    :   in std_logic;
+    sci_rd    :   in std_logic;
+    sci_wrn    :   in std_logic;
+    fpga_txrefclk  :   in std_logic;
+    tx_serdes_rst_c    :   in std_logic;
+    tx_pll_lol_qd_s   :   out std_logic;
+    tx_sync_qd_c    :   in std_logic;
+    rst_qd_c    :   in std_logic;
+    serdes_rst_qd_c    :   in std_logic);
+
+end serdes_sync_125_full;
+
+
+architecture serdes_sync_125_full_arch of serdes_sync_125_full is
+
+component VLO
+port (
+   Z : out std_logic);
+end component;
+
+component VHI
+port (
+   Z : out std_logic);
+end component;
+
+
+
+component PCSD
+--synopsys translate_off
+GENERIC(
+  CONFIG_FILE : String;
+  QUAD_MODE : String;
+  CH0_CDR_SRC   : String := "REFCLK_EXT";
+  CH1_CDR_SRC   : String := "REFCLK_EXT";
+  CH2_CDR_SRC   : String := "REFCLK_EXT";
+  CH3_CDR_SRC   : String := "REFCLK_EXT";
+  PLL_SRC   : String
+  );
+--synopsys translate_on
+port (
+  HDINN0             : in std_logic;
+  HDINN1             : in std_logic;
+  HDINN2             : in std_logic;
+  HDINN3             : in std_logic;
+  HDINP0             : in std_logic;
+  HDINP1             : in std_logic;
+  HDINP2             : in std_logic;
+  HDINP3             : in std_logic;
+  REFCLKN             : in std_logic;
+  REFCLKP             : in std_logic;
+  CIN0             : in std_logic;
+  CIN1             : in std_logic;
+  CIN2             : in std_logic;
+  CIN3             : in std_logic;
+  CIN4             : in std_logic;
+  CIN5             : in std_logic;
+  CIN6             : in std_logic;
+  CIN7             : in std_logic;
+  CIN8             : in std_logic;
+  CIN9             : in std_logic;
+  CIN10             : in std_logic;
+  CIN11             : in std_logic;
+  CYAWSTN             : in std_logic;
+  FF_EBRD_CLK_0             : in std_logic;
+  FF_EBRD_CLK_1             : in std_logic;
+  FF_EBRD_CLK_2             : in std_logic;
+  FF_EBRD_CLK_3             : in std_logic;
+  FF_RXI_CLK_0             : in std_logic;
+  FF_RXI_CLK_1             : in std_logic;
+  FF_RXI_CLK_2             : in std_logic;
+  FF_RXI_CLK_3             : in std_logic;
+  FF_TX_D_0_0             : in std_logic;
+  FF_TX_D_0_1             : in std_logic;
+  FF_TX_D_0_2             : in std_logic;
+  FF_TX_D_0_3             : in std_logic;
+  FF_TX_D_0_4             : in std_logic;
+  FF_TX_D_0_5             : in std_logic;
+  FF_TX_D_0_6             : in std_logic;
+  FF_TX_D_0_7             : in std_logic;
+  FF_TX_D_0_8             : in std_logic;
+  FF_TX_D_0_9             : in std_logic;
+  FF_TX_D_0_10             : in std_logic;
+  FF_TX_D_0_11             : in std_logic;
+  FF_TX_D_0_12             : in std_logic;
+  FF_TX_D_0_13             : in std_logic;
+  FF_TX_D_0_14             : in std_logic;
+  FF_TX_D_0_15             : in std_logic;
+  FF_TX_D_0_16             : in std_logic;
+  FF_TX_D_0_17             : in std_logic;
+  FF_TX_D_0_18             : in std_logic;
+  FF_TX_D_0_19             : in std_logic;
+  FF_TX_D_0_20             : in std_logic;
+  FF_TX_D_0_21             : in std_logic;
+  FF_TX_D_0_22             : in std_logic;
+  FF_TX_D_0_23             : in std_logic;
+  FF_TX_D_1_0             : in std_logic;
+  FF_TX_D_1_1             : in std_logic;
+  FF_TX_D_1_2             : in std_logic;
+  FF_TX_D_1_3             : in std_logic;
+  FF_TX_D_1_4             : in std_logic;
+  FF_TX_D_1_5             : in std_logic;
+  FF_TX_D_1_6             : in std_logic;
+  FF_TX_D_1_7             : in std_logic;
+  FF_TX_D_1_8             : in std_logic;
+  FF_TX_D_1_9             : in std_logic;
+  FF_TX_D_1_10             : in std_logic;
+  FF_TX_D_1_11             : in std_logic;
+  FF_TX_D_1_12             : in std_logic;
+  FF_TX_D_1_13             : in std_logic;
+  FF_TX_D_1_14             : in std_logic;
+  FF_TX_D_1_15             : in std_logic;
+  FF_TX_D_1_16             : in std_logic;
+  FF_TX_D_1_17             : in std_logic;
+  FF_TX_D_1_18             : in std_logic;
+  FF_TX_D_1_19             : in std_logic;
+  FF_TX_D_1_20             : in std_logic;
+  FF_TX_D_1_21             : in std_logic;
+  FF_TX_D_1_22             : in std_logic;
+  FF_TX_D_1_23             : in std_logic;
+  FF_TX_D_2_0             : in std_logic;
+  FF_TX_D_2_1             : in std_logic;
+  FF_TX_D_2_2             : in std_logic;
+  FF_TX_D_2_3             : in std_logic;
+  FF_TX_D_2_4             : in std_logic;
+  FF_TX_D_2_5             : in std_logic;
+  FF_TX_D_2_6             : in std_logic;
+  FF_TX_D_2_7             : in std_logic;
+  FF_TX_D_2_8             : in std_logic;
+  FF_TX_D_2_9             : in std_logic;
+  FF_TX_D_2_10             : in std_logic;
+  FF_TX_D_2_11             : in std_logic;
+  FF_TX_D_2_12             : in std_logic;
+  FF_TX_D_2_13             : in std_logic;
+  FF_TX_D_2_14             : in std_logic;
+  FF_TX_D_2_15             : in std_logic;
+  FF_TX_D_2_16             : in std_logic;
+  FF_TX_D_2_17             : in std_logic;
+  FF_TX_D_2_18             : in std_logic;
+  FF_TX_D_2_19             : in std_logic;
+  FF_TX_D_2_20             : in std_logic;
+  FF_TX_D_2_21             : in std_logic;
+  FF_TX_D_2_22             : in std_logic;
+  FF_TX_D_2_23             : in std_logic;
+  FF_TX_D_3_0             : in std_logic;
+  FF_TX_D_3_1             : in std_logic;
+  FF_TX_D_3_2             : in std_logic;
+  FF_TX_D_3_3             : in std_logic;
+  FF_TX_D_3_4             : in std_logic;
+  FF_TX_D_3_5             : in std_logic;
+  FF_TX_D_3_6             : in std_logic;
+  FF_TX_D_3_7             : in std_logic;
+  FF_TX_D_3_8             : in std_logic;
+  FF_TX_D_3_9             : in std_logic;
+  FF_TX_D_3_10             : in std_logic;
+  FF_TX_D_3_11             : in std_logic;
+  FF_TX_D_3_12             : in std_logic;
+  FF_TX_D_3_13             : in std_logic;
+  FF_TX_D_3_14             : in std_logic;
+  FF_TX_D_3_15             : in std_logic;
+  FF_TX_D_3_16             : in std_logic;
+  FF_TX_D_3_17             : in std_logic;
+  FF_TX_D_3_18             : in std_logic;
+  FF_TX_D_3_19             : in std_logic;
+  FF_TX_D_3_20             : in std_logic;
+  FF_TX_D_3_21             : in std_logic;
+  FF_TX_D_3_22             : in std_logic;
+  FF_TX_D_3_23             : in std_logic;
+  FF_TXI_CLK_0             : in std_logic;
+  FF_TXI_CLK_1             : in std_logic;
+  FF_TXI_CLK_2             : in std_logic;
+  FF_TXI_CLK_3             : in std_logic;
+  FFC_CK_CORE_RX_0         : in std_logic;
+  FFC_CK_CORE_RX_1         : in std_logic;
+  FFC_CK_CORE_RX_2         : in std_logic;
+  FFC_CK_CORE_RX_3         : in std_logic;
+  FFC_CK_CORE_TX           : in std_logic;
+  FFC_EI_EN_0             : in std_logic;
+  FFC_EI_EN_1             : in std_logic;
+  FFC_EI_EN_2             : in std_logic;
+  FFC_EI_EN_3             : in std_logic;
+  FFC_ENABLE_CGALIGN_0             : in std_logic;
+  FFC_ENABLE_CGALIGN_1             : in std_logic;
+  FFC_ENABLE_CGALIGN_2             : in std_logic;
+  FFC_ENABLE_CGALIGN_3             : in std_logic;
+  FFC_FB_LOOPBACK_0             : in std_logic;
+  FFC_FB_LOOPBACK_1             : in std_logic;
+  FFC_FB_LOOPBACK_2             : in std_logic;
+  FFC_FB_LOOPBACK_3             : in std_logic;
+  FFC_LANE_RX_RST_0             : in std_logic;
+  FFC_LANE_RX_RST_1             : in std_logic;
+  FFC_LANE_RX_RST_2             : in std_logic;
+  FFC_LANE_RX_RST_3             : in std_logic;
+  FFC_LANE_TX_RST_0             : in std_logic;
+  FFC_LANE_TX_RST_1             : in std_logic;
+  FFC_LANE_TX_RST_2             : in std_logic;
+  FFC_LANE_TX_RST_3             : in std_logic;
+  FFC_MACRO_RST             : in std_logic;
+  FFC_PCI_DET_EN_0             : in std_logic;
+  FFC_PCI_DET_EN_1             : in std_logic;
+  FFC_PCI_DET_EN_2             : in std_logic;
+  FFC_PCI_DET_EN_3             : in std_logic;
+  FFC_PCIE_CT_0             : in std_logic;
+  FFC_PCIE_CT_1             : in std_logic;
+  FFC_PCIE_CT_2             : in std_logic;
+  FFC_PCIE_CT_3             : in std_logic;
+  FFC_PFIFO_CLR_0             : in std_logic;
+  FFC_PFIFO_CLR_1             : in std_logic;
+  FFC_PFIFO_CLR_2             : in std_logic;
+  FFC_PFIFO_CLR_3             : in std_logic;
+  FFC_QUAD_RST             : in std_logic;
+  FFC_RRST_0             : in std_logic;
+  FFC_RRST_1             : in std_logic;
+  FFC_RRST_2             : in std_logic;
+  FFC_RRST_3             : in std_logic;
+  FFC_RXPWDNB_0             : in std_logic;
+  FFC_RXPWDNB_1             : in std_logic;
+  FFC_RXPWDNB_2             : in std_logic;
+  FFC_RXPWDNB_3             : in std_logic;
+  FFC_SB_INV_RX_0             : in std_logic;
+  FFC_SB_INV_RX_1             : in std_logic;
+  FFC_SB_INV_RX_2             : in std_logic;
+  FFC_SB_INV_RX_3             : in std_logic;
+  FFC_SB_PFIFO_LP_0             : in std_logic;
+  FFC_SB_PFIFO_LP_1             : in std_logic;
+  FFC_SB_PFIFO_LP_2             : in std_logic;
+  FFC_SB_PFIFO_LP_3             : in std_logic;
+  FFC_SIGNAL_DETECT_0             : in std_logic;
+  FFC_SIGNAL_DETECT_1             : in std_logic;
+  FFC_SIGNAL_DETECT_2             : in std_logic;
+  FFC_SIGNAL_DETECT_3             : in std_logic;
+  FFC_SYNC_TOGGLE             : in std_logic;
+  FFC_TRST             : in std_logic;
+  FFC_TXPWDNB_0             : in std_logic;
+  FFC_TXPWDNB_1             : in std_logic;
+  FFC_TXPWDNB_2             : in std_logic;
+  FFC_TXPWDNB_3             : in std_logic;
+  FFC_RATE_MODE_RX_0        : in std_logic;
+  FFC_RATE_MODE_RX_1        : in std_logic;
+  FFC_RATE_MODE_RX_2        : in std_logic;
+  FFC_RATE_MODE_RX_3        : in std_logic;
+  FFC_RATE_MODE_TX_0        : in std_logic;
+  FFC_RATE_MODE_TX_1        : in std_logic;
+  FFC_RATE_MODE_TX_2        : in std_logic;
+  FFC_RATE_MODE_TX_3        : in std_logic;
+  FFC_DIV11_MODE_RX_0       : in std_logic;
+  FFC_DIV11_MODE_RX_1       : in std_logic;
+  FFC_DIV11_MODE_RX_2       : in std_logic;
+  FFC_DIV11_MODE_RX_3       : in std_logic;
+  FFC_DIV11_MODE_TX_0       : in std_logic;
+  FFC_DIV11_MODE_TX_1       : in std_logic;
+  FFC_DIV11_MODE_TX_2       : in std_logic;
+  FFC_DIV11_MODE_TX_3       : in std_logic;
+  LDR_CORE2TX_0             : in std_logic;
+  LDR_CORE2TX_1             : in std_logic;
+  LDR_CORE2TX_2             : in std_logic;
+  LDR_CORE2TX_3             : in std_logic;
+  FFC_LDR_CORE2TX_EN_0      : in std_logic;
+  FFC_LDR_CORE2TX_EN_1      : in std_logic;
+  FFC_LDR_CORE2TX_EN_2      : in std_logic;
+  FFC_LDR_CORE2TX_EN_3      : in std_logic;
+  PCIE_POWERDOWN_0_0      : in std_logic;
+  PCIE_POWERDOWN_0_1      : in std_logic;
+  PCIE_POWERDOWN_1_0      : in std_logic;
+  PCIE_POWERDOWN_1_1      : in std_logic;
+  PCIE_POWERDOWN_2_0      : in std_logic;
+  PCIE_POWERDOWN_2_1      : in std_logic;
+  PCIE_POWERDOWN_3_0      : in std_logic;
+  PCIE_POWERDOWN_3_1      : in std_logic;
+  PCIE_RXPOLARITY_0         : in std_logic;
+  PCIE_RXPOLARITY_1         : in std_logic;
+  PCIE_RXPOLARITY_2         : in std_logic;
+  PCIE_RXPOLARITY_3         : in std_logic;
+  PCIE_TXCOMPLIANCE_0       : in std_logic;
+  PCIE_TXCOMPLIANCE_1       : in std_logic;
+  PCIE_TXCOMPLIANCE_2       : in std_logic;
+  PCIE_TXCOMPLIANCE_3       : in std_logic;
+  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
+  SCIADDR0             : in std_logic;
+  SCIADDR1             : in std_logic;
+  SCIADDR2             : in std_logic;
+  SCIADDR3             : in std_logic;
+  SCIADDR4             : in std_logic;
+  SCIADDR5             : in std_logic;
+  SCIENAUX             : in std_logic;
+  SCIENCH0             : in std_logic;
+  SCIENCH1             : in std_logic;
+  SCIENCH2             : in std_logic;
+  SCIENCH3             : in std_logic;
+  SCIRD                : in std_logic;
+  SCISELAUX             : in std_logic;
+  SCISELCH0             : in std_logic;
+  SCISELCH1             : in std_logic;
+  SCISELCH2             : in std_logic;
+  SCISELCH3             : in std_logic;
+  SCIWDATA0             : in std_logic;
+  SCIWDATA1             : in std_logic;
+  SCIWDATA2             : in std_logic;
+  SCIWDATA3             : in std_logic;
+  SCIWDATA4             : in std_logic;
+  SCIWDATA5             : in std_logic;
+  SCIWDATA6             : in std_logic;
+  SCIWDATA7             : in std_logic;
+  SCIWSTN               : in std_logic;
+  REFCLK_FROM_NQ        : in std_logic;
+  HDOUTN0             : out std_logic;
+  HDOUTN1             : out std_logic;
+  HDOUTN2             : out std_logic;
+  HDOUTN3             : out std_logic;
+  HDOUTP0             : out std_logic;
+  HDOUTP1             : out std_logic;
+  HDOUTP2             : out std_logic;
+  HDOUTP3             : out std_logic;
+  COUT0             : out std_logic;
+  COUT1             : out std_logic;
+  COUT2             : out std_logic;
+  COUT3             : out std_logic;
+  COUT4             : out std_logic;
+  COUT5             : out std_logic;
+  COUT6             : out std_logic;
+  COUT7             : out std_logic;
+  COUT8             : out std_logic;
+  COUT9             : out std_logic;
+  COUT10             : out std_logic;
+  COUT11             : out std_logic;
+  COUT12             : out std_logic;
+  COUT13             : out std_logic;
+  COUT14             : out std_logic;
+  COUT15             : out std_logic;
+  COUT16             : out std_logic;
+  COUT17             : out std_logic;
+  COUT18             : out std_logic;
+  COUT19             : out std_logic;
+  FF_RX_D_0_0             : out std_logic;
+  FF_RX_D_0_1             : out std_logic;
+  FF_RX_D_0_2             : out std_logic;
+  FF_RX_D_0_3             : out std_logic;
+  FF_RX_D_0_4             : out std_logic;
+  FF_RX_D_0_5             : out std_logic;
+  FF_RX_D_0_6             : out std_logic;
+  FF_RX_D_0_7             : out std_logic;
+  FF_RX_D_0_8             : out std_logic;
+  FF_RX_D_0_9             : out std_logic;
+  FF_RX_D_0_10             : out std_logic;
+  FF_RX_D_0_11             : out std_logic;
+  FF_RX_D_0_12             : out std_logic;
+  FF_RX_D_0_13             : out std_logic;
+  FF_RX_D_0_14             : out std_logic;
+  FF_RX_D_0_15             : out std_logic;
+  FF_RX_D_0_16             : out std_logic;
+  FF_RX_D_0_17             : out std_logic;
+  FF_RX_D_0_18             : out std_logic;
+  FF_RX_D_0_19             : out std_logic;
+  FF_RX_D_0_20             : out std_logic;
+  FF_RX_D_0_21             : out std_logic;
+  FF_RX_D_0_22             : out std_logic;
+  FF_RX_D_0_23             : out std_logic;
+  FF_RX_D_1_0             : out std_logic;
+  FF_RX_D_1_1             : out std_logic;
+  FF_RX_D_1_2             : out std_logic;
+  FF_RX_D_1_3             : out std_logic;
+  FF_RX_D_1_4             : out std_logic;
+  FF_RX_D_1_5             : out std_logic;
+  FF_RX_D_1_6             : out std_logic;
+  FF_RX_D_1_7             : out std_logic;
+  FF_RX_D_1_8             : out std_logic;
+  FF_RX_D_1_9             : out std_logic;
+  FF_RX_D_1_10             : out std_logic;
+  FF_RX_D_1_11             : out std_logic;
+  FF_RX_D_1_12             : out std_logic;
+  FF_RX_D_1_13             : out std_logic;
+  FF_RX_D_1_14             : out std_logic;
+  FF_RX_D_1_15             : out std_logic;
+  FF_RX_D_1_16             : out std_logic;
+  FF_RX_D_1_17             : out std_logic;
+  FF_RX_D_1_18             : out std_logic;
+  FF_RX_D_1_19             : out std_logic;
+  FF_RX_D_1_20             : out std_logic;
+  FF_RX_D_1_21             : out std_logic;
+  FF_RX_D_1_22             : out std_logic;
+  FF_RX_D_1_23             : out std_logic;
+  FF_RX_D_2_0             : out std_logic;
+  FF_RX_D_2_1             : out std_logic;
+  FF_RX_D_2_2             : out std_logic;
+  FF_RX_D_2_3             : out std_logic;
+  FF_RX_D_2_4             : out std_logic;
+  FF_RX_D_2_5             : out std_logic;
+  FF_RX_D_2_6             : out std_logic;
+  FF_RX_D_2_7             : out std_logic;
+  FF_RX_D_2_8             : out std_logic;
+  FF_RX_D_2_9             : out std_logic;
+  FF_RX_D_2_10             : out std_logic;
+  FF_RX_D_2_11             : out std_logic;
+  FF_RX_D_2_12             : out std_logic;
+  FF_RX_D_2_13             : out std_logic;
+  FF_RX_D_2_14             : out std_logic;
+  FF_RX_D_2_15             : out std_logic;
+  FF_RX_D_2_16             : out std_logic;
+  FF_RX_D_2_17             : out std_logic;
+  FF_RX_D_2_18             : out std_logic;
+  FF_RX_D_2_19             : out std_logic;
+  FF_RX_D_2_20             : out std_logic;
+  FF_RX_D_2_21             : out std_logic;
+  FF_RX_D_2_22             : out std_logic;
+  FF_RX_D_2_23             : out std_logic;
+  FF_RX_D_3_0             : out std_logic;
+  FF_RX_D_3_1             : out std_logic;
+  FF_RX_D_3_2             : out std_logic;
+  FF_RX_D_3_3             : out std_logic;
+  FF_RX_D_3_4             : out std_logic;
+  FF_RX_D_3_5             : out std_logic;
+  FF_RX_D_3_6             : out std_logic;
+  FF_RX_D_3_7             : out std_logic;
+  FF_RX_D_3_8             : out std_logic;
+  FF_RX_D_3_9             : out std_logic;
+  FF_RX_D_3_10             : out std_logic;
+  FF_RX_D_3_11             : out std_logic;
+  FF_RX_D_3_12             : out std_logic;
+  FF_RX_D_3_13             : out std_logic;
+  FF_RX_D_3_14             : out std_logic;
+  FF_RX_D_3_15             : out std_logic;
+  FF_RX_D_3_16             : out std_logic;
+  FF_RX_D_3_17             : out std_logic;
+  FF_RX_D_3_18             : out std_logic;
+  FF_RX_D_3_19             : out std_logic;
+  FF_RX_D_3_20             : out std_logic;
+  FF_RX_D_3_21             : out std_logic;
+  FF_RX_D_3_22             : out std_logic;
+  FF_RX_D_3_23             : out std_logic;
+  FF_RX_F_CLK_0             : out std_logic;
+  FF_RX_F_CLK_1             : out std_logic;
+  FF_RX_F_CLK_2             : out std_logic;
+  FF_RX_F_CLK_3             : out std_logic;
+  FF_RX_H_CLK_0             : out std_logic;
+  FF_RX_H_CLK_1             : out std_logic;
+  FF_RX_H_CLK_2             : out std_logic;
+  FF_RX_H_CLK_3             : out std_logic;
+  FF_TX_F_CLK_0             : out std_logic;
+  FF_TX_F_CLK_1             : out std_logic;
+  FF_TX_F_CLK_2             : out std_logic;
+  FF_TX_F_CLK_3             : out std_logic;
+  FF_TX_H_CLK_0             : out std_logic;
+  FF_TX_H_CLK_1             : out std_logic;
+  FF_TX_H_CLK_2             : out std_logic;
+  FF_TX_H_CLK_3             : out std_logic;
+  FFS_CC_OVERRUN_0             : out std_logic;
+  FFS_CC_OVERRUN_1             : out std_logic;
+  FFS_CC_OVERRUN_2             : out std_logic;
+  FFS_CC_OVERRUN_3             : out std_logic;
+  FFS_CC_UNDERRUN_0             : out std_logic;
+  FFS_CC_UNDERRUN_1             : out std_logic;
+  FFS_CC_UNDERRUN_2             : out std_logic;
+  FFS_CC_UNDERRUN_3             : out std_logic;
+  FFS_LS_SYNC_STATUS_0             : out std_logic;
+  FFS_LS_SYNC_STATUS_1             : out std_logic;
+  FFS_LS_SYNC_STATUS_2             : out std_logic;
+  FFS_LS_SYNC_STATUS_3             : out std_logic;
+  FFS_CDR_TRAIN_DONE_0             : out std_logic;
+  FFS_CDR_TRAIN_DONE_1             : out std_logic;
+  FFS_CDR_TRAIN_DONE_2             : out std_logic;
+  FFS_CDR_TRAIN_DONE_3             : out std_logic;
+  FFS_PCIE_CON_0             : out std_logic;
+  FFS_PCIE_CON_1             : out std_logic;
+  FFS_PCIE_CON_2             : out std_logic;
+  FFS_PCIE_CON_3             : out std_logic;
+  FFS_PCIE_DONE_0             : out std_logic;
+  FFS_PCIE_DONE_1             : out std_logic;
+  FFS_PCIE_DONE_2             : out std_logic;
+  FFS_PCIE_DONE_3             : out std_logic;
+  FFS_PLOL             : out std_logic;
+  FFS_RLOL_0             : out std_logic;
+  FFS_RLOL_1             : out std_logic;
+  FFS_RLOL_2             : out std_logic;
+  FFS_RLOL_3             : out std_logic;
+  FFS_RLOS_HI_0             : out std_logic;
+  FFS_RLOS_HI_1             : out std_logic;
+  FFS_RLOS_HI_2             : out std_logic;
+  FFS_RLOS_HI_3             : out std_logic;
+  FFS_RLOS_LO_0             : out std_logic;
+  FFS_RLOS_LO_1             : out std_logic;
+  FFS_RLOS_LO_2             : out std_logic;
+  FFS_RLOS_LO_3             : out std_logic;
+  FFS_RXFBFIFO_ERROR_0             : out std_logic;
+  FFS_RXFBFIFO_ERROR_1             : out std_logic;
+  FFS_RXFBFIFO_ERROR_2             : out std_logic;
+  FFS_RXFBFIFO_ERROR_3             : out std_logic;
+  FFS_TXFBFIFO_ERROR_0             : out std_logic;
+  FFS_TXFBFIFO_ERROR_1             : out std_logic;
+  FFS_TXFBFIFO_ERROR_2             : out std_logic;
+  FFS_TXFBFIFO_ERROR_3             : out std_logic;
+  PCIE_PHYSTATUS_0             : out std_logic;
+  PCIE_PHYSTATUS_1             : out std_logic;
+  PCIE_PHYSTATUS_2             : out std_logic;
+  PCIE_PHYSTATUS_3             : out std_logic;
+  PCIE_RXVALID_0               : out std_logic;
+  PCIE_RXVALID_1               : out std_logic;
+  PCIE_RXVALID_2               : out std_logic;
+  PCIE_RXVALID_3               : out std_logic;
+  FFS_SKP_ADDED_0                  : out std_logic;
+  FFS_SKP_ADDED_1                  : out std_logic;
+  FFS_SKP_ADDED_2                  : out std_logic;
+  FFS_SKP_ADDED_3                  : out std_logic;
+  FFS_SKP_DELETED_0                : out std_logic;
+  FFS_SKP_DELETED_1                : out std_logic;
+  FFS_SKP_DELETED_2                : out std_logic;
+  FFS_SKP_DELETED_3                : out std_logic;
+  LDR_RX2CORE_0                    : out std_logic;
+  LDR_RX2CORE_1                    : out std_logic;
+  LDR_RX2CORE_2                    : out std_logic;
+  LDR_RX2CORE_3                    : out std_logic;
+  REFCK2CORE             : out std_logic;
+  SCIINT                : out std_logic;
+  SCIRDATA0             : out std_logic;
+  SCIRDATA1             : out std_logic;
+  SCIRDATA2             : out std_logic;
+  SCIRDATA3             : out std_logic;
+  SCIRDATA4             : out std_logic;
+  SCIRDATA5             : out std_logic;
+  SCIRDATA6             : out std_logic;
+  SCIRDATA7             : out std_logic;
+  REFCLK_TO_NQ          : out std_logic
+);
+end component;
+   attribute CONFIG_FILE: string;
+   attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
+   attribute QUAD_MODE: string;
+   attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
+   attribute PLL_SRC: string;
+   attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
+   attribute CH0_CDR_SRC: string;
+   attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+   attribute CH1_CDR_SRC: string;
+   attribute CH1_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+   attribute CH2_CDR_SRC: string;
+   attribute CH2_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+   attribute CH3_CDR_SRC: string;
+   attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "125.000";
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "125.000";
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "125.000";
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "125.000";
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "62.5000";
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "62.5000";
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "62.5000";
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "62.5000";
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "125.000";
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "125.000";
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "125.000";
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "125.000";
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "62.5000";
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "62.5000";
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "62.5000";
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "62.5000";
+   attribute black_box_pad_pin: string;
+   attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
+
+signal refclk_from_nq : std_logic := '0';
+signal fpsc_vlo : std_logic := '0';
+signal fpsc_vhi : std_logic := '1';
+signal cin : std_logic_vector (11 downto 0) := "000000000000";
+signal cout : std_logic_vector (19 downto 0);
+signal    tx_full_clk_ch0_sig   :   std_logic;
+signal    tx_full_clk_ch1_sig   :   std_logic;
+signal    tx_full_clk_ch2_sig   :   std_logic;
+signal    tx_full_clk_ch3_sig   :   std_logic;
+
+signal    refclk2fpga_sig  :   std_logic;
+signal    tx_pll_lol_qd_sig  :   std_logic;
+signal    rx_los_low_ch0_sig  :   std_logic;
+signal    rx_los_low_ch1_sig  :   std_logic;
+signal    rx_los_low_ch2_sig  :   std_logic;
+signal    rx_los_low_ch3_sig  :   std_logic;
+signal    rx_cdr_lol_ch0_sig  :   std_logic;
+signal    rx_cdr_lol_ch1_sig  :   std_logic;
+signal    rx_cdr_lol_ch2_sig  :   std_logic;
+signal    rx_cdr_lol_ch3_sig  :   std_logic;
+
+
+
+
+
+begin
+
+vlo_inst : VLO port map(Z => fpsc_vlo);
+vhi_inst : VHI port map(Z => fpsc_vhi);
+
+    rx_los_low_ch0_s <= rx_los_low_ch0_sig;
+    rx_los_low_ch1_s <= rx_los_low_ch1_sig;
+    rx_los_low_ch2_s <= rx_los_low_ch2_sig;
+    rx_los_low_ch3_s <= rx_los_low_ch3_sig;
+    rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig;
+    rx_cdr_lol_ch1_s <= rx_cdr_lol_ch1_sig;
+    rx_cdr_lol_ch2_s <= rx_cdr_lol_ch2_sig;
+    rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig;
+  tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
+  tx_full_clk_ch0 <= tx_full_clk_ch0_sig;
+  tx_full_clk_ch1 <= tx_full_clk_ch1_sig;
+  tx_full_clk_ch2 <= tx_full_clk_ch2_sig;
+  tx_full_clk_ch3 <= tx_full_clk_ch3_sig;
+
+-- pcs_quad instance
+PCSD_INST : PCSD
+--synopsys translate_off
+  generic map (CONFIG_FILE => USER_CONFIG_FILE,
+               QUAD_MODE => "SINGLE",
+               CH0_CDR_SRC => "REFCLK_CORE",
+               CH1_CDR_SRC => "REFCLK_CORE",
+               CH2_CDR_SRC => "REFCLK_CORE",
+               CH3_CDR_SRC => "REFCLK_CORE",
+               PLL_SRC  => "REFCLK_CORE"
+  )
+--synopsys translate_on
+port map  (
+  REFCLKP => fpsc_vlo,
+  REFCLKN => fpsc_vlo,
+
+----- CH0 -----
+  HDOUTP0 => hdoutp_ch0,
+  HDOUTN0 => hdoutn_ch0,
+  HDINP0 => hdinp_ch0,
+  HDINN0 => hdinn_ch0,
+  PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
+  PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
+  PCIE_RXPOLARITY_0 => fpsc_vlo,
+  PCIE_POWERDOWN_0_0 => fpsc_vlo,
+  PCIE_POWERDOWN_0_1 => fpsc_vlo,
+  PCIE_RXVALID_0 => open,
+  PCIE_PHYSTATUS_0 => open,
+  SCISELCH0 => sci_sel_ch0,
+  SCIENCH0 => fpsc_vhi,
+  FF_RXI_CLK_0 => rxiclk_ch0,
+  FF_TXI_CLK_0 => txiclk_ch0,
+  FF_EBRD_CLK_0 => fpsc_vlo,
+  FF_RX_F_CLK_0 => rx_full_clk_ch0,
+  FF_RX_H_CLK_0 => rx_half_clk_ch0,
+  FF_TX_F_CLK_0 => tx_full_clk_ch0_sig,
+  FF_TX_H_CLK_0 => tx_half_clk_ch0,
+  FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0,
+  FF_TX_D_0_0 => txdata_ch0(0),
+  FF_TX_D_0_1 => txdata_ch0(1),
+  FF_TX_D_0_2 => txdata_ch0(2),
+  FF_TX_D_0_3 => txdata_ch0(3),
+  FF_TX_D_0_4 => txdata_ch0(4),
+  FF_TX_D_0_5 => txdata_ch0(5),
+  FF_TX_D_0_6 => txdata_ch0(6),
+  FF_TX_D_0_7 => txdata_ch0(7),
+  FF_TX_D_0_8 => tx_k_ch0,
+  FF_TX_D_0_9 => tx_force_disp_ch0,
+  FF_TX_D_0_10 => tx_disp_sel_ch0,
+  FF_TX_D_0_11 => fpsc_vlo,
+  FF_TX_D_0_12 => fpsc_vlo,
+  FF_TX_D_0_13 => fpsc_vlo,
+  FF_TX_D_0_14 => fpsc_vlo,
+  FF_TX_D_0_15 => fpsc_vlo,
+  FF_TX_D_0_16 => fpsc_vlo,
+  FF_TX_D_0_17 => fpsc_vlo,
+  FF_TX_D_0_18 => fpsc_vlo,
+  FF_TX_D_0_19 => fpsc_vlo,
+  FF_TX_D_0_20 => fpsc_vlo,
+  FF_TX_D_0_21 => fpsc_vlo,
+  FF_TX_D_0_22 => fpsc_vlo,
+  FF_TX_D_0_23 => fpsc_vlo,
+  FF_RX_D_0_0 => rxdata_ch0(0),
+  FF_RX_D_0_1 => rxdata_ch0(1),
+  FF_RX_D_0_2 => rxdata_ch0(2),
+  FF_RX_D_0_3 => rxdata_ch0(3),
+  FF_RX_D_0_4 => rxdata_ch0(4),
+  FF_RX_D_0_5 => rxdata_ch0(5),
+  FF_RX_D_0_6 => rxdata_ch0(6),
+  FF_RX_D_0_7 => rxdata_ch0(7),
+  FF_RX_D_0_8 => rx_k_ch0,
+  FF_RX_D_0_9 => rx_disp_err_ch0,
+  FF_RX_D_0_10 => rx_cv_err_ch0,
+  FF_RX_D_0_11 => open,
+  FF_RX_D_0_12 => open,
+  FF_RX_D_0_13 => open,
+  FF_RX_D_0_14 => open,
+  FF_RX_D_0_15 => open,
+  FF_RX_D_0_16 => open,
+  FF_RX_D_0_17 => open,
+  FF_RX_D_0_18 => open,
+  FF_RX_D_0_19 => open,
+  FF_RX_D_0_20 => open,
+  FF_RX_D_0_21 => open,
+  FF_RX_D_0_22 => open,
+  FF_RX_D_0_23 => open,
+
+  FFC_RRST_0 => rx_serdes_rst_ch0_c,
+  FFC_SIGNAL_DETECT_0 => fpsc_vlo,
+  FFC_SB_PFIFO_LP_0 => sb_felb_ch0_c,
+  FFC_PFIFO_CLR_0 => sb_felb_rst_ch0_c,
+  FFC_SB_INV_RX_0 => fpsc_vlo,
+  FFC_PCIE_CT_0 => fpsc_vlo,
+  FFC_PCI_DET_EN_0 => fpsc_vlo,
+  FFC_FB_LOOPBACK_0 => fpsc_vlo,
+  FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
+  FFC_EI_EN_0 => fpsc_vlo,
+  FFC_LANE_TX_RST_0 => tx_pcs_rst_ch0_c,
+  FFC_TXPWDNB_0 => tx_pwrup_ch0_c,
+  FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c,
+  FFC_RXPWDNB_0 => rx_pwrup_ch0_c,
+  FFS_RLOS_LO_0 => rx_los_low_ch0_sig,
+  FFS_RLOS_HI_0 => open,
+  FFS_PCIE_CON_0 => open,
+  FFS_PCIE_DONE_0 => open,
+  FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s,
+  FFS_CC_OVERRUN_0 => open,
+  FFS_CC_UNDERRUN_0 => open,
+  FFS_SKP_ADDED_0 => open,
+  FFS_SKP_DELETED_0 => open,
+  FFS_RLOL_0 => rx_cdr_lol_ch0_sig,
+  FFS_RXFBFIFO_ERROR_0 => open,
+  FFS_TXFBFIFO_ERROR_0 => open,
+  LDR_CORE2TX_0 => fpsc_vlo,
+  FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
+  LDR_RX2CORE_0 => open,
+  FFS_CDR_TRAIN_DONE_0 => open,
+  FFC_DIV11_MODE_TX_0 => fpsc_vlo,
+  FFC_RATE_MODE_TX_0 => tx_div2_mode_ch0_c,
+  FFC_DIV11_MODE_RX_0 => fpsc_vlo,
+  FFC_RATE_MODE_RX_0 => rx_div2_mode_ch0_c,
+
+----- CH1 -----
+  HDOUTP1 => hdoutp_ch1,
+  HDOUTN1 => hdoutn_ch1,
+  HDINP1 => hdinp_ch1,
+  HDINN1 => hdinn_ch1,
+  PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
+  PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
+  PCIE_RXPOLARITY_1 => fpsc_vlo,
+  PCIE_POWERDOWN_1_0 => fpsc_vlo,
+  PCIE_POWERDOWN_1_1 => fpsc_vlo,
+  PCIE_RXVALID_1 => open,
+  PCIE_PHYSTATUS_1 => open,
+  SCISELCH1 => sci_sel_ch1,
+  SCIENCH1 => fpsc_vhi,
+  FF_RXI_CLK_1 => rxiclk_ch1,
+  FF_TXI_CLK_1 => txiclk_ch1,
+  FF_EBRD_CLK_1 => fpsc_vlo,
+  FF_RX_F_CLK_1 => rx_full_clk_ch1,
+  FF_RX_H_CLK_1 => rx_half_clk_ch1,
+  FF_TX_F_CLK_1 => tx_full_clk_ch1_sig,
+  FF_TX_H_CLK_1 => tx_half_clk_ch1,
+  FFC_CK_CORE_RX_1 => fpga_rxrefclk_ch1,
+  FF_TX_D_1_0 => txdata_ch1(0),
+  FF_TX_D_1_1 => txdata_ch1(1),
+  FF_TX_D_1_2 => txdata_ch1(2),
+  FF_TX_D_1_3 => txdata_ch1(3),
+  FF_TX_D_1_4 => txdata_ch1(4),
+  FF_TX_D_1_5 => txdata_ch1(5),
+  FF_TX_D_1_6 => txdata_ch1(6),
+  FF_TX_D_1_7 => txdata_ch1(7),
+  FF_TX_D_1_8 => tx_k_ch1,
+  FF_TX_D_1_9 => tx_force_disp_ch1,
+  FF_TX_D_1_10 => tx_disp_sel_ch1,
+  FF_TX_D_1_11 => fpsc_vlo,
+  FF_TX_D_1_12 => fpsc_vlo,
+  FF_TX_D_1_13 => fpsc_vlo,
+  FF_TX_D_1_14 => fpsc_vlo,
+  FF_TX_D_1_15 => fpsc_vlo,
+  FF_TX_D_1_16 => fpsc_vlo,
+  FF_TX_D_1_17 => fpsc_vlo,
+  FF_TX_D_1_18 => fpsc_vlo,
+  FF_TX_D_1_19 => fpsc_vlo,
+  FF_TX_D_1_20 => fpsc_vlo,
+  FF_TX_D_1_21 => fpsc_vlo,
+  FF_TX_D_1_22 => fpsc_vlo,
+  FF_TX_D_1_23 => fpsc_vlo,
+  FF_RX_D_1_0 => rxdata_ch1(0),
+  FF_RX_D_1_1 => rxdata_ch1(1),
+  FF_RX_D_1_2 => rxdata_ch1(2),
+  FF_RX_D_1_3 => rxdata_ch1(3),
+  FF_RX_D_1_4 => rxdata_ch1(4),
+  FF_RX_D_1_5 => rxdata_ch1(5),
+  FF_RX_D_1_6 => rxdata_ch1(6),
+  FF_RX_D_1_7 => rxdata_ch1(7),
+  FF_RX_D_1_8 => rx_k_ch1,
+  FF_RX_D_1_9 => rx_disp_err_ch1,
+  FF_RX_D_1_10 => rx_cv_err_ch1,
+  FF_RX_D_1_11 => open,
+  FF_RX_D_1_12 => open,
+  FF_RX_D_1_13 => open,
+  FF_RX_D_1_14 => open,
+  FF_RX_D_1_15 => open,
+  FF_RX_D_1_16 => open,
+  FF_RX_D_1_17 => open,
+  FF_RX_D_1_18 => open,
+  FF_RX_D_1_19 => open,
+  FF_RX_D_1_20 => open,
+  FF_RX_D_1_21 => open,
+  FF_RX_D_1_22 => open,
+  FF_RX_D_1_23 => open,
+
+  FFC_RRST_1 => rx_serdes_rst_ch1_c,
+  FFC_SIGNAL_DETECT_1 => fpsc_vlo,
+  FFC_SB_PFIFO_LP_1 => sb_felb_ch1_c,
+  FFC_PFIFO_CLR_1 => sb_felb_rst_ch1_c,
+  FFC_SB_INV_RX_1 => fpsc_vlo,
+  FFC_PCIE_CT_1 => fpsc_vlo,
+  FFC_PCI_DET_EN_1 => fpsc_vlo,
+  FFC_FB_LOOPBACK_1 => fpsc_vlo,
+  FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
+  FFC_EI_EN_1 => fpsc_vlo,
+  FFC_LANE_TX_RST_1 => tx_pcs_rst_ch1_c,
+  FFC_TXPWDNB_1 => tx_pwrup_ch1_c,
+  FFC_LANE_RX_RST_1 => rx_pcs_rst_ch1_c,
+  FFC_RXPWDNB_1 => rx_pwrup_ch1_c,
+  FFS_RLOS_LO_1 => rx_los_low_ch1_sig,
+  FFS_RLOS_HI_1 => open,
+  FFS_PCIE_CON_1 => open,
+  FFS_PCIE_DONE_1 => open,
+  FFS_LS_SYNC_STATUS_1 => lsm_status_ch1_s,
+  FFS_CC_OVERRUN_1 => open,
+  FFS_CC_UNDERRUN_1 => open,
+  FFS_SKP_ADDED_1 => open,
+  FFS_SKP_DELETED_1 => open,
+  FFS_RLOL_1 => rx_cdr_lol_ch1_sig,
+  FFS_RXFBFIFO_ERROR_1 => open,
+  FFS_TXFBFIFO_ERROR_1 => open,
+  LDR_CORE2TX_1 => fpsc_vlo,
+  FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
+  LDR_RX2CORE_1 => open,
+  FFS_CDR_TRAIN_DONE_1 => open,
+  FFC_DIV11_MODE_TX_1 => fpsc_vlo,
+  FFC_RATE_MODE_TX_1 => tx_div2_mode_ch1_c,
+  FFC_DIV11_MODE_RX_1 => fpsc_vlo,
+  FFC_RATE_MODE_RX_1 => rx_div2_mode_ch1_c,
+
+----- CH2 -----
+  HDOUTP2 => hdoutp_ch2,
+  HDOUTN2 => hdoutn_ch2,
+  HDINP2 => hdinp_ch2,
+  HDINN2 => hdinn_ch2,
+  PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
+  PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
+  PCIE_RXPOLARITY_2 => fpsc_vlo,
+  PCIE_POWERDOWN_2_0 => fpsc_vlo,
+  PCIE_POWERDOWN_2_1 => fpsc_vlo,
+  PCIE_RXVALID_2 => open,
+  PCIE_PHYSTATUS_2 => open,
+  SCISELCH2 => sci_sel_ch2,
+  SCIENCH2 => fpsc_vhi,
+  FF_RXI_CLK_2 => rxiclk_ch2,
+  FF_TXI_CLK_2 => txiclk_ch2,
+  FF_EBRD_CLK_2 => fpsc_vlo,
+  FF_RX_F_CLK_2 => rx_full_clk_ch2,
+  FF_RX_H_CLK_2 => rx_half_clk_ch2,
+  FF_TX_F_CLK_2 => tx_full_clk_ch2_sig,
+  FF_TX_H_CLK_2 => tx_half_clk_ch2,
+  FFC_CK_CORE_RX_2 => fpga_rxrefclk_ch2,
+  FF_TX_D_2_0 => txdata_ch2(0),
+  FF_TX_D_2_1 => txdata_ch2(1),
+  FF_TX_D_2_2 => txdata_ch2(2),
+  FF_TX_D_2_3 => txdata_ch2(3),
+  FF_TX_D_2_4 => txdata_ch2(4),
+  FF_TX_D_2_5 => txdata_ch2(5),
+  FF_TX_D_2_6 => txdata_ch2(6),
+  FF_TX_D_2_7 => txdata_ch2(7),
+  FF_TX_D_2_8 => tx_k_ch2,
+  FF_TX_D_2_9 => tx_force_disp_ch2,
+  FF_TX_D_2_10 => tx_disp_sel_ch2,
+  FF_TX_D_2_11 => fpsc_vlo,
+  FF_TX_D_2_12 => fpsc_vlo,
+  FF_TX_D_2_13 => fpsc_vlo,
+  FF_TX_D_2_14 => fpsc_vlo,
+  FF_TX_D_2_15 => fpsc_vlo,
+  FF_TX_D_2_16 => fpsc_vlo,
+  FF_TX_D_2_17 => fpsc_vlo,
+  FF_TX_D_2_18 => fpsc_vlo,
+  FF_TX_D_2_19 => fpsc_vlo,
+  FF_TX_D_2_20 => fpsc_vlo,
+  FF_TX_D_2_21 => fpsc_vlo,
+  FF_TX_D_2_22 => fpsc_vlo,
+  FF_TX_D_2_23 => fpsc_vlo,
+  FF_RX_D_2_0 => rxdata_ch2(0),
+  FF_RX_D_2_1 => rxdata_ch2(1),
+  FF_RX_D_2_2 => rxdata_ch2(2),
+  FF_RX_D_2_3 => rxdata_ch2(3),
+  FF_RX_D_2_4 => rxdata_ch2(4),
+  FF_RX_D_2_5 => rxdata_ch2(5),
+  FF_RX_D_2_6 => rxdata_ch2(6),
+  FF_RX_D_2_7 => rxdata_ch2(7),
+  FF_RX_D_2_8 => rx_k_ch2,
+  FF_RX_D_2_9 => rx_disp_err_ch2,
+  FF_RX_D_2_10 => rx_cv_err_ch2,
+  FF_RX_D_2_11 => open,
+  FF_RX_D_2_12 => open,
+  FF_RX_D_2_13 => open,
+  FF_RX_D_2_14 => open,
+  FF_RX_D_2_15 => open,
+  FF_RX_D_2_16 => open,
+  FF_RX_D_2_17 => open,
+  FF_RX_D_2_18 => open,
+  FF_RX_D_2_19 => open,
+  FF_RX_D_2_20 => open,
+  FF_RX_D_2_21 => open,
+  FF_RX_D_2_22 => open,
+  FF_RX_D_2_23 => open,
+
+  FFC_RRST_2 => rx_serdes_rst_ch2_c,
+  FFC_SIGNAL_DETECT_2 => fpsc_vlo,
+  FFC_SB_PFIFO_LP_2 => sb_felb_ch2_c,
+  FFC_PFIFO_CLR_2 => sb_felb_rst_ch2_c,
+  FFC_SB_INV_RX_2 => fpsc_vlo,
+  FFC_PCIE_CT_2 => fpsc_vlo,
+  FFC_PCI_DET_EN_2 => fpsc_vlo,
+  FFC_FB_LOOPBACK_2 => fpsc_vlo,
+  FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
+  FFC_EI_EN_2 => fpsc_vlo,
+  FFC_LANE_TX_RST_2 => tx_pcs_rst_ch2_c,
+  FFC_TXPWDNB_2 => tx_pwrup_ch2_c,
+  FFC_LANE_RX_RST_2 => rx_pcs_rst_ch2_c,
+  FFC_RXPWDNB_2 => rx_pwrup_ch2_c,
+  FFS_RLOS_LO_2 => rx_los_low_ch2_sig,
+  FFS_RLOS_HI_2 => open,
+  FFS_PCIE_CON_2 => open,
+  FFS_PCIE_DONE_2 => open,
+  FFS_LS_SYNC_STATUS_2 => lsm_status_ch2_s,
+  FFS_CC_OVERRUN_2 => open,
+  FFS_CC_UNDERRUN_2 => open,
+  FFS_SKP_ADDED_2 => open,
+  FFS_SKP_DELETED_2 => open,
+  FFS_RLOL_2 => rx_cdr_lol_ch2_sig,
+  FFS_RXFBFIFO_ERROR_2 => open,
+  FFS_TXFBFIFO_ERROR_2 => open,
+  LDR_CORE2TX_2 => fpsc_vlo,
+  FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
+  LDR_RX2CORE_2 => open,
+  FFS_CDR_TRAIN_DONE_2 => open,
+  FFC_DIV11_MODE_TX_2 => fpsc_vlo,
+  FFC_RATE_MODE_TX_2 => tx_div2_mode_ch2_c,
+  FFC_DIV11_MODE_RX_2 => fpsc_vlo,
+  FFC_RATE_MODE_RX_2 => rx_div2_mode_ch2_c,
+
+----- CH3 -----
+  HDOUTP3 => hdoutp_ch3,
+  HDOUTN3 => hdoutn_ch3,
+  HDINP3 => hdinp_ch3,
+  HDINN3 => hdinn_ch3,
+  PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
+  PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
+  PCIE_RXPOLARITY_3 => fpsc_vlo,
+  PCIE_POWERDOWN_3_0 => fpsc_vlo,
+  PCIE_POWERDOWN_3_1 => fpsc_vlo,
+  PCIE_RXVALID_3 => open,
+  PCIE_PHYSTATUS_3 => open,
+  SCISELCH3 => sci_sel_ch3,
+  SCIENCH3 => fpsc_vhi,
+  FF_RXI_CLK_3 => rxiclk_ch3,
+  FF_TXI_CLK_3 => txiclk_ch3,
+  FF_EBRD_CLK_3 => fpsc_vlo,
+  FF_RX_F_CLK_3 => rx_full_clk_ch3,
+  FF_RX_H_CLK_3 => rx_half_clk_ch3,
+  FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,
+  FF_TX_H_CLK_3 => tx_half_clk_ch3,
+  FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3,
+  FF_TX_D_3_0 => txdata_ch3(0),
+  FF_TX_D_3_1 => txdata_ch3(1),
+  FF_TX_D_3_2 => txdata_ch3(2),
+  FF_TX_D_3_3 => txdata_ch3(3),
+  FF_TX_D_3_4 => txdata_ch3(4),
+  FF_TX_D_3_5 => txdata_ch3(5),
+  FF_TX_D_3_6 => txdata_ch3(6),
+  FF_TX_D_3_7 => txdata_ch3(7),
+  FF_TX_D_3_8 => tx_k_ch3,
+  FF_TX_D_3_9 => tx_force_disp_ch3,
+  FF_TX_D_3_10 => tx_disp_sel_ch3,
+  FF_TX_D_3_11 => fpsc_vlo,
+  FF_TX_D_3_12 => fpsc_vlo,
+  FF_TX_D_3_13 => fpsc_vlo,
+  FF_TX_D_3_14 => fpsc_vlo,
+  FF_TX_D_3_15 => fpsc_vlo,
+  FF_TX_D_3_16 => fpsc_vlo,
+  FF_TX_D_3_17 => fpsc_vlo,
+  FF_TX_D_3_18 => fpsc_vlo,
+  FF_TX_D_3_19 => fpsc_vlo,
+  FF_TX_D_3_20 => fpsc_vlo,
+  FF_TX_D_3_21 => fpsc_vlo,
+  FF_TX_D_3_22 => fpsc_vlo,
+  FF_TX_D_3_23 => fpsc_vlo,
+  FF_RX_D_3_0 => rxdata_ch3(0),
+  FF_RX_D_3_1 => rxdata_ch3(1),
+  FF_RX_D_3_2 => rxdata_ch3(2),
+  FF_RX_D_3_3 => rxdata_ch3(3),
+  FF_RX_D_3_4 => rxdata_ch3(4),
+  FF_RX_D_3_5 => rxdata_ch3(5),
+  FF_RX_D_3_6 => rxdata_ch3(6),
+  FF_RX_D_3_7 => rxdata_ch3(7),
+  FF_RX_D_3_8 => rx_k_ch3,
+  FF_RX_D_3_9 => rx_disp_err_ch3,
+  FF_RX_D_3_10 => rx_cv_err_ch3,
+  FF_RX_D_3_11 => open,
+  FF_RX_D_3_12 => open,
+  FF_RX_D_3_13 => open,
+  FF_RX_D_3_14 => open,
+  FF_RX_D_3_15 => open,
+  FF_RX_D_3_16 => open,
+  FF_RX_D_3_17 => open,
+  FF_RX_D_3_18 => open,
+  FF_RX_D_3_19 => open,
+  FF_RX_D_3_20 => open,
+  FF_RX_D_3_21 => open,
+  FF_RX_D_3_22 => open,
+  FF_RX_D_3_23 => open,
+
+  FFC_RRST_3 => rx_serdes_rst_ch3_c,
+  FFC_SIGNAL_DETECT_3 => fpsc_vlo,
+  FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c,
+  FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c,
+  FFC_SB_INV_RX_3 => fpsc_vlo,
+  FFC_PCIE_CT_3 => fpsc_vlo,
+  FFC_PCI_DET_EN_3 => fpsc_vlo,
+  FFC_FB_LOOPBACK_3 => fpsc_vlo,
+  FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
+  FFC_EI_EN_3 => fpsc_vlo,
+  FFC_LANE_TX_RST_3 => tx_pcs_rst_ch3_c,
+  FFC_TXPWDNB_3 => tx_pwrup_ch3_c,
+  FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c,
+  FFC_RXPWDNB_3 => rx_pwrup_ch3_c,
+  FFS_RLOS_LO_3 => rx_los_low_ch3_sig,
+  FFS_RLOS_HI_3 => open,
+  FFS_PCIE_CON_3 => open,
+  FFS_PCIE_DONE_3 => open,
+  FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s,
+  FFS_CC_OVERRUN_3 => open,
+  FFS_CC_UNDERRUN_3 => open,
+  FFS_SKP_ADDED_3 => open,
+  FFS_SKP_DELETED_3 => open,
+  FFS_RLOL_3 => rx_cdr_lol_ch3_sig,
+  FFS_RXFBFIFO_ERROR_3 => open,
+  FFS_TXFBFIFO_ERROR_3 => open,
+  LDR_CORE2TX_3 => fpsc_vlo,
+  FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
+  LDR_RX2CORE_3 => open,
+  FFS_CDR_TRAIN_DONE_3 => open,
+  FFC_DIV11_MODE_TX_3 => fpsc_vlo,
+  FFC_RATE_MODE_TX_3 => tx_div2_mode_ch3_c,
+  FFC_DIV11_MODE_RX_3 => fpsc_vlo,
+  FFC_RATE_MODE_RX_3 => rx_div2_mode_ch3_c,
+
+----- Auxilliary ----
+  SCIWDATA7 => sci_wrdata(7),
+  SCIWDATA6 => sci_wrdata(6),
+  SCIWDATA5 => sci_wrdata(5),
+  SCIWDATA4 => sci_wrdata(4),
+  SCIWDATA3 => sci_wrdata(3),
+  SCIWDATA2 => sci_wrdata(2),
+  SCIWDATA1 => sci_wrdata(1),
+  SCIWDATA0 => sci_wrdata(0),
+  SCIADDR5 => sci_addr(5),
+  SCIADDR4 => sci_addr(4),
+  SCIADDR3 => sci_addr(3),
+  SCIADDR2 => sci_addr(2),
+  SCIADDR1 => sci_addr(1),
+  SCIADDR0 => sci_addr(0),
+  SCIRDATA7 => sci_rddata(7),
+  SCIRDATA6 => sci_rddata(6),
+  SCIRDATA5 => sci_rddata(5),
+  SCIRDATA4 => sci_rddata(4),
+  SCIRDATA3 => sci_rddata(3),
+  SCIRDATA2 => sci_rddata(2),
+  SCIRDATA1 => sci_rddata(1),
+  SCIRDATA0 => sci_rddata(0),
+  SCIENAUX => fpsc_vhi,
+  SCISELAUX => sci_sel_quad,
+  SCIRD => sci_rd,
+  SCIWSTN => sci_wrn,
+  CYAWSTN => fpsc_vlo,
+  SCIINT => open,
+  FFC_CK_CORE_TX => fpga_txrefclk,
+  FFC_MACRO_RST => serdes_rst_qd_c,
+  FFC_QUAD_RST => rst_qd_c,
+  FFC_TRST => tx_serdes_rst_c,
+  FFS_PLOL => tx_pll_lol_qd_sig,
+  FFC_SYNC_TOGGLE => tx_sync_qd_c,
+  REFCK2CORE => refclk2fpga_sig,
+  CIN0 => fpsc_vlo,
+  CIN1 => fpsc_vlo,
+  CIN2 => fpsc_vlo,
+  CIN3 => fpsc_vlo,
+  CIN4 => fpsc_vlo,
+  CIN5 => fpsc_vlo,
+  CIN6 => fpsc_vlo,
+  CIN7 => fpsc_vlo,
+  CIN8 => fpsc_vlo,
+  CIN9 => fpsc_vlo,
+  CIN10 => fpsc_vlo,
+  CIN11 => fpsc_vlo,
+  COUT0 => open,
+  COUT1 => open,
+  COUT2 => open,
+  COUT3 => open,
+  COUT4 => open,
+  COUT5 => open,
+  COUT6 => open,
+  COUT7 => open,
+  COUT8 => open,
+  COUT9 => open,
+  COUT10 => open,
+  COUT11 => open,
+  COUT12 => open,
+  COUT13 => open,
+  COUT14 => open,
+  COUT15 => open,
+  COUT16 => open,
+  COUT17 => open,
+  COUT18 => open,
+  COUT19 => open,
+  REFCLK_FROM_NQ => refclk_from_nq,
+  REFCLK_TO_NQ => open);
+
+                                                                                              
+                                                                                              
+                                                                                              
+--synopsys translate_off
+file_read : PROCESS
+VARIABLE open_status : file_open_status;
+FILE config : text;
+BEGIN
+   file_open (open_status, config, USER_CONFIG_FILE, read_mode);
+   IF (open_status = name_error) THEN
+      report "Auto configuration file for PCS module not found.  PCS internal configuration registers will not be initialized correctly during simulation!"
+      severity ERROR;
+   END IF;
+   wait;
+END PROCESS;
+--synopsys translate_on
+end serdes_sync_125_full_arch ;
diff --git a/data_concentrator/sources/lattice/ecp3/serdes_sync_160_full.ipx b/data_concentrator/sources/lattice/ecp3/serdes_sync_160_full.ipx
new file mode 100644
index 0000000..e29a3d5
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/serdes_sync_160_full.ipx
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="serdes_sync_160_full" module="serdes_sync_160_full" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 08 29 13:27:22.516" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="serdes_sync_160_full.lpc" type="lpc" modified="2014 08 29 13:27:15.199"/>
+		<File name="serdes_sync_160_full.pp" type="pp" modified="2014 08 29 13:27:15.201"/>
+		<File name="serdes_sync_160_full.sym" type="sym" modified="2014 08 29 13:27:15.445"/>
+		<File name="serdes_sync_160_full.tft" type="tft" modified="2014 08 29 13:27:15.231"/>
+		<File name="serdes_sync_160_full.txt" type="pcs_module" modified="2014 08 29 13:27:15.234"/>
+		<File name="serdes_sync_160_full.vhd" type="top_level_vhdl" modified="2014 08 29 13:27:15.230"/>
+  </Package>
+</DiamondModule>
diff --git a/data_concentrator/sources/lattice/ecp3/serdes_sync_160_full.lpc b/data_concentrator/sources/lattice/ecp3/serdes_sync_160_full.lpc
new file mode 100644
index 0000000..0da2936
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/serdes_sync_160_full.lpc
@@ -0,0 +1,258 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PCS
+CoreRevision=8.2
+ModuleName=serdes_sync_160_full
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=08/29/2014
+Time=13:27:15
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+_mode0=RXTX
+_mode1=RXTX
+_mode2=RXTX
+_mode3=RXTX
+_protocol0=G8B10B
+_protocol1=G8B10B
+_protocol2=G8B10B
+_protocol3=G8B10B
+_ldr0=DISABLED
+_ldr1=DISABLED
+_ldr2=DISABLED
+_ldr3=DISABLED
+_datarange=1.6
+_pll_txsrc=INTERNAL
+_refclk_mult=10X
+_refclk_rate=160.0
+_tx_protocol0=G8B10B
+_tx_protocol1=G8B10B
+_tx_protocol2=G8B10B
+_tx_protocol3=G8B10B
+_tx_data_rate0=FULL
+_tx_data_rate1=FULL
+_tx_data_rate2=FULL
+_tx_data_rate3=FULL
+_tx_data_width0=8
+_tx_data_width1=8
+_tx_data_width2=8
+_tx_data_width3=8
+_tx_fifo0=DISABLED
+_tx_fifo1=DISABLED
+_tx_fifo2=DISABLED
+_tx_fifo3=DISABLED
+_tx_ficlk_rate0=160.0
+_tx_ficlk_rate1=160.0
+_tx_ficlk_rate2=160.0
+_tx_ficlk_rate3=160.0
+_pll_rxsrc0=INTERNAL
+_pll_rxsrc1=INTERNAL
+_pll_rxsrc2=INTERNAL
+_pll_rxsrc3=INTERNAL
+Multiplier0=
+Multiplier1=
+Multiplier2=
+Multiplier3=
+_rx_datarange0=1.6
+_rx_datarange1=1.6
+_rx_datarange2=1.6
+_rx_datarange3=1.6
+_rx_protocol0=G8B10B
+_rx_protocol1=G8B10B
+_rx_protocol2=G8B10B
+_rx_protocol3=G8B10B
+_rx_data_rate0=FULL
+_rx_data_rate1=FULL
+_rx_data_rate2=FULL
+_rx_data_rate3=FULL
+_rxrefclk_rate0=160.0
+_rxrefclk_rate1=160.0
+_rxrefclk_rate2=160.0
+_rxrefclk_rate3=160.0
+_rx_data_width0=8
+_rx_data_width1=8
+_rx_data_width2=8
+_rx_data_width3=8
+_rx_fifo0=ENABLED
+_rx_fifo1=ENABLED
+_rx_fifo2=ENABLED
+_rx_fifo3=ENABLED
+_rx_ficlk_rate0=160.0
+_rx_ficlk_rate1=160.0
+_rx_ficlk_rate2=160.0
+_rx_ficlk_rate3=160.0
+_tdrv_ch0=1
+_tdrv_ch1=1
+_tdrv_ch2=1
+_tdrv_ch3=1
+_tx_pre0=DISABLED
+_tx_pre1=DISABLED
+_tx_pre2=DISABLED
+_tx_pre3=DISABLED
+_rterm_tx0=50
+_rterm_tx1=50
+_rterm_tx2=50
+_rterm_tx3=50
+_rx_eq0=DISABLED
+_rx_eq1=DISABLED
+_rx_eq2=DISABLED
+_rx_eq3=DISABLED
+_rterm_rx0=50
+_rterm_rx1=50
+_rterm_rx2=50
+_rterm_rx3=50
+_rx_dcc0=DC
+_rx_dcc1=DC
+_rx_dcc2=DC
+_rx_dcc3=DC
+_los_threshold_mode0=LOS_E
+_los_threshold_mode1=LOS_E
+_los_threshold_mode2=LOS_E
+_los_threshold_mode3=LOS_E
+_los_threshold_lo0=2
+_los_threshold_lo1=2
+_los_threshold_lo2=2
+_los_threshold_lo3=2
+_los_threshold_hi0=7
+_los_threshold_hi1=7
+_los_threshold_hi2=7
+_los_threshold_hi3=7
+_pll_term=50
+_pll_dcc=AC
+_pll_lol_set=1
+_tx_sb0=DISABLED
+_tx_sb1=DISABLED
+_tx_sb2=DISABLED
+_tx_sb3=DISABLED
+_tx_8b10b0=ENABLED
+_tx_8b10b1=ENABLED
+_tx_8b10b2=ENABLED
+_tx_8b10b3=ENABLED
+_rx_sb0=DISABLED
+_rx_sb1=DISABLED
+_rx_sb2=DISABLED
+_rx_sb3=DISABLED
+_ird0=DISABLED
+_ird1=DISABLED
+_ird2=DISABLED
+_ird3=DISABLED
+_rx_8b10b0=ENABLED
+_rx_8b10b1=ENABLED
+_rx_8b10b2=ENABLED
+_rx_8b10b3=ENABLED
+_rxwa0=ENABLED
+_rxwa1=ENABLED
+_rxwa2=ENABLED
+_rxwa3=ENABLED
+_ilsm0=ENABLED
+_ilsm1=ENABLED
+_ilsm2=ENABLED
+_ilsm3=ENABLED
+_scomma0=User Defined
+_scomma1=User Defined
+_scomma2=User Defined
+_scomma3=User Defined
+_comma_a0=1100000101
+_comma_a1=1100000101
+_comma_a2=1100000101
+_comma_a3=1100000101
+_comma_b0=0011111010
+_comma_b1=0011111010
+_comma_b2=0011111010
+_comma_b3=0011111010
+_comma_m0=1111111111
+_comma_m1=1111111111
+_comma_m2=1111111111
+_comma_m3=1111111111
+_ctc0=DISABLED
+_ctc1=DISABLED
+_ctc2=DISABLED
+_ctc3=DISABLED
+_cc_match_mode0=1
+_cc_match_mode1=1
+_cc_match_mode2=1
+_cc_match_mode3=1
+_k00=01
+_k01=01
+_k02=01
+_k03=01
+_k10=00
+_k11=00
+_k12=00
+_k13=00
+_k20=01
+_k21=01
+_k22=01
+_k23=01
+_k30=01
+_k31=01
+_k32=01
+_k33=01
+_byten00=00011100
+_byten01=00011100
+_byten02=00011100
+_byten03=00011100
+_byten10=00000000
+_byten11=00000000
+_byten12=00000000
+_byten13=00000000
+_byten20=00011100
+_byten21=00011100
+_byten22=00011100
+_byten23=00011100
+_byten30=00011100
+_byten31=00011100
+_byten32=00011100
+_byten33=00011100
+_cc_min_ipg0=3
+_cc_min_ipg1=3
+_cc_min_ipg2=3
+_cc_min_ipg3=3
+_cchmark=9
+_cclmark=7
+_loopback=DISABLED
+_lbtype0=DISABLED
+_lbtype1=DISABLED
+_lbtype2=DISABLED
+_lbtype3=DISABLED
+_teidle_ch0=DISABLED
+_teidle_ch1=DISABLED
+_teidle_ch2=DISABLED
+_teidle_ch3=DISABLED
+_rst_gen=DISABLED
+_rx_los_port0=Internal
+_rx_los_port1=Internal
+_rx_los_port2=Internal
+_rx_los_port3=Internal
+_sci_ports=ENABLED
+_sci_int_port=DISABLED
+_refck2core=DISABLED
+Regen=auto
+PAR1=0
+PARTrace1=0
+PAR3=0
+PARTrace3=0
+
+[FilesGenerated]
+serdes_sync_160_full.pp=pp
+serdes_sync_160_full.tft=tft
+serdes_sync_160_full.txt=pcs_module
+serdes_sync_160_full.sym=sym
diff --git a/data_concentrator/sources/lattice/ecp3/serdes_sync_160_full.vhd b/data_concentrator/sources/lattice/ecp3/serdes_sync_160_full.vhd
new file mode 100644
index 0000000..a0d67da
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/serdes_sync_160_full.vhd
@@ -0,0 +1,2810 @@
+
+                                                                                                         
+
+--synopsys translate_off
+
+library pcsd_work;
+use pcsd_work.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity PCSD is
+GENERIC(
+  CONFIG_FILE : String;
+  QUAD_MODE : String;
+  CH0_CDR_SRC   : String := "REFCLK_EXT";
+  CH1_CDR_SRC   : String := "REFCLK_EXT";
+  CH2_CDR_SRC   : String := "REFCLK_EXT";
+  CH3_CDR_SRC   : String := "REFCLK_EXT";
+  PLL_SRC   : String
+--  CONFIG_FILE : String  := "serdes_sync_160_full.txt";
+--  QUAD_MODE : String := "SINGLE";
+--  CH0_CDR_SRC   : String := "REFCLK_CORE";
+--  CH1_CDR_SRC   : String := "REFCLK_CORE";
+--  CH2_CDR_SRC   : String := "REFCLK_CORE";
+--  CH3_CDR_SRC   : String := "REFCLK_CORE";
+--  PLL_SRC   : String := "REFCLK_CORE"
+  );
+port (
+  HDINN0             : in std_logic;
+  HDINN1             : in std_logic;
+  HDINN2             : in std_logic;
+  HDINN3             : in std_logic;
+  HDINP0             : in std_logic;
+  HDINP1             : in std_logic;
+  HDINP2             : in std_logic;
+  HDINP3             : in std_logic;
+  REFCLKN             : in std_logic;
+  REFCLKP             : in std_logic;
+  CIN0             : in std_logic;
+  CIN1             : in std_logic;
+  CIN2             : in std_logic;
+  CIN3             : in std_logic;
+  CIN4             : in std_logic;
+  CIN5             : in std_logic;
+  CIN6             : in std_logic;
+  CIN7             : in std_logic;
+  CIN8             : in std_logic;
+  CIN9             : in std_logic;
+  CIN10             : in std_logic;
+  CIN11             : in std_logic;
+  CYAWSTN             : in std_logic;
+  FF_EBRD_CLK_0             : in std_logic;
+  FF_EBRD_CLK_1             : in std_logic;
+  FF_EBRD_CLK_2             : in std_logic;
+  FF_EBRD_CLK_3             : in std_logic;
+  FF_RXI_CLK_0             : in std_logic;
+  FF_RXI_CLK_1             : in std_logic;
+  FF_RXI_CLK_2             : in std_logic;
+  FF_RXI_CLK_3             : in std_logic;
+  FF_TX_D_0_0             : in std_logic;
+  FF_TX_D_0_1             : in std_logic;
+  FF_TX_D_0_2             : in std_logic;
+  FF_TX_D_0_3             : in std_logic;
+  FF_TX_D_0_4             : in std_logic;
+  FF_TX_D_0_5             : in std_logic;
+  FF_TX_D_0_6             : in std_logic;
+  FF_TX_D_0_7             : in std_logic;
+  FF_TX_D_0_8             : in std_logic;
+  FF_TX_D_0_9             : in std_logic;
+  FF_TX_D_0_10             : in std_logic;
+  FF_TX_D_0_11             : in std_logic;
+  FF_TX_D_0_12             : in std_logic;
+  FF_TX_D_0_13             : in std_logic;
+  FF_TX_D_0_14             : in std_logic;
+  FF_TX_D_0_15             : in std_logic;
+  FF_TX_D_0_16             : in std_logic;
+  FF_TX_D_0_17             : in std_logic;
+  FF_TX_D_0_18             : in std_logic;
+  FF_TX_D_0_19             : in std_logic;
+  FF_TX_D_0_20             : in std_logic;
+  FF_TX_D_0_21             : in std_logic;
+  FF_TX_D_0_22             : in std_logic;
+  FF_TX_D_0_23             : in std_logic;
+  FF_TX_D_1_0             : in std_logic;
+  FF_TX_D_1_1             : in std_logic;
+  FF_TX_D_1_2             : in std_logic;
+  FF_TX_D_1_3             : in std_logic;
+  FF_TX_D_1_4             : in std_logic;
+  FF_TX_D_1_5             : in std_logic;
+  FF_TX_D_1_6             : in std_logic;
+  FF_TX_D_1_7             : in std_logic;
+  FF_TX_D_1_8             : in std_logic;
+  FF_TX_D_1_9             : in std_logic;
+  FF_TX_D_1_10             : in std_logic;
+  FF_TX_D_1_11             : in std_logic;
+  FF_TX_D_1_12             : in std_logic;
+  FF_TX_D_1_13             : in std_logic;
+  FF_TX_D_1_14             : in std_logic;
+  FF_TX_D_1_15             : in std_logic;
+  FF_TX_D_1_16             : in std_logic;
+  FF_TX_D_1_17             : in std_logic;
+  FF_TX_D_1_18             : in std_logic;
+  FF_TX_D_1_19             : in std_logic;
+  FF_TX_D_1_20             : in std_logic;
+  FF_TX_D_1_21             : in std_logic;
+  FF_TX_D_1_22             : in std_logic;
+  FF_TX_D_1_23             : in std_logic;
+  FF_TX_D_2_0             : in std_logic;
+  FF_TX_D_2_1             : in std_logic;
+  FF_TX_D_2_2             : in std_logic;
+  FF_TX_D_2_3             : in std_logic;
+  FF_TX_D_2_4             : in std_logic;
+  FF_TX_D_2_5             : in std_logic;
+  FF_TX_D_2_6             : in std_logic;
+  FF_TX_D_2_7             : in std_logic;
+  FF_TX_D_2_8             : in std_logic;
+  FF_TX_D_2_9             : in std_logic;
+  FF_TX_D_2_10             : in std_logic;
+  FF_TX_D_2_11             : in std_logic;
+  FF_TX_D_2_12             : in std_logic;
+  FF_TX_D_2_13             : in std_logic;
+  FF_TX_D_2_14             : in std_logic;
+  FF_TX_D_2_15             : in std_logic;
+  FF_TX_D_2_16             : in std_logic;
+  FF_TX_D_2_17             : in std_logic;
+  FF_TX_D_2_18             : in std_logic;
+  FF_TX_D_2_19             : in std_logic;
+  FF_TX_D_2_20             : in std_logic;
+  FF_TX_D_2_21             : in std_logic;
+  FF_TX_D_2_22             : in std_logic;
+  FF_TX_D_2_23             : in std_logic;
+  FF_TX_D_3_0             : in std_logic;
+  FF_TX_D_3_1             : in std_logic;
+  FF_TX_D_3_2             : in std_logic;
+  FF_TX_D_3_3             : in std_logic;
+  FF_TX_D_3_4             : in std_logic;
+  FF_TX_D_3_5             : in std_logic;
+  FF_TX_D_3_6             : in std_logic;
+  FF_TX_D_3_7             : in std_logic;
+  FF_TX_D_3_8             : in std_logic;
+  FF_TX_D_3_9             : in std_logic;
+  FF_TX_D_3_10             : in std_logic;
+  FF_TX_D_3_11             : in std_logic;
+  FF_TX_D_3_12             : in std_logic;
+  FF_TX_D_3_13             : in std_logic;
+  FF_TX_D_3_14             : in std_logic;
+  FF_TX_D_3_15             : in std_logic;
+  FF_TX_D_3_16             : in std_logic;
+  FF_TX_D_3_17             : in std_logic;
+  FF_TX_D_3_18             : in std_logic;
+  FF_TX_D_3_19             : in std_logic;
+  FF_TX_D_3_20             : in std_logic;
+  FF_TX_D_3_21             : in std_logic;
+  FF_TX_D_3_22             : in std_logic;
+  FF_TX_D_3_23             : in std_logic;
+  FF_TXI_CLK_0             : in std_logic;
+  FF_TXI_CLK_1             : in std_logic;
+  FF_TXI_CLK_2             : in std_logic;
+  FF_TXI_CLK_3             : in std_logic;
+  FFC_CK_CORE_RX_0         : in std_logic;
+  FFC_CK_CORE_RX_1         : in std_logic;
+  FFC_CK_CORE_RX_2         : in std_logic;
+  FFC_CK_CORE_RX_3         : in std_logic;
+  FFC_CK_CORE_TX           : in std_logic;
+  FFC_EI_EN_0             : in std_logic;
+  FFC_EI_EN_1             : in std_logic;
+  FFC_EI_EN_2             : in std_logic;
+  FFC_EI_EN_3             : in std_logic;
+  FFC_ENABLE_CGALIGN_0             : in std_logic;
+  FFC_ENABLE_CGALIGN_1             : in std_logic;
+  FFC_ENABLE_CGALIGN_2             : in std_logic;
+  FFC_ENABLE_CGALIGN_3             : in std_logic;
+  FFC_FB_LOOPBACK_0             : in std_logic;
+  FFC_FB_LOOPBACK_1             : in std_logic;
+  FFC_FB_LOOPBACK_2             : in std_logic;
+  FFC_FB_LOOPBACK_3             : in std_logic;
+  FFC_LANE_RX_RST_0             : in std_logic;
+  FFC_LANE_RX_RST_1             : in std_logic;
+  FFC_LANE_RX_RST_2             : in std_logic;
+  FFC_LANE_RX_RST_3             : in std_logic;
+  FFC_LANE_TX_RST_0             : in std_logic;
+  FFC_LANE_TX_RST_1             : in std_logic;
+  FFC_LANE_TX_RST_2             : in std_logic;
+  FFC_LANE_TX_RST_3             : in std_logic;
+  FFC_MACRO_RST             : in std_logic;
+  FFC_PCI_DET_EN_0             : in std_logic;
+  FFC_PCI_DET_EN_1             : in std_logic;
+  FFC_PCI_DET_EN_2             : in std_logic;
+  FFC_PCI_DET_EN_3             : in std_logic;
+  FFC_PCIE_CT_0             : in std_logic;
+  FFC_PCIE_CT_1             : in std_logic;
+  FFC_PCIE_CT_2             : in std_logic;
+  FFC_PCIE_CT_3             : in std_logic;
+  FFC_PFIFO_CLR_0             : in std_logic;
+  FFC_PFIFO_CLR_1             : in std_logic;
+  FFC_PFIFO_CLR_2             : in std_logic;
+  FFC_PFIFO_CLR_3             : in std_logic;
+  FFC_QUAD_RST             : in std_logic;
+  FFC_RRST_0             : in std_logic;
+  FFC_RRST_1             : in std_logic;
+  FFC_RRST_2             : in std_logic;
+  FFC_RRST_3             : in std_logic;
+  FFC_RXPWDNB_0             : in std_logic;
+  FFC_RXPWDNB_1             : in std_logic;
+  FFC_RXPWDNB_2             : in std_logic;
+  FFC_RXPWDNB_3             : in std_logic;
+  FFC_SB_INV_RX_0             : in std_logic;
+  FFC_SB_INV_RX_1             : in std_logic;
+  FFC_SB_INV_RX_2             : in std_logic;
+  FFC_SB_INV_RX_3             : in std_logic;
+  FFC_SB_PFIFO_LP_0             : in std_logic;
+  FFC_SB_PFIFO_LP_1             : in std_logic;
+  FFC_SB_PFIFO_LP_2             : in std_logic;
+  FFC_SB_PFIFO_LP_3             : in std_logic;
+  FFC_SIGNAL_DETECT_0             : in std_logic;
+  FFC_SIGNAL_DETECT_1             : in std_logic;
+  FFC_SIGNAL_DETECT_2             : in std_logic;
+  FFC_SIGNAL_DETECT_3             : in std_logic;
+  FFC_SYNC_TOGGLE             : in std_logic;
+  FFC_TRST             : in std_logic;
+  FFC_TXPWDNB_0             : in std_logic;
+  FFC_TXPWDNB_1             : in std_logic;
+  FFC_TXPWDNB_2             : in std_logic;
+  FFC_TXPWDNB_3             : in std_logic;
+  FFC_RATE_MODE_RX_0        : in std_logic;
+  FFC_RATE_MODE_RX_1        : in std_logic;
+  FFC_RATE_MODE_RX_2        : in std_logic;
+  FFC_RATE_MODE_RX_3        : in std_logic;
+  FFC_RATE_MODE_TX_0        : in std_logic;
+  FFC_RATE_MODE_TX_1        : in std_logic;
+  FFC_RATE_MODE_TX_2        : in std_logic;
+  FFC_RATE_MODE_TX_3        : in std_logic;
+  FFC_DIV11_MODE_RX_0       : in std_logic;
+  FFC_DIV11_MODE_RX_1       : in std_logic;
+  FFC_DIV11_MODE_RX_2       : in std_logic;
+  FFC_DIV11_MODE_RX_3       : in std_logic;
+  FFC_DIV11_MODE_TX_0       : in std_logic;
+  FFC_DIV11_MODE_TX_1       : in std_logic;
+  FFC_DIV11_MODE_TX_2       : in std_logic;
+  FFC_DIV11_MODE_TX_3       : in std_logic;
+  LDR_CORE2TX_0             : in std_logic;
+  LDR_CORE2TX_1             : in std_logic;
+  LDR_CORE2TX_2             : in std_logic;
+  LDR_CORE2TX_3             : in std_logic;
+  FFC_LDR_CORE2TX_EN_0      : in std_logic;
+  FFC_LDR_CORE2TX_EN_1      : in std_logic;
+  FFC_LDR_CORE2TX_EN_2      : in std_logic;
+  FFC_LDR_CORE2TX_EN_3      : in std_logic;
+  PCIE_POWERDOWN_0_0      : in std_logic;
+  PCIE_POWERDOWN_0_1      : in std_logic;
+  PCIE_POWERDOWN_1_0      : in std_logic;
+  PCIE_POWERDOWN_1_1      : in std_logic;
+  PCIE_POWERDOWN_2_0      : in std_logic;
+  PCIE_POWERDOWN_2_1      : in std_logic;
+  PCIE_POWERDOWN_3_0      : in std_logic;
+  PCIE_POWERDOWN_3_1      : in std_logic;
+  PCIE_RXPOLARITY_0         : in std_logic;
+  PCIE_RXPOLARITY_1         : in std_logic;
+  PCIE_RXPOLARITY_2         : in std_logic;
+  PCIE_RXPOLARITY_3         : in std_logic;
+  PCIE_TXCOMPLIANCE_0       : in std_logic;
+  PCIE_TXCOMPLIANCE_1       : in std_logic;
+  PCIE_TXCOMPLIANCE_2       : in std_logic;
+  PCIE_TXCOMPLIANCE_3       : in std_logic;
+  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
+  SCIADDR0             : in std_logic;
+  SCIADDR1             : in std_logic;
+  SCIADDR2             : in std_logic;
+  SCIADDR3             : in std_logic;
+  SCIADDR4             : in std_logic;
+  SCIADDR5             : in std_logic;
+  SCIENAUX             : in std_logic;
+  SCIENCH0             : in std_logic;
+  SCIENCH1             : in std_logic;
+  SCIENCH2             : in std_logic;
+  SCIENCH3             : in std_logic;
+  SCIRD                : in std_logic;
+  SCISELAUX             : in std_logic;
+  SCISELCH0             : in std_logic;
+  SCISELCH1             : in std_logic;
+  SCISELCH2             : in std_logic;
+  SCISELCH3             : in std_logic;
+  SCIWDATA0             : in std_logic;
+  SCIWDATA1             : in std_logic;
+  SCIWDATA2             : in std_logic;
+  SCIWDATA3             : in std_logic;
+  SCIWDATA4             : in std_logic;
+  SCIWDATA5             : in std_logic;
+  SCIWDATA6             : in std_logic;
+  SCIWDATA7             : in std_logic;
+  SCIWSTN               : in std_logic;
+  REFCLK_FROM_NQ        : in std_logic;
+
+  HDOUTN0             : out std_logic;
+  HDOUTN1             : out std_logic;
+  HDOUTN2             : out std_logic;
+  HDOUTN3             : out std_logic;
+  HDOUTP0             : out std_logic;
+  HDOUTP1             : out std_logic;
+  HDOUTP2             : out std_logic;
+  HDOUTP3             : out std_logic;
+  COUT0             : out std_logic;
+  COUT1             : out std_logic;
+  COUT2             : out std_logic;
+  COUT3             : out std_logic;
+  COUT4             : out std_logic;
+  COUT5             : out std_logic;
+  COUT6             : out std_logic;
+  COUT7             : out std_logic;
+  COUT8             : out std_logic;
+  COUT9             : out std_logic;
+  COUT10             : out std_logic;
+  COUT11             : out std_logic;
+  COUT12             : out std_logic;
+  COUT13             : out std_logic;
+  COUT14             : out std_logic;
+  COUT15             : out std_logic;
+  COUT16             : out std_logic;
+  COUT17             : out std_logic;
+  COUT18             : out std_logic;
+  COUT19             : out std_logic;
+  FF_RX_D_0_0             : out std_logic;
+  FF_RX_D_0_1             : out std_logic;
+  FF_RX_D_0_2             : out std_logic;
+  FF_RX_D_0_3             : out std_logic;
+  FF_RX_D_0_4             : out std_logic;
+  FF_RX_D_0_5             : out std_logic;
+  FF_RX_D_0_6             : out std_logic;
+  FF_RX_D_0_7             : out std_logic;
+  FF_RX_D_0_8             : out std_logic;
+  FF_RX_D_0_9             : out std_logic;
+  FF_RX_D_0_10             : out std_logic;
+  FF_RX_D_0_11             : out std_logic;
+  FF_RX_D_0_12             : out std_logic;
+  FF_RX_D_0_13             : out std_logic;
+  FF_RX_D_0_14             : out std_logic;
+  FF_RX_D_0_15             : out std_logic;
+  FF_RX_D_0_16             : out std_logic;
+  FF_RX_D_0_17             : out std_logic;
+  FF_RX_D_0_18             : out std_logic;
+  FF_RX_D_0_19             : out std_logic;
+  FF_RX_D_0_20             : out std_logic;
+  FF_RX_D_0_21             : out std_logic;
+  FF_RX_D_0_22             : out std_logic;
+  FF_RX_D_0_23             : out std_logic;
+  FF_RX_D_1_0             : out std_logic;
+  FF_RX_D_1_1             : out std_logic;
+  FF_RX_D_1_2             : out std_logic;
+  FF_RX_D_1_3             : out std_logic;
+  FF_RX_D_1_4             : out std_logic;
+  FF_RX_D_1_5             : out std_logic;
+  FF_RX_D_1_6             : out std_logic;
+  FF_RX_D_1_7             : out std_logic;
+  FF_RX_D_1_8             : out std_logic;
+  FF_RX_D_1_9             : out std_logic;
+  FF_RX_D_1_10             : out std_logic;
+  FF_RX_D_1_11             : out std_logic;
+  FF_RX_D_1_12             : out std_logic;
+  FF_RX_D_1_13             : out std_logic;
+  FF_RX_D_1_14             : out std_logic;
+  FF_RX_D_1_15             : out std_logic;
+  FF_RX_D_1_16             : out std_logic;
+  FF_RX_D_1_17             : out std_logic;
+  FF_RX_D_1_18             : out std_logic;
+  FF_RX_D_1_19             : out std_logic;
+  FF_RX_D_1_20             : out std_logic;
+  FF_RX_D_1_21             : out std_logic;
+  FF_RX_D_1_22             : out std_logic;
+  FF_RX_D_1_23             : out std_logic;
+  FF_RX_D_2_0             : out std_logic;
+  FF_RX_D_2_1             : out std_logic;
+  FF_RX_D_2_2             : out std_logic;
+  FF_RX_D_2_3             : out std_logic;
+  FF_RX_D_2_4             : out std_logic;
+  FF_RX_D_2_5             : out std_logic;
+  FF_RX_D_2_6             : out std_logic;
+  FF_RX_D_2_7             : out std_logic;
+  FF_RX_D_2_8             : out std_logic;
+  FF_RX_D_2_9             : out std_logic;
+  FF_RX_D_2_10             : out std_logic;
+  FF_RX_D_2_11             : out std_logic;
+  FF_RX_D_2_12             : out std_logic;
+  FF_RX_D_2_13             : out std_logic;
+  FF_RX_D_2_14             : out std_logic;
+  FF_RX_D_2_15             : out std_logic;
+  FF_RX_D_2_16             : out std_logic;
+  FF_RX_D_2_17             : out std_logic;
+  FF_RX_D_2_18             : out std_logic;
+  FF_RX_D_2_19             : out std_logic;
+  FF_RX_D_2_20             : out std_logic;
+  FF_RX_D_2_21             : out std_logic;
+  FF_RX_D_2_22             : out std_logic;
+  FF_RX_D_2_23             : out std_logic;
+  FF_RX_D_3_0             : out std_logic;
+  FF_RX_D_3_1             : out std_logic;
+  FF_RX_D_3_2             : out std_logic;
+  FF_RX_D_3_3             : out std_logic;
+  FF_RX_D_3_4             : out std_logic;
+  FF_RX_D_3_5             : out std_logic;
+  FF_RX_D_3_6             : out std_logic;
+  FF_RX_D_3_7             : out std_logic;
+  FF_RX_D_3_8             : out std_logic;
+  FF_RX_D_3_9             : out std_logic;
+  FF_RX_D_3_10             : out std_logic;
+  FF_RX_D_3_11             : out std_logic;
+  FF_RX_D_3_12             : out std_logic;
+  FF_RX_D_3_13             : out std_logic;
+  FF_RX_D_3_14             : out std_logic;
+  FF_RX_D_3_15             : out std_logic;
+  FF_RX_D_3_16             : out std_logic;
+  FF_RX_D_3_17             : out std_logic;
+  FF_RX_D_3_18             : out std_logic;
+  FF_RX_D_3_19             : out std_logic;
+  FF_RX_D_3_20             : out std_logic;
+  FF_RX_D_3_21             : out std_logic;
+  FF_RX_D_3_22             : out std_logic;
+  FF_RX_D_3_23             : out std_logic;
+  FF_RX_F_CLK_0             : out std_logic;
+  FF_RX_F_CLK_1             : out std_logic;
+  FF_RX_F_CLK_2             : out std_logic;
+  FF_RX_F_CLK_3             : out std_logic;
+  FF_RX_H_CLK_0             : out std_logic;
+  FF_RX_H_CLK_1             : out std_logic;
+  FF_RX_H_CLK_2             : out std_logic;
+  FF_RX_H_CLK_3             : out std_logic;
+  FF_TX_F_CLK_0             : out std_logic;
+  FF_TX_F_CLK_1             : out std_logic;
+  FF_TX_F_CLK_2             : out std_logic;
+  FF_TX_F_CLK_3             : out std_logic;
+  FF_TX_H_CLK_0             : out std_logic;
+  FF_TX_H_CLK_1             : out std_logic;
+  FF_TX_H_CLK_2             : out std_logic;
+  FF_TX_H_CLK_3             : out std_logic;
+  FFS_CC_OVERRUN_0             : out std_logic;
+  FFS_CC_OVERRUN_1             : out std_logic;
+  FFS_CC_OVERRUN_2             : out std_logic;
+  FFS_CC_OVERRUN_3             : out std_logic;
+  FFS_CC_UNDERRUN_0             : out std_logic;
+  FFS_CC_UNDERRUN_1             : out std_logic;
+  FFS_CC_UNDERRUN_2             : out std_logic;
+  FFS_CC_UNDERRUN_3             : out std_logic;
+  FFS_LS_SYNC_STATUS_0             : out std_logic;
+  FFS_LS_SYNC_STATUS_1             : out std_logic;
+  FFS_LS_SYNC_STATUS_2             : out std_logic;
+  FFS_LS_SYNC_STATUS_3             : out std_logic;
+  FFS_CDR_TRAIN_DONE_0             : out std_logic;
+  FFS_CDR_TRAIN_DONE_1             : out std_logic;
+  FFS_CDR_TRAIN_DONE_2             : out std_logic;
+  FFS_CDR_TRAIN_DONE_3             : out std_logic;
+  FFS_PCIE_CON_0             : out std_logic;
+  FFS_PCIE_CON_1             : out std_logic;
+  FFS_PCIE_CON_2             : out std_logic;
+  FFS_PCIE_CON_3             : out std_logic;
+  FFS_PCIE_DONE_0             : out std_logic;
+  FFS_PCIE_DONE_1             : out std_logic;
+  FFS_PCIE_DONE_2             : out std_logic;
+  FFS_PCIE_DONE_3             : out std_logic;
+  FFS_PLOL             : out std_logic;
+  FFS_RLOL_0             : out std_logic;
+  FFS_RLOL_1             : out std_logic;
+  FFS_RLOL_2             : out std_logic;
+  FFS_RLOL_3             : out std_logic;
+  FFS_RLOS_HI_0             : out std_logic;
+  FFS_RLOS_HI_1             : out std_logic;
+  FFS_RLOS_HI_2             : out std_logic;
+  FFS_RLOS_HI_3             : out std_logic;
+  FFS_RLOS_LO_0             : out std_logic;
+  FFS_RLOS_LO_1             : out std_logic;
+  FFS_RLOS_LO_2             : out std_logic;
+  FFS_RLOS_LO_3             : out std_logic;
+  FFS_RXFBFIFO_ERROR_0             : out std_logic;
+  FFS_RXFBFIFO_ERROR_1             : out std_logic;
+  FFS_RXFBFIFO_ERROR_2             : out std_logic;
+  FFS_RXFBFIFO_ERROR_3             : out std_logic;
+  FFS_TXFBFIFO_ERROR_0             : out std_logic;
+  FFS_TXFBFIFO_ERROR_1             : out std_logic;
+  FFS_TXFBFIFO_ERROR_2             : out std_logic;
+  FFS_TXFBFIFO_ERROR_3             : out std_logic;
+  PCIE_PHYSTATUS_0             : out std_logic;
+  PCIE_PHYSTATUS_1             : out std_logic;
+  PCIE_PHYSTATUS_2             : out std_logic;
+  PCIE_PHYSTATUS_3             : out std_logic;
+  PCIE_RXVALID_0               : out std_logic;
+  PCIE_RXVALID_1               : out std_logic;
+  PCIE_RXVALID_2               : out std_logic;
+  PCIE_RXVALID_3               : out std_logic;
+  FFS_SKP_ADDED_0                  : out std_logic;
+  FFS_SKP_ADDED_1                  : out std_logic;
+  FFS_SKP_ADDED_2                  : out std_logic;
+  FFS_SKP_ADDED_3                  : out std_logic;
+  FFS_SKP_DELETED_0                : out std_logic;
+  FFS_SKP_DELETED_1                : out std_logic;
+  FFS_SKP_DELETED_2                : out std_logic;
+  FFS_SKP_DELETED_3                : out std_logic;
+  LDR_RX2CORE_0                    : out std_logic;
+  LDR_RX2CORE_1                    : out std_logic;
+  LDR_RX2CORE_2                    : out std_logic;
+  LDR_RX2CORE_3                    : out std_logic;
+  REFCK2CORE             : out std_logic;
+  SCIINT                : out std_logic;
+  SCIRDATA0             : out std_logic;
+  SCIRDATA1             : out std_logic;
+  SCIRDATA2             : out std_logic;
+  SCIRDATA3             : out std_logic;
+  SCIRDATA4             : out std_logic;
+  SCIRDATA5             : out std_logic;
+  SCIRDATA6             : out std_logic;
+  SCIRDATA7             : out std_logic;
+  REFCLK_TO_NQ          : out std_logic
+);
+
+end PCSD;
+
+architecture PCSD_arch of PCSD is
+
+
+component PCSD_sim
+GENERIC(
+  CONFIG_FILE : String;
+  QUAD_MODE : String;
+  CH0_CDR_SRC   : String;
+  CH1_CDR_SRC   : String;
+  CH2_CDR_SRC   : String;
+  CH3_CDR_SRC   : String;
+  PLL_SRC   : String
+  );
+port (
+  HDINN0             : in std_logic;
+  HDINN1             : in std_logic;
+  HDINN2             : in std_logic;
+  HDINN3             : in std_logic;
+  HDINP0             : in std_logic;
+  HDINP1             : in std_logic;
+  HDINP2             : in std_logic;
+  HDINP3             : in std_logic;
+  REFCLKN             : in std_logic;
+  REFCLKP             : in std_logic;
+  CIN0             : in std_logic;
+  CIN1             : in std_logic;
+  CIN2             : in std_logic;
+  CIN3             : in std_logic;
+  CIN4             : in std_logic;
+  CIN5             : in std_logic;
+  CIN6             : in std_logic;
+  CIN7             : in std_logic;
+  CIN8             : in std_logic;
+  CIN9             : in std_logic;
+  CIN10             : in std_logic;
+  CIN11             : in std_logic;
+  CYAWSTN             : in std_logic;
+  FF_EBRD_CLK_0             : in std_logic;
+  FF_EBRD_CLK_1             : in std_logic;
+  FF_EBRD_CLK_2             : in std_logic;
+  FF_EBRD_CLK_3             : in std_logic;
+  FF_RXI_CLK_0             : in std_logic;
+  FF_RXI_CLK_1             : in std_logic;
+  FF_RXI_CLK_2             : in std_logic;
+  FF_RXI_CLK_3             : in std_logic;
+  FF_TX_D_0_0             : in std_logic;
+  FF_TX_D_0_1             : in std_logic;
+  FF_TX_D_0_2             : in std_logic;
+  FF_TX_D_0_3             : in std_logic;
+  FF_TX_D_0_4             : in std_logic;
+  FF_TX_D_0_5             : in std_logic;
+  FF_TX_D_0_6             : in std_logic;
+  FF_TX_D_0_7             : in std_logic;
+  FF_TX_D_0_8             : in std_logic;
+  FF_TX_D_0_9             : in std_logic;
+  FF_TX_D_0_10             : in std_logic;
+  FF_TX_D_0_11             : in std_logic;
+  FF_TX_D_0_12             : in std_logic;
+  FF_TX_D_0_13             : in std_logic;
+  FF_TX_D_0_14             : in std_logic;
+  FF_TX_D_0_15             : in std_logic;
+  FF_TX_D_0_16             : in std_logic;
+  FF_TX_D_0_17             : in std_logic;
+  FF_TX_D_0_18             : in std_logic;
+  FF_TX_D_0_19             : in std_logic;
+  FF_TX_D_0_20             : in std_logic;
+  FF_TX_D_0_21             : in std_logic;
+  FF_TX_D_0_22             : in std_logic;
+  FF_TX_D_0_23             : in std_logic;
+  FF_TX_D_1_0             : in std_logic;
+  FF_TX_D_1_1             : in std_logic;
+  FF_TX_D_1_2             : in std_logic;
+  FF_TX_D_1_3             : in std_logic;
+  FF_TX_D_1_4             : in std_logic;
+  FF_TX_D_1_5             : in std_logic;
+  FF_TX_D_1_6             : in std_logic;
+  FF_TX_D_1_7             : in std_logic;
+  FF_TX_D_1_8             : in std_logic;
+  FF_TX_D_1_9             : in std_logic;
+  FF_TX_D_1_10             : in std_logic;
+  FF_TX_D_1_11             : in std_logic;
+  FF_TX_D_1_12             : in std_logic;
+  FF_TX_D_1_13             : in std_logic;
+  FF_TX_D_1_14             : in std_logic;
+  FF_TX_D_1_15             : in std_logic;
+  FF_TX_D_1_16             : in std_logic;
+  FF_TX_D_1_17             : in std_logic;
+  FF_TX_D_1_18             : in std_logic;
+  FF_TX_D_1_19             : in std_logic;
+  FF_TX_D_1_20             : in std_logic;
+  FF_TX_D_1_21             : in std_logic;
+  FF_TX_D_1_22             : in std_logic;
+  FF_TX_D_1_23             : in std_logic;
+  FF_TX_D_2_0             : in std_logic;
+  FF_TX_D_2_1             : in std_logic;
+  FF_TX_D_2_2             : in std_logic;
+  FF_TX_D_2_3             : in std_logic;
+  FF_TX_D_2_4             : in std_logic;
+  FF_TX_D_2_5             : in std_logic;
+  FF_TX_D_2_6             : in std_logic;
+  FF_TX_D_2_7             : in std_logic;
+  FF_TX_D_2_8             : in std_logic;
+  FF_TX_D_2_9             : in std_logic;
+  FF_TX_D_2_10             : in std_logic;
+  FF_TX_D_2_11             : in std_logic;
+  FF_TX_D_2_12             : in std_logic;
+  FF_TX_D_2_13             : in std_logic;
+  FF_TX_D_2_14             : in std_logic;
+  FF_TX_D_2_15             : in std_logic;
+  FF_TX_D_2_16             : in std_logic;
+  FF_TX_D_2_17             : in std_logic;
+  FF_TX_D_2_18             : in std_logic;
+  FF_TX_D_2_19             : in std_logic;
+  FF_TX_D_2_20             : in std_logic;
+  FF_TX_D_2_21             : in std_logic;
+  FF_TX_D_2_22             : in std_logic;
+  FF_TX_D_2_23             : in std_logic;
+  FF_TX_D_3_0             : in std_logic;
+  FF_TX_D_3_1             : in std_logic;
+  FF_TX_D_3_2             : in std_logic;
+  FF_TX_D_3_3             : in std_logic;
+  FF_TX_D_3_4             : in std_logic;
+  FF_TX_D_3_5             : in std_logic;
+  FF_TX_D_3_6             : in std_logic;
+  FF_TX_D_3_7             : in std_logic;
+  FF_TX_D_3_8             : in std_logic;
+  FF_TX_D_3_9             : in std_logic;
+  FF_TX_D_3_10             : in std_logic;
+  FF_TX_D_3_11             : in std_logic;
+  FF_TX_D_3_12             : in std_logic;
+  FF_TX_D_3_13             : in std_logic;
+  FF_TX_D_3_14             : in std_logic;
+  FF_TX_D_3_15             : in std_logic;
+  FF_TX_D_3_16             : in std_logic;
+  FF_TX_D_3_17             : in std_logic;
+  FF_TX_D_3_18             : in std_logic;
+  FF_TX_D_3_19             : in std_logic;
+  FF_TX_D_3_20             : in std_logic;
+  FF_TX_D_3_21             : in std_logic;
+  FF_TX_D_3_22             : in std_logic;
+  FF_TX_D_3_23             : in std_logic;
+  FF_TXI_CLK_0             : in std_logic;
+  FF_TXI_CLK_1             : in std_logic;
+  FF_TXI_CLK_2             : in std_logic;
+  FF_TXI_CLK_3             : in std_logic;
+  FFC_CK_CORE_RX_0         : in std_logic;
+  FFC_CK_CORE_RX_1         : in std_logic;
+  FFC_CK_CORE_RX_2         : in std_logic;
+  FFC_CK_CORE_RX_3         : in std_logic;
+  FFC_CK_CORE_TX           : in std_logic;
+  FFC_EI_EN_0             : in std_logic;
+  FFC_EI_EN_1             : in std_logic;
+  FFC_EI_EN_2             : in std_logic;
+  FFC_EI_EN_3             : in std_logic;
+  FFC_ENABLE_CGALIGN_0             : in std_logic;
+  FFC_ENABLE_CGALIGN_1             : in std_logic;
+  FFC_ENABLE_CGALIGN_2             : in std_logic;
+  FFC_ENABLE_CGALIGN_3             : in std_logic;
+  FFC_FB_LOOPBACK_0             : in std_logic;
+  FFC_FB_LOOPBACK_1             : in std_logic;
+  FFC_FB_LOOPBACK_2             : in std_logic;
+  FFC_FB_LOOPBACK_3             : in std_logic;
+  FFC_LANE_RX_RST_0             : in std_logic;
+  FFC_LANE_RX_RST_1             : in std_logic;
+  FFC_LANE_RX_RST_2             : in std_logic;
+  FFC_LANE_RX_RST_3             : in std_logic;
+  FFC_LANE_TX_RST_0             : in std_logic;
+  FFC_LANE_TX_RST_1             : in std_logic;
+  FFC_LANE_TX_RST_2             : in std_logic;
+  FFC_LANE_TX_RST_3             : in std_logic;
+  FFC_MACRO_RST             : in std_logic;
+  FFC_PCI_DET_EN_0             : in std_logic;
+  FFC_PCI_DET_EN_1             : in std_logic;
+  FFC_PCI_DET_EN_2             : in std_logic;
+  FFC_PCI_DET_EN_3             : in std_logic;
+  FFC_PCIE_CT_0             : in std_logic;
+  FFC_PCIE_CT_1             : in std_logic;
+  FFC_PCIE_CT_2             : in std_logic;
+  FFC_PCIE_CT_3             : in std_logic;
+  FFC_PFIFO_CLR_0             : in std_logic;
+  FFC_PFIFO_CLR_1             : in std_logic;
+  FFC_PFIFO_CLR_2             : in std_logic;
+  FFC_PFIFO_CLR_3             : in std_logic;
+  FFC_QUAD_RST             : in std_logic;
+  FFC_RRST_0             : in std_logic;
+  FFC_RRST_1             : in std_logic;
+  FFC_RRST_2             : in std_logic;
+  FFC_RRST_3             : in std_logic;
+  FFC_RXPWDNB_0             : in std_logic;
+  FFC_RXPWDNB_1             : in std_logic;
+  FFC_RXPWDNB_2             : in std_logic;
+  FFC_RXPWDNB_3             : in std_logic;
+  FFC_SB_INV_RX_0             : in std_logic;
+  FFC_SB_INV_RX_1             : in std_logic;
+  FFC_SB_INV_RX_2             : in std_logic;
+  FFC_SB_INV_RX_3             : in std_logic;
+  FFC_SB_PFIFO_LP_0             : in std_logic;
+  FFC_SB_PFIFO_LP_1             : in std_logic;
+  FFC_SB_PFIFO_LP_2             : in std_logic;
+  FFC_SB_PFIFO_LP_3             : in std_logic;
+  FFC_SIGNAL_DETECT_0             : in std_logic;
+  FFC_SIGNAL_DETECT_1             : in std_logic;
+  FFC_SIGNAL_DETECT_2             : in std_logic;
+  FFC_SIGNAL_DETECT_3             : in std_logic;
+  FFC_SYNC_TOGGLE             : in std_logic;
+  FFC_TRST             : in std_logic;
+  FFC_TXPWDNB_0             : in std_logic;
+  FFC_TXPWDNB_1             : in std_logic;
+  FFC_TXPWDNB_2             : in std_logic;
+  FFC_TXPWDNB_3             : in std_logic;
+  FFC_RATE_MODE_RX_0        : in std_logic;
+  FFC_RATE_MODE_RX_1        : in std_logic;
+  FFC_RATE_MODE_RX_2        : in std_logic;
+  FFC_RATE_MODE_RX_3        : in std_logic;
+  FFC_RATE_MODE_TX_0        : in std_logic;
+  FFC_RATE_MODE_TX_1        : in std_logic;
+  FFC_RATE_MODE_TX_2        : in std_logic;
+  FFC_RATE_MODE_TX_3        : in std_logic;
+  FFC_DIV11_MODE_RX_0       : in std_logic;
+  FFC_DIV11_MODE_RX_1       : in std_logic;
+  FFC_DIV11_MODE_RX_2       : in std_logic;
+  FFC_DIV11_MODE_RX_3       : in std_logic;
+  FFC_DIV11_MODE_TX_0       : in std_logic;
+  FFC_DIV11_MODE_TX_1       : in std_logic;
+  FFC_DIV11_MODE_TX_2       : in std_logic;
+  FFC_DIV11_MODE_TX_3       : in std_logic;
+  LDR_CORE2TX_0             : in std_logic;
+  LDR_CORE2TX_1             : in std_logic;
+  LDR_CORE2TX_2             : in std_logic;
+  LDR_CORE2TX_3             : in std_logic;
+  FFC_LDR_CORE2TX_EN_0      : in std_logic;
+  FFC_LDR_CORE2TX_EN_1      : in std_logic;
+  FFC_LDR_CORE2TX_EN_2      : in std_logic;
+  FFC_LDR_CORE2TX_EN_3      : in std_logic;
+  PCIE_POWERDOWN_0_0      : in std_logic;
+  PCIE_POWERDOWN_0_1      : in std_logic;
+  PCIE_POWERDOWN_1_0      : in std_logic;
+  PCIE_POWERDOWN_1_1      : in std_logic;
+  PCIE_POWERDOWN_2_0      : in std_logic;
+  PCIE_POWERDOWN_2_1      : in std_logic;
+  PCIE_POWERDOWN_3_0      : in std_logic;
+  PCIE_POWERDOWN_3_1      : in std_logic;
+  PCIE_RXPOLARITY_0         : in std_logic;
+  PCIE_RXPOLARITY_1         : in std_logic;
+  PCIE_RXPOLARITY_2         : in std_logic;
+  PCIE_RXPOLARITY_3         : in std_logic;
+  PCIE_TXCOMPLIANCE_0       : in std_logic;
+  PCIE_TXCOMPLIANCE_1       : in std_logic;
+  PCIE_TXCOMPLIANCE_2       : in std_logic;
+  PCIE_TXCOMPLIANCE_3       : in std_logic;
+  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
+  SCIADDR0             : in std_logic;
+  SCIADDR1             : in std_logic;
+  SCIADDR2             : in std_logic;
+  SCIADDR3             : in std_logic;
+  SCIADDR4             : in std_logic;
+  SCIADDR5             : in std_logic;
+  SCIENAUX             : in std_logic;
+  SCIENCH0             : in std_logic;
+  SCIENCH1             : in std_logic;
+  SCIENCH2             : in std_logic;
+  SCIENCH3             : in std_logic;
+  SCIRD                : in std_logic;
+  SCISELAUX             : in std_logic;
+  SCISELCH0             : in std_logic;
+  SCISELCH1             : in std_logic;
+  SCISELCH2             : in std_logic;
+  SCISELCH3             : in std_logic;
+  SCIWDATA0             : in std_logic;
+  SCIWDATA1             : in std_logic;
+  SCIWDATA2             : in std_logic;
+  SCIWDATA3             : in std_logic;
+  SCIWDATA4             : in std_logic;
+  SCIWDATA5             : in std_logic;
+  SCIWDATA6             : in std_logic;
+  SCIWDATA7             : in std_logic;
+  SCIWSTN               : in std_logic;
+  REFCLK_FROM_NQ        : in std_logic;
+
+  HDOUTN0             : out std_logic;
+  HDOUTN1             : out std_logic;
+  HDOUTN2             : out std_logic;
+  HDOUTN3             : out std_logic;
+  HDOUTP0             : out std_logic;
+  HDOUTP1             : out std_logic;
+  HDOUTP2             : out std_logic;
+  HDOUTP3             : out std_logic;
+  COUT0             : out std_logic;
+  COUT1             : out std_logic;
+  COUT2             : out std_logic;
+  COUT3             : out std_logic;
+  COUT4             : out std_logic;
+  COUT5             : out std_logic;
+  COUT6             : out std_logic;
+  COUT7             : out std_logic;
+  COUT8             : out std_logic;
+  COUT9             : out std_logic;
+  COUT10             : out std_logic;
+  COUT11             : out std_logic;
+  COUT12             : out std_logic;
+  COUT13             : out std_logic;
+  COUT14             : out std_logic;
+  COUT15             : out std_logic;
+  COUT16             : out std_logic;
+  COUT17             : out std_logic;
+  COUT18             : out std_logic;
+  COUT19             : out std_logic;
+  FF_RX_D_0_0             : out std_logic;
+  FF_RX_D_0_1             : out std_logic;
+  FF_RX_D_0_2             : out std_logic;
+  FF_RX_D_0_3             : out std_logic;
+  FF_RX_D_0_4             : out std_logic;
+  FF_RX_D_0_5             : out std_logic;
+  FF_RX_D_0_6             : out std_logic;
+  FF_RX_D_0_7             : out std_logic;
+  FF_RX_D_0_8             : out std_logic;
+  FF_RX_D_0_9             : out std_logic;
+  FF_RX_D_0_10             : out std_logic;
+  FF_RX_D_0_11             : out std_logic;
+  FF_RX_D_0_12             : out std_logic;
+  FF_RX_D_0_13             : out std_logic;
+  FF_RX_D_0_14             : out std_logic;
+  FF_RX_D_0_15             : out std_logic;
+  FF_RX_D_0_16             : out std_logic;
+  FF_RX_D_0_17             : out std_logic;
+  FF_RX_D_0_18             : out std_logic;
+  FF_RX_D_0_19             : out std_logic;
+  FF_RX_D_0_20             : out std_logic;
+  FF_RX_D_0_21             : out std_logic;
+  FF_RX_D_0_22             : out std_logic;
+  FF_RX_D_0_23             : out std_logic;
+  FF_RX_D_1_0             : out std_logic;
+  FF_RX_D_1_1             : out std_logic;
+  FF_RX_D_1_2             : out std_logic;
+  FF_RX_D_1_3             : out std_logic;
+  FF_RX_D_1_4             : out std_logic;
+  FF_RX_D_1_5             : out std_logic;
+  FF_RX_D_1_6             : out std_logic;
+  FF_RX_D_1_7             : out std_logic;
+  FF_RX_D_1_8             : out std_logic;
+  FF_RX_D_1_9             : out std_logic;
+  FF_RX_D_1_10             : out std_logic;
+  FF_RX_D_1_11             : out std_logic;
+  FF_RX_D_1_12             : out std_logic;
+  FF_RX_D_1_13             : out std_logic;
+  FF_RX_D_1_14             : out std_logic;
+  FF_RX_D_1_15             : out std_logic;
+  FF_RX_D_1_16             : out std_logic;
+  FF_RX_D_1_17             : out std_logic;
+  FF_RX_D_1_18             : out std_logic;
+  FF_RX_D_1_19             : out std_logic;
+  FF_RX_D_1_20             : out std_logic;
+  FF_RX_D_1_21             : out std_logic;
+  FF_RX_D_1_22             : out std_logic;
+  FF_RX_D_1_23             : out std_logic;
+  FF_RX_D_2_0             : out std_logic;
+  FF_RX_D_2_1             : out std_logic;
+  FF_RX_D_2_2             : out std_logic;
+  FF_RX_D_2_3             : out std_logic;
+  FF_RX_D_2_4             : out std_logic;
+  FF_RX_D_2_5             : out std_logic;
+  FF_RX_D_2_6             : out std_logic;
+  FF_RX_D_2_7             : out std_logic;
+  FF_RX_D_2_8             : out std_logic;
+  FF_RX_D_2_9             : out std_logic;
+  FF_RX_D_2_10             : out std_logic;
+  FF_RX_D_2_11             : out std_logic;
+  FF_RX_D_2_12             : out std_logic;
+  FF_RX_D_2_13             : out std_logic;
+  FF_RX_D_2_14             : out std_logic;
+  FF_RX_D_2_15             : out std_logic;
+  FF_RX_D_2_16             : out std_logic;
+  FF_RX_D_2_17             : out std_logic;
+  FF_RX_D_2_18             : out std_logic;
+  FF_RX_D_2_19             : out std_logic;
+  FF_RX_D_2_20             : out std_logic;
+  FF_RX_D_2_21             : out std_logic;
+  FF_RX_D_2_22             : out std_logic;
+  FF_RX_D_2_23             : out std_logic;
+  FF_RX_D_3_0             : out std_logic;
+  FF_RX_D_3_1             : out std_logic;
+  FF_RX_D_3_2             : out std_logic;
+  FF_RX_D_3_3             : out std_logic;
+  FF_RX_D_3_4             : out std_logic;
+  FF_RX_D_3_5             : out std_logic;
+  FF_RX_D_3_6             : out std_logic;
+  FF_RX_D_3_7             : out std_logic;
+  FF_RX_D_3_8             : out std_logic;
+  FF_RX_D_3_9             : out std_logic;
+  FF_RX_D_3_10             : out std_logic;
+  FF_RX_D_3_11             : out std_logic;
+  FF_RX_D_3_12             : out std_logic;
+  FF_RX_D_3_13             : out std_logic;
+  FF_RX_D_3_14             : out std_logic;
+  FF_RX_D_3_15             : out std_logic;
+  FF_RX_D_3_16             : out std_logic;
+  FF_RX_D_3_17             : out std_logic;
+  FF_RX_D_3_18             : out std_logic;
+  FF_RX_D_3_19             : out std_logic;
+  FF_RX_D_3_20             : out std_logic;
+  FF_RX_D_3_21             : out std_logic;
+  FF_RX_D_3_22             : out std_logic;
+  FF_RX_D_3_23             : out std_logic;
+  FF_RX_F_CLK_0             : out std_logic;
+  FF_RX_F_CLK_1             : out std_logic;
+  FF_RX_F_CLK_2             : out std_logic;
+  FF_RX_F_CLK_3             : out std_logic;
+  FF_RX_H_CLK_0             : out std_logic;
+  FF_RX_H_CLK_1             : out std_logic;
+  FF_RX_H_CLK_2             : out std_logic;
+  FF_RX_H_CLK_3             : out std_logic;
+  FF_TX_F_CLK_0             : out std_logic;
+  FF_TX_F_CLK_1             : out std_logic;
+  FF_TX_F_CLK_2             : out std_logic;
+  FF_TX_F_CLK_3             : out std_logic;
+  FF_TX_H_CLK_0             : out std_logic;
+  FF_TX_H_CLK_1             : out std_logic;
+  FF_TX_H_CLK_2             : out std_logic;
+  FF_TX_H_CLK_3             : out std_logic;
+  FFS_CC_OVERRUN_0             : out std_logic;
+  FFS_CC_OVERRUN_1             : out std_logic;
+  FFS_CC_OVERRUN_2             : out std_logic;
+  FFS_CC_OVERRUN_3             : out std_logic;
+  FFS_CC_UNDERRUN_0             : out std_logic;
+  FFS_CC_UNDERRUN_1             : out std_logic;
+  FFS_CC_UNDERRUN_2             : out std_logic;
+  FFS_CC_UNDERRUN_3             : out std_logic;
+  FFS_LS_SYNC_STATUS_0             : out std_logic;
+  FFS_LS_SYNC_STATUS_1             : out std_logic;
+  FFS_LS_SYNC_STATUS_2             : out std_logic;
+  FFS_LS_SYNC_STATUS_3             : out std_logic;
+  FFS_CDR_TRAIN_DONE_0             : out std_logic;
+  FFS_CDR_TRAIN_DONE_1             : out std_logic;
+  FFS_CDR_TRAIN_DONE_2             : out std_logic;
+  FFS_CDR_TRAIN_DONE_3             : out std_logic;
+  FFS_PCIE_CON_0             : out std_logic;
+  FFS_PCIE_CON_1             : out std_logic;
+  FFS_PCIE_CON_2             : out std_logic;
+  FFS_PCIE_CON_3             : out std_logic;
+  FFS_PCIE_DONE_0             : out std_logic;
+  FFS_PCIE_DONE_1             : out std_logic;
+  FFS_PCIE_DONE_2             : out std_logic;
+  FFS_PCIE_DONE_3             : out std_logic;
+  FFS_PLOL             : out std_logic;
+  FFS_RLOL_0             : out std_logic;
+  FFS_RLOL_1             : out std_logic;
+  FFS_RLOL_2             : out std_logic;
+  FFS_RLOL_3             : out std_logic;
+  FFS_RLOS_HI_0             : out std_logic;
+  FFS_RLOS_HI_1             : out std_logic;
+  FFS_RLOS_HI_2             : out std_logic;
+  FFS_RLOS_HI_3             : out std_logic;
+  FFS_RLOS_LO_0             : out std_logic;
+  FFS_RLOS_LO_1             : out std_logic;
+  FFS_RLOS_LO_2             : out std_logic;
+  FFS_RLOS_LO_3             : out std_logic;
+  FFS_RXFBFIFO_ERROR_0             : out std_logic;
+  FFS_RXFBFIFO_ERROR_1             : out std_logic;
+  FFS_RXFBFIFO_ERROR_2             : out std_logic;
+  FFS_RXFBFIFO_ERROR_3             : out std_logic;
+  FFS_TXFBFIFO_ERROR_0             : out std_logic;
+  FFS_TXFBFIFO_ERROR_1             : out std_logic;
+  FFS_TXFBFIFO_ERROR_2             : out std_logic;
+  FFS_TXFBFIFO_ERROR_3             : out std_logic;
+  PCIE_PHYSTATUS_0             : out std_logic;
+  PCIE_PHYSTATUS_1             : out std_logic;
+  PCIE_PHYSTATUS_2             : out std_logic;
+  PCIE_PHYSTATUS_3             : out std_logic;
+  PCIE_RXVALID_0               : out std_logic;
+  PCIE_RXVALID_1               : out std_logic;
+  PCIE_RXVALID_2               : out std_logic;
+  PCIE_RXVALID_3               : out std_logic;
+  FFS_SKP_ADDED_0                  : out std_logic;
+  FFS_SKP_ADDED_1                  : out std_logic;
+  FFS_SKP_ADDED_2                  : out std_logic;
+  FFS_SKP_ADDED_3                  : out std_logic;
+  FFS_SKP_DELETED_0                : out std_logic;
+  FFS_SKP_DELETED_1                : out std_logic;
+  FFS_SKP_DELETED_2                : out std_logic;
+  FFS_SKP_DELETED_3                : out std_logic;
+  LDR_RX2CORE_0                    : out std_logic;
+  LDR_RX2CORE_1                    : out std_logic;
+  LDR_RX2CORE_2                    : out std_logic;
+  LDR_RX2CORE_3                    : out std_logic;
+  REFCK2CORE             : out std_logic;
+  SCIINT                : out std_logic;
+  SCIRDATA0             : out std_logic;
+  SCIRDATA1             : out std_logic;
+  SCIRDATA2             : out std_logic;
+  SCIRDATA3             : out std_logic;
+  SCIRDATA4             : out std_logic;
+  SCIRDATA5             : out std_logic;
+  SCIRDATA6             : out std_logic;
+  SCIRDATA7             : out std_logic;
+  REFCLK_TO_NQ          : out std_logic
+);
+end component;
+
+begin
+
+PCSD_sim_inst : PCSD_sim
+generic map (
+  CONFIG_FILE => CONFIG_FILE,
+  QUAD_MODE => QUAD_MODE,
+  CH0_CDR_SRC => CH0_CDR_SRC,
+  CH1_CDR_SRC => CH1_CDR_SRC,
+  CH2_CDR_SRC => CH2_CDR_SRC,
+  CH3_CDR_SRC => CH3_CDR_SRC,
+  PLL_SRC => PLL_SRC
+  )
+port map (
+   HDINN0 => HDINN0,
+   HDINN1 => HDINN1,
+   HDINN2 => HDINN2,
+   HDINN3 => HDINN3,
+   HDINP0 => HDINP0,
+   HDINP1 => HDINP1,
+   HDINP2 => HDINP2,
+   HDINP3 => HDINP3,
+   REFCLKN => REFCLKN,
+   REFCLKP => REFCLKP,
+   CIN11 => CIN11,
+   CIN10 => CIN10,
+   CIN9 => CIN9,
+   CIN8 => CIN8,
+   CIN7 => CIN7,
+   CIN6 => CIN6,
+   CIN5 => CIN5,
+   CIN4 => CIN4,
+   CIN3 => CIN3,
+   CIN2 => CIN2,
+   CIN1 => CIN1,
+   CIN0 => CIN0,
+   CYAWSTN => CYAWSTN,
+   FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
+   FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
+   FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
+   FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
+   FF_RXI_CLK_3 => FF_RXI_CLK_3,
+   FF_RXI_CLK_2 => FF_RXI_CLK_2,
+   FF_RXI_CLK_1 => FF_RXI_CLK_1,
+   FF_RXI_CLK_0 => FF_RXI_CLK_0,
+   FF_TX_D_0_0 => FF_TX_D_0_0,
+   FF_TX_D_0_1 => FF_TX_D_0_1,
+   FF_TX_D_0_2 => FF_TX_D_0_2,
+   FF_TX_D_0_3 => FF_TX_D_0_3,
+   FF_TX_D_0_4 => FF_TX_D_0_4,
+   FF_TX_D_0_5 => FF_TX_D_0_5,
+   FF_TX_D_0_6 => FF_TX_D_0_6,
+   FF_TX_D_0_7 => FF_TX_D_0_7,
+   FF_TX_D_0_8 => FF_TX_D_0_8,
+   FF_TX_D_0_9 => FF_TX_D_0_9,
+   FF_TX_D_0_10 => FF_TX_D_0_10,
+   FF_TX_D_0_11 => FF_TX_D_0_11,
+   FF_TX_D_0_12 => FF_TX_D_0_12,
+   FF_TX_D_0_13 => FF_TX_D_0_13,
+   FF_TX_D_0_14 => FF_TX_D_0_14,
+   FF_TX_D_0_15 => FF_TX_D_0_15,
+   FF_TX_D_0_16 => FF_TX_D_0_16,
+   FF_TX_D_0_17 => FF_TX_D_0_17,
+   FF_TX_D_0_18 => FF_TX_D_0_18,
+   FF_TX_D_0_19 => FF_TX_D_0_19,
+   FF_TX_D_0_20 => FF_TX_D_0_20,
+   FF_TX_D_0_21 => FF_TX_D_0_21,
+   FF_TX_D_0_22 => FF_TX_D_0_22,
+   FF_TX_D_0_23 => FF_TX_D_0_23,
+   FF_TX_D_1_0 => FF_TX_D_1_0,
+   FF_TX_D_1_1 => FF_TX_D_1_1,
+   FF_TX_D_1_2 => FF_TX_D_1_2,
+   FF_TX_D_1_3 => FF_TX_D_1_3,
+   FF_TX_D_1_4 => FF_TX_D_1_4,
+   FF_TX_D_1_5 => FF_TX_D_1_5,
+   FF_TX_D_1_6 => FF_TX_D_1_6,
+   FF_TX_D_1_7 => FF_TX_D_1_7,
+   FF_TX_D_1_8 => FF_TX_D_1_8,
+   FF_TX_D_1_9 => FF_TX_D_1_9,
+   FF_TX_D_1_10 => FF_TX_D_1_10,
+   FF_TX_D_1_11 => FF_TX_D_1_11,
+   FF_TX_D_1_12 => FF_TX_D_1_12,
+   FF_TX_D_1_13 => FF_TX_D_1_13,
+   FF_TX_D_1_14 => FF_TX_D_1_14,
+   FF_TX_D_1_15 => FF_TX_D_1_15,
+   FF_TX_D_1_16 => FF_TX_D_1_16,
+   FF_TX_D_1_17 => FF_TX_D_1_17,
+   FF_TX_D_1_18 => FF_TX_D_1_18,
+   FF_TX_D_1_19 => FF_TX_D_1_19,
+   FF_TX_D_1_20 => FF_TX_D_1_20,
+   FF_TX_D_1_21 => FF_TX_D_1_21,
+   FF_TX_D_1_22 => FF_TX_D_1_22,
+   FF_TX_D_1_23 => FF_TX_D_1_23,
+   FF_TX_D_2_0 => FF_TX_D_2_0,
+   FF_TX_D_2_1 => FF_TX_D_2_1,
+   FF_TX_D_2_2 => FF_TX_D_2_2,
+   FF_TX_D_2_3 => FF_TX_D_2_3,
+   FF_TX_D_2_4 => FF_TX_D_2_4,
+   FF_TX_D_2_5 => FF_TX_D_2_5,
+   FF_TX_D_2_6 => FF_TX_D_2_6,
+   FF_TX_D_2_7 => FF_TX_D_2_7,
+   FF_TX_D_2_8 => FF_TX_D_2_8,
+   FF_TX_D_2_9 => FF_TX_D_2_9,
+   FF_TX_D_2_10 => FF_TX_D_2_10,
+   FF_TX_D_2_11 => FF_TX_D_2_11,
+   FF_TX_D_2_12 => FF_TX_D_2_12,
+   FF_TX_D_2_13 => FF_TX_D_2_13,
+   FF_TX_D_2_14 => FF_TX_D_2_14,
+   FF_TX_D_2_15 => FF_TX_D_2_15,
+   FF_TX_D_2_16 => FF_TX_D_2_16,
+   FF_TX_D_2_17 => FF_TX_D_2_17,
+   FF_TX_D_2_18 => FF_TX_D_2_18,
+   FF_TX_D_2_19 => FF_TX_D_2_19,
+   FF_TX_D_2_20 => FF_TX_D_2_20,
+   FF_TX_D_2_21 => FF_TX_D_2_21,
+   FF_TX_D_2_22 => FF_TX_D_2_22,
+   FF_TX_D_2_23 => FF_TX_D_2_23,
+   FF_TX_D_3_0 => FF_TX_D_3_0,
+   FF_TX_D_3_1 => FF_TX_D_3_1,
+   FF_TX_D_3_2 => FF_TX_D_3_2,
+   FF_TX_D_3_3 => FF_TX_D_3_3,
+   FF_TX_D_3_4 => FF_TX_D_3_4,
+   FF_TX_D_3_5 => FF_TX_D_3_5,
+   FF_TX_D_3_6 => FF_TX_D_3_6,
+   FF_TX_D_3_7 => FF_TX_D_3_7,
+   FF_TX_D_3_8 => FF_TX_D_3_8,
+   FF_TX_D_3_9 => FF_TX_D_3_9,
+   FF_TX_D_3_10 => FF_TX_D_3_10,
+   FF_TX_D_3_11 => FF_TX_D_3_11,
+   FF_TX_D_3_12 => FF_TX_D_3_12,
+   FF_TX_D_3_13 => FF_TX_D_3_13,
+   FF_TX_D_3_14 => FF_TX_D_3_14,
+   FF_TX_D_3_15 => FF_TX_D_3_15,
+   FF_TX_D_3_16 => FF_TX_D_3_16,
+   FF_TX_D_3_17 => FF_TX_D_3_17,
+   FF_TX_D_3_18 => FF_TX_D_3_18,
+   FF_TX_D_3_19 => FF_TX_D_3_19,
+   FF_TX_D_3_20 => FF_TX_D_3_20,
+   FF_TX_D_3_21 => FF_TX_D_3_21,
+   FF_TX_D_3_22 => FF_TX_D_3_22,
+   FF_TX_D_3_23 => FF_TX_D_3_23,
+   FF_TXI_CLK_0 => FF_TXI_CLK_0,
+   FF_TXI_CLK_1 => FF_TXI_CLK_1,
+   FF_TXI_CLK_2 => FF_TXI_CLK_2,
+   FF_TXI_CLK_3 => FF_TXI_CLK_3,
+   FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
+   FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
+   FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
+   FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
+   FFC_CK_CORE_TX => FFC_CK_CORE_TX,
+   FFC_EI_EN_0 => FFC_EI_EN_0,
+   FFC_EI_EN_1 => FFC_EI_EN_1,
+   FFC_EI_EN_2 => FFC_EI_EN_2,
+   FFC_EI_EN_3 => FFC_EI_EN_3,
+   FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
+   FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
+   FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
+   FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
+   FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
+   FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
+   FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
+   FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
+   FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
+   FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
+   FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
+   FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
+   FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
+   FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
+   FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
+   FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
+   FFC_MACRO_RST => FFC_MACRO_RST,
+   FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
+   FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
+   FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
+   FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
+   FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
+   FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
+   FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
+   FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
+   FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
+   FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
+   FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
+   FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
+   FFC_QUAD_RST => FFC_QUAD_RST,
+   FFC_RRST_0 => FFC_RRST_0,
+   FFC_RRST_1 => FFC_RRST_1,
+   FFC_RRST_2 => FFC_RRST_2,
+   FFC_RRST_3 => FFC_RRST_3,
+   FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
+   FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
+   FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
+   FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
+   FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
+   FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
+   FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
+   FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
+   FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
+   FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
+   FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
+   FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
+   FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
+   FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
+   FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
+   FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
+   FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
+   FFC_TRST => FFC_TRST,
+   FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
+   FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
+   FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
+   FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
+   FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
+   FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
+   FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
+   FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
+   FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
+   FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
+   FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
+   FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
+   FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
+   FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
+   FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
+   FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
+   FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
+   FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
+   FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
+   FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
+   LDR_CORE2TX_0 => LDR_CORE2TX_0,
+   LDR_CORE2TX_1 => LDR_CORE2TX_1,
+   LDR_CORE2TX_2 => LDR_CORE2TX_2,
+   LDR_CORE2TX_3 => LDR_CORE2TX_3,
+   FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
+   FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
+   FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
+   FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
+   PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
+   PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
+   PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
+   PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
+   PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
+   PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
+   PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
+   PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
+   PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
+   PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
+   PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
+   PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
+   PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
+   PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
+   PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
+   PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
+   PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
+   PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
+   PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
+   PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
+   SCIADDR0 => SCIADDR0,
+   SCIADDR1 => SCIADDR1,
+   SCIADDR2 => SCIADDR2,
+   SCIADDR3 => SCIADDR3,
+   SCIADDR4 => SCIADDR4,
+   SCIADDR5 => SCIADDR5,
+   SCIENAUX => SCIENAUX,
+   SCIENCH0 => SCIENCH0,
+   SCIENCH1 => SCIENCH1,
+   SCIENCH2 => SCIENCH2,
+   SCIENCH3 => SCIENCH3,
+   SCIRD => SCIRD,
+   SCISELAUX => SCISELAUX,
+   SCISELCH0 => SCISELCH0,
+   SCISELCH1 => SCISELCH1,
+   SCISELCH2 => SCISELCH2,
+   SCISELCH3 => SCISELCH3,
+   SCIWDATA0 => SCIWDATA0,
+   SCIWDATA1 => SCIWDATA1,
+   SCIWDATA2 => SCIWDATA2,
+   SCIWDATA3 => SCIWDATA3,
+   SCIWDATA4 => SCIWDATA4,
+   SCIWDATA5 => SCIWDATA5,
+   SCIWDATA6 => SCIWDATA6,
+   SCIWDATA7 => SCIWDATA7,
+   SCIWSTN => SCIWSTN,
+   HDOUTN0 => HDOUTN0,
+   HDOUTN1 => HDOUTN1,
+   HDOUTN2 => HDOUTN2,
+   HDOUTN3 => HDOUTN3,
+   HDOUTP0 => HDOUTP0,
+   HDOUTP1 => HDOUTP1,
+   HDOUTP2 => HDOUTP2,
+   HDOUTP3 => HDOUTP3,
+   COUT19 => COUT19,
+   COUT18 => COUT18,
+   COUT17 => COUT17,
+   COUT16 => COUT16,
+   COUT15 => COUT15,
+   COUT14 => COUT14,
+   COUT13 => COUT13,
+   COUT12 => COUT12,
+   COUT11 => COUT11,
+   COUT10 => COUT10,
+   COUT9 => COUT9,
+   COUT8 => COUT8,
+   COUT7 => COUT7,
+   COUT6 => COUT6,
+   COUT5 => COUT5,
+   COUT4 => COUT4,
+   COUT3 => COUT3,
+   COUT2 => COUT2,
+   COUT1 => COUT1,
+   COUT0 => COUT0,
+   FF_RX_D_0_0 => FF_RX_D_0_0,
+   FF_RX_D_0_1 => FF_RX_D_0_1,
+   FF_RX_D_0_2 => FF_RX_D_0_2,
+   FF_RX_D_0_3 => FF_RX_D_0_3,
+   FF_RX_D_0_4 => FF_RX_D_0_4,
+   FF_RX_D_0_5 => FF_RX_D_0_5,
+   FF_RX_D_0_6 => FF_RX_D_0_6,
+   FF_RX_D_0_7 => FF_RX_D_0_7,
+   FF_RX_D_0_8 => FF_RX_D_0_8,
+   FF_RX_D_0_9 => FF_RX_D_0_9,
+   FF_RX_D_0_10 => FF_RX_D_0_10,
+   FF_RX_D_0_11 => FF_RX_D_0_11,
+   FF_RX_D_0_12 => FF_RX_D_0_12,
+   FF_RX_D_0_13 => FF_RX_D_0_13,
+   FF_RX_D_0_14 => FF_RX_D_0_14,
+   FF_RX_D_0_15 => FF_RX_D_0_15,
+   FF_RX_D_0_16 => FF_RX_D_0_16,
+   FF_RX_D_0_17 => FF_RX_D_0_17,
+   FF_RX_D_0_18 => FF_RX_D_0_18,
+   FF_RX_D_0_19 => FF_RX_D_0_19,
+   FF_RX_D_0_20 => FF_RX_D_0_20,
+   FF_RX_D_0_21 => FF_RX_D_0_21,
+   FF_RX_D_0_22 => FF_RX_D_0_22,
+   FF_RX_D_0_23 => FF_RX_D_0_23,
+   FF_RX_D_1_0 => FF_RX_D_1_0,
+   FF_RX_D_1_1 => FF_RX_D_1_1,
+   FF_RX_D_1_2 => FF_RX_D_1_2,
+   FF_RX_D_1_3 => FF_RX_D_1_3,
+   FF_RX_D_1_4 => FF_RX_D_1_4,
+   FF_RX_D_1_5 => FF_RX_D_1_5,
+   FF_RX_D_1_6 => FF_RX_D_1_6,
+   FF_RX_D_1_7 => FF_RX_D_1_7,
+   FF_RX_D_1_8 => FF_RX_D_1_8,
+   FF_RX_D_1_9 => FF_RX_D_1_9,
+   FF_RX_D_1_10 => FF_RX_D_1_10,
+   FF_RX_D_1_11 => FF_RX_D_1_11,
+   FF_RX_D_1_12 => FF_RX_D_1_12,
+   FF_RX_D_1_13 => FF_RX_D_1_13,
+   FF_RX_D_1_14 => FF_RX_D_1_14,
+   FF_RX_D_1_15 => FF_RX_D_1_15,
+   FF_RX_D_1_16 => FF_RX_D_1_16,
+   FF_RX_D_1_17 => FF_RX_D_1_17,
+   FF_RX_D_1_18 => FF_RX_D_1_18,
+   FF_RX_D_1_19 => FF_RX_D_1_19,
+   FF_RX_D_1_20 => FF_RX_D_1_20,
+   FF_RX_D_1_21 => FF_RX_D_1_21,
+   FF_RX_D_1_22 => FF_RX_D_1_22,
+   FF_RX_D_1_23 => FF_RX_D_1_23,
+   FF_RX_D_2_0 => FF_RX_D_2_0,
+   FF_RX_D_2_1 => FF_RX_D_2_1,
+   FF_RX_D_2_2 => FF_RX_D_2_2,
+   FF_RX_D_2_3 => FF_RX_D_2_3,
+   FF_RX_D_2_4 => FF_RX_D_2_4,
+   FF_RX_D_2_5 => FF_RX_D_2_5,
+   FF_RX_D_2_6 => FF_RX_D_2_6,
+   FF_RX_D_2_7 => FF_RX_D_2_7,
+   FF_RX_D_2_8 => FF_RX_D_2_8,
+   FF_RX_D_2_9 => FF_RX_D_2_9,
+   FF_RX_D_2_10 => FF_RX_D_2_10,
+   FF_RX_D_2_11 => FF_RX_D_2_11,
+   FF_RX_D_2_12 => FF_RX_D_2_12,
+   FF_RX_D_2_13 => FF_RX_D_2_13,
+   FF_RX_D_2_14 => FF_RX_D_2_14,
+   FF_RX_D_2_15 => FF_RX_D_2_15,
+   FF_RX_D_2_16 => FF_RX_D_2_16,
+   FF_RX_D_2_17 => FF_RX_D_2_17,
+   FF_RX_D_2_18 => FF_RX_D_2_18,
+   FF_RX_D_2_19 => FF_RX_D_2_19,
+   FF_RX_D_2_20 => FF_RX_D_2_20,
+   FF_RX_D_2_21 => FF_RX_D_2_21,
+   FF_RX_D_2_22 => FF_RX_D_2_22,
+   FF_RX_D_2_23 => FF_RX_D_2_23,
+   FF_RX_D_3_0 => FF_RX_D_3_0,
+   FF_RX_D_3_1 => FF_RX_D_3_1,
+   FF_RX_D_3_2 => FF_RX_D_3_2,
+   FF_RX_D_3_3 => FF_RX_D_3_3,
+   FF_RX_D_3_4 => FF_RX_D_3_4,
+   FF_RX_D_3_5 => FF_RX_D_3_5,
+   FF_RX_D_3_6 => FF_RX_D_3_6,
+   FF_RX_D_3_7 => FF_RX_D_3_7,
+   FF_RX_D_3_8 => FF_RX_D_3_8,
+   FF_RX_D_3_9 => FF_RX_D_3_9,
+   FF_RX_D_3_10 => FF_RX_D_3_10,
+   FF_RX_D_3_11 => FF_RX_D_3_11,
+   FF_RX_D_3_12 => FF_RX_D_3_12,
+   FF_RX_D_3_13 => FF_RX_D_3_13,
+   FF_RX_D_3_14 => FF_RX_D_3_14,
+   FF_RX_D_3_15 => FF_RX_D_3_15,
+   FF_RX_D_3_16 => FF_RX_D_3_16,
+   FF_RX_D_3_17 => FF_RX_D_3_17,
+   FF_RX_D_3_18 => FF_RX_D_3_18,
+   FF_RX_D_3_19 => FF_RX_D_3_19,
+   FF_RX_D_3_20 => FF_RX_D_3_20,
+   FF_RX_D_3_21 => FF_RX_D_3_21,
+   FF_RX_D_3_22 => FF_RX_D_3_22,
+   FF_RX_D_3_23 => FF_RX_D_3_23,
+   FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
+   FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
+   FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
+   FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
+   FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
+   FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
+   FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
+   FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
+   FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
+   FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
+   FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
+   FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
+   FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
+   FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
+   FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
+   FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
+   FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
+   FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
+   FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
+   FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
+   FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
+   FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
+   FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
+   FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
+   FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
+   FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
+   FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
+   FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
+   FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
+   FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
+   FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
+   FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
+   FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
+   FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
+   FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
+   FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
+   FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
+   FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
+   FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
+   FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
+   FFS_PLOL => FFS_PLOL,
+   FFS_RLOL_0 => FFS_RLOL_0,
+   FFS_RLOL_1 => FFS_RLOL_1,
+   FFS_RLOL_2 => FFS_RLOL_2,
+   FFS_RLOL_3 => FFS_RLOL_3,
+   FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
+   FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
+   FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
+   FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
+   FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
+   FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
+   FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
+   FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
+   FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
+   FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
+   FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
+   FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
+   FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
+   FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
+   FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
+   FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
+   PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
+   PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
+   PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
+   PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
+   PCIE_RXVALID_0 => PCIE_RXVALID_0,
+   PCIE_RXVALID_1 => PCIE_RXVALID_1,
+   PCIE_RXVALID_2 => PCIE_RXVALID_2,
+   PCIE_RXVALID_3 => PCIE_RXVALID_3,
+   FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
+   FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
+   FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
+   FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
+   FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
+   FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
+   FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
+   FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
+   LDR_RX2CORE_0 => LDR_RX2CORE_0,
+   LDR_RX2CORE_1 => LDR_RX2CORE_1,
+   LDR_RX2CORE_2 => LDR_RX2CORE_2,
+   LDR_RX2CORE_3 => LDR_RX2CORE_3,
+   REFCK2CORE => REFCK2CORE,
+   SCIINT => SCIINT,
+   SCIRDATA0 => SCIRDATA0,
+   SCIRDATA1 => SCIRDATA1,
+   SCIRDATA2 => SCIRDATA2,
+   SCIRDATA3 => SCIRDATA3,
+   SCIRDATA4 => SCIRDATA4,
+   SCIRDATA5 => SCIRDATA5,
+   SCIRDATA6 => SCIRDATA6,
+   SCIRDATA7 => SCIRDATA7,
+   REFCLK_FROM_NQ => REFCLK_FROM_NQ,
+   REFCLK_TO_NQ => REFCLK_TO_NQ
+   );
+
+end PCSD_arch;
+
+--synopsys translate_on
+
+
+
+
+--synopsys translate_off
+library ECP3;
+use ECP3.components.all;
+--synopsys translate_on
+
+
+library IEEE, STD;
+use IEEE.std_logic_1164.all;
+use STD.TEXTIO.all;
+
+entity serdes_sync_160_full is
+   GENERIC (USER_CONFIG_FILE    :  String := "serdes_sync_160_full.txt");
+ port (
+------------------
+-- CH0 --
+    hdinp_ch0, hdinn_ch0    :   in std_logic;
+    hdoutp_ch0, hdoutn_ch0   :   out std_logic;
+    sci_sel_ch0    :   in std_logic;
+    rxiclk_ch0    :   in std_logic;
+    txiclk_ch0    :   in std_logic;
+    rx_full_clk_ch0   :   out std_logic;
+    rx_half_clk_ch0   :   out std_logic;
+    tx_full_clk_ch0   :   out std_logic;
+    tx_half_clk_ch0   :   out std_logic;
+    fpga_rxrefclk_ch0    :   in std_logic;
+    txdata_ch0    :   in std_logic_vector (7 downto 0);
+    tx_k_ch0    :   in std_logic;
+    tx_force_disp_ch0    :   in std_logic;
+    tx_disp_sel_ch0    :   in std_logic;
+    rxdata_ch0   :   out std_logic_vector (7 downto 0);
+    rx_k_ch0   :   out std_logic;
+    rx_disp_err_ch0   :   out std_logic;
+    rx_cv_err_ch0   :   out std_logic;
+    rx_serdes_rst_ch0_c    :   in std_logic;
+    sb_felb_ch0_c    :   in std_logic;
+    sb_felb_rst_ch0_c    :   in std_logic;
+    tx_pcs_rst_ch0_c    :   in std_logic;
+    tx_pwrup_ch0_c    :   in std_logic;
+    rx_pcs_rst_ch0_c    :   in std_logic;
+    rx_pwrup_ch0_c    :   in std_logic;
+    rx_los_low_ch0_s   :   out std_logic;
+    lsm_status_ch0_s   :   out std_logic;
+    rx_cdr_lol_ch0_s   :   out std_logic;
+    tx_div2_mode_ch0_c   : in std_logic;
+    rx_div2_mode_ch0_c   : in std_logic;
+-- CH1 --
+    hdinp_ch1, hdinn_ch1    :   in std_logic;
+    hdoutp_ch1, hdoutn_ch1   :   out std_logic;
+    sci_sel_ch1    :   in std_logic;
+    rxiclk_ch1    :   in std_logic;
+    txiclk_ch1    :   in std_logic;
+    rx_full_clk_ch1   :   out std_logic;
+    rx_half_clk_ch1   :   out std_logic;
+    tx_full_clk_ch1   :   out std_logic;
+    tx_half_clk_ch1   :   out std_logic;
+    fpga_rxrefclk_ch1    :   in std_logic;
+    txdata_ch1    :   in std_logic_vector (7 downto 0);
+    tx_k_ch1    :   in std_logic;
+    tx_force_disp_ch1    :   in std_logic;
+    tx_disp_sel_ch1    :   in std_logic;
+    rxdata_ch1   :   out std_logic_vector (7 downto 0);
+    rx_k_ch1   :   out std_logic;
+    rx_disp_err_ch1   :   out std_logic;
+    rx_cv_err_ch1   :   out std_logic;
+    rx_serdes_rst_ch1_c    :   in std_logic;
+    sb_felb_ch1_c    :   in std_logic;
+    sb_felb_rst_ch1_c    :   in std_logic;
+    tx_pcs_rst_ch1_c    :   in std_logic;
+    tx_pwrup_ch1_c    :   in std_logic;
+    rx_pcs_rst_ch1_c    :   in std_logic;
+    rx_pwrup_ch1_c    :   in std_logic;
+    rx_los_low_ch1_s   :   out std_logic;
+    lsm_status_ch1_s   :   out std_logic;
+    rx_cdr_lol_ch1_s   :   out std_logic;
+    tx_div2_mode_ch1_c   : in std_logic;
+    rx_div2_mode_ch1_c   : in std_logic;
+-- CH2 --
+    hdinp_ch2, hdinn_ch2    :   in std_logic;
+    hdoutp_ch2, hdoutn_ch2   :   out std_logic;
+    sci_sel_ch2    :   in std_logic;
+    rxiclk_ch2    :   in std_logic;
+    txiclk_ch2    :   in std_logic;
+    rx_full_clk_ch2   :   out std_logic;
+    rx_half_clk_ch2   :   out std_logic;
+    tx_full_clk_ch2   :   out std_logic;
+    tx_half_clk_ch2   :   out std_logic;
+    fpga_rxrefclk_ch2    :   in std_logic;
+    txdata_ch2    :   in std_logic_vector (7 downto 0);
+    tx_k_ch2    :   in std_logic;
+    tx_force_disp_ch2    :   in std_logic;
+    tx_disp_sel_ch2    :   in std_logic;
+    rxdata_ch2   :   out std_logic_vector (7 downto 0);
+    rx_k_ch2   :   out std_logic;
+    rx_disp_err_ch2   :   out std_logic;
+    rx_cv_err_ch2   :   out std_logic;
+    rx_serdes_rst_ch2_c    :   in std_logic;
+    sb_felb_ch2_c    :   in std_logic;
+    sb_felb_rst_ch2_c    :   in std_logic;
+    tx_pcs_rst_ch2_c    :   in std_logic;
+    tx_pwrup_ch2_c    :   in std_logic;
+    rx_pcs_rst_ch2_c    :   in std_logic;
+    rx_pwrup_ch2_c    :   in std_logic;
+    rx_los_low_ch2_s   :   out std_logic;
+    lsm_status_ch2_s   :   out std_logic;
+    rx_cdr_lol_ch2_s   :   out std_logic;
+    tx_div2_mode_ch2_c   : in std_logic;
+    rx_div2_mode_ch2_c   : in std_logic;
+-- CH3 --
+    hdinp_ch3, hdinn_ch3    :   in std_logic;
+    hdoutp_ch3, hdoutn_ch3   :   out std_logic;
+    sci_sel_ch3    :   in std_logic;
+    rxiclk_ch3    :   in std_logic;
+    txiclk_ch3    :   in std_logic;
+    rx_full_clk_ch3   :   out std_logic;
+    rx_half_clk_ch3   :   out std_logic;
+    tx_full_clk_ch3   :   out std_logic;
+    tx_half_clk_ch3   :   out std_logic;
+    fpga_rxrefclk_ch3    :   in std_logic;
+    txdata_ch3    :   in std_logic_vector (7 downto 0);
+    tx_k_ch3    :   in std_logic;
+    tx_force_disp_ch3    :   in std_logic;
+    tx_disp_sel_ch3    :   in std_logic;
+    rxdata_ch3   :   out std_logic_vector (7 downto 0);
+    rx_k_ch3   :   out std_logic;
+    rx_disp_err_ch3   :   out std_logic;
+    rx_cv_err_ch3   :   out std_logic;
+    rx_serdes_rst_ch3_c    :   in std_logic;
+    sb_felb_ch3_c    :   in std_logic;
+    sb_felb_rst_ch3_c    :   in std_logic;
+    tx_pcs_rst_ch3_c    :   in std_logic;
+    tx_pwrup_ch3_c    :   in std_logic;
+    rx_pcs_rst_ch3_c    :   in std_logic;
+    rx_pwrup_ch3_c    :   in std_logic;
+    rx_los_low_ch3_s   :   out std_logic;
+    lsm_status_ch3_s   :   out std_logic;
+    rx_cdr_lol_ch3_s   :   out std_logic;
+    tx_div2_mode_ch3_c   : in std_logic;
+    rx_div2_mode_ch3_c   : in std_logic;
+---- Miscillaneous ports
+    sci_wrdata    :   in std_logic_vector (7 downto 0);
+    sci_addr    :   in std_logic_vector (5 downto 0);
+    sci_rddata   :   out std_logic_vector (7 downto 0);
+    sci_sel_quad    :   in std_logic;
+    sci_rd    :   in std_logic;
+    sci_wrn    :   in std_logic;
+    fpga_txrefclk  :   in std_logic;
+    tx_serdes_rst_c    :   in std_logic;
+    tx_pll_lol_qd_s   :   out std_logic;
+    tx_sync_qd_c    :   in std_logic;
+    rst_qd_c    :   in std_logic;
+    serdes_rst_qd_c    :   in std_logic);
+
+end serdes_sync_160_full;
+
+
+architecture serdes_sync_160_full_arch of serdes_sync_160_full is
+
+component VLO
+port (
+   Z : out std_logic);
+end component;
+
+component VHI
+port (
+   Z : out std_logic);
+end component;
+
+
+
+component PCSD
+--synopsys translate_off
+GENERIC(
+  CONFIG_FILE : String;
+  QUAD_MODE : String;
+  CH0_CDR_SRC   : String := "REFCLK_EXT";
+  CH1_CDR_SRC   : String := "REFCLK_EXT";
+  CH2_CDR_SRC   : String := "REFCLK_EXT";
+  CH3_CDR_SRC   : String := "REFCLK_EXT";
+  PLL_SRC   : String
+  );
+--synopsys translate_on
+port (
+  HDINN0             : in std_logic;
+  HDINN1             : in std_logic;
+  HDINN2             : in std_logic;
+  HDINN3             : in std_logic;
+  HDINP0             : in std_logic;
+  HDINP1             : in std_logic;
+  HDINP2             : in std_logic;
+  HDINP3             : in std_logic;
+  REFCLKN             : in std_logic;
+  REFCLKP             : in std_logic;
+  CIN0             : in std_logic;
+  CIN1             : in std_logic;
+  CIN2             : in std_logic;
+  CIN3             : in std_logic;
+  CIN4             : in std_logic;
+  CIN5             : in std_logic;
+  CIN6             : in std_logic;
+  CIN7             : in std_logic;
+  CIN8             : in std_logic;
+  CIN9             : in std_logic;
+  CIN10             : in std_logic;
+  CIN11             : in std_logic;
+  CYAWSTN             : in std_logic;
+  FF_EBRD_CLK_0             : in std_logic;
+  FF_EBRD_CLK_1             : in std_logic;
+  FF_EBRD_CLK_2             : in std_logic;
+  FF_EBRD_CLK_3             : in std_logic;
+  FF_RXI_CLK_0             : in std_logic;
+  FF_RXI_CLK_1             : in std_logic;
+  FF_RXI_CLK_2             : in std_logic;
+  FF_RXI_CLK_3             : in std_logic;
+  FF_TX_D_0_0             : in std_logic;
+  FF_TX_D_0_1             : in std_logic;
+  FF_TX_D_0_2             : in std_logic;
+  FF_TX_D_0_3             : in std_logic;
+  FF_TX_D_0_4             : in std_logic;
+  FF_TX_D_0_5             : in std_logic;
+  FF_TX_D_0_6             : in std_logic;
+  FF_TX_D_0_7             : in std_logic;
+  FF_TX_D_0_8             : in std_logic;
+  FF_TX_D_0_9             : in std_logic;
+  FF_TX_D_0_10             : in std_logic;
+  FF_TX_D_0_11             : in std_logic;
+  FF_TX_D_0_12             : in std_logic;
+  FF_TX_D_0_13             : in std_logic;
+  FF_TX_D_0_14             : in std_logic;
+  FF_TX_D_0_15             : in std_logic;
+  FF_TX_D_0_16             : in std_logic;
+  FF_TX_D_0_17             : in std_logic;
+  FF_TX_D_0_18             : in std_logic;
+  FF_TX_D_0_19             : in std_logic;
+  FF_TX_D_0_20             : in std_logic;
+  FF_TX_D_0_21             : in std_logic;
+  FF_TX_D_0_22             : in std_logic;
+  FF_TX_D_0_23             : in std_logic;
+  FF_TX_D_1_0             : in std_logic;
+  FF_TX_D_1_1             : in std_logic;
+  FF_TX_D_1_2             : in std_logic;
+  FF_TX_D_1_3             : in std_logic;
+  FF_TX_D_1_4             : in std_logic;
+  FF_TX_D_1_5             : in std_logic;
+  FF_TX_D_1_6             : in std_logic;
+  FF_TX_D_1_7             : in std_logic;
+  FF_TX_D_1_8             : in std_logic;
+  FF_TX_D_1_9             : in std_logic;
+  FF_TX_D_1_10             : in std_logic;
+  FF_TX_D_1_11             : in std_logic;
+  FF_TX_D_1_12             : in std_logic;
+  FF_TX_D_1_13             : in std_logic;
+  FF_TX_D_1_14             : in std_logic;
+  FF_TX_D_1_15             : in std_logic;
+  FF_TX_D_1_16             : in std_logic;
+  FF_TX_D_1_17             : in std_logic;
+  FF_TX_D_1_18             : in std_logic;
+  FF_TX_D_1_19             : in std_logic;
+  FF_TX_D_1_20             : in std_logic;
+  FF_TX_D_1_21             : in std_logic;
+  FF_TX_D_1_22             : in std_logic;
+  FF_TX_D_1_23             : in std_logic;
+  FF_TX_D_2_0             : in std_logic;
+  FF_TX_D_2_1             : in std_logic;
+  FF_TX_D_2_2             : in std_logic;
+  FF_TX_D_2_3             : in std_logic;
+  FF_TX_D_2_4             : in std_logic;
+  FF_TX_D_2_5             : in std_logic;
+  FF_TX_D_2_6             : in std_logic;
+  FF_TX_D_2_7             : in std_logic;
+  FF_TX_D_2_8             : in std_logic;
+  FF_TX_D_2_9             : in std_logic;
+  FF_TX_D_2_10             : in std_logic;
+  FF_TX_D_2_11             : in std_logic;
+  FF_TX_D_2_12             : in std_logic;
+  FF_TX_D_2_13             : in std_logic;
+  FF_TX_D_2_14             : in std_logic;
+  FF_TX_D_2_15             : in std_logic;
+  FF_TX_D_2_16             : in std_logic;
+  FF_TX_D_2_17             : in std_logic;
+  FF_TX_D_2_18             : in std_logic;
+  FF_TX_D_2_19             : in std_logic;
+  FF_TX_D_2_20             : in std_logic;
+  FF_TX_D_2_21             : in std_logic;
+  FF_TX_D_2_22             : in std_logic;
+  FF_TX_D_2_23             : in std_logic;
+  FF_TX_D_3_0             : in std_logic;
+  FF_TX_D_3_1             : in std_logic;
+  FF_TX_D_3_2             : in std_logic;
+  FF_TX_D_3_3             : in std_logic;
+  FF_TX_D_3_4             : in std_logic;
+  FF_TX_D_3_5             : in std_logic;
+  FF_TX_D_3_6             : in std_logic;
+  FF_TX_D_3_7             : in std_logic;
+  FF_TX_D_3_8             : in std_logic;
+  FF_TX_D_3_9             : in std_logic;
+  FF_TX_D_3_10             : in std_logic;
+  FF_TX_D_3_11             : in std_logic;
+  FF_TX_D_3_12             : in std_logic;
+  FF_TX_D_3_13             : in std_logic;
+  FF_TX_D_3_14             : in std_logic;
+  FF_TX_D_3_15             : in std_logic;
+  FF_TX_D_3_16             : in std_logic;
+  FF_TX_D_3_17             : in std_logic;
+  FF_TX_D_3_18             : in std_logic;
+  FF_TX_D_3_19             : in std_logic;
+  FF_TX_D_3_20             : in std_logic;
+  FF_TX_D_3_21             : in std_logic;
+  FF_TX_D_3_22             : in std_logic;
+  FF_TX_D_3_23             : in std_logic;
+  FF_TXI_CLK_0             : in std_logic;
+  FF_TXI_CLK_1             : in std_logic;
+  FF_TXI_CLK_2             : in std_logic;
+  FF_TXI_CLK_3             : in std_logic;
+  FFC_CK_CORE_RX_0         : in std_logic;
+  FFC_CK_CORE_RX_1         : in std_logic;
+  FFC_CK_CORE_RX_2         : in std_logic;
+  FFC_CK_CORE_RX_3         : in std_logic;
+  FFC_CK_CORE_TX           : in std_logic;
+  FFC_EI_EN_0             : in std_logic;
+  FFC_EI_EN_1             : in std_logic;
+  FFC_EI_EN_2             : in std_logic;
+  FFC_EI_EN_3             : in std_logic;
+  FFC_ENABLE_CGALIGN_0             : in std_logic;
+  FFC_ENABLE_CGALIGN_1             : in std_logic;
+  FFC_ENABLE_CGALIGN_2             : in std_logic;
+  FFC_ENABLE_CGALIGN_3             : in std_logic;
+  FFC_FB_LOOPBACK_0             : in std_logic;
+  FFC_FB_LOOPBACK_1             : in std_logic;
+  FFC_FB_LOOPBACK_2             : in std_logic;
+  FFC_FB_LOOPBACK_3             : in std_logic;
+  FFC_LANE_RX_RST_0             : in std_logic;
+  FFC_LANE_RX_RST_1             : in std_logic;
+  FFC_LANE_RX_RST_2             : in std_logic;
+  FFC_LANE_RX_RST_3             : in std_logic;
+  FFC_LANE_TX_RST_0             : in std_logic;
+  FFC_LANE_TX_RST_1             : in std_logic;
+  FFC_LANE_TX_RST_2             : in std_logic;
+  FFC_LANE_TX_RST_3             : in std_logic;
+  FFC_MACRO_RST             : in std_logic;
+  FFC_PCI_DET_EN_0             : in std_logic;
+  FFC_PCI_DET_EN_1             : in std_logic;
+  FFC_PCI_DET_EN_2             : in std_logic;
+  FFC_PCI_DET_EN_3             : in std_logic;
+  FFC_PCIE_CT_0             : in std_logic;
+  FFC_PCIE_CT_1             : in std_logic;
+  FFC_PCIE_CT_2             : in std_logic;
+  FFC_PCIE_CT_3             : in std_logic;
+  FFC_PFIFO_CLR_0             : in std_logic;
+  FFC_PFIFO_CLR_1             : in std_logic;
+  FFC_PFIFO_CLR_2             : in std_logic;
+  FFC_PFIFO_CLR_3             : in std_logic;
+  FFC_QUAD_RST             : in std_logic;
+  FFC_RRST_0             : in std_logic;
+  FFC_RRST_1             : in std_logic;
+  FFC_RRST_2             : in std_logic;
+  FFC_RRST_3             : in std_logic;
+  FFC_RXPWDNB_0             : in std_logic;
+  FFC_RXPWDNB_1             : in std_logic;
+  FFC_RXPWDNB_2             : in std_logic;
+  FFC_RXPWDNB_3             : in std_logic;
+  FFC_SB_INV_RX_0             : in std_logic;
+  FFC_SB_INV_RX_1             : in std_logic;
+  FFC_SB_INV_RX_2             : in std_logic;
+  FFC_SB_INV_RX_3             : in std_logic;
+  FFC_SB_PFIFO_LP_0             : in std_logic;
+  FFC_SB_PFIFO_LP_1             : in std_logic;
+  FFC_SB_PFIFO_LP_2             : in std_logic;
+  FFC_SB_PFIFO_LP_3             : in std_logic;
+  FFC_SIGNAL_DETECT_0             : in std_logic;
+  FFC_SIGNAL_DETECT_1             : in std_logic;
+  FFC_SIGNAL_DETECT_2             : in std_logic;
+  FFC_SIGNAL_DETECT_3             : in std_logic;
+  FFC_SYNC_TOGGLE             : in std_logic;
+  FFC_TRST             : in std_logic;
+  FFC_TXPWDNB_0             : in std_logic;
+  FFC_TXPWDNB_1             : in std_logic;
+  FFC_TXPWDNB_2             : in std_logic;
+  FFC_TXPWDNB_3             : in std_logic;
+  FFC_RATE_MODE_RX_0        : in std_logic;
+  FFC_RATE_MODE_RX_1        : in std_logic;
+  FFC_RATE_MODE_RX_2        : in std_logic;
+  FFC_RATE_MODE_RX_3        : in std_logic;
+  FFC_RATE_MODE_TX_0        : in std_logic;
+  FFC_RATE_MODE_TX_1        : in std_logic;
+  FFC_RATE_MODE_TX_2        : in std_logic;
+  FFC_RATE_MODE_TX_3        : in std_logic;
+  FFC_DIV11_MODE_RX_0       : in std_logic;
+  FFC_DIV11_MODE_RX_1       : in std_logic;
+  FFC_DIV11_MODE_RX_2       : in std_logic;
+  FFC_DIV11_MODE_RX_3       : in std_logic;
+  FFC_DIV11_MODE_TX_0       : in std_logic;
+  FFC_DIV11_MODE_TX_1       : in std_logic;
+  FFC_DIV11_MODE_TX_2       : in std_logic;
+  FFC_DIV11_MODE_TX_3       : in std_logic;
+  LDR_CORE2TX_0             : in std_logic;
+  LDR_CORE2TX_1             : in std_logic;
+  LDR_CORE2TX_2             : in std_logic;
+  LDR_CORE2TX_3             : in std_logic;
+  FFC_LDR_CORE2TX_EN_0      : in std_logic;
+  FFC_LDR_CORE2TX_EN_1      : in std_logic;
+  FFC_LDR_CORE2TX_EN_2      : in std_logic;
+  FFC_LDR_CORE2TX_EN_3      : in std_logic;
+  PCIE_POWERDOWN_0_0      : in std_logic;
+  PCIE_POWERDOWN_0_1      : in std_logic;
+  PCIE_POWERDOWN_1_0      : in std_logic;
+  PCIE_POWERDOWN_1_1      : in std_logic;
+  PCIE_POWERDOWN_2_0      : in std_logic;
+  PCIE_POWERDOWN_2_1      : in std_logic;
+  PCIE_POWERDOWN_3_0      : in std_logic;
+  PCIE_POWERDOWN_3_1      : in std_logic;
+  PCIE_RXPOLARITY_0         : in std_logic;
+  PCIE_RXPOLARITY_1         : in std_logic;
+  PCIE_RXPOLARITY_2         : in std_logic;
+  PCIE_RXPOLARITY_3         : in std_logic;
+  PCIE_TXCOMPLIANCE_0       : in std_logic;
+  PCIE_TXCOMPLIANCE_1       : in std_logic;
+  PCIE_TXCOMPLIANCE_2       : in std_logic;
+  PCIE_TXCOMPLIANCE_3       : in std_logic;
+  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
+  SCIADDR0             : in std_logic;
+  SCIADDR1             : in std_logic;
+  SCIADDR2             : in std_logic;
+  SCIADDR3             : in std_logic;
+  SCIADDR4             : in std_logic;
+  SCIADDR5             : in std_logic;
+  SCIENAUX             : in std_logic;
+  SCIENCH0             : in std_logic;
+  SCIENCH1             : in std_logic;
+  SCIENCH2             : in std_logic;
+  SCIENCH3             : in std_logic;
+  SCIRD                : in std_logic;
+  SCISELAUX             : in std_logic;
+  SCISELCH0             : in std_logic;
+  SCISELCH1             : in std_logic;
+  SCISELCH2             : in std_logic;
+  SCISELCH3             : in std_logic;
+  SCIWDATA0             : in std_logic;
+  SCIWDATA1             : in std_logic;
+  SCIWDATA2             : in std_logic;
+  SCIWDATA3             : in std_logic;
+  SCIWDATA4             : in std_logic;
+  SCIWDATA5             : in std_logic;
+  SCIWDATA6             : in std_logic;
+  SCIWDATA7             : in std_logic;
+  SCIWSTN               : in std_logic;
+  REFCLK_FROM_NQ        : in std_logic;
+  HDOUTN0             : out std_logic;
+  HDOUTN1             : out std_logic;
+  HDOUTN2             : out std_logic;
+  HDOUTN3             : out std_logic;
+  HDOUTP0             : out std_logic;
+  HDOUTP1             : out std_logic;
+  HDOUTP2             : out std_logic;
+  HDOUTP3             : out std_logic;
+  COUT0             : out std_logic;
+  COUT1             : out std_logic;
+  COUT2             : out std_logic;
+  COUT3             : out std_logic;
+  COUT4             : out std_logic;
+  COUT5             : out std_logic;
+  COUT6             : out std_logic;
+  COUT7             : out std_logic;
+  COUT8             : out std_logic;
+  COUT9             : out std_logic;
+  COUT10             : out std_logic;
+  COUT11             : out std_logic;
+  COUT12             : out std_logic;
+  COUT13             : out std_logic;
+  COUT14             : out std_logic;
+  COUT15             : out std_logic;
+  COUT16             : out std_logic;
+  COUT17             : out std_logic;
+  COUT18             : out std_logic;
+  COUT19             : out std_logic;
+  FF_RX_D_0_0             : out std_logic;
+  FF_RX_D_0_1             : out std_logic;
+  FF_RX_D_0_2             : out std_logic;
+  FF_RX_D_0_3             : out std_logic;
+  FF_RX_D_0_4             : out std_logic;
+  FF_RX_D_0_5             : out std_logic;
+  FF_RX_D_0_6             : out std_logic;
+  FF_RX_D_0_7             : out std_logic;
+  FF_RX_D_0_8             : out std_logic;
+  FF_RX_D_0_9             : out std_logic;
+  FF_RX_D_0_10             : out std_logic;
+  FF_RX_D_0_11             : out std_logic;
+  FF_RX_D_0_12             : out std_logic;
+  FF_RX_D_0_13             : out std_logic;
+  FF_RX_D_0_14             : out std_logic;
+  FF_RX_D_0_15             : out std_logic;
+  FF_RX_D_0_16             : out std_logic;
+  FF_RX_D_0_17             : out std_logic;
+  FF_RX_D_0_18             : out std_logic;
+  FF_RX_D_0_19             : out std_logic;
+  FF_RX_D_0_20             : out std_logic;
+  FF_RX_D_0_21             : out std_logic;
+  FF_RX_D_0_22             : out std_logic;
+  FF_RX_D_0_23             : out std_logic;
+  FF_RX_D_1_0             : out std_logic;
+  FF_RX_D_1_1             : out std_logic;
+  FF_RX_D_1_2             : out std_logic;
+  FF_RX_D_1_3             : out std_logic;
+  FF_RX_D_1_4             : out std_logic;
+  FF_RX_D_1_5             : out std_logic;
+  FF_RX_D_1_6             : out std_logic;
+  FF_RX_D_1_7             : out std_logic;
+  FF_RX_D_1_8             : out std_logic;
+  FF_RX_D_1_9             : out std_logic;
+  FF_RX_D_1_10             : out std_logic;
+  FF_RX_D_1_11             : out std_logic;
+  FF_RX_D_1_12             : out std_logic;
+  FF_RX_D_1_13             : out std_logic;
+  FF_RX_D_1_14             : out std_logic;
+  FF_RX_D_1_15             : out std_logic;
+  FF_RX_D_1_16             : out std_logic;
+  FF_RX_D_1_17             : out std_logic;
+  FF_RX_D_1_18             : out std_logic;
+  FF_RX_D_1_19             : out std_logic;
+  FF_RX_D_1_20             : out std_logic;
+  FF_RX_D_1_21             : out std_logic;
+  FF_RX_D_1_22             : out std_logic;
+  FF_RX_D_1_23             : out std_logic;
+  FF_RX_D_2_0             : out std_logic;
+  FF_RX_D_2_1             : out std_logic;
+  FF_RX_D_2_2             : out std_logic;
+  FF_RX_D_2_3             : out std_logic;
+  FF_RX_D_2_4             : out std_logic;
+  FF_RX_D_2_5             : out std_logic;
+  FF_RX_D_2_6             : out std_logic;
+  FF_RX_D_2_7             : out std_logic;
+  FF_RX_D_2_8             : out std_logic;
+  FF_RX_D_2_9             : out std_logic;
+  FF_RX_D_2_10             : out std_logic;
+  FF_RX_D_2_11             : out std_logic;
+  FF_RX_D_2_12             : out std_logic;
+  FF_RX_D_2_13             : out std_logic;
+  FF_RX_D_2_14             : out std_logic;
+  FF_RX_D_2_15             : out std_logic;
+  FF_RX_D_2_16             : out std_logic;
+  FF_RX_D_2_17             : out std_logic;
+  FF_RX_D_2_18             : out std_logic;
+  FF_RX_D_2_19             : out std_logic;
+  FF_RX_D_2_20             : out std_logic;
+  FF_RX_D_2_21             : out std_logic;
+  FF_RX_D_2_22             : out std_logic;
+  FF_RX_D_2_23             : out std_logic;
+  FF_RX_D_3_0             : out std_logic;
+  FF_RX_D_3_1             : out std_logic;
+  FF_RX_D_3_2             : out std_logic;
+  FF_RX_D_3_3             : out std_logic;
+  FF_RX_D_3_4             : out std_logic;
+  FF_RX_D_3_5             : out std_logic;
+  FF_RX_D_3_6             : out std_logic;
+  FF_RX_D_3_7             : out std_logic;
+  FF_RX_D_3_8             : out std_logic;
+  FF_RX_D_3_9             : out std_logic;
+  FF_RX_D_3_10             : out std_logic;
+  FF_RX_D_3_11             : out std_logic;
+  FF_RX_D_3_12             : out std_logic;
+  FF_RX_D_3_13             : out std_logic;
+  FF_RX_D_3_14             : out std_logic;
+  FF_RX_D_3_15             : out std_logic;
+  FF_RX_D_3_16             : out std_logic;
+  FF_RX_D_3_17             : out std_logic;
+  FF_RX_D_3_18             : out std_logic;
+  FF_RX_D_3_19             : out std_logic;
+  FF_RX_D_3_20             : out std_logic;
+  FF_RX_D_3_21             : out std_logic;
+  FF_RX_D_3_22             : out std_logic;
+  FF_RX_D_3_23             : out std_logic;
+  FF_RX_F_CLK_0             : out std_logic;
+  FF_RX_F_CLK_1             : out std_logic;
+  FF_RX_F_CLK_2             : out std_logic;
+  FF_RX_F_CLK_3             : out std_logic;
+  FF_RX_H_CLK_0             : out std_logic;
+  FF_RX_H_CLK_1             : out std_logic;
+  FF_RX_H_CLK_2             : out std_logic;
+  FF_RX_H_CLK_3             : out std_logic;
+  FF_TX_F_CLK_0             : out std_logic;
+  FF_TX_F_CLK_1             : out std_logic;
+  FF_TX_F_CLK_2             : out std_logic;
+  FF_TX_F_CLK_3             : out std_logic;
+  FF_TX_H_CLK_0             : out std_logic;
+  FF_TX_H_CLK_1             : out std_logic;
+  FF_TX_H_CLK_2             : out std_logic;
+  FF_TX_H_CLK_3             : out std_logic;
+  FFS_CC_OVERRUN_0             : out std_logic;
+  FFS_CC_OVERRUN_1             : out std_logic;
+  FFS_CC_OVERRUN_2             : out std_logic;
+  FFS_CC_OVERRUN_3             : out std_logic;
+  FFS_CC_UNDERRUN_0             : out std_logic;
+  FFS_CC_UNDERRUN_1             : out std_logic;
+  FFS_CC_UNDERRUN_2             : out std_logic;
+  FFS_CC_UNDERRUN_3             : out std_logic;
+  FFS_LS_SYNC_STATUS_0             : out std_logic;
+  FFS_LS_SYNC_STATUS_1             : out std_logic;
+  FFS_LS_SYNC_STATUS_2             : out std_logic;
+  FFS_LS_SYNC_STATUS_3             : out std_logic;
+  FFS_CDR_TRAIN_DONE_0             : out std_logic;
+  FFS_CDR_TRAIN_DONE_1             : out std_logic;
+  FFS_CDR_TRAIN_DONE_2             : out std_logic;
+  FFS_CDR_TRAIN_DONE_3             : out std_logic;
+  FFS_PCIE_CON_0             : out std_logic;
+  FFS_PCIE_CON_1             : out std_logic;
+  FFS_PCIE_CON_2             : out std_logic;
+  FFS_PCIE_CON_3             : out std_logic;
+  FFS_PCIE_DONE_0             : out std_logic;
+  FFS_PCIE_DONE_1             : out std_logic;
+  FFS_PCIE_DONE_2             : out std_logic;
+  FFS_PCIE_DONE_3             : out std_logic;
+  FFS_PLOL             : out std_logic;
+  FFS_RLOL_0             : out std_logic;
+  FFS_RLOL_1             : out std_logic;
+  FFS_RLOL_2             : out std_logic;
+  FFS_RLOL_3             : out std_logic;
+  FFS_RLOS_HI_0             : out std_logic;
+  FFS_RLOS_HI_1             : out std_logic;
+  FFS_RLOS_HI_2             : out std_logic;
+  FFS_RLOS_HI_3             : out std_logic;
+  FFS_RLOS_LO_0             : out std_logic;
+  FFS_RLOS_LO_1             : out std_logic;
+  FFS_RLOS_LO_2             : out std_logic;
+  FFS_RLOS_LO_3             : out std_logic;
+  FFS_RXFBFIFO_ERROR_0             : out std_logic;
+  FFS_RXFBFIFO_ERROR_1             : out std_logic;
+  FFS_RXFBFIFO_ERROR_2             : out std_logic;
+  FFS_RXFBFIFO_ERROR_3             : out std_logic;
+  FFS_TXFBFIFO_ERROR_0             : out std_logic;
+  FFS_TXFBFIFO_ERROR_1             : out std_logic;
+  FFS_TXFBFIFO_ERROR_2             : out std_logic;
+  FFS_TXFBFIFO_ERROR_3             : out std_logic;
+  PCIE_PHYSTATUS_0             : out std_logic;
+  PCIE_PHYSTATUS_1             : out std_logic;
+  PCIE_PHYSTATUS_2             : out std_logic;
+  PCIE_PHYSTATUS_3             : out std_logic;
+  PCIE_RXVALID_0               : out std_logic;
+  PCIE_RXVALID_1               : out std_logic;
+  PCIE_RXVALID_2               : out std_logic;
+  PCIE_RXVALID_3               : out std_logic;
+  FFS_SKP_ADDED_0                  : out std_logic;
+  FFS_SKP_ADDED_1                  : out std_logic;
+  FFS_SKP_ADDED_2                  : out std_logic;
+  FFS_SKP_ADDED_3                  : out std_logic;
+  FFS_SKP_DELETED_0                : out std_logic;
+  FFS_SKP_DELETED_1                : out std_logic;
+  FFS_SKP_DELETED_2                : out std_logic;
+  FFS_SKP_DELETED_3                : out std_logic;
+  LDR_RX2CORE_0                    : out std_logic;
+  LDR_RX2CORE_1                    : out std_logic;
+  LDR_RX2CORE_2                    : out std_logic;
+  LDR_RX2CORE_3                    : out std_logic;
+  REFCK2CORE             : out std_logic;
+  SCIINT                : out std_logic;
+  SCIRDATA0             : out std_logic;
+  SCIRDATA1             : out std_logic;
+  SCIRDATA2             : out std_logic;
+  SCIRDATA3             : out std_logic;
+  SCIRDATA4             : out std_logic;
+  SCIRDATA5             : out std_logic;
+  SCIRDATA6             : out std_logic;
+  SCIRDATA7             : out std_logic;
+  REFCLK_TO_NQ          : out std_logic
+);
+end component;
+   attribute CONFIG_FILE: string;
+   attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
+   attribute QUAD_MODE: string;
+   attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
+   attribute PLL_SRC: string;
+   attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
+   attribute CH0_CDR_SRC: string;
+   attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+   attribute CH1_CDR_SRC: string;
+   attribute CH1_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+   attribute CH2_CDR_SRC: string;
+   attribute CH2_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+   attribute CH3_CDR_SRC: string;
+   attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "160.000";
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "160.000";
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "160.000";
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "160.000";
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "80.0000";
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "80.0000";
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "80.0000";
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "80.0000";
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "160.000";
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "160.000";
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "160.000";
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "160.000";
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "80.0000";
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "80.0000";
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "80.0000";
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "80.0000";
+   attribute black_box_pad_pin: string;
+   attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
+
+signal refclk_from_nq : std_logic := '0';
+signal fpsc_vlo : std_logic := '0';
+signal fpsc_vhi : std_logic := '1';
+signal cin : std_logic_vector (11 downto 0) := "000000000000";
+signal cout : std_logic_vector (19 downto 0);
+signal    tx_full_clk_ch0_sig   :   std_logic;
+signal    tx_full_clk_ch1_sig   :   std_logic;
+signal    tx_full_clk_ch2_sig   :   std_logic;
+signal    tx_full_clk_ch3_sig   :   std_logic;
+
+signal    refclk2fpga_sig  :   std_logic;
+signal    tx_pll_lol_qd_sig  :   std_logic;
+signal    rx_los_low_ch0_sig  :   std_logic;
+signal    rx_los_low_ch1_sig  :   std_logic;
+signal    rx_los_low_ch2_sig  :   std_logic;
+signal    rx_los_low_ch3_sig  :   std_logic;
+signal    rx_cdr_lol_ch0_sig  :   std_logic;
+signal    rx_cdr_lol_ch1_sig  :   std_logic;
+signal    rx_cdr_lol_ch2_sig  :   std_logic;
+signal    rx_cdr_lol_ch3_sig  :   std_logic;
+
+
+
+
+
+begin
+
+vlo_inst : VLO port map(Z => fpsc_vlo);
+vhi_inst : VHI port map(Z => fpsc_vhi);
+
+    rx_los_low_ch0_s <= rx_los_low_ch0_sig;
+    rx_los_low_ch1_s <= rx_los_low_ch1_sig;
+    rx_los_low_ch2_s <= rx_los_low_ch2_sig;
+    rx_los_low_ch3_s <= rx_los_low_ch3_sig;
+    rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig;
+    rx_cdr_lol_ch1_s <= rx_cdr_lol_ch1_sig;
+    rx_cdr_lol_ch2_s <= rx_cdr_lol_ch2_sig;
+    rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig;
+  tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
+  tx_full_clk_ch0 <= tx_full_clk_ch0_sig;
+  tx_full_clk_ch1 <= tx_full_clk_ch1_sig;
+  tx_full_clk_ch2 <= tx_full_clk_ch2_sig;
+  tx_full_clk_ch3 <= tx_full_clk_ch3_sig;
+
+-- pcs_quad instance
+PCSD_INST : PCSD
+--synopsys translate_off
+  generic map (CONFIG_FILE => USER_CONFIG_FILE,
+               QUAD_MODE => "SINGLE",
+               CH0_CDR_SRC => "REFCLK_CORE",
+               CH1_CDR_SRC => "REFCLK_CORE",
+               CH2_CDR_SRC => "REFCLK_CORE",
+               CH3_CDR_SRC => "REFCLK_CORE",
+               PLL_SRC  => "REFCLK_CORE"
+  )
+--synopsys translate_on
+port map  (
+  REFCLKP => fpsc_vlo,
+  REFCLKN => fpsc_vlo,
+
+----- CH0 -----
+  HDOUTP0 => hdoutp_ch0,
+  HDOUTN0 => hdoutn_ch0,
+  HDINP0 => hdinp_ch0,
+  HDINN0 => hdinn_ch0,
+  PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
+  PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
+  PCIE_RXPOLARITY_0 => fpsc_vlo,
+  PCIE_POWERDOWN_0_0 => fpsc_vlo,
+  PCIE_POWERDOWN_0_1 => fpsc_vlo,
+  PCIE_RXVALID_0 => open,
+  PCIE_PHYSTATUS_0 => open,
+  SCISELCH0 => sci_sel_ch0,
+  SCIENCH0 => fpsc_vhi,
+  FF_RXI_CLK_0 => rxiclk_ch0,
+  FF_TXI_CLK_0 => txiclk_ch0,
+  FF_EBRD_CLK_0 => fpsc_vlo,
+  FF_RX_F_CLK_0 => rx_full_clk_ch0,
+  FF_RX_H_CLK_0 => rx_half_clk_ch0,
+  FF_TX_F_CLK_0 => tx_full_clk_ch0_sig,
+  FF_TX_H_CLK_0 => tx_half_clk_ch0,
+  FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0,
+  FF_TX_D_0_0 => txdata_ch0(0),
+  FF_TX_D_0_1 => txdata_ch0(1),
+  FF_TX_D_0_2 => txdata_ch0(2),
+  FF_TX_D_0_3 => txdata_ch0(3),
+  FF_TX_D_0_4 => txdata_ch0(4),
+  FF_TX_D_0_5 => txdata_ch0(5),
+  FF_TX_D_0_6 => txdata_ch0(6),
+  FF_TX_D_0_7 => txdata_ch0(7),
+  FF_TX_D_0_8 => tx_k_ch0,
+  FF_TX_D_0_9 => tx_force_disp_ch0,
+  FF_TX_D_0_10 => tx_disp_sel_ch0,
+  FF_TX_D_0_11 => fpsc_vlo,
+  FF_TX_D_0_12 => fpsc_vlo,
+  FF_TX_D_0_13 => fpsc_vlo,
+  FF_TX_D_0_14 => fpsc_vlo,
+  FF_TX_D_0_15 => fpsc_vlo,
+  FF_TX_D_0_16 => fpsc_vlo,
+  FF_TX_D_0_17 => fpsc_vlo,
+  FF_TX_D_0_18 => fpsc_vlo,
+  FF_TX_D_0_19 => fpsc_vlo,
+  FF_TX_D_0_20 => fpsc_vlo,
+  FF_TX_D_0_21 => fpsc_vlo,
+  FF_TX_D_0_22 => fpsc_vlo,
+  FF_TX_D_0_23 => fpsc_vlo,
+  FF_RX_D_0_0 => rxdata_ch0(0),
+  FF_RX_D_0_1 => rxdata_ch0(1),
+  FF_RX_D_0_2 => rxdata_ch0(2),
+  FF_RX_D_0_3 => rxdata_ch0(3),
+  FF_RX_D_0_4 => rxdata_ch0(4),
+  FF_RX_D_0_5 => rxdata_ch0(5),
+  FF_RX_D_0_6 => rxdata_ch0(6),
+  FF_RX_D_0_7 => rxdata_ch0(7),
+  FF_RX_D_0_8 => rx_k_ch0,
+  FF_RX_D_0_9 => rx_disp_err_ch0,
+  FF_RX_D_0_10 => rx_cv_err_ch0,
+  FF_RX_D_0_11 => open,
+  FF_RX_D_0_12 => open,
+  FF_RX_D_0_13 => open,
+  FF_RX_D_0_14 => open,
+  FF_RX_D_0_15 => open,
+  FF_RX_D_0_16 => open,
+  FF_RX_D_0_17 => open,
+  FF_RX_D_0_18 => open,
+  FF_RX_D_0_19 => open,
+  FF_RX_D_0_20 => open,
+  FF_RX_D_0_21 => open,
+  FF_RX_D_0_22 => open,
+  FF_RX_D_0_23 => open,
+
+  FFC_RRST_0 => rx_serdes_rst_ch0_c,
+  FFC_SIGNAL_DETECT_0 => fpsc_vlo,
+  FFC_SB_PFIFO_LP_0 => sb_felb_ch0_c,
+  FFC_PFIFO_CLR_0 => sb_felb_rst_ch0_c,
+  FFC_SB_INV_RX_0 => fpsc_vlo,
+  FFC_PCIE_CT_0 => fpsc_vlo,
+  FFC_PCI_DET_EN_0 => fpsc_vlo,
+  FFC_FB_LOOPBACK_0 => fpsc_vlo,
+  FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
+  FFC_EI_EN_0 => fpsc_vlo,
+  FFC_LANE_TX_RST_0 => tx_pcs_rst_ch0_c,
+  FFC_TXPWDNB_0 => tx_pwrup_ch0_c,
+  FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c,
+  FFC_RXPWDNB_0 => rx_pwrup_ch0_c,
+  FFS_RLOS_LO_0 => rx_los_low_ch0_sig,
+  FFS_RLOS_HI_0 => open,
+  FFS_PCIE_CON_0 => open,
+  FFS_PCIE_DONE_0 => open,
+  FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s,
+  FFS_CC_OVERRUN_0 => open,
+  FFS_CC_UNDERRUN_0 => open,
+  FFS_SKP_ADDED_0 => open,
+  FFS_SKP_DELETED_0 => open,
+  FFS_RLOL_0 => rx_cdr_lol_ch0_sig,
+  FFS_RXFBFIFO_ERROR_0 => open,
+  FFS_TXFBFIFO_ERROR_0 => open,
+  LDR_CORE2TX_0 => fpsc_vlo,
+  FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
+  LDR_RX2CORE_0 => open,
+  FFS_CDR_TRAIN_DONE_0 => open,
+  FFC_DIV11_MODE_TX_0 => fpsc_vlo,
+  FFC_RATE_MODE_TX_0 => tx_div2_mode_ch0_c,
+  FFC_DIV11_MODE_RX_0 => fpsc_vlo,
+  FFC_RATE_MODE_RX_0 => rx_div2_mode_ch0_c,
+
+----- CH1 -----
+  HDOUTP1 => hdoutp_ch1,
+  HDOUTN1 => hdoutn_ch1,
+  HDINP1 => hdinp_ch1,
+  HDINN1 => hdinn_ch1,
+  PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
+  PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
+  PCIE_RXPOLARITY_1 => fpsc_vlo,
+  PCIE_POWERDOWN_1_0 => fpsc_vlo,
+  PCIE_POWERDOWN_1_1 => fpsc_vlo,
+  PCIE_RXVALID_1 => open,
+  PCIE_PHYSTATUS_1 => open,
+  SCISELCH1 => sci_sel_ch1,
+  SCIENCH1 => fpsc_vhi,
+  FF_RXI_CLK_1 => rxiclk_ch1,
+  FF_TXI_CLK_1 => txiclk_ch1,
+  FF_EBRD_CLK_1 => fpsc_vlo,
+  FF_RX_F_CLK_1 => rx_full_clk_ch1,
+  FF_RX_H_CLK_1 => rx_half_clk_ch1,
+  FF_TX_F_CLK_1 => tx_full_clk_ch1_sig,
+  FF_TX_H_CLK_1 => tx_half_clk_ch1,
+  FFC_CK_CORE_RX_1 => fpga_rxrefclk_ch1,
+  FF_TX_D_1_0 => txdata_ch1(0),
+  FF_TX_D_1_1 => txdata_ch1(1),
+  FF_TX_D_1_2 => txdata_ch1(2),
+  FF_TX_D_1_3 => txdata_ch1(3),
+  FF_TX_D_1_4 => txdata_ch1(4),
+  FF_TX_D_1_5 => txdata_ch1(5),
+  FF_TX_D_1_6 => txdata_ch1(6),
+  FF_TX_D_1_7 => txdata_ch1(7),
+  FF_TX_D_1_8 => tx_k_ch1,
+  FF_TX_D_1_9 => tx_force_disp_ch1,
+  FF_TX_D_1_10 => tx_disp_sel_ch1,
+  FF_TX_D_1_11 => fpsc_vlo,
+  FF_TX_D_1_12 => fpsc_vlo,
+  FF_TX_D_1_13 => fpsc_vlo,
+  FF_TX_D_1_14 => fpsc_vlo,
+  FF_TX_D_1_15 => fpsc_vlo,
+  FF_TX_D_1_16 => fpsc_vlo,
+  FF_TX_D_1_17 => fpsc_vlo,
+  FF_TX_D_1_18 => fpsc_vlo,
+  FF_TX_D_1_19 => fpsc_vlo,
+  FF_TX_D_1_20 => fpsc_vlo,
+  FF_TX_D_1_21 => fpsc_vlo,
+  FF_TX_D_1_22 => fpsc_vlo,
+  FF_TX_D_1_23 => fpsc_vlo,
+  FF_RX_D_1_0 => rxdata_ch1(0),
+  FF_RX_D_1_1 => rxdata_ch1(1),
+  FF_RX_D_1_2 => rxdata_ch1(2),
+  FF_RX_D_1_3 => rxdata_ch1(3),
+  FF_RX_D_1_4 => rxdata_ch1(4),
+  FF_RX_D_1_5 => rxdata_ch1(5),
+  FF_RX_D_1_6 => rxdata_ch1(6),
+  FF_RX_D_1_7 => rxdata_ch1(7),
+  FF_RX_D_1_8 => rx_k_ch1,
+  FF_RX_D_1_9 => rx_disp_err_ch1,
+  FF_RX_D_1_10 => rx_cv_err_ch1,
+  FF_RX_D_1_11 => open,
+  FF_RX_D_1_12 => open,
+  FF_RX_D_1_13 => open,
+  FF_RX_D_1_14 => open,
+  FF_RX_D_1_15 => open,
+  FF_RX_D_1_16 => open,
+  FF_RX_D_1_17 => open,
+  FF_RX_D_1_18 => open,
+  FF_RX_D_1_19 => open,
+  FF_RX_D_1_20 => open,
+  FF_RX_D_1_21 => open,
+  FF_RX_D_1_22 => open,
+  FF_RX_D_1_23 => open,
+
+  FFC_RRST_1 => rx_serdes_rst_ch1_c,
+  FFC_SIGNAL_DETECT_1 => fpsc_vlo,
+  FFC_SB_PFIFO_LP_1 => sb_felb_ch1_c,
+  FFC_PFIFO_CLR_1 => sb_felb_rst_ch1_c,
+  FFC_SB_INV_RX_1 => fpsc_vlo,
+  FFC_PCIE_CT_1 => fpsc_vlo,
+  FFC_PCI_DET_EN_1 => fpsc_vlo,
+  FFC_FB_LOOPBACK_1 => fpsc_vlo,
+  FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
+  FFC_EI_EN_1 => fpsc_vlo,
+  FFC_LANE_TX_RST_1 => tx_pcs_rst_ch1_c,
+  FFC_TXPWDNB_1 => tx_pwrup_ch1_c,
+  FFC_LANE_RX_RST_1 => rx_pcs_rst_ch1_c,
+  FFC_RXPWDNB_1 => rx_pwrup_ch1_c,
+  FFS_RLOS_LO_1 => rx_los_low_ch1_sig,
+  FFS_RLOS_HI_1 => open,
+  FFS_PCIE_CON_1 => open,
+  FFS_PCIE_DONE_1 => open,
+  FFS_LS_SYNC_STATUS_1 => lsm_status_ch1_s,
+  FFS_CC_OVERRUN_1 => open,
+  FFS_CC_UNDERRUN_1 => open,
+  FFS_SKP_ADDED_1 => open,
+  FFS_SKP_DELETED_1 => open,
+  FFS_RLOL_1 => rx_cdr_lol_ch1_sig,
+  FFS_RXFBFIFO_ERROR_1 => open,
+  FFS_TXFBFIFO_ERROR_1 => open,
+  LDR_CORE2TX_1 => fpsc_vlo,
+  FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
+  LDR_RX2CORE_1 => open,
+  FFS_CDR_TRAIN_DONE_1 => open,
+  FFC_DIV11_MODE_TX_1 => fpsc_vlo,
+  FFC_RATE_MODE_TX_1 => tx_div2_mode_ch1_c,
+  FFC_DIV11_MODE_RX_1 => fpsc_vlo,
+  FFC_RATE_MODE_RX_1 => rx_div2_mode_ch1_c,
+
+----- CH2 -----
+  HDOUTP2 => hdoutp_ch2,
+  HDOUTN2 => hdoutn_ch2,
+  HDINP2 => hdinp_ch2,
+  HDINN2 => hdinn_ch2,
+  PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
+  PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
+  PCIE_RXPOLARITY_2 => fpsc_vlo,
+  PCIE_POWERDOWN_2_0 => fpsc_vlo,
+  PCIE_POWERDOWN_2_1 => fpsc_vlo,
+  PCIE_RXVALID_2 => open,
+  PCIE_PHYSTATUS_2 => open,
+  SCISELCH2 => sci_sel_ch2,
+  SCIENCH2 => fpsc_vhi,
+  FF_RXI_CLK_2 => rxiclk_ch2,
+  FF_TXI_CLK_2 => txiclk_ch2,
+  FF_EBRD_CLK_2 => fpsc_vlo,
+  FF_RX_F_CLK_2 => rx_full_clk_ch2,
+  FF_RX_H_CLK_2 => rx_half_clk_ch2,
+  FF_TX_F_CLK_2 => tx_full_clk_ch2_sig,
+  FF_TX_H_CLK_2 => tx_half_clk_ch2,
+  FFC_CK_CORE_RX_2 => fpga_rxrefclk_ch2,
+  FF_TX_D_2_0 => txdata_ch2(0),
+  FF_TX_D_2_1 => txdata_ch2(1),
+  FF_TX_D_2_2 => txdata_ch2(2),
+  FF_TX_D_2_3 => txdata_ch2(3),
+  FF_TX_D_2_4 => txdata_ch2(4),
+  FF_TX_D_2_5 => txdata_ch2(5),
+  FF_TX_D_2_6 => txdata_ch2(6),
+  FF_TX_D_2_7 => txdata_ch2(7),
+  FF_TX_D_2_8 => tx_k_ch2,
+  FF_TX_D_2_9 => tx_force_disp_ch2,
+  FF_TX_D_2_10 => tx_disp_sel_ch2,
+  FF_TX_D_2_11 => fpsc_vlo,
+  FF_TX_D_2_12 => fpsc_vlo,
+  FF_TX_D_2_13 => fpsc_vlo,
+  FF_TX_D_2_14 => fpsc_vlo,
+  FF_TX_D_2_15 => fpsc_vlo,
+  FF_TX_D_2_16 => fpsc_vlo,
+  FF_TX_D_2_17 => fpsc_vlo,
+  FF_TX_D_2_18 => fpsc_vlo,
+  FF_TX_D_2_19 => fpsc_vlo,
+  FF_TX_D_2_20 => fpsc_vlo,
+  FF_TX_D_2_21 => fpsc_vlo,
+  FF_TX_D_2_22 => fpsc_vlo,
+  FF_TX_D_2_23 => fpsc_vlo,
+  FF_RX_D_2_0 => rxdata_ch2(0),
+  FF_RX_D_2_1 => rxdata_ch2(1),
+  FF_RX_D_2_2 => rxdata_ch2(2),
+  FF_RX_D_2_3 => rxdata_ch2(3),
+  FF_RX_D_2_4 => rxdata_ch2(4),
+  FF_RX_D_2_5 => rxdata_ch2(5),
+  FF_RX_D_2_6 => rxdata_ch2(6),
+  FF_RX_D_2_7 => rxdata_ch2(7),
+  FF_RX_D_2_8 => rx_k_ch2,
+  FF_RX_D_2_9 => rx_disp_err_ch2,
+  FF_RX_D_2_10 => rx_cv_err_ch2,
+  FF_RX_D_2_11 => open,
+  FF_RX_D_2_12 => open,
+  FF_RX_D_2_13 => open,
+  FF_RX_D_2_14 => open,
+  FF_RX_D_2_15 => open,
+  FF_RX_D_2_16 => open,
+  FF_RX_D_2_17 => open,
+  FF_RX_D_2_18 => open,
+  FF_RX_D_2_19 => open,
+  FF_RX_D_2_20 => open,
+  FF_RX_D_2_21 => open,
+  FF_RX_D_2_22 => open,
+  FF_RX_D_2_23 => open,
+
+  FFC_RRST_2 => rx_serdes_rst_ch2_c,
+  FFC_SIGNAL_DETECT_2 => fpsc_vlo,
+  FFC_SB_PFIFO_LP_2 => sb_felb_ch2_c,
+  FFC_PFIFO_CLR_2 => sb_felb_rst_ch2_c,
+  FFC_SB_INV_RX_2 => fpsc_vlo,
+  FFC_PCIE_CT_2 => fpsc_vlo,
+  FFC_PCI_DET_EN_2 => fpsc_vlo,
+  FFC_FB_LOOPBACK_2 => fpsc_vlo,
+  FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
+  FFC_EI_EN_2 => fpsc_vlo,
+  FFC_LANE_TX_RST_2 => tx_pcs_rst_ch2_c,
+  FFC_TXPWDNB_2 => tx_pwrup_ch2_c,
+  FFC_LANE_RX_RST_2 => rx_pcs_rst_ch2_c,
+  FFC_RXPWDNB_2 => rx_pwrup_ch2_c,
+  FFS_RLOS_LO_2 => rx_los_low_ch2_sig,
+  FFS_RLOS_HI_2 => open,
+  FFS_PCIE_CON_2 => open,
+  FFS_PCIE_DONE_2 => open,
+  FFS_LS_SYNC_STATUS_2 => lsm_status_ch2_s,
+  FFS_CC_OVERRUN_2 => open,
+  FFS_CC_UNDERRUN_2 => open,
+  FFS_SKP_ADDED_2 => open,
+  FFS_SKP_DELETED_2 => open,
+  FFS_RLOL_2 => rx_cdr_lol_ch2_sig,
+  FFS_RXFBFIFO_ERROR_2 => open,
+  FFS_TXFBFIFO_ERROR_2 => open,
+  LDR_CORE2TX_2 => fpsc_vlo,
+  FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
+  LDR_RX2CORE_2 => open,
+  FFS_CDR_TRAIN_DONE_2 => open,
+  FFC_DIV11_MODE_TX_2 => fpsc_vlo,
+  FFC_RATE_MODE_TX_2 => tx_div2_mode_ch2_c,
+  FFC_DIV11_MODE_RX_2 => fpsc_vlo,
+  FFC_RATE_MODE_RX_2 => rx_div2_mode_ch2_c,
+
+----- CH3 -----
+  HDOUTP3 => hdoutp_ch3,
+  HDOUTN3 => hdoutn_ch3,
+  HDINP3 => hdinp_ch3,
+  HDINN3 => hdinn_ch3,
+  PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
+  PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
+  PCIE_RXPOLARITY_3 => fpsc_vlo,
+  PCIE_POWERDOWN_3_0 => fpsc_vlo,
+  PCIE_POWERDOWN_3_1 => fpsc_vlo,
+  PCIE_RXVALID_3 => open,
+  PCIE_PHYSTATUS_3 => open,
+  SCISELCH3 => sci_sel_ch3,
+  SCIENCH3 => fpsc_vhi,
+  FF_RXI_CLK_3 => rxiclk_ch3,
+  FF_TXI_CLK_3 => txiclk_ch3,
+  FF_EBRD_CLK_3 => fpsc_vlo,
+  FF_RX_F_CLK_3 => rx_full_clk_ch3,
+  FF_RX_H_CLK_3 => rx_half_clk_ch3,
+  FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,
+  FF_TX_H_CLK_3 => tx_half_clk_ch3,
+  FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3,
+  FF_TX_D_3_0 => txdata_ch3(0),
+  FF_TX_D_3_1 => txdata_ch3(1),
+  FF_TX_D_3_2 => txdata_ch3(2),
+  FF_TX_D_3_3 => txdata_ch3(3),
+  FF_TX_D_3_4 => txdata_ch3(4),
+  FF_TX_D_3_5 => txdata_ch3(5),
+  FF_TX_D_3_6 => txdata_ch3(6),
+  FF_TX_D_3_7 => txdata_ch3(7),
+  FF_TX_D_3_8 => tx_k_ch3,
+  FF_TX_D_3_9 => tx_force_disp_ch3,
+  FF_TX_D_3_10 => tx_disp_sel_ch3,
+  FF_TX_D_3_11 => fpsc_vlo,
+  FF_TX_D_3_12 => fpsc_vlo,
+  FF_TX_D_3_13 => fpsc_vlo,
+  FF_TX_D_3_14 => fpsc_vlo,
+  FF_TX_D_3_15 => fpsc_vlo,
+  FF_TX_D_3_16 => fpsc_vlo,
+  FF_TX_D_3_17 => fpsc_vlo,
+  FF_TX_D_3_18 => fpsc_vlo,
+  FF_TX_D_3_19 => fpsc_vlo,
+  FF_TX_D_3_20 => fpsc_vlo,
+  FF_TX_D_3_21 => fpsc_vlo,
+  FF_TX_D_3_22 => fpsc_vlo,
+  FF_TX_D_3_23 => fpsc_vlo,
+  FF_RX_D_3_0 => rxdata_ch3(0),
+  FF_RX_D_3_1 => rxdata_ch3(1),
+  FF_RX_D_3_2 => rxdata_ch3(2),
+  FF_RX_D_3_3 => rxdata_ch3(3),
+  FF_RX_D_3_4 => rxdata_ch3(4),
+  FF_RX_D_3_5 => rxdata_ch3(5),
+  FF_RX_D_3_6 => rxdata_ch3(6),
+  FF_RX_D_3_7 => rxdata_ch3(7),
+  FF_RX_D_3_8 => rx_k_ch3,
+  FF_RX_D_3_9 => rx_disp_err_ch3,
+  FF_RX_D_3_10 => rx_cv_err_ch3,
+  FF_RX_D_3_11 => open,
+  FF_RX_D_3_12 => open,
+  FF_RX_D_3_13 => open,
+  FF_RX_D_3_14 => open,
+  FF_RX_D_3_15 => open,
+  FF_RX_D_3_16 => open,
+  FF_RX_D_3_17 => open,
+  FF_RX_D_3_18 => open,
+  FF_RX_D_3_19 => open,
+  FF_RX_D_3_20 => open,
+  FF_RX_D_3_21 => open,
+  FF_RX_D_3_22 => open,
+  FF_RX_D_3_23 => open,
+
+  FFC_RRST_3 => rx_serdes_rst_ch3_c,
+  FFC_SIGNAL_DETECT_3 => fpsc_vlo,
+  FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c,
+  FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c,
+  FFC_SB_INV_RX_3 => fpsc_vlo,
+  FFC_PCIE_CT_3 => fpsc_vlo,
+  FFC_PCI_DET_EN_3 => fpsc_vlo,
+  FFC_FB_LOOPBACK_3 => fpsc_vlo,
+  FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
+  FFC_EI_EN_3 => fpsc_vlo,
+  FFC_LANE_TX_RST_3 => tx_pcs_rst_ch3_c,
+  FFC_TXPWDNB_3 => tx_pwrup_ch3_c,
+  FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c,
+  FFC_RXPWDNB_3 => rx_pwrup_ch3_c,
+  FFS_RLOS_LO_3 => rx_los_low_ch3_sig,
+  FFS_RLOS_HI_3 => open,
+  FFS_PCIE_CON_3 => open,
+  FFS_PCIE_DONE_3 => open,
+  FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s,
+  FFS_CC_OVERRUN_3 => open,
+  FFS_CC_UNDERRUN_3 => open,
+  FFS_SKP_ADDED_3 => open,
+  FFS_SKP_DELETED_3 => open,
+  FFS_RLOL_3 => rx_cdr_lol_ch3_sig,
+  FFS_RXFBFIFO_ERROR_3 => open,
+  FFS_TXFBFIFO_ERROR_3 => open,
+  LDR_CORE2TX_3 => fpsc_vlo,
+  FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
+  LDR_RX2CORE_3 => open,
+  FFS_CDR_TRAIN_DONE_3 => open,
+  FFC_DIV11_MODE_TX_3 => fpsc_vlo,
+  FFC_RATE_MODE_TX_3 => tx_div2_mode_ch3_c,
+  FFC_DIV11_MODE_RX_3 => fpsc_vlo,
+  FFC_RATE_MODE_RX_3 => rx_div2_mode_ch3_c,
+
+----- Auxilliary ----
+  SCIWDATA7 => sci_wrdata(7),
+  SCIWDATA6 => sci_wrdata(6),
+  SCIWDATA5 => sci_wrdata(5),
+  SCIWDATA4 => sci_wrdata(4),
+  SCIWDATA3 => sci_wrdata(3),
+  SCIWDATA2 => sci_wrdata(2),
+  SCIWDATA1 => sci_wrdata(1),
+  SCIWDATA0 => sci_wrdata(0),
+  SCIADDR5 => sci_addr(5),
+  SCIADDR4 => sci_addr(4),
+  SCIADDR3 => sci_addr(3),
+  SCIADDR2 => sci_addr(2),
+  SCIADDR1 => sci_addr(1),
+  SCIADDR0 => sci_addr(0),
+  SCIRDATA7 => sci_rddata(7),
+  SCIRDATA6 => sci_rddata(6),
+  SCIRDATA5 => sci_rddata(5),
+  SCIRDATA4 => sci_rddata(4),
+  SCIRDATA3 => sci_rddata(3),
+  SCIRDATA2 => sci_rddata(2),
+  SCIRDATA1 => sci_rddata(1),
+  SCIRDATA0 => sci_rddata(0),
+  SCIENAUX => fpsc_vhi,
+  SCISELAUX => sci_sel_quad,
+  SCIRD => sci_rd,
+  SCIWSTN => sci_wrn,
+  CYAWSTN => fpsc_vlo,
+  SCIINT => open,
+  FFC_CK_CORE_TX => fpga_txrefclk,
+  FFC_MACRO_RST => serdes_rst_qd_c,
+  FFC_QUAD_RST => rst_qd_c,
+  FFC_TRST => tx_serdes_rst_c,
+  FFS_PLOL => tx_pll_lol_qd_sig,
+  FFC_SYNC_TOGGLE => tx_sync_qd_c,
+  REFCK2CORE => refclk2fpga_sig,
+  CIN0 => fpsc_vlo,
+  CIN1 => fpsc_vlo,
+  CIN2 => fpsc_vlo,
+  CIN3 => fpsc_vlo,
+  CIN4 => fpsc_vlo,
+  CIN5 => fpsc_vlo,
+  CIN6 => fpsc_vlo,
+  CIN7 => fpsc_vlo,
+  CIN8 => fpsc_vlo,
+  CIN9 => fpsc_vlo,
+  CIN10 => fpsc_vlo,
+  CIN11 => fpsc_vlo,
+  COUT0 => open,
+  COUT1 => open,
+  COUT2 => open,
+  COUT3 => open,
+  COUT4 => open,
+  COUT5 => open,
+  COUT6 => open,
+  COUT7 => open,
+  COUT8 => open,
+  COUT9 => open,
+  COUT10 => open,
+  COUT11 => open,
+  COUT12 => open,
+  COUT13 => open,
+  COUT14 => open,
+  COUT15 => open,
+  COUT16 => open,
+  COUT17 => open,
+  COUT18 => open,
+  COUT19 => open,
+  REFCLK_FROM_NQ => refclk_from_nq,
+  REFCLK_TO_NQ => open);
+
+                                                                                              
+                                                                                              
+                                                                                              
+--synopsys translate_off
+file_read : PROCESS
+VARIABLE open_status : file_open_status;
+FILE config : text;
+BEGIN
+   file_open (open_status, config, USER_CONFIG_FILE, read_mode);
+   IF (open_status = name_error) THEN
+      report "Auto configuration file for PCS module not found.  PCS internal configuration registers will not be initialized correctly during simulation!"
+      severity ERROR;
+   END IF;
+   wait;
+END PROCESS;
+--synopsys translate_on
+end serdes_sync_160_full_arch ;
diff --git a/data_concentrator/sources/lattice/ecp3/serdes_sync_200_full.ipx b/data_concentrator/sources/lattice/ecp3/serdes_sync_200_full.ipx
new file mode 100644
index 0000000..f19145b
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/serdes_sync_200_full.ipx
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="serdes_sync_200_full" module="serdes_sync_200_full" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 11 27 15:50:28.339" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="serdes_sync_200_full.lpc" type="lpc" modified="2014 11 27 15:50:24.795"/>
+		<File name="serdes_sync_200_full.pp" type="pp" modified="2014 11 27 15:50:24.796"/>
+		<File name="serdes_sync_200_full.sym" type="sym" modified="2014 11 27 15:50:25.058"/>
+		<File name="serdes_sync_200_full.tft" type="tft" modified="2014 11 27 15:50:24.828"/>
+		<File name="serdes_sync_200_full.txt" type="pcs_module" modified="2014 11 27 15:50:24.831"/>
+		<File name="serdes_sync_200_full.vhd" type="top_level_vhdl" modified="2014 11 27 15:50:24.827"/>
+  </Package>
+</DiamondModule>
diff --git a/data_concentrator/sources/lattice/ecp3/serdes_sync_200_full.lpc b/data_concentrator/sources/lattice/ecp3/serdes_sync_200_full.lpc
new file mode 100644
index 0000000..440ac03
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/serdes_sync_200_full.lpc
@@ -0,0 +1,258 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PCS
+CoreRevision=8.2
+ModuleName=serdes_sync_200_full
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=11/27/2014
+Time=15:50:24
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+_mode0=RXTX
+_mode1=RXTX
+_mode2=RXTX
+_mode3=RXTX
+_protocol0=G8B10B
+_protocol1=G8B10B
+_protocol2=G8B10B
+_protocol3=G8B10B
+_ldr0=DISABLED
+_ldr1=DISABLED
+_ldr2=DISABLED
+_ldr3=DISABLED
+_datarange=2
+_pll_txsrc=INTERNAL
+_refclk_mult=10X
+_refclk_rate=200
+_tx_protocol0=G8B10B
+_tx_protocol1=G8B10B
+_tx_protocol2=G8B10B
+_tx_protocol3=G8B10B
+_tx_data_rate0=FULL
+_tx_data_rate1=FULL
+_tx_data_rate2=FULL
+_tx_data_rate3=FULL
+_tx_data_width0=8
+_tx_data_width1=8
+_tx_data_width2=8
+_tx_data_width3=8
+_tx_fifo0=DISABLED
+_tx_fifo1=DISABLED
+_tx_fifo2=DISABLED
+_tx_fifo3=DISABLED
+_tx_ficlk_rate0=200
+_tx_ficlk_rate1=200
+_tx_ficlk_rate2=200
+_tx_ficlk_rate3=200
+_pll_rxsrc0=INTERNAL
+_pll_rxsrc1=INTERNAL
+_pll_rxsrc2=INTERNAL
+_pll_rxsrc3=INTERNAL
+Multiplier0=
+Multiplier1=
+Multiplier2=
+Multiplier3=
+_rx_datarange0=2
+_rx_datarange1=2
+_rx_datarange2=2
+_rx_datarange3=2
+_rx_protocol0=G8B10B
+_rx_protocol1=G8B10B
+_rx_protocol2=G8B10B
+_rx_protocol3=G8B10B
+_rx_data_rate0=FULL
+_rx_data_rate1=FULL
+_rx_data_rate2=FULL
+_rx_data_rate3=FULL
+_rxrefclk_rate0=200
+_rxrefclk_rate1=200
+_rxrefclk_rate2=200
+_rxrefclk_rate3=200
+_rx_data_width0=8
+_rx_data_width1=8
+_rx_data_width2=8
+_rx_data_width3=8
+_rx_fifo0=ENABLED
+_rx_fifo1=ENABLED
+_rx_fifo2=ENABLED
+_rx_fifo3=ENABLED
+_rx_ficlk_rate0=200
+_rx_ficlk_rate1=200
+_rx_ficlk_rate2=200
+_rx_ficlk_rate3=200
+_tdrv_ch0=1
+_tdrv_ch1=1
+_tdrv_ch2=1
+_tdrv_ch3=1
+_tx_pre0=DISABLED
+_tx_pre1=DISABLED
+_tx_pre2=DISABLED
+_tx_pre3=DISABLED
+_rterm_tx0=50
+_rterm_tx1=50
+_rterm_tx2=50
+_rterm_tx3=50
+_rx_eq0=DISABLED
+_rx_eq1=DISABLED
+_rx_eq2=DISABLED
+_rx_eq3=DISABLED
+_rterm_rx0=50
+_rterm_rx1=50
+_rterm_rx2=50
+_rterm_rx3=50
+_rx_dcc0=DC
+_rx_dcc1=DC
+_rx_dcc2=DC
+_rx_dcc3=DC
+_los_threshold_mode0=LOS_E
+_los_threshold_mode1=LOS_E
+_los_threshold_mode2=LOS_E
+_los_threshold_mode3=LOS_E
+_los_threshold_lo0=2
+_los_threshold_lo1=2
+_los_threshold_lo2=2
+_los_threshold_lo3=2
+_los_threshold_hi0=7
+_los_threshold_hi1=7
+_los_threshold_hi2=7
+_los_threshold_hi3=7
+_pll_term=50
+_pll_dcc=AC
+_pll_lol_set=1
+_tx_sb0=DISABLED
+_tx_sb1=DISABLED
+_tx_sb2=DISABLED
+_tx_sb3=DISABLED
+_tx_8b10b0=ENABLED
+_tx_8b10b1=ENABLED
+_tx_8b10b2=ENABLED
+_tx_8b10b3=ENABLED
+_rx_sb0=DISABLED
+_rx_sb1=DISABLED
+_rx_sb2=DISABLED
+_rx_sb3=DISABLED
+_ird0=DISABLED
+_ird1=DISABLED
+_ird2=DISABLED
+_ird3=DISABLED
+_rx_8b10b0=ENABLED
+_rx_8b10b1=ENABLED
+_rx_8b10b2=ENABLED
+_rx_8b10b3=ENABLED
+_rxwa0=ENABLED
+_rxwa1=ENABLED
+_rxwa2=ENABLED
+_rxwa3=ENABLED
+_ilsm0=ENABLED
+_ilsm1=ENABLED
+_ilsm2=ENABLED
+_ilsm3=ENABLED
+_scomma0=K28P157
+_scomma1=K28P157
+_scomma2=K28P157
+_scomma3=K28P157
+_comma_a0=1100000101
+_comma_a1=1100000101
+_comma_a2=1100000101
+_comma_a3=1100000101
+_comma_b0=0011111010
+_comma_b1=0011111010
+_comma_b2=0011111010
+_comma_b3=0011111010
+_comma_m0=1111111100
+_comma_m1=1111111100
+_comma_m2=1111111100
+_comma_m3=1111111100
+_ctc0=DISABLED
+_ctc1=DISABLED
+_ctc2=DISABLED
+_ctc3=DISABLED
+_cc_match_mode0=1
+_cc_match_mode1=1
+_cc_match_mode2=1
+_cc_match_mode3=1
+_k00=00
+_k01=00
+_k02=00
+_k03=00
+_k10=00
+_k11=00
+_k12=00
+_k13=00
+_k20=01
+_k21=01
+_k22=01
+_k23=01
+_k30=01
+_k31=01
+_k32=01
+_k33=01
+_byten00=00011100
+_byten01=00011100
+_byten02=00011100
+_byten03=00011100
+_byten10=00000000
+_byten11=00000000
+_byten12=00000000
+_byten13=00000000
+_byten20=00011100
+_byten21=00011100
+_byten22=00011100
+_byten23=00011100
+_byten30=00011100
+_byten31=00011100
+_byten32=00011100
+_byten33=00011100
+_cc_min_ipg0=3
+_cc_min_ipg1=3
+_cc_min_ipg2=3
+_cc_min_ipg3=3
+_cchmark=9
+_cclmark=7
+_loopback=DISABLED
+_lbtype0=DISABLED
+_lbtype1=DISABLED
+_lbtype2=DISABLED
+_lbtype3=DISABLED
+_teidle_ch0=DISABLED
+_teidle_ch1=DISABLED
+_teidle_ch2=DISABLED
+_teidle_ch3=DISABLED
+_rst_gen=DISABLED
+_rx_los_port0=Internal
+_rx_los_port1=Internal
+_rx_los_port2=Internal
+_rx_los_port3=Internal
+_sci_ports=ENABLED
+_sci_int_port=DISABLED
+_refck2core=DISABLED
+Regen=auto
+PAR1=0
+PARTrace1=0
+PAR3=0
+PARTrace3=0
+
+[FilesGenerated]
+serdes_sync_200_full.pp=pp
+serdes_sync_200_full.tft=tft
+serdes_sync_200_full.txt=pcs_module
+serdes_sync_200_full.sym=sym
diff --git a/data_concentrator/sources/lattice/ecp3/serdes_sync_200_full.vhd b/data_concentrator/sources/lattice/ecp3/serdes_sync_200_full.vhd
new file mode 100644
index 0000000..ebaeffd
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/serdes_sync_200_full.vhd
@@ -0,0 +1,2810 @@
+
+                                                                                                         
+
+--synopsys translate_off
+
+library pcsd_work;
+use pcsd_work.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity PCSD is
+GENERIC(
+  CONFIG_FILE : String;
+  QUAD_MODE : String;
+  CH0_CDR_SRC   : String := "REFCLK_EXT";
+  CH1_CDR_SRC   : String := "REFCLK_EXT";
+  CH2_CDR_SRC   : String := "REFCLK_EXT";
+  CH3_CDR_SRC   : String := "REFCLK_EXT";
+  PLL_SRC   : String
+--  CONFIG_FILE : String  := "serdes_sync_200_full.txt";
+--  QUAD_MODE : String := "SINGLE";
+--  CH0_CDR_SRC   : String := "REFCLK_CORE";
+--  CH1_CDR_SRC   : String := "REFCLK_CORE";
+--  CH2_CDR_SRC   : String := "REFCLK_CORE";
+--  CH3_CDR_SRC   : String := "REFCLK_CORE";
+--  PLL_SRC   : String := "REFCLK_CORE"
+  );
+port (
+  HDINN0             : in std_logic;
+  HDINN1             : in std_logic;
+  HDINN2             : in std_logic;
+  HDINN3             : in std_logic;
+  HDINP0             : in std_logic;
+  HDINP1             : in std_logic;
+  HDINP2             : in std_logic;
+  HDINP3             : in std_logic;
+  REFCLKN             : in std_logic;
+  REFCLKP             : in std_logic;
+  CIN0             : in std_logic;
+  CIN1             : in std_logic;
+  CIN2             : in std_logic;
+  CIN3             : in std_logic;
+  CIN4             : in std_logic;
+  CIN5             : in std_logic;
+  CIN6             : in std_logic;
+  CIN7             : in std_logic;
+  CIN8             : in std_logic;
+  CIN9             : in std_logic;
+  CIN10             : in std_logic;
+  CIN11             : in std_logic;
+  CYAWSTN             : in std_logic;
+  FF_EBRD_CLK_0             : in std_logic;
+  FF_EBRD_CLK_1             : in std_logic;
+  FF_EBRD_CLK_2             : in std_logic;
+  FF_EBRD_CLK_3             : in std_logic;
+  FF_RXI_CLK_0             : in std_logic;
+  FF_RXI_CLK_1             : in std_logic;
+  FF_RXI_CLK_2             : in std_logic;
+  FF_RXI_CLK_3             : in std_logic;
+  FF_TX_D_0_0             : in std_logic;
+  FF_TX_D_0_1             : in std_logic;
+  FF_TX_D_0_2             : in std_logic;
+  FF_TX_D_0_3             : in std_logic;
+  FF_TX_D_0_4             : in std_logic;
+  FF_TX_D_0_5             : in std_logic;
+  FF_TX_D_0_6             : in std_logic;
+  FF_TX_D_0_7             : in std_logic;
+  FF_TX_D_0_8             : in std_logic;
+  FF_TX_D_0_9             : in std_logic;
+  FF_TX_D_0_10             : in std_logic;
+  FF_TX_D_0_11             : in std_logic;
+  FF_TX_D_0_12             : in std_logic;
+  FF_TX_D_0_13             : in std_logic;
+  FF_TX_D_0_14             : in std_logic;
+  FF_TX_D_0_15             : in std_logic;
+  FF_TX_D_0_16             : in std_logic;
+  FF_TX_D_0_17             : in std_logic;
+  FF_TX_D_0_18             : in std_logic;
+  FF_TX_D_0_19             : in std_logic;
+  FF_TX_D_0_20             : in std_logic;
+  FF_TX_D_0_21             : in std_logic;
+  FF_TX_D_0_22             : in std_logic;
+  FF_TX_D_0_23             : in std_logic;
+  FF_TX_D_1_0             : in std_logic;
+  FF_TX_D_1_1             : in std_logic;
+  FF_TX_D_1_2             : in std_logic;
+  FF_TX_D_1_3             : in std_logic;
+  FF_TX_D_1_4             : in std_logic;
+  FF_TX_D_1_5             : in std_logic;
+  FF_TX_D_1_6             : in std_logic;
+  FF_TX_D_1_7             : in std_logic;
+  FF_TX_D_1_8             : in std_logic;
+  FF_TX_D_1_9             : in std_logic;
+  FF_TX_D_1_10             : in std_logic;
+  FF_TX_D_1_11             : in std_logic;
+  FF_TX_D_1_12             : in std_logic;
+  FF_TX_D_1_13             : in std_logic;
+  FF_TX_D_1_14             : in std_logic;
+  FF_TX_D_1_15             : in std_logic;
+  FF_TX_D_1_16             : in std_logic;
+  FF_TX_D_1_17             : in std_logic;
+  FF_TX_D_1_18             : in std_logic;
+  FF_TX_D_1_19             : in std_logic;
+  FF_TX_D_1_20             : in std_logic;
+  FF_TX_D_1_21             : in std_logic;
+  FF_TX_D_1_22             : in std_logic;
+  FF_TX_D_1_23             : in std_logic;
+  FF_TX_D_2_0             : in std_logic;
+  FF_TX_D_2_1             : in std_logic;
+  FF_TX_D_2_2             : in std_logic;
+  FF_TX_D_2_3             : in std_logic;
+  FF_TX_D_2_4             : in std_logic;
+  FF_TX_D_2_5             : in std_logic;
+  FF_TX_D_2_6             : in std_logic;
+  FF_TX_D_2_7             : in std_logic;
+  FF_TX_D_2_8             : in std_logic;
+  FF_TX_D_2_9             : in std_logic;
+  FF_TX_D_2_10             : in std_logic;
+  FF_TX_D_2_11             : in std_logic;
+  FF_TX_D_2_12             : in std_logic;
+  FF_TX_D_2_13             : in std_logic;
+  FF_TX_D_2_14             : in std_logic;
+  FF_TX_D_2_15             : in std_logic;
+  FF_TX_D_2_16             : in std_logic;
+  FF_TX_D_2_17             : in std_logic;
+  FF_TX_D_2_18             : in std_logic;
+  FF_TX_D_2_19             : in std_logic;
+  FF_TX_D_2_20             : in std_logic;
+  FF_TX_D_2_21             : in std_logic;
+  FF_TX_D_2_22             : in std_logic;
+  FF_TX_D_2_23             : in std_logic;
+  FF_TX_D_3_0             : in std_logic;
+  FF_TX_D_3_1             : in std_logic;
+  FF_TX_D_3_2             : in std_logic;
+  FF_TX_D_3_3             : in std_logic;
+  FF_TX_D_3_4             : in std_logic;
+  FF_TX_D_3_5             : in std_logic;
+  FF_TX_D_3_6             : in std_logic;
+  FF_TX_D_3_7             : in std_logic;
+  FF_TX_D_3_8             : in std_logic;
+  FF_TX_D_3_9             : in std_logic;
+  FF_TX_D_3_10             : in std_logic;
+  FF_TX_D_3_11             : in std_logic;
+  FF_TX_D_3_12             : in std_logic;
+  FF_TX_D_3_13             : in std_logic;
+  FF_TX_D_3_14             : in std_logic;
+  FF_TX_D_3_15             : in std_logic;
+  FF_TX_D_3_16             : in std_logic;
+  FF_TX_D_3_17             : in std_logic;
+  FF_TX_D_3_18             : in std_logic;
+  FF_TX_D_3_19             : in std_logic;
+  FF_TX_D_3_20             : in std_logic;
+  FF_TX_D_3_21             : in std_logic;
+  FF_TX_D_3_22             : in std_logic;
+  FF_TX_D_3_23             : in std_logic;
+  FF_TXI_CLK_0             : in std_logic;
+  FF_TXI_CLK_1             : in std_logic;
+  FF_TXI_CLK_2             : in std_logic;
+  FF_TXI_CLK_3             : in std_logic;
+  FFC_CK_CORE_RX_0         : in std_logic;
+  FFC_CK_CORE_RX_1         : in std_logic;
+  FFC_CK_CORE_RX_2         : in std_logic;
+  FFC_CK_CORE_RX_3         : in std_logic;
+  FFC_CK_CORE_TX           : in std_logic;
+  FFC_EI_EN_0             : in std_logic;
+  FFC_EI_EN_1             : in std_logic;
+  FFC_EI_EN_2             : in std_logic;
+  FFC_EI_EN_3             : in std_logic;
+  FFC_ENABLE_CGALIGN_0             : in std_logic;
+  FFC_ENABLE_CGALIGN_1             : in std_logic;
+  FFC_ENABLE_CGALIGN_2             : in std_logic;
+  FFC_ENABLE_CGALIGN_3             : in std_logic;
+  FFC_FB_LOOPBACK_0             : in std_logic;
+  FFC_FB_LOOPBACK_1             : in std_logic;
+  FFC_FB_LOOPBACK_2             : in std_logic;
+  FFC_FB_LOOPBACK_3             : in std_logic;
+  FFC_LANE_RX_RST_0             : in std_logic;
+  FFC_LANE_RX_RST_1             : in std_logic;
+  FFC_LANE_RX_RST_2             : in std_logic;
+  FFC_LANE_RX_RST_3             : in std_logic;
+  FFC_LANE_TX_RST_0             : in std_logic;
+  FFC_LANE_TX_RST_1             : in std_logic;
+  FFC_LANE_TX_RST_2             : in std_logic;
+  FFC_LANE_TX_RST_3             : in std_logic;
+  FFC_MACRO_RST             : in std_logic;
+  FFC_PCI_DET_EN_0             : in std_logic;
+  FFC_PCI_DET_EN_1             : in std_logic;
+  FFC_PCI_DET_EN_2             : in std_logic;
+  FFC_PCI_DET_EN_3             : in std_logic;
+  FFC_PCIE_CT_0             : in std_logic;
+  FFC_PCIE_CT_1             : in std_logic;
+  FFC_PCIE_CT_2             : in std_logic;
+  FFC_PCIE_CT_3             : in std_logic;
+  FFC_PFIFO_CLR_0             : in std_logic;
+  FFC_PFIFO_CLR_1             : in std_logic;
+  FFC_PFIFO_CLR_2             : in std_logic;
+  FFC_PFIFO_CLR_3             : in std_logic;
+  FFC_QUAD_RST             : in std_logic;
+  FFC_RRST_0             : in std_logic;
+  FFC_RRST_1             : in std_logic;
+  FFC_RRST_2             : in std_logic;
+  FFC_RRST_3             : in std_logic;
+  FFC_RXPWDNB_0             : in std_logic;
+  FFC_RXPWDNB_1             : in std_logic;
+  FFC_RXPWDNB_2             : in std_logic;
+  FFC_RXPWDNB_3             : in std_logic;
+  FFC_SB_INV_RX_0             : in std_logic;
+  FFC_SB_INV_RX_1             : in std_logic;
+  FFC_SB_INV_RX_2             : in std_logic;
+  FFC_SB_INV_RX_3             : in std_logic;
+  FFC_SB_PFIFO_LP_0             : in std_logic;
+  FFC_SB_PFIFO_LP_1             : in std_logic;
+  FFC_SB_PFIFO_LP_2             : in std_logic;
+  FFC_SB_PFIFO_LP_3             : in std_logic;
+  FFC_SIGNAL_DETECT_0             : in std_logic;
+  FFC_SIGNAL_DETECT_1             : in std_logic;
+  FFC_SIGNAL_DETECT_2             : in std_logic;
+  FFC_SIGNAL_DETECT_3             : in std_logic;
+  FFC_SYNC_TOGGLE             : in std_logic;
+  FFC_TRST             : in std_logic;
+  FFC_TXPWDNB_0             : in std_logic;
+  FFC_TXPWDNB_1             : in std_logic;
+  FFC_TXPWDNB_2             : in std_logic;
+  FFC_TXPWDNB_3             : in std_logic;
+  FFC_RATE_MODE_RX_0        : in std_logic;
+  FFC_RATE_MODE_RX_1        : in std_logic;
+  FFC_RATE_MODE_RX_2        : in std_logic;
+  FFC_RATE_MODE_RX_3        : in std_logic;
+  FFC_RATE_MODE_TX_0        : in std_logic;
+  FFC_RATE_MODE_TX_1        : in std_logic;
+  FFC_RATE_MODE_TX_2        : in std_logic;
+  FFC_RATE_MODE_TX_3        : in std_logic;
+  FFC_DIV11_MODE_RX_0       : in std_logic;
+  FFC_DIV11_MODE_RX_1       : in std_logic;
+  FFC_DIV11_MODE_RX_2       : in std_logic;
+  FFC_DIV11_MODE_RX_3       : in std_logic;
+  FFC_DIV11_MODE_TX_0       : in std_logic;
+  FFC_DIV11_MODE_TX_1       : in std_logic;
+  FFC_DIV11_MODE_TX_2       : in std_logic;
+  FFC_DIV11_MODE_TX_3       : in std_logic;
+  LDR_CORE2TX_0             : in std_logic;
+  LDR_CORE2TX_1             : in std_logic;
+  LDR_CORE2TX_2             : in std_logic;
+  LDR_CORE2TX_3             : in std_logic;
+  FFC_LDR_CORE2TX_EN_0      : in std_logic;
+  FFC_LDR_CORE2TX_EN_1      : in std_logic;
+  FFC_LDR_CORE2TX_EN_2      : in std_logic;
+  FFC_LDR_CORE2TX_EN_3      : in std_logic;
+  PCIE_POWERDOWN_0_0      : in std_logic;
+  PCIE_POWERDOWN_0_1      : in std_logic;
+  PCIE_POWERDOWN_1_0      : in std_logic;
+  PCIE_POWERDOWN_1_1      : in std_logic;
+  PCIE_POWERDOWN_2_0      : in std_logic;
+  PCIE_POWERDOWN_2_1      : in std_logic;
+  PCIE_POWERDOWN_3_0      : in std_logic;
+  PCIE_POWERDOWN_3_1      : in std_logic;
+  PCIE_RXPOLARITY_0         : in std_logic;
+  PCIE_RXPOLARITY_1         : in std_logic;
+  PCIE_RXPOLARITY_2         : in std_logic;
+  PCIE_RXPOLARITY_3         : in std_logic;
+  PCIE_TXCOMPLIANCE_0       : in std_logic;
+  PCIE_TXCOMPLIANCE_1       : in std_logic;
+  PCIE_TXCOMPLIANCE_2       : in std_logic;
+  PCIE_TXCOMPLIANCE_3       : in std_logic;
+  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
+  SCIADDR0             : in std_logic;
+  SCIADDR1             : in std_logic;
+  SCIADDR2             : in std_logic;
+  SCIADDR3             : in std_logic;
+  SCIADDR4             : in std_logic;
+  SCIADDR5             : in std_logic;
+  SCIENAUX             : in std_logic;
+  SCIENCH0             : in std_logic;
+  SCIENCH1             : in std_logic;
+  SCIENCH2             : in std_logic;
+  SCIENCH3             : in std_logic;
+  SCIRD                : in std_logic;
+  SCISELAUX             : in std_logic;
+  SCISELCH0             : in std_logic;
+  SCISELCH1             : in std_logic;
+  SCISELCH2             : in std_logic;
+  SCISELCH3             : in std_logic;
+  SCIWDATA0             : in std_logic;
+  SCIWDATA1             : in std_logic;
+  SCIWDATA2             : in std_logic;
+  SCIWDATA3             : in std_logic;
+  SCIWDATA4             : in std_logic;
+  SCIWDATA5             : in std_logic;
+  SCIWDATA6             : in std_logic;
+  SCIWDATA7             : in std_logic;
+  SCIWSTN               : in std_logic;
+  REFCLK_FROM_NQ        : in std_logic;
+
+  HDOUTN0             : out std_logic;
+  HDOUTN1             : out std_logic;
+  HDOUTN2             : out std_logic;
+  HDOUTN3             : out std_logic;
+  HDOUTP0             : out std_logic;
+  HDOUTP1             : out std_logic;
+  HDOUTP2             : out std_logic;
+  HDOUTP3             : out std_logic;
+  COUT0             : out std_logic;
+  COUT1             : out std_logic;
+  COUT2             : out std_logic;
+  COUT3             : out std_logic;
+  COUT4             : out std_logic;
+  COUT5             : out std_logic;
+  COUT6             : out std_logic;
+  COUT7             : out std_logic;
+  COUT8             : out std_logic;
+  COUT9             : out std_logic;
+  COUT10             : out std_logic;
+  COUT11             : out std_logic;
+  COUT12             : out std_logic;
+  COUT13             : out std_logic;
+  COUT14             : out std_logic;
+  COUT15             : out std_logic;
+  COUT16             : out std_logic;
+  COUT17             : out std_logic;
+  COUT18             : out std_logic;
+  COUT19             : out std_logic;
+  FF_RX_D_0_0             : out std_logic;
+  FF_RX_D_0_1             : out std_logic;
+  FF_RX_D_0_2             : out std_logic;
+  FF_RX_D_0_3             : out std_logic;
+  FF_RX_D_0_4             : out std_logic;
+  FF_RX_D_0_5             : out std_logic;
+  FF_RX_D_0_6             : out std_logic;
+  FF_RX_D_0_7             : out std_logic;
+  FF_RX_D_0_8             : out std_logic;
+  FF_RX_D_0_9             : out std_logic;
+  FF_RX_D_0_10             : out std_logic;
+  FF_RX_D_0_11             : out std_logic;
+  FF_RX_D_0_12             : out std_logic;
+  FF_RX_D_0_13             : out std_logic;
+  FF_RX_D_0_14             : out std_logic;
+  FF_RX_D_0_15             : out std_logic;
+  FF_RX_D_0_16             : out std_logic;
+  FF_RX_D_0_17             : out std_logic;
+  FF_RX_D_0_18             : out std_logic;
+  FF_RX_D_0_19             : out std_logic;
+  FF_RX_D_0_20             : out std_logic;
+  FF_RX_D_0_21             : out std_logic;
+  FF_RX_D_0_22             : out std_logic;
+  FF_RX_D_0_23             : out std_logic;
+  FF_RX_D_1_0             : out std_logic;
+  FF_RX_D_1_1             : out std_logic;
+  FF_RX_D_1_2             : out std_logic;
+  FF_RX_D_1_3             : out std_logic;
+  FF_RX_D_1_4             : out std_logic;
+  FF_RX_D_1_5             : out std_logic;
+  FF_RX_D_1_6             : out std_logic;
+  FF_RX_D_1_7             : out std_logic;
+  FF_RX_D_1_8             : out std_logic;
+  FF_RX_D_1_9             : out std_logic;
+  FF_RX_D_1_10             : out std_logic;
+  FF_RX_D_1_11             : out std_logic;
+  FF_RX_D_1_12             : out std_logic;
+  FF_RX_D_1_13             : out std_logic;
+  FF_RX_D_1_14             : out std_logic;
+  FF_RX_D_1_15             : out std_logic;
+  FF_RX_D_1_16             : out std_logic;
+  FF_RX_D_1_17             : out std_logic;
+  FF_RX_D_1_18             : out std_logic;
+  FF_RX_D_1_19             : out std_logic;
+  FF_RX_D_1_20             : out std_logic;
+  FF_RX_D_1_21             : out std_logic;
+  FF_RX_D_1_22             : out std_logic;
+  FF_RX_D_1_23             : out std_logic;
+  FF_RX_D_2_0             : out std_logic;
+  FF_RX_D_2_1             : out std_logic;
+  FF_RX_D_2_2             : out std_logic;
+  FF_RX_D_2_3             : out std_logic;
+  FF_RX_D_2_4             : out std_logic;
+  FF_RX_D_2_5             : out std_logic;
+  FF_RX_D_2_6             : out std_logic;
+  FF_RX_D_2_7             : out std_logic;
+  FF_RX_D_2_8             : out std_logic;
+  FF_RX_D_2_9             : out std_logic;
+  FF_RX_D_2_10             : out std_logic;
+  FF_RX_D_2_11             : out std_logic;
+  FF_RX_D_2_12             : out std_logic;
+  FF_RX_D_2_13             : out std_logic;
+  FF_RX_D_2_14             : out std_logic;
+  FF_RX_D_2_15             : out std_logic;
+  FF_RX_D_2_16             : out std_logic;
+  FF_RX_D_2_17             : out std_logic;
+  FF_RX_D_2_18             : out std_logic;
+  FF_RX_D_2_19             : out std_logic;
+  FF_RX_D_2_20             : out std_logic;
+  FF_RX_D_2_21             : out std_logic;
+  FF_RX_D_2_22             : out std_logic;
+  FF_RX_D_2_23             : out std_logic;
+  FF_RX_D_3_0             : out std_logic;
+  FF_RX_D_3_1             : out std_logic;
+  FF_RX_D_3_2             : out std_logic;
+  FF_RX_D_3_3             : out std_logic;
+  FF_RX_D_3_4             : out std_logic;
+  FF_RX_D_3_5             : out std_logic;
+  FF_RX_D_3_6             : out std_logic;
+  FF_RX_D_3_7             : out std_logic;
+  FF_RX_D_3_8             : out std_logic;
+  FF_RX_D_3_9             : out std_logic;
+  FF_RX_D_3_10             : out std_logic;
+  FF_RX_D_3_11             : out std_logic;
+  FF_RX_D_3_12             : out std_logic;
+  FF_RX_D_3_13             : out std_logic;
+  FF_RX_D_3_14             : out std_logic;
+  FF_RX_D_3_15             : out std_logic;
+  FF_RX_D_3_16             : out std_logic;
+  FF_RX_D_3_17             : out std_logic;
+  FF_RX_D_3_18             : out std_logic;
+  FF_RX_D_3_19             : out std_logic;
+  FF_RX_D_3_20             : out std_logic;
+  FF_RX_D_3_21             : out std_logic;
+  FF_RX_D_3_22             : out std_logic;
+  FF_RX_D_3_23             : out std_logic;
+  FF_RX_F_CLK_0             : out std_logic;
+  FF_RX_F_CLK_1             : out std_logic;
+  FF_RX_F_CLK_2             : out std_logic;
+  FF_RX_F_CLK_3             : out std_logic;
+  FF_RX_H_CLK_0             : out std_logic;
+  FF_RX_H_CLK_1             : out std_logic;
+  FF_RX_H_CLK_2             : out std_logic;
+  FF_RX_H_CLK_3             : out std_logic;
+  FF_TX_F_CLK_0             : out std_logic;
+  FF_TX_F_CLK_1             : out std_logic;
+  FF_TX_F_CLK_2             : out std_logic;
+  FF_TX_F_CLK_3             : out std_logic;
+  FF_TX_H_CLK_0             : out std_logic;
+  FF_TX_H_CLK_1             : out std_logic;
+  FF_TX_H_CLK_2             : out std_logic;
+  FF_TX_H_CLK_3             : out std_logic;
+  FFS_CC_OVERRUN_0             : out std_logic;
+  FFS_CC_OVERRUN_1             : out std_logic;
+  FFS_CC_OVERRUN_2             : out std_logic;
+  FFS_CC_OVERRUN_3             : out std_logic;
+  FFS_CC_UNDERRUN_0             : out std_logic;
+  FFS_CC_UNDERRUN_1             : out std_logic;
+  FFS_CC_UNDERRUN_2             : out std_logic;
+  FFS_CC_UNDERRUN_3             : out std_logic;
+  FFS_LS_SYNC_STATUS_0             : out std_logic;
+  FFS_LS_SYNC_STATUS_1             : out std_logic;
+  FFS_LS_SYNC_STATUS_2             : out std_logic;
+  FFS_LS_SYNC_STATUS_3             : out std_logic;
+  FFS_CDR_TRAIN_DONE_0             : out std_logic;
+  FFS_CDR_TRAIN_DONE_1             : out std_logic;
+  FFS_CDR_TRAIN_DONE_2             : out std_logic;
+  FFS_CDR_TRAIN_DONE_3             : out std_logic;
+  FFS_PCIE_CON_0             : out std_logic;
+  FFS_PCIE_CON_1             : out std_logic;
+  FFS_PCIE_CON_2             : out std_logic;
+  FFS_PCIE_CON_3             : out std_logic;
+  FFS_PCIE_DONE_0             : out std_logic;
+  FFS_PCIE_DONE_1             : out std_logic;
+  FFS_PCIE_DONE_2             : out std_logic;
+  FFS_PCIE_DONE_3             : out std_logic;
+  FFS_PLOL             : out std_logic;
+  FFS_RLOL_0             : out std_logic;
+  FFS_RLOL_1             : out std_logic;
+  FFS_RLOL_2             : out std_logic;
+  FFS_RLOL_3             : out std_logic;
+  FFS_RLOS_HI_0             : out std_logic;
+  FFS_RLOS_HI_1             : out std_logic;
+  FFS_RLOS_HI_2             : out std_logic;
+  FFS_RLOS_HI_3             : out std_logic;
+  FFS_RLOS_LO_0             : out std_logic;
+  FFS_RLOS_LO_1             : out std_logic;
+  FFS_RLOS_LO_2             : out std_logic;
+  FFS_RLOS_LO_3             : out std_logic;
+  FFS_RXFBFIFO_ERROR_0             : out std_logic;
+  FFS_RXFBFIFO_ERROR_1             : out std_logic;
+  FFS_RXFBFIFO_ERROR_2             : out std_logic;
+  FFS_RXFBFIFO_ERROR_3             : out std_logic;
+  FFS_TXFBFIFO_ERROR_0             : out std_logic;
+  FFS_TXFBFIFO_ERROR_1             : out std_logic;
+  FFS_TXFBFIFO_ERROR_2             : out std_logic;
+  FFS_TXFBFIFO_ERROR_3             : out std_logic;
+  PCIE_PHYSTATUS_0             : out std_logic;
+  PCIE_PHYSTATUS_1             : out std_logic;
+  PCIE_PHYSTATUS_2             : out std_logic;
+  PCIE_PHYSTATUS_3             : out std_logic;
+  PCIE_RXVALID_0               : out std_logic;
+  PCIE_RXVALID_1               : out std_logic;
+  PCIE_RXVALID_2               : out std_logic;
+  PCIE_RXVALID_3               : out std_logic;
+  FFS_SKP_ADDED_0                  : out std_logic;
+  FFS_SKP_ADDED_1                  : out std_logic;
+  FFS_SKP_ADDED_2                  : out std_logic;
+  FFS_SKP_ADDED_3                  : out std_logic;
+  FFS_SKP_DELETED_0                : out std_logic;
+  FFS_SKP_DELETED_1                : out std_logic;
+  FFS_SKP_DELETED_2                : out std_logic;
+  FFS_SKP_DELETED_3                : out std_logic;
+  LDR_RX2CORE_0                    : out std_logic;
+  LDR_RX2CORE_1                    : out std_logic;
+  LDR_RX2CORE_2                    : out std_logic;
+  LDR_RX2CORE_3                    : out std_logic;
+  REFCK2CORE             : out std_logic;
+  SCIINT                : out std_logic;
+  SCIRDATA0             : out std_logic;
+  SCIRDATA1             : out std_logic;
+  SCIRDATA2             : out std_logic;
+  SCIRDATA3             : out std_logic;
+  SCIRDATA4             : out std_logic;
+  SCIRDATA5             : out std_logic;
+  SCIRDATA6             : out std_logic;
+  SCIRDATA7             : out std_logic;
+  REFCLK_TO_NQ          : out std_logic
+);
+
+end PCSD;
+
+architecture PCSD_arch of PCSD is
+
+
+component PCSD_sim
+GENERIC(
+  CONFIG_FILE : String;
+  QUAD_MODE : String;
+  CH0_CDR_SRC   : String;
+  CH1_CDR_SRC   : String;
+  CH2_CDR_SRC   : String;
+  CH3_CDR_SRC   : String;
+  PLL_SRC   : String
+  );
+port (
+  HDINN0             : in std_logic;
+  HDINN1             : in std_logic;
+  HDINN2             : in std_logic;
+  HDINN3             : in std_logic;
+  HDINP0             : in std_logic;
+  HDINP1             : in std_logic;
+  HDINP2             : in std_logic;
+  HDINP3             : in std_logic;
+  REFCLKN             : in std_logic;
+  REFCLKP             : in std_logic;
+  CIN0             : in std_logic;
+  CIN1             : in std_logic;
+  CIN2             : in std_logic;
+  CIN3             : in std_logic;
+  CIN4             : in std_logic;
+  CIN5             : in std_logic;
+  CIN6             : in std_logic;
+  CIN7             : in std_logic;
+  CIN8             : in std_logic;
+  CIN9             : in std_logic;
+  CIN10             : in std_logic;
+  CIN11             : in std_logic;
+  CYAWSTN             : in std_logic;
+  FF_EBRD_CLK_0             : in std_logic;
+  FF_EBRD_CLK_1             : in std_logic;
+  FF_EBRD_CLK_2             : in std_logic;
+  FF_EBRD_CLK_3             : in std_logic;
+  FF_RXI_CLK_0             : in std_logic;
+  FF_RXI_CLK_1             : in std_logic;
+  FF_RXI_CLK_2             : in std_logic;
+  FF_RXI_CLK_3             : in std_logic;
+  FF_TX_D_0_0             : in std_logic;
+  FF_TX_D_0_1             : in std_logic;
+  FF_TX_D_0_2             : in std_logic;
+  FF_TX_D_0_3             : in std_logic;
+  FF_TX_D_0_4             : in std_logic;
+  FF_TX_D_0_5             : in std_logic;
+  FF_TX_D_0_6             : in std_logic;
+  FF_TX_D_0_7             : in std_logic;
+  FF_TX_D_0_8             : in std_logic;
+  FF_TX_D_0_9             : in std_logic;
+  FF_TX_D_0_10             : in std_logic;
+  FF_TX_D_0_11             : in std_logic;
+  FF_TX_D_0_12             : in std_logic;
+  FF_TX_D_0_13             : in std_logic;
+  FF_TX_D_0_14             : in std_logic;
+  FF_TX_D_0_15             : in std_logic;
+  FF_TX_D_0_16             : in std_logic;
+  FF_TX_D_0_17             : in std_logic;
+  FF_TX_D_0_18             : in std_logic;
+  FF_TX_D_0_19             : in std_logic;
+  FF_TX_D_0_20             : in std_logic;
+  FF_TX_D_0_21             : in std_logic;
+  FF_TX_D_0_22             : in std_logic;
+  FF_TX_D_0_23             : in std_logic;
+  FF_TX_D_1_0             : in std_logic;
+  FF_TX_D_1_1             : in std_logic;
+  FF_TX_D_1_2             : in std_logic;
+  FF_TX_D_1_3             : in std_logic;
+  FF_TX_D_1_4             : in std_logic;
+  FF_TX_D_1_5             : in std_logic;
+  FF_TX_D_1_6             : in std_logic;
+  FF_TX_D_1_7             : in std_logic;
+  FF_TX_D_1_8             : in std_logic;
+  FF_TX_D_1_9             : in std_logic;
+  FF_TX_D_1_10             : in std_logic;
+  FF_TX_D_1_11             : in std_logic;
+  FF_TX_D_1_12             : in std_logic;
+  FF_TX_D_1_13             : in std_logic;
+  FF_TX_D_1_14             : in std_logic;
+  FF_TX_D_1_15             : in std_logic;
+  FF_TX_D_1_16             : in std_logic;
+  FF_TX_D_1_17             : in std_logic;
+  FF_TX_D_1_18             : in std_logic;
+  FF_TX_D_1_19             : in std_logic;
+  FF_TX_D_1_20             : in std_logic;
+  FF_TX_D_1_21             : in std_logic;
+  FF_TX_D_1_22             : in std_logic;
+  FF_TX_D_1_23             : in std_logic;
+  FF_TX_D_2_0             : in std_logic;
+  FF_TX_D_2_1             : in std_logic;
+  FF_TX_D_2_2             : in std_logic;
+  FF_TX_D_2_3             : in std_logic;
+  FF_TX_D_2_4             : in std_logic;
+  FF_TX_D_2_5             : in std_logic;
+  FF_TX_D_2_6             : in std_logic;
+  FF_TX_D_2_7             : in std_logic;
+  FF_TX_D_2_8             : in std_logic;
+  FF_TX_D_2_9             : in std_logic;
+  FF_TX_D_2_10             : in std_logic;
+  FF_TX_D_2_11             : in std_logic;
+  FF_TX_D_2_12             : in std_logic;
+  FF_TX_D_2_13             : in std_logic;
+  FF_TX_D_2_14             : in std_logic;
+  FF_TX_D_2_15             : in std_logic;
+  FF_TX_D_2_16             : in std_logic;
+  FF_TX_D_2_17             : in std_logic;
+  FF_TX_D_2_18             : in std_logic;
+  FF_TX_D_2_19             : in std_logic;
+  FF_TX_D_2_20             : in std_logic;
+  FF_TX_D_2_21             : in std_logic;
+  FF_TX_D_2_22             : in std_logic;
+  FF_TX_D_2_23             : in std_logic;
+  FF_TX_D_3_0             : in std_logic;
+  FF_TX_D_3_1             : in std_logic;
+  FF_TX_D_3_2             : in std_logic;
+  FF_TX_D_3_3             : in std_logic;
+  FF_TX_D_3_4             : in std_logic;
+  FF_TX_D_3_5             : in std_logic;
+  FF_TX_D_3_6             : in std_logic;
+  FF_TX_D_3_7             : in std_logic;
+  FF_TX_D_3_8             : in std_logic;
+  FF_TX_D_3_9             : in std_logic;
+  FF_TX_D_3_10             : in std_logic;
+  FF_TX_D_3_11             : in std_logic;
+  FF_TX_D_3_12             : in std_logic;
+  FF_TX_D_3_13             : in std_logic;
+  FF_TX_D_3_14             : in std_logic;
+  FF_TX_D_3_15             : in std_logic;
+  FF_TX_D_3_16             : in std_logic;
+  FF_TX_D_3_17             : in std_logic;
+  FF_TX_D_3_18             : in std_logic;
+  FF_TX_D_3_19             : in std_logic;
+  FF_TX_D_3_20             : in std_logic;
+  FF_TX_D_3_21             : in std_logic;
+  FF_TX_D_3_22             : in std_logic;
+  FF_TX_D_3_23             : in std_logic;
+  FF_TXI_CLK_0             : in std_logic;
+  FF_TXI_CLK_1             : in std_logic;
+  FF_TXI_CLK_2             : in std_logic;
+  FF_TXI_CLK_3             : in std_logic;
+  FFC_CK_CORE_RX_0         : in std_logic;
+  FFC_CK_CORE_RX_1         : in std_logic;
+  FFC_CK_CORE_RX_2         : in std_logic;
+  FFC_CK_CORE_RX_3         : in std_logic;
+  FFC_CK_CORE_TX           : in std_logic;
+  FFC_EI_EN_0             : in std_logic;
+  FFC_EI_EN_1             : in std_logic;
+  FFC_EI_EN_2             : in std_logic;
+  FFC_EI_EN_3             : in std_logic;
+  FFC_ENABLE_CGALIGN_0             : in std_logic;
+  FFC_ENABLE_CGALIGN_1             : in std_logic;
+  FFC_ENABLE_CGALIGN_2             : in std_logic;
+  FFC_ENABLE_CGALIGN_3             : in std_logic;
+  FFC_FB_LOOPBACK_0             : in std_logic;
+  FFC_FB_LOOPBACK_1             : in std_logic;
+  FFC_FB_LOOPBACK_2             : in std_logic;
+  FFC_FB_LOOPBACK_3             : in std_logic;
+  FFC_LANE_RX_RST_0             : in std_logic;
+  FFC_LANE_RX_RST_1             : in std_logic;
+  FFC_LANE_RX_RST_2             : in std_logic;
+  FFC_LANE_RX_RST_3             : in std_logic;
+  FFC_LANE_TX_RST_0             : in std_logic;
+  FFC_LANE_TX_RST_1             : in std_logic;
+  FFC_LANE_TX_RST_2             : in std_logic;
+  FFC_LANE_TX_RST_3             : in std_logic;
+  FFC_MACRO_RST             : in std_logic;
+  FFC_PCI_DET_EN_0             : in std_logic;
+  FFC_PCI_DET_EN_1             : in std_logic;
+  FFC_PCI_DET_EN_2             : in std_logic;
+  FFC_PCI_DET_EN_3             : in std_logic;
+  FFC_PCIE_CT_0             : in std_logic;
+  FFC_PCIE_CT_1             : in std_logic;
+  FFC_PCIE_CT_2             : in std_logic;
+  FFC_PCIE_CT_3             : in std_logic;
+  FFC_PFIFO_CLR_0             : in std_logic;
+  FFC_PFIFO_CLR_1             : in std_logic;
+  FFC_PFIFO_CLR_2             : in std_logic;
+  FFC_PFIFO_CLR_3             : in std_logic;
+  FFC_QUAD_RST             : in std_logic;
+  FFC_RRST_0             : in std_logic;
+  FFC_RRST_1             : in std_logic;
+  FFC_RRST_2             : in std_logic;
+  FFC_RRST_3             : in std_logic;
+  FFC_RXPWDNB_0             : in std_logic;
+  FFC_RXPWDNB_1             : in std_logic;
+  FFC_RXPWDNB_2             : in std_logic;
+  FFC_RXPWDNB_3             : in std_logic;
+  FFC_SB_INV_RX_0             : in std_logic;
+  FFC_SB_INV_RX_1             : in std_logic;
+  FFC_SB_INV_RX_2             : in std_logic;
+  FFC_SB_INV_RX_3             : in std_logic;
+  FFC_SB_PFIFO_LP_0             : in std_logic;
+  FFC_SB_PFIFO_LP_1             : in std_logic;
+  FFC_SB_PFIFO_LP_2             : in std_logic;
+  FFC_SB_PFIFO_LP_3             : in std_logic;
+  FFC_SIGNAL_DETECT_0             : in std_logic;
+  FFC_SIGNAL_DETECT_1             : in std_logic;
+  FFC_SIGNAL_DETECT_2             : in std_logic;
+  FFC_SIGNAL_DETECT_3             : in std_logic;
+  FFC_SYNC_TOGGLE             : in std_logic;
+  FFC_TRST             : in std_logic;
+  FFC_TXPWDNB_0             : in std_logic;
+  FFC_TXPWDNB_1             : in std_logic;
+  FFC_TXPWDNB_2             : in std_logic;
+  FFC_TXPWDNB_3             : in std_logic;
+  FFC_RATE_MODE_RX_0        : in std_logic;
+  FFC_RATE_MODE_RX_1        : in std_logic;
+  FFC_RATE_MODE_RX_2        : in std_logic;
+  FFC_RATE_MODE_RX_3        : in std_logic;
+  FFC_RATE_MODE_TX_0        : in std_logic;
+  FFC_RATE_MODE_TX_1        : in std_logic;
+  FFC_RATE_MODE_TX_2        : in std_logic;
+  FFC_RATE_MODE_TX_3        : in std_logic;
+  FFC_DIV11_MODE_RX_0       : in std_logic;
+  FFC_DIV11_MODE_RX_1       : in std_logic;
+  FFC_DIV11_MODE_RX_2       : in std_logic;
+  FFC_DIV11_MODE_RX_3       : in std_logic;
+  FFC_DIV11_MODE_TX_0       : in std_logic;
+  FFC_DIV11_MODE_TX_1       : in std_logic;
+  FFC_DIV11_MODE_TX_2       : in std_logic;
+  FFC_DIV11_MODE_TX_3       : in std_logic;
+  LDR_CORE2TX_0             : in std_logic;
+  LDR_CORE2TX_1             : in std_logic;
+  LDR_CORE2TX_2             : in std_logic;
+  LDR_CORE2TX_3             : in std_logic;
+  FFC_LDR_CORE2TX_EN_0      : in std_logic;
+  FFC_LDR_CORE2TX_EN_1      : in std_logic;
+  FFC_LDR_CORE2TX_EN_2      : in std_logic;
+  FFC_LDR_CORE2TX_EN_3      : in std_logic;
+  PCIE_POWERDOWN_0_0      : in std_logic;
+  PCIE_POWERDOWN_0_1      : in std_logic;
+  PCIE_POWERDOWN_1_0      : in std_logic;
+  PCIE_POWERDOWN_1_1      : in std_logic;
+  PCIE_POWERDOWN_2_0      : in std_logic;
+  PCIE_POWERDOWN_2_1      : in std_logic;
+  PCIE_POWERDOWN_3_0      : in std_logic;
+  PCIE_POWERDOWN_3_1      : in std_logic;
+  PCIE_RXPOLARITY_0         : in std_logic;
+  PCIE_RXPOLARITY_1         : in std_logic;
+  PCIE_RXPOLARITY_2         : in std_logic;
+  PCIE_RXPOLARITY_3         : in std_logic;
+  PCIE_TXCOMPLIANCE_0       : in std_logic;
+  PCIE_TXCOMPLIANCE_1       : in std_logic;
+  PCIE_TXCOMPLIANCE_2       : in std_logic;
+  PCIE_TXCOMPLIANCE_3       : in std_logic;
+  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
+  SCIADDR0             : in std_logic;
+  SCIADDR1             : in std_logic;
+  SCIADDR2             : in std_logic;
+  SCIADDR3             : in std_logic;
+  SCIADDR4             : in std_logic;
+  SCIADDR5             : in std_logic;
+  SCIENAUX             : in std_logic;
+  SCIENCH0             : in std_logic;
+  SCIENCH1             : in std_logic;
+  SCIENCH2             : in std_logic;
+  SCIENCH3             : in std_logic;
+  SCIRD                : in std_logic;
+  SCISELAUX             : in std_logic;
+  SCISELCH0             : in std_logic;
+  SCISELCH1             : in std_logic;
+  SCISELCH2             : in std_logic;
+  SCISELCH3             : in std_logic;
+  SCIWDATA0             : in std_logic;
+  SCIWDATA1             : in std_logic;
+  SCIWDATA2             : in std_logic;
+  SCIWDATA3             : in std_logic;
+  SCIWDATA4             : in std_logic;
+  SCIWDATA5             : in std_logic;
+  SCIWDATA6             : in std_logic;
+  SCIWDATA7             : in std_logic;
+  SCIWSTN               : in std_logic;
+  REFCLK_FROM_NQ        : in std_logic;
+
+  HDOUTN0             : out std_logic;
+  HDOUTN1             : out std_logic;
+  HDOUTN2             : out std_logic;
+  HDOUTN3             : out std_logic;
+  HDOUTP0             : out std_logic;
+  HDOUTP1             : out std_logic;
+  HDOUTP2             : out std_logic;
+  HDOUTP3             : out std_logic;
+  COUT0             : out std_logic;
+  COUT1             : out std_logic;
+  COUT2             : out std_logic;
+  COUT3             : out std_logic;
+  COUT4             : out std_logic;
+  COUT5             : out std_logic;
+  COUT6             : out std_logic;
+  COUT7             : out std_logic;
+  COUT8             : out std_logic;
+  COUT9             : out std_logic;
+  COUT10             : out std_logic;
+  COUT11             : out std_logic;
+  COUT12             : out std_logic;
+  COUT13             : out std_logic;
+  COUT14             : out std_logic;
+  COUT15             : out std_logic;
+  COUT16             : out std_logic;
+  COUT17             : out std_logic;
+  COUT18             : out std_logic;
+  COUT19             : out std_logic;
+  FF_RX_D_0_0             : out std_logic;
+  FF_RX_D_0_1             : out std_logic;
+  FF_RX_D_0_2             : out std_logic;
+  FF_RX_D_0_3             : out std_logic;
+  FF_RX_D_0_4             : out std_logic;
+  FF_RX_D_0_5             : out std_logic;
+  FF_RX_D_0_6             : out std_logic;
+  FF_RX_D_0_7             : out std_logic;
+  FF_RX_D_0_8             : out std_logic;
+  FF_RX_D_0_9             : out std_logic;
+  FF_RX_D_0_10             : out std_logic;
+  FF_RX_D_0_11             : out std_logic;
+  FF_RX_D_0_12             : out std_logic;
+  FF_RX_D_0_13             : out std_logic;
+  FF_RX_D_0_14             : out std_logic;
+  FF_RX_D_0_15             : out std_logic;
+  FF_RX_D_0_16             : out std_logic;
+  FF_RX_D_0_17             : out std_logic;
+  FF_RX_D_0_18             : out std_logic;
+  FF_RX_D_0_19             : out std_logic;
+  FF_RX_D_0_20             : out std_logic;
+  FF_RX_D_0_21             : out std_logic;
+  FF_RX_D_0_22             : out std_logic;
+  FF_RX_D_0_23             : out std_logic;
+  FF_RX_D_1_0             : out std_logic;
+  FF_RX_D_1_1             : out std_logic;
+  FF_RX_D_1_2             : out std_logic;
+  FF_RX_D_1_3             : out std_logic;
+  FF_RX_D_1_4             : out std_logic;
+  FF_RX_D_1_5             : out std_logic;
+  FF_RX_D_1_6             : out std_logic;
+  FF_RX_D_1_7             : out std_logic;
+  FF_RX_D_1_8             : out std_logic;
+  FF_RX_D_1_9             : out std_logic;
+  FF_RX_D_1_10             : out std_logic;
+  FF_RX_D_1_11             : out std_logic;
+  FF_RX_D_1_12             : out std_logic;
+  FF_RX_D_1_13             : out std_logic;
+  FF_RX_D_1_14             : out std_logic;
+  FF_RX_D_1_15             : out std_logic;
+  FF_RX_D_1_16             : out std_logic;
+  FF_RX_D_1_17             : out std_logic;
+  FF_RX_D_1_18             : out std_logic;
+  FF_RX_D_1_19             : out std_logic;
+  FF_RX_D_1_20             : out std_logic;
+  FF_RX_D_1_21             : out std_logic;
+  FF_RX_D_1_22             : out std_logic;
+  FF_RX_D_1_23             : out std_logic;
+  FF_RX_D_2_0             : out std_logic;
+  FF_RX_D_2_1             : out std_logic;
+  FF_RX_D_2_2             : out std_logic;
+  FF_RX_D_2_3             : out std_logic;
+  FF_RX_D_2_4             : out std_logic;
+  FF_RX_D_2_5             : out std_logic;
+  FF_RX_D_2_6             : out std_logic;
+  FF_RX_D_2_7             : out std_logic;
+  FF_RX_D_2_8             : out std_logic;
+  FF_RX_D_2_9             : out std_logic;
+  FF_RX_D_2_10             : out std_logic;
+  FF_RX_D_2_11             : out std_logic;
+  FF_RX_D_2_12             : out std_logic;
+  FF_RX_D_2_13             : out std_logic;
+  FF_RX_D_2_14             : out std_logic;
+  FF_RX_D_2_15             : out std_logic;
+  FF_RX_D_2_16             : out std_logic;
+  FF_RX_D_2_17             : out std_logic;
+  FF_RX_D_2_18             : out std_logic;
+  FF_RX_D_2_19             : out std_logic;
+  FF_RX_D_2_20             : out std_logic;
+  FF_RX_D_2_21             : out std_logic;
+  FF_RX_D_2_22             : out std_logic;
+  FF_RX_D_2_23             : out std_logic;
+  FF_RX_D_3_0             : out std_logic;
+  FF_RX_D_3_1             : out std_logic;
+  FF_RX_D_3_2             : out std_logic;
+  FF_RX_D_3_3             : out std_logic;
+  FF_RX_D_3_4             : out std_logic;
+  FF_RX_D_3_5             : out std_logic;
+  FF_RX_D_3_6             : out std_logic;
+  FF_RX_D_3_7             : out std_logic;
+  FF_RX_D_3_8             : out std_logic;
+  FF_RX_D_3_9             : out std_logic;
+  FF_RX_D_3_10             : out std_logic;
+  FF_RX_D_3_11             : out std_logic;
+  FF_RX_D_3_12             : out std_logic;
+  FF_RX_D_3_13             : out std_logic;
+  FF_RX_D_3_14             : out std_logic;
+  FF_RX_D_3_15             : out std_logic;
+  FF_RX_D_3_16             : out std_logic;
+  FF_RX_D_3_17             : out std_logic;
+  FF_RX_D_3_18             : out std_logic;
+  FF_RX_D_3_19             : out std_logic;
+  FF_RX_D_3_20             : out std_logic;
+  FF_RX_D_3_21             : out std_logic;
+  FF_RX_D_3_22             : out std_logic;
+  FF_RX_D_3_23             : out std_logic;
+  FF_RX_F_CLK_0             : out std_logic;
+  FF_RX_F_CLK_1             : out std_logic;
+  FF_RX_F_CLK_2             : out std_logic;
+  FF_RX_F_CLK_3             : out std_logic;
+  FF_RX_H_CLK_0             : out std_logic;
+  FF_RX_H_CLK_1             : out std_logic;
+  FF_RX_H_CLK_2             : out std_logic;
+  FF_RX_H_CLK_3             : out std_logic;
+  FF_TX_F_CLK_0             : out std_logic;
+  FF_TX_F_CLK_1             : out std_logic;
+  FF_TX_F_CLK_2             : out std_logic;
+  FF_TX_F_CLK_3             : out std_logic;
+  FF_TX_H_CLK_0             : out std_logic;
+  FF_TX_H_CLK_1             : out std_logic;
+  FF_TX_H_CLK_2             : out std_logic;
+  FF_TX_H_CLK_3             : out std_logic;
+  FFS_CC_OVERRUN_0             : out std_logic;
+  FFS_CC_OVERRUN_1             : out std_logic;
+  FFS_CC_OVERRUN_2             : out std_logic;
+  FFS_CC_OVERRUN_3             : out std_logic;
+  FFS_CC_UNDERRUN_0             : out std_logic;
+  FFS_CC_UNDERRUN_1             : out std_logic;
+  FFS_CC_UNDERRUN_2             : out std_logic;
+  FFS_CC_UNDERRUN_3             : out std_logic;
+  FFS_LS_SYNC_STATUS_0             : out std_logic;
+  FFS_LS_SYNC_STATUS_1             : out std_logic;
+  FFS_LS_SYNC_STATUS_2             : out std_logic;
+  FFS_LS_SYNC_STATUS_3             : out std_logic;
+  FFS_CDR_TRAIN_DONE_0             : out std_logic;
+  FFS_CDR_TRAIN_DONE_1             : out std_logic;
+  FFS_CDR_TRAIN_DONE_2             : out std_logic;
+  FFS_CDR_TRAIN_DONE_3             : out std_logic;
+  FFS_PCIE_CON_0             : out std_logic;
+  FFS_PCIE_CON_1             : out std_logic;
+  FFS_PCIE_CON_2             : out std_logic;
+  FFS_PCIE_CON_3             : out std_logic;
+  FFS_PCIE_DONE_0             : out std_logic;
+  FFS_PCIE_DONE_1             : out std_logic;
+  FFS_PCIE_DONE_2             : out std_logic;
+  FFS_PCIE_DONE_3             : out std_logic;
+  FFS_PLOL             : out std_logic;
+  FFS_RLOL_0             : out std_logic;
+  FFS_RLOL_1             : out std_logic;
+  FFS_RLOL_2             : out std_logic;
+  FFS_RLOL_3             : out std_logic;
+  FFS_RLOS_HI_0             : out std_logic;
+  FFS_RLOS_HI_1             : out std_logic;
+  FFS_RLOS_HI_2             : out std_logic;
+  FFS_RLOS_HI_3             : out std_logic;
+  FFS_RLOS_LO_0             : out std_logic;
+  FFS_RLOS_LO_1             : out std_logic;
+  FFS_RLOS_LO_2             : out std_logic;
+  FFS_RLOS_LO_3             : out std_logic;
+  FFS_RXFBFIFO_ERROR_0             : out std_logic;
+  FFS_RXFBFIFO_ERROR_1             : out std_logic;
+  FFS_RXFBFIFO_ERROR_2             : out std_logic;
+  FFS_RXFBFIFO_ERROR_3             : out std_logic;
+  FFS_TXFBFIFO_ERROR_0             : out std_logic;
+  FFS_TXFBFIFO_ERROR_1             : out std_logic;
+  FFS_TXFBFIFO_ERROR_2             : out std_logic;
+  FFS_TXFBFIFO_ERROR_3             : out std_logic;
+  PCIE_PHYSTATUS_0             : out std_logic;
+  PCIE_PHYSTATUS_1             : out std_logic;
+  PCIE_PHYSTATUS_2             : out std_logic;
+  PCIE_PHYSTATUS_3             : out std_logic;
+  PCIE_RXVALID_0               : out std_logic;
+  PCIE_RXVALID_1               : out std_logic;
+  PCIE_RXVALID_2               : out std_logic;
+  PCIE_RXVALID_3               : out std_logic;
+  FFS_SKP_ADDED_0                  : out std_logic;
+  FFS_SKP_ADDED_1                  : out std_logic;
+  FFS_SKP_ADDED_2                  : out std_logic;
+  FFS_SKP_ADDED_3                  : out std_logic;
+  FFS_SKP_DELETED_0                : out std_logic;
+  FFS_SKP_DELETED_1                : out std_logic;
+  FFS_SKP_DELETED_2                : out std_logic;
+  FFS_SKP_DELETED_3                : out std_logic;
+  LDR_RX2CORE_0                    : out std_logic;
+  LDR_RX2CORE_1                    : out std_logic;
+  LDR_RX2CORE_2                    : out std_logic;
+  LDR_RX2CORE_3                    : out std_logic;
+  REFCK2CORE             : out std_logic;
+  SCIINT                : out std_logic;
+  SCIRDATA0             : out std_logic;
+  SCIRDATA1             : out std_logic;
+  SCIRDATA2             : out std_logic;
+  SCIRDATA3             : out std_logic;
+  SCIRDATA4             : out std_logic;
+  SCIRDATA5             : out std_logic;
+  SCIRDATA6             : out std_logic;
+  SCIRDATA7             : out std_logic;
+  REFCLK_TO_NQ          : out std_logic
+);
+end component;
+
+begin
+
+PCSD_sim_inst : PCSD_sim
+generic map (
+  CONFIG_FILE => CONFIG_FILE,
+  QUAD_MODE => QUAD_MODE,
+  CH0_CDR_SRC => CH0_CDR_SRC,
+  CH1_CDR_SRC => CH1_CDR_SRC,
+  CH2_CDR_SRC => CH2_CDR_SRC,
+  CH3_CDR_SRC => CH3_CDR_SRC,
+  PLL_SRC => PLL_SRC
+  )
+port map (
+   HDINN0 => HDINN0,
+   HDINN1 => HDINN1,
+   HDINN2 => HDINN2,
+   HDINN3 => HDINN3,
+   HDINP0 => HDINP0,
+   HDINP1 => HDINP1,
+   HDINP2 => HDINP2,
+   HDINP3 => HDINP3,
+   REFCLKN => REFCLKN,
+   REFCLKP => REFCLKP,
+   CIN11 => CIN11,
+   CIN10 => CIN10,
+   CIN9 => CIN9,
+   CIN8 => CIN8,
+   CIN7 => CIN7,
+   CIN6 => CIN6,
+   CIN5 => CIN5,
+   CIN4 => CIN4,
+   CIN3 => CIN3,
+   CIN2 => CIN2,
+   CIN1 => CIN1,
+   CIN0 => CIN0,
+   CYAWSTN => CYAWSTN,
+   FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
+   FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
+   FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
+   FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
+   FF_RXI_CLK_3 => FF_RXI_CLK_3,
+   FF_RXI_CLK_2 => FF_RXI_CLK_2,
+   FF_RXI_CLK_1 => FF_RXI_CLK_1,
+   FF_RXI_CLK_0 => FF_RXI_CLK_0,
+   FF_TX_D_0_0 => FF_TX_D_0_0,
+   FF_TX_D_0_1 => FF_TX_D_0_1,
+   FF_TX_D_0_2 => FF_TX_D_0_2,
+   FF_TX_D_0_3 => FF_TX_D_0_3,
+   FF_TX_D_0_4 => FF_TX_D_0_4,
+   FF_TX_D_0_5 => FF_TX_D_0_5,
+   FF_TX_D_0_6 => FF_TX_D_0_6,
+   FF_TX_D_0_7 => FF_TX_D_0_7,
+   FF_TX_D_0_8 => FF_TX_D_0_8,
+   FF_TX_D_0_9 => FF_TX_D_0_9,
+   FF_TX_D_0_10 => FF_TX_D_0_10,
+   FF_TX_D_0_11 => FF_TX_D_0_11,
+   FF_TX_D_0_12 => FF_TX_D_0_12,
+   FF_TX_D_0_13 => FF_TX_D_0_13,
+   FF_TX_D_0_14 => FF_TX_D_0_14,
+   FF_TX_D_0_15 => FF_TX_D_0_15,
+   FF_TX_D_0_16 => FF_TX_D_0_16,
+   FF_TX_D_0_17 => FF_TX_D_0_17,
+   FF_TX_D_0_18 => FF_TX_D_0_18,
+   FF_TX_D_0_19 => FF_TX_D_0_19,
+   FF_TX_D_0_20 => FF_TX_D_0_20,
+   FF_TX_D_0_21 => FF_TX_D_0_21,
+   FF_TX_D_0_22 => FF_TX_D_0_22,
+   FF_TX_D_0_23 => FF_TX_D_0_23,
+   FF_TX_D_1_0 => FF_TX_D_1_0,
+   FF_TX_D_1_1 => FF_TX_D_1_1,
+   FF_TX_D_1_2 => FF_TX_D_1_2,
+   FF_TX_D_1_3 => FF_TX_D_1_3,
+   FF_TX_D_1_4 => FF_TX_D_1_4,
+   FF_TX_D_1_5 => FF_TX_D_1_5,
+   FF_TX_D_1_6 => FF_TX_D_1_6,
+   FF_TX_D_1_7 => FF_TX_D_1_7,
+   FF_TX_D_1_8 => FF_TX_D_1_8,
+   FF_TX_D_1_9 => FF_TX_D_1_9,
+   FF_TX_D_1_10 => FF_TX_D_1_10,
+   FF_TX_D_1_11 => FF_TX_D_1_11,
+   FF_TX_D_1_12 => FF_TX_D_1_12,
+   FF_TX_D_1_13 => FF_TX_D_1_13,
+   FF_TX_D_1_14 => FF_TX_D_1_14,
+   FF_TX_D_1_15 => FF_TX_D_1_15,
+   FF_TX_D_1_16 => FF_TX_D_1_16,
+   FF_TX_D_1_17 => FF_TX_D_1_17,
+   FF_TX_D_1_18 => FF_TX_D_1_18,
+   FF_TX_D_1_19 => FF_TX_D_1_19,
+   FF_TX_D_1_20 => FF_TX_D_1_20,
+   FF_TX_D_1_21 => FF_TX_D_1_21,
+   FF_TX_D_1_22 => FF_TX_D_1_22,
+   FF_TX_D_1_23 => FF_TX_D_1_23,
+   FF_TX_D_2_0 => FF_TX_D_2_0,
+   FF_TX_D_2_1 => FF_TX_D_2_1,
+   FF_TX_D_2_2 => FF_TX_D_2_2,
+   FF_TX_D_2_3 => FF_TX_D_2_3,
+   FF_TX_D_2_4 => FF_TX_D_2_4,
+   FF_TX_D_2_5 => FF_TX_D_2_5,
+   FF_TX_D_2_6 => FF_TX_D_2_6,
+   FF_TX_D_2_7 => FF_TX_D_2_7,
+   FF_TX_D_2_8 => FF_TX_D_2_8,
+   FF_TX_D_2_9 => FF_TX_D_2_9,
+   FF_TX_D_2_10 => FF_TX_D_2_10,
+   FF_TX_D_2_11 => FF_TX_D_2_11,
+   FF_TX_D_2_12 => FF_TX_D_2_12,
+   FF_TX_D_2_13 => FF_TX_D_2_13,
+   FF_TX_D_2_14 => FF_TX_D_2_14,
+   FF_TX_D_2_15 => FF_TX_D_2_15,
+   FF_TX_D_2_16 => FF_TX_D_2_16,
+   FF_TX_D_2_17 => FF_TX_D_2_17,
+   FF_TX_D_2_18 => FF_TX_D_2_18,
+   FF_TX_D_2_19 => FF_TX_D_2_19,
+   FF_TX_D_2_20 => FF_TX_D_2_20,
+   FF_TX_D_2_21 => FF_TX_D_2_21,
+   FF_TX_D_2_22 => FF_TX_D_2_22,
+   FF_TX_D_2_23 => FF_TX_D_2_23,
+   FF_TX_D_3_0 => FF_TX_D_3_0,
+   FF_TX_D_3_1 => FF_TX_D_3_1,
+   FF_TX_D_3_2 => FF_TX_D_3_2,
+   FF_TX_D_3_3 => FF_TX_D_3_3,
+   FF_TX_D_3_4 => FF_TX_D_3_4,
+   FF_TX_D_3_5 => FF_TX_D_3_5,
+   FF_TX_D_3_6 => FF_TX_D_3_6,
+   FF_TX_D_3_7 => FF_TX_D_3_7,
+   FF_TX_D_3_8 => FF_TX_D_3_8,
+   FF_TX_D_3_9 => FF_TX_D_3_9,
+   FF_TX_D_3_10 => FF_TX_D_3_10,
+   FF_TX_D_3_11 => FF_TX_D_3_11,
+   FF_TX_D_3_12 => FF_TX_D_3_12,
+   FF_TX_D_3_13 => FF_TX_D_3_13,
+   FF_TX_D_3_14 => FF_TX_D_3_14,
+   FF_TX_D_3_15 => FF_TX_D_3_15,
+   FF_TX_D_3_16 => FF_TX_D_3_16,
+   FF_TX_D_3_17 => FF_TX_D_3_17,
+   FF_TX_D_3_18 => FF_TX_D_3_18,
+   FF_TX_D_3_19 => FF_TX_D_3_19,
+   FF_TX_D_3_20 => FF_TX_D_3_20,
+   FF_TX_D_3_21 => FF_TX_D_3_21,
+   FF_TX_D_3_22 => FF_TX_D_3_22,
+   FF_TX_D_3_23 => FF_TX_D_3_23,
+   FF_TXI_CLK_0 => FF_TXI_CLK_0,
+   FF_TXI_CLK_1 => FF_TXI_CLK_1,
+   FF_TXI_CLK_2 => FF_TXI_CLK_2,
+   FF_TXI_CLK_3 => FF_TXI_CLK_3,
+   FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
+   FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
+   FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
+   FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
+   FFC_CK_CORE_TX => FFC_CK_CORE_TX,
+   FFC_EI_EN_0 => FFC_EI_EN_0,
+   FFC_EI_EN_1 => FFC_EI_EN_1,
+   FFC_EI_EN_2 => FFC_EI_EN_2,
+   FFC_EI_EN_3 => FFC_EI_EN_3,
+   FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
+   FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
+   FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
+   FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
+   FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
+   FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
+   FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
+   FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
+   FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
+   FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
+   FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
+   FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
+   FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
+   FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
+   FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
+   FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
+   FFC_MACRO_RST => FFC_MACRO_RST,
+   FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
+   FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
+   FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
+   FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
+   FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
+   FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
+   FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
+   FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
+   FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
+   FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
+   FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
+   FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
+   FFC_QUAD_RST => FFC_QUAD_RST,
+   FFC_RRST_0 => FFC_RRST_0,
+   FFC_RRST_1 => FFC_RRST_1,
+   FFC_RRST_2 => FFC_RRST_2,
+   FFC_RRST_3 => FFC_RRST_3,
+   FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
+   FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
+   FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
+   FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
+   FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
+   FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
+   FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
+   FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
+   FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
+   FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
+   FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
+   FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
+   FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
+   FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
+   FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
+   FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
+   FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
+   FFC_TRST => FFC_TRST,
+   FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
+   FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
+   FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
+   FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
+   FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
+   FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
+   FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
+   FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
+   FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
+   FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
+   FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
+   FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
+   FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
+   FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
+   FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
+   FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
+   FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
+   FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
+   FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
+   FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
+   LDR_CORE2TX_0 => LDR_CORE2TX_0,
+   LDR_CORE2TX_1 => LDR_CORE2TX_1,
+   LDR_CORE2TX_2 => LDR_CORE2TX_2,
+   LDR_CORE2TX_3 => LDR_CORE2TX_3,
+   FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
+   FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
+   FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
+   FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
+   PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
+   PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
+   PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
+   PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
+   PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
+   PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
+   PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
+   PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
+   PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
+   PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
+   PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
+   PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
+   PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
+   PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
+   PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
+   PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
+   PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
+   PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
+   PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
+   PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
+   SCIADDR0 => SCIADDR0,
+   SCIADDR1 => SCIADDR1,
+   SCIADDR2 => SCIADDR2,
+   SCIADDR3 => SCIADDR3,
+   SCIADDR4 => SCIADDR4,
+   SCIADDR5 => SCIADDR5,
+   SCIENAUX => SCIENAUX,
+   SCIENCH0 => SCIENCH0,
+   SCIENCH1 => SCIENCH1,
+   SCIENCH2 => SCIENCH2,
+   SCIENCH3 => SCIENCH3,
+   SCIRD => SCIRD,
+   SCISELAUX => SCISELAUX,
+   SCISELCH0 => SCISELCH0,
+   SCISELCH1 => SCISELCH1,
+   SCISELCH2 => SCISELCH2,
+   SCISELCH3 => SCISELCH3,
+   SCIWDATA0 => SCIWDATA0,
+   SCIWDATA1 => SCIWDATA1,
+   SCIWDATA2 => SCIWDATA2,
+   SCIWDATA3 => SCIWDATA3,
+   SCIWDATA4 => SCIWDATA4,
+   SCIWDATA5 => SCIWDATA5,
+   SCIWDATA6 => SCIWDATA6,
+   SCIWDATA7 => SCIWDATA7,
+   SCIWSTN => SCIWSTN,
+   HDOUTN0 => HDOUTN0,
+   HDOUTN1 => HDOUTN1,
+   HDOUTN2 => HDOUTN2,
+   HDOUTN3 => HDOUTN3,
+   HDOUTP0 => HDOUTP0,
+   HDOUTP1 => HDOUTP1,
+   HDOUTP2 => HDOUTP2,
+   HDOUTP3 => HDOUTP3,
+   COUT19 => COUT19,
+   COUT18 => COUT18,
+   COUT17 => COUT17,
+   COUT16 => COUT16,
+   COUT15 => COUT15,
+   COUT14 => COUT14,
+   COUT13 => COUT13,
+   COUT12 => COUT12,
+   COUT11 => COUT11,
+   COUT10 => COUT10,
+   COUT9 => COUT9,
+   COUT8 => COUT8,
+   COUT7 => COUT7,
+   COUT6 => COUT6,
+   COUT5 => COUT5,
+   COUT4 => COUT4,
+   COUT3 => COUT3,
+   COUT2 => COUT2,
+   COUT1 => COUT1,
+   COUT0 => COUT0,
+   FF_RX_D_0_0 => FF_RX_D_0_0,
+   FF_RX_D_0_1 => FF_RX_D_0_1,
+   FF_RX_D_0_2 => FF_RX_D_0_2,
+   FF_RX_D_0_3 => FF_RX_D_0_3,
+   FF_RX_D_0_4 => FF_RX_D_0_4,
+   FF_RX_D_0_5 => FF_RX_D_0_5,
+   FF_RX_D_0_6 => FF_RX_D_0_6,
+   FF_RX_D_0_7 => FF_RX_D_0_7,
+   FF_RX_D_0_8 => FF_RX_D_0_8,
+   FF_RX_D_0_9 => FF_RX_D_0_9,
+   FF_RX_D_0_10 => FF_RX_D_0_10,
+   FF_RX_D_0_11 => FF_RX_D_0_11,
+   FF_RX_D_0_12 => FF_RX_D_0_12,
+   FF_RX_D_0_13 => FF_RX_D_0_13,
+   FF_RX_D_0_14 => FF_RX_D_0_14,
+   FF_RX_D_0_15 => FF_RX_D_0_15,
+   FF_RX_D_0_16 => FF_RX_D_0_16,
+   FF_RX_D_0_17 => FF_RX_D_0_17,
+   FF_RX_D_0_18 => FF_RX_D_0_18,
+   FF_RX_D_0_19 => FF_RX_D_0_19,
+   FF_RX_D_0_20 => FF_RX_D_0_20,
+   FF_RX_D_0_21 => FF_RX_D_0_21,
+   FF_RX_D_0_22 => FF_RX_D_0_22,
+   FF_RX_D_0_23 => FF_RX_D_0_23,
+   FF_RX_D_1_0 => FF_RX_D_1_0,
+   FF_RX_D_1_1 => FF_RX_D_1_1,
+   FF_RX_D_1_2 => FF_RX_D_1_2,
+   FF_RX_D_1_3 => FF_RX_D_1_3,
+   FF_RX_D_1_4 => FF_RX_D_1_4,
+   FF_RX_D_1_5 => FF_RX_D_1_5,
+   FF_RX_D_1_6 => FF_RX_D_1_6,
+   FF_RX_D_1_7 => FF_RX_D_1_7,
+   FF_RX_D_1_8 => FF_RX_D_1_8,
+   FF_RX_D_1_9 => FF_RX_D_1_9,
+   FF_RX_D_1_10 => FF_RX_D_1_10,
+   FF_RX_D_1_11 => FF_RX_D_1_11,
+   FF_RX_D_1_12 => FF_RX_D_1_12,
+   FF_RX_D_1_13 => FF_RX_D_1_13,
+   FF_RX_D_1_14 => FF_RX_D_1_14,
+   FF_RX_D_1_15 => FF_RX_D_1_15,
+   FF_RX_D_1_16 => FF_RX_D_1_16,
+   FF_RX_D_1_17 => FF_RX_D_1_17,
+   FF_RX_D_1_18 => FF_RX_D_1_18,
+   FF_RX_D_1_19 => FF_RX_D_1_19,
+   FF_RX_D_1_20 => FF_RX_D_1_20,
+   FF_RX_D_1_21 => FF_RX_D_1_21,
+   FF_RX_D_1_22 => FF_RX_D_1_22,
+   FF_RX_D_1_23 => FF_RX_D_1_23,
+   FF_RX_D_2_0 => FF_RX_D_2_0,
+   FF_RX_D_2_1 => FF_RX_D_2_1,
+   FF_RX_D_2_2 => FF_RX_D_2_2,
+   FF_RX_D_2_3 => FF_RX_D_2_3,
+   FF_RX_D_2_4 => FF_RX_D_2_4,
+   FF_RX_D_2_5 => FF_RX_D_2_5,
+   FF_RX_D_2_6 => FF_RX_D_2_6,
+   FF_RX_D_2_7 => FF_RX_D_2_7,
+   FF_RX_D_2_8 => FF_RX_D_2_8,
+   FF_RX_D_2_9 => FF_RX_D_2_9,
+   FF_RX_D_2_10 => FF_RX_D_2_10,
+   FF_RX_D_2_11 => FF_RX_D_2_11,
+   FF_RX_D_2_12 => FF_RX_D_2_12,
+   FF_RX_D_2_13 => FF_RX_D_2_13,
+   FF_RX_D_2_14 => FF_RX_D_2_14,
+   FF_RX_D_2_15 => FF_RX_D_2_15,
+   FF_RX_D_2_16 => FF_RX_D_2_16,
+   FF_RX_D_2_17 => FF_RX_D_2_17,
+   FF_RX_D_2_18 => FF_RX_D_2_18,
+   FF_RX_D_2_19 => FF_RX_D_2_19,
+   FF_RX_D_2_20 => FF_RX_D_2_20,
+   FF_RX_D_2_21 => FF_RX_D_2_21,
+   FF_RX_D_2_22 => FF_RX_D_2_22,
+   FF_RX_D_2_23 => FF_RX_D_2_23,
+   FF_RX_D_3_0 => FF_RX_D_3_0,
+   FF_RX_D_3_1 => FF_RX_D_3_1,
+   FF_RX_D_3_2 => FF_RX_D_3_2,
+   FF_RX_D_3_3 => FF_RX_D_3_3,
+   FF_RX_D_3_4 => FF_RX_D_3_4,
+   FF_RX_D_3_5 => FF_RX_D_3_5,
+   FF_RX_D_3_6 => FF_RX_D_3_6,
+   FF_RX_D_3_7 => FF_RX_D_3_7,
+   FF_RX_D_3_8 => FF_RX_D_3_8,
+   FF_RX_D_3_9 => FF_RX_D_3_9,
+   FF_RX_D_3_10 => FF_RX_D_3_10,
+   FF_RX_D_3_11 => FF_RX_D_3_11,
+   FF_RX_D_3_12 => FF_RX_D_3_12,
+   FF_RX_D_3_13 => FF_RX_D_3_13,
+   FF_RX_D_3_14 => FF_RX_D_3_14,
+   FF_RX_D_3_15 => FF_RX_D_3_15,
+   FF_RX_D_3_16 => FF_RX_D_3_16,
+   FF_RX_D_3_17 => FF_RX_D_3_17,
+   FF_RX_D_3_18 => FF_RX_D_3_18,
+   FF_RX_D_3_19 => FF_RX_D_3_19,
+   FF_RX_D_3_20 => FF_RX_D_3_20,
+   FF_RX_D_3_21 => FF_RX_D_3_21,
+   FF_RX_D_3_22 => FF_RX_D_3_22,
+   FF_RX_D_3_23 => FF_RX_D_3_23,
+   FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
+   FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
+   FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
+   FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
+   FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
+   FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
+   FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
+   FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
+   FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
+   FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
+   FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
+   FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
+   FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
+   FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
+   FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
+   FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
+   FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
+   FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
+   FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
+   FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
+   FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
+   FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
+   FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
+   FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
+   FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
+   FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
+   FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
+   FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
+   FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
+   FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
+   FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
+   FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
+   FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
+   FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
+   FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
+   FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
+   FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
+   FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
+   FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
+   FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
+   FFS_PLOL => FFS_PLOL,
+   FFS_RLOL_0 => FFS_RLOL_0,
+   FFS_RLOL_1 => FFS_RLOL_1,
+   FFS_RLOL_2 => FFS_RLOL_2,
+   FFS_RLOL_3 => FFS_RLOL_3,
+   FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
+   FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
+   FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
+   FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
+   FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
+   FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
+   FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
+   FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
+   FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
+   FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
+   FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
+   FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
+   FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
+   FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
+   FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
+   FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
+   PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
+   PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
+   PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
+   PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
+   PCIE_RXVALID_0 => PCIE_RXVALID_0,
+   PCIE_RXVALID_1 => PCIE_RXVALID_1,
+   PCIE_RXVALID_2 => PCIE_RXVALID_2,
+   PCIE_RXVALID_3 => PCIE_RXVALID_3,
+   FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
+   FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
+   FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
+   FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
+   FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
+   FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
+   FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
+   FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
+   LDR_RX2CORE_0 => LDR_RX2CORE_0,
+   LDR_RX2CORE_1 => LDR_RX2CORE_1,
+   LDR_RX2CORE_2 => LDR_RX2CORE_2,
+   LDR_RX2CORE_3 => LDR_RX2CORE_3,
+   REFCK2CORE => REFCK2CORE,
+   SCIINT => SCIINT,
+   SCIRDATA0 => SCIRDATA0,
+   SCIRDATA1 => SCIRDATA1,
+   SCIRDATA2 => SCIRDATA2,
+   SCIRDATA3 => SCIRDATA3,
+   SCIRDATA4 => SCIRDATA4,
+   SCIRDATA5 => SCIRDATA5,
+   SCIRDATA6 => SCIRDATA6,
+   SCIRDATA7 => SCIRDATA7,
+   REFCLK_FROM_NQ => REFCLK_FROM_NQ,
+   REFCLK_TO_NQ => REFCLK_TO_NQ
+   );
+
+end PCSD_arch;
+
+--synopsys translate_on
+
+
+
+
+--synopsys translate_off
+library ECP3;
+use ECP3.components.all;
+--synopsys translate_on
+
+
+library IEEE, STD;
+use IEEE.std_logic_1164.all;
+use STD.TEXTIO.all;
+
+entity serdes_sync_200_full is
+   GENERIC (USER_CONFIG_FILE    :  String := "serdes_sync_200_full.txt");
+ port (
+------------------
+-- CH0 --
+    hdinp_ch0, hdinn_ch0    :   in std_logic;
+    hdoutp_ch0, hdoutn_ch0   :   out std_logic;
+    sci_sel_ch0    :   in std_logic;
+    rxiclk_ch0    :   in std_logic;
+    txiclk_ch0    :   in std_logic;
+    rx_full_clk_ch0   :   out std_logic;
+    rx_half_clk_ch0   :   out std_logic;
+    tx_full_clk_ch0   :   out std_logic;
+    tx_half_clk_ch0   :   out std_logic;
+    fpga_rxrefclk_ch0    :   in std_logic;
+    txdata_ch0    :   in std_logic_vector (7 downto 0);
+    tx_k_ch0    :   in std_logic;
+    tx_force_disp_ch0    :   in std_logic;
+    tx_disp_sel_ch0    :   in std_logic;
+    rxdata_ch0   :   out std_logic_vector (7 downto 0);
+    rx_k_ch0   :   out std_logic;
+    rx_disp_err_ch0   :   out std_logic;
+    rx_cv_err_ch0   :   out std_logic;
+    rx_serdes_rst_ch0_c    :   in std_logic;
+    sb_felb_ch0_c    :   in std_logic;
+    sb_felb_rst_ch0_c    :   in std_logic;
+    tx_pcs_rst_ch0_c    :   in std_logic;
+    tx_pwrup_ch0_c    :   in std_logic;
+    rx_pcs_rst_ch0_c    :   in std_logic;
+    rx_pwrup_ch0_c    :   in std_logic;
+    rx_los_low_ch0_s   :   out std_logic;
+    lsm_status_ch0_s   :   out std_logic;
+    rx_cdr_lol_ch0_s   :   out std_logic;
+    tx_div2_mode_ch0_c   : in std_logic;
+    rx_div2_mode_ch0_c   : in std_logic;
+-- CH1 --
+    hdinp_ch1, hdinn_ch1    :   in std_logic;
+    hdoutp_ch1, hdoutn_ch1   :   out std_logic;
+    sci_sel_ch1    :   in std_logic;
+    rxiclk_ch1    :   in std_logic;
+    txiclk_ch1    :   in std_logic;
+    rx_full_clk_ch1   :   out std_logic;
+    rx_half_clk_ch1   :   out std_logic;
+    tx_full_clk_ch1   :   out std_logic;
+    tx_half_clk_ch1   :   out std_logic;
+    fpga_rxrefclk_ch1    :   in std_logic;
+    txdata_ch1    :   in std_logic_vector (7 downto 0);
+    tx_k_ch1    :   in std_logic;
+    tx_force_disp_ch1    :   in std_logic;
+    tx_disp_sel_ch1    :   in std_logic;
+    rxdata_ch1   :   out std_logic_vector (7 downto 0);
+    rx_k_ch1   :   out std_logic;
+    rx_disp_err_ch1   :   out std_logic;
+    rx_cv_err_ch1   :   out std_logic;
+    rx_serdes_rst_ch1_c    :   in std_logic;
+    sb_felb_ch1_c    :   in std_logic;
+    sb_felb_rst_ch1_c    :   in std_logic;
+    tx_pcs_rst_ch1_c    :   in std_logic;
+    tx_pwrup_ch1_c    :   in std_logic;
+    rx_pcs_rst_ch1_c    :   in std_logic;
+    rx_pwrup_ch1_c    :   in std_logic;
+    rx_los_low_ch1_s   :   out std_logic;
+    lsm_status_ch1_s   :   out std_logic;
+    rx_cdr_lol_ch1_s   :   out std_logic;
+    tx_div2_mode_ch1_c   : in std_logic;
+    rx_div2_mode_ch1_c   : in std_logic;
+-- CH2 --
+    hdinp_ch2, hdinn_ch2    :   in std_logic;
+    hdoutp_ch2, hdoutn_ch2   :   out std_logic;
+    sci_sel_ch2    :   in std_logic;
+    rxiclk_ch2    :   in std_logic;
+    txiclk_ch2    :   in std_logic;
+    rx_full_clk_ch2   :   out std_logic;
+    rx_half_clk_ch2   :   out std_logic;
+    tx_full_clk_ch2   :   out std_logic;
+    tx_half_clk_ch2   :   out std_logic;
+    fpga_rxrefclk_ch2    :   in std_logic;
+    txdata_ch2    :   in std_logic_vector (7 downto 0);
+    tx_k_ch2    :   in std_logic;
+    tx_force_disp_ch2    :   in std_logic;
+    tx_disp_sel_ch2    :   in std_logic;
+    rxdata_ch2   :   out std_logic_vector (7 downto 0);
+    rx_k_ch2   :   out std_logic;
+    rx_disp_err_ch2   :   out std_logic;
+    rx_cv_err_ch2   :   out std_logic;
+    rx_serdes_rst_ch2_c    :   in std_logic;
+    sb_felb_ch2_c    :   in std_logic;
+    sb_felb_rst_ch2_c    :   in std_logic;
+    tx_pcs_rst_ch2_c    :   in std_logic;
+    tx_pwrup_ch2_c    :   in std_logic;
+    rx_pcs_rst_ch2_c    :   in std_logic;
+    rx_pwrup_ch2_c    :   in std_logic;
+    rx_los_low_ch2_s   :   out std_logic;
+    lsm_status_ch2_s   :   out std_logic;
+    rx_cdr_lol_ch2_s   :   out std_logic;
+    tx_div2_mode_ch2_c   : in std_logic;
+    rx_div2_mode_ch2_c   : in std_logic;
+-- CH3 --
+    hdinp_ch3, hdinn_ch3    :   in std_logic;
+    hdoutp_ch3, hdoutn_ch3   :   out std_logic;
+    sci_sel_ch3    :   in std_logic;
+    rxiclk_ch3    :   in std_logic;
+    txiclk_ch3    :   in std_logic;
+    rx_full_clk_ch3   :   out std_logic;
+    rx_half_clk_ch3   :   out std_logic;
+    tx_full_clk_ch3   :   out std_logic;
+    tx_half_clk_ch3   :   out std_logic;
+    fpga_rxrefclk_ch3    :   in std_logic;
+    txdata_ch3    :   in std_logic_vector (7 downto 0);
+    tx_k_ch3    :   in std_logic;
+    tx_force_disp_ch3    :   in std_logic;
+    tx_disp_sel_ch3    :   in std_logic;
+    rxdata_ch3   :   out std_logic_vector (7 downto 0);
+    rx_k_ch3   :   out std_logic;
+    rx_disp_err_ch3   :   out std_logic;
+    rx_cv_err_ch3   :   out std_logic;
+    rx_serdes_rst_ch3_c    :   in std_logic;
+    sb_felb_ch3_c    :   in std_logic;
+    sb_felb_rst_ch3_c    :   in std_logic;
+    tx_pcs_rst_ch3_c    :   in std_logic;
+    tx_pwrup_ch3_c    :   in std_logic;
+    rx_pcs_rst_ch3_c    :   in std_logic;
+    rx_pwrup_ch3_c    :   in std_logic;
+    rx_los_low_ch3_s   :   out std_logic;
+    lsm_status_ch3_s   :   out std_logic;
+    rx_cdr_lol_ch3_s   :   out std_logic;
+    tx_div2_mode_ch3_c   : in std_logic;
+    rx_div2_mode_ch3_c   : in std_logic;
+---- Miscillaneous ports
+    sci_wrdata    :   in std_logic_vector (7 downto 0);
+    sci_addr    :   in std_logic_vector (5 downto 0);
+    sci_rddata   :   out std_logic_vector (7 downto 0);
+    sci_sel_quad    :   in std_logic;
+    sci_rd    :   in std_logic;
+    sci_wrn    :   in std_logic;
+    fpga_txrefclk  :   in std_logic;
+    tx_serdes_rst_c    :   in std_logic;
+    tx_pll_lol_qd_s   :   out std_logic;
+    tx_sync_qd_c    :   in std_logic;
+    rst_qd_c    :   in std_logic;
+    serdes_rst_qd_c    :   in std_logic);
+
+end serdes_sync_200_full;
+
+
+architecture serdes_sync_200_full_arch of serdes_sync_200_full is
+
+component VLO
+port (
+   Z : out std_logic);
+end component;
+
+component VHI
+port (
+   Z : out std_logic);
+end component;
+
+
+
+component PCSD
+--synopsys translate_off
+GENERIC(
+  CONFIG_FILE : String;
+  QUAD_MODE : String;
+  CH0_CDR_SRC   : String := "REFCLK_EXT";
+  CH1_CDR_SRC   : String := "REFCLK_EXT";
+  CH2_CDR_SRC   : String := "REFCLK_EXT";
+  CH3_CDR_SRC   : String := "REFCLK_EXT";
+  PLL_SRC   : String
+  );
+--synopsys translate_on
+port (
+  HDINN0             : in std_logic;
+  HDINN1             : in std_logic;
+  HDINN2             : in std_logic;
+  HDINN3             : in std_logic;
+  HDINP0             : in std_logic;
+  HDINP1             : in std_logic;
+  HDINP2             : in std_logic;
+  HDINP3             : in std_logic;
+  REFCLKN             : in std_logic;
+  REFCLKP             : in std_logic;
+  CIN0             : in std_logic;
+  CIN1             : in std_logic;
+  CIN2             : in std_logic;
+  CIN3             : in std_logic;
+  CIN4             : in std_logic;
+  CIN5             : in std_logic;
+  CIN6             : in std_logic;
+  CIN7             : in std_logic;
+  CIN8             : in std_logic;
+  CIN9             : in std_logic;
+  CIN10             : in std_logic;
+  CIN11             : in std_logic;
+  CYAWSTN             : in std_logic;
+  FF_EBRD_CLK_0             : in std_logic;
+  FF_EBRD_CLK_1             : in std_logic;
+  FF_EBRD_CLK_2             : in std_logic;
+  FF_EBRD_CLK_3             : in std_logic;
+  FF_RXI_CLK_0             : in std_logic;
+  FF_RXI_CLK_1             : in std_logic;
+  FF_RXI_CLK_2             : in std_logic;
+  FF_RXI_CLK_3             : in std_logic;
+  FF_TX_D_0_0             : in std_logic;
+  FF_TX_D_0_1             : in std_logic;
+  FF_TX_D_0_2             : in std_logic;
+  FF_TX_D_0_3             : in std_logic;
+  FF_TX_D_0_4             : in std_logic;
+  FF_TX_D_0_5             : in std_logic;
+  FF_TX_D_0_6             : in std_logic;
+  FF_TX_D_0_7             : in std_logic;
+  FF_TX_D_0_8             : in std_logic;
+  FF_TX_D_0_9             : in std_logic;
+  FF_TX_D_0_10             : in std_logic;
+  FF_TX_D_0_11             : in std_logic;
+  FF_TX_D_0_12             : in std_logic;
+  FF_TX_D_0_13             : in std_logic;
+  FF_TX_D_0_14             : in std_logic;
+  FF_TX_D_0_15             : in std_logic;
+  FF_TX_D_0_16             : in std_logic;
+  FF_TX_D_0_17             : in std_logic;
+  FF_TX_D_0_18             : in std_logic;
+  FF_TX_D_0_19             : in std_logic;
+  FF_TX_D_0_20             : in std_logic;
+  FF_TX_D_0_21             : in std_logic;
+  FF_TX_D_0_22             : in std_logic;
+  FF_TX_D_0_23             : in std_logic;
+  FF_TX_D_1_0             : in std_logic;
+  FF_TX_D_1_1             : in std_logic;
+  FF_TX_D_1_2             : in std_logic;
+  FF_TX_D_1_3             : in std_logic;
+  FF_TX_D_1_4             : in std_logic;
+  FF_TX_D_1_5             : in std_logic;
+  FF_TX_D_1_6             : in std_logic;
+  FF_TX_D_1_7             : in std_logic;
+  FF_TX_D_1_8             : in std_logic;
+  FF_TX_D_1_9             : in std_logic;
+  FF_TX_D_1_10             : in std_logic;
+  FF_TX_D_1_11             : in std_logic;
+  FF_TX_D_1_12             : in std_logic;
+  FF_TX_D_1_13             : in std_logic;
+  FF_TX_D_1_14             : in std_logic;
+  FF_TX_D_1_15             : in std_logic;
+  FF_TX_D_1_16             : in std_logic;
+  FF_TX_D_1_17             : in std_logic;
+  FF_TX_D_1_18             : in std_logic;
+  FF_TX_D_1_19             : in std_logic;
+  FF_TX_D_1_20             : in std_logic;
+  FF_TX_D_1_21             : in std_logic;
+  FF_TX_D_1_22             : in std_logic;
+  FF_TX_D_1_23             : in std_logic;
+  FF_TX_D_2_0             : in std_logic;
+  FF_TX_D_2_1             : in std_logic;
+  FF_TX_D_2_2             : in std_logic;
+  FF_TX_D_2_3             : in std_logic;
+  FF_TX_D_2_4             : in std_logic;
+  FF_TX_D_2_5             : in std_logic;
+  FF_TX_D_2_6             : in std_logic;
+  FF_TX_D_2_7             : in std_logic;
+  FF_TX_D_2_8             : in std_logic;
+  FF_TX_D_2_9             : in std_logic;
+  FF_TX_D_2_10             : in std_logic;
+  FF_TX_D_2_11             : in std_logic;
+  FF_TX_D_2_12             : in std_logic;
+  FF_TX_D_2_13             : in std_logic;
+  FF_TX_D_2_14             : in std_logic;
+  FF_TX_D_2_15             : in std_logic;
+  FF_TX_D_2_16             : in std_logic;
+  FF_TX_D_2_17             : in std_logic;
+  FF_TX_D_2_18             : in std_logic;
+  FF_TX_D_2_19             : in std_logic;
+  FF_TX_D_2_20             : in std_logic;
+  FF_TX_D_2_21             : in std_logic;
+  FF_TX_D_2_22             : in std_logic;
+  FF_TX_D_2_23             : in std_logic;
+  FF_TX_D_3_0             : in std_logic;
+  FF_TX_D_3_1             : in std_logic;
+  FF_TX_D_3_2             : in std_logic;
+  FF_TX_D_3_3             : in std_logic;
+  FF_TX_D_3_4             : in std_logic;
+  FF_TX_D_3_5             : in std_logic;
+  FF_TX_D_3_6             : in std_logic;
+  FF_TX_D_3_7             : in std_logic;
+  FF_TX_D_3_8             : in std_logic;
+  FF_TX_D_3_9             : in std_logic;
+  FF_TX_D_3_10             : in std_logic;
+  FF_TX_D_3_11             : in std_logic;
+  FF_TX_D_3_12             : in std_logic;
+  FF_TX_D_3_13             : in std_logic;
+  FF_TX_D_3_14             : in std_logic;
+  FF_TX_D_3_15             : in std_logic;
+  FF_TX_D_3_16             : in std_logic;
+  FF_TX_D_3_17             : in std_logic;
+  FF_TX_D_3_18             : in std_logic;
+  FF_TX_D_3_19             : in std_logic;
+  FF_TX_D_3_20             : in std_logic;
+  FF_TX_D_3_21             : in std_logic;
+  FF_TX_D_3_22             : in std_logic;
+  FF_TX_D_3_23             : in std_logic;
+  FF_TXI_CLK_0             : in std_logic;
+  FF_TXI_CLK_1             : in std_logic;
+  FF_TXI_CLK_2             : in std_logic;
+  FF_TXI_CLK_3             : in std_logic;
+  FFC_CK_CORE_RX_0         : in std_logic;
+  FFC_CK_CORE_RX_1         : in std_logic;
+  FFC_CK_CORE_RX_2         : in std_logic;
+  FFC_CK_CORE_RX_3         : in std_logic;
+  FFC_CK_CORE_TX           : in std_logic;
+  FFC_EI_EN_0             : in std_logic;
+  FFC_EI_EN_1             : in std_logic;
+  FFC_EI_EN_2             : in std_logic;
+  FFC_EI_EN_3             : in std_logic;
+  FFC_ENABLE_CGALIGN_0             : in std_logic;
+  FFC_ENABLE_CGALIGN_1             : in std_logic;
+  FFC_ENABLE_CGALIGN_2             : in std_logic;
+  FFC_ENABLE_CGALIGN_3             : in std_logic;
+  FFC_FB_LOOPBACK_0             : in std_logic;
+  FFC_FB_LOOPBACK_1             : in std_logic;
+  FFC_FB_LOOPBACK_2             : in std_logic;
+  FFC_FB_LOOPBACK_3             : in std_logic;
+  FFC_LANE_RX_RST_0             : in std_logic;
+  FFC_LANE_RX_RST_1             : in std_logic;
+  FFC_LANE_RX_RST_2             : in std_logic;
+  FFC_LANE_RX_RST_3             : in std_logic;
+  FFC_LANE_TX_RST_0             : in std_logic;
+  FFC_LANE_TX_RST_1             : in std_logic;
+  FFC_LANE_TX_RST_2             : in std_logic;
+  FFC_LANE_TX_RST_3             : in std_logic;
+  FFC_MACRO_RST             : in std_logic;
+  FFC_PCI_DET_EN_0             : in std_logic;
+  FFC_PCI_DET_EN_1             : in std_logic;
+  FFC_PCI_DET_EN_2             : in std_logic;
+  FFC_PCI_DET_EN_3             : in std_logic;
+  FFC_PCIE_CT_0             : in std_logic;
+  FFC_PCIE_CT_1             : in std_logic;
+  FFC_PCIE_CT_2             : in std_logic;
+  FFC_PCIE_CT_3             : in std_logic;
+  FFC_PFIFO_CLR_0             : in std_logic;
+  FFC_PFIFO_CLR_1             : in std_logic;
+  FFC_PFIFO_CLR_2             : in std_logic;
+  FFC_PFIFO_CLR_3             : in std_logic;
+  FFC_QUAD_RST             : in std_logic;
+  FFC_RRST_0             : in std_logic;
+  FFC_RRST_1             : in std_logic;
+  FFC_RRST_2             : in std_logic;
+  FFC_RRST_3             : in std_logic;
+  FFC_RXPWDNB_0             : in std_logic;
+  FFC_RXPWDNB_1             : in std_logic;
+  FFC_RXPWDNB_2             : in std_logic;
+  FFC_RXPWDNB_3             : in std_logic;
+  FFC_SB_INV_RX_0             : in std_logic;
+  FFC_SB_INV_RX_1             : in std_logic;
+  FFC_SB_INV_RX_2             : in std_logic;
+  FFC_SB_INV_RX_3             : in std_logic;
+  FFC_SB_PFIFO_LP_0             : in std_logic;
+  FFC_SB_PFIFO_LP_1             : in std_logic;
+  FFC_SB_PFIFO_LP_2             : in std_logic;
+  FFC_SB_PFIFO_LP_3             : in std_logic;
+  FFC_SIGNAL_DETECT_0             : in std_logic;
+  FFC_SIGNAL_DETECT_1             : in std_logic;
+  FFC_SIGNAL_DETECT_2             : in std_logic;
+  FFC_SIGNAL_DETECT_3             : in std_logic;
+  FFC_SYNC_TOGGLE             : in std_logic;
+  FFC_TRST             : in std_logic;
+  FFC_TXPWDNB_0             : in std_logic;
+  FFC_TXPWDNB_1             : in std_logic;
+  FFC_TXPWDNB_2             : in std_logic;
+  FFC_TXPWDNB_3             : in std_logic;
+  FFC_RATE_MODE_RX_0        : in std_logic;
+  FFC_RATE_MODE_RX_1        : in std_logic;
+  FFC_RATE_MODE_RX_2        : in std_logic;
+  FFC_RATE_MODE_RX_3        : in std_logic;
+  FFC_RATE_MODE_TX_0        : in std_logic;
+  FFC_RATE_MODE_TX_1        : in std_logic;
+  FFC_RATE_MODE_TX_2        : in std_logic;
+  FFC_RATE_MODE_TX_3        : in std_logic;
+  FFC_DIV11_MODE_RX_0       : in std_logic;
+  FFC_DIV11_MODE_RX_1       : in std_logic;
+  FFC_DIV11_MODE_RX_2       : in std_logic;
+  FFC_DIV11_MODE_RX_3       : in std_logic;
+  FFC_DIV11_MODE_TX_0       : in std_logic;
+  FFC_DIV11_MODE_TX_1       : in std_logic;
+  FFC_DIV11_MODE_TX_2       : in std_logic;
+  FFC_DIV11_MODE_TX_3       : in std_logic;
+  LDR_CORE2TX_0             : in std_logic;
+  LDR_CORE2TX_1             : in std_logic;
+  LDR_CORE2TX_2             : in std_logic;
+  LDR_CORE2TX_3             : in std_logic;
+  FFC_LDR_CORE2TX_EN_0      : in std_logic;
+  FFC_LDR_CORE2TX_EN_1      : in std_logic;
+  FFC_LDR_CORE2TX_EN_2      : in std_logic;
+  FFC_LDR_CORE2TX_EN_3      : in std_logic;
+  PCIE_POWERDOWN_0_0      : in std_logic;
+  PCIE_POWERDOWN_0_1      : in std_logic;
+  PCIE_POWERDOWN_1_0      : in std_logic;
+  PCIE_POWERDOWN_1_1      : in std_logic;
+  PCIE_POWERDOWN_2_0      : in std_logic;
+  PCIE_POWERDOWN_2_1      : in std_logic;
+  PCIE_POWERDOWN_3_0      : in std_logic;
+  PCIE_POWERDOWN_3_1      : in std_logic;
+  PCIE_RXPOLARITY_0         : in std_logic;
+  PCIE_RXPOLARITY_1         : in std_logic;
+  PCIE_RXPOLARITY_2         : in std_logic;
+  PCIE_RXPOLARITY_3         : in std_logic;
+  PCIE_TXCOMPLIANCE_0       : in std_logic;
+  PCIE_TXCOMPLIANCE_1       : in std_logic;
+  PCIE_TXCOMPLIANCE_2       : in std_logic;
+  PCIE_TXCOMPLIANCE_3       : in std_logic;
+  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
+  SCIADDR0             : in std_logic;
+  SCIADDR1             : in std_logic;
+  SCIADDR2             : in std_logic;
+  SCIADDR3             : in std_logic;
+  SCIADDR4             : in std_logic;
+  SCIADDR5             : in std_logic;
+  SCIENAUX             : in std_logic;
+  SCIENCH0             : in std_logic;
+  SCIENCH1             : in std_logic;
+  SCIENCH2             : in std_logic;
+  SCIENCH3             : in std_logic;
+  SCIRD                : in std_logic;
+  SCISELAUX             : in std_logic;
+  SCISELCH0             : in std_logic;
+  SCISELCH1             : in std_logic;
+  SCISELCH2             : in std_logic;
+  SCISELCH3             : in std_logic;
+  SCIWDATA0             : in std_logic;
+  SCIWDATA1             : in std_logic;
+  SCIWDATA2             : in std_logic;
+  SCIWDATA3             : in std_logic;
+  SCIWDATA4             : in std_logic;
+  SCIWDATA5             : in std_logic;
+  SCIWDATA6             : in std_logic;
+  SCIWDATA7             : in std_logic;
+  SCIWSTN               : in std_logic;
+  REFCLK_FROM_NQ        : in std_logic;
+  HDOUTN0             : out std_logic;
+  HDOUTN1             : out std_logic;
+  HDOUTN2             : out std_logic;
+  HDOUTN3             : out std_logic;
+  HDOUTP0             : out std_logic;
+  HDOUTP1             : out std_logic;
+  HDOUTP2             : out std_logic;
+  HDOUTP3             : out std_logic;
+  COUT0             : out std_logic;
+  COUT1             : out std_logic;
+  COUT2             : out std_logic;
+  COUT3             : out std_logic;
+  COUT4             : out std_logic;
+  COUT5             : out std_logic;
+  COUT6             : out std_logic;
+  COUT7             : out std_logic;
+  COUT8             : out std_logic;
+  COUT9             : out std_logic;
+  COUT10             : out std_logic;
+  COUT11             : out std_logic;
+  COUT12             : out std_logic;
+  COUT13             : out std_logic;
+  COUT14             : out std_logic;
+  COUT15             : out std_logic;
+  COUT16             : out std_logic;
+  COUT17             : out std_logic;
+  COUT18             : out std_logic;
+  COUT19             : out std_logic;
+  FF_RX_D_0_0             : out std_logic;
+  FF_RX_D_0_1             : out std_logic;
+  FF_RX_D_0_2             : out std_logic;
+  FF_RX_D_0_3             : out std_logic;
+  FF_RX_D_0_4             : out std_logic;
+  FF_RX_D_0_5             : out std_logic;
+  FF_RX_D_0_6             : out std_logic;
+  FF_RX_D_0_7             : out std_logic;
+  FF_RX_D_0_8             : out std_logic;
+  FF_RX_D_0_9             : out std_logic;
+  FF_RX_D_0_10             : out std_logic;
+  FF_RX_D_0_11             : out std_logic;
+  FF_RX_D_0_12             : out std_logic;
+  FF_RX_D_0_13             : out std_logic;
+  FF_RX_D_0_14             : out std_logic;
+  FF_RX_D_0_15             : out std_logic;
+  FF_RX_D_0_16             : out std_logic;
+  FF_RX_D_0_17             : out std_logic;
+  FF_RX_D_0_18             : out std_logic;
+  FF_RX_D_0_19             : out std_logic;
+  FF_RX_D_0_20             : out std_logic;
+  FF_RX_D_0_21             : out std_logic;
+  FF_RX_D_0_22             : out std_logic;
+  FF_RX_D_0_23             : out std_logic;
+  FF_RX_D_1_0             : out std_logic;
+  FF_RX_D_1_1             : out std_logic;
+  FF_RX_D_1_2             : out std_logic;
+  FF_RX_D_1_3             : out std_logic;
+  FF_RX_D_1_4             : out std_logic;
+  FF_RX_D_1_5             : out std_logic;
+  FF_RX_D_1_6             : out std_logic;
+  FF_RX_D_1_7             : out std_logic;
+  FF_RX_D_1_8             : out std_logic;
+  FF_RX_D_1_9             : out std_logic;
+  FF_RX_D_1_10             : out std_logic;
+  FF_RX_D_1_11             : out std_logic;
+  FF_RX_D_1_12             : out std_logic;
+  FF_RX_D_1_13             : out std_logic;
+  FF_RX_D_1_14             : out std_logic;
+  FF_RX_D_1_15             : out std_logic;
+  FF_RX_D_1_16             : out std_logic;
+  FF_RX_D_1_17             : out std_logic;
+  FF_RX_D_1_18             : out std_logic;
+  FF_RX_D_1_19             : out std_logic;
+  FF_RX_D_1_20             : out std_logic;
+  FF_RX_D_1_21             : out std_logic;
+  FF_RX_D_1_22             : out std_logic;
+  FF_RX_D_1_23             : out std_logic;
+  FF_RX_D_2_0             : out std_logic;
+  FF_RX_D_2_1             : out std_logic;
+  FF_RX_D_2_2             : out std_logic;
+  FF_RX_D_2_3             : out std_logic;
+  FF_RX_D_2_4             : out std_logic;
+  FF_RX_D_2_5             : out std_logic;
+  FF_RX_D_2_6             : out std_logic;
+  FF_RX_D_2_7             : out std_logic;
+  FF_RX_D_2_8             : out std_logic;
+  FF_RX_D_2_9             : out std_logic;
+  FF_RX_D_2_10             : out std_logic;
+  FF_RX_D_2_11             : out std_logic;
+  FF_RX_D_2_12             : out std_logic;
+  FF_RX_D_2_13             : out std_logic;
+  FF_RX_D_2_14             : out std_logic;
+  FF_RX_D_2_15             : out std_logic;
+  FF_RX_D_2_16             : out std_logic;
+  FF_RX_D_2_17             : out std_logic;
+  FF_RX_D_2_18             : out std_logic;
+  FF_RX_D_2_19             : out std_logic;
+  FF_RX_D_2_20             : out std_logic;
+  FF_RX_D_2_21             : out std_logic;
+  FF_RX_D_2_22             : out std_logic;
+  FF_RX_D_2_23             : out std_logic;
+  FF_RX_D_3_0             : out std_logic;
+  FF_RX_D_3_1             : out std_logic;
+  FF_RX_D_3_2             : out std_logic;
+  FF_RX_D_3_3             : out std_logic;
+  FF_RX_D_3_4             : out std_logic;
+  FF_RX_D_3_5             : out std_logic;
+  FF_RX_D_3_6             : out std_logic;
+  FF_RX_D_3_7             : out std_logic;
+  FF_RX_D_3_8             : out std_logic;
+  FF_RX_D_3_9             : out std_logic;
+  FF_RX_D_3_10             : out std_logic;
+  FF_RX_D_3_11             : out std_logic;
+  FF_RX_D_3_12             : out std_logic;
+  FF_RX_D_3_13             : out std_logic;
+  FF_RX_D_3_14             : out std_logic;
+  FF_RX_D_3_15             : out std_logic;
+  FF_RX_D_3_16             : out std_logic;
+  FF_RX_D_3_17             : out std_logic;
+  FF_RX_D_3_18             : out std_logic;
+  FF_RX_D_3_19             : out std_logic;
+  FF_RX_D_3_20             : out std_logic;
+  FF_RX_D_3_21             : out std_logic;
+  FF_RX_D_3_22             : out std_logic;
+  FF_RX_D_3_23             : out std_logic;
+  FF_RX_F_CLK_0             : out std_logic;
+  FF_RX_F_CLK_1             : out std_logic;
+  FF_RX_F_CLK_2             : out std_logic;
+  FF_RX_F_CLK_3             : out std_logic;
+  FF_RX_H_CLK_0             : out std_logic;
+  FF_RX_H_CLK_1             : out std_logic;
+  FF_RX_H_CLK_2             : out std_logic;
+  FF_RX_H_CLK_3             : out std_logic;
+  FF_TX_F_CLK_0             : out std_logic;
+  FF_TX_F_CLK_1             : out std_logic;
+  FF_TX_F_CLK_2             : out std_logic;
+  FF_TX_F_CLK_3             : out std_logic;
+  FF_TX_H_CLK_0             : out std_logic;
+  FF_TX_H_CLK_1             : out std_logic;
+  FF_TX_H_CLK_2             : out std_logic;
+  FF_TX_H_CLK_3             : out std_logic;
+  FFS_CC_OVERRUN_0             : out std_logic;
+  FFS_CC_OVERRUN_1             : out std_logic;
+  FFS_CC_OVERRUN_2             : out std_logic;
+  FFS_CC_OVERRUN_3             : out std_logic;
+  FFS_CC_UNDERRUN_0             : out std_logic;
+  FFS_CC_UNDERRUN_1             : out std_logic;
+  FFS_CC_UNDERRUN_2             : out std_logic;
+  FFS_CC_UNDERRUN_3             : out std_logic;
+  FFS_LS_SYNC_STATUS_0             : out std_logic;
+  FFS_LS_SYNC_STATUS_1             : out std_logic;
+  FFS_LS_SYNC_STATUS_2             : out std_logic;
+  FFS_LS_SYNC_STATUS_3             : out std_logic;
+  FFS_CDR_TRAIN_DONE_0             : out std_logic;
+  FFS_CDR_TRAIN_DONE_1             : out std_logic;
+  FFS_CDR_TRAIN_DONE_2             : out std_logic;
+  FFS_CDR_TRAIN_DONE_3             : out std_logic;
+  FFS_PCIE_CON_0             : out std_logic;
+  FFS_PCIE_CON_1             : out std_logic;
+  FFS_PCIE_CON_2             : out std_logic;
+  FFS_PCIE_CON_3             : out std_logic;
+  FFS_PCIE_DONE_0             : out std_logic;
+  FFS_PCIE_DONE_1             : out std_logic;
+  FFS_PCIE_DONE_2             : out std_logic;
+  FFS_PCIE_DONE_3             : out std_logic;
+  FFS_PLOL             : out std_logic;
+  FFS_RLOL_0             : out std_logic;
+  FFS_RLOL_1             : out std_logic;
+  FFS_RLOL_2             : out std_logic;
+  FFS_RLOL_3             : out std_logic;
+  FFS_RLOS_HI_0             : out std_logic;
+  FFS_RLOS_HI_1             : out std_logic;
+  FFS_RLOS_HI_2             : out std_logic;
+  FFS_RLOS_HI_3             : out std_logic;
+  FFS_RLOS_LO_0             : out std_logic;
+  FFS_RLOS_LO_1             : out std_logic;
+  FFS_RLOS_LO_2             : out std_logic;
+  FFS_RLOS_LO_3             : out std_logic;
+  FFS_RXFBFIFO_ERROR_0             : out std_logic;
+  FFS_RXFBFIFO_ERROR_1             : out std_logic;
+  FFS_RXFBFIFO_ERROR_2             : out std_logic;
+  FFS_RXFBFIFO_ERROR_3             : out std_logic;
+  FFS_TXFBFIFO_ERROR_0             : out std_logic;
+  FFS_TXFBFIFO_ERROR_1             : out std_logic;
+  FFS_TXFBFIFO_ERROR_2             : out std_logic;
+  FFS_TXFBFIFO_ERROR_3             : out std_logic;
+  PCIE_PHYSTATUS_0             : out std_logic;
+  PCIE_PHYSTATUS_1             : out std_logic;
+  PCIE_PHYSTATUS_2             : out std_logic;
+  PCIE_PHYSTATUS_3             : out std_logic;
+  PCIE_RXVALID_0               : out std_logic;
+  PCIE_RXVALID_1               : out std_logic;
+  PCIE_RXVALID_2               : out std_logic;
+  PCIE_RXVALID_3               : out std_logic;
+  FFS_SKP_ADDED_0                  : out std_logic;
+  FFS_SKP_ADDED_1                  : out std_logic;
+  FFS_SKP_ADDED_2                  : out std_logic;
+  FFS_SKP_ADDED_3                  : out std_logic;
+  FFS_SKP_DELETED_0                : out std_logic;
+  FFS_SKP_DELETED_1                : out std_logic;
+  FFS_SKP_DELETED_2                : out std_logic;
+  FFS_SKP_DELETED_3                : out std_logic;
+  LDR_RX2CORE_0                    : out std_logic;
+  LDR_RX2CORE_1                    : out std_logic;
+  LDR_RX2CORE_2                    : out std_logic;
+  LDR_RX2CORE_3                    : out std_logic;
+  REFCK2CORE             : out std_logic;
+  SCIINT                : out std_logic;
+  SCIRDATA0             : out std_logic;
+  SCIRDATA1             : out std_logic;
+  SCIRDATA2             : out std_logic;
+  SCIRDATA3             : out std_logic;
+  SCIRDATA4             : out std_logic;
+  SCIRDATA5             : out std_logic;
+  SCIRDATA6             : out std_logic;
+  SCIRDATA7             : out std_logic;
+  REFCLK_TO_NQ          : out std_logic
+);
+end component;
+   attribute CONFIG_FILE: string;
+   attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
+   attribute QUAD_MODE: string;
+   attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
+   attribute PLL_SRC: string;
+   attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
+   attribute CH0_CDR_SRC: string;
+   attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+   attribute CH1_CDR_SRC: string;
+   attribute CH1_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+   attribute CH2_CDR_SRC: string;
+   attribute CH2_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+   attribute CH3_CDR_SRC: string;
+   attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200";
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "200";
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "200";
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200";
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100";
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "100";
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "100";
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100";
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200";
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200";
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200";
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "200";
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100";
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100";
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100";
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100";
+   attribute black_box_pad_pin: string;
+   attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
+
+signal refclk_from_nq : std_logic := '0';
+signal fpsc_vlo : std_logic := '0';
+signal fpsc_vhi : std_logic := '1';
+signal cin : std_logic_vector (11 downto 0) := "000000000000";
+signal cout : std_logic_vector (19 downto 0);
+signal    tx_full_clk_ch0_sig   :   std_logic;
+signal    tx_full_clk_ch1_sig   :   std_logic;
+signal    tx_full_clk_ch2_sig   :   std_logic;
+signal    tx_full_clk_ch3_sig   :   std_logic;
+
+signal    refclk2fpga_sig  :   std_logic;
+signal    tx_pll_lol_qd_sig  :   std_logic;
+signal    rx_los_low_ch0_sig  :   std_logic;
+signal    rx_los_low_ch1_sig  :   std_logic;
+signal    rx_los_low_ch2_sig  :   std_logic;
+signal    rx_los_low_ch3_sig  :   std_logic;
+signal    rx_cdr_lol_ch0_sig  :   std_logic;
+signal    rx_cdr_lol_ch1_sig  :   std_logic;
+signal    rx_cdr_lol_ch2_sig  :   std_logic;
+signal    rx_cdr_lol_ch3_sig  :   std_logic;
+
+
+
+
+
+begin
+
+vlo_inst : VLO port map(Z => fpsc_vlo);
+vhi_inst : VHI port map(Z => fpsc_vhi);
+
+    rx_los_low_ch0_s <= rx_los_low_ch0_sig;
+    rx_los_low_ch1_s <= rx_los_low_ch1_sig;
+    rx_los_low_ch2_s <= rx_los_low_ch2_sig;
+    rx_los_low_ch3_s <= rx_los_low_ch3_sig;
+    rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig;
+    rx_cdr_lol_ch1_s <= rx_cdr_lol_ch1_sig;
+    rx_cdr_lol_ch2_s <= rx_cdr_lol_ch2_sig;
+    rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig;
+  tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
+  tx_full_clk_ch0 <= tx_full_clk_ch0_sig;
+  tx_full_clk_ch1 <= tx_full_clk_ch1_sig;
+  tx_full_clk_ch2 <= tx_full_clk_ch2_sig;
+  tx_full_clk_ch3 <= tx_full_clk_ch3_sig;
+
+-- pcs_quad instance
+PCSD_INST : PCSD
+--synopsys translate_off
+  generic map (CONFIG_FILE => USER_CONFIG_FILE,
+               QUAD_MODE => "SINGLE",
+               CH0_CDR_SRC => "REFCLK_CORE",
+               CH1_CDR_SRC => "REFCLK_CORE",
+               CH2_CDR_SRC => "REFCLK_CORE",
+               CH3_CDR_SRC => "REFCLK_CORE",
+               PLL_SRC  => "REFCLK_CORE"
+  )
+--synopsys translate_on
+port map  (
+  REFCLKP => fpsc_vlo,
+  REFCLKN => fpsc_vlo,
+
+----- CH0 -----
+  HDOUTP0 => hdoutp_ch0,
+  HDOUTN0 => hdoutn_ch0,
+  HDINP0 => hdinp_ch0,
+  HDINN0 => hdinn_ch0,
+  PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
+  PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
+  PCIE_RXPOLARITY_0 => fpsc_vlo,
+  PCIE_POWERDOWN_0_0 => fpsc_vlo,
+  PCIE_POWERDOWN_0_1 => fpsc_vlo,
+  PCIE_RXVALID_0 => open,
+  PCIE_PHYSTATUS_0 => open,
+  SCISELCH0 => sci_sel_ch0,
+  SCIENCH0 => fpsc_vhi,
+  FF_RXI_CLK_0 => rxiclk_ch0,
+  FF_TXI_CLK_0 => txiclk_ch0,
+  FF_EBRD_CLK_0 => fpsc_vlo,
+  FF_RX_F_CLK_0 => rx_full_clk_ch0,
+  FF_RX_H_CLK_0 => rx_half_clk_ch0,
+  FF_TX_F_CLK_0 => tx_full_clk_ch0_sig,
+  FF_TX_H_CLK_0 => tx_half_clk_ch0,
+  FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0,
+  FF_TX_D_0_0 => txdata_ch0(0),
+  FF_TX_D_0_1 => txdata_ch0(1),
+  FF_TX_D_0_2 => txdata_ch0(2),
+  FF_TX_D_0_3 => txdata_ch0(3),
+  FF_TX_D_0_4 => txdata_ch0(4),
+  FF_TX_D_0_5 => txdata_ch0(5),
+  FF_TX_D_0_6 => txdata_ch0(6),
+  FF_TX_D_0_7 => txdata_ch0(7),
+  FF_TX_D_0_8 => tx_k_ch0,
+  FF_TX_D_0_9 => tx_force_disp_ch0,
+  FF_TX_D_0_10 => tx_disp_sel_ch0,
+  FF_TX_D_0_11 => fpsc_vlo,
+  FF_TX_D_0_12 => fpsc_vlo,
+  FF_TX_D_0_13 => fpsc_vlo,
+  FF_TX_D_0_14 => fpsc_vlo,
+  FF_TX_D_0_15 => fpsc_vlo,
+  FF_TX_D_0_16 => fpsc_vlo,
+  FF_TX_D_0_17 => fpsc_vlo,
+  FF_TX_D_0_18 => fpsc_vlo,
+  FF_TX_D_0_19 => fpsc_vlo,
+  FF_TX_D_0_20 => fpsc_vlo,
+  FF_TX_D_0_21 => fpsc_vlo,
+  FF_TX_D_0_22 => fpsc_vlo,
+  FF_TX_D_0_23 => fpsc_vlo,
+  FF_RX_D_0_0 => rxdata_ch0(0),
+  FF_RX_D_0_1 => rxdata_ch0(1),
+  FF_RX_D_0_2 => rxdata_ch0(2),
+  FF_RX_D_0_3 => rxdata_ch0(3),
+  FF_RX_D_0_4 => rxdata_ch0(4),
+  FF_RX_D_0_5 => rxdata_ch0(5),
+  FF_RX_D_0_6 => rxdata_ch0(6),
+  FF_RX_D_0_7 => rxdata_ch0(7),
+  FF_RX_D_0_8 => rx_k_ch0,
+  FF_RX_D_0_9 => rx_disp_err_ch0,
+  FF_RX_D_0_10 => rx_cv_err_ch0,
+  FF_RX_D_0_11 => open,
+  FF_RX_D_0_12 => open,
+  FF_RX_D_0_13 => open,
+  FF_RX_D_0_14 => open,
+  FF_RX_D_0_15 => open,
+  FF_RX_D_0_16 => open,
+  FF_RX_D_0_17 => open,
+  FF_RX_D_0_18 => open,
+  FF_RX_D_0_19 => open,
+  FF_RX_D_0_20 => open,
+  FF_RX_D_0_21 => open,
+  FF_RX_D_0_22 => open,
+  FF_RX_D_0_23 => open,
+
+  FFC_RRST_0 => rx_serdes_rst_ch0_c,
+  FFC_SIGNAL_DETECT_0 => fpsc_vlo,
+  FFC_SB_PFIFO_LP_0 => sb_felb_ch0_c,
+  FFC_PFIFO_CLR_0 => sb_felb_rst_ch0_c,
+  FFC_SB_INV_RX_0 => fpsc_vlo,
+  FFC_PCIE_CT_0 => fpsc_vlo,
+  FFC_PCI_DET_EN_0 => fpsc_vlo,
+  FFC_FB_LOOPBACK_0 => fpsc_vlo,
+  FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
+  FFC_EI_EN_0 => fpsc_vlo,
+  FFC_LANE_TX_RST_0 => tx_pcs_rst_ch0_c,
+  FFC_TXPWDNB_0 => tx_pwrup_ch0_c,
+  FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c,
+  FFC_RXPWDNB_0 => rx_pwrup_ch0_c,
+  FFS_RLOS_LO_0 => rx_los_low_ch0_sig,
+  FFS_RLOS_HI_0 => open,
+  FFS_PCIE_CON_0 => open,
+  FFS_PCIE_DONE_0 => open,
+  FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s,
+  FFS_CC_OVERRUN_0 => open,
+  FFS_CC_UNDERRUN_0 => open,
+  FFS_SKP_ADDED_0 => open,
+  FFS_SKP_DELETED_0 => open,
+  FFS_RLOL_0 => rx_cdr_lol_ch0_sig,
+  FFS_RXFBFIFO_ERROR_0 => open,
+  FFS_TXFBFIFO_ERROR_0 => open,
+  LDR_CORE2TX_0 => fpsc_vlo,
+  FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
+  LDR_RX2CORE_0 => open,
+  FFS_CDR_TRAIN_DONE_0 => open,
+  FFC_DIV11_MODE_TX_0 => fpsc_vlo,
+  FFC_RATE_MODE_TX_0 => tx_div2_mode_ch0_c,
+  FFC_DIV11_MODE_RX_0 => fpsc_vlo,
+  FFC_RATE_MODE_RX_0 => rx_div2_mode_ch0_c,
+
+----- CH1 -----
+  HDOUTP1 => hdoutp_ch1,
+  HDOUTN1 => hdoutn_ch1,
+  HDINP1 => hdinp_ch1,
+  HDINN1 => hdinn_ch1,
+  PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
+  PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
+  PCIE_RXPOLARITY_1 => fpsc_vlo,
+  PCIE_POWERDOWN_1_0 => fpsc_vlo,
+  PCIE_POWERDOWN_1_1 => fpsc_vlo,
+  PCIE_RXVALID_1 => open,
+  PCIE_PHYSTATUS_1 => open,
+  SCISELCH1 => sci_sel_ch1,
+  SCIENCH1 => fpsc_vhi,
+  FF_RXI_CLK_1 => rxiclk_ch1,
+  FF_TXI_CLK_1 => txiclk_ch1,
+  FF_EBRD_CLK_1 => fpsc_vlo,
+  FF_RX_F_CLK_1 => rx_full_clk_ch1,
+  FF_RX_H_CLK_1 => rx_half_clk_ch1,
+  FF_TX_F_CLK_1 => tx_full_clk_ch1_sig,
+  FF_TX_H_CLK_1 => tx_half_clk_ch1,
+  FFC_CK_CORE_RX_1 => fpga_rxrefclk_ch1,
+  FF_TX_D_1_0 => txdata_ch1(0),
+  FF_TX_D_1_1 => txdata_ch1(1),
+  FF_TX_D_1_2 => txdata_ch1(2),
+  FF_TX_D_1_3 => txdata_ch1(3),
+  FF_TX_D_1_4 => txdata_ch1(4),
+  FF_TX_D_1_5 => txdata_ch1(5),
+  FF_TX_D_1_6 => txdata_ch1(6),
+  FF_TX_D_1_7 => txdata_ch1(7),
+  FF_TX_D_1_8 => tx_k_ch1,
+  FF_TX_D_1_9 => tx_force_disp_ch1,
+  FF_TX_D_1_10 => tx_disp_sel_ch1,
+  FF_TX_D_1_11 => fpsc_vlo,
+  FF_TX_D_1_12 => fpsc_vlo,
+  FF_TX_D_1_13 => fpsc_vlo,
+  FF_TX_D_1_14 => fpsc_vlo,
+  FF_TX_D_1_15 => fpsc_vlo,
+  FF_TX_D_1_16 => fpsc_vlo,
+  FF_TX_D_1_17 => fpsc_vlo,
+  FF_TX_D_1_18 => fpsc_vlo,
+  FF_TX_D_1_19 => fpsc_vlo,
+  FF_TX_D_1_20 => fpsc_vlo,
+  FF_TX_D_1_21 => fpsc_vlo,
+  FF_TX_D_1_22 => fpsc_vlo,
+  FF_TX_D_1_23 => fpsc_vlo,
+  FF_RX_D_1_0 => rxdata_ch1(0),
+  FF_RX_D_1_1 => rxdata_ch1(1),
+  FF_RX_D_1_2 => rxdata_ch1(2),
+  FF_RX_D_1_3 => rxdata_ch1(3),
+  FF_RX_D_1_4 => rxdata_ch1(4),
+  FF_RX_D_1_5 => rxdata_ch1(5),
+  FF_RX_D_1_6 => rxdata_ch1(6),
+  FF_RX_D_1_7 => rxdata_ch1(7),
+  FF_RX_D_1_8 => rx_k_ch1,
+  FF_RX_D_1_9 => rx_disp_err_ch1,
+  FF_RX_D_1_10 => rx_cv_err_ch1,
+  FF_RX_D_1_11 => open,
+  FF_RX_D_1_12 => open,
+  FF_RX_D_1_13 => open,
+  FF_RX_D_1_14 => open,
+  FF_RX_D_1_15 => open,
+  FF_RX_D_1_16 => open,
+  FF_RX_D_1_17 => open,
+  FF_RX_D_1_18 => open,
+  FF_RX_D_1_19 => open,
+  FF_RX_D_1_20 => open,
+  FF_RX_D_1_21 => open,
+  FF_RX_D_1_22 => open,
+  FF_RX_D_1_23 => open,
+
+  FFC_RRST_1 => rx_serdes_rst_ch1_c,
+  FFC_SIGNAL_DETECT_1 => fpsc_vlo,
+  FFC_SB_PFIFO_LP_1 => sb_felb_ch1_c,
+  FFC_PFIFO_CLR_1 => sb_felb_rst_ch1_c,
+  FFC_SB_INV_RX_1 => fpsc_vlo,
+  FFC_PCIE_CT_1 => fpsc_vlo,
+  FFC_PCI_DET_EN_1 => fpsc_vlo,
+  FFC_FB_LOOPBACK_1 => fpsc_vlo,
+  FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
+  FFC_EI_EN_1 => fpsc_vlo,
+  FFC_LANE_TX_RST_1 => tx_pcs_rst_ch1_c,
+  FFC_TXPWDNB_1 => tx_pwrup_ch1_c,
+  FFC_LANE_RX_RST_1 => rx_pcs_rst_ch1_c,
+  FFC_RXPWDNB_1 => rx_pwrup_ch1_c,
+  FFS_RLOS_LO_1 => rx_los_low_ch1_sig,
+  FFS_RLOS_HI_1 => open,
+  FFS_PCIE_CON_1 => open,
+  FFS_PCIE_DONE_1 => open,
+  FFS_LS_SYNC_STATUS_1 => lsm_status_ch1_s,
+  FFS_CC_OVERRUN_1 => open,
+  FFS_CC_UNDERRUN_1 => open,
+  FFS_SKP_ADDED_1 => open,
+  FFS_SKP_DELETED_1 => open,
+  FFS_RLOL_1 => rx_cdr_lol_ch1_sig,
+  FFS_RXFBFIFO_ERROR_1 => open,
+  FFS_TXFBFIFO_ERROR_1 => open,
+  LDR_CORE2TX_1 => fpsc_vlo,
+  FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
+  LDR_RX2CORE_1 => open,
+  FFS_CDR_TRAIN_DONE_1 => open,
+  FFC_DIV11_MODE_TX_1 => fpsc_vlo,
+  FFC_RATE_MODE_TX_1 => tx_div2_mode_ch1_c,
+  FFC_DIV11_MODE_RX_1 => fpsc_vlo,
+  FFC_RATE_MODE_RX_1 => rx_div2_mode_ch1_c,
+
+----- CH2 -----
+  HDOUTP2 => hdoutp_ch2,
+  HDOUTN2 => hdoutn_ch2,
+  HDINP2 => hdinp_ch2,
+  HDINN2 => hdinn_ch2,
+  PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
+  PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
+  PCIE_RXPOLARITY_2 => fpsc_vlo,
+  PCIE_POWERDOWN_2_0 => fpsc_vlo,
+  PCIE_POWERDOWN_2_1 => fpsc_vlo,
+  PCIE_RXVALID_2 => open,
+  PCIE_PHYSTATUS_2 => open,
+  SCISELCH2 => sci_sel_ch2,
+  SCIENCH2 => fpsc_vhi,
+  FF_RXI_CLK_2 => rxiclk_ch2,
+  FF_TXI_CLK_2 => txiclk_ch2,
+  FF_EBRD_CLK_2 => fpsc_vlo,
+  FF_RX_F_CLK_2 => rx_full_clk_ch2,
+  FF_RX_H_CLK_2 => rx_half_clk_ch2,
+  FF_TX_F_CLK_2 => tx_full_clk_ch2_sig,
+  FF_TX_H_CLK_2 => tx_half_clk_ch2,
+  FFC_CK_CORE_RX_2 => fpga_rxrefclk_ch2,
+  FF_TX_D_2_0 => txdata_ch2(0),
+  FF_TX_D_2_1 => txdata_ch2(1),
+  FF_TX_D_2_2 => txdata_ch2(2),
+  FF_TX_D_2_3 => txdata_ch2(3),
+  FF_TX_D_2_4 => txdata_ch2(4),
+  FF_TX_D_2_5 => txdata_ch2(5),
+  FF_TX_D_2_6 => txdata_ch2(6),
+  FF_TX_D_2_7 => txdata_ch2(7),
+  FF_TX_D_2_8 => tx_k_ch2,
+  FF_TX_D_2_9 => tx_force_disp_ch2,
+  FF_TX_D_2_10 => tx_disp_sel_ch2,
+  FF_TX_D_2_11 => fpsc_vlo,
+  FF_TX_D_2_12 => fpsc_vlo,
+  FF_TX_D_2_13 => fpsc_vlo,
+  FF_TX_D_2_14 => fpsc_vlo,
+  FF_TX_D_2_15 => fpsc_vlo,
+  FF_TX_D_2_16 => fpsc_vlo,
+  FF_TX_D_2_17 => fpsc_vlo,
+  FF_TX_D_2_18 => fpsc_vlo,
+  FF_TX_D_2_19 => fpsc_vlo,
+  FF_TX_D_2_20 => fpsc_vlo,
+  FF_TX_D_2_21 => fpsc_vlo,
+  FF_TX_D_2_22 => fpsc_vlo,
+  FF_TX_D_2_23 => fpsc_vlo,
+  FF_RX_D_2_0 => rxdata_ch2(0),
+  FF_RX_D_2_1 => rxdata_ch2(1),
+  FF_RX_D_2_2 => rxdata_ch2(2),
+  FF_RX_D_2_3 => rxdata_ch2(3),
+  FF_RX_D_2_4 => rxdata_ch2(4),
+  FF_RX_D_2_5 => rxdata_ch2(5),
+  FF_RX_D_2_6 => rxdata_ch2(6),
+  FF_RX_D_2_7 => rxdata_ch2(7),
+  FF_RX_D_2_8 => rx_k_ch2,
+  FF_RX_D_2_9 => rx_disp_err_ch2,
+  FF_RX_D_2_10 => rx_cv_err_ch2,
+  FF_RX_D_2_11 => open,
+  FF_RX_D_2_12 => open,
+  FF_RX_D_2_13 => open,
+  FF_RX_D_2_14 => open,
+  FF_RX_D_2_15 => open,
+  FF_RX_D_2_16 => open,
+  FF_RX_D_2_17 => open,
+  FF_RX_D_2_18 => open,
+  FF_RX_D_2_19 => open,
+  FF_RX_D_2_20 => open,
+  FF_RX_D_2_21 => open,
+  FF_RX_D_2_22 => open,
+  FF_RX_D_2_23 => open,
+
+  FFC_RRST_2 => rx_serdes_rst_ch2_c,
+  FFC_SIGNAL_DETECT_2 => fpsc_vlo,
+  FFC_SB_PFIFO_LP_2 => sb_felb_ch2_c,
+  FFC_PFIFO_CLR_2 => sb_felb_rst_ch2_c,
+  FFC_SB_INV_RX_2 => fpsc_vlo,
+  FFC_PCIE_CT_2 => fpsc_vlo,
+  FFC_PCI_DET_EN_2 => fpsc_vlo,
+  FFC_FB_LOOPBACK_2 => fpsc_vlo,
+  FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
+  FFC_EI_EN_2 => fpsc_vlo,
+  FFC_LANE_TX_RST_2 => tx_pcs_rst_ch2_c,
+  FFC_TXPWDNB_2 => tx_pwrup_ch2_c,
+  FFC_LANE_RX_RST_2 => rx_pcs_rst_ch2_c,
+  FFC_RXPWDNB_2 => rx_pwrup_ch2_c,
+  FFS_RLOS_LO_2 => rx_los_low_ch2_sig,
+  FFS_RLOS_HI_2 => open,
+  FFS_PCIE_CON_2 => open,
+  FFS_PCIE_DONE_2 => open,
+  FFS_LS_SYNC_STATUS_2 => lsm_status_ch2_s,
+  FFS_CC_OVERRUN_2 => open,
+  FFS_CC_UNDERRUN_2 => open,
+  FFS_SKP_ADDED_2 => open,
+  FFS_SKP_DELETED_2 => open,
+  FFS_RLOL_2 => rx_cdr_lol_ch2_sig,
+  FFS_RXFBFIFO_ERROR_2 => open,
+  FFS_TXFBFIFO_ERROR_2 => open,
+  LDR_CORE2TX_2 => fpsc_vlo,
+  FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
+  LDR_RX2CORE_2 => open,
+  FFS_CDR_TRAIN_DONE_2 => open,
+  FFC_DIV11_MODE_TX_2 => fpsc_vlo,
+  FFC_RATE_MODE_TX_2 => tx_div2_mode_ch2_c,
+  FFC_DIV11_MODE_RX_2 => fpsc_vlo,
+  FFC_RATE_MODE_RX_2 => rx_div2_mode_ch2_c,
+
+----- CH3 -----
+  HDOUTP3 => hdoutp_ch3,
+  HDOUTN3 => hdoutn_ch3,
+  HDINP3 => hdinp_ch3,
+  HDINN3 => hdinn_ch3,
+  PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
+  PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
+  PCIE_RXPOLARITY_3 => fpsc_vlo,
+  PCIE_POWERDOWN_3_0 => fpsc_vlo,
+  PCIE_POWERDOWN_3_1 => fpsc_vlo,
+  PCIE_RXVALID_3 => open,
+  PCIE_PHYSTATUS_3 => open,
+  SCISELCH3 => sci_sel_ch3,
+  SCIENCH3 => fpsc_vhi,
+  FF_RXI_CLK_3 => rxiclk_ch3,
+  FF_TXI_CLK_3 => txiclk_ch3,
+  FF_EBRD_CLK_3 => fpsc_vlo,
+  FF_RX_F_CLK_3 => rx_full_clk_ch3,
+  FF_RX_H_CLK_3 => rx_half_clk_ch3,
+  FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,
+  FF_TX_H_CLK_3 => tx_half_clk_ch3,
+  FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3,
+  FF_TX_D_3_0 => txdata_ch3(0),
+  FF_TX_D_3_1 => txdata_ch3(1),
+  FF_TX_D_3_2 => txdata_ch3(2),
+  FF_TX_D_3_3 => txdata_ch3(3),
+  FF_TX_D_3_4 => txdata_ch3(4),
+  FF_TX_D_3_5 => txdata_ch3(5),
+  FF_TX_D_3_6 => txdata_ch3(6),
+  FF_TX_D_3_7 => txdata_ch3(7),
+  FF_TX_D_3_8 => tx_k_ch3,
+  FF_TX_D_3_9 => tx_force_disp_ch3,
+  FF_TX_D_3_10 => tx_disp_sel_ch3,
+  FF_TX_D_3_11 => fpsc_vlo,
+  FF_TX_D_3_12 => fpsc_vlo,
+  FF_TX_D_3_13 => fpsc_vlo,
+  FF_TX_D_3_14 => fpsc_vlo,
+  FF_TX_D_3_15 => fpsc_vlo,
+  FF_TX_D_3_16 => fpsc_vlo,
+  FF_TX_D_3_17 => fpsc_vlo,
+  FF_TX_D_3_18 => fpsc_vlo,
+  FF_TX_D_3_19 => fpsc_vlo,
+  FF_TX_D_3_20 => fpsc_vlo,
+  FF_TX_D_3_21 => fpsc_vlo,
+  FF_TX_D_3_22 => fpsc_vlo,
+  FF_TX_D_3_23 => fpsc_vlo,
+  FF_RX_D_3_0 => rxdata_ch3(0),
+  FF_RX_D_3_1 => rxdata_ch3(1),
+  FF_RX_D_3_2 => rxdata_ch3(2),
+  FF_RX_D_3_3 => rxdata_ch3(3),
+  FF_RX_D_3_4 => rxdata_ch3(4),
+  FF_RX_D_3_5 => rxdata_ch3(5),
+  FF_RX_D_3_6 => rxdata_ch3(6),
+  FF_RX_D_3_7 => rxdata_ch3(7),
+  FF_RX_D_3_8 => rx_k_ch3,
+  FF_RX_D_3_9 => rx_disp_err_ch3,
+  FF_RX_D_3_10 => rx_cv_err_ch3,
+  FF_RX_D_3_11 => open,
+  FF_RX_D_3_12 => open,
+  FF_RX_D_3_13 => open,
+  FF_RX_D_3_14 => open,
+  FF_RX_D_3_15 => open,
+  FF_RX_D_3_16 => open,
+  FF_RX_D_3_17 => open,
+  FF_RX_D_3_18 => open,
+  FF_RX_D_3_19 => open,
+  FF_RX_D_3_20 => open,
+  FF_RX_D_3_21 => open,
+  FF_RX_D_3_22 => open,
+  FF_RX_D_3_23 => open,
+
+  FFC_RRST_3 => rx_serdes_rst_ch3_c,
+  FFC_SIGNAL_DETECT_3 => fpsc_vlo,
+  FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c,
+  FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c,
+  FFC_SB_INV_RX_3 => fpsc_vlo,
+  FFC_PCIE_CT_3 => fpsc_vlo,
+  FFC_PCI_DET_EN_3 => fpsc_vlo,
+  FFC_FB_LOOPBACK_3 => fpsc_vlo,
+  FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
+  FFC_EI_EN_3 => fpsc_vlo,
+  FFC_LANE_TX_RST_3 => tx_pcs_rst_ch3_c,
+  FFC_TXPWDNB_3 => tx_pwrup_ch3_c,
+  FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c,
+  FFC_RXPWDNB_3 => rx_pwrup_ch3_c,
+  FFS_RLOS_LO_3 => rx_los_low_ch3_sig,
+  FFS_RLOS_HI_3 => open,
+  FFS_PCIE_CON_3 => open,
+  FFS_PCIE_DONE_3 => open,
+  FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s,
+  FFS_CC_OVERRUN_3 => open,
+  FFS_CC_UNDERRUN_3 => open,
+  FFS_SKP_ADDED_3 => open,
+  FFS_SKP_DELETED_3 => open,
+  FFS_RLOL_3 => rx_cdr_lol_ch3_sig,
+  FFS_RXFBFIFO_ERROR_3 => open,
+  FFS_TXFBFIFO_ERROR_3 => open,
+  LDR_CORE2TX_3 => fpsc_vlo,
+  FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
+  LDR_RX2CORE_3 => open,
+  FFS_CDR_TRAIN_DONE_3 => open,
+  FFC_DIV11_MODE_TX_3 => fpsc_vlo,
+  FFC_RATE_MODE_TX_3 => tx_div2_mode_ch3_c,
+  FFC_DIV11_MODE_RX_3 => fpsc_vlo,
+  FFC_RATE_MODE_RX_3 => rx_div2_mode_ch3_c,
+
+----- Auxilliary ----
+  SCIWDATA7 => sci_wrdata(7),
+  SCIWDATA6 => sci_wrdata(6),
+  SCIWDATA5 => sci_wrdata(5),
+  SCIWDATA4 => sci_wrdata(4),
+  SCIWDATA3 => sci_wrdata(3),
+  SCIWDATA2 => sci_wrdata(2),
+  SCIWDATA1 => sci_wrdata(1),
+  SCIWDATA0 => sci_wrdata(0),
+  SCIADDR5 => sci_addr(5),
+  SCIADDR4 => sci_addr(4),
+  SCIADDR3 => sci_addr(3),
+  SCIADDR2 => sci_addr(2),
+  SCIADDR1 => sci_addr(1),
+  SCIADDR0 => sci_addr(0),
+  SCIRDATA7 => sci_rddata(7),
+  SCIRDATA6 => sci_rddata(6),
+  SCIRDATA5 => sci_rddata(5),
+  SCIRDATA4 => sci_rddata(4),
+  SCIRDATA3 => sci_rddata(3),
+  SCIRDATA2 => sci_rddata(2),
+  SCIRDATA1 => sci_rddata(1),
+  SCIRDATA0 => sci_rddata(0),
+  SCIENAUX => fpsc_vhi,
+  SCISELAUX => sci_sel_quad,
+  SCIRD => sci_rd,
+  SCIWSTN => sci_wrn,
+  CYAWSTN => fpsc_vlo,
+  SCIINT => open,
+  FFC_CK_CORE_TX => fpga_txrefclk,
+  FFC_MACRO_RST => serdes_rst_qd_c,
+  FFC_QUAD_RST => rst_qd_c,
+  FFC_TRST => tx_serdes_rst_c,
+  FFS_PLOL => tx_pll_lol_qd_sig,
+  FFC_SYNC_TOGGLE => tx_sync_qd_c,
+  REFCK2CORE => refclk2fpga_sig,
+  CIN0 => fpsc_vlo,
+  CIN1 => fpsc_vlo,
+  CIN2 => fpsc_vlo,
+  CIN3 => fpsc_vlo,
+  CIN4 => fpsc_vlo,
+  CIN5 => fpsc_vlo,
+  CIN6 => fpsc_vlo,
+  CIN7 => fpsc_vlo,
+  CIN8 => fpsc_vlo,
+  CIN9 => fpsc_vlo,
+  CIN10 => fpsc_vlo,
+  CIN11 => fpsc_vlo,
+  COUT0 => open,
+  COUT1 => open,
+  COUT2 => open,
+  COUT3 => open,
+  COUT4 => open,
+  COUT5 => open,
+  COUT6 => open,
+  COUT7 => open,
+  COUT8 => open,
+  COUT9 => open,
+  COUT10 => open,
+  COUT11 => open,
+  COUT12 => open,
+  COUT13 => open,
+  COUT14 => open,
+  COUT15 => open,
+  COUT16 => open,
+  COUT17 => open,
+  COUT18 => open,
+  COUT19 => open,
+  REFCLK_FROM_NQ => refclk_from_nq,
+  REFCLK_TO_NQ => open);
+
+                                                                                              
+                                                                                              
+                                                                                              
+--synopsys translate_off
+file_read : PROCESS
+VARIABLE open_status : file_open_status;
+FILE config : text;
+BEGIN
+   file_open (open_status, config, USER_CONFIG_FILE, read_mode);
+   IF (open_status = name_error) THEN
+      report "Auto configuration file for PCS module not found.  PCS internal configuration registers will not be initialized correctly during simulation!"
+      severity ERROR;
+   END IF;
+   wait;
+END PROCESS;
+--synopsys translate_on
+end serdes_sync_200_full_arch ;
diff --git a/data_concentrator/sources/lattice/ecp3/sfp_1_2sync_3_200_int.ipx b/data_concentrator/sources/lattice/ecp3/sfp_1_2sync_3_200_int.ipx
new file mode 100644
index 0000000..805587b
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/sfp_1_2sync_3_200_int.ipx
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="sfp_1_2sync_3_200_int" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 12 02 16:27:17.402" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="sfp_1_2sync_3_200_int.lpc" type="lpc" modified="2014 12 02 16:27:11.236"/>
+		<File name="sfp_1_2sync_3_200_int.pp" type="pp" modified="2014 12 02 16:27:11.238"/>
+		<File name="sfp_1_2sync_3_200_int.sym" type="sym" modified="2014 12 02 16:27:11.491"/>
+		<File name="sfp_1_2sync_3_200_int.tft" type="tft" modified="2014 12 02 16:27:11.271"/>
+		<File name="sfp_1_2sync_3_200_int.txt" type="pcs_module" modified="2014 12 02 16:27:11.274"/>
+		<File name="sfp_1_2sync_3_200_int.vhd" type="top_level_vhdl" modified="2014 12 02 16:27:11.270"/>
+  </Package>
+</DiamondModule>
diff --git a/data_concentrator/sources/lattice/ecp3/sfp_1_2sync_3_200_int.lpc b/data_concentrator/sources/lattice/ecp3/sfp_1_2sync_3_200_int.lpc
new file mode 100644
index 0000000..2e081b6
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/sfp_1_2sync_3_200_int.lpc
@@ -0,0 +1,258 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PCS
+CoreRevision=8.2
+ModuleName=sfp_1_2sync_3_200_int
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=12/02/2014
+Time=16:27:11
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+_mode0=DISABLED
+_mode1=RXTX
+_mode2=RXTX
+_mode3=TXONLY
+_protocol0=G8B10B
+_protocol1=G8B10B
+_protocol2=G8B10B
+_protocol3=G8B10B
+_ldr0=DISABLED
+_ldr1=DISABLED
+_ldr2=DISABLED
+_ldr3=DISABLED
+_datarange=2
+_pll_txsrc=INTERNAL
+_refclk_mult=10X
+_refclk_rate=200
+_tx_protocol0=DISABLED
+_tx_protocol1=G8B10B
+_tx_protocol2=G8B10B
+_tx_protocol3=G8B10B
+_tx_data_rate0=FULL
+_tx_data_rate1=FULL
+_tx_data_rate2=FULL
+_tx_data_rate3=DIV2
+_tx_data_width0=8
+_tx_data_width1=16
+_tx_data_width2=8
+_tx_data_width3=8
+_tx_fifo0=ENABLED
+_tx_fifo1=ENABLED
+_tx_fifo2=DISABLED
+_tx_fifo3=ENABLED
+_tx_ficlk_rate0=200
+_tx_ficlk_rate1=100
+_tx_ficlk_rate2=200
+_tx_ficlk_rate3=100
+_pll_rxsrc0=EXTERNAL
+_pll_rxsrc1=INTERNAL
+_pll_rxsrc2=INTERNAL
+_pll_rxsrc3=EXTERNAL
+Multiplier0=
+Multiplier1=
+Multiplier2=
+Multiplier3=
+_rx_datarange0=2.5
+_rx_datarange1=2
+_rx_datarange2=2
+_rx_datarange3=2.5
+_rx_protocol0=DISABLED
+_rx_protocol1=G8B10B
+_rx_protocol2=G8B10B
+_rx_protocol3=DISABLED
+_rx_data_rate0=FULL
+_rx_data_rate1=FULL
+_rx_data_rate2=FULL
+_rx_data_rate3=FULL
+_rxrefclk_rate0=250.0
+_rxrefclk_rate1=200
+_rxrefclk_rate2=200
+_rxrefclk_rate3=250.0
+_rx_data_width0=8
+_rx_data_width1=16
+_rx_data_width2=8
+_rx_data_width3=8
+_rx_fifo0=ENABLED
+_rx_fifo1=ENABLED
+_rx_fifo2=ENABLED
+_rx_fifo3=DISABLED
+_rx_ficlk_rate0=250.0
+_rx_ficlk_rate1=100
+_rx_ficlk_rate2=200
+_rx_ficlk_rate3=250.0
+_tdrv_ch0=0
+_tdrv_ch1=0
+_tdrv_ch2=0
+_tdrv_ch3=0
+_tx_pre0=DISABLED
+_tx_pre1=DISABLED
+_tx_pre2=DISABLED
+_tx_pre3=DISABLED
+_rterm_tx0=50
+_rterm_tx1=50
+_rterm_tx2=50
+_rterm_tx3=50
+_rx_eq0=DISABLED
+_rx_eq1=DISABLED
+_rx_eq2=DISABLED
+_rx_eq3=DISABLED
+_rterm_rx0=50
+_rterm_rx1=50
+_rterm_rx2=50
+_rterm_rx3=50
+_rx_dcc0=AC
+_rx_dcc1=DC
+_rx_dcc2=DC
+_rx_dcc3=AC
+_los_threshold_mode0=LOS_E
+_los_threshold_mode1=LOS_E
+_los_threshold_mode2=LOS_E
+_los_threshold_mode3=LOS_E
+_los_threshold_lo0=2
+_los_threshold_lo1=2
+_los_threshold_lo2=2
+_los_threshold_lo3=2
+_los_threshold_hi0=7
+_los_threshold_hi1=7
+_los_threshold_hi2=7
+_los_threshold_hi3=7
+_pll_term=50
+_pll_dcc=AC
+_pll_lol_set=0
+_tx_sb0=DISABLED
+_tx_sb1=DISABLED
+_tx_sb2=DISABLED
+_tx_sb3=DISABLED
+_tx_8b10b0=ENABLED
+_tx_8b10b1=ENABLED
+_tx_8b10b2=ENABLED
+_tx_8b10b3=ENABLED
+_rx_sb0=DISABLED
+_rx_sb1=DISABLED
+_rx_sb2=DISABLED
+_rx_sb3=DISABLED
+_ird0=DISABLED
+_ird1=DISABLED
+_ird2=DISABLED
+_ird3=DISABLED
+_rx_8b10b0=ENABLED
+_rx_8b10b1=ENABLED
+_rx_8b10b2=ENABLED
+_rx_8b10b3=ENABLED
+_rxwa0=ENABLED
+_rxwa1=ENABLED
+_rxwa2=ENABLED
+_rxwa3=ENABLED
+_ilsm0=ENABLED
+_ilsm1=ENABLED
+_ilsm2=ENABLED
+_ilsm3=ENABLED
+_scomma0=K28P157
+_scomma1=K28P157
+_scomma2=K28P157
+_scomma3=K28P157
+_comma_a0=1100000101
+_comma_a1=1100000101
+_comma_a2=1100000101
+_comma_a3=1100000101
+_comma_b0=0011111010
+_comma_b1=0011111010
+_comma_b2=0011111010
+_comma_b3=0011111010
+_comma_m0=1111111100
+_comma_m1=1111111100
+_comma_m2=1111111100
+_comma_m3=1111111100
+_ctc0=DISABLED
+_ctc1=DISABLED
+_ctc2=DISABLED
+_ctc3=DISABLED
+_cc_match_mode0=1
+_cc_match_mode1=1
+_cc_match_mode2=1
+_cc_match_mode3=1
+_k00=00
+_k01=01
+_k02=01
+_k03=00
+_k10=00
+_k11=00
+_k12=00
+_k13=00
+_k20=01
+_k21=01
+_k22=01
+_k23=01
+_k30=01
+_k31=01
+_k32=01
+_k33=01
+_byten00=00000000
+_byten01=00011100
+_byten02=00011100
+_byten03=00000000
+_byten10=00000000
+_byten11=00000000
+_byten12=00000000
+_byten13=00000000
+_byten20=00011100
+_byten21=00011100
+_byten22=00011100
+_byten23=00011100
+_byten30=00011100
+_byten31=00011100
+_byten32=00011100
+_byten33=00011100
+_cc_min_ipg0=3
+_cc_min_ipg1=3
+_cc_min_ipg2=3
+_cc_min_ipg3=3
+_cchmark=9
+_cclmark=7
+_loopback=DISABLED
+_lbtype0=DISABLED
+_lbtype1=DISABLED
+_lbtype2=DISABLED
+_lbtype3=DISABLED
+_teidle_ch0=DISABLED
+_teidle_ch1=DISABLED
+_teidle_ch2=DISABLED
+_teidle_ch3=DISABLED
+_rst_gen=DISABLED
+_rx_los_port0=Internal
+_rx_los_port1=Internal
+_rx_los_port2=Internal
+_rx_los_port3=Internal
+_sci_ports=ENABLED
+_sci_int_port=DISABLED
+_refck2core=DISABLED
+Regen=auto
+PAR1=0
+PARTrace1=0
+PAR3=0
+PARTrace3=0
+
+[FilesGenerated]
+sfp_1_2sync_3_200_int.pp=pp
+sfp_1_2sync_3_200_int.tft=tft
+sfp_1_2sync_3_200_int.txt=pcs_module
+sfp_1_2sync_3_200_int.sym=sym
diff --git a/data_concentrator/sources/lattice/ecp3/sfp_1_2sync_3_200_int.vhd b/data_concentrator/sources/lattice/ecp3/sfp_1_2sync_3_200_int.vhd
new file mode 100644
index 0000000..0646069
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/sfp_1_2sync_3_200_int.vhd
@@ -0,0 +1,2753 @@
+
+                                                                                                         
+
+--synopsys translate_off
+
+library pcsd_work;
+use pcsd_work.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity PCSD is
+GENERIC(
+  CONFIG_FILE : String;
+  QUAD_MODE : String;
+  CH0_CDR_SRC   : String := "REFCLK_EXT";
+  CH1_CDR_SRC   : String := "REFCLK_EXT";
+  CH2_CDR_SRC   : String := "REFCLK_EXT";
+  CH3_CDR_SRC   : String := "REFCLK_EXT";
+  PLL_SRC   : String
+--  CONFIG_FILE : String  := "sfp_1_2sync_3_200_int.txt";
+--  QUAD_MODE : String := "SINGLE";
+--  CH0_CDR_SRC   : String := "REFCLK_EXT";
+--  CH1_CDR_SRC   : String := "REFCLK_CORE";
+--  CH2_CDR_SRC   : String := "REFCLK_CORE";
+--  CH3_CDR_SRC   : String := "REFCLK_EXT";
+--  PLL_SRC   : String := "REFCLK_CORE"
+  );
+port (
+  HDINN0             : in std_logic;
+  HDINN1             : in std_logic;
+  HDINN2             : in std_logic;
+  HDINN3             : in std_logic;
+  HDINP0             : in std_logic;
+  HDINP1             : in std_logic;
+  HDINP2             : in std_logic;
+  HDINP3             : in std_logic;
+  REFCLKN             : in std_logic;
+  REFCLKP             : in std_logic;
+  CIN0             : in std_logic;
+  CIN1             : in std_logic;
+  CIN2             : in std_logic;
+  CIN3             : in std_logic;
+  CIN4             : in std_logic;
+  CIN5             : in std_logic;
+  CIN6             : in std_logic;
+  CIN7             : in std_logic;
+  CIN8             : in std_logic;
+  CIN9             : in std_logic;
+  CIN10             : in std_logic;
+  CIN11             : in std_logic;
+  CYAWSTN             : in std_logic;
+  FF_EBRD_CLK_0             : in std_logic;
+  FF_EBRD_CLK_1             : in std_logic;
+  FF_EBRD_CLK_2             : in std_logic;
+  FF_EBRD_CLK_3             : in std_logic;
+  FF_RXI_CLK_0             : in std_logic;
+  FF_RXI_CLK_1             : in std_logic;
+  FF_RXI_CLK_2             : in std_logic;
+  FF_RXI_CLK_3             : in std_logic;
+  FF_TX_D_0_0             : in std_logic;
+  FF_TX_D_0_1             : in std_logic;
+  FF_TX_D_0_2             : in std_logic;
+  FF_TX_D_0_3             : in std_logic;
+  FF_TX_D_0_4             : in std_logic;
+  FF_TX_D_0_5             : in std_logic;
+  FF_TX_D_0_6             : in std_logic;
+  FF_TX_D_0_7             : in std_logic;
+  FF_TX_D_0_8             : in std_logic;
+  FF_TX_D_0_9             : in std_logic;
+  FF_TX_D_0_10             : in std_logic;
+  FF_TX_D_0_11             : in std_logic;
+  FF_TX_D_0_12             : in std_logic;
+  FF_TX_D_0_13             : in std_logic;
+  FF_TX_D_0_14             : in std_logic;
+  FF_TX_D_0_15             : in std_logic;
+  FF_TX_D_0_16             : in std_logic;
+  FF_TX_D_0_17             : in std_logic;
+  FF_TX_D_0_18             : in std_logic;
+  FF_TX_D_0_19             : in std_logic;
+  FF_TX_D_0_20             : in std_logic;
+  FF_TX_D_0_21             : in std_logic;
+  FF_TX_D_0_22             : in std_logic;
+  FF_TX_D_0_23             : in std_logic;
+  FF_TX_D_1_0             : in std_logic;
+  FF_TX_D_1_1             : in std_logic;
+  FF_TX_D_1_2             : in std_logic;
+  FF_TX_D_1_3             : in std_logic;
+  FF_TX_D_1_4             : in std_logic;
+  FF_TX_D_1_5             : in std_logic;
+  FF_TX_D_1_6             : in std_logic;
+  FF_TX_D_1_7             : in std_logic;
+  FF_TX_D_1_8             : in std_logic;
+  FF_TX_D_1_9             : in std_logic;
+  FF_TX_D_1_10             : in std_logic;
+  FF_TX_D_1_11             : in std_logic;
+  FF_TX_D_1_12             : in std_logic;
+  FF_TX_D_1_13             : in std_logic;
+  FF_TX_D_1_14             : in std_logic;
+  FF_TX_D_1_15             : in std_logic;
+  FF_TX_D_1_16             : in std_logic;
+  FF_TX_D_1_17             : in std_logic;
+  FF_TX_D_1_18             : in std_logic;
+  FF_TX_D_1_19             : in std_logic;
+  FF_TX_D_1_20             : in std_logic;
+  FF_TX_D_1_21             : in std_logic;
+  FF_TX_D_1_22             : in std_logic;
+  FF_TX_D_1_23             : in std_logic;
+  FF_TX_D_2_0             : in std_logic;
+  FF_TX_D_2_1             : in std_logic;
+  FF_TX_D_2_2             : in std_logic;
+  FF_TX_D_2_3             : in std_logic;
+  FF_TX_D_2_4             : in std_logic;
+  FF_TX_D_2_5             : in std_logic;
+  FF_TX_D_2_6             : in std_logic;
+  FF_TX_D_2_7             : in std_logic;
+  FF_TX_D_2_8             : in std_logic;
+  FF_TX_D_2_9             : in std_logic;
+  FF_TX_D_2_10             : in std_logic;
+  FF_TX_D_2_11             : in std_logic;
+  FF_TX_D_2_12             : in std_logic;
+  FF_TX_D_2_13             : in std_logic;
+  FF_TX_D_2_14             : in std_logic;
+  FF_TX_D_2_15             : in std_logic;
+  FF_TX_D_2_16             : in std_logic;
+  FF_TX_D_2_17             : in std_logic;
+  FF_TX_D_2_18             : in std_logic;
+  FF_TX_D_2_19             : in std_logic;
+  FF_TX_D_2_20             : in std_logic;
+  FF_TX_D_2_21             : in std_logic;
+  FF_TX_D_2_22             : in std_logic;
+  FF_TX_D_2_23             : in std_logic;
+  FF_TX_D_3_0             : in std_logic;
+  FF_TX_D_3_1             : in std_logic;
+  FF_TX_D_3_2             : in std_logic;
+  FF_TX_D_3_3             : in std_logic;
+  FF_TX_D_3_4             : in std_logic;
+  FF_TX_D_3_5             : in std_logic;
+  FF_TX_D_3_6             : in std_logic;
+  FF_TX_D_3_7             : in std_logic;
+  FF_TX_D_3_8             : in std_logic;
+  FF_TX_D_3_9             : in std_logic;
+  FF_TX_D_3_10             : in std_logic;
+  FF_TX_D_3_11             : in std_logic;
+  FF_TX_D_3_12             : in std_logic;
+  FF_TX_D_3_13             : in std_logic;
+  FF_TX_D_3_14             : in std_logic;
+  FF_TX_D_3_15             : in std_logic;
+  FF_TX_D_3_16             : in std_logic;
+  FF_TX_D_3_17             : in std_logic;
+  FF_TX_D_3_18             : in std_logic;
+  FF_TX_D_3_19             : in std_logic;
+  FF_TX_D_3_20             : in std_logic;
+  FF_TX_D_3_21             : in std_logic;
+  FF_TX_D_3_22             : in std_logic;
+  FF_TX_D_3_23             : in std_logic;
+  FF_TXI_CLK_0             : in std_logic;
+  FF_TXI_CLK_1             : in std_logic;
+  FF_TXI_CLK_2             : in std_logic;
+  FF_TXI_CLK_3             : in std_logic;
+  FFC_CK_CORE_RX_0         : in std_logic;
+  FFC_CK_CORE_RX_1         : in std_logic;
+  FFC_CK_CORE_RX_2         : in std_logic;
+  FFC_CK_CORE_RX_3         : in std_logic;
+  FFC_CK_CORE_TX           : in std_logic;
+  FFC_EI_EN_0             : in std_logic;
+  FFC_EI_EN_1             : in std_logic;
+  FFC_EI_EN_2             : in std_logic;
+  FFC_EI_EN_3             : in std_logic;
+  FFC_ENABLE_CGALIGN_0             : in std_logic;
+  FFC_ENABLE_CGALIGN_1             : in std_logic;
+  FFC_ENABLE_CGALIGN_2             : in std_logic;
+  FFC_ENABLE_CGALIGN_3             : in std_logic;
+  FFC_FB_LOOPBACK_0             : in std_logic;
+  FFC_FB_LOOPBACK_1             : in std_logic;
+  FFC_FB_LOOPBACK_2             : in std_logic;
+  FFC_FB_LOOPBACK_3             : in std_logic;
+  FFC_LANE_RX_RST_0             : in std_logic;
+  FFC_LANE_RX_RST_1             : in std_logic;
+  FFC_LANE_RX_RST_2             : in std_logic;
+  FFC_LANE_RX_RST_3             : in std_logic;
+  FFC_LANE_TX_RST_0             : in std_logic;
+  FFC_LANE_TX_RST_1             : in std_logic;
+  FFC_LANE_TX_RST_2             : in std_logic;
+  FFC_LANE_TX_RST_3             : in std_logic;
+  FFC_MACRO_RST             : in std_logic;
+  FFC_PCI_DET_EN_0             : in std_logic;
+  FFC_PCI_DET_EN_1             : in std_logic;
+  FFC_PCI_DET_EN_2             : in std_logic;
+  FFC_PCI_DET_EN_3             : in std_logic;
+  FFC_PCIE_CT_0             : in std_logic;
+  FFC_PCIE_CT_1             : in std_logic;
+  FFC_PCIE_CT_2             : in std_logic;
+  FFC_PCIE_CT_3             : in std_logic;
+  FFC_PFIFO_CLR_0             : in std_logic;
+  FFC_PFIFO_CLR_1             : in std_logic;
+  FFC_PFIFO_CLR_2             : in std_logic;
+  FFC_PFIFO_CLR_3             : in std_logic;
+  FFC_QUAD_RST             : in std_logic;
+  FFC_RRST_0             : in std_logic;
+  FFC_RRST_1             : in std_logic;
+  FFC_RRST_2             : in std_logic;
+  FFC_RRST_3             : in std_logic;
+  FFC_RXPWDNB_0             : in std_logic;
+  FFC_RXPWDNB_1             : in std_logic;
+  FFC_RXPWDNB_2             : in std_logic;
+  FFC_RXPWDNB_3             : in std_logic;
+  FFC_SB_INV_RX_0             : in std_logic;
+  FFC_SB_INV_RX_1             : in std_logic;
+  FFC_SB_INV_RX_2             : in std_logic;
+  FFC_SB_INV_RX_3             : in std_logic;
+  FFC_SB_PFIFO_LP_0             : in std_logic;
+  FFC_SB_PFIFO_LP_1             : in std_logic;
+  FFC_SB_PFIFO_LP_2             : in std_logic;
+  FFC_SB_PFIFO_LP_3             : in std_logic;
+  FFC_SIGNAL_DETECT_0             : in std_logic;
+  FFC_SIGNAL_DETECT_1             : in std_logic;
+  FFC_SIGNAL_DETECT_2             : in std_logic;
+  FFC_SIGNAL_DETECT_3             : in std_logic;
+  FFC_SYNC_TOGGLE             : in std_logic;
+  FFC_TRST             : in std_logic;
+  FFC_TXPWDNB_0             : in std_logic;
+  FFC_TXPWDNB_1             : in std_logic;
+  FFC_TXPWDNB_2             : in std_logic;
+  FFC_TXPWDNB_3             : in std_logic;
+  FFC_RATE_MODE_RX_0        : in std_logic;
+  FFC_RATE_MODE_RX_1        : in std_logic;
+  FFC_RATE_MODE_RX_2        : in std_logic;
+  FFC_RATE_MODE_RX_3        : in std_logic;
+  FFC_RATE_MODE_TX_0        : in std_logic;
+  FFC_RATE_MODE_TX_1        : in std_logic;
+  FFC_RATE_MODE_TX_2        : in std_logic;
+  FFC_RATE_MODE_TX_3        : in std_logic;
+  FFC_DIV11_MODE_RX_0       : in std_logic;
+  FFC_DIV11_MODE_RX_1       : in std_logic;
+  FFC_DIV11_MODE_RX_2       : in std_logic;
+  FFC_DIV11_MODE_RX_3       : in std_logic;
+  FFC_DIV11_MODE_TX_0       : in std_logic;
+  FFC_DIV11_MODE_TX_1       : in std_logic;
+  FFC_DIV11_MODE_TX_2       : in std_logic;
+  FFC_DIV11_MODE_TX_3       : in std_logic;
+  LDR_CORE2TX_0             : in std_logic;
+  LDR_CORE2TX_1             : in std_logic;
+  LDR_CORE2TX_2             : in std_logic;
+  LDR_CORE2TX_3             : in std_logic;
+  FFC_LDR_CORE2TX_EN_0      : in std_logic;
+  FFC_LDR_CORE2TX_EN_1      : in std_logic;
+  FFC_LDR_CORE2TX_EN_2      : in std_logic;
+  FFC_LDR_CORE2TX_EN_3      : in std_logic;
+  PCIE_POWERDOWN_0_0      : in std_logic;
+  PCIE_POWERDOWN_0_1      : in std_logic;
+  PCIE_POWERDOWN_1_0      : in std_logic;
+  PCIE_POWERDOWN_1_1      : in std_logic;
+  PCIE_POWERDOWN_2_0      : in std_logic;
+  PCIE_POWERDOWN_2_1      : in std_logic;
+  PCIE_POWERDOWN_3_0      : in std_logic;
+  PCIE_POWERDOWN_3_1      : in std_logic;
+  PCIE_RXPOLARITY_0         : in std_logic;
+  PCIE_RXPOLARITY_1         : in std_logic;
+  PCIE_RXPOLARITY_2         : in std_logic;
+  PCIE_RXPOLARITY_3         : in std_logic;
+  PCIE_TXCOMPLIANCE_0       : in std_logic;
+  PCIE_TXCOMPLIANCE_1       : in std_logic;
+  PCIE_TXCOMPLIANCE_2       : in std_logic;
+  PCIE_TXCOMPLIANCE_3       : in std_logic;
+  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
+  SCIADDR0             : in std_logic;
+  SCIADDR1             : in std_logic;
+  SCIADDR2             : in std_logic;
+  SCIADDR3             : in std_logic;
+  SCIADDR4             : in std_logic;
+  SCIADDR5             : in std_logic;
+  SCIENAUX             : in std_logic;
+  SCIENCH0             : in std_logic;
+  SCIENCH1             : in std_logic;
+  SCIENCH2             : in std_logic;
+  SCIENCH3             : in std_logic;
+  SCIRD                : in std_logic;
+  SCISELAUX             : in std_logic;
+  SCISELCH0             : in std_logic;
+  SCISELCH1             : in std_logic;
+  SCISELCH2             : in std_logic;
+  SCISELCH3             : in std_logic;
+  SCIWDATA0             : in std_logic;
+  SCIWDATA1             : in std_logic;
+  SCIWDATA2             : in std_logic;
+  SCIWDATA3             : in std_logic;
+  SCIWDATA4             : in std_logic;
+  SCIWDATA5             : in std_logic;
+  SCIWDATA6             : in std_logic;
+  SCIWDATA7             : in std_logic;
+  SCIWSTN               : in std_logic;
+  REFCLK_FROM_NQ        : in std_logic;
+
+  HDOUTN0             : out std_logic;
+  HDOUTN1             : out std_logic;
+  HDOUTN2             : out std_logic;
+  HDOUTN3             : out std_logic;
+  HDOUTP0             : out std_logic;
+  HDOUTP1             : out std_logic;
+  HDOUTP2             : out std_logic;
+  HDOUTP3             : out std_logic;
+  COUT0             : out std_logic;
+  COUT1             : out std_logic;
+  COUT2             : out std_logic;
+  COUT3             : out std_logic;
+  COUT4             : out std_logic;
+  COUT5             : out std_logic;
+  COUT6             : out std_logic;
+  COUT7             : out std_logic;
+  COUT8             : out std_logic;
+  COUT9             : out std_logic;
+  COUT10             : out std_logic;
+  COUT11             : out std_logic;
+  COUT12             : out std_logic;
+  COUT13             : out std_logic;
+  COUT14             : out std_logic;
+  COUT15             : out std_logic;
+  COUT16             : out std_logic;
+  COUT17             : out std_logic;
+  COUT18             : out std_logic;
+  COUT19             : out std_logic;
+  FF_RX_D_0_0             : out std_logic;
+  FF_RX_D_0_1             : out std_logic;
+  FF_RX_D_0_2             : out std_logic;
+  FF_RX_D_0_3             : out std_logic;
+  FF_RX_D_0_4             : out std_logic;
+  FF_RX_D_0_5             : out std_logic;
+  FF_RX_D_0_6             : out std_logic;
+  FF_RX_D_0_7             : out std_logic;
+  FF_RX_D_0_8             : out std_logic;
+  FF_RX_D_0_9             : out std_logic;
+  FF_RX_D_0_10             : out std_logic;
+  FF_RX_D_0_11             : out std_logic;
+  FF_RX_D_0_12             : out std_logic;
+  FF_RX_D_0_13             : out std_logic;
+  FF_RX_D_0_14             : out std_logic;
+  FF_RX_D_0_15             : out std_logic;
+  FF_RX_D_0_16             : out std_logic;
+  FF_RX_D_0_17             : out std_logic;
+  FF_RX_D_0_18             : out std_logic;
+  FF_RX_D_0_19             : out std_logic;
+  FF_RX_D_0_20             : out std_logic;
+  FF_RX_D_0_21             : out std_logic;
+  FF_RX_D_0_22             : out std_logic;
+  FF_RX_D_0_23             : out std_logic;
+  FF_RX_D_1_0             : out std_logic;
+  FF_RX_D_1_1             : out std_logic;
+  FF_RX_D_1_2             : out std_logic;
+  FF_RX_D_1_3             : out std_logic;
+  FF_RX_D_1_4             : out std_logic;
+  FF_RX_D_1_5             : out std_logic;
+  FF_RX_D_1_6             : out std_logic;
+  FF_RX_D_1_7             : out std_logic;
+  FF_RX_D_1_8             : out std_logic;
+  FF_RX_D_1_9             : out std_logic;
+  FF_RX_D_1_10             : out std_logic;
+  FF_RX_D_1_11             : out std_logic;
+  FF_RX_D_1_12             : out std_logic;
+  FF_RX_D_1_13             : out std_logic;
+  FF_RX_D_1_14             : out std_logic;
+  FF_RX_D_1_15             : out std_logic;
+  FF_RX_D_1_16             : out std_logic;
+  FF_RX_D_1_17             : out std_logic;
+  FF_RX_D_1_18             : out std_logic;
+  FF_RX_D_1_19             : out std_logic;
+  FF_RX_D_1_20             : out std_logic;
+  FF_RX_D_1_21             : out std_logic;
+  FF_RX_D_1_22             : out std_logic;
+  FF_RX_D_1_23             : out std_logic;
+  FF_RX_D_2_0             : out std_logic;
+  FF_RX_D_2_1             : out std_logic;
+  FF_RX_D_2_2             : out std_logic;
+  FF_RX_D_2_3             : out std_logic;
+  FF_RX_D_2_4             : out std_logic;
+  FF_RX_D_2_5             : out std_logic;
+  FF_RX_D_2_6             : out std_logic;
+  FF_RX_D_2_7             : out std_logic;
+  FF_RX_D_2_8             : out std_logic;
+  FF_RX_D_2_9             : out std_logic;
+  FF_RX_D_2_10             : out std_logic;
+  FF_RX_D_2_11             : out std_logic;
+  FF_RX_D_2_12             : out std_logic;
+  FF_RX_D_2_13             : out std_logic;
+  FF_RX_D_2_14             : out std_logic;
+  FF_RX_D_2_15             : out std_logic;
+  FF_RX_D_2_16             : out std_logic;
+  FF_RX_D_2_17             : out std_logic;
+  FF_RX_D_2_18             : out std_logic;
+  FF_RX_D_2_19             : out std_logic;
+  FF_RX_D_2_20             : out std_logic;
+  FF_RX_D_2_21             : out std_logic;
+  FF_RX_D_2_22             : out std_logic;
+  FF_RX_D_2_23             : out std_logic;
+  FF_RX_D_3_0             : out std_logic;
+  FF_RX_D_3_1             : out std_logic;
+  FF_RX_D_3_2             : out std_logic;
+  FF_RX_D_3_3             : out std_logic;
+  FF_RX_D_3_4             : out std_logic;
+  FF_RX_D_3_5             : out std_logic;
+  FF_RX_D_3_6             : out std_logic;
+  FF_RX_D_3_7             : out std_logic;
+  FF_RX_D_3_8             : out std_logic;
+  FF_RX_D_3_9             : out std_logic;
+  FF_RX_D_3_10             : out std_logic;
+  FF_RX_D_3_11             : out std_logic;
+  FF_RX_D_3_12             : out std_logic;
+  FF_RX_D_3_13             : out std_logic;
+  FF_RX_D_3_14             : out std_logic;
+  FF_RX_D_3_15             : out std_logic;
+  FF_RX_D_3_16             : out std_logic;
+  FF_RX_D_3_17             : out std_logic;
+  FF_RX_D_3_18             : out std_logic;
+  FF_RX_D_3_19             : out std_logic;
+  FF_RX_D_3_20             : out std_logic;
+  FF_RX_D_3_21             : out std_logic;
+  FF_RX_D_3_22             : out std_logic;
+  FF_RX_D_3_23             : out std_logic;
+  FF_RX_F_CLK_0             : out std_logic;
+  FF_RX_F_CLK_1             : out std_logic;
+  FF_RX_F_CLK_2             : out std_logic;
+  FF_RX_F_CLK_3             : out std_logic;
+  FF_RX_H_CLK_0             : out std_logic;
+  FF_RX_H_CLK_1             : out std_logic;
+  FF_RX_H_CLK_2             : out std_logic;
+  FF_RX_H_CLK_3             : out std_logic;
+  FF_TX_F_CLK_0             : out std_logic;
+  FF_TX_F_CLK_1             : out std_logic;
+  FF_TX_F_CLK_2             : out std_logic;
+  FF_TX_F_CLK_3             : out std_logic;
+  FF_TX_H_CLK_0             : out std_logic;
+  FF_TX_H_CLK_1             : out std_logic;
+  FF_TX_H_CLK_2             : out std_logic;
+  FF_TX_H_CLK_3             : out std_logic;
+  FFS_CC_OVERRUN_0             : out std_logic;
+  FFS_CC_OVERRUN_1             : out std_logic;
+  FFS_CC_OVERRUN_2             : out std_logic;
+  FFS_CC_OVERRUN_3             : out std_logic;
+  FFS_CC_UNDERRUN_0             : out std_logic;
+  FFS_CC_UNDERRUN_1             : out std_logic;
+  FFS_CC_UNDERRUN_2             : out std_logic;
+  FFS_CC_UNDERRUN_3             : out std_logic;
+  FFS_LS_SYNC_STATUS_0             : out std_logic;
+  FFS_LS_SYNC_STATUS_1             : out std_logic;
+  FFS_LS_SYNC_STATUS_2             : out std_logic;
+  FFS_LS_SYNC_STATUS_3             : out std_logic;
+  FFS_CDR_TRAIN_DONE_0             : out std_logic;
+  FFS_CDR_TRAIN_DONE_1             : out std_logic;
+  FFS_CDR_TRAIN_DONE_2             : out std_logic;
+  FFS_CDR_TRAIN_DONE_3             : out std_logic;
+  FFS_PCIE_CON_0             : out std_logic;
+  FFS_PCIE_CON_1             : out std_logic;
+  FFS_PCIE_CON_2             : out std_logic;
+  FFS_PCIE_CON_3             : out std_logic;
+  FFS_PCIE_DONE_0             : out std_logic;
+  FFS_PCIE_DONE_1             : out std_logic;
+  FFS_PCIE_DONE_2             : out std_logic;
+  FFS_PCIE_DONE_3             : out std_logic;
+  FFS_PLOL             : out std_logic;
+  FFS_RLOL_0             : out std_logic;
+  FFS_RLOL_1             : out std_logic;
+  FFS_RLOL_2             : out std_logic;
+  FFS_RLOL_3             : out std_logic;
+  FFS_RLOS_HI_0             : out std_logic;
+  FFS_RLOS_HI_1             : out std_logic;
+  FFS_RLOS_HI_2             : out std_logic;
+  FFS_RLOS_HI_3             : out std_logic;
+  FFS_RLOS_LO_0             : out std_logic;
+  FFS_RLOS_LO_1             : out std_logic;
+  FFS_RLOS_LO_2             : out std_logic;
+  FFS_RLOS_LO_3             : out std_logic;
+  FFS_RXFBFIFO_ERROR_0             : out std_logic;
+  FFS_RXFBFIFO_ERROR_1             : out std_logic;
+  FFS_RXFBFIFO_ERROR_2             : out std_logic;
+  FFS_RXFBFIFO_ERROR_3             : out std_logic;
+  FFS_TXFBFIFO_ERROR_0             : out std_logic;
+  FFS_TXFBFIFO_ERROR_1             : out std_logic;
+  FFS_TXFBFIFO_ERROR_2             : out std_logic;
+  FFS_TXFBFIFO_ERROR_3             : out std_logic;
+  PCIE_PHYSTATUS_0             : out std_logic;
+  PCIE_PHYSTATUS_1             : out std_logic;
+  PCIE_PHYSTATUS_2             : out std_logic;
+  PCIE_PHYSTATUS_3             : out std_logic;
+  PCIE_RXVALID_0               : out std_logic;
+  PCIE_RXVALID_1               : out std_logic;
+  PCIE_RXVALID_2               : out std_logic;
+  PCIE_RXVALID_3               : out std_logic;
+  FFS_SKP_ADDED_0                  : out std_logic;
+  FFS_SKP_ADDED_1                  : out std_logic;
+  FFS_SKP_ADDED_2                  : out std_logic;
+  FFS_SKP_ADDED_3                  : out std_logic;
+  FFS_SKP_DELETED_0                : out std_logic;
+  FFS_SKP_DELETED_1                : out std_logic;
+  FFS_SKP_DELETED_2                : out std_logic;
+  FFS_SKP_DELETED_3                : out std_logic;
+  LDR_RX2CORE_0                    : out std_logic;
+  LDR_RX2CORE_1                    : out std_logic;
+  LDR_RX2CORE_2                    : out std_logic;
+  LDR_RX2CORE_3                    : out std_logic;
+  REFCK2CORE             : out std_logic;
+  SCIINT                : out std_logic;
+  SCIRDATA0             : out std_logic;
+  SCIRDATA1             : out std_logic;
+  SCIRDATA2             : out std_logic;
+  SCIRDATA3             : out std_logic;
+  SCIRDATA4             : out std_logic;
+  SCIRDATA5             : out std_logic;
+  SCIRDATA6             : out std_logic;
+  SCIRDATA7             : out std_logic;
+  REFCLK_TO_NQ          : out std_logic
+);
+
+end PCSD;
+
+architecture PCSD_arch of PCSD is
+
+
+component PCSD_sim
+GENERIC(
+  CONFIG_FILE : String;
+  QUAD_MODE : String;
+  CH0_CDR_SRC   : String;
+  CH1_CDR_SRC   : String;
+  CH2_CDR_SRC   : String;
+  CH3_CDR_SRC   : String;
+  PLL_SRC   : String
+  );
+port (
+  HDINN0             : in std_logic;
+  HDINN1             : in std_logic;
+  HDINN2             : in std_logic;
+  HDINN3             : in std_logic;
+  HDINP0             : in std_logic;
+  HDINP1             : in std_logic;
+  HDINP2             : in std_logic;
+  HDINP3             : in std_logic;
+  REFCLKN             : in std_logic;
+  REFCLKP             : in std_logic;
+  CIN0             : in std_logic;
+  CIN1             : in std_logic;
+  CIN2             : in std_logic;
+  CIN3             : in std_logic;
+  CIN4             : in std_logic;
+  CIN5             : in std_logic;
+  CIN6             : in std_logic;
+  CIN7             : in std_logic;
+  CIN8             : in std_logic;
+  CIN9             : in std_logic;
+  CIN10             : in std_logic;
+  CIN11             : in std_logic;
+  CYAWSTN             : in std_logic;
+  FF_EBRD_CLK_0             : in std_logic;
+  FF_EBRD_CLK_1             : in std_logic;
+  FF_EBRD_CLK_2             : in std_logic;
+  FF_EBRD_CLK_3             : in std_logic;
+  FF_RXI_CLK_0             : in std_logic;
+  FF_RXI_CLK_1             : in std_logic;
+  FF_RXI_CLK_2             : in std_logic;
+  FF_RXI_CLK_3             : in std_logic;
+  FF_TX_D_0_0             : in std_logic;
+  FF_TX_D_0_1             : in std_logic;
+  FF_TX_D_0_2             : in std_logic;
+  FF_TX_D_0_3             : in std_logic;
+  FF_TX_D_0_4             : in std_logic;
+  FF_TX_D_0_5             : in std_logic;
+  FF_TX_D_0_6             : in std_logic;
+  FF_TX_D_0_7             : in std_logic;
+  FF_TX_D_0_8             : in std_logic;
+  FF_TX_D_0_9             : in std_logic;
+  FF_TX_D_0_10             : in std_logic;
+  FF_TX_D_0_11             : in std_logic;
+  FF_TX_D_0_12             : in std_logic;
+  FF_TX_D_0_13             : in std_logic;
+  FF_TX_D_0_14             : in std_logic;
+  FF_TX_D_0_15             : in std_logic;
+  FF_TX_D_0_16             : in std_logic;
+  FF_TX_D_0_17             : in std_logic;
+  FF_TX_D_0_18             : in std_logic;
+  FF_TX_D_0_19             : in std_logic;
+  FF_TX_D_0_20             : in std_logic;
+  FF_TX_D_0_21             : in std_logic;
+  FF_TX_D_0_22             : in std_logic;
+  FF_TX_D_0_23             : in std_logic;
+  FF_TX_D_1_0             : in std_logic;
+  FF_TX_D_1_1             : in std_logic;
+  FF_TX_D_1_2             : in std_logic;
+  FF_TX_D_1_3             : in std_logic;
+  FF_TX_D_1_4             : in std_logic;
+  FF_TX_D_1_5             : in std_logic;
+  FF_TX_D_1_6             : in std_logic;
+  FF_TX_D_1_7             : in std_logic;
+  FF_TX_D_1_8             : in std_logic;
+  FF_TX_D_1_9             : in std_logic;
+  FF_TX_D_1_10             : in std_logic;
+  FF_TX_D_1_11             : in std_logic;
+  FF_TX_D_1_12             : in std_logic;
+  FF_TX_D_1_13             : in std_logic;
+  FF_TX_D_1_14             : in std_logic;
+  FF_TX_D_1_15             : in std_logic;
+  FF_TX_D_1_16             : in std_logic;
+  FF_TX_D_1_17             : in std_logic;
+  FF_TX_D_1_18             : in std_logic;
+  FF_TX_D_1_19             : in std_logic;
+  FF_TX_D_1_20             : in std_logic;
+  FF_TX_D_1_21             : in std_logic;
+  FF_TX_D_1_22             : in std_logic;
+  FF_TX_D_1_23             : in std_logic;
+  FF_TX_D_2_0             : in std_logic;
+  FF_TX_D_2_1             : in std_logic;
+  FF_TX_D_2_2             : in std_logic;
+  FF_TX_D_2_3             : in std_logic;
+  FF_TX_D_2_4             : in std_logic;
+  FF_TX_D_2_5             : in std_logic;
+  FF_TX_D_2_6             : in std_logic;
+  FF_TX_D_2_7             : in std_logic;
+  FF_TX_D_2_8             : in std_logic;
+  FF_TX_D_2_9             : in std_logic;
+  FF_TX_D_2_10             : in std_logic;
+  FF_TX_D_2_11             : in std_logic;
+  FF_TX_D_2_12             : in std_logic;
+  FF_TX_D_2_13             : in std_logic;
+  FF_TX_D_2_14             : in std_logic;
+  FF_TX_D_2_15             : in std_logic;
+  FF_TX_D_2_16             : in std_logic;
+  FF_TX_D_2_17             : in std_logic;
+  FF_TX_D_2_18             : in std_logic;
+  FF_TX_D_2_19             : in std_logic;
+  FF_TX_D_2_20             : in std_logic;
+  FF_TX_D_2_21             : in std_logic;
+  FF_TX_D_2_22             : in std_logic;
+  FF_TX_D_2_23             : in std_logic;
+  FF_TX_D_3_0             : in std_logic;
+  FF_TX_D_3_1             : in std_logic;
+  FF_TX_D_3_2             : in std_logic;
+  FF_TX_D_3_3             : in std_logic;
+  FF_TX_D_3_4             : in std_logic;
+  FF_TX_D_3_5             : in std_logic;
+  FF_TX_D_3_6             : in std_logic;
+  FF_TX_D_3_7             : in std_logic;
+  FF_TX_D_3_8             : in std_logic;
+  FF_TX_D_3_9             : in std_logic;
+  FF_TX_D_3_10             : in std_logic;
+  FF_TX_D_3_11             : in std_logic;
+  FF_TX_D_3_12             : in std_logic;
+  FF_TX_D_3_13             : in std_logic;
+  FF_TX_D_3_14             : in std_logic;
+  FF_TX_D_3_15             : in std_logic;
+  FF_TX_D_3_16             : in std_logic;
+  FF_TX_D_3_17             : in std_logic;
+  FF_TX_D_3_18             : in std_logic;
+  FF_TX_D_3_19             : in std_logic;
+  FF_TX_D_3_20             : in std_logic;
+  FF_TX_D_3_21             : in std_logic;
+  FF_TX_D_3_22             : in std_logic;
+  FF_TX_D_3_23             : in std_logic;
+  FF_TXI_CLK_0             : in std_logic;
+  FF_TXI_CLK_1             : in std_logic;
+  FF_TXI_CLK_2             : in std_logic;
+  FF_TXI_CLK_3             : in std_logic;
+  FFC_CK_CORE_RX_0         : in std_logic;
+  FFC_CK_CORE_RX_1         : in std_logic;
+  FFC_CK_CORE_RX_2         : in std_logic;
+  FFC_CK_CORE_RX_3         : in std_logic;
+  FFC_CK_CORE_TX           : in std_logic;
+  FFC_EI_EN_0             : in std_logic;
+  FFC_EI_EN_1             : in std_logic;
+  FFC_EI_EN_2             : in std_logic;
+  FFC_EI_EN_3             : in std_logic;
+  FFC_ENABLE_CGALIGN_0             : in std_logic;
+  FFC_ENABLE_CGALIGN_1             : in std_logic;
+  FFC_ENABLE_CGALIGN_2             : in std_logic;
+  FFC_ENABLE_CGALIGN_3             : in std_logic;
+  FFC_FB_LOOPBACK_0             : in std_logic;
+  FFC_FB_LOOPBACK_1             : in std_logic;
+  FFC_FB_LOOPBACK_2             : in std_logic;
+  FFC_FB_LOOPBACK_3             : in std_logic;
+  FFC_LANE_RX_RST_0             : in std_logic;
+  FFC_LANE_RX_RST_1             : in std_logic;
+  FFC_LANE_RX_RST_2             : in std_logic;
+  FFC_LANE_RX_RST_3             : in std_logic;
+  FFC_LANE_TX_RST_0             : in std_logic;
+  FFC_LANE_TX_RST_1             : in std_logic;
+  FFC_LANE_TX_RST_2             : in std_logic;
+  FFC_LANE_TX_RST_3             : in std_logic;
+  FFC_MACRO_RST             : in std_logic;
+  FFC_PCI_DET_EN_0             : in std_logic;
+  FFC_PCI_DET_EN_1             : in std_logic;
+  FFC_PCI_DET_EN_2             : in std_logic;
+  FFC_PCI_DET_EN_3             : in std_logic;
+  FFC_PCIE_CT_0             : in std_logic;
+  FFC_PCIE_CT_1             : in std_logic;
+  FFC_PCIE_CT_2             : in std_logic;
+  FFC_PCIE_CT_3             : in std_logic;
+  FFC_PFIFO_CLR_0             : in std_logic;
+  FFC_PFIFO_CLR_1             : in std_logic;
+  FFC_PFIFO_CLR_2             : in std_logic;
+  FFC_PFIFO_CLR_3             : in std_logic;
+  FFC_QUAD_RST             : in std_logic;
+  FFC_RRST_0             : in std_logic;
+  FFC_RRST_1             : in std_logic;
+  FFC_RRST_2             : in std_logic;
+  FFC_RRST_3             : in std_logic;
+  FFC_RXPWDNB_0             : in std_logic;
+  FFC_RXPWDNB_1             : in std_logic;
+  FFC_RXPWDNB_2             : in std_logic;
+  FFC_RXPWDNB_3             : in std_logic;
+  FFC_SB_INV_RX_0             : in std_logic;
+  FFC_SB_INV_RX_1             : in std_logic;
+  FFC_SB_INV_RX_2             : in std_logic;
+  FFC_SB_INV_RX_3             : in std_logic;
+  FFC_SB_PFIFO_LP_0             : in std_logic;
+  FFC_SB_PFIFO_LP_1             : in std_logic;
+  FFC_SB_PFIFO_LP_2             : in std_logic;
+  FFC_SB_PFIFO_LP_3             : in std_logic;
+  FFC_SIGNAL_DETECT_0             : in std_logic;
+  FFC_SIGNAL_DETECT_1             : in std_logic;
+  FFC_SIGNAL_DETECT_2             : in std_logic;
+  FFC_SIGNAL_DETECT_3             : in std_logic;
+  FFC_SYNC_TOGGLE             : in std_logic;
+  FFC_TRST             : in std_logic;
+  FFC_TXPWDNB_0             : in std_logic;
+  FFC_TXPWDNB_1             : in std_logic;
+  FFC_TXPWDNB_2             : in std_logic;
+  FFC_TXPWDNB_3             : in std_logic;
+  FFC_RATE_MODE_RX_0        : in std_logic;
+  FFC_RATE_MODE_RX_1        : in std_logic;
+  FFC_RATE_MODE_RX_2        : in std_logic;
+  FFC_RATE_MODE_RX_3        : in std_logic;
+  FFC_RATE_MODE_TX_0        : in std_logic;
+  FFC_RATE_MODE_TX_1        : in std_logic;
+  FFC_RATE_MODE_TX_2        : in std_logic;
+  FFC_RATE_MODE_TX_3        : in std_logic;
+  FFC_DIV11_MODE_RX_0       : in std_logic;
+  FFC_DIV11_MODE_RX_1       : in std_logic;
+  FFC_DIV11_MODE_RX_2       : in std_logic;
+  FFC_DIV11_MODE_RX_3       : in std_logic;
+  FFC_DIV11_MODE_TX_0       : in std_logic;
+  FFC_DIV11_MODE_TX_1       : in std_logic;
+  FFC_DIV11_MODE_TX_2       : in std_logic;
+  FFC_DIV11_MODE_TX_3       : in std_logic;
+  LDR_CORE2TX_0             : in std_logic;
+  LDR_CORE2TX_1             : in std_logic;
+  LDR_CORE2TX_2             : in std_logic;
+  LDR_CORE2TX_3             : in std_logic;
+  FFC_LDR_CORE2TX_EN_0      : in std_logic;
+  FFC_LDR_CORE2TX_EN_1      : in std_logic;
+  FFC_LDR_CORE2TX_EN_2      : in std_logic;
+  FFC_LDR_CORE2TX_EN_3      : in std_logic;
+  PCIE_POWERDOWN_0_0      : in std_logic;
+  PCIE_POWERDOWN_0_1      : in std_logic;
+  PCIE_POWERDOWN_1_0      : in std_logic;
+  PCIE_POWERDOWN_1_1      : in std_logic;
+  PCIE_POWERDOWN_2_0      : in std_logic;
+  PCIE_POWERDOWN_2_1      : in std_logic;
+  PCIE_POWERDOWN_3_0      : in std_logic;
+  PCIE_POWERDOWN_3_1      : in std_logic;
+  PCIE_RXPOLARITY_0         : in std_logic;
+  PCIE_RXPOLARITY_1         : in std_logic;
+  PCIE_RXPOLARITY_2         : in std_logic;
+  PCIE_RXPOLARITY_3         : in std_logic;
+  PCIE_TXCOMPLIANCE_0       : in std_logic;
+  PCIE_TXCOMPLIANCE_1       : in std_logic;
+  PCIE_TXCOMPLIANCE_2       : in std_logic;
+  PCIE_TXCOMPLIANCE_3       : in std_logic;
+  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
+  SCIADDR0             : in std_logic;
+  SCIADDR1             : in std_logic;
+  SCIADDR2             : in std_logic;
+  SCIADDR3             : in std_logic;
+  SCIADDR4             : in std_logic;
+  SCIADDR5             : in std_logic;
+  SCIENAUX             : in std_logic;
+  SCIENCH0             : in std_logic;
+  SCIENCH1             : in std_logic;
+  SCIENCH2             : in std_logic;
+  SCIENCH3             : in std_logic;
+  SCIRD                : in std_logic;
+  SCISELAUX             : in std_logic;
+  SCISELCH0             : in std_logic;
+  SCISELCH1             : in std_logic;
+  SCISELCH2             : in std_logic;
+  SCISELCH3             : in std_logic;
+  SCIWDATA0             : in std_logic;
+  SCIWDATA1             : in std_logic;
+  SCIWDATA2             : in std_logic;
+  SCIWDATA3             : in std_logic;
+  SCIWDATA4             : in std_logic;
+  SCIWDATA5             : in std_logic;
+  SCIWDATA6             : in std_logic;
+  SCIWDATA7             : in std_logic;
+  SCIWSTN               : in std_logic;
+  REFCLK_FROM_NQ        : in std_logic;
+
+  HDOUTN0             : out std_logic;
+  HDOUTN1             : out std_logic;
+  HDOUTN2             : out std_logic;
+  HDOUTN3             : out std_logic;
+  HDOUTP0             : out std_logic;
+  HDOUTP1             : out std_logic;
+  HDOUTP2             : out std_logic;
+  HDOUTP3             : out std_logic;
+  COUT0             : out std_logic;
+  COUT1             : out std_logic;
+  COUT2             : out std_logic;
+  COUT3             : out std_logic;
+  COUT4             : out std_logic;
+  COUT5             : out std_logic;
+  COUT6             : out std_logic;
+  COUT7             : out std_logic;
+  COUT8             : out std_logic;
+  COUT9             : out std_logic;
+  COUT10             : out std_logic;
+  COUT11             : out std_logic;
+  COUT12             : out std_logic;
+  COUT13             : out std_logic;
+  COUT14             : out std_logic;
+  COUT15             : out std_logic;
+  COUT16             : out std_logic;
+  COUT17             : out std_logic;
+  COUT18             : out std_logic;
+  COUT19             : out std_logic;
+  FF_RX_D_0_0             : out std_logic;
+  FF_RX_D_0_1             : out std_logic;
+  FF_RX_D_0_2             : out std_logic;
+  FF_RX_D_0_3             : out std_logic;
+  FF_RX_D_0_4             : out std_logic;
+  FF_RX_D_0_5             : out std_logic;
+  FF_RX_D_0_6             : out std_logic;
+  FF_RX_D_0_7             : out std_logic;
+  FF_RX_D_0_8             : out std_logic;
+  FF_RX_D_0_9             : out std_logic;
+  FF_RX_D_0_10             : out std_logic;
+  FF_RX_D_0_11             : out std_logic;
+  FF_RX_D_0_12             : out std_logic;
+  FF_RX_D_0_13             : out std_logic;
+  FF_RX_D_0_14             : out std_logic;
+  FF_RX_D_0_15             : out std_logic;
+  FF_RX_D_0_16             : out std_logic;
+  FF_RX_D_0_17             : out std_logic;
+  FF_RX_D_0_18             : out std_logic;
+  FF_RX_D_0_19             : out std_logic;
+  FF_RX_D_0_20             : out std_logic;
+  FF_RX_D_0_21             : out std_logic;
+  FF_RX_D_0_22             : out std_logic;
+  FF_RX_D_0_23             : out std_logic;
+  FF_RX_D_1_0             : out std_logic;
+  FF_RX_D_1_1             : out std_logic;
+  FF_RX_D_1_2             : out std_logic;
+  FF_RX_D_1_3             : out std_logic;
+  FF_RX_D_1_4             : out std_logic;
+  FF_RX_D_1_5             : out std_logic;
+  FF_RX_D_1_6             : out std_logic;
+  FF_RX_D_1_7             : out std_logic;
+  FF_RX_D_1_8             : out std_logic;
+  FF_RX_D_1_9             : out std_logic;
+  FF_RX_D_1_10             : out std_logic;
+  FF_RX_D_1_11             : out std_logic;
+  FF_RX_D_1_12             : out std_logic;
+  FF_RX_D_1_13             : out std_logic;
+  FF_RX_D_1_14             : out std_logic;
+  FF_RX_D_1_15             : out std_logic;
+  FF_RX_D_1_16             : out std_logic;
+  FF_RX_D_1_17             : out std_logic;
+  FF_RX_D_1_18             : out std_logic;
+  FF_RX_D_1_19             : out std_logic;
+  FF_RX_D_1_20             : out std_logic;
+  FF_RX_D_1_21             : out std_logic;
+  FF_RX_D_1_22             : out std_logic;
+  FF_RX_D_1_23             : out std_logic;
+  FF_RX_D_2_0             : out std_logic;
+  FF_RX_D_2_1             : out std_logic;
+  FF_RX_D_2_2             : out std_logic;
+  FF_RX_D_2_3             : out std_logic;
+  FF_RX_D_2_4             : out std_logic;
+  FF_RX_D_2_5             : out std_logic;
+  FF_RX_D_2_6             : out std_logic;
+  FF_RX_D_2_7             : out std_logic;
+  FF_RX_D_2_8             : out std_logic;
+  FF_RX_D_2_9             : out std_logic;
+  FF_RX_D_2_10             : out std_logic;
+  FF_RX_D_2_11             : out std_logic;
+  FF_RX_D_2_12             : out std_logic;
+  FF_RX_D_2_13             : out std_logic;
+  FF_RX_D_2_14             : out std_logic;
+  FF_RX_D_2_15             : out std_logic;
+  FF_RX_D_2_16             : out std_logic;
+  FF_RX_D_2_17             : out std_logic;
+  FF_RX_D_2_18             : out std_logic;
+  FF_RX_D_2_19             : out std_logic;
+  FF_RX_D_2_20             : out std_logic;
+  FF_RX_D_2_21             : out std_logic;
+  FF_RX_D_2_22             : out std_logic;
+  FF_RX_D_2_23             : out std_logic;
+  FF_RX_D_3_0             : out std_logic;
+  FF_RX_D_3_1             : out std_logic;
+  FF_RX_D_3_2             : out std_logic;
+  FF_RX_D_3_3             : out std_logic;
+  FF_RX_D_3_4             : out std_logic;
+  FF_RX_D_3_5             : out std_logic;
+  FF_RX_D_3_6             : out std_logic;
+  FF_RX_D_3_7             : out std_logic;
+  FF_RX_D_3_8             : out std_logic;
+  FF_RX_D_3_9             : out std_logic;
+  FF_RX_D_3_10             : out std_logic;
+  FF_RX_D_3_11             : out std_logic;
+  FF_RX_D_3_12             : out std_logic;
+  FF_RX_D_3_13             : out std_logic;
+  FF_RX_D_3_14             : out std_logic;
+  FF_RX_D_3_15             : out std_logic;
+  FF_RX_D_3_16             : out std_logic;
+  FF_RX_D_3_17             : out std_logic;
+  FF_RX_D_3_18             : out std_logic;
+  FF_RX_D_3_19             : out std_logic;
+  FF_RX_D_3_20             : out std_logic;
+  FF_RX_D_3_21             : out std_logic;
+  FF_RX_D_3_22             : out std_logic;
+  FF_RX_D_3_23             : out std_logic;
+  FF_RX_F_CLK_0             : out std_logic;
+  FF_RX_F_CLK_1             : out std_logic;
+  FF_RX_F_CLK_2             : out std_logic;
+  FF_RX_F_CLK_3             : out std_logic;
+  FF_RX_H_CLK_0             : out std_logic;
+  FF_RX_H_CLK_1             : out std_logic;
+  FF_RX_H_CLK_2             : out std_logic;
+  FF_RX_H_CLK_3             : out std_logic;
+  FF_TX_F_CLK_0             : out std_logic;
+  FF_TX_F_CLK_1             : out std_logic;
+  FF_TX_F_CLK_2             : out std_logic;
+  FF_TX_F_CLK_3             : out std_logic;
+  FF_TX_H_CLK_0             : out std_logic;
+  FF_TX_H_CLK_1             : out std_logic;
+  FF_TX_H_CLK_2             : out std_logic;
+  FF_TX_H_CLK_3             : out std_logic;
+  FFS_CC_OVERRUN_0             : out std_logic;
+  FFS_CC_OVERRUN_1             : out std_logic;
+  FFS_CC_OVERRUN_2             : out std_logic;
+  FFS_CC_OVERRUN_3             : out std_logic;
+  FFS_CC_UNDERRUN_0             : out std_logic;
+  FFS_CC_UNDERRUN_1             : out std_logic;
+  FFS_CC_UNDERRUN_2             : out std_logic;
+  FFS_CC_UNDERRUN_3             : out std_logic;
+  FFS_LS_SYNC_STATUS_0             : out std_logic;
+  FFS_LS_SYNC_STATUS_1             : out std_logic;
+  FFS_LS_SYNC_STATUS_2             : out std_logic;
+  FFS_LS_SYNC_STATUS_3             : out std_logic;
+  FFS_CDR_TRAIN_DONE_0             : out std_logic;
+  FFS_CDR_TRAIN_DONE_1             : out std_logic;
+  FFS_CDR_TRAIN_DONE_2             : out std_logic;
+  FFS_CDR_TRAIN_DONE_3             : out std_logic;
+  FFS_PCIE_CON_0             : out std_logic;
+  FFS_PCIE_CON_1             : out std_logic;
+  FFS_PCIE_CON_2             : out std_logic;
+  FFS_PCIE_CON_3             : out std_logic;
+  FFS_PCIE_DONE_0             : out std_logic;
+  FFS_PCIE_DONE_1             : out std_logic;
+  FFS_PCIE_DONE_2             : out std_logic;
+  FFS_PCIE_DONE_3             : out std_logic;
+  FFS_PLOL             : out std_logic;
+  FFS_RLOL_0             : out std_logic;
+  FFS_RLOL_1             : out std_logic;
+  FFS_RLOL_2             : out std_logic;
+  FFS_RLOL_3             : out std_logic;
+  FFS_RLOS_HI_0             : out std_logic;
+  FFS_RLOS_HI_1             : out std_logic;
+  FFS_RLOS_HI_2             : out std_logic;
+  FFS_RLOS_HI_3             : out std_logic;
+  FFS_RLOS_LO_0             : out std_logic;
+  FFS_RLOS_LO_1             : out std_logic;
+  FFS_RLOS_LO_2             : out std_logic;
+  FFS_RLOS_LO_3             : out std_logic;
+  FFS_RXFBFIFO_ERROR_0             : out std_logic;
+  FFS_RXFBFIFO_ERROR_1             : out std_logic;
+  FFS_RXFBFIFO_ERROR_2             : out std_logic;
+  FFS_RXFBFIFO_ERROR_3             : out std_logic;
+  FFS_TXFBFIFO_ERROR_0             : out std_logic;
+  FFS_TXFBFIFO_ERROR_1             : out std_logic;
+  FFS_TXFBFIFO_ERROR_2             : out std_logic;
+  FFS_TXFBFIFO_ERROR_3             : out std_logic;
+  PCIE_PHYSTATUS_0             : out std_logic;
+  PCIE_PHYSTATUS_1             : out std_logic;
+  PCIE_PHYSTATUS_2             : out std_logic;
+  PCIE_PHYSTATUS_3             : out std_logic;
+  PCIE_RXVALID_0               : out std_logic;
+  PCIE_RXVALID_1               : out std_logic;
+  PCIE_RXVALID_2               : out std_logic;
+  PCIE_RXVALID_3               : out std_logic;
+  FFS_SKP_ADDED_0                  : out std_logic;
+  FFS_SKP_ADDED_1                  : out std_logic;
+  FFS_SKP_ADDED_2                  : out std_logic;
+  FFS_SKP_ADDED_3                  : out std_logic;
+  FFS_SKP_DELETED_0                : out std_logic;
+  FFS_SKP_DELETED_1                : out std_logic;
+  FFS_SKP_DELETED_2                : out std_logic;
+  FFS_SKP_DELETED_3                : out std_logic;
+  LDR_RX2CORE_0                    : out std_logic;
+  LDR_RX2CORE_1                    : out std_logic;
+  LDR_RX2CORE_2                    : out std_logic;
+  LDR_RX2CORE_3                    : out std_logic;
+  REFCK2CORE             : out std_logic;
+  SCIINT                : out std_logic;
+  SCIRDATA0             : out std_logic;
+  SCIRDATA1             : out std_logic;
+  SCIRDATA2             : out std_logic;
+  SCIRDATA3             : out std_logic;
+  SCIRDATA4             : out std_logic;
+  SCIRDATA5             : out std_logic;
+  SCIRDATA6             : out std_logic;
+  SCIRDATA7             : out std_logic;
+  REFCLK_TO_NQ          : out std_logic
+);
+end component;
+
+begin
+
+PCSD_sim_inst : PCSD_sim
+generic map (
+  CONFIG_FILE => CONFIG_FILE,
+  QUAD_MODE => QUAD_MODE,
+  CH0_CDR_SRC => CH0_CDR_SRC,
+  CH1_CDR_SRC => CH1_CDR_SRC,
+  CH2_CDR_SRC => CH2_CDR_SRC,
+  CH3_CDR_SRC => CH3_CDR_SRC,
+  PLL_SRC => PLL_SRC
+  )
+port map (
+   HDINN0 => HDINN0,
+   HDINN1 => HDINN1,
+   HDINN2 => HDINN2,
+   HDINN3 => HDINN3,
+   HDINP0 => HDINP0,
+   HDINP1 => HDINP1,
+   HDINP2 => HDINP2,
+   HDINP3 => HDINP3,
+   REFCLKN => REFCLKN,
+   REFCLKP => REFCLKP,
+   CIN11 => CIN11,
+   CIN10 => CIN10,
+   CIN9 => CIN9,
+   CIN8 => CIN8,
+   CIN7 => CIN7,
+   CIN6 => CIN6,
+   CIN5 => CIN5,
+   CIN4 => CIN4,
+   CIN3 => CIN3,
+   CIN2 => CIN2,
+   CIN1 => CIN1,
+   CIN0 => CIN0,
+   CYAWSTN => CYAWSTN,
+   FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
+   FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
+   FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
+   FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
+   FF_RXI_CLK_3 => FF_RXI_CLK_3,
+   FF_RXI_CLK_2 => FF_RXI_CLK_2,
+   FF_RXI_CLK_1 => FF_RXI_CLK_1,
+   FF_RXI_CLK_0 => FF_RXI_CLK_0,
+   FF_TX_D_0_0 => FF_TX_D_0_0,
+   FF_TX_D_0_1 => FF_TX_D_0_1,
+   FF_TX_D_0_2 => FF_TX_D_0_2,
+   FF_TX_D_0_3 => FF_TX_D_0_3,
+   FF_TX_D_0_4 => FF_TX_D_0_4,
+   FF_TX_D_0_5 => FF_TX_D_0_5,
+   FF_TX_D_0_6 => FF_TX_D_0_6,
+   FF_TX_D_0_7 => FF_TX_D_0_7,
+   FF_TX_D_0_8 => FF_TX_D_0_8,
+   FF_TX_D_0_9 => FF_TX_D_0_9,
+   FF_TX_D_0_10 => FF_TX_D_0_10,
+   FF_TX_D_0_11 => FF_TX_D_0_11,
+   FF_TX_D_0_12 => FF_TX_D_0_12,
+   FF_TX_D_0_13 => FF_TX_D_0_13,
+   FF_TX_D_0_14 => FF_TX_D_0_14,
+   FF_TX_D_0_15 => FF_TX_D_0_15,
+   FF_TX_D_0_16 => FF_TX_D_0_16,
+   FF_TX_D_0_17 => FF_TX_D_0_17,
+   FF_TX_D_0_18 => FF_TX_D_0_18,
+   FF_TX_D_0_19 => FF_TX_D_0_19,
+   FF_TX_D_0_20 => FF_TX_D_0_20,
+   FF_TX_D_0_21 => FF_TX_D_0_21,
+   FF_TX_D_0_22 => FF_TX_D_0_22,
+   FF_TX_D_0_23 => FF_TX_D_0_23,
+   FF_TX_D_1_0 => FF_TX_D_1_0,
+   FF_TX_D_1_1 => FF_TX_D_1_1,
+   FF_TX_D_1_2 => FF_TX_D_1_2,
+   FF_TX_D_1_3 => FF_TX_D_1_3,
+   FF_TX_D_1_4 => FF_TX_D_1_4,
+   FF_TX_D_1_5 => FF_TX_D_1_5,
+   FF_TX_D_1_6 => FF_TX_D_1_6,
+   FF_TX_D_1_7 => FF_TX_D_1_7,
+   FF_TX_D_1_8 => FF_TX_D_1_8,
+   FF_TX_D_1_9 => FF_TX_D_1_9,
+   FF_TX_D_1_10 => FF_TX_D_1_10,
+   FF_TX_D_1_11 => FF_TX_D_1_11,
+   FF_TX_D_1_12 => FF_TX_D_1_12,
+   FF_TX_D_1_13 => FF_TX_D_1_13,
+   FF_TX_D_1_14 => FF_TX_D_1_14,
+   FF_TX_D_1_15 => FF_TX_D_1_15,
+   FF_TX_D_1_16 => FF_TX_D_1_16,
+   FF_TX_D_1_17 => FF_TX_D_1_17,
+   FF_TX_D_1_18 => FF_TX_D_1_18,
+   FF_TX_D_1_19 => FF_TX_D_1_19,
+   FF_TX_D_1_20 => FF_TX_D_1_20,
+   FF_TX_D_1_21 => FF_TX_D_1_21,
+   FF_TX_D_1_22 => FF_TX_D_1_22,
+   FF_TX_D_1_23 => FF_TX_D_1_23,
+   FF_TX_D_2_0 => FF_TX_D_2_0,
+   FF_TX_D_2_1 => FF_TX_D_2_1,
+   FF_TX_D_2_2 => FF_TX_D_2_2,
+   FF_TX_D_2_3 => FF_TX_D_2_3,
+   FF_TX_D_2_4 => FF_TX_D_2_4,
+   FF_TX_D_2_5 => FF_TX_D_2_5,
+   FF_TX_D_2_6 => FF_TX_D_2_6,
+   FF_TX_D_2_7 => FF_TX_D_2_7,
+   FF_TX_D_2_8 => FF_TX_D_2_8,
+   FF_TX_D_2_9 => FF_TX_D_2_9,
+   FF_TX_D_2_10 => FF_TX_D_2_10,
+   FF_TX_D_2_11 => FF_TX_D_2_11,
+   FF_TX_D_2_12 => FF_TX_D_2_12,
+   FF_TX_D_2_13 => FF_TX_D_2_13,
+   FF_TX_D_2_14 => FF_TX_D_2_14,
+   FF_TX_D_2_15 => FF_TX_D_2_15,
+   FF_TX_D_2_16 => FF_TX_D_2_16,
+   FF_TX_D_2_17 => FF_TX_D_2_17,
+   FF_TX_D_2_18 => FF_TX_D_2_18,
+   FF_TX_D_2_19 => FF_TX_D_2_19,
+   FF_TX_D_2_20 => FF_TX_D_2_20,
+   FF_TX_D_2_21 => FF_TX_D_2_21,
+   FF_TX_D_2_22 => FF_TX_D_2_22,
+   FF_TX_D_2_23 => FF_TX_D_2_23,
+   FF_TX_D_3_0 => FF_TX_D_3_0,
+   FF_TX_D_3_1 => FF_TX_D_3_1,
+   FF_TX_D_3_2 => FF_TX_D_3_2,
+   FF_TX_D_3_3 => FF_TX_D_3_3,
+   FF_TX_D_3_4 => FF_TX_D_3_4,
+   FF_TX_D_3_5 => FF_TX_D_3_5,
+   FF_TX_D_3_6 => FF_TX_D_3_6,
+   FF_TX_D_3_7 => FF_TX_D_3_7,
+   FF_TX_D_3_8 => FF_TX_D_3_8,
+   FF_TX_D_3_9 => FF_TX_D_3_9,
+   FF_TX_D_3_10 => FF_TX_D_3_10,
+   FF_TX_D_3_11 => FF_TX_D_3_11,
+   FF_TX_D_3_12 => FF_TX_D_3_12,
+   FF_TX_D_3_13 => FF_TX_D_3_13,
+   FF_TX_D_3_14 => FF_TX_D_3_14,
+   FF_TX_D_3_15 => FF_TX_D_3_15,
+   FF_TX_D_3_16 => FF_TX_D_3_16,
+   FF_TX_D_3_17 => FF_TX_D_3_17,
+   FF_TX_D_3_18 => FF_TX_D_3_18,
+   FF_TX_D_3_19 => FF_TX_D_3_19,
+   FF_TX_D_3_20 => FF_TX_D_3_20,
+   FF_TX_D_3_21 => FF_TX_D_3_21,
+   FF_TX_D_3_22 => FF_TX_D_3_22,
+   FF_TX_D_3_23 => FF_TX_D_3_23,
+   FF_TXI_CLK_0 => FF_TXI_CLK_0,
+   FF_TXI_CLK_1 => FF_TXI_CLK_1,
+   FF_TXI_CLK_2 => FF_TXI_CLK_2,
+   FF_TXI_CLK_3 => FF_TXI_CLK_3,
+   FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
+   FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
+   FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
+   FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
+   FFC_CK_CORE_TX => FFC_CK_CORE_TX,
+   FFC_EI_EN_0 => FFC_EI_EN_0,
+   FFC_EI_EN_1 => FFC_EI_EN_1,
+   FFC_EI_EN_2 => FFC_EI_EN_2,
+   FFC_EI_EN_3 => FFC_EI_EN_3,
+   FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
+   FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
+   FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
+   FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
+   FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
+   FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
+   FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
+   FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
+   FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
+   FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
+   FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
+   FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
+   FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
+   FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
+   FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
+   FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
+   FFC_MACRO_RST => FFC_MACRO_RST,
+   FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
+   FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
+   FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
+   FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
+   FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
+   FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
+   FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
+   FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
+   FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
+   FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
+   FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
+   FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
+   FFC_QUAD_RST => FFC_QUAD_RST,
+   FFC_RRST_0 => FFC_RRST_0,
+   FFC_RRST_1 => FFC_RRST_1,
+   FFC_RRST_2 => FFC_RRST_2,
+   FFC_RRST_3 => FFC_RRST_3,
+   FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
+   FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
+   FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
+   FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
+   FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
+   FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
+   FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
+   FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
+   FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
+   FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
+   FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
+   FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
+   FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
+   FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
+   FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
+   FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
+   FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
+   FFC_TRST => FFC_TRST,
+   FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
+   FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
+   FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
+   FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
+   FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
+   FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
+   FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
+   FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
+   FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
+   FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
+   FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
+   FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
+   FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
+   FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
+   FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
+   FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
+   FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
+   FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
+   FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
+   FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
+   LDR_CORE2TX_0 => LDR_CORE2TX_0,
+   LDR_CORE2TX_1 => LDR_CORE2TX_1,
+   LDR_CORE2TX_2 => LDR_CORE2TX_2,
+   LDR_CORE2TX_3 => LDR_CORE2TX_3,
+   FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
+   FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
+   FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
+   FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
+   PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
+   PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
+   PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
+   PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
+   PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
+   PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
+   PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
+   PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
+   PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
+   PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
+   PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
+   PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
+   PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
+   PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
+   PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
+   PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
+   PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
+   PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
+   PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
+   PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
+   SCIADDR0 => SCIADDR0,
+   SCIADDR1 => SCIADDR1,
+   SCIADDR2 => SCIADDR2,
+   SCIADDR3 => SCIADDR3,
+   SCIADDR4 => SCIADDR4,
+   SCIADDR5 => SCIADDR5,
+   SCIENAUX => SCIENAUX,
+   SCIENCH0 => SCIENCH0,
+   SCIENCH1 => SCIENCH1,
+   SCIENCH2 => SCIENCH2,
+   SCIENCH3 => SCIENCH3,
+   SCIRD => SCIRD,
+   SCISELAUX => SCISELAUX,
+   SCISELCH0 => SCISELCH0,
+   SCISELCH1 => SCISELCH1,
+   SCISELCH2 => SCISELCH2,
+   SCISELCH3 => SCISELCH3,
+   SCIWDATA0 => SCIWDATA0,
+   SCIWDATA1 => SCIWDATA1,
+   SCIWDATA2 => SCIWDATA2,
+   SCIWDATA3 => SCIWDATA3,
+   SCIWDATA4 => SCIWDATA4,
+   SCIWDATA5 => SCIWDATA5,
+   SCIWDATA6 => SCIWDATA6,
+   SCIWDATA7 => SCIWDATA7,
+   SCIWSTN => SCIWSTN,
+   HDOUTN0 => HDOUTN0,
+   HDOUTN1 => HDOUTN1,
+   HDOUTN2 => HDOUTN2,
+   HDOUTN3 => HDOUTN3,
+   HDOUTP0 => HDOUTP0,
+   HDOUTP1 => HDOUTP1,
+   HDOUTP2 => HDOUTP2,
+   HDOUTP3 => HDOUTP3,
+   COUT19 => COUT19,
+   COUT18 => COUT18,
+   COUT17 => COUT17,
+   COUT16 => COUT16,
+   COUT15 => COUT15,
+   COUT14 => COUT14,
+   COUT13 => COUT13,
+   COUT12 => COUT12,
+   COUT11 => COUT11,
+   COUT10 => COUT10,
+   COUT9 => COUT9,
+   COUT8 => COUT8,
+   COUT7 => COUT7,
+   COUT6 => COUT6,
+   COUT5 => COUT5,
+   COUT4 => COUT4,
+   COUT3 => COUT3,
+   COUT2 => COUT2,
+   COUT1 => COUT1,
+   COUT0 => COUT0,
+   FF_RX_D_0_0 => FF_RX_D_0_0,
+   FF_RX_D_0_1 => FF_RX_D_0_1,
+   FF_RX_D_0_2 => FF_RX_D_0_2,
+   FF_RX_D_0_3 => FF_RX_D_0_3,
+   FF_RX_D_0_4 => FF_RX_D_0_4,
+   FF_RX_D_0_5 => FF_RX_D_0_5,
+   FF_RX_D_0_6 => FF_RX_D_0_6,
+   FF_RX_D_0_7 => FF_RX_D_0_7,
+   FF_RX_D_0_8 => FF_RX_D_0_8,
+   FF_RX_D_0_9 => FF_RX_D_0_9,
+   FF_RX_D_0_10 => FF_RX_D_0_10,
+   FF_RX_D_0_11 => FF_RX_D_0_11,
+   FF_RX_D_0_12 => FF_RX_D_0_12,
+   FF_RX_D_0_13 => FF_RX_D_0_13,
+   FF_RX_D_0_14 => FF_RX_D_0_14,
+   FF_RX_D_0_15 => FF_RX_D_0_15,
+   FF_RX_D_0_16 => FF_RX_D_0_16,
+   FF_RX_D_0_17 => FF_RX_D_0_17,
+   FF_RX_D_0_18 => FF_RX_D_0_18,
+   FF_RX_D_0_19 => FF_RX_D_0_19,
+   FF_RX_D_0_20 => FF_RX_D_0_20,
+   FF_RX_D_0_21 => FF_RX_D_0_21,
+   FF_RX_D_0_22 => FF_RX_D_0_22,
+   FF_RX_D_0_23 => FF_RX_D_0_23,
+   FF_RX_D_1_0 => FF_RX_D_1_0,
+   FF_RX_D_1_1 => FF_RX_D_1_1,
+   FF_RX_D_1_2 => FF_RX_D_1_2,
+   FF_RX_D_1_3 => FF_RX_D_1_3,
+   FF_RX_D_1_4 => FF_RX_D_1_4,
+   FF_RX_D_1_5 => FF_RX_D_1_5,
+   FF_RX_D_1_6 => FF_RX_D_1_6,
+   FF_RX_D_1_7 => FF_RX_D_1_7,
+   FF_RX_D_1_8 => FF_RX_D_1_8,
+   FF_RX_D_1_9 => FF_RX_D_1_9,
+   FF_RX_D_1_10 => FF_RX_D_1_10,
+   FF_RX_D_1_11 => FF_RX_D_1_11,
+   FF_RX_D_1_12 => FF_RX_D_1_12,
+   FF_RX_D_1_13 => FF_RX_D_1_13,
+   FF_RX_D_1_14 => FF_RX_D_1_14,
+   FF_RX_D_1_15 => FF_RX_D_1_15,
+   FF_RX_D_1_16 => FF_RX_D_1_16,
+   FF_RX_D_1_17 => FF_RX_D_1_17,
+   FF_RX_D_1_18 => FF_RX_D_1_18,
+   FF_RX_D_1_19 => FF_RX_D_1_19,
+   FF_RX_D_1_20 => FF_RX_D_1_20,
+   FF_RX_D_1_21 => FF_RX_D_1_21,
+   FF_RX_D_1_22 => FF_RX_D_1_22,
+   FF_RX_D_1_23 => FF_RX_D_1_23,
+   FF_RX_D_2_0 => FF_RX_D_2_0,
+   FF_RX_D_2_1 => FF_RX_D_2_1,
+   FF_RX_D_2_2 => FF_RX_D_2_2,
+   FF_RX_D_2_3 => FF_RX_D_2_3,
+   FF_RX_D_2_4 => FF_RX_D_2_4,
+   FF_RX_D_2_5 => FF_RX_D_2_5,
+   FF_RX_D_2_6 => FF_RX_D_2_6,
+   FF_RX_D_2_7 => FF_RX_D_2_7,
+   FF_RX_D_2_8 => FF_RX_D_2_8,
+   FF_RX_D_2_9 => FF_RX_D_2_9,
+   FF_RX_D_2_10 => FF_RX_D_2_10,
+   FF_RX_D_2_11 => FF_RX_D_2_11,
+   FF_RX_D_2_12 => FF_RX_D_2_12,
+   FF_RX_D_2_13 => FF_RX_D_2_13,
+   FF_RX_D_2_14 => FF_RX_D_2_14,
+   FF_RX_D_2_15 => FF_RX_D_2_15,
+   FF_RX_D_2_16 => FF_RX_D_2_16,
+   FF_RX_D_2_17 => FF_RX_D_2_17,
+   FF_RX_D_2_18 => FF_RX_D_2_18,
+   FF_RX_D_2_19 => FF_RX_D_2_19,
+   FF_RX_D_2_20 => FF_RX_D_2_20,
+   FF_RX_D_2_21 => FF_RX_D_2_21,
+   FF_RX_D_2_22 => FF_RX_D_2_22,
+   FF_RX_D_2_23 => FF_RX_D_2_23,
+   FF_RX_D_3_0 => FF_RX_D_3_0,
+   FF_RX_D_3_1 => FF_RX_D_3_1,
+   FF_RX_D_3_2 => FF_RX_D_3_2,
+   FF_RX_D_3_3 => FF_RX_D_3_3,
+   FF_RX_D_3_4 => FF_RX_D_3_4,
+   FF_RX_D_3_5 => FF_RX_D_3_5,
+   FF_RX_D_3_6 => FF_RX_D_3_6,
+   FF_RX_D_3_7 => FF_RX_D_3_7,
+   FF_RX_D_3_8 => FF_RX_D_3_8,
+   FF_RX_D_3_9 => FF_RX_D_3_9,
+   FF_RX_D_3_10 => FF_RX_D_3_10,
+   FF_RX_D_3_11 => FF_RX_D_3_11,
+   FF_RX_D_3_12 => FF_RX_D_3_12,
+   FF_RX_D_3_13 => FF_RX_D_3_13,
+   FF_RX_D_3_14 => FF_RX_D_3_14,
+   FF_RX_D_3_15 => FF_RX_D_3_15,
+   FF_RX_D_3_16 => FF_RX_D_3_16,
+   FF_RX_D_3_17 => FF_RX_D_3_17,
+   FF_RX_D_3_18 => FF_RX_D_3_18,
+   FF_RX_D_3_19 => FF_RX_D_3_19,
+   FF_RX_D_3_20 => FF_RX_D_3_20,
+   FF_RX_D_3_21 => FF_RX_D_3_21,
+   FF_RX_D_3_22 => FF_RX_D_3_22,
+   FF_RX_D_3_23 => FF_RX_D_3_23,
+   FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
+   FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
+   FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
+   FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
+   FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
+   FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
+   FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
+   FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
+   FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
+   FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
+   FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
+   FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
+   FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
+   FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
+   FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
+   FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
+   FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
+   FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
+   FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
+   FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
+   FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
+   FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
+   FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
+   FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
+   FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
+   FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
+   FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
+   FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
+   FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
+   FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
+   FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
+   FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
+   FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
+   FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
+   FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
+   FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
+   FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
+   FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
+   FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
+   FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
+   FFS_PLOL => FFS_PLOL,
+   FFS_RLOL_0 => FFS_RLOL_0,
+   FFS_RLOL_1 => FFS_RLOL_1,
+   FFS_RLOL_2 => FFS_RLOL_2,
+   FFS_RLOL_3 => FFS_RLOL_3,
+   FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
+   FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
+   FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
+   FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
+   FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
+   FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
+   FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
+   FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
+   FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
+   FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
+   FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
+   FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
+   FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
+   FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
+   FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
+   FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
+   PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
+   PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
+   PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
+   PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
+   PCIE_RXVALID_0 => PCIE_RXVALID_0,
+   PCIE_RXVALID_1 => PCIE_RXVALID_1,
+   PCIE_RXVALID_2 => PCIE_RXVALID_2,
+   PCIE_RXVALID_3 => PCIE_RXVALID_3,
+   FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
+   FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
+   FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
+   FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
+   FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
+   FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
+   FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
+   FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
+   LDR_RX2CORE_0 => LDR_RX2CORE_0,
+   LDR_RX2CORE_1 => LDR_RX2CORE_1,
+   LDR_RX2CORE_2 => LDR_RX2CORE_2,
+   LDR_RX2CORE_3 => LDR_RX2CORE_3,
+   REFCK2CORE => REFCK2CORE,
+   SCIINT => SCIINT,
+   SCIRDATA0 => SCIRDATA0,
+   SCIRDATA1 => SCIRDATA1,
+   SCIRDATA2 => SCIRDATA2,
+   SCIRDATA3 => SCIRDATA3,
+   SCIRDATA4 => SCIRDATA4,
+   SCIRDATA5 => SCIRDATA5,
+   SCIRDATA6 => SCIRDATA6,
+   SCIRDATA7 => SCIRDATA7,
+   REFCLK_FROM_NQ => REFCLK_FROM_NQ,
+   REFCLK_TO_NQ => REFCLK_TO_NQ
+   );
+
+end PCSD_arch;
+
+--synopsys translate_on
+
+
+
+
+--synopsys translate_off
+library ECP3;
+use ECP3.components.all;
+--synopsys translate_on
+
+
+library IEEE, STD;
+use IEEE.std_logic_1164.all;
+use STD.TEXTIO.all;
+
+entity sfp_1_2sync_3_200_int is
+   GENERIC (USER_CONFIG_FILE    :  String := "sfp_1_2sync_3_200_int.txt");
+ port (
+------------------
+-- CH0 --
+-- CH1 --
+    hdinp_ch1, hdinn_ch1    :   in std_logic;
+    hdoutp_ch1, hdoutn_ch1   :   out std_logic;
+    sci_sel_ch1    :   in std_logic;
+    rxiclk_ch1    :   in std_logic;
+    txiclk_ch1    :   in std_logic;
+    rx_full_clk_ch1   :   out std_logic;
+    rx_half_clk_ch1   :   out std_logic;
+    tx_full_clk_ch1   :   out std_logic;
+    tx_half_clk_ch1   :   out std_logic;
+    fpga_rxrefclk_ch1    :   in std_logic;
+    txdata_ch1    :   in std_logic_vector (15 downto 0);
+    tx_k_ch1    :   in std_logic_vector (1 downto 0);
+    tx_force_disp_ch1    :   in std_logic_vector (1 downto 0);
+    tx_disp_sel_ch1    :   in std_logic_vector (1 downto 0);
+    rxdata_ch1   :   out std_logic_vector (15 downto 0);
+    rx_k_ch1   :   out std_logic_vector (1 downto 0);
+    rx_disp_err_ch1   :   out std_logic_vector (1 downto 0);
+    rx_cv_err_ch1   :   out std_logic_vector (1 downto 0);
+    rx_serdes_rst_ch1_c    :   in std_logic;
+    sb_felb_ch1_c    :   in std_logic;
+    sb_felb_rst_ch1_c    :   in std_logic;
+    tx_pcs_rst_ch1_c    :   in std_logic;
+    tx_pwrup_ch1_c    :   in std_logic;
+    rx_pcs_rst_ch1_c    :   in std_logic;
+    rx_pwrup_ch1_c    :   in std_logic;
+    rx_los_low_ch1_s   :   out std_logic;
+    lsm_status_ch1_s   :   out std_logic;
+    rx_cdr_lol_ch1_s   :   out std_logic;
+    tx_div2_mode_ch1_c   : in std_logic;
+    rx_div2_mode_ch1_c   : in std_logic;
+-- CH2 --
+    hdinp_ch2, hdinn_ch2    :   in std_logic;
+    hdoutp_ch2, hdoutn_ch2   :   out std_logic;
+    sci_sel_ch2    :   in std_logic;
+    rxiclk_ch2    :   in std_logic;
+    txiclk_ch2    :   in std_logic;
+    rx_full_clk_ch2   :   out std_logic;
+    rx_half_clk_ch2   :   out std_logic;
+    tx_full_clk_ch2   :   out std_logic;
+    tx_half_clk_ch2   :   out std_logic;
+    fpga_rxrefclk_ch2    :   in std_logic;
+    txdata_ch2    :   in std_logic_vector (7 downto 0);
+    tx_k_ch2    :   in std_logic;
+    tx_force_disp_ch2    :   in std_logic;
+    tx_disp_sel_ch2    :   in std_logic;
+    rxdata_ch2   :   out std_logic_vector (7 downto 0);
+    rx_k_ch2   :   out std_logic;
+    rx_disp_err_ch2   :   out std_logic;
+    rx_cv_err_ch2   :   out std_logic;
+    rx_serdes_rst_ch2_c    :   in std_logic;
+    sb_felb_ch2_c    :   in std_logic;
+    sb_felb_rst_ch2_c    :   in std_logic;
+    tx_pcs_rst_ch2_c    :   in std_logic;
+    tx_pwrup_ch2_c    :   in std_logic;
+    rx_pcs_rst_ch2_c    :   in std_logic;
+    rx_pwrup_ch2_c    :   in std_logic;
+    rx_los_low_ch2_s   :   out std_logic;
+    lsm_status_ch2_s   :   out std_logic;
+    rx_cdr_lol_ch2_s   :   out std_logic;
+    tx_div2_mode_ch2_c   : in std_logic;
+    rx_div2_mode_ch2_c   : in std_logic;
+-- CH3 --
+    hdoutp_ch3, hdoutn_ch3   :   out std_logic;
+    sci_sel_ch3    :   in std_logic;
+    txiclk_ch3    :   in std_logic;
+    tx_full_clk_ch3   :   out std_logic;
+    tx_half_clk_ch3   :   out std_logic;
+    txdata_ch3    :   in std_logic_vector (7 downto 0);
+    tx_k_ch3    :   in std_logic;
+    tx_force_disp_ch3    :   in std_logic;
+    tx_disp_sel_ch3    :   in std_logic;
+    tx_pcs_rst_ch3_c    :   in std_logic;
+    tx_pwrup_ch3_c    :   in std_logic;
+    tx_div2_mode_ch3_c   : in std_logic;
+---- Miscillaneous ports
+    sci_wrdata    :   in std_logic_vector (7 downto 0);
+    sci_addr    :   in std_logic_vector (5 downto 0);
+    sci_rddata   :   out std_logic_vector (7 downto 0);
+    sci_sel_quad    :   in std_logic;
+    sci_rd    :   in std_logic;
+    sci_wrn    :   in std_logic;
+    fpga_txrefclk  :   in std_logic;
+    tx_serdes_rst_c    :   in std_logic;
+    tx_pll_lol_qd_s   :   out std_logic;
+    tx_sync_qd_c    :   in std_logic;
+    rst_qd_c    :   in std_logic;
+    serdes_rst_qd_c    :   in std_logic);
+
+end sfp_1_2sync_3_200_int;
+
+
+architecture sfp_1_2sync_3_200_int_arch of sfp_1_2sync_3_200_int is
+
+component VLO
+port (
+   Z : out std_logic);
+end component;
+
+component VHI
+port (
+   Z : out std_logic);
+end component;
+
+
+
+component PCSD
+--synopsys translate_off
+GENERIC(
+  CONFIG_FILE : String;
+  QUAD_MODE : String;
+  CH0_CDR_SRC   : String := "REFCLK_EXT";
+  CH1_CDR_SRC   : String := "REFCLK_EXT";
+  CH2_CDR_SRC   : String := "REFCLK_EXT";
+  CH3_CDR_SRC   : String := "REFCLK_EXT";
+  PLL_SRC   : String
+  );
+--synopsys translate_on
+port (
+  HDINN0             : in std_logic;
+  HDINN1             : in std_logic;
+  HDINN2             : in std_logic;
+  HDINN3             : in std_logic;
+  HDINP0             : in std_logic;
+  HDINP1             : in std_logic;
+  HDINP2             : in std_logic;
+  HDINP3             : in std_logic;
+  REFCLKN             : in std_logic;
+  REFCLKP             : in std_logic;
+  CIN0             : in std_logic;
+  CIN1             : in std_logic;
+  CIN2             : in std_logic;
+  CIN3             : in std_logic;
+  CIN4             : in std_logic;
+  CIN5             : in std_logic;
+  CIN6             : in std_logic;
+  CIN7             : in std_logic;
+  CIN8             : in std_logic;
+  CIN9             : in std_logic;
+  CIN10             : in std_logic;
+  CIN11             : in std_logic;
+  CYAWSTN             : in std_logic;
+  FF_EBRD_CLK_0             : in std_logic;
+  FF_EBRD_CLK_1             : in std_logic;
+  FF_EBRD_CLK_2             : in std_logic;
+  FF_EBRD_CLK_3             : in std_logic;
+  FF_RXI_CLK_0             : in std_logic;
+  FF_RXI_CLK_1             : in std_logic;
+  FF_RXI_CLK_2             : in std_logic;
+  FF_RXI_CLK_3             : in std_logic;
+  FF_TX_D_0_0             : in std_logic;
+  FF_TX_D_0_1             : in std_logic;
+  FF_TX_D_0_2             : in std_logic;
+  FF_TX_D_0_3             : in std_logic;
+  FF_TX_D_0_4             : in std_logic;
+  FF_TX_D_0_5             : in std_logic;
+  FF_TX_D_0_6             : in std_logic;
+  FF_TX_D_0_7             : in std_logic;
+  FF_TX_D_0_8             : in std_logic;
+  FF_TX_D_0_9             : in std_logic;
+  FF_TX_D_0_10             : in std_logic;
+  FF_TX_D_0_11             : in std_logic;
+  FF_TX_D_0_12             : in std_logic;
+  FF_TX_D_0_13             : in std_logic;
+  FF_TX_D_0_14             : in std_logic;
+  FF_TX_D_0_15             : in std_logic;
+  FF_TX_D_0_16             : in std_logic;
+  FF_TX_D_0_17             : in std_logic;
+  FF_TX_D_0_18             : in std_logic;
+  FF_TX_D_0_19             : in std_logic;
+  FF_TX_D_0_20             : in std_logic;
+  FF_TX_D_0_21             : in std_logic;
+  FF_TX_D_0_22             : in std_logic;
+  FF_TX_D_0_23             : in std_logic;
+  FF_TX_D_1_0             : in std_logic;
+  FF_TX_D_1_1             : in std_logic;
+  FF_TX_D_1_2             : in std_logic;
+  FF_TX_D_1_3             : in std_logic;
+  FF_TX_D_1_4             : in std_logic;
+  FF_TX_D_1_5             : in std_logic;
+  FF_TX_D_1_6             : in std_logic;
+  FF_TX_D_1_7             : in std_logic;
+  FF_TX_D_1_8             : in std_logic;
+  FF_TX_D_1_9             : in std_logic;
+  FF_TX_D_1_10             : in std_logic;
+  FF_TX_D_1_11             : in std_logic;
+  FF_TX_D_1_12             : in std_logic;
+  FF_TX_D_1_13             : in std_logic;
+  FF_TX_D_1_14             : in std_logic;
+  FF_TX_D_1_15             : in std_logic;
+  FF_TX_D_1_16             : in std_logic;
+  FF_TX_D_1_17             : in std_logic;
+  FF_TX_D_1_18             : in std_logic;
+  FF_TX_D_1_19             : in std_logic;
+  FF_TX_D_1_20             : in std_logic;
+  FF_TX_D_1_21             : in std_logic;
+  FF_TX_D_1_22             : in std_logic;
+  FF_TX_D_1_23             : in std_logic;
+  FF_TX_D_2_0             : in std_logic;
+  FF_TX_D_2_1             : in std_logic;
+  FF_TX_D_2_2             : in std_logic;
+  FF_TX_D_2_3             : in std_logic;
+  FF_TX_D_2_4             : in std_logic;
+  FF_TX_D_2_5             : in std_logic;
+  FF_TX_D_2_6             : in std_logic;
+  FF_TX_D_2_7             : in std_logic;
+  FF_TX_D_2_8             : in std_logic;
+  FF_TX_D_2_9             : in std_logic;
+  FF_TX_D_2_10             : in std_logic;
+  FF_TX_D_2_11             : in std_logic;
+  FF_TX_D_2_12             : in std_logic;
+  FF_TX_D_2_13             : in std_logic;
+  FF_TX_D_2_14             : in std_logic;
+  FF_TX_D_2_15             : in std_logic;
+  FF_TX_D_2_16             : in std_logic;
+  FF_TX_D_2_17             : in std_logic;
+  FF_TX_D_2_18             : in std_logic;
+  FF_TX_D_2_19             : in std_logic;
+  FF_TX_D_2_20             : in std_logic;
+  FF_TX_D_2_21             : in std_logic;
+  FF_TX_D_2_22             : in std_logic;
+  FF_TX_D_2_23             : in std_logic;
+  FF_TX_D_3_0             : in std_logic;
+  FF_TX_D_3_1             : in std_logic;
+  FF_TX_D_3_2             : in std_logic;
+  FF_TX_D_3_3             : in std_logic;
+  FF_TX_D_3_4             : in std_logic;
+  FF_TX_D_3_5             : in std_logic;
+  FF_TX_D_3_6             : in std_logic;
+  FF_TX_D_3_7             : in std_logic;
+  FF_TX_D_3_8             : in std_logic;
+  FF_TX_D_3_9             : in std_logic;
+  FF_TX_D_3_10             : in std_logic;
+  FF_TX_D_3_11             : in std_logic;
+  FF_TX_D_3_12             : in std_logic;
+  FF_TX_D_3_13             : in std_logic;
+  FF_TX_D_3_14             : in std_logic;
+  FF_TX_D_3_15             : in std_logic;
+  FF_TX_D_3_16             : in std_logic;
+  FF_TX_D_3_17             : in std_logic;
+  FF_TX_D_3_18             : in std_logic;
+  FF_TX_D_3_19             : in std_logic;
+  FF_TX_D_3_20             : in std_logic;
+  FF_TX_D_3_21             : in std_logic;
+  FF_TX_D_3_22             : in std_logic;
+  FF_TX_D_3_23             : in std_logic;
+  FF_TXI_CLK_0             : in std_logic;
+  FF_TXI_CLK_1             : in std_logic;
+  FF_TXI_CLK_2             : in std_logic;
+  FF_TXI_CLK_3             : in std_logic;
+  FFC_CK_CORE_RX_0         : in std_logic;
+  FFC_CK_CORE_RX_1         : in std_logic;
+  FFC_CK_CORE_RX_2         : in std_logic;
+  FFC_CK_CORE_RX_3         : in std_logic;
+  FFC_CK_CORE_TX           : in std_logic;
+  FFC_EI_EN_0             : in std_logic;
+  FFC_EI_EN_1             : in std_logic;
+  FFC_EI_EN_2             : in std_logic;
+  FFC_EI_EN_3             : in std_logic;
+  FFC_ENABLE_CGALIGN_0             : in std_logic;
+  FFC_ENABLE_CGALIGN_1             : in std_logic;
+  FFC_ENABLE_CGALIGN_2             : in std_logic;
+  FFC_ENABLE_CGALIGN_3             : in std_logic;
+  FFC_FB_LOOPBACK_0             : in std_logic;
+  FFC_FB_LOOPBACK_1             : in std_logic;
+  FFC_FB_LOOPBACK_2             : in std_logic;
+  FFC_FB_LOOPBACK_3             : in std_logic;
+  FFC_LANE_RX_RST_0             : in std_logic;
+  FFC_LANE_RX_RST_1             : in std_logic;
+  FFC_LANE_RX_RST_2             : in std_logic;
+  FFC_LANE_RX_RST_3             : in std_logic;
+  FFC_LANE_TX_RST_0             : in std_logic;
+  FFC_LANE_TX_RST_1             : in std_logic;
+  FFC_LANE_TX_RST_2             : in std_logic;
+  FFC_LANE_TX_RST_3             : in std_logic;
+  FFC_MACRO_RST             : in std_logic;
+  FFC_PCI_DET_EN_0             : in std_logic;
+  FFC_PCI_DET_EN_1             : in std_logic;
+  FFC_PCI_DET_EN_2             : in std_logic;
+  FFC_PCI_DET_EN_3             : in std_logic;
+  FFC_PCIE_CT_0             : in std_logic;
+  FFC_PCIE_CT_1             : in std_logic;
+  FFC_PCIE_CT_2             : in std_logic;
+  FFC_PCIE_CT_3             : in std_logic;
+  FFC_PFIFO_CLR_0             : in std_logic;
+  FFC_PFIFO_CLR_1             : in std_logic;
+  FFC_PFIFO_CLR_2             : in std_logic;
+  FFC_PFIFO_CLR_3             : in std_logic;
+  FFC_QUAD_RST             : in std_logic;
+  FFC_RRST_0             : in std_logic;
+  FFC_RRST_1             : in std_logic;
+  FFC_RRST_2             : in std_logic;
+  FFC_RRST_3             : in std_logic;
+  FFC_RXPWDNB_0             : in std_logic;
+  FFC_RXPWDNB_1             : in std_logic;
+  FFC_RXPWDNB_2             : in std_logic;
+  FFC_RXPWDNB_3             : in std_logic;
+  FFC_SB_INV_RX_0             : in std_logic;
+  FFC_SB_INV_RX_1             : in std_logic;
+  FFC_SB_INV_RX_2             : in std_logic;
+  FFC_SB_INV_RX_3             : in std_logic;
+  FFC_SB_PFIFO_LP_0             : in std_logic;
+  FFC_SB_PFIFO_LP_1             : in std_logic;
+  FFC_SB_PFIFO_LP_2             : in std_logic;
+  FFC_SB_PFIFO_LP_3             : in std_logic;
+  FFC_SIGNAL_DETECT_0             : in std_logic;
+  FFC_SIGNAL_DETECT_1             : in std_logic;
+  FFC_SIGNAL_DETECT_2             : in std_logic;
+  FFC_SIGNAL_DETECT_3             : in std_logic;
+  FFC_SYNC_TOGGLE             : in std_logic;
+  FFC_TRST             : in std_logic;
+  FFC_TXPWDNB_0             : in std_logic;
+  FFC_TXPWDNB_1             : in std_logic;
+  FFC_TXPWDNB_2             : in std_logic;
+  FFC_TXPWDNB_3             : in std_logic;
+  FFC_RATE_MODE_RX_0        : in std_logic;
+  FFC_RATE_MODE_RX_1        : in std_logic;
+  FFC_RATE_MODE_RX_2        : in std_logic;
+  FFC_RATE_MODE_RX_3        : in std_logic;
+  FFC_RATE_MODE_TX_0        : in std_logic;
+  FFC_RATE_MODE_TX_1        : in std_logic;
+  FFC_RATE_MODE_TX_2        : in std_logic;
+  FFC_RATE_MODE_TX_3        : in std_logic;
+  FFC_DIV11_MODE_RX_0       : in std_logic;
+  FFC_DIV11_MODE_RX_1       : in std_logic;
+  FFC_DIV11_MODE_RX_2       : in std_logic;
+  FFC_DIV11_MODE_RX_3       : in std_logic;
+  FFC_DIV11_MODE_TX_0       : in std_logic;
+  FFC_DIV11_MODE_TX_1       : in std_logic;
+  FFC_DIV11_MODE_TX_2       : in std_logic;
+  FFC_DIV11_MODE_TX_3       : in std_logic;
+  LDR_CORE2TX_0             : in std_logic;
+  LDR_CORE2TX_1             : in std_logic;
+  LDR_CORE2TX_2             : in std_logic;
+  LDR_CORE2TX_3             : in std_logic;
+  FFC_LDR_CORE2TX_EN_0      : in std_logic;
+  FFC_LDR_CORE2TX_EN_1      : in std_logic;
+  FFC_LDR_CORE2TX_EN_2      : in std_logic;
+  FFC_LDR_CORE2TX_EN_3      : in std_logic;
+  PCIE_POWERDOWN_0_0      : in std_logic;
+  PCIE_POWERDOWN_0_1      : in std_logic;
+  PCIE_POWERDOWN_1_0      : in std_logic;
+  PCIE_POWERDOWN_1_1      : in std_logic;
+  PCIE_POWERDOWN_2_0      : in std_logic;
+  PCIE_POWERDOWN_2_1      : in std_logic;
+  PCIE_POWERDOWN_3_0      : in std_logic;
+  PCIE_POWERDOWN_3_1      : in std_logic;
+  PCIE_RXPOLARITY_0         : in std_logic;
+  PCIE_RXPOLARITY_1         : in std_logic;
+  PCIE_RXPOLARITY_2         : in std_logic;
+  PCIE_RXPOLARITY_3         : in std_logic;
+  PCIE_TXCOMPLIANCE_0       : in std_logic;
+  PCIE_TXCOMPLIANCE_1       : in std_logic;
+  PCIE_TXCOMPLIANCE_2       : in std_logic;
+  PCIE_TXCOMPLIANCE_3       : in std_logic;
+  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
+  SCIADDR0             : in std_logic;
+  SCIADDR1             : in std_logic;
+  SCIADDR2             : in std_logic;
+  SCIADDR3             : in std_logic;
+  SCIADDR4             : in std_logic;
+  SCIADDR5             : in std_logic;
+  SCIENAUX             : in std_logic;
+  SCIENCH0             : in std_logic;
+  SCIENCH1             : in std_logic;
+  SCIENCH2             : in std_logic;
+  SCIENCH3             : in std_logic;
+  SCIRD                : in std_logic;
+  SCISELAUX             : in std_logic;
+  SCISELCH0             : in std_logic;
+  SCISELCH1             : in std_logic;
+  SCISELCH2             : in std_logic;
+  SCISELCH3             : in std_logic;
+  SCIWDATA0             : in std_logic;
+  SCIWDATA1             : in std_logic;
+  SCIWDATA2             : in std_logic;
+  SCIWDATA3             : in std_logic;
+  SCIWDATA4             : in std_logic;
+  SCIWDATA5             : in std_logic;
+  SCIWDATA6             : in std_logic;
+  SCIWDATA7             : in std_logic;
+  SCIWSTN               : in std_logic;
+  REFCLK_FROM_NQ        : in std_logic;
+  HDOUTN0             : out std_logic;
+  HDOUTN1             : out std_logic;
+  HDOUTN2             : out std_logic;
+  HDOUTN3             : out std_logic;
+  HDOUTP0             : out std_logic;
+  HDOUTP1             : out std_logic;
+  HDOUTP2             : out std_logic;
+  HDOUTP3             : out std_logic;
+  COUT0             : out std_logic;
+  COUT1             : out std_logic;
+  COUT2             : out std_logic;
+  COUT3             : out std_logic;
+  COUT4             : out std_logic;
+  COUT5             : out std_logic;
+  COUT6             : out std_logic;
+  COUT7             : out std_logic;
+  COUT8             : out std_logic;
+  COUT9             : out std_logic;
+  COUT10             : out std_logic;
+  COUT11             : out std_logic;
+  COUT12             : out std_logic;
+  COUT13             : out std_logic;
+  COUT14             : out std_logic;
+  COUT15             : out std_logic;
+  COUT16             : out std_logic;
+  COUT17             : out std_logic;
+  COUT18             : out std_logic;
+  COUT19             : out std_logic;
+  FF_RX_D_0_0             : out std_logic;
+  FF_RX_D_0_1             : out std_logic;
+  FF_RX_D_0_2             : out std_logic;
+  FF_RX_D_0_3             : out std_logic;
+  FF_RX_D_0_4             : out std_logic;
+  FF_RX_D_0_5             : out std_logic;
+  FF_RX_D_0_6             : out std_logic;
+  FF_RX_D_0_7             : out std_logic;
+  FF_RX_D_0_8             : out std_logic;
+  FF_RX_D_0_9             : out std_logic;
+  FF_RX_D_0_10             : out std_logic;
+  FF_RX_D_0_11             : out std_logic;
+  FF_RX_D_0_12             : out std_logic;
+  FF_RX_D_0_13             : out std_logic;
+  FF_RX_D_0_14             : out std_logic;
+  FF_RX_D_0_15             : out std_logic;
+  FF_RX_D_0_16             : out std_logic;
+  FF_RX_D_0_17             : out std_logic;
+  FF_RX_D_0_18             : out std_logic;
+  FF_RX_D_0_19             : out std_logic;
+  FF_RX_D_0_20             : out std_logic;
+  FF_RX_D_0_21             : out std_logic;
+  FF_RX_D_0_22             : out std_logic;
+  FF_RX_D_0_23             : out std_logic;
+  FF_RX_D_1_0             : out std_logic;
+  FF_RX_D_1_1             : out std_logic;
+  FF_RX_D_1_2             : out std_logic;
+  FF_RX_D_1_3             : out std_logic;
+  FF_RX_D_1_4             : out std_logic;
+  FF_RX_D_1_5             : out std_logic;
+  FF_RX_D_1_6             : out std_logic;
+  FF_RX_D_1_7             : out std_logic;
+  FF_RX_D_1_8             : out std_logic;
+  FF_RX_D_1_9             : out std_logic;
+  FF_RX_D_1_10             : out std_logic;
+  FF_RX_D_1_11             : out std_logic;
+  FF_RX_D_1_12             : out std_logic;
+  FF_RX_D_1_13             : out std_logic;
+  FF_RX_D_1_14             : out std_logic;
+  FF_RX_D_1_15             : out std_logic;
+  FF_RX_D_1_16             : out std_logic;
+  FF_RX_D_1_17             : out std_logic;
+  FF_RX_D_1_18             : out std_logic;
+  FF_RX_D_1_19             : out std_logic;
+  FF_RX_D_1_20             : out std_logic;
+  FF_RX_D_1_21             : out std_logic;
+  FF_RX_D_1_22             : out std_logic;
+  FF_RX_D_1_23             : out std_logic;
+  FF_RX_D_2_0             : out std_logic;
+  FF_RX_D_2_1             : out std_logic;
+  FF_RX_D_2_2             : out std_logic;
+  FF_RX_D_2_3             : out std_logic;
+  FF_RX_D_2_4             : out std_logic;
+  FF_RX_D_2_5             : out std_logic;
+  FF_RX_D_2_6             : out std_logic;
+  FF_RX_D_2_7             : out std_logic;
+  FF_RX_D_2_8             : out std_logic;
+  FF_RX_D_2_9             : out std_logic;
+  FF_RX_D_2_10             : out std_logic;
+  FF_RX_D_2_11             : out std_logic;
+  FF_RX_D_2_12             : out std_logic;
+  FF_RX_D_2_13             : out std_logic;
+  FF_RX_D_2_14             : out std_logic;
+  FF_RX_D_2_15             : out std_logic;
+  FF_RX_D_2_16             : out std_logic;
+  FF_RX_D_2_17             : out std_logic;
+  FF_RX_D_2_18             : out std_logic;
+  FF_RX_D_2_19             : out std_logic;
+  FF_RX_D_2_20             : out std_logic;
+  FF_RX_D_2_21             : out std_logic;
+  FF_RX_D_2_22             : out std_logic;
+  FF_RX_D_2_23             : out std_logic;
+  FF_RX_D_3_0             : out std_logic;
+  FF_RX_D_3_1             : out std_logic;
+  FF_RX_D_3_2             : out std_logic;
+  FF_RX_D_3_3             : out std_logic;
+  FF_RX_D_3_4             : out std_logic;
+  FF_RX_D_3_5             : out std_logic;
+  FF_RX_D_3_6             : out std_logic;
+  FF_RX_D_3_7             : out std_logic;
+  FF_RX_D_3_8             : out std_logic;
+  FF_RX_D_3_9             : out std_logic;
+  FF_RX_D_3_10             : out std_logic;
+  FF_RX_D_3_11             : out std_logic;
+  FF_RX_D_3_12             : out std_logic;
+  FF_RX_D_3_13             : out std_logic;
+  FF_RX_D_3_14             : out std_logic;
+  FF_RX_D_3_15             : out std_logic;
+  FF_RX_D_3_16             : out std_logic;
+  FF_RX_D_3_17             : out std_logic;
+  FF_RX_D_3_18             : out std_logic;
+  FF_RX_D_3_19             : out std_logic;
+  FF_RX_D_3_20             : out std_logic;
+  FF_RX_D_3_21             : out std_logic;
+  FF_RX_D_3_22             : out std_logic;
+  FF_RX_D_3_23             : out std_logic;
+  FF_RX_F_CLK_0             : out std_logic;
+  FF_RX_F_CLK_1             : out std_logic;
+  FF_RX_F_CLK_2             : out std_logic;
+  FF_RX_F_CLK_3             : out std_logic;
+  FF_RX_H_CLK_0             : out std_logic;
+  FF_RX_H_CLK_1             : out std_logic;
+  FF_RX_H_CLK_2             : out std_logic;
+  FF_RX_H_CLK_3             : out std_logic;
+  FF_TX_F_CLK_0             : out std_logic;
+  FF_TX_F_CLK_1             : out std_logic;
+  FF_TX_F_CLK_2             : out std_logic;
+  FF_TX_F_CLK_3             : out std_logic;
+  FF_TX_H_CLK_0             : out std_logic;
+  FF_TX_H_CLK_1             : out std_logic;
+  FF_TX_H_CLK_2             : out std_logic;
+  FF_TX_H_CLK_3             : out std_logic;
+  FFS_CC_OVERRUN_0             : out std_logic;
+  FFS_CC_OVERRUN_1             : out std_logic;
+  FFS_CC_OVERRUN_2             : out std_logic;
+  FFS_CC_OVERRUN_3             : out std_logic;
+  FFS_CC_UNDERRUN_0             : out std_logic;
+  FFS_CC_UNDERRUN_1             : out std_logic;
+  FFS_CC_UNDERRUN_2             : out std_logic;
+  FFS_CC_UNDERRUN_3             : out std_logic;
+  FFS_LS_SYNC_STATUS_0             : out std_logic;
+  FFS_LS_SYNC_STATUS_1             : out std_logic;
+  FFS_LS_SYNC_STATUS_2             : out std_logic;
+  FFS_LS_SYNC_STATUS_3             : out std_logic;
+  FFS_CDR_TRAIN_DONE_0             : out std_logic;
+  FFS_CDR_TRAIN_DONE_1             : out std_logic;
+  FFS_CDR_TRAIN_DONE_2             : out std_logic;
+  FFS_CDR_TRAIN_DONE_3             : out std_logic;
+  FFS_PCIE_CON_0             : out std_logic;
+  FFS_PCIE_CON_1             : out std_logic;
+  FFS_PCIE_CON_2             : out std_logic;
+  FFS_PCIE_CON_3             : out std_logic;
+  FFS_PCIE_DONE_0             : out std_logic;
+  FFS_PCIE_DONE_1             : out std_logic;
+  FFS_PCIE_DONE_2             : out std_logic;
+  FFS_PCIE_DONE_3             : out std_logic;
+  FFS_PLOL             : out std_logic;
+  FFS_RLOL_0             : out std_logic;
+  FFS_RLOL_1             : out std_logic;
+  FFS_RLOL_2             : out std_logic;
+  FFS_RLOL_3             : out std_logic;
+  FFS_RLOS_HI_0             : out std_logic;
+  FFS_RLOS_HI_1             : out std_logic;
+  FFS_RLOS_HI_2             : out std_logic;
+  FFS_RLOS_HI_3             : out std_logic;
+  FFS_RLOS_LO_0             : out std_logic;
+  FFS_RLOS_LO_1             : out std_logic;
+  FFS_RLOS_LO_2             : out std_logic;
+  FFS_RLOS_LO_3             : out std_logic;
+  FFS_RXFBFIFO_ERROR_0             : out std_logic;
+  FFS_RXFBFIFO_ERROR_1             : out std_logic;
+  FFS_RXFBFIFO_ERROR_2             : out std_logic;
+  FFS_RXFBFIFO_ERROR_3             : out std_logic;
+  FFS_TXFBFIFO_ERROR_0             : out std_logic;
+  FFS_TXFBFIFO_ERROR_1             : out std_logic;
+  FFS_TXFBFIFO_ERROR_2             : out std_logic;
+  FFS_TXFBFIFO_ERROR_3             : out std_logic;
+  PCIE_PHYSTATUS_0             : out std_logic;
+  PCIE_PHYSTATUS_1             : out std_logic;
+  PCIE_PHYSTATUS_2             : out std_logic;
+  PCIE_PHYSTATUS_3             : out std_logic;
+  PCIE_RXVALID_0               : out std_logic;
+  PCIE_RXVALID_1               : out std_logic;
+  PCIE_RXVALID_2               : out std_logic;
+  PCIE_RXVALID_3               : out std_logic;
+  FFS_SKP_ADDED_0                  : out std_logic;
+  FFS_SKP_ADDED_1                  : out std_logic;
+  FFS_SKP_ADDED_2                  : out std_logic;
+  FFS_SKP_ADDED_3                  : out std_logic;
+  FFS_SKP_DELETED_0                : out std_logic;
+  FFS_SKP_DELETED_1                : out std_logic;
+  FFS_SKP_DELETED_2                : out std_logic;
+  FFS_SKP_DELETED_3                : out std_logic;
+  LDR_RX2CORE_0                    : out std_logic;
+  LDR_RX2CORE_1                    : out std_logic;
+  LDR_RX2CORE_2                    : out std_logic;
+  LDR_RX2CORE_3                    : out std_logic;
+  REFCK2CORE             : out std_logic;
+  SCIINT                : out std_logic;
+  SCIRDATA0             : out std_logic;
+  SCIRDATA1             : out std_logic;
+  SCIRDATA2             : out std_logic;
+  SCIRDATA3             : out std_logic;
+  SCIRDATA4             : out std_logic;
+  SCIRDATA5             : out std_logic;
+  SCIRDATA6             : out std_logic;
+  SCIRDATA7             : out std_logic;
+  REFCLK_TO_NQ          : out std_logic
+);
+end component;
+   attribute CONFIG_FILE: string;
+   attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
+   attribute QUAD_MODE: string;
+   attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
+   attribute PLL_SRC: string;
+   attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
+   attribute CH1_CDR_SRC: string;
+   attribute CH1_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+   attribute CH2_CDR_SRC: string;
+   attribute CH2_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+   attribute CH3_CDR_SRC: string;
+   attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_EXT";
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "250.000";
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "200";
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "200";
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "250.000";
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "125.000";
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "100";
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "100";
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "125.000";
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200";
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200";
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200";
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "100";
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100";
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100";
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100";
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "50";
+   attribute black_box_pad_pin: string;
+   attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
+
+signal refclk_from_nq : std_logic := '0';
+signal fpsc_vlo : std_logic := '0';
+signal fpsc_vhi : std_logic := '1';
+signal cin : std_logic_vector (11 downto 0) := "000000000000";
+signal cout : std_logic_vector (19 downto 0);
+signal    tx_full_clk_ch1_sig   :   std_logic;
+signal    tx_full_clk_ch2_sig   :   std_logic;
+signal    tx_full_clk_ch3_sig   :   std_logic;
+
+signal    refclk2fpga_sig  :   std_logic;
+signal    tx_pll_lol_qd_sig  :   std_logic;
+signal    rx_los_low_ch0_sig  :   std_logic;
+signal    rx_los_low_ch1_sig  :   std_logic;
+signal    rx_los_low_ch2_sig  :   std_logic;
+signal    rx_los_low_ch3_sig  :   std_logic;
+signal    rx_cdr_lol_ch0_sig  :   std_logic;
+signal    rx_cdr_lol_ch1_sig  :   std_logic;
+signal    rx_cdr_lol_ch2_sig  :   std_logic;
+signal    rx_cdr_lol_ch3_sig  :   std_logic;
+
+
+
+
+
+begin
+
+vlo_inst : VLO port map(Z => fpsc_vlo);
+vhi_inst : VHI port map(Z => fpsc_vhi);
+
+    rx_los_low_ch1_s <= rx_los_low_ch1_sig;
+    rx_los_low_ch2_s <= rx_los_low_ch2_sig;
+    rx_cdr_lol_ch1_s <= rx_cdr_lol_ch1_sig;
+    rx_cdr_lol_ch2_s <= rx_cdr_lol_ch2_sig;
+  tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
+  tx_full_clk_ch1 <= tx_full_clk_ch1_sig;
+  tx_full_clk_ch2 <= tx_full_clk_ch2_sig;
+  tx_full_clk_ch3 <= tx_full_clk_ch3_sig;
+
+-- pcs_quad instance
+PCSD_INST : PCSD
+--synopsys translate_off
+  generic map (CONFIG_FILE => USER_CONFIG_FILE,
+               QUAD_MODE => "SINGLE",
+               CH1_CDR_SRC => "REFCLK_CORE",
+               CH2_CDR_SRC => "REFCLK_CORE",
+               CH3_CDR_SRC => "REFCLK_EXT",
+               PLL_SRC  => "REFCLK_CORE"
+  )
+--synopsys translate_on
+port map  (
+  REFCLKP => fpsc_vlo,
+  REFCLKN => fpsc_vlo,
+
+----- CH0 -----
+  HDOUTP0 => open,
+  HDOUTN0 => open,
+  HDINP0 => fpsc_vlo,
+  HDINN0 => fpsc_vlo,
+  PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
+  PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
+  PCIE_RXPOLARITY_0 => fpsc_vlo,
+  PCIE_POWERDOWN_0_0 => fpsc_vlo,
+  PCIE_POWERDOWN_0_1 => fpsc_vlo,
+  PCIE_RXVALID_0 => open,
+  PCIE_PHYSTATUS_0 => open,
+  SCISELCH0 => fpsc_vlo,
+  SCIENCH0 => fpsc_vlo,
+  FF_RXI_CLK_0 => fpsc_vlo,
+  FF_TXI_CLK_0 => fpsc_vlo,
+  FF_EBRD_CLK_0 => fpsc_vlo,
+  FF_RX_F_CLK_0 => open,
+  FF_RX_H_CLK_0 => open,
+  FF_TX_F_CLK_0 => open,
+  FF_TX_H_CLK_0 => open,
+  FFC_CK_CORE_RX_0 => fpsc_vlo,
+  FF_TX_D_0_0 => fpsc_vlo,
+  FF_TX_D_0_1 => fpsc_vlo,
+  FF_TX_D_0_2 => fpsc_vlo,
+  FF_TX_D_0_3 => fpsc_vlo,
+  FF_TX_D_0_4 => fpsc_vlo,
+  FF_TX_D_0_5 => fpsc_vlo,
+  FF_TX_D_0_6 => fpsc_vlo,
+  FF_TX_D_0_7 => fpsc_vlo,
+  FF_TX_D_0_8 => fpsc_vlo,
+  FF_TX_D_0_9 => fpsc_vlo,
+  FF_TX_D_0_10 => fpsc_vlo,
+  FF_TX_D_0_11 => fpsc_vlo,
+  FF_TX_D_0_12 => fpsc_vlo,
+  FF_TX_D_0_13 => fpsc_vlo,
+  FF_TX_D_0_14 => fpsc_vlo,
+  FF_TX_D_0_15 => fpsc_vlo,
+  FF_TX_D_0_16 => fpsc_vlo,
+  FF_TX_D_0_17 => fpsc_vlo,
+  FF_TX_D_0_18 => fpsc_vlo,
+  FF_TX_D_0_19 => fpsc_vlo,
+  FF_TX_D_0_20 => fpsc_vlo,
+  FF_TX_D_0_21 => fpsc_vlo,
+  FF_TX_D_0_22 => fpsc_vlo,
+  FF_TX_D_0_23 => fpsc_vlo,
+  FF_RX_D_0_0 => open,
+  FF_RX_D_0_1 => open,
+  FF_RX_D_0_2 => open,
+  FF_RX_D_0_3 => open,
+  FF_RX_D_0_4 => open,
+  FF_RX_D_0_5 => open,
+  FF_RX_D_0_6 => open,
+  FF_RX_D_0_7 => open,
+  FF_RX_D_0_8 => open,
+  FF_RX_D_0_9 => open,
+  FF_RX_D_0_10 => open,
+  FF_RX_D_0_11 => open,
+  FF_RX_D_0_12 => open,
+  FF_RX_D_0_13 => open,
+  FF_RX_D_0_14 => open,
+  FF_RX_D_0_15 => open,
+  FF_RX_D_0_16 => open,
+  FF_RX_D_0_17 => open,
+  FF_RX_D_0_18 => open,
+  FF_RX_D_0_19 => open,
+  FF_RX_D_0_20 => open,
+  FF_RX_D_0_21 => open,
+  FF_RX_D_0_22 => open,
+  FF_RX_D_0_23 => open,
+
+  FFC_RRST_0 => fpsc_vlo,
+  FFC_SIGNAL_DETECT_0 => fpsc_vlo,
+  FFC_SB_PFIFO_LP_0 => fpsc_vlo,
+  FFC_PFIFO_CLR_0 => fpsc_vlo,
+  FFC_SB_INV_RX_0 => fpsc_vlo,
+  FFC_PCIE_CT_0 => fpsc_vlo,
+  FFC_PCI_DET_EN_0 => fpsc_vlo,
+  FFC_FB_LOOPBACK_0 => fpsc_vlo,
+  FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
+  FFC_EI_EN_0 => fpsc_vlo,
+  FFC_LANE_TX_RST_0 => fpsc_vlo,
+  FFC_TXPWDNB_0 => fpsc_vlo,
+  FFC_LANE_RX_RST_0 => fpsc_vlo,
+  FFC_RXPWDNB_0 => fpsc_vlo,
+  FFS_RLOS_LO_0 => open,
+  FFS_RLOS_HI_0 => open,
+  FFS_PCIE_CON_0 => open,
+  FFS_PCIE_DONE_0 => open,
+  FFS_LS_SYNC_STATUS_0 => open,
+  FFS_CC_OVERRUN_0 => open,
+  FFS_CC_UNDERRUN_0 => open,
+  FFS_SKP_ADDED_0 => open,
+  FFS_SKP_DELETED_0 => open,
+  FFS_RLOL_0 => open,
+  FFS_RXFBFIFO_ERROR_0 => open,
+  FFS_TXFBFIFO_ERROR_0 => open,
+  LDR_CORE2TX_0 => fpsc_vlo,
+  FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
+  LDR_RX2CORE_0 => open,
+  FFS_CDR_TRAIN_DONE_0 => open,
+  FFC_DIV11_MODE_TX_0 => fpsc_vlo,
+  FFC_RATE_MODE_TX_0 => fpsc_vlo,
+  FFC_DIV11_MODE_RX_0 => fpsc_vlo,
+  FFC_RATE_MODE_RX_0 => fpsc_vlo,
+
+----- CH1 -----
+  HDOUTP1 => hdoutp_ch1,
+  HDOUTN1 => hdoutn_ch1,
+  HDINP1 => hdinp_ch1,
+  HDINN1 => hdinn_ch1,
+  PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
+  PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
+  PCIE_RXPOLARITY_1 => fpsc_vlo,
+  PCIE_POWERDOWN_1_0 => fpsc_vlo,
+  PCIE_POWERDOWN_1_1 => fpsc_vlo,
+  PCIE_RXVALID_1 => open,
+  PCIE_PHYSTATUS_1 => open,
+  SCISELCH1 => sci_sel_ch1,
+  SCIENCH1 => fpsc_vhi,
+  FF_RXI_CLK_1 => rxiclk_ch1,
+  FF_TXI_CLK_1 => txiclk_ch1,
+  FF_EBRD_CLK_1 => fpsc_vlo,
+  FF_RX_F_CLK_1 => rx_full_clk_ch1,
+  FF_RX_H_CLK_1 => rx_half_clk_ch1,
+  FF_TX_F_CLK_1 => tx_full_clk_ch1_sig,
+  FF_TX_H_CLK_1 => tx_half_clk_ch1,
+  FFC_CK_CORE_RX_1 => fpga_rxrefclk_ch1,
+  FF_TX_D_1_0 => txdata_ch1(0),
+  FF_TX_D_1_1 => txdata_ch1(1),
+  FF_TX_D_1_2 => txdata_ch1(2),
+  FF_TX_D_1_3 => txdata_ch1(3),
+  FF_TX_D_1_4 => txdata_ch1(4),
+  FF_TX_D_1_5 => txdata_ch1(5),
+  FF_TX_D_1_6 => txdata_ch1(6),
+  FF_TX_D_1_7 => txdata_ch1(7),
+  FF_TX_D_1_8 => tx_k_ch1(0),
+  FF_TX_D_1_9 => tx_force_disp_ch1(0),
+  FF_TX_D_1_10 => tx_disp_sel_ch1(0),
+  FF_TX_D_1_11 => fpsc_vlo,
+  FF_TX_D_1_12 => txdata_ch1(8),
+  FF_TX_D_1_13 => txdata_ch1(9),
+  FF_TX_D_1_14 => txdata_ch1(10),
+  FF_TX_D_1_15 => txdata_ch1(11),
+  FF_TX_D_1_16 => txdata_ch1(12),
+  FF_TX_D_1_17 => txdata_ch1(13),
+  FF_TX_D_1_18 => txdata_ch1(14),
+  FF_TX_D_1_19 => txdata_ch1(15),
+  FF_TX_D_1_20 => tx_k_ch1(1),
+  FF_TX_D_1_21 => tx_force_disp_ch1(1),
+  FF_TX_D_1_22 => tx_disp_sel_ch1(1),
+  FF_TX_D_1_23 => fpsc_vlo,
+  FF_RX_D_1_0 => rxdata_ch1(0),
+  FF_RX_D_1_1 => rxdata_ch1(1),
+  FF_RX_D_1_2 => rxdata_ch1(2),
+  FF_RX_D_1_3 => rxdata_ch1(3),
+  FF_RX_D_1_4 => rxdata_ch1(4),
+  FF_RX_D_1_5 => rxdata_ch1(5),
+  FF_RX_D_1_6 => rxdata_ch1(6),
+  FF_RX_D_1_7 => rxdata_ch1(7),
+  FF_RX_D_1_8 => rx_k_ch1(0),
+  FF_RX_D_1_9 => rx_disp_err_ch1(0),
+  FF_RX_D_1_10 => rx_cv_err_ch1(0),
+  FF_RX_D_1_11 => open,
+  FF_RX_D_1_12 => rxdata_ch1(8),
+  FF_RX_D_1_13 => rxdata_ch1(9),
+  FF_RX_D_1_14 => rxdata_ch1(10),
+  FF_RX_D_1_15 => rxdata_ch1(11),
+  FF_RX_D_1_16 => rxdata_ch1(12),
+  FF_RX_D_1_17 => rxdata_ch1(13),
+  FF_RX_D_1_18 => rxdata_ch1(14),
+  FF_RX_D_1_19 => rxdata_ch1(15),
+  FF_RX_D_1_20 => rx_k_ch1(1),
+  FF_RX_D_1_21 => rx_disp_err_ch1(1),
+  FF_RX_D_1_22 => rx_cv_err_ch1(1),
+  FF_RX_D_1_23 => open,
+
+  FFC_RRST_1 => rx_serdes_rst_ch1_c,
+  FFC_SIGNAL_DETECT_1 => fpsc_vlo,
+  FFC_SB_PFIFO_LP_1 => sb_felb_ch1_c,
+  FFC_PFIFO_CLR_1 => sb_felb_rst_ch1_c,
+  FFC_SB_INV_RX_1 => fpsc_vlo,
+  FFC_PCIE_CT_1 => fpsc_vlo,
+  FFC_PCI_DET_EN_1 => fpsc_vlo,
+  FFC_FB_LOOPBACK_1 => fpsc_vlo,
+  FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
+  FFC_EI_EN_1 => fpsc_vlo,
+  FFC_LANE_TX_RST_1 => tx_pcs_rst_ch1_c,
+  FFC_TXPWDNB_1 => tx_pwrup_ch1_c,
+  FFC_LANE_RX_RST_1 => rx_pcs_rst_ch1_c,
+  FFC_RXPWDNB_1 => rx_pwrup_ch1_c,
+  FFS_RLOS_LO_1 => rx_los_low_ch1_sig,
+  FFS_RLOS_HI_1 => open,
+  FFS_PCIE_CON_1 => open,
+  FFS_PCIE_DONE_1 => open,
+  FFS_LS_SYNC_STATUS_1 => lsm_status_ch1_s,
+  FFS_CC_OVERRUN_1 => open,
+  FFS_CC_UNDERRUN_1 => open,
+  FFS_SKP_ADDED_1 => open,
+  FFS_SKP_DELETED_1 => open,
+  FFS_RLOL_1 => rx_cdr_lol_ch1_sig,
+  FFS_RXFBFIFO_ERROR_1 => open,
+  FFS_TXFBFIFO_ERROR_1 => open,
+  LDR_CORE2TX_1 => fpsc_vlo,
+  FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
+  LDR_RX2CORE_1 => open,
+  FFS_CDR_TRAIN_DONE_1 => open,
+  FFC_DIV11_MODE_TX_1 => fpsc_vlo,
+  FFC_RATE_MODE_TX_1 => tx_div2_mode_ch1_c,
+  FFC_DIV11_MODE_RX_1 => fpsc_vlo,
+  FFC_RATE_MODE_RX_1 => rx_div2_mode_ch1_c,
+
+----- CH2 -----
+  HDOUTP2 => hdoutp_ch2,
+  HDOUTN2 => hdoutn_ch2,
+  HDINP2 => hdinp_ch2,
+  HDINN2 => hdinn_ch2,
+  PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
+  PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
+  PCIE_RXPOLARITY_2 => fpsc_vlo,
+  PCIE_POWERDOWN_2_0 => fpsc_vlo,
+  PCIE_POWERDOWN_2_1 => fpsc_vlo,
+  PCIE_RXVALID_2 => open,
+  PCIE_PHYSTATUS_2 => open,
+  SCISELCH2 => sci_sel_ch2,
+  SCIENCH2 => fpsc_vhi,
+  FF_RXI_CLK_2 => rxiclk_ch2,
+  FF_TXI_CLK_2 => txiclk_ch2,
+  FF_EBRD_CLK_2 => fpsc_vlo,
+  FF_RX_F_CLK_2 => rx_full_clk_ch2,
+  FF_RX_H_CLK_2 => rx_half_clk_ch2,
+  FF_TX_F_CLK_2 => tx_full_clk_ch2_sig,
+  FF_TX_H_CLK_2 => tx_half_clk_ch2,
+  FFC_CK_CORE_RX_2 => fpga_rxrefclk_ch2,
+  FF_TX_D_2_0 => txdata_ch2(0),
+  FF_TX_D_2_1 => txdata_ch2(1),
+  FF_TX_D_2_2 => txdata_ch2(2),
+  FF_TX_D_2_3 => txdata_ch2(3),
+  FF_TX_D_2_4 => txdata_ch2(4),
+  FF_TX_D_2_5 => txdata_ch2(5),
+  FF_TX_D_2_6 => txdata_ch2(6),
+  FF_TX_D_2_7 => txdata_ch2(7),
+  FF_TX_D_2_8 => tx_k_ch2,
+  FF_TX_D_2_9 => tx_force_disp_ch2,
+  FF_TX_D_2_10 => tx_disp_sel_ch2,
+  FF_TX_D_2_11 => fpsc_vlo,
+  FF_TX_D_2_12 => fpsc_vlo,
+  FF_TX_D_2_13 => fpsc_vlo,
+  FF_TX_D_2_14 => fpsc_vlo,
+  FF_TX_D_2_15 => fpsc_vlo,
+  FF_TX_D_2_16 => fpsc_vlo,
+  FF_TX_D_2_17 => fpsc_vlo,
+  FF_TX_D_2_18 => fpsc_vlo,
+  FF_TX_D_2_19 => fpsc_vlo,
+  FF_TX_D_2_20 => fpsc_vlo,
+  FF_TX_D_2_21 => fpsc_vlo,
+  FF_TX_D_2_22 => fpsc_vlo,
+  FF_TX_D_2_23 => fpsc_vlo,
+  FF_RX_D_2_0 => rxdata_ch2(0),
+  FF_RX_D_2_1 => rxdata_ch2(1),
+  FF_RX_D_2_2 => rxdata_ch2(2),
+  FF_RX_D_2_3 => rxdata_ch2(3),
+  FF_RX_D_2_4 => rxdata_ch2(4),
+  FF_RX_D_2_5 => rxdata_ch2(5),
+  FF_RX_D_2_6 => rxdata_ch2(6),
+  FF_RX_D_2_7 => rxdata_ch2(7),
+  FF_RX_D_2_8 => rx_k_ch2,
+  FF_RX_D_2_9 => rx_disp_err_ch2,
+  FF_RX_D_2_10 => rx_cv_err_ch2,
+  FF_RX_D_2_11 => open,
+  FF_RX_D_2_12 => open,
+  FF_RX_D_2_13 => open,
+  FF_RX_D_2_14 => open,
+  FF_RX_D_2_15 => open,
+  FF_RX_D_2_16 => open,
+  FF_RX_D_2_17 => open,
+  FF_RX_D_2_18 => open,
+  FF_RX_D_2_19 => open,
+  FF_RX_D_2_20 => open,
+  FF_RX_D_2_21 => open,
+  FF_RX_D_2_22 => open,
+  FF_RX_D_2_23 => open,
+
+  FFC_RRST_2 => rx_serdes_rst_ch2_c,
+  FFC_SIGNAL_DETECT_2 => fpsc_vlo,
+  FFC_SB_PFIFO_LP_2 => sb_felb_ch2_c,
+  FFC_PFIFO_CLR_2 => sb_felb_rst_ch2_c,
+  FFC_SB_INV_RX_2 => fpsc_vlo,
+  FFC_PCIE_CT_2 => fpsc_vlo,
+  FFC_PCI_DET_EN_2 => fpsc_vlo,
+  FFC_FB_LOOPBACK_2 => fpsc_vlo,
+  FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
+  FFC_EI_EN_2 => fpsc_vlo,
+  FFC_LANE_TX_RST_2 => tx_pcs_rst_ch2_c,
+  FFC_TXPWDNB_2 => tx_pwrup_ch2_c,
+  FFC_LANE_RX_RST_2 => rx_pcs_rst_ch2_c,
+  FFC_RXPWDNB_2 => rx_pwrup_ch2_c,
+  FFS_RLOS_LO_2 => rx_los_low_ch2_sig,
+  FFS_RLOS_HI_2 => open,
+  FFS_PCIE_CON_2 => open,
+  FFS_PCIE_DONE_2 => open,
+  FFS_LS_SYNC_STATUS_2 => lsm_status_ch2_s,
+  FFS_CC_OVERRUN_2 => open,
+  FFS_CC_UNDERRUN_2 => open,
+  FFS_SKP_ADDED_2 => open,
+  FFS_SKP_DELETED_2 => open,
+  FFS_RLOL_2 => rx_cdr_lol_ch2_sig,
+  FFS_RXFBFIFO_ERROR_2 => open,
+  FFS_TXFBFIFO_ERROR_2 => open,
+  LDR_CORE2TX_2 => fpsc_vlo,
+  FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
+  LDR_RX2CORE_2 => open,
+  FFS_CDR_TRAIN_DONE_2 => open,
+  FFC_DIV11_MODE_TX_2 => fpsc_vlo,
+  FFC_RATE_MODE_TX_2 => tx_div2_mode_ch2_c,
+  FFC_DIV11_MODE_RX_2 => fpsc_vlo,
+  FFC_RATE_MODE_RX_2 => rx_div2_mode_ch2_c,
+
+----- CH3 -----
+  HDOUTP3 => hdoutp_ch3,
+  HDOUTN3 => hdoutn_ch3,
+  HDINP3 => fpsc_vlo,
+  HDINN3 => fpsc_vlo,
+  PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
+  PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
+  PCIE_RXPOLARITY_3 => fpsc_vlo,
+  PCIE_POWERDOWN_3_0 => fpsc_vlo,
+  PCIE_POWERDOWN_3_1 => fpsc_vlo,
+  PCIE_RXVALID_3 => open,
+  PCIE_PHYSTATUS_3 => open,
+  SCISELCH3 => sci_sel_ch3,
+  SCIENCH3 => fpsc_vhi,
+  FF_RXI_CLK_3 => fpsc_vlo,
+  FF_TXI_CLK_3 => txiclk_ch3,
+  FF_EBRD_CLK_3 => fpsc_vlo,
+  FF_RX_F_CLK_3 => open,
+  FF_RX_H_CLK_3 => open,
+  FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,
+  FF_TX_H_CLK_3 => tx_half_clk_ch3,
+  FFC_CK_CORE_RX_3 => fpsc_vlo,
+  FF_TX_D_3_0 => txdata_ch3(0),
+  FF_TX_D_3_1 => txdata_ch3(1),
+  FF_TX_D_3_2 => txdata_ch3(2),
+  FF_TX_D_3_3 => txdata_ch3(3),
+  FF_TX_D_3_4 => txdata_ch3(4),
+  FF_TX_D_3_5 => txdata_ch3(5),
+  FF_TX_D_3_6 => txdata_ch3(6),
+  FF_TX_D_3_7 => txdata_ch3(7),
+  FF_TX_D_3_8 => tx_k_ch3,
+  FF_TX_D_3_9 => tx_force_disp_ch3,
+  FF_TX_D_3_10 => tx_disp_sel_ch3,
+  FF_TX_D_3_11 => fpsc_vlo,
+  FF_TX_D_3_12 => fpsc_vlo,
+  FF_TX_D_3_13 => fpsc_vlo,
+  FF_TX_D_3_14 => fpsc_vlo,
+  FF_TX_D_3_15 => fpsc_vlo,
+  FF_TX_D_3_16 => fpsc_vlo,
+  FF_TX_D_3_17 => fpsc_vlo,
+  FF_TX_D_3_18 => fpsc_vlo,
+  FF_TX_D_3_19 => fpsc_vlo,
+  FF_TX_D_3_20 => fpsc_vlo,
+  FF_TX_D_3_21 => fpsc_vlo,
+  FF_TX_D_3_22 => fpsc_vlo,
+  FF_TX_D_3_23 => fpsc_vlo,
+  FF_RX_D_3_0 => open,
+  FF_RX_D_3_1 => open,
+  FF_RX_D_3_2 => open,
+  FF_RX_D_3_3 => open,
+  FF_RX_D_3_4 => open,
+  FF_RX_D_3_5 => open,
+  FF_RX_D_3_6 => open,
+  FF_RX_D_3_7 => open,
+  FF_RX_D_3_8 => open,
+  FF_RX_D_3_9 => open,
+  FF_RX_D_3_10 => open,
+  FF_RX_D_3_11 => open,
+  FF_RX_D_3_12 => open,
+  FF_RX_D_3_13 => open,
+  FF_RX_D_3_14 => open,
+  FF_RX_D_3_15 => open,
+  FF_RX_D_3_16 => open,
+  FF_RX_D_3_17 => open,
+  FF_RX_D_3_18 => open,
+  FF_RX_D_3_19 => open,
+  FF_RX_D_3_20 => open,
+  FF_RX_D_3_21 => open,
+  FF_RX_D_3_22 => open,
+  FF_RX_D_3_23 => open,
+
+  FFC_RRST_3 => fpsc_vlo,
+  FFC_SIGNAL_DETECT_3 => fpsc_vlo,
+  FFC_SB_PFIFO_LP_3 => fpsc_vlo,
+  FFC_PFIFO_CLR_3 => fpsc_vlo,
+  FFC_SB_INV_RX_3 => fpsc_vlo,
+  FFC_PCIE_CT_3 => fpsc_vlo,
+  FFC_PCI_DET_EN_3 => fpsc_vlo,
+  FFC_FB_LOOPBACK_3 => fpsc_vlo,
+  FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
+  FFC_EI_EN_3 => fpsc_vlo,
+  FFC_LANE_TX_RST_3 => tx_pcs_rst_ch3_c,
+  FFC_TXPWDNB_3 => tx_pwrup_ch3_c,
+  FFC_LANE_RX_RST_3 => fpsc_vlo,
+  FFC_RXPWDNB_3 => fpsc_vlo,
+  FFS_RLOS_LO_3 => open,
+  FFS_RLOS_HI_3 => open,
+  FFS_PCIE_CON_3 => open,
+  FFS_PCIE_DONE_3 => open,
+  FFS_LS_SYNC_STATUS_3 => open,
+  FFS_CC_OVERRUN_3 => open,
+  FFS_CC_UNDERRUN_3 => open,
+  FFS_SKP_ADDED_3 => open,
+  FFS_SKP_DELETED_3 => open,
+  FFS_RLOL_3 => open,
+  FFS_RXFBFIFO_ERROR_3 => open,
+  FFS_TXFBFIFO_ERROR_3 => open,
+  LDR_CORE2TX_3 => fpsc_vlo,
+  FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
+  LDR_RX2CORE_3 => open,
+  FFS_CDR_TRAIN_DONE_3 => open,
+  FFC_DIV11_MODE_TX_3 => fpsc_vlo,
+  FFC_RATE_MODE_TX_3 => tx_div2_mode_ch3_c,
+  FFC_DIV11_MODE_RX_3 => fpsc_vlo,
+  FFC_RATE_MODE_RX_3 => fpsc_vlo,
+
+----- Auxilliary ----
+  SCIWDATA7 => sci_wrdata(7),
+  SCIWDATA6 => sci_wrdata(6),
+  SCIWDATA5 => sci_wrdata(5),
+  SCIWDATA4 => sci_wrdata(4),
+  SCIWDATA3 => sci_wrdata(3),
+  SCIWDATA2 => sci_wrdata(2),
+  SCIWDATA1 => sci_wrdata(1),
+  SCIWDATA0 => sci_wrdata(0),
+  SCIADDR5 => sci_addr(5),
+  SCIADDR4 => sci_addr(4),
+  SCIADDR3 => sci_addr(3),
+  SCIADDR2 => sci_addr(2),
+  SCIADDR1 => sci_addr(1),
+  SCIADDR0 => sci_addr(0),
+  SCIRDATA7 => sci_rddata(7),
+  SCIRDATA6 => sci_rddata(6),
+  SCIRDATA5 => sci_rddata(5),
+  SCIRDATA4 => sci_rddata(4),
+  SCIRDATA3 => sci_rddata(3),
+  SCIRDATA2 => sci_rddata(2),
+  SCIRDATA1 => sci_rddata(1),
+  SCIRDATA0 => sci_rddata(0),
+  SCIENAUX => fpsc_vhi,
+  SCISELAUX => sci_sel_quad,
+  SCIRD => sci_rd,
+  SCIWSTN => sci_wrn,
+  CYAWSTN => fpsc_vlo,
+  SCIINT => open,
+  FFC_CK_CORE_TX => fpga_txrefclk,
+  FFC_MACRO_RST => serdes_rst_qd_c,
+  FFC_QUAD_RST => rst_qd_c,
+  FFC_TRST => tx_serdes_rst_c,
+  FFS_PLOL => tx_pll_lol_qd_sig,
+  FFC_SYNC_TOGGLE => tx_sync_qd_c,
+  REFCK2CORE => refclk2fpga_sig,
+  CIN0 => fpsc_vlo,
+  CIN1 => fpsc_vlo,
+  CIN2 => fpsc_vlo,
+  CIN3 => fpsc_vlo,
+  CIN4 => fpsc_vlo,
+  CIN5 => fpsc_vlo,
+  CIN6 => fpsc_vlo,
+  CIN7 => fpsc_vlo,
+  CIN8 => fpsc_vlo,
+  CIN9 => fpsc_vlo,
+  CIN10 => fpsc_vlo,
+  CIN11 => fpsc_vlo,
+  COUT0 => open,
+  COUT1 => open,
+  COUT2 => open,
+  COUT3 => open,
+  COUT4 => open,
+  COUT5 => open,
+  COUT6 => open,
+  COUT7 => open,
+  COUT8 => open,
+  COUT9 => open,
+  COUT10 => open,
+  COUT11 => open,
+  COUT12 => open,
+  COUT13 => open,
+  COUT14 => open,
+  COUT15 => open,
+  COUT16 => open,
+  COUT17 => open,
+  COUT18 => open,
+  COUT19 => open,
+  REFCLK_FROM_NQ => refclk_from_nq,
+  REFCLK_TO_NQ => open);
+
+                                                                                              
+                                                                                              
+                                                                                              
+--synopsys translate_off
+file_read : PROCESS
+VARIABLE open_status : file_open_status;
+FILE config : text;
+BEGIN
+   file_open (open_status, config, USER_CONFIG_FILE, read_mode);
+   IF (open_status = name_error) THEN
+      report "Auto configuration file for PCS module not found.  PCS internal configuration registers will not be initialized correctly during simulation!"
+      severity ERROR;
+   END IF;
+   wait;
+END PROCESS;
+--synopsys translate_on
+end sfp_1_2sync_3_200_int_arch ;
diff --git a/data_concentrator/sources/lattice/ecp3/sfp_1_3_200_int.ipx b/data_concentrator/sources/lattice/ecp3/sfp_1_3_200_int.ipx
new file mode 100644
index 0000000..21a7516
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/sfp_1_3_200_int.ipx
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="sfp_1_3_200_int" module="sfp_1_3_200_int" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 06 25 09:30:34.887" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="sfp_1_3_200_int.lpc" type="lpc" modified="2014 06 25 09:30:30.819"/>
+		<File name="sfp_1_3_200_int.pp" type="pp" modified="2014 06 25 09:30:30.821"/>
+		<File name="sfp_1_3_200_int.sym" type="sym" modified="2014 06 25 09:30:31.064"/>
+		<File name="sfp_1_3_200_int.txt" type="pcs_module" modified="2014 06 25 09:30:30.841"/>
+		<File name="sfp_1_3_200_int.vhd" type="top_level_vhdl" modified="2014 06 24 10:41:47.249"/>
+  </Package>
+</DiamondModule>
diff --git a/data_concentrator/sources/lattice/ecp3/sfp_1_3_200_int.lpc b/data_concentrator/sources/lattice/ecp3/sfp_1_3_200_int.lpc
new file mode 100644
index 0000000..e720afe
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/sfp_1_3_200_int.lpc
@@ -0,0 +1,258 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PCS
+CoreRevision=8.1
+ModuleName=sfp_1_3_200_int
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=06/25/2014
+Time=09:30:30
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+_mode0=DISABLED
+_mode1=RXTX
+_mode2=DISABLED
+_mode3=TXONLY
+_protocol0=G8B10B
+_protocol1=G8B10B
+_protocol2=G8B10B
+_protocol3=G8B10B
+_ldr0=DISABLED
+_ldr1=DISABLED
+_ldr2=DISABLED
+_ldr3=DISABLED
+_datarange=2
+_pll_txsrc=INTERNAL
+_refclk_mult=10X
+_refclk_rate=200
+_tx_protocol0=DISABLED
+_tx_protocol1=G8B10B
+_tx_protocol2=DISABLED
+_tx_protocol3=G8B10B
+_tx_data_rate0=FULL
+_tx_data_rate1=FULL
+_tx_data_rate2=FULL
+_tx_data_rate3=DIV2
+_tx_data_width0=8
+_tx_data_width1=16
+_tx_data_width2=8
+_tx_data_width3=8
+_tx_fifo0=ENABLED
+_tx_fifo1=ENABLED
+_tx_fifo2=ENABLED
+_tx_fifo3=ENABLED
+_tx_ficlk_rate0=200
+_tx_ficlk_rate1=100
+_tx_ficlk_rate2=200
+_tx_ficlk_rate3=100
+_pll_rxsrc0=EXTERNAL
+_pll_rxsrc1=INTERNAL
+_pll_rxsrc2=EXTERNAL
+_pll_rxsrc3=INTERNAL
+Multiplier0=
+Multiplier1=
+Multiplier2=
+Multiplier3=
+_rx_datarange0=2.5
+_rx_datarange1=2
+_rx_datarange2=2.5
+_rx_datarange3=2
+_rx_protocol0=DISABLED
+_rx_protocol1=G8B10B
+_rx_protocol2=DISABLED
+_rx_protocol3=DISABLED
+_rx_data_rate0=FULL
+_rx_data_rate1=FULL
+_rx_data_rate2=FULL
+_rx_data_rate3=FULL
+_rxrefclk_rate0=250.0
+_rxrefclk_rate1=200
+_rxrefclk_rate2=250.0
+_rxrefclk_rate3=200
+_rx_data_width0=8
+_rx_data_width1=16
+_rx_data_width2=8
+_rx_data_width3=16
+_rx_fifo0=ENABLED
+_rx_fifo1=ENABLED
+_rx_fifo2=ENABLED
+_rx_fifo3=DISABLED
+_rx_ficlk_rate0=250.0
+_rx_ficlk_rate1=100
+_rx_ficlk_rate2=250.0
+_rx_ficlk_rate3=100
+_tdrv_ch0=0
+_tdrv_ch1=0
+_tdrv_ch2=0
+_tdrv_ch3=0
+_tx_pre0=DISABLED
+_tx_pre1=DISABLED
+_tx_pre2=DISABLED
+_tx_pre3=DISABLED
+_rterm_tx0=50
+_rterm_tx1=50
+_rterm_tx2=50
+_rterm_tx3=50
+_rx_eq0=DISABLED
+_rx_eq1=DISABLED
+_rx_eq2=DISABLED
+_rx_eq3=DISABLED
+_rterm_rx0=50
+_rterm_rx1=50
+_rterm_rx2=50
+_rterm_rx3=50
+_rx_dcc0=AC
+_rx_dcc1=DC
+_rx_dcc2=AC
+_rx_dcc3=DC
+_los_threshold_mode0=LOS_E
+_los_threshold_mode1=LOS_E
+_los_threshold_mode2=LOS_E
+_los_threshold_mode3=LOS_E
+_los_threshold_lo0=2
+_los_threshold_lo1=2
+_los_threshold_lo2=2
+_los_threshold_lo3=2
+_los_threshold_hi0=7
+_los_threshold_hi1=7
+_los_threshold_hi2=7
+_los_threshold_hi3=7
+_pll_term=50
+_pll_dcc=AC
+_pll_lol_set=0
+_tx_sb0=DISABLED
+_tx_sb1=DISABLED
+_tx_sb2=DISABLED
+_tx_sb3=DISABLED
+_tx_8b10b0=ENABLED
+_tx_8b10b1=ENABLED
+_tx_8b10b2=ENABLED
+_tx_8b10b3=ENABLED
+_rx_sb0=DISABLED
+_rx_sb1=DISABLED
+_rx_sb2=DISABLED
+_rx_sb3=DISABLED
+_ird0=DISABLED
+_ird1=DISABLED
+_ird2=DISABLED
+_ird3=DISABLED
+_rx_8b10b0=ENABLED
+_rx_8b10b1=ENABLED
+_rx_8b10b2=ENABLED
+_rx_8b10b3=ENABLED
+_rxwa0=ENABLED
+_rxwa1=ENABLED
+_rxwa2=ENABLED
+_rxwa3=ENABLED
+_ilsm0=ENABLED
+_ilsm1=ENABLED
+_ilsm2=ENABLED
+_ilsm3=ENABLED
+_scomma0=K28P157
+_scomma1=K28P157
+_scomma2=K28P157
+_scomma3=K28P157
+_comma_a0=1100000101
+_comma_a1=1100000101
+_comma_a2=1100000101
+_comma_a3=1100000101
+_comma_b0=0011111010
+_comma_b1=0011111010
+_comma_b2=0011111010
+_comma_b3=0011111010
+_comma_m0=1111111100
+_comma_m1=1111111100
+_comma_m2=1111111100
+_comma_m3=1111111100
+_ctc0=DISABLED
+_ctc1=DISABLED
+_ctc2=DISABLED
+_ctc3=DISABLED
+_cc_match_mode0=1
+_cc_match_mode1=1
+_cc_match_mode2=1
+_cc_match_mode3=1
+_k00=00
+_k01=01
+_k02=00
+_k03=01
+_k10=00
+_k11=00
+_k12=00
+_k13=00
+_k20=01
+_k21=01
+_k22=01
+_k23=01
+_k30=01
+_k31=01
+_k32=01
+_k33=01
+_byten00=00000000
+_byten01=00011100
+_byten02=00000000
+_byten03=00011100
+_byten10=00000000
+_byten11=00000000
+_byten12=00000000
+_byten13=00000000
+_byten20=00011100
+_byten21=00011100
+_byten22=00011100
+_byten23=00011100
+_byten30=00011100
+_byten31=00011100
+_byten32=00011100
+_byten33=00011100
+_cc_min_ipg0=3
+_cc_min_ipg1=3
+_cc_min_ipg2=3
+_cc_min_ipg3=3
+_cchmark=9
+_cclmark=7
+_loopback=DISABLED
+_lbtype0=DISABLED
+_lbtype1=DISABLED
+_lbtype2=DISABLED
+_lbtype3=DISABLED
+_teidle_ch0=DISABLED
+_teidle_ch1=DISABLED
+_teidle_ch2=DISABLED
+_teidle_ch3=DISABLED
+_rst_gen=ENABLED
+_rx_los_port0=Internal
+_rx_los_port1=Internal
+_rx_los_port2=Internal
+_rx_los_port3=Internal
+_sci_ports=ENABLED
+_sci_int_port=DISABLED
+_refck2core=ENABLED
+Regen=auto
+PAR1=0
+PARTrace1=0
+PAR3=0
+PARTrace3=0
+
+[FilesGenerated]
+sfp_1_3_200_int.pp=pp
+sfp_1_3_200_int.tft=tft
+sfp_1_3_200_int.txt=pcs_module
+sfp_1_3_200_int.sym=sym
diff --git a/data_concentrator/sources/lattice/ecp3/sfp_1_3_200_int.vhd b/data_concentrator/sources/lattice/ecp3/sfp_1_3_200_int.vhd
new file mode 100644
index 0000000..5563ff3
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/sfp_1_3_200_int.vhd
@@ -0,0 +1,3180 @@
+
+                                                                                                         
+
+--synopsys translate_off
+
+library pcsd_work;
+use pcsd_work.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity PCSD is
+GENERIC(
+  CONFIG_FILE : String;
+  QUAD_MODE : String;
+  CH0_CDR_SRC   : String := "REFCLK_EXT";
+  CH1_CDR_SRC   : String := "REFCLK_EXT";
+  CH2_CDR_SRC   : String := "REFCLK_EXT";
+  CH3_CDR_SRC   : String := "REFCLK_EXT";
+  PLL_SRC   : String
+--  CONFIG_FILE : String  := "sfp_1_3_200_int.txt";
+--  QUAD_MODE : String := "SINGLE";
+--  CH0_CDR_SRC   : String := "REFCLK_EXT";
+--  CH1_CDR_SRC   : String := "REFCLK_CORE";
+--  CH2_CDR_SRC   : String := "REFCLK_EXT";
+--  CH3_CDR_SRC   : String := "REFCLK_CORE";
+--  PLL_SRC   : String := "REFCLK_CORE"
+  );
+port (
+  HDINN0             : in std_logic;
+  HDINN1             : in std_logic;
+  HDINN2             : in std_logic;
+  HDINN3             : in std_logic;
+  HDINP0             : in std_logic;
+  HDINP1             : in std_logic;
+  HDINP2             : in std_logic;
+  HDINP3             : in std_logic;
+  REFCLKN             : in std_logic;
+  REFCLKP             : in std_logic;
+  CIN0             : in std_logic;
+  CIN1             : in std_logic;
+  CIN2             : in std_logic;
+  CIN3             : in std_logic;
+  CIN4             : in std_logic;
+  CIN5             : in std_logic;
+  CIN6             : in std_logic;
+  CIN7             : in std_logic;
+  CIN8             : in std_logic;
+  CIN9             : in std_logic;
+  CIN10             : in std_logic;
+  CIN11             : in std_logic;
+  CYAWSTN             : in std_logic;
+  FF_EBRD_CLK_0             : in std_logic;
+  FF_EBRD_CLK_1             : in std_logic;
+  FF_EBRD_CLK_2             : in std_logic;
+  FF_EBRD_CLK_3             : in std_logic;
+  FF_RXI_CLK_0             : in std_logic;
+  FF_RXI_CLK_1             : in std_logic;
+  FF_RXI_CLK_2             : in std_logic;
+  FF_RXI_CLK_3             : in std_logic;
+  FF_TX_D_0_0             : in std_logic;
+  FF_TX_D_0_1             : in std_logic;
+  FF_TX_D_0_2             : in std_logic;
+  FF_TX_D_0_3             : in std_logic;
+  FF_TX_D_0_4             : in std_logic;
+  FF_TX_D_0_5             : in std_logic;
+  FF_TX_D_0_6             : in std_logic;
+  FF_TX_D_0_7             : in std_logic;
+  FF_TX_D_0_8             : in std_logic;
+  FF_TX_D_0_9             : in std_logic;
+  FF_TX_D_0_10             : in std_logic;
+  FF_TX_D_0_11             : in std_logic;
+  FF_TX_D_0_12             : in std_logic;
+  FF_TX_D_0_13             : in std_logic;
+  FF_TX_D_0_14             : in std_logic;
+  FF_TX_D_0_15             : in std_logic;
+  FF_TX_D_0_16             : in std_logic;
+  FF_TX_D_0_17             : in std_logic;
+  FF_TX_D_0_18             : in std_logic;
+  FF_TX_D_0_19             : in std_logic;
+  FF_TX_D_0_20             : in std_logic;
+  FF_TX_D_0_21             : in std_logic;
+  FF_TX_D_0_22             : in std_logic;
+  FF_TX_D_0_23             : in std_logic;
+  FF_TX_D_1_0             : in std_logic;
+  FF_TX_D_1_1             : in std_logic;
+  FF_TX_D_1_2             : in std_logic;
+  FF_TX_D_1_3             : in std_logic;
+  FF_TX_D_1_4             : in std_logic;
+  FF_TX_D_1_5             : in std_logic;
+  FF_TX_D_1_6             : in std_logic;
+  FF_TX_D_1_7             : in std_logic;
+  FF_TX_D_1_8             : in std_logic;
+  FF_TX_D_1_9             : in std_logic;
+  FF_TX_D_1_10             : in std_logic;
+  FF_TX_D_1_11             : in std_logic;
+  FF_TX_D_1_12             : in std_logic;
+  FF_TX_D_1_13             : in std_logic;
+  FF_TX_D_1_14             : in std_logic;
+  FF_TX_D_1_15             : in std_logic;
+  FF_TX_D_1_16             : in std_logic;
+  FF_TX_D_1_17             : in std_logic;
+  FF_TX_D_1_18             : in std_logic;
+  FF_TX_D_1_19             : in std_logic;
+  FF_TX_D_1_20             : in std_logic;
+  FF_TX_D_1_21             : in std_logic;
+  FF_TX_D_1_22             : in std_logic;
+  FF_TX_D_1_23             : in std_logic;
+  FF_TX_D_2_0             : in std_logic;
+  FF_TX_D_2_1             : in std_logic;
+  FF_TX_D_2_2             : in std_logic;
+  FF_TX_D_2_3             : in std_logic;
+  FF_TX_D_2_4             : in std_logic;
+  FF_TX_D_2_5             : in std_logic;
+  FF_TX_D_2_6             : in std_logic;
+  FF_TX_D_2_7             : in std_logic;
+  FF_TX_D_2_8             : in std_logic;
+  FF_TX_D_2_9             : in std_logic;
+  FF_TX_D_2_10             : in std_logic;
+  FF_TX_D_2_11             : in std_logic;
+  FF_TX_D_2_12             : in std_logic;
+  FF_TX_D_2_13             : in std_logic;
+  FF_TX_D_2_14             : in std_logic;
+  FF_TX_D_2_15             : in std_logic;
+  FF_TX_D_2_16             : in std_logic;
+  FF_TX_D_2_17             : in std_logic;
+  FF_TX_D_2_18             : in std_logic;
+  FF_TX_D_2_19             : in std_logic;
+  FF_TX_D_2_20             : in std_logic;
+  FF_TX_D_2_21             : in std_logic;
+  FF_TX_D_2_22             : in std_logic;
+  FF_TX_D_2_23             : in std_logic;
+  FF_TX_D_3_0             : in std_logic;
+  FF_TX_D_3_1             : in std_logic;
+  FF_TX_D_3_2             : in std_logic;
+  FF_TX_D_3_3             : in std_logic;
+  FF_TX_D_3_4             : in std_logic;
+  FF_TX_D_3_5             : in std_logic;
+  FF_TX_D_3_6             : in std_logic;
+  FF_TX_D_3_7             : in std_logic;
+  FF_TX_D_3_8             : in std_logic;
+  FF_TX_D_3_9             : in std_logic;
+  FF_TX_D_3_10             : in std_logic;
+  FF_TX_D_3_11             : in std_logic;
+  FF_TX_D_3_12             : in std_logic;
+  FF_TX_D_3_13             : in std_logic;
+  FF_TX_D_3_14             : in std_logic;
+  FF_TX_D_3_15             : in std_logic;
+  FF_TX_D_3_16             : in std_logic;
+  FF_TX_D_3_17             : in std_logic;
+  FF_TX_D_3_18             : in std_logic;
+  FF_TX_D_3_19             : in std_logic;
+  FF_TX_D_3_20             : in std_logic;
+  FF_TX_D_3_21             : in std_logic;
+  FF_TX_D_3_22             : in std_logic;
+  FF_TX_D_3_23             : in std_logic;
+  FF_TXI_CLK_0             : in std_logic;
+  FF_TXI_CLK_1             : in std_logic;
+  FF_TXI_CLK_2             : in std_logic;
+  FF_TXI_CLK_3             : in std_logic;
+  FFC_CK_CORE_RX_0         : in std_logic;
+  FFC_CK_CORE_RX_1         : in std_logic;
+  FFC_CK_CORE_RX_2         : in std_logic;
+  FFC_CK_CORE_RX_3         : in std_logic;
+  FFC_CK_CORE_TX           : in std_logic;
+  FFC_EI_EN_0             : in std_logic;
+  FFC_EI_EN_1             : in std_logic;
+  FFC_EI_EN_2             : in std_logic;
+  FFC_EI_EN_3             : in std_logic;
+  FFC_ENABLE_CGALIGN_0             : in std_logic;
+  FFC_ENABLE_CGALIGN_1             : in std_logic;
+  FFC_ENABLE_CGALIGN_2             : in std_logic;
+  FFC_ENABLE_CGALIGN_3             : in std_logic;
+  FFC_FB_LOOPBACK_0             : in std_logic;
+  FFC_FB_LOOPBACK_1             : in std_logic;
+  FFC_FB_LOOPBACK_2             : in std_logic;
+  FFC_FB_LOOPBACK_3             : in std_logic;
+  FFC_LANE_RX_RST_0             : in std_logic;
+  FFC_LANE_RX_RST_1             : in std_logic;
+  FFC_LANE_RX_RST_2             : in std_logic;
+  FFC_LANE_RX_RST_3             : in std_logic;
+  FFC_LANE_TX_RST_0             : in std_logic;
+  FFC_LANE_TX_RST_1             : in std_logic;
+  FFC_LANE_TX_RST_2             : in std_logic;
+  FFC_LANE_TX_RST_3             : in std_logic;
+  FFC_MACRO_RST             : in std_logic;
+  FFC_PCI_DET_EN_0             : in std_logic;
+  FFC_PCI_DET_EN_1             : in std_logic;
+  FFC_PCI_DET_EN_2             : in std_logic;
+  FFC_PCI_DET_EN_3             : in std_logic;
+  FFC_PCIE_CT_0             : in std_logic;
+  FFC_PCIE_CT_1             : in std_logic;
+  FFC_PCIE_CT_2             : in std_logic;
+  FFC_PCIE_CT_3             : in std_logic;
+  FFC_PFIFO_CLR_0             : in std_logic;
+  FFC_PFIFO_CLR_1             : in std_logic;
+  FFC_PFIFO_CLR_2             : in std_logic;
+  FFC_PFIFO_CLR_3             : in std_logic;
+  FFC_QUAD_RST             : in std_logic;
+  FFC_RRST_0             : in std_logic;
+  FFC_RRST_1             : in std_logic;
+  FFC_RRST_2             : in std_logic;
+  FFC_RRST_3             : in std_logic;
+  FFC_RXPWDNB_0             : in std_logic;
+  FFC_RXPWDNB_1             : in std_logic;
+  FFC_RXPWDNB_2             : in std_logic;
+  FFC_RXPWDNB_3             : in std_logic;
+  FFC_SB_INV_RX_0             : in std_logic;
+  FFC_SB_INV_RX_1             : in std_logic;
+  FFC_SB_INV_RX_2             : in std_logic;
+  FFC_SB_INV_RX_3             : in std_logic;
+  FFC_SB_PFIFO_LP_0             : in std_logic;
+  FFC_SB_PFIFO_LP_1             : in std_logic;
+  FFC_SB_PFIFO_LP_2             : in std_logic;
+  FFC_SB_PFIFO_LP_3             : in std_logic;
+  FFC_SIGNAL_DETECT_0             : in std_logic;
+  FFC_SIGNAL_DETECT_1             : in std_logic;
+  FFC_SIGNAL_DETECT_2             : in std_logic;
+  FFC_SIGNAL_DETECT_3             : in std_logic;
+  FFC_SYNC_TOGGLE             : in std_logic;
+  FFC_TRST             : in std_logic;
+  FFC_TXPWDNB_0             : in std_logic;
+  FFC_TXPWDNB_1             : in std_logic;
+  FFC_TXPWDNB_2             : in std_logic;
+  FFC_TXPWDNB_3             : in std_logic;
+  FFC_RATE_MODE_RX_0        : in std_logic;
+  FFC_RATE_MODE_RX_1        : in std_logic;
+  FFC_RATE_MODE_RX_2        : in std_logic;
+  FFC_RATE_MODE_RX_3        : in std_logic;
+  FFC_RATE_MODE_TX_0        : in std_logic;
+  FFC_RATE_MODE_TX_1        : in std_logic;
+  FFC_RATE_MODE_TX_2        : in std_logic;
+  FFC_RATE_MODE_TX_3        : in std_logic;
+  FFC_DIV11_MODE_RX_0       : in std_logic;
+  FFC_DIV11_MODE_RX_1       : in std_logic;
+  FFC_DIV11_MODE_RX_2       : in std_logic;
+  FFC_DIV11_MODE_RX_3       : in std_logic;
+  FFC_DIV11_MODE_TX_0       : in std_logic;
+  FFC_DIV11_MODE_TX_1       : in std_logic;
+  FFC_DIV11_MODE_TX_2       : in std_logic;
+  FFC_DIV11_MODE_TX_3       : in std_logic;
+  LDR_CORE2TX_0             : in std_logic;
+  LDR_CORE2TX_1             : in std_logic;
+  LDR_CORE2TX_2             : in std_logic;
+  LDR_CORE2TX_3             : in std_logic;
+  FFC_LDR_CORE2TX_EN_0      : in std_logic;
+  FFC_LDR_CORE2TX_EN_1      : in std_logic;
+  FFC_LDR_CORE2TX_EN_2      : in std_logic;
+  FFC_LDR_CORE2TX_EN_3      : in std_logic;
+  PCIE_POWERDOWN_0_0      : in std_logic;
+  PCIE_POWERDOWN_0_1      : in std_logic;
+  PCIE_POWERDOWN_1_0      : in std_logic;
+  PCIE_POWERDOWN_1_1      : in std_logic;
+  PCIE_POWERDOWN_2_0      : in std_logic;
+  PCIE_POWERDOWN_2_1      : in std_logic;
+  PCIE_POWERDOWN_3_0      : in std_logic;
+  PCIE_POWERDOWN_3_1      : in std_logic;
+  PCIE_RXPOLARITY_0         : in std_logic;
+  PCIE_RXPOLARITY_1         : in std_logic;
+  PCIE_RXPOLARITY_2         : in std_logic;
+  PCIE_RXPOLARITY_3         : in std_logic;
+  PCIE_TXCOMPLIANCE_0       : in std_logic;
+  PCIE_TXCOMPLIANCE_1       : in std_logic;
+  PCIE_TXCOMPLIANCE_2       : in std_logic;
+  PCIE_TXCOMPLIANCE_3       : in std_logic;
+  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
+  SCIADDR0             : in std_logic;
+  SCIADDR1             : in std_logic;
+  SCIADDR2             : in std_logic;
+  SCIADDR3             : in std_logic;
+  SCIADDR4             : in std_logic;
+  SCIADDR5             : in std_logic;
+  SCIENAUX             : in std_logic;
+  SCIENCH0             : in std_logic;
+  SCIENCH1             : in std_logic;
+  SCIENCH2             : in std_logic;
+  SCIENCH3             : in std_logic;
+  SCIRD                : in std_logic;
+  SCISELAUX             : in std_logic;
+  SCISELCH0             : in std_logic;
+  SCISELCH1             : in std_logic;
+  SCISELCH2             : in std_logic;
+  SCISELCH3             : in std_logic;
+  SCIWDATA0             : in std_logic;
+  SCIWDATA1             : in std_logic;
+  SCIWDATA2             : in std_logic;
+  SCIWDATA3             : in std_logic;
+  SCIWDATA4             : in std_logic;
+  SCIWDATA5             : in std_logic;
+  SCIWDATA6             : in std_logic;
+  SCIWDATA7             : in std_logic;
+  SCIWSTN               : in std_logic;
+  REFCLK_FROM_NQ        : in std_logic;
+
+  HDOUTN0             : out std_logic;
+  HDOUTN1             : out std_logic;
+  HDOUTN2             : out std_logic;
+  HDOUTN3             : out std_logic;
+  HDOUTP0             : out std_logic;
+  HDOUTP1             : out std_logic;
+  HDOUTP2             : out std_logic;
+  HDOUTP3             : out std_logic;
+  COUT0             : out std_logic;
+  COUT1             : out std_logic;
+  COUT2             : out std_logic;
+  COUT3             : out std_logic;
+  COUT4             : out std_logic;
+  COUT5             : out std_logic;
+  COUT6             : out std_logic;
+  COUT7             : out std_logic;
+  COUT8             : out std_logic;
+  COUT9             : out std_logic;
+  COUT10             : out std_logic;
+  COUT11             : out std_logic;
+  COUT12             : out std_logic;
+  COUT13             : out std_logic;
+  COUT14             : out std_logic;
+  COUT15             : out std_logic;
+  COUT16             : out std_logic;
+  COUT17             : out std_logic;
+  COUT18             : out std_logic;
+  COUT19             : out std_logic;
+  FF_RX_D_0_0             : out std_logic;
+  FF_RX_D_0_1             : out std_logic;
+  FF_RX_D_0_2             : out std_logic;
+  FF_RX_D_0_3             : out std_logic;
+  FF_RX_D_0_4             : out std_logic;
+  FF_RX_D_0_5             : out std_logic;
+  FF_RX_D_0_6             : out std_logic;
+  FF_RX_D_0_7             : out std_logic;
+  FF_RX_D_0_8             : out std_logic;
+  FF_RX_D_0_9             : out std_logic;
+  FF_RX_D_0_10             : out std_logic;
+  FF_RX_D_0_11             : out std_logic;
+  FF_RX_D_0_12             : out std_logic;
+  FF_RX_D_0_13             : out std_logic;
+  FF_RX_D_0_14             : out std_logic;
+  FF_RX_D_0_15             : out std_logic;
+  FF_RX_D_0_16             : out std_logic;
+  FF_RX_D_0_17             : out std_logic;
+  FF_RX_D_0_18             : out std_logic;
+  FF_RX_D_0_19             : out std_logic;
+  FF_RX_D_0_20             : out std_logic;
+  FF_RX_D_0_21             : out std_logic;
+  FF_RX_D_0_22             : out std_logic;
+  FF_RX_D_0_23             : out std_logic;
+  FF_RX_D_1_0             : out std_logic;
+  FF_RX_D_1_1             : out std_logic;
+  FF_RX_D_1_2             : out std_logic;
+  FF_RX_D_1_3             : out std_logic;
+  FF_RX_D_1_4             : out std_logic;
+  FF_RX_D_1_5             : out std_logic;
+  FF_RX_D_1_6             : out std_logic;
+  FF_RX_D_1_7             : out std_logic;
+  FF_RX_D_1_8             : out std_logic;
+  FF_RX_D_1_9             : out std_logic;
+  FF_RX_D_1_10             : out std_logic;
+  FF_RX_D_1_11             : out std_logic;
+  FF_RX_D_1_12             : out std_logic;
+  FF_RX_D_1_13             : out std_logic;
+  FF_RX_D_1_14             : out std_logic;
+  FF_RX_D_1_15             : out std_logic;
+  FF_RX_D_1_16             : out std_logic;
+  FF_RX_D_1_17             : out std_logic;
+  FF_RX_D_1_18             : out std_logic;
+  FF_RX_D_1_19             : out std_logic;
+  FF_RX_D_1_20             : out std_logic;
+  FF_RX_D_1_21             : out std_logic;
+  FF_RX_D_1_22             : out std_logic;
+  FF_RX_D_1_23             : out std_logic;
+  FF_RX_D_2_0             : out std_logic;
+  FF_RX_D_2_1             : out std_logic;
+  FF_RX_D_2_2             : out std_logic;
+  FF_RX_D_2_3             : out std_logic;
+  FF_RX_D_2_4             : out std_logic;
+  FF_RX_D_2_5             : out std_logic;
+  FF_RX_D_2_6             : out std_logic;
+  FF_RX_D_2_7             : out std_logic;
+  FF_RX_D_2_8             : out std_logic;
+  FF_RX_D_2_9             : out std_logic;
+  FF_RX_D_2_10             : out std_logic;
+  FF_RX_D_2_11             : out std_logic;
+  FF_RX_D_2_12             : out std_logic;
+  FF_RX_D_2_13             : out std_logic;
+  FF_RX_D_2_14             : out std_logic;
+  FF_RX_D_2_15             : out std_logic;
+  FF_RX_D_2_16             : out std_logic;
+  FF_RX_D_2_17             : out std_logic;
+  FF_RX_D_2_18             : out std_logic;
+  FF_RX_D_2_19             : out std_logic;
+  FF_RX_D_2_20             : out std_logic;
+  FF_RX_D_2_21             : out std_logic;
+  FF_RX_D_2_22             : out std_logic;
+  FF_RX_D_2_23             : out std_logic;
+  FF_RX_D_3_0             : out std_logic;
+  FF_RX_D_3_1             : out std_logic;
+  FF_RX_D_3_2             : out std_logic;
+  FF_RX_D_3_3             : out std_logic;
+  FF_RX_D_3_4             : out std_logic;
+  FF_RX_D_3_5             : out std_logic;
+  FF_RX_D_3_6             : out std_logic;
+  FF_RX_D_3_7             : out std_logic;
+  FF_RX_D_3_8             : out std_logic;
+  FF_RX_D_3_9             : out std_logic;
+  FF_RX_D_3_10             : out std_logic;
+  FF_RX_D_3_11             : out std_logic;
+  FF_RX_D_3_12             : out std_logic;
+  FF_RX_D_3_13             : out std_logic;
+  FF_RX_D_3_14             : out std_logic;
+  FF_RX_D_3_15             : out std_logic;
+  FF_RX_D_3_16             : out std_logic;
+  FF_RX_D_3_17             : out std_logic;
+  FF_RX_D_3_18             : out std_logic;
+  FF_RX_D_3_19             : out std_logic;
+  FF_RX_D_3_20             : out std_logic;
+  FF_RX_D_3_21             : out std_logic;
+  FF_RX_D_3_22             : out std_logic;
+  FF_RX_D_3_23             : out std_logic;
+  FF_RX_F_CLK_0             : out std_logic;
+  FF_RX_F_CLK_1             : out std_logic;
+  FF_RX_F_CLK_2             : out std_logic;
+  FF_RX_F_CLK_3             : out std_logic;
+  FF_RX_H_CLK_0             : out std_logic;
+  FF_RX_H_CLK_1             : out std_logic;
+  FF_RX_H_CLK_2             : out std_logic;
+  FF_RX_H_CLK_3             : out std_logic;
+  FF_TX_F_CLK_0             : out std_logic;
+  FF_TX_F_CLK_1             : out std_logic;
+  FF_TX_F_CLK_2             : out std_logic;
+  FF_TX_F_CLK_3             : out std_logic;
+  FF_TX_H_CLK_0             : out std_logic;
+  FF_TX_H_CLK_1             : out std_logic;
+  FF_TX_H_CLK_2             : out std_logic;
+  FF_TX_H_CLK_3             : out std_logic;
+  FFS_CC_OVERRUN_0             : out std_logic;
+  FFS_CC_OVERRUN_1             : out std_logic;
+  FFS_CC_OVERRUN_2             : out std_logic;
+  FFS_CC_OVERRUN_3             : out std_logic;
+  FFS_CC_UNDERRUN_0             : out std_logic;
+  FFS_CC_UNDERRUN_1             : out std_logic;
+  FFS_CC_UNDERRUN_2             : out std_logic;
+  FFS_CC_UNDERRUN_3             : out std_logic;
+  FFS_LS_SYNC_STATUS_0             : out std_logic;
+  FFS_LS_SYNC_STATUS_1             : out std_logic;
+  FFS_LS_SYNC_STATUS_2             : out std_logic;
+  FFS_LS_SYNC_STATUS_3             : out std_logic;
+  FFS_CDR_TRAIN_DONE_0             : out std_logic;
+  FFS_CDR_TRAIN_DONE_1             : out std_logic;
+  FFS_CDR_TRAIN_DONE_2             : out std_logic;
+  FFS_CDR_TRAIN_DONE_3             : out std_logic;
+  FFS_PCIE_CON_0             : out std_logic;
+  FFS_PCIE_CON_1             : out std_logic;
+  FFS_PCIE_CON_2             : out std_logic;
+  FFS_PCIE_CON_3             : out std_logic;
+  FFS_PCIE_DONE_0             : out std_logic;
+  FFS_PCIE_DONE_1             : out std_logic;
+  FFS_PCIE_DONE_2             : out std_logic;
+  FFS_PCIE_DONE_3             : out std_logic;
+  FFS_PLOL             : out std_logic;
+  FFS_RLOL_0             : out std_logic;
+  FFS_RLOL_1             : out std_logic;
+  FFS_RLOL_2             : out std_logic;
+  FFS_RLOL_3             : out std_logic;
+  FFS_RLOS_HI_0             : out std_logic;
+  FFS_RLOS_HI_1             : out std_logic;
+  FFS_RLOS_HI_2             : out std_logic;
+  FFS_RLOS_HI_3             : out std_logic;
+  FFS_RLOS_LO_0             : out std_logic;
+  FFS_RLOS_LO_1             : out std_logic;
+  FFS_RLOS_LO_2             : out std_logic;
+  FFS_RLOS_LO_3             : out std_logic;
+  FFS_RXFBFIFO_ERROR_0             : out std_logic;
+  FFS_RXFBFIFO_ERROR_1             : out std_logic;
+  FFS_RXFBFIFO_ERROR_2             : out std_logic;
+  FFS_RXFBFIFO_ERROR_3             : out std_logic;
+  FFS_TXFBFIFO_ERROR_0             : out std_logic;
+  FFS_TXFBFIFO_ERROR_1             : out std_logic;
+  FFS_TXFBFIFO_ERROR_2             : out std_logic;
+  FFS_TXFBFIFO_ERROR_3             : out std_logic;
+  PCIE_PHYSTATUS_0             : out std_logic;
+  PCIE_PHYSTATUS_1             : out std_logic;
+  PCIE_PHYSTATUS_2             : out std_logic;
+  PCIE_PHYSTATUS_3             : out std_logic;
+  PCIE_RXVALID_0               : out std_logic;
+  PCIE_RXVALID_1               : out std_logic;
+  PCIE_RXVALID_2               : out std_logic;
+  PCIE_RXVALID_3               : out std_logic;
+  FFS_SKP_ADDED_0                  : out std_logic;
+  FFS_SKP_ADDED_1                  : out std_logic;
+  FFS_SKP_ADDED_2                  : out std_logic;
+  FFS_SKP_ADDED_3                  : out std_logic;
+  FFS_SKP_DELETED_0                : out std_logic;
+  FFS_SKP_DELETED_1                : out std_logic;
+  FFS_SKP_DELETED_2                : out std_logic;
+  FFS_SKP_DELETED_3                : out std_logic;
+  LDR_RX2CORE_0                    : out std_logic;
+  LDR_RX2CORE_1                    : out std_logic;
+  LDR_RX2CORE_2                    : out std_logic;
+  LDR_RX2CORE_3                    : out std_logic;
+  REFCK2CORE             : out std_logic;
+  SCIINT                : out std_logic;
+  SCIRDATA0             : out std_logic;
+  SCIRDATA1             : out std_logic;
+  SCIRDATA2             : out std_logic;
+  SCIRDATA3             : out std_logic;
+  SCIRDATA4             : out std_logic;
+  SCIRDATA5             : out std_logic;
+  SCIRDATA6             : out std_logic;
+  SCIRDATA7             : out std_logic;
+  REFCLK_TO_NQ          : out std_logic
+);
+
+end PCSD;
+
+architecture PCSD_arch of PCSD is
+
+
+component PCSD_sim
+GENERIC(
+  CONFIG_FILE : String;
+  QUAD_MODE : String;
+  CH0_CDR_SRC   : String;
+  CH1_CDR_SRC   : String;
+  CH2_CDR_SRC   : String;
+  CH3_CDR_SRC   : String;
+  PLL_SRC   : String
+  );
+port (
+  HDINN0             : in std_logic;
+  HDINN1             : in std_logic;
+  HDINN2             : in std_logic;
+  HDINN3             : in std_logic;
+  HDINP0             : in std_logic;
+  HDINP1             : in std_logic;
+  HDINP2             : in std_logic;
+  HDINP3             : in std_logic;
+  REFCLKN             : in std_logic;
+  REFCLKP             : in std_logic;
+  CIN0             : in std_logic;
+  CIN1             : in std_logic;
+  CIN2             : in std_logic;
+  CIN3             : in std_logic;
+  CIN4             : in std_logic;
+  CIN5             : in std_logic;
+  CIN6             : in std_logic;
+  CIN7             : in std_logic;
+  CIN8             : in std_logic;
+  CIN9             : in std_logic;
+  CIN10             : in std_logic;
+  CIN11             : in std_logic;
+  CYAWSTN             : in std_logic;
+  FF_EBRD_CLK_0             : in std_logic;
+  FF_EBRD_CLK_1             : in std_logic;
+  FF_EBRD_CLK_2             : in std_logic;
+  FF_EBRD_CLK_3             : in std_logic;
+  FF_RXI_CLK_0             : in std_logic;
+  FF_RXI_CLK_1             : in std_logic;
+  FF_RXI_CLK_2             : in std_logic;
+  FF_RXI_CLK_3             : in std_logic;
+  FF_TX_D_0_0             : in std_logic;
+  FF_TX_D_0_1             : in std_logic;
+  FF_TX_D_0_2             : in std_logic;
+  FF_TX_D_0_3             : in std_logic;
+  FF_TX_D_0_4             : in std_logic;
+  FF_TX_D_0_5             : in std_logic;
+  FF_TX_D_0_6             : in std_logic;
+  FF_TX_D_0_7             : in std_logic;
+  FF_TX_D_0_8             : in std_logic;
+  FF_TX_D_0_9             : in std_logic;
+  FF_TX_D_0_10             : in std_logic;
+  FF_TX_D_0_11             : in std_logic;
+  FF_TX_D_0_12             : in std_logic;
+  FF_TX_D_0_13             : in std_logic;
+  FF_TX_D_0_14             : in std_logic;
+  FF_TX_D_0_15             : in std_logic;
+  FF_TX_D_0_16             : in std_logic;
+  FF_TX_D_0_17             : in std_logic;
+  FF_TX_D_0_18             : in std_logic;
+  FF_TX_D_0_19             : in std_logic;
+  FF_TX_D_0_20             : in std_logic;
+  FF_TX_D_0_21             : in std_logic;
+  FF_TX_D_0_22             : in std_logic;
+  FF_TX_D_0_23             : in std_logic;
+  FF_TX_D_1_0             : in std_logic;
+  FF_TX_D_1_1             : in std_logic;
+  FF_TX_D_1_2             : in std_logic;
+  FF_TX_D_1_3             : in std_logic;
+  FF_TX_D_1_4             : in std_logic;
+  FF_TX_D_1_5             : in std_logic;
+  FF_TX_D_1_6             : in std_logic;
+  FF_TX_D_1_7             : in std_logic;
+  FF_TX_D_1_8             : in std_logic;
+  FF_TX_D_1_9             : in std_logic;
+  FF_TX_D_1_10             : in std_logic;
+  FF_TX_D_1_11             : in std_logic;
+  FF_TX_D_1_12             : in std_logic;
+  FF_TX_D_1_13             : in std_logic;
+  FF_TX_D_1_14             : in std_logic;
+  FF_TX_D_1_15             : in std_logic;
+  FF_TX_D_1_16             : in std_logic;
+  FF_TX_D_1_17             : in std_logic;
+  FF_TX_D_1_18             : in std_logic;
+  FF_TX_D_1_19             : in std_logic;
+  FF_TX_D_1_20             : in std_logic;
+  FF_TX_D_1_21             : in std_logic;
+  FF_TX_D_1_22             : in std_logic;
+  FF_TX_D_1_23             : in std_logic;
+  FF_TX_D_2_0             : in std_logic;
+  FF_TX_D_2_1             : in std_logic;
+  FF_TX_D_2_2             : in std_logic;
+  FF_TX_D_2_3             : in std_logic;
+  FF_TX_D_2_4             : in std_logic;
+  FF_TX_D_2_5             : in std_logic;
+  FF_TX_D_2_6             : in std_logic;
+  FF_TX_D_2_7             : in std_logic;
+  FF_TX_D_2_8             : in std_logic;
+  FF_TX_D_2_9             : in std_logic;
+  FF_TX_D_2_10             : in std_logic;
+  FF_TX_D_2_11             : in std_logic;
+  FF_TX_D_2_12             : in std_logic;
+  FF_TX_D_2_13             : in std_logic;
+  FF_TX_D_2_14             : in std_logic;
+  FF_TX_D_2_15             : in std_logic;
+  FF_TX_D_2_16             : in std_logic;
+  FF_TX_D_2_17             : in std_logic;
+  FF_TX_D_2_18             : in std_logic;
+  FF_TX_D_2_19             : in std_logic;
+  FF_TX_D_2_20             : in std_logic;
+  FF_TX_D_2_21             : in std_logic;
+  FF_TX_D_2_22             : in std_logic;
+  FF_TX_D_2_23             : in std_logic;
+  FF_TX_D_3_0             : in std_logic;
+  FF_TX_D_3_1             : in std_logic;
+  FF_TX_D_3_2             : in std_logic;
+  FF_TX_D_3_3             : in std_logic;
+  FF_TX_D_3_4             : in std_logic;
+  FF_TX_D_3_5             : in std_logic;
+  FF_TX_D_3_6             : in std_logic;
+  FF_TX_D_3_7             : in std_logic;
+  FF_TX_D_3_8             : in std_logic;
+  FF_TX_D_3_9             : in std_logic;
+  FF_TX_D_3_10             : in std_logic;
+  FF_TX_D_3_11             : in std_logic;
+  FF_TX_D_3_12             : in std_logic;
+  FF_TX_D_3_13             : in std_logic;
+  FF_TX_D_3_14             : in std_logic;
+  FF_TX_D_3_15             : in std_logic;
+  FF_TX_D_3_16             : in std_logic;
+  FF_TX_D_3_17             : in std_logic;
+  FF_TX_D_3_18             : in std_logic;
+  FF_TX_D_3_19             : in std_logic;
+  FF_TX_D_3_20             : in std_logic;
+  FF_TX_D_3_21             : in std_logic;
+  FF_TX_D_3_22             : in std_logic;
+  FF_TX_D_3_23             : in std_logic;
+  FF_TXI_CLK_0             : in std_logic;
+  FF_TXI_CLK_1             : in std_logic;
+  FF_TXI_CLK_2             : in std_logic;
+  FF_TXI_CLK_3             : in std_logic;
+  FFC_CK_CORE_RX_0         : in std_logic;
+  FFC_CK_CORE_RX_1         : in std_logic;
+  FFC_CK_CORE_RX_2         : in std_logic;
+  FFC_CK_CORE_RX_3         : in std_logic;
+  FFC_CK_CORE_TX           : in std_logic;
+  FFC_EI_EN_0             : in std_logic;
+  FFC_EI_EN_1             : in std_logic;
+  FFC_EI_EN_2             : in std_logic;
+  FFC_EI_EN_3             : in std_logic;
+  FFC_ENABLE_CGALIGN_0             : in std_logic;
+  FFC_ENABLE_CGALIGN_1             : in std_logic;
+  FFC_ENABLE_CGALIGN_2             : in std_logic;
+  FFC_ENABLE_CGALIGN_3             : in std_logic;
+  FFC_FB_LOOPBACK_0             : in std_logic;
+  FFC_FB_LOOPBACK_1             : in std_logic;
+  FFC_FB_LOOPBACK_2             : in std_logic;
+  FFC_FB_LOOPBACK_3             : in std_logic;
+  FFC_LANE_RX_RST_0             : in std_logic;
+  FFC_LANE_RX_RST_1             : in std_logic;
+  FFC_LANE_RX_RST_2             : in std_logic;
+  FFC_LANE_RX_RST_3             : in std_logic;
+  FFC_LANE_TX_RST_0             : in std_logic;
+  FFC_LANE_TX_RST_1             : in std_logic;
+  FFC_LANE_TX_RST_2             : in std_logic;
+  FFC_LANE_TX_RST_3             : in std_logic;
+  FFC_MACRO_RST             : in std_logic;
+  FFC_PCI_DET_EN_0             : in std_logic;
+  FFC_PCI_DET_EN_1             : in std_logic;
+  FFC_PCI_DET_EN_2             : in std_logic;
+  FFC_PCI_DET_EN_3             : in std_logic;
+  FFC_PCIE_CT_0             : in std_logic;
+  FFC_PCIE_CT_1             : in std_logic;
+  FFC_PCIE_CT_2             : in std_logic;
+  FFC_PCIE_CT_3             : in std_logic;
+  FFC_PFIFO_CLR_0             : in std_logic;
+  FFC_PFIFO_CLR_1             : in std_logic;
+  FFC_PFIFO_CLR_2             : in std_logic;
+  FFC_PFIFO_CLR_3             : in std_logic;
+  FFC_QUAD_RST             : in std_logic;
+  FFC_RRST_0             : in std_logic;
+  FFC_RRST_1             : in std_logic;
+  FFC_RRST_2             : in std_logic;
+  FFC_RRST_3             : in std_logic;
+  FFC_RXPWDNB_0             : in std_logic;
+  FFC_RXPWDNB_1             : in std_logic;
+  FFC_RXPWDNB_2             : in std_logic;
+  FFC_RXPWDNB_3             : in std_logic;
+  FFC_SB_INV_RX_0             : in std_logic;
+  FFC_SB_INV_RX_1             : in std_logic;
+  FFC_SB_INV_RX_2             : in std_logic;
+  FFC_SB_INV_RX_3             : in std_logic;
+  FFC_SB_PFIFO_LP_0             : in std_logic;
+  FFC_SB_PFIFO_LP_1             : in std_logic;
+  FFC_SB_PFIFO_LP_2             : in std_logic;
+  FFC_SB_PFIFO_LP_3             : in std_logic;
+  FFC_SIGNAL_DETECT_0             : in std_logic;
+  FFC_SIGNAL_DETECT_1             : in std_logic;
+  FFC_SIGNAL_DETECT_2             : in std_logic;
+  FFC_SIGNAL_DETECT_3             : in std_logic;
+  FFC_SYNC_TOGGLE             : in std_logic;
+  FFC_TRST             : in std_logic;
+  FFC_TXPWDNB_0             : in std_logic;
+  FFC_TXPWDNB_1             : in std_logic;
+  FFC_TXPWDNB_2             : in std_logic;
+  FFC_TXPWDNB_3             : in std_logic;
+  FFC_RATE_MODE_RX_0        : in std_logic;
+  FFC_RATE_MODE_RX_1        : in std_logic;
+  FFC_RATE_MODE_RX_2        : in std_logic;
+  FFC_RATE_MODE_RX_3        : in std_logic;
+  FFC_RATE_MODE_TX_0        : in std_logic;
+  FFC_RATE_MODE_TX_1        : in std_logic;
+  FFC_RATE_MODE_TX_2        : in std_logic;
+  FFC_RATE_MODE_TX_3        : in std_logic;
+  FFC_DIV11_MODE_RX_0       : in std_logic;
+  FFC_DIV11_MODE_RX_1       : in std_logic;
+  FFC_DIV11_MODE_RX_2       : in std_logic;
+  FFC_DIV11_MODE_RX_3       : in std_logic;
+  FFC_DIV11_MODE_TX_0       : in std_logic;
+  FFC_DIV11_MODE_TX_1       : in std_logic;
+  FFC_DIV11_MODE_TX_2       : in std_logic;
+  FFC_DIV11_MODE_TX_3       : in std_logic;
+  LDR_CORE2TX_0             : in std_logic;
+  LDR_CORE2TX_1             : in std_logic;
+  LDR_CORE2TX_2             : in std_logic;
+  LDR_CORE2TX_3             : in std_logic;
+  FFC_LDR_CORE2TX_EN_0      : in std_logic;
+  FFC_LDR_CORE2TX_EN_1      : in std_logic;
+  FFC_LDR_CORE2TX_EN_2      : in std_logic;
+  FFC_LDR_CORE2TX_EN_3      : in std_logic;
+  PCIE_POWERDOWN_0_0      : in std_logic;
+  PCIE_POWERDOWN_0_1      : in std_logic;
+  PCIE_POWERDOWN_1_0      : in std_logic;
+  PCIE_POWERDOWN_1_1      : in std_logic;
+  PCIE_POWERDOWN_2_0      : in std_logic;
+  PCIE_POWERDOWN_2_1      : in std_logic;
+  PCIE_POWERDOWN_3_0      : in std_logic;
+  PCIE_POWERDOWN_3_1      : in std_logic;
+  PCIE_RXPOLARITY_0         : in std_logic;
+  PCIE_RXPOLARITY_1         : in std_logic;
+  PCIE_RXPOLARITY_2         : in std_logic;
+  PCIE_RXPOLARITY_3         : in std_logic;
+  PCIE_TXCOMPLIANCE_0       : in std_logic;
+  PCIE_TXCOMPLIANCE_1       : in std_logic;
+  PCIE_TXCOMPLIANCE_2       : in std_logic;
+  PCIE_TXCOMPLIANCE_3       : in std_logic;
+  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
+  SCIADDR0             : in std_logic;
+  SCIADDR1             : in std_logic;
+  SCIADDR2             : in std_logic;
+  SCIADDR3             : in std_logic;
+  SCIADDR4             : in std_logic;
+  SCIADDR5             : in std_logic;
+  SCIENAUX             : in std_logic;
+  SCIENCH0             : in std_logic;
+  SCIENCH1             : in std_logic;
+  SCIENCH2             : in std_logic;
+  SCIENCH3             : in std_logic;
+  SCIRD                : in std_logic;
+  SCISELAUX             : in std_logic;
+  SCISELCH0             : in std_logic;
+  SCISELCH1             : in std_logic;
+  SCISELCH2             : in std_logic;
+  SCISELCH3             : in std_logic;
+  SCIWDATA0             : in std_logic;
+  SCIWDATA1             : in std_logic;
+  SCIWDATA2             : in std_logic;
+  SCIWDATA3             : in std_logic;
+  SCIWDATA4             : in std_logic;
+  SCIWDATA5             : in std_logic;
+  SCIWDATA6             : in std_logic;
+  SCIWDATA7             : in std_logic;
+  SCIWSTN               : in std_logic;
+  REFCLK_FROM_NQ        : in std_logic;
+
+  HDOUTN0             : out std_logic;
+  HDOUTN1             : out std_logic;
+  HDOUTN2             : out std_logic;
+  HDOUTN3             : out std_logic;
+  HDOUTP0             : out std_logic;
+  HDOUTP1             : out std_logic;
+  HDOUTP2             : out std_logic;
+  HDOUTP3             : out std_logic;
+  COUT0             : out std_logic;
+  COUT1             : out std_logic;
+  COUT2             : out std_logic;
+  COUT3             : out std_logic;
+  COUT4             : out std_logic;
+  COUT5             : out std_logic;
+  COUT6             : out std_logic;
+  COUT7             : out std_logic;
+  COUT8             : out std_logic;
+  COUT9             : out std_logic;
+  COUT10             : out std_logic;
+  COUT11             : out std_logic;
+  COUT12             : out std_logic;
+  COUT13             : out std_logic;
+  COUT14             : out std_logic;
+  COUT15             : out std_logic;
+  COUT16             : out std_logic;
+  COUT17             : out std_logic;
+  COUT18             : out std_logic;
+  COUT19             : out std_logic;
+  FF_RX_D_0_0             : out std_logic;
+  FF_RX_D_0_1             : out std_logic;
+  FF_RX_D_0_2             : out std_logic;
+  FF_RX_D_0_3             : out std_logic;
+  FF_RX_D_0_4             : out std_logic;
+  FF_RX_D_0_5             : out std_logic;
+  FF_RX_D_0_6             : out std_logic;
+  FF_RX_D_0_7             : out std_logic;
+  FF_RX_D_0_8             : out std_logic;
+  FF_RX_D_0_9             : out std_logic;
+  FF_RX_D_0_10             : out std_logic;
+  FF_RX_D_0_11             : out std_logic;
+  FF_RX_D_0_12             : out std_logic;
+  FF_RX_D_0_13             : out std_logic;
+  FF_RX_D_0_14             : out std_logic;
+  FF_RX_D_0_15             : out std_logic;
+  FF_RX_D_0_16             : out std_logic;
+  FF_RX_D_0_17             : out std_logic;
+  FF_RX_D_0_18             : out std_logic;
+  FF_RX_D_0_19             : out std_logic;
+  FF_RX_D_0_20             : out std_logic;
+  FF_RX_D_0_21             : out std_logic;
+  FF_RX_D_0_22             : out std_logic;
+  FF_RX_D_0_23             : out std_logic;
+  FF_RX_D_1_0             : out std_logic;
+  FF_RX_D_1_1             : out std_logic;
+  FF_RX_D_1_2             : out std_logic;
+  FF_RX_D_1_3             : out std_logic;
+  FF_RX_D_1_4             : out std_logic;
+  FF_RX_D_1_5             : out std_logic;
+  FF_RX_D_1_6             : out std_logic;
+  FF_RX_D_1_7             : out std_logic;
+  FF_RX_D_1_8             : out std_logic;
+  FF_RX_D_1_9             : out std_logic;
+  FF_RX_D_1_10             : out std_logic;
+  FF_RX_D_1_11             : out std_logic;
+  FF_RX_D_1_12             : out std_logic;
+  FF_RX_D_1_13             : out std_logic;
+  FF_RX_D_1_14             : out std_logic;
+  FF_RX_D_1_15             : out std_logic;
+  FF_RX_D_1_16             : out std_logic;
+  FF_RX_D_1_17             : out std_logic;
+  FF_RX_D_1_18             : out std_logic;
+  FF_RX_D_1_19             : out std_logic;
+  FF_RX_D_1_20             : out std_logic;
+  FF_RX_D_1_21             : out std_logic;
+  FF_RX_D_1_22             : out std_logic;
+  FF_RX_D_1_23             : out std_logic;
+  FF_RX_D_2_0             : out std_logic;
+  FF_RX_D_2_1             : out std_logic;
+  FF_RX_D_2_2             : out std_logic;
+  FF_RX_D_2_3             : out std_logic;
+  FF_RX_D_2_4             : out std_logic;
+  FF_RX_D_2_5             : out std_logic;
+  FF_RX_D_2_6             : out std_logic;
+  FF_RX_D_2_7             : out std_logic;
+  FF_RX_D_2_8             : out std_logic;
+  FF_RX_D_2_9             : out std_logic;
+  FF_RX_D_2_10             : out std_logic;
+  FF_RX_D_2_11             : out std_logic;
+  FF_RX_D_2_12             : out std_logic;
+  FF_RX_D_2_13             : out std_logic;
+  FF_RX_D_2_14             : out std_logic;
+  FF_RX_D_2_15             : out std_logic;
+  FF_RX_D_2_16             : out std_logic;
+  FF_RX_D_2_17             : out std_logic;
+  FF_RX_D_2_18             : out std_logic;
+  FF_RX_D_2_19             : out std_logic;
+  FF_RX_D_2_20             : out std_logic;
+  FF_RX_D_2_21             : out std_logic;
+  FF_RX_D_2_22             : out std_logic;
+  FF_RX_D_2_23             : out std_logic;
+  FF_RX_D_3_0             : out std_logic;
+  FF_RX_D_3_1             : out std_logic;
+  FF_RX_D_3_2             : out std_logic;
+  FF_RX_D_3_3             : out std_logic;
+  FF_RX_D_3_4             : out std_logic;
+  FF_RX_D_3_5             : out std_logic;
+  FF_RX_D_3_6             : out std_logic;
+  FF_RX_D_3_7             : out std_logic;
+  FF_RX_D_3_8             : out std_logic;
+  FF_RX_D_3_9             : out std_logic;
+  FF_RX_D_3_10             : out std_logic;
+  FF_RX_D_3_11             : out std_logic;
+  FF_RX_D_3_12             : out std_logic;
+  FF_RX_D_3_13             : out std_logic;
+  FF_RX_D_3_14             : out std_logic;
+  FF_RX_D_3_15             : out std_logic;
+  FF_RX_D_3_16             : out std_logic;
+  FF_RX_D_3_17             : out std_logic;
+  FF_RX_D_3_18             : out std_logic;
+  FF_RX_D_3_19             : out std_logic;
+  FF_RX_D_3_20             : out std_logic;
+  FF_RX_D_3_21             : out std_logic;
+  FF_RX_D_3_22             : out std_logic;
+  FF_RX_D_3_23             : out std_logic;
+  FF_RX_F_CLK_0             : out std_logic;
+  FF_RX_F_CLK_1             : out std_logic;
+  FF_RX_F_CLK_2             : out std_logic;
+  FF_RX_F_CLK_3             : out std_logic;
+  FF_RX_H_CLK_0             : out std_logic;
+  FF_RX_H_CLK_1             : out std_logic;
+  FF_RX_H_CLK_2             : out std_logic;
+  FF_RX_H_CLK_3             : out std_logic;
+  FF_TX_F_CLK_0             : out std_logic;
+  FF_TX_F_CLK_1             : out std_logic;
+  FF_TX_F_CLK_2             : out std_logic;
+  FF_TX_F_CLK_3             : out std_logic;
+  FF_TX_H_CLK_0             : out std_logic;
+  FF_TX_H_CLK_1             : out std_logic;
+  FF_TX_H_CLK_2             : out std_logic;
+  FF_TX_H_CLK_3             : out std_logic;
+  FFS_CC_OVERRUN_0             : out std_logic;
+  FFS_CC_OVERRUN_1             : out std_logic;
+  FFS_CC_OVERRUN_2             : out std_logic;
+  FFS_CC_OVERRUN_3             : out std_logic;
+  FFS_CC_UNDERRUN_0             : out std_logic;
+  FFS_CC_UNDERRUN_1             : out std_logic;
+  FFS_CC_UNDERRUN_2             : out std_logic;
+  FFS_CC_UNDERRUN_3             : out std_logic;
+  FFS_LS_SYNC_STATUS_0             : out std_logic;
+  FFS_LS_SYNC_STATUS_1             : out std_logic;
+  FFS_LS_SYNC_STATUS_2             : out std_logic;
+  FFS_LS_SYNC_STATUS_3             : out std_logic;
+  FFS_CDR_TRAIN_DONE_0             : out std_logic;
+  FFS_CDR_TRAIN_DONE_1             : out std_logic;
+  FFS_CDR_TRAIN_DONE_2             : out std_logic;
+  FFS_CDR_TRAIN_DONE_3             : out std_logic;
+  FFS_PCIE_CON_0             : out std_logic;
+  FFS_PCIE_CON_1             : out std_logic;
+  FFS_PCIE_CON_2             : out std_logic;
+  FFS_PCIE_CON_3             : out std_logic;
+  FFS_PCIE_DONE_0             : out std_logic;
+  FFS_PCIE_DONE_1             : out std_logic;
+  FFS_PCIE_DONE_2             : out std_logic;
+  FFS_PCIE_DONE_3             : out std_logic;
+  FFS_PLOL             : out std_logic;
+  FFS_RLOL_0             : out std_logic;
+  FFS_RLOL_1             : out std_logic;
+  FFS_RLOL_2             : out std_logic;
+  FFS_RLOL_3             : out std_logic;
+  FFS_RLOS_HI_0             : out std_logic;
+  FFS_RLOS_HI_1             : out std_logic;
+  FFS_RLOS_HI_2             : out std_logic;
+  FFS_RLOS_HI_3             : out std_logic;
+  FFS_RLOS_LO_0             : out std_logic;
+  FFS_RLOS_LO_1             : out std_logic;
+  FFS_RLOS_LO_2             : out std_logic;
+  FFS_RLOS_LO_3             : out std_logic;
+  FFS_RXFBFIFO_ERROR_0             : out std_logic;
+  FFS_RXFBFIFO_ERROR_1             : out std_logic;
+  FFS_RXFBFIFO_ERROR_2             : out std_logic;
+  FFS_RXFBFIFO_ERROR_3             : out std_logic;
+  FFS_TXFBFIFO_ERROR_0             : out std_logic;
+  FFS_TXFBFIFO_ERROR_1             : out std_logic;
+  FFS_TXFBFIFO_ERROR_2             : out std_logic;
+  FFS_TXFBFIFO_ERROR_3             : out std_logic;
+  PCIE_PHYSTATUS_0             : out std_logic;
+  PCIE_PHYSTATUS_1             : out std_logic;
+  PCIE_PHYSTATUS_2             : out std_logic;
+  PCIE_PHYSTATUS_3             : out std_logic;
+  PCIE_RXVALID_0               : out std_logic;
+  PCIE_RXVALID_1               : out std_logic;
+  PCIE_RXVALID_2               : out std_logic;
+  PCIE_RXVALID_3               : out std_logic;
+  FFS_SKP_ADDED_0                  : out std_logic;
+  FFS_SKP_ADDED_1                  : out std_logic;
+  FFS_SKP_ADDED_2                  : out std_logic;
+  FFS_SKP_ADDED_3                  : out std_logic;
+  FFS_SKP_DELETED_0                : out std_logic;
+  FFS_SKP_DELETED_1                : out std_logic;
+  FFS_SKP_DELETED_2                : out std_logic;
+  FFS_SKP_DELETED_3                : out std_logic;
+  LDR_RX2CORE_0                    : out std_logic;
+  LDR_RX2CORE_1                    : out std_logic;
+  LDR_RX2CORE_2                    : out std_logic;
+  LDR_RX2CORE_3                    : out std_logic;
+  REFCK2CORE             : out std_logic;
+  SCIINT                : out std_logic;
+  SCIRDATA0             : out std_logic;
+  SCIRDATA1             : out std_logic;
+  SCIRDATA2             : out std_logic;
+  SCIRDATA3             : out std_logic;
+  SCIRDATA4             : out std_logic;
+  SCIRDATA5             : out std_logic;
+  SCIRDATA6             : out std_logic;
+  SCIRDATA7             : out std_logic;
+  REFCLK_TO_NQ          : out std_logic
+);
+end component;
+
+begin
+
+PCSD_sim_inst : PCSD_sim
+generic map (
+  CONFIG_FILE => CONFIG_FILE,
+  QUAD_MODE => QUAD_MODE,
+  CH0_CDR_SRC => CH0_CDR_SRC,
+  CH1_CDR_SRC => CH1_CDR_SRC,
+  CH2_CDR_SRC => CH2_CDR_SRC,
+  CH3_CDR_SRC => CH3_CDR_SRC,
+  PLL_SRC => PLL_SRC
+  )
+port map (
+   HDINN0 => HDINN0,
+   HDINN1 => HDINN1,
+   HDINN2 => HDINN2,
+   HDINN3 => HDINN3,
+   HDINP0 => HDINP0,
+   HDINP1 => HDINP1,
+   HDINP2 => HDINP2,
+   HDINP3 => HDINP3,
+   REFCLKN => REFCLKN,
+   REFCLKP => REFCLKP,
+   CIN11 => CIN11,
+   CIN10 => CIN10,
+   CIN9 => CIN9,
+   CIN8 => CIN8,
+   CIN7 => CIN7,
+   CIN6 => CIN6,
+   CIN5 => CIN5,
+   CIN4 => CIN4,
+   CIN3 => CIN3,
+   CIN2 => CIN2,
+   CIN1 => CIN1,
+   CIN0 => CIN0,
+   CYAWSTN => CYAWSTN,
+   FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
+   FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
+   FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
+   FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
+   FF_RXI_CLK_3 => FF_RXI_CLK_3,
+   FF_RXI_CLK_2 => FF_RXI_CLK_2,
+   FF_RXI_CLK_1 => FF_RXI_CLK_1,
+   FF_RXI_CLK_0 => FF_RXI_CLK_0,
+   FF_TX_D_0_0 => FF_TX_D_0_0,
+   FF_TX_D_0_1 => FF_TX_D_0_1,
+   FF_TX_D_0_2 => FF_TX_D_0_2,
+   FF_TX_D_0_3 => FF_TX_D_0_3,
+   FF_TX_D_0_4 => FF_TX_D_0_4,
+   FF_TX_D_0_5 => FF_TX_D_0_5,
+   FF_TX_D_0_6 => FF_TX_D_0_6,
+   FF_TX_D_0_7 => FF_TX_D_0_7,
+   FF_TX_D_0_8 => FF_TX_D_0_8,
+   FF_TX_D_0_9 => FF_TX_D_0_9,
+   FF_TX_D_0_10 => FF_TX_D_0_10,
+   FF_TX_D_0_11 => FF_TX_D_0_11,
+   FF_TX_D_0_12 => FF_TX_D_0_12,
+   FF_TX_D_0_13 => FF_TX_D_0_13,
+   FF_TX_D_0_14 => FF_TX_D_0_14,
+   FF_TX_D_0_15 => FF_TX_D_0_15,
+   FF_TX_D_0_16 => FF_TX_D_0_16,
+   FF_TX_D_0_17 => FF_TX_D_0_17,
+   FF_TX_D_0_18 => FF_TX_D_0_18,
+   FF_TX_D_0_19 => FF_TX_D_0_19,
+   FF_TX_D_0_20 => FF_TX_D_0_20,
+   FF_TX_D_0_21 => FF_TX_D_0_21,
+   FF_TX_D_0_22 => FF_TX_D_0_22,
+   FF_TX_D_0_23 => FF_TX_D_0_23,
+   FF_TX_D_1_0 => FF_TX_D_1_0,
+   FF_TX_D_1_1 => FF_TX_D_1_1,
+   FF_TX_D_1_2 => FF_TX_D_1_2,
+   FF_TX_D_1_3 => FF_TX_D_1_3,
+   FF_TX_D_1_4 => FF_TX_D_1_4,
+   FF_TX_D_1_5 => FF_TX_D_1_5,
+   FF_TX_D_1_6 => FF_TX_D_1_6,
+   FF_TX_D_1_7 => FF_TX_D_1_7,
+   FF_TX_D_1_8 => FF_TX_D_1_8,
+   FF_TX_D_1_9 => FF_TX_D_1_9,
+   FF_TX_D_1_10 => FF_TX_D_1_10,
+   FF_TX_D_1_11 => FF_TX_D_1_11,
+   FF_TX_D_1_12 => FF_TX_D_1_12,
+   FF_TX_D_1_13 => FF_TX_D_1_13,
+   FF_TX_D_1_14 => FF_TX_D_1_14,
+   FF_TX_D_1_15 => FF_TX_D_1_15,
+   FF_TX_D_1_16 => FF_TX_D_1_16,
+   FF_TX_D_1_17 => FF_TX_D_1_17,
+   FF_TX_D_1_18 => FF_TX_D_1_18,
+   FF_TX_D_1_19 => FF_TX_D_1_19,
+   FF_TX_D_1_20 => FF_TX_D_1_20,
+   FF_TX_D_1_21 => FF_TX_D_1_21,
+   FF_TX_D_1_22 => FF_TX_D_1_22,
+   FF_TX_D_1_23 => FF_TX_D_1_23,
+   FF_TX_D_2_0 => FF_TX_D_2_0,
+   FF_TX_D_2_1 => FF_TX_D_2_1,
+   FF_TX_D_2_2 => FF_TX_D_2_2,
+   FF_TX_D_2_3 => FF_TX_D_2_3,
+   FF_TX_D_2_4 => FF_TX_D_2_4,
+   FF_TX_D_2_5 => FF_TX_D_2_5,
+   FF_TX_D_2_6 => FF_TX_D_2_6,
+   FF_TX_D_2_7 => FF_TX_D_2_7,
+   FF_TX_D_2_8 => FF_TX_D_2_8,
+   FF_TX_D_2_9 => FF_TX_D_2_9,
+   FF_TX_D_2_10 => FF_TX_D_2_10,
+   FF_TX_D_2_11 => FF_TX_D_2_11,
+   FF_TX_D_2_12 => FF_TX_D_2_12,
+   FF_TX_D_2_13 => FF_TX_D_2_13,
+   FF_TX_D_2_14 => FF_TX_D_2_14,
+   FF_TX_D_2_15 => FF_TX_D_2_15,
+   FF_TX_D_2_16 => FF_TX_D_2_16,
+   FF_TX_D_2_17 => FF_TX_D_2_17,
+   FF_TX_D_2_18 => FF_TX_D_2_18,
+   FF_TX_D_2_19 => FF_TX_D_2_19,
+   FF_TX_D_2_20 => FF_TX_D_2_20,
+   FF_TX_D_2_21 => FF_TX_D_2_21,
+   FF_TX_D_2_22 => FF_TX_D_2_22,
+   FF_TX_D_2_23 => FF_TX_D_2_23,
+   FF_TX_D_3_0 => FF_TX_D_3_0,
+   FF_TX_D_3_1 => FF_TX_D_3_1,
+   FF_TX_D_3_2 => FF_TX_D_3_2,
+   FF_TX_D_3_3 => FF_TX_D_3_3,
+   FF_TX_D_3_4 => FF_TX_D_3_4,
+   FF_TX_D_3_5 => FF_TX_D_3_5,
+   FF_TX_D_3_6 => FF_TX_D_3_6,
+   FF_TX_D_3_7 => FF_TX_D_3_7,
+   FF_TX_D_3_8 => FF_TX_D_3_8,
+   FF_TX_D_3_9 => FF_TX_D_3_9,
+   FF_TX_D_3_10 => FF_TX_D_3_10,
+   FF_TX_D_3_11 => FF_TX_D_3_11,
+   FF_TX_D_3_12 => FF_TX_D_3_12,
+   FF_TX_D_3_13 => FF_TX_D_3_13,
+   FF_TX_D_3_14 => FF_TX_D_3_14,
+   FF_TX_D_3_15 => FF_TX_D_3_15,
+   FF_TX_D_3_16 => FF_TX_D_3_16,
+   FF_TX_D_3_17 => FF_TX_D_3_17,
+   FF_TX_D_3_18 => FF_TX_D_3_18,
+   FF_TX_D_3_19 => FF_TX_D_3_19,
+   FF_TX_D_3_20 => FF_TX_D_3_20,
+   FF_TX_D_3_21 => FF_TX_D_3_21,
+   FF_TX_D_3_22 => FF_TX_D_3_22,
+   FF_TX_D_3_23 => FF_TX_D_3_23,
+   FF_TXI_CLK_0 => FF_TXI_CLK_0,
+   FF_TXI_CLK_1 => FF_TXI_CLK_1,
+   FF_TXI_CLK_2 => FF_TXI_CLK_2,
+   FF_TXI_CLK_3 => FF_TXI_CLK_3,
+   FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
+   FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
+   FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
+   FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
+   FFC_CK_CORE_TX => FFC_CK_CORE_TX,
+   FFC_EI_EN_0 => FFC_EI_EN_0,
+   FFC_EI_EN_1 => FFC_EI_EN_1,
+   FFC_EI_EN_2 => FFC_EI_EN_2,
+   FFC_EI_EN_3 => FFC_EI_EN_3,
+   FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
+   FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
+   FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
+   FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
+   FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
+   FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
+   FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
+   FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
+   FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
+   FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
+   FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
+   FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
+   FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
+   FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
+   FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
+   FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
+   FFC_MACRO_RST => FFC_MACRO_RST,
+   FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
+   FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
+   FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
+   FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
+   FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
+   FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
+   FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
+   FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
+   FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
+   FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
+   FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
+   FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
+   FFC_QUAD_RST => FFC_QUAD_RST,
+   FFC_RRST_0 => FFC_RRST_0,
+   FFC_RRST_1 => FFC_RRST_1,
+   FFC_RRST_2 => FFC_RRST_2,
+   FFC_RRST_3 => FFC_RRST_3,
+   FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
+   FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
+   FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
+   FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
+   FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
+   FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
+   FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
+   FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
+   FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
+   FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
+   FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
+   FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
+   FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
+   FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
+   FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
+   FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
+   FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
+   FFC_TRST => FFC_TRST,
+   FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
+   FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
+   FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
+   FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
+   FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
+   FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
+   FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
+   FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
+   FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
+   FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
+   FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
+   FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
+   FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
+   FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
+   FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
+   FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
+   FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
+   FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
+   FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
+   FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
+   LDR_CORE2TX_0 => LDR_CORE2TX_0,
+   LDR_CORE2TX_1 => LDR_CORE2TX_1,
+   LDR_CORE2TX_2 => LDR_CORE2TX_2,
+   LDR_CORE2TX_3 => LDR_CORE2TX_3,
+   FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
+   FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
+   FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
+   FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
+   PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
+   PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
+   PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
+   PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
+   PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
+   PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
+   PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
+   PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
+   PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
+   PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
+   PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
+   PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
+   PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
+   PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
+   PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
+   PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
+   PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
+   PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
+   PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
+   PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
+   SCIADDR0 => SCIADDR0,
+   SCIADDR1 => SCIADDR1,
+   SCIADDR2 => SCIADDR2,
+   SCIADDR3 => SCIADDR3,
+   SCIADDR4 => SCIADDR4,
+   SCIADDR5 => SCIADDR5,
+   SCIENAUX => SCIENAUX,
+   SCIENCH0 => SCIENCH0,
+   SCIENCH1 => SCIENCH1,
+   SCIENCH2 => SCIENCH2,
+   SCIENCH3 => SCIENCH3,
+   SCIRD => SCIRD,
+   SCISELAUX => SCISELAUX,
+   SCISELCH0 => SCISELCH0,
+   SCISELCH1 => SCISELCH1,
+   SCISELCH2 => SCISELCH2,
+   SCISELCH3 => SCISELCH3,
+   SCIWDATA0 => SCIWDATA0,
+   SCIWDATA1 => SCIWDATA1,
+   SCIWDATA2 => SCIWDATA2,
+   SCIWDATA3 => SCIWDATA3,
+   SCIWDATA4 => SCIWDATA4,
+   SCIWDATA5 => SCIWDATA5,
+   SCIWDATA6 => SCIWDATA6,
+   SCIWDATA7 => SCIWDATA7,
+   SCIWSTN => SCIWSTN,
+   HDOUTN0 => HDOUTN0,
+   HDOUTN1 => HDOUTN1,
+   HDOUTN2 => HDOUTN2,
+   HDOUTN3 => HDOUTN3,
+   HDOUTP0 => HDOUTP0,
+   HDOUTP1 => HDOUTP1,
+   HDOUTP2 => HDOUTP2,
+   HDOUTP3 => HDOUTP3,
+   COUT19 => COUT19,
+   COUT18 => COUT18,
+   COUT17 => COUT17,
+   COUT16 => COUT16,
+   COUT15 => COUT15,
+   COUT14 => COUT14,
+   COUT13 => COUT13,
+   COUT12 => COUT12,
+   COUT11 => COUT11,
+   COUT10 => COUT10,
+   COUT9 => COUT9,
+   COUT8 => COUT8,
+   COUT7 => COUT7,
+   COUT6 => COUT6,
+   COUT5 => COUT5,
+   COUT4 => COUT4,
+   COUT3 => COUT3,
+   COUT2 => COUT2,
+   COUT1 => COUT1,
+   COUT0 => COUT0,
+   FF_RX_D_0_0 => FF_RX_D_0_0,
+   FF_RX_D_0_1 => FF_RX_D_0_1,
+   FF_RX_D_0_2 => FF_RX_D_0_2,
+   FF_RX_D_0_3 => FF_RX_D_0_3,
+   FF_RX_D_0_4 => FF_RX_D_0_4,
+   FF_RX_D_0_5 => FF_RX_D_0_5,
+   FF_RX_D_0_6 => FF_RX_D_0_6,
+   FF_RX_D_0_7 => FF_RX_D_0_7,
+   FF_RX_D_0_8 => FF_RX_D_0_8,
+   FF_RX_D_0_9 => FF_RX_D_0_9,
+   FF_RX_D_0_10 => FF_RX_D_0_10,
+   FF_RX_D_0_11 => FF_RX_D_0_11,
+   FF_RX_D_0_12 => FF_RX_D_0_12,
+   FF_RX_D_0_13 => FF_RX_D_0_13,
+   FF_RX_D_0_14 => FF_RX_D_0_14,
+   FF_RX_D_0_15 => FF_RX_D_0_15,
+   FF_RX_D_0_16 => FF_RX_D_0_16,
+   FF_RX_D_0_17 => FF_RX_D_0_17,
+   FF_RX_D_0_18 => FF_RX_D_0_18,
+   FF_RX_D_0_19 => FF_RX_D_0_19,
+   FF_RX_D_0_20 => FF_RX_D_0_20,
+   FF_RX_D_0_21 => FF_RX_D_0_21,
+   FF_RX_D_0_22 => FF_RX_D_0_22,
+   FF_RX_D_0_23 => FF_RX_D_0_23,
+   FF_RX_D_1_0 => FF_RX_D_1_0,
+   FF_RX_D_1_1 => FF_RX_D_1_1,
+   FF_RX_D_1_2 => FF_RX_D_1_2,
+   FF_RX_D_1_3 => FF_RX_D_1_3,
+   FF_RX_D_1_4 => FF_RX_D_1_4,
+   FF_RX_D_1_5 => FF_RX_D_1_5,
+   FF_RX_D_1_6 => FF_RX_D_1_6,
+   FF_RX_D_1_7 => FF_RX_D_1_7,
+   FF_RX_D_1_8 => FF_RX_D_1_8,
+   FF_RX_D_1_9 => FF_RX_D_1_9,
+   FF_RX_D_1_10 => FF_RX_D_1_10,
+   FF_RX_D_1_11 => FF_RX_D_1_11,
+   FF_RX_D_1_12 => FF_RX_D_1_12,
+   FF_RX_D_1_13 => FF_RX_D_1_13,
+   FF_RX_D_1_14 => FF_RX_D_1_14,
+   FF_RX_D_1_15 => FF_RX_D_1_15,
+   FF_RX_D_1_16 => FF_RX_D_1_16,
+   FF_RX_D_1_17 => FF_RX_D_1_17,
+   FF_RX_D_1_18 => FF_RX_D_1_18,
+   FF_RX_D_1_19 => FF_RX_D_1_19,
+   FF_RX_D_1_20 => FF_RX_D_1_20,
+   FF_RX_D_1_21 => FF_RX_D_1_21,
+   FF_RX_D_1_22 => FF_RX_D_1_22,
+   FF_RX_D_1_23 => FF_RX_D_1_23,
+   FF_RX_D_2_0 => FF_RX_D_2_0,
+   FF_RX_D_2_1 => FF_RX_D_2_1,
+   FF_RX_D_2_2 => FF_RX_D_2_2,
+   FF_RX_D_2_3 => FF_RX_D_2_3,
+   FF_RX_D_2_4 => FF_RX_D_2_4,
+   FF_RX_D_2_5 => FF_RX_D_2_5,
+   FF_RX_D_2_6 => FF_RX_D_2_6,
+   FF_RX_D_2_7 => FF_RX_D_2_7,
+   FF_RX_D_2_8 => FF_RX_D_2_8,
+   FF_RX_D_2_9 => FF_RX_D_2_9,
+   FF_RX_D_2_10 => FF_RX_D_2_10,
+   FF_RX_D_2_11 => FF_RX_D_2_11,
+   FF_RX_D_2_12 => FF_RX_D_2_12,
+   FF_RX_D_2_13 => FF_RX_D_2_13,
+   FF_RX_D_2_14 => FF_RX_D_2_14,
+   FF_RX_D_2_15 => FF_RX_D_2_15,
+   FF_RX_D_2_16 => FF_RX_D_2_16,
+   FF_RX_D_2_17 => FF_RX_D_2_17,
+   FF_RX_D_2_18 => FF_RX_D_2_18,
+   FF_RX_D_2_19 => FF_RX_D_2_19,
+   FF_RX_D_2_20 => FF_RX_D_2_20,
+   FF_RX_D_2_21 => FF_RX_D_2_21,
+   FF_RX_D_2_22 => FF_RX_D_2_22,
+   FF_RX_D_2_23 => FF_RX_D_2_23,
+   FF_RX_D_3_0 => FF_RX_D_3_0,
+   FF_RX_D_3_1 => FF_RX_D_3_1,
+   FF_RX_D_3_2 => FF_RX_D_3_2,
+   FF_RX_D_3_3 => FF_RX_D_3_3,
+   FF_RX_D_3_4 => FF_RX_D_3_4,
+   FF_RX_D_3_5 => FF_RX_D_3_5,
+   FF_RX_D_3_6 => FF_RX_D_3_6,
+   FF_RX_D_3_7 => FF_RX_D_3_7,
+   FF_RX_D_3_8 => FF_RX_D_3_8,
+   FF_RX_D_3_9 => FF_RX_D_3_9,
+   FF_RX_D_3_10 => FF_RX_D_3_10,
+   FF_RX_D_3_11 => FF_RX_D_3_11,
+   FF_RX_D_3_12 => FF_RX_D_3_12,
+   FF_RX_D_3_13 => FF_RX_D_3_13,
+   FF_RX_D_3_14 => FF_RX_D_3_14,
+   FF_RX_D_3_15 => FF_RX_D_3_15,
+   FF_RX_D_3_16 => FF_RX_D_3_16,
+   FF_RX_D_3_17 => FF_RX_D_3_17,
+   FF_RX_D_3_18 => FF_RX_D_3_18,
+   FF_RX_D_3_19 => FF_RX_D_3_19,
+   FF_RX_D_3_20 => FF_RX_D_3_20,
+   FF_RX_D_3_21 => FF_RX_D_3_21,
+   FF_RX_D_3_22 => FF_RX_D_3_22,
+   FF_RX_D_3_23 => FF_RX_D_3_23,
+   FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
+   FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
+   FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
+   FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
+   FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
+   FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
+   FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
+   FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
+   FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
+   FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
+   FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
+   FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
+   FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
+   FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
+   FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
+   FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
+   FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
+   FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
+   FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
+   FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
+   FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
+   FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
+   FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
+   FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
+   FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
+   FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
+   FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
+   FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
+   FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
+   FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
+   FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
+   FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
+   FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
+   FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
+   FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
+   FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
+   FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
+   FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
+   FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
+   FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
+   FFS_PLOL => FFS_PLOL,
+   FFS_RLOL_0 => FFS_RLOL_0,
+   FFS_RLOL_1 => FFS_RLOL_1,
+   FFS_RLOL_2 => FFS_RLOL_2,
+   FFS_RLOL_3 => FFS_RLOL_3,
+   FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
+   FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
+   FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
+   FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
+   FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
+   FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
+   FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
+   FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
+   FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
+   FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
+   FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
+   FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
+   FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
+   FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
+   FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
+   FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
+   PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
+   PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
+   PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
+   PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
+   PCIE_RXVALID_0 => PCIE_RXVALID_0,
+   PCIE_RXVALID_1 => PCIE_RXVALID_1,
+   PCIE_RXVALID_2 => PCIE_RXVALID_2,
+   PCIE_RXVALID_3 => PCIE_RXVALID_3,
+   FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
+   FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
+   FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
+   FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
+   FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
+   FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
+   FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
+   FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
+   LDR_RX2CORE_0 => LDR_RX2CORE_0,
+   LDR_RX2CORE_1 => LDR_RX2CORE_1,
+   LDR_RX2CORE_2 => LDR_RX2CORE_2,
+   LDR_RX2CORE_3 => LDR_RX2CORE_3,
+   REFCK2CORE => REFCK2CORE,
+   SCIINT => SCIINT,
+   SCIRDATA0 => SCIRDATA0,
+   SCIRDATA1 => SCIRDATA1,
+   SCIRDATA2 => SCIRDATA2,
+   SCIRDATA3 => SCIRDATA3,
+   SCIRDATA4 => SCIRDATA4,
+   SCIRDATA5 => SCIRDATA5,
+   SCIRDATA6 => SCIRDATA6,
+   SCIRDATA7 => SCIRDATA7,
+   REFCLK_FROM_NQ => REFCLK_FROM_NQ,
+   REFCLK_TO_NQ => REFCLK_TO_NQ
+   );
+
+end PCSD_arch;
+
+--synopsys translate_on
+
+--THIS MODULE IS INSTANTIATED PER RX CHANNEL
+--Reset Sequence Generator
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+                                                                                              
+entity sfp_1_3_200_intrx_reset_sm is
+generic (count_index: integer :=18);
+port (
+   rst_n       : in std_logic;
+   refclkdiv2        : in std_logic;
+   tx_pll_lol_qd_s   : in std_logic;
+   rx_serdes_rst_ch_c: out std_logic;
+   rx_cdr_lol_ch_s   : in std_logic;
+   rx_los_low_ch_s   : in std_logic;
+   rx_pcs_rst_ch_c   : out std_logic
+);
+end sfp_1_3_200_intrx_reset_sm ;
+                                                                                              
+architecture rx_reset_sm_arch of sfp_1_3_200_intrx_reset_sm is
+                                                                                              
+type statetype is (WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_LOS, WAIT_FOR_TIMER2, NORMAL);
+                                                                                              
+signal   cs:      statetype;  -- current state of lsm
+signal   ns:      statetype;  -- next state of lsm
+attribute syn_encoding : string;
+attribute syn_encoding of cs : signal is "safe";
+attribute syn_encoding of ns : signal is "safe";
+                                                                                              
+signal   tx_pll_lol_qd_s_int: std_logic;
+signal   rx_los_low_int:         std_logic;
+signal   plol_los_int:        std_logic;
+signal   rx_lol_los  :  std_logic;
+signal   rx_lol_los_int:      std_logic;
+signal   rx_lol_los_del:      std_logic;
+signal   rx_pcs_rst_ch_c_int: std_logic;
+signal   rx_serdes_rst_ch_c_int: std_logic;
+                                                                                              
+signal   reset_timer1:  std_logic;
+signal   reset_timer2:  std_logic;
+                                                                                              
+signal   counter1:   std_logic_vector(1 downto 0);
+signal   TIMER1:  std_logic;
+                                                                                              
+signal   counter2: std_logic_vector(18 downto 0);
+signal   TIMER2   : std_logic;
+signal   rstn_m1:       std_logic;                                           
+signal   rstn_m2:       std_logic;                                           
+signal   sync_rst_n:       std_logic;                                                                                                                                      
+begin
+
+process (refclkdiv2, rst_n)
+begin
+   if rst_n = '0' then
+      rstn_m1 <= '0';
+      rstn_m2 <= '0';
+   else if rising_edge(refclkdiv2) then
+      rstn_m1 <= '1';
+      rstn_m2 <= rstn_m1;
+   end if;
+   end if;
+end process;
+
+   sync_rst_n <= rstn_m2;                   
+                                                                                              
+rx_lol_los <= rx_cdr_lol_ch_s or rx_los_low_ch_s ;
+                                                                                              
+process(refclkdiv2, sync_rst_n)
+begin
+   if  sync_rst_n = '0' then
+         cs <= WAIT_FOR_PLOL;
+         rx_lol_los_int <= '1';
+         rx_lol_los_del <= '1';
+         tx_pll_lol_qd_s_int <= '1';
+         rx_pcs_rst_ch_c <= '1';
+         rx_serdes_rst_ch_c <= '0';
+         rx_los_low_int <= '1';
+      else if rising_edge(refclkdiv2) then
+         cs <= ns;
+         rx_lol_los_del <= rx_lol_los;
+         rx_lol_los_int <= rx_lol_los_del;
+         tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
+         rx_pcs_rst_ch_c <= rx_pcs_rst_ch_c_int;
+         rx_serdes_rst_ch_c <= rx_serdes_rst_ch_c_int;
+         rx_los_low_int <= rx_los_low_ch_s;
+      end if;
+   end if;
+end process;
+                                                                                              
+--TIMER1 = 3NS;
+--Fastest REFCLK = 312 MHz, or 3ns. We need 1 REFCLK cycles or 2 REFCLKDIV2 cycles
+--A 1 bit counter  counts 2 cycles, so a 2 bit ([1:0]) counter will do if we set TIMER1 = bit[1]
+                                                                                              
+process(refclkdiv2, reset_timer1)
+begin
+   if rising_edge(refclkdiv2) then
+      if reset_timer1 = '1' then
+         counter1 <= "00";
+         TIMER1 <= '0';
+      else
+         if counter1(1) = '1' then
+            TIMER1 <='1';
+         else
+            TIMER1 <='0';
+            counter1 <= counter1 + 1 ;
+         end if;
+      end if;
+   end if;
+end process;
+                                                                                              
+--TIMER2 = 400,000 Refclk cycles or 200,000 REFCLKDIV2 cycles
+--An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
+                                                                                              
+process(refclkdiv2, reset_timer2)
+begin
+   if rising_edge(refclkdiv2) then
+      if reset_timer2 = '1' then
+         counter2 <= "0000000000000000000";
+         TIMER2 <= '0';
+      else
+         if counter2(count_index) = '1' then
+            TIMER2 <='1';
+         else
+            TIMER2 <='0';
+            counter2 <= counter2 + 1 ;
+         end if;
+      end if;
+   end if;
+end process;
+                                                                                              
+                                                                                              
+process(cs, tx_pll_lol_qd_s_int, rx_los_low_int, TIMER1, rx_lol_los_int, TIMER2)
+begin
+      reset_timer1 <= '0';
+      reset_timer2 <= '0';
+                                                                                              
+   case cs is
+      when WAIT_FOR_PLOL =>
+         rx_pcs_rst_ch_c_int <= '1';
+         rx_serdes_rst_ch_c_int <= '0';
+         if (tx_pll_lol_qd_s_int = '1' or rx_los_low_int = '1') then  --Also make sure A Signal
+            ns <= WAIT_FOR_PLOL;             --is Present prior to moving to the next
+         else
+            ns <= RX_SERDES_RESET;
+            end if;
+                                                                                              
+       when RX_SERDES_RESET =>
+         rx_pcs_rst_ch_c_int <= '1';
+         rx_serdes_rst_ch_c_int <= '1';
+         reset_timer1 <= '1';
+            ns <= WAIT_FOR_TIMER1;
+                                                                                              
+                                                                                              
+      when WAIT_FOR_TIMER1 =>
+         rx_pcs_rst_ch_c_int <= '1';
+         rx_serdes_rst_ch_c_int <= '1';
+         if TIMER1 = '1' then
+            ns <= CHECK_LOL_LOS;
+         else
+            ns <= WAIT_FOR_TIMER1;
+            end if;
+                                                                                              
+      when CHECK_LOL_LOS =>
+         rx_pcs_rst_ch_c_int <= '1';
+         rx_serdes_rst_ch_c_int <= '0';
+         reset_timer2 <= '1';
+            ns <= WAIT_FOR_TIMER2;
+                                                                                              
+      when WAIT_FOR_TIMER2 =>
+         rx_pcs_rst_ch_c_int <= '1';
+         rx_serdes_rst_ch_c_int <= '0';
+         if rx_lol_los_int = rx_lol_los_del then   --NO RISING OR FALLING EDGES
+            if TIMER2 = '1' then
+               if rx_lol_los_int = '1' then
+                  ns <= WAIT_FOR_PLOL;
+               else
+                  ns <= NORMAL;
+               end if;
+            else
+               ns <= WAIT_FOR_TIMER2;
+            end if;
+         else
+               ns <= CHECK_LOL_LOS;    --RESET TIMER2
+         end if;
+                                                                                              
+      when NORMAL =>
+         rx_pcs_rst_ch_c_int <= '0';
+         rx_serdes_rst_ch_c_int <= '0';
+         if rx_lol_los_int = '1' then
+            ns <= WAIT_FOR_PLOL;
+         else
+            ns <= NORMAL;
+         end if;
+                                                                                              
+      when others =>
+         ns <= WAIT_FOR_PLOL;
+                                                                                              
+      end case;
+                                                                                              
+end process;
+                                                                                              
+                                                                                              
+end rx_reset_sm_arch;
+
+--THIS MODULE IS INSTANTIATED PER TX  QUAD
+--TX Reset Sequence state machine--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+                                                                                              
+entity sfp_1_3_200_inttx_reset_sm is
+generic (count_index: integer :=18);
+port (
+   rst_n          : in std_logic;
+   refclkdiv2      : in std_logic;
+   tx_pll_lol_qd_s : in std_logic;
+   rst_qd_c    : out std_logic;
+   tx_pcs_rst_ch_c : out std_logic
+   );
+end sfp_1_3_200_inttx_reset_sm;
+                                                                                              
+architecture tx_reset_sm_arch of sfp_1_3_200_inttx_reset_sm is
+                                                                                              
+type statetype is (QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NORMAL);
+                                                                                              
+signal   cs:      statetype;  -- current state of lsm
+signal   ns:      statetype;  -- next state of lsm
+attribute syn_encoding : string;
+attribute syn_encoding of cs : signal is "safe";
+attribute syn_encoding of ns : signal is "safe";
+                                                                                              
+signal   tx_pll_lol_qd_s_int  : std_logic;
+signal   tx_pcs_rst_ch_c_int  : std_logic_vector(3 downto 0);
+signal   rst_qd_c_int      : std_logic;
+                                                                                              
+signal   reset_timer1:  std_logic;
+signal   reset_timer2:  std_logic;
+                                                                                              
+signal   counter1:      std_logic_vector(2 downto 0);
+signal   TIMER1:        std_logic;
+                                                                                              
+signal   counter2:      std_logic_vector(18 downto 0);
+signal   TIMER2:        std_logic;
+
+signal   rstn_m1:       std_logic;                                                                                  
+signal   rstn_m2:       std_logic;                                                                                              
+signal   sync_rst_n:       std_logic;                                                                                              
+begin
+
+process (refclkdiv2, rst_n)
+begin
+   if rst_n = '0' then
+      rstn_m1 <= '0';
+      rstn_m2 <= '0';
+   else if rising_edge(refclkdiv2) then
+      rstn_m1 <= '1';
+      rstn_m2 <= rstn_m1;
+   end if;
+   end if;
+end process;
+   
+   sync_rst_n <= rstn_m2;                                                                                           
+process (refclkdiv2, sync_rst_n)
+begin
+   if sync_rst_n = '0' then
+      cs <= QUAD_RESET;
+      tx_pll_lol_qd_s_int <= '1';
+      tx_pcs_rst_ch_c <= '1';
+      rst_qd_c <= '1';
+   else if rising_edge(refclkdiv2) then
+      cs <= ns;
+      tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
+      tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int(0);
+      rst_qd_c <= rst_qd_c_int;
+   end if;
+   end if;
+end process;
+--TIMER1 = 20ns;
+--Fastest REFLCK =312 MHZ, or 3 ns. We need 8 REFCLK cycles or 4 REFCLKDIV2 cycles
+-- A 2 bit counter ([1:0]) counts 4 cycles, so a 3 bit ([2:0]) counter will do if we set TIMER1 = bit[2]
+                                                                                              
+                                                                                              
+process (refclkdiv2, reset_timer1)
+begin
+   if rising_edge(refclkdiv2) then
+      if reset_timer1 = '1' then
+         counter1 <= "000";
+         TIMER1 <= '0';
+      else
+         if counter1(2) = '1' then
+            TIMER1 <= '1';
+         else
+            TIMER1 <='0';
+            counter1 <= counter1 + 1 ;
+         end if;
+      end if;
+   end if;
+end process;
+                                                                                              
+                                                                                              
+--TIMER2 = 1,400,000 UI;
+--WORST CASE CYCLES is with smallest multipier factor.
+-- This would be with X8 clock multiplier in DIV2 mode
+-- IN this casse, 1 UI = 2/8 REFCLK  CYCLES = 1/8 REFCLKDIV2 CYCLES
+-- SO 1,400,000 UI =1,400,000/8 = 175,000 REFCLKDIV2 CYCLES
+-- An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
+                                                                                              
+                                                                                              
+process(refclkdiv2, reset_timer2)
+begin
+   if rising_edge(refclkdiv2) then
+      if reset_timer2 = '1' then
+         counter2 <= "0000000000000000000";
+         TIMER2 <= '0';
+      else
+         if counter2(count_index) = '1' then
+            TIMER2 <='1';
+         else
+            TIMER2 <='0';
+            counter2 <= counter2 + 1 ;
+         end if;
+      end if;
+   end if;
+end process;
+                                                                                              
+process(cs, TIMER1, TIMER2, tx_pll_lol_qd_s_int)
+begin
+                                                                                              
+      reset_timer1 <= '0';
+      reset_timer2 <= '0';
+                                                                                              
+   case cs is
+                                                                                              
+      when QUAD_RESET   =>
+      tx_pcs_rst_ch_c_int <= "1111";
+      rst_qd_c_int <= '1';
+      reset_timer1 <= '1';
+         ns <= WAIT_FOR_TIMER1;
+                                                                                              
+      when WAIT_FOR_TIMER1 =>
+      tx_pcs_rst_ch_c_int <= "1111";
+      rst_qd_c_int <= '1';
+      if TIMER1 = '1' then
+         ns <= CHECK_PLOL;
+      else
+         ns <= WAIT_FOR_TIMER1;
+         end if;
+                                                                                              
+      when CHECK_PLOL   =>
+      tx_pcs_rst_ch_c_int <= "1111";
+      rst_qd_c_int <= '0';
+      reset_timer2 <= '1';
+         ns <= WAIT_FOR_TIMER2;
+                                                                                              
+      when WAIT_FOR_TIMER2 =>
+      tx_pcs_rst_ch_c_int <= "1111";
+      rst_qd_c_int <= '0';
+      if TIMER2 = '1' then
+         if tx_pll_lol_qd_s_int = '1' then
+            ns <= QUAD_RESET;
+         else
+            ns <= NORMAL;
+         end if;
+      else
+            ns <= WAIT_FOR_TIMER2;
+            end if;
+                                                                                              
+   when NORMAL =>
+      tx_pcs_rst_ch_c_int <= "0000";
+      rst_qd_c_int <= '0';
+      if tx_pll_lol_qd_s_int = '1' then
+         ns <= QUAD_RESET;
+      else
+         ns <= NORMAL;
+         end if;
+                                                                                              
+   when others =>
+      ns <=    QUAD_RESET;
+                                                                                              
+   end case;
+                                                                                              
+end process;
+                                                                                              
+end tx_reset_sm_arch;
+
+
+--synopsys translate_off
+library ECP3;
+use ECP3.components.all;
+--synopsys translate_on
+
+
+library IEEE, STD;
+use IEEE.std_logic_1164.all;
+use STD.TEXTIO.all;
+
+entity sfp_1_3_200_int is
+   GENERIC (USER_CONFIG_FILE    :  String := "sfp_1_3_200_int.txt");
+ port (
+------------------
+-- CH0 --
+-- CH1 --
+    hdinp_ch1, hdinn_ch1    :   in std_logic;
+    hdoutp_ch1, hdoutn_ch1   :   out std_logic;
+    sci_sel_ch1    :   in std_logic;
+    rxiclk_ch1    :   in std_logic;
+    txiclk_ch1    :   in std_logic;
+    rx_full_clk_ch1   :   out std_logic;
+    rx_half_clk_ch1   :   out std_logic;
+    tx_full_clk_ch1   :   out std_logic;
+    tx_half_clk_ch1   :   out std_logic;
+    fpga_rxrefclk_ch1    :   in std_logic;
+    txdata_ch1    :   in std_logic_vector (15 downto 0);
+    tx_k_ch1    :   in std_logic_vector (1 downto 0);
+    tx_force_disp_ch1    :   in std_logic_vector (1 downto 0);
+    tx_disp_sel_ch1    :   in std_logic_vector (1 downto 0);
+    rxdata_ch1   :   out std_logic_vector (15 downto 0);
+    rx_k_ch1   :   out std_logic_vector (1 downto 0);
+    rx_disp_err_ch1   :   out std_logic_vector (1 downto 0);
+    rx_cv_err_ch1   :   out std_logic_vector (1 downto 0);
+    sb_felb_ch1_c    :   in std_logic;
+    sb_felb_rst_ch1_c    :   in std_logic;
+    tx_pwrup_ch1_c    :   in std_logic;
+    rx_pwrup_ch1_c    :   in std_logic;
+    rx_los_low_ch1_s   :   out std_logic;
+    lsm_status_ch1_s   :   out std_logic;
+    rx_cdr_lol_ch1_s   :   out std_logic;
+    tx_div2_mode_ch1_c   : in std_logic;
+    rx_div2_mode_ch1_c   : in std_logic;
+-- CH2 --
+-- CH3 --
+    hdoutp_ch3, hdoutn_ch3   :   out std_logic;
+    sci_sel_ch3    :   in std_logic;
+    txiclk_ch3    :   in std_logic;
+    tx_full_clk_ch3   :   out std_logic;
+    tx_half_clk_ch3   :   out std_logic;
+    fpga_rxrefclk_ch3    :   in std_logic;
+    txdata_ch3    :   in std_logic_vector (7 downto 0);
+    tx_k_ch3    :   in std_logic;
+    tx_force_disp_ch3    :   in std_logic;
+    tx_disp_sel_ch3    :   in std_logic;
+    tx_pwrup_ch3_c    :   in std_logic;
+    tx_div2_mode_ch3_c   : in std_logic;
+---- Miscillaneous ports
+    sci_wrdata    :   in std_logic_vector (7 downto 0);
+    sci_addr    :   in std_logic_vector (5 downto 0);
+    sci_rddata   :   out std_logic_vector (7 downto 0);
+    sci_sel_quad    :   in std_logic;
+    sci_rd    :   in std_logic;
+    sci_wrn    :   in std_logic;
+    fpga_txrefclk  :   in std_logic;
+    tx_serdes_rst_c    :   in std_logic;
+    tx_pll_lol_qd_s   :   out std_logic;
+    tx_sync_qd_c    :   in std_logic;
+    refclk2fpga   :   out std_logic;
+    rst_n      :   in std_logic;
+    serdes_rst_qd_c    :   in std_logic);
+
+end sfp_1_3_200_int;
+
+
+architecture sfp_1_3_200_int_arch of sfp_1_3_200_int is
+
+component VLO
+port (
+   Z : out std_logic);
+end component;
+
+component VHI
+port (
+   Z : out std_logic);
+end component;
+
+component sfp_1_3_200_intrx_reset_sm
+generic (count_index: integer :=18);
+port (
+   rst_n       : in std_logic;
+   refclkdiv2        : in std_logic;
+   tx_pll_lol_qd_s   : in std_logic;
+   rx_serdes_rst_ch_c: out std_logic;
+   rx_cdr_lol_ch_s   : in std_logic;
+   rx_los_low_ch_s   : in std_logic;
+   rx_pcs_rst_ch_c   : out std_logic
+);
+end component ;
+
+component sfp_1_3_200_inttx_reset_sm
+generic (count_index: integer :=18);
+port (
+   rst_n          : in std_logic;
+   refclkdiv2      : in std_logic;
+   tx_pll_lol_qd_s : in std_logic;
+   rst_qd_c    : out std_logic;
+   tx_pcs_rst_ch_c : out std_logic
+   );
+end component;
+
+component PCSD
+--synopsys translate_off
+GENERIC(
+  CONFIG_FILE : String;
+  QUAD_MODE : String;
+  CH0_CDR_SRC   : String := "REFCLK_EXT";
+  CH1_CDR_SRC   : String := "REFCLK_EXT";
+  CH2_CDR_SRC   : String := "REFCLK_EXT";
+  CH3_CDR_SRC   : String := "REFCLK_EXT";
+  PLL_SRC   : String
+  );
+--synopsys translate_on
+port (
+  HDINN0             : in std_logic;
+  HDINN1             : in std_logic;
+  HDINN2             : in std_logic;
+  HDINN3             : in std_logic;
+  HDINP0             : in std_logic;
+  HDINP1             : in std_logic;
+  HDINP2             : in std_logic;
+  HDINP3             : in std_logic;
+  REFCLKN             : in std_logic;
+  REFCLKP             : in std_logic;
+  CIN0             : in std_logic;
+  CIN1             : in std_logic;
+  CIN2             : in std_logic;
+  CIN3             : in std_logic;
+  CIN4             : in std_logic;
+  CIN5             : in std_logic;
+  CIN6             : in std_logic;
+  CIN7             : in std_logic;
+  CIN8             : in std_logic;
+  CIN9             : in std_logic;
+  CIN10             : in std_logic;
+  CIN11             : in std_logic;
+  CYAWSTN             : in std_logic;
+  FF_EBRD_CLK_0             : in std_logic;
+  FF_EBRD_CLK_1             : in std_logic;
+  FF_EBRD_CLK_2             : in std_logic;
+  FF_EBRD_CLK_3             : in std_logic;
+  FF_RXI_CLK_0             : in std_logic;
+  FF_RXI_CLK_1             : in std_logic;
+  FF_RXI_CLK_2             : in std_logic;
+  FF_RXI_CLK_3             : in std_logic;
+  FF_TX_D_0_0             : in std_logic;
+  FF_TX_D_0_1             : in std_logic;
+  FF_TX_D_0_2             : in std_logic;
+  FF_TX_D_0_3             : in std_logic;
+  FF_TX_D_0_4             : in std_logic;
+  FF_TX_D_0_5             : in std_logic;
+  FF_TX_D_0_6             : in std_logic;
+  FF_TX_D_0_7             : in std_logic;
+  FF_TX_D_0_8             : in std_logic;
+  FF_TX_D_0_9             : in std_logic;
+  FF_TX_D_0_10             : in std_logic;
+  FF_TX_D_0_11             : in std_logic;
+  FF_TX_D_0_12             : in std_logic;
+  FF_TX_D_0_13             : in std_logic;
+  FF_TX_D_0_14             : in std_logic;
+  FF_TX_D_0_15             : in std_logic;
+  FF_TX_D_0_16             : in std_logic;
+  FF_TX_D_0_17             : in std_logic;
+  FF_TX_D_0_18             : in std_logic;
+  FF_TX_D_0_19             : in std_logic;
+  FF_TX_D_0_20             : in std_logic;
+  FF_TX_D_0_21             : in std_logic;
+  FF_TX_D_0_22             : in std_logic;
+  FF_TX_D_0_23             : in std_logic;
+  FF_TX_D_1_0             : in std_logic;
+  FF_TX_D_1_1             : in std_logic;
+  FF_TX_D_1_2             : in std_logic;
+  FF_TX_D_1_3             : in std_logic;
+  FF_TX_D_1_4             : in std_logic;
+  FF_TX_D_1_5             : in std_logic;
+  FF_TX_D_1_6             : in std_logic;
+  FF_TX_D_1_7             : in std_logic;
+  FF_TX_D_1_8             : in std_logic;
+  FF_TX_D_1_9             : in std_logic;
+  FF_TX_D_1_10             : in std_logic;
+  FF_TX_D_1_11             : in std_logic;
+  FF_TX_D_1_12             : in std_logic;
+  FF_TX_D_1_13             : in std_logic;
+  FF_TX_D_1_14             : in std_logic;
+  FF_TX_D_1_15             : in std_logic;
+  FF_TX_D_1_16             : in std_logic;
+  FF_TX_D_1_17             : in std_logic;
+  FF_TX_D_1_18             : in std_logic;
+  FF_TX_D_1_19             : in std_logic;
+  FF_TX_D_1_20             : in std_logic;
+  FF_TX_D_1_21             : in std_logic;
+  FF_TX_D_1_22             : in std_logic;
+  FF_TX_D_1_23             : in std_logic;
+  FF_TX_D_2_0             : in std_logic;
+  FF_TX_D_2_1             : in std_logic;
+  FF_TX_D_2_2             : in std_logic;
+  FF_TX_D_2_3             : in std_logic;
+  FF_TX_D_2_4             : in std_logic;
+  FF_TX_D_2_5             : in std_logic;
+  FF_TX_D_2_6             : in std_logic;
+  FF_TX_D_2_7             : in std_logic;
+  FF_TX_D_2_8             : in std_logic;
+  FF_TX_D_2_9             : in std_logic;
+  FF_TX_D_2_10             : in std_logic;
+  FF_TX_D_2_11             : in std_logic;
+  FF_TX_D_2_12             : in std_logic;
+  FF_TX_D_2_13             : in std_logic;
+  FF_TX_D_2_14             : in std_logic;
+  FF_TX_D_2_15             : in std_logic;
+  FF_TX_D_2_16             : in std_logic;
+  FF_TX_D_2_17             : in std_logic;
+  FF_TX_D_2_18             : in std_logic;
+  FF_TX_D_2_19             : in std_logic;
+  FF_TX_D_2_20             : in std_logic;
+  FF_TX_D_2_21             : in std_logic;
+  FF_TX_D_2_22             : in std_logic;
+  FF_TX_D_2_23             : in std_logic;
+  FF_TX_D_3_0             : in std_logic;
+  FF_TX_D_3_1             : in std_logic;
+  FF_TX_D_3_2             : in std_logic;
+  FF_TX_D_3_3             : in std_logic;
+  FF_TX_D_3_4             : in std_logic;
+  FF_TX_D_3_5             : in std_logic;
+  FF_TX_D_3_6             : in std_logic;
+  FF_TX_D_3_7             : in std_logic;
+  FF_TX_D_3_8             : in std_logic;
+  FF_TX_D_3_9             : in std_logic;
+  FF_TX_D_3_10             : in std_logic;
+  FF_TX_D_3_11             : in std_logic;
+  FF_TX_D_3_12             : in std_logic;
+  FF_TX_D_3_13             : in std_logic;
+  FF_TX_D_3_14             : in std_logic;
+  FF_TX_D_3_15             : in std_logic;
+  FF_TX_D_3_16             : in std_logic;
+  FF_TX_D_3_17             : in std_logic;
+  FF_TX_D_3_18             : in std_logic;
+  FF_TX_D_3_19             : in std_logic;
+  FF_TX_D_3_20             : in std_logic;
+  FF_TX_D_3_21             : in std_logic;
+  FF_TX_D_3_22             : in std_logic;
+  FF_TX_D_3_23             : in std_logic;
+  FF_TXI_CLK_0             : in std_logic;
+  FF_TXI_CLK_1             : in std_logic;
+  FF_TXI_CLK_2             : in std_logic;
+  FF_TXI_CLK_3             : in std_logic;
+  FFC_CK_CORE_RX_0         : in std_logic;
+  FFC_CK_CORE_RX_1         : in std_logic;
+  FFC_CK_CORE_RX_2         : in std_logic;
+  FFC_CK_CORE_RX_3         : in std_logic;
+  FFC_CK_CORE_TX           : in std_logic;
+  FFC_EI_EN_0             : in std_logic;
+  FFC_EI_EN_1             : in std_logic;
+  FFC_EI_EN_2             : in std_logic;
+  FFC_EI_EN_3             : in std_logic;
+  FFC_ENABLE_CGALIGN_0             : in std_logic;
+  FFC_ENABLE_CGALIGN_1             : in std_logic;
+  FFC_ENABLE_CGALIGN_2             : in std_logic;
+  FFC_ENABLE_CGALIGN_3             : in std_logic;
+  FFC_FB_LOOPBACK_0             : in std_logic;
+  FFC_FB_LOOPBACK_1             : in std_logic;
+  FFC_FB_LOOPBACK_2             : in std_logic;
+  FFC_FB_LOOPBACK_3             : in std_logic;
+  FFC_LANE_RX_RST_0             : in std_logic;
+  FFC_LANE_RX_RST_1             : in std_logic;
+  FFC_LANE_RX_RST_2             : in std_logic;
+  FFC_LANE_RX_RST_3             : in std_logic;
+  FFC_LANE_TX_RST_0             : in std_logic;
+  FFC_LANE_TX_RST_1             : in std_logic;
+  FFC_LANE_TX_RST_2             : in std_logic;
+  FFC_LANE_TX_RST_3             : in std_logic;
+  FFC_MACRO_RST             : in std_logic;
+  FFC_PCI_DET_EN_0             : in std_logic;
+  FFC_PCI_DET_EN_1             : in std_logic;
+  FFC_PCI_DET_EN_2             : in std_logic;
+  FFC_PCI_DET_EN_3             : in std_logic;
+  FFC_PCIE_CT_0             : in std_logic;
+  FFC_PCIE_CT_1             : in std_logic;
+  FFC_PCIE_CT_2             : in std_logic;
+  FFC_PCIE_CT_3             : in std_logic;
+  FFC_PFIFO_CLR_0             : in std_logic;
+  FFC_PFIFO_CLR_1             : in std_logic;
+  FFC_PFIFO_CLR_2             : in std_logic;
+  FFC_PFIFO_CLR_3             : in std_logic;
+  FFC_QUAD_RST             : in std_logic;
+  FFC_RRST_0             : in std_logic;
+  FFC_RRST_1             : in std_logic;
+  FFC_RRST_2             : in std_logic;
+  FFC_RRST_3             : in std_logic;
+  FFC_RXPWDNB_0             : in std_logic;
+  FFC_RXPWDNB_1             : in std_logic;
+  FFC_RXPWDNB_2             : in std_logic;
+  FFC_RXPWDNB_3             : in std_logic;
+  FFC_SB_INV_RX_0             : in std_logic;
+  FFC_SB_INV_RX_1             : in std_logic;
+  FFC_SB_INV_RX_2             : in std_logic;
+  FFC_SB_INV_RX_3             : in std_logic;
+  FFC_SB_PFIFO_LP_0             : in std_logic;
+  FFC_SB_PFIFO_LP_1             : in std_logic;
+  FFC_SB_PFIFO_LP_2             : in std_logic;
+  FFC_SB_PFIFO_LP_3             : in std_logic;
+  FFC_SIGNAL_DETECT_0             : in std_logic;
+  FFC_SIGNAL_DETECT_1             : in std_logic;
+  FFC_SIGNAL_DETECT_2             : in std_logic;
+  FFC_SIGNAL_DETECT_3             : in std_logic;
+  FFC_SYNC_TOGGLE             : in std_logic;
+  FFC_TRST             : in std_logic;
+  FFC_TXPWDNB_0             : in std_logic;
+  FFC_TXPWDNB_1             : in std_logic;
+  FFC_TXPWDNB_2             : in std_logic;
+  FFC_TXPWDNB_3             : in std_logic;
+  FFC_RATE_MODE_RX_0        : in std_logic;
+  FFC_RATE_MODE_RX_1        : in std_logic;
+  FFC_RATE_MODE_RX_2        : in std_logic;
+  FFC_RATE_MODE_RX_3        : in std_logic;
+  FFC_RATE_MODE_TX_0        : in std_logic;
+  FFC_RATE_MODE_TX_1        : in std_logic;
+  FFC_RATE_MODE_TX_2        : in std_logic;
+  FFC_RATE_MODE_TX_3        : in std_logic;
+  FFC_DIV11_MODE_RX_0       : in std_logic;
+  FFC_DIV11_MODE_RX_1       : in std_logic;
+  FFC_DIV11_MODE_RX_2       : in std_logic;
+  FFC_DIV11_MODE_RX_3       : in std_logic;
+  FFC_DIV11_MODE_TX_0       : in std_logic;
+  FFC_DIV11_MODE_TX_1       : in std_logic;
+  FFC_DIV11_MODE_TX_2       : in std_logic;
+  FFC_DIV11_MODE_TX_3       : in std_logic;
+  LDR_CORE2TX_0             : in std_logic;
+  LDR_CORE2TX_1             : in std_logic;
+  LDR_CORE2TX_2             : in std_logic;
+  LDR_CORE2TX_3             : in std_logic;
+  FFC_LDR_CORE2TX_EN_0      : in std_logic;
+  FFC_LDR_CORE2TX_EN_1      : in std_logic;
+  FFC_LDR_CORE2TX_EN_2      : in std_logic;
+  FFC_LDR_CORE2TX_EN_3      : in std_logic;
+  PCIE_POWERDOWN_0_0      : in std_logic;
+  PCIE_POWERDOWN_0_1      : in std_logic;
+  PCIE_POWERDOWN_1_0      : in std_logic;
+  PCIE_POWERDOWN_1_1      : in std_logic;
+  PCIE_POWERDOWN_2_0      : in std_logic;
+  PCIE_POWERDOWN_2_1      : in std_logic;
+  PCIE_POWERDOWN_3_0      : in std_logic;
+  PCIE_POWERDOWN_3_1      : in std_logic;
+  PCIE_RXPOLARITY_0         : in std_logic;
+  PCIE_RXPOLARITY_1         : in std_logic;
+  PCIE_RXPOLARITY_2         : in std_logic;
+  PCIE_RXPOLARITY_3         : in std_logic;
+  PCIE_TXCOMPLIANCE_0       : in std_logic;
+  PCIE_TXCOMPLIANCE_1       : in std_logic;
+  PCIE_TXCOMPLIANCE_2       : in std_logic;
+  PCIE_TXCOMPLIANCE_3       : in std_logic;
+  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
+  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
+  SCIADDR0             : in std_logic;
+  SCIADDR1             : in std_logic;
+  SCIADDR2             : in std_logic;
+  SCIADDR3             : in std_logic;
+  SCIADDR4             : in std_logic;
+  SCIADDR5             : in std_logic;
+  SCIENAUX             : in std_logic;
+  SCIENCH0             : in std_logic;
+  SCIENCH1             : in std_logic;
+  SCIENCH2             : in std_logic;
+  SCIENCH3             : in std_logic;
+  SCIRD                : in std_logic;
+  SCISELAUX             : in std_logic;
+  SCISELCH0             : in std_logic;
+  SCISELCH1             : in std_logic;
+  SCISELCH2             : in std_logic;
+  SCISELCH3             : in std_logic;
+  SCIWDATA0             : in std_logic;
+  SCIWDATA1             : in std_logic;
+  SCIWDATA2             : in std_logic;
+  SCIWDATA3             : in std_logic;
+  SCIWDATA4             : in std_logic;
+  SCIWDATA5             : in std_logic;
+  SCIWDATA6             : in std_logic;
+  SCIWDATA7             : in std_logic;
+  SCIWSTN               : in std_logic;
+  REFCLK_FROM_NQ        : in std_logic;
+  HDOUTN0             : out std_logic;
+  HDOUTN1             : out std_logic;
+  HDOUTN2             : out std_logic;
+  HDOUTN3             : out std_logic;
+  HDOUTP0             : out std_logic;
+  HDOUTP1             : out std_logic;
+  HDOUTP2             : out std_logic;
+  HDOUTP3             : out std_logic;
+  COUT0             : out std_logic;
+  COUT1             : out std_logic;
+  COUT2             : out std_logic;
+  COUT3             : out std_logic;
+  COUT4             : out std_logic;
+  COUT5             : out std_logic;
+  COUT6             : out std_logic;
+  COUT7             : out std_logic;
+  COUT8             : out std_logic;
+  COUT9             : out std_logic;
+  COUT10             : out std_logic;
+  COUT11             : out std_logic;
+  COUT12             : out std_logic;
+  COUT13             : out std_logic;
+  COUT14             : out std_logic;
+  COUT15             : out std_logic;
+  COUT16             : out std_logic;
+  COUT17             : out std_logic;
+  COUT18             : out std_logic;
+  COUT19             : out std_logic;
+  FF_RX_D_0_0             : out std_logic;
+  FF_RX_D_0_1             : out std_logic;
+  FF_RX_D_0_2             : out std_logic;
+  FF_RX_D_0_3             : out std_logic;
+  FF_RX_D_0_4             : out std_logic;
+  FF_RX_D_0_5             : out std_logic;
+  FF_RX_D_0_6             : out std_logic;
+  FF_RX_D_0_7             : out std_logic;
+  FF_RX_D_0_8             : out std_logic;
+  FF_RX_D_0_9             : out std_logic;
+  FF_RX_D_0_10             : out std_logic;
+  FF_RX_D_0_11             : out std_logic;
+  FF_RX_D_0_12             : out std_logic;
+  FF_RX_D_0_13             : out std_logic;
+  FF_RX_D_0_14             : out std_logic;
+  FF_RX_D_0_15             : out std_logic;
+  FF_RX_D_0_16             : out std_logic;
+  FF_RX_D_0_17             : out std_logic;
+  FF_RX_D_0_18             : out std_logic;
+  FF_RX_D_0_19             : out std_logic;
+  FF_RX_D_0_20             : out std_logic;
+  FF_RX_D_0_21             : out std_logic;
+  FF_RX_D_0_22             : out std_logic;
+  FF_RX_D_0_23             : out std_logic;
+  FF_RX_D_1_0             : out std_logic;
+  FF_RX_D_1_1             : out std_logic;
+  FF_RX_D_1_2             : out std_logic;
+  FF_RX_D_1_3             : out std_logic;
+  FF_RX_D_1_4             : out std_logic;
+  FF_RX_D_1_5             : out std_logic;
+  FF_RX_D_1_6             : out std_logic;
+  FF_RX_D_1_7             : out std_logic;
+  FF_RX_D_1_8             : out std_logic;
+  FF_RX_D_1_9             : out std_logic;
+  FF_RX_D_1_10             : out std_logic;
+  FF_RX_D_1_11             : out std_logic;
+  FF_RX_D_1_12             : out std_logic;
+  FF_RX_D_1_13             : out std_logic;
+  FF_RX_D_1_14             : out std_logic;
+  FF_RX_D_1_15             : out std_logic;
+  FF_RX_D_1_16             : out std_logic;
+  FF_RX_D_1_17             : out std_logic;
+  FF_RX_D_1_18             : out std_logic;
+  FF_RX_D_1_19             : out std_logic;
+  FF_RX_D_1_20             : out std_logic;
+  FF_RX_D_1_21             : out std_logic;
+  FF_RX_D_1_22             : out std_logic;
+  FF_RX_D_1_23             : out std_logic;
+  FF_RX_D_2_0             : out std_logic;
+  FF_RX_D_2_1             : out std_logic;
+  FF_RX_D_2_2             : out std_logic;
+  FF_RX_D_2_3             : out std_logic;
+  FF_RX_D_2_4             : out std_logic;
+  FF_RX_D_2_5             : out std_logic;
+  FF_RX_D_2_6             : out std_logic;
+  FF_RX_D_2_7             : out std_logic;
+  FF_RX_D_2_8             : out std_logic;
+  FF_RX_D_2_9             : out std_logic;
+  FF_RX_D_2_10             : out std_logic;
+  FF_RX_D_2_11             : out std_logic;
+  FF_RX_D_2_12             : out std_logic;
+  FF_RX_D_2_13             : out std_logic;
+  FF_RX_D_2_14             : out std_logic;
+  FF_RX_D_2_15             : out std_logic;
+  FF_RX_D_2_16             : out std_logic;
+  FF_RX_D_2_17             : out std_logic;
+  FF_RX_D_2_18             : out std_logic;
+  FF_RX_D_2_19             : out std_logic;
+  FF_RX_D_2_20             : out std_logic;
+  FF_RX_D_2_21             : out std_logic;
+  FF_RX_D_2_22             : out std_logic;
+  FF_RX_D_2_23             : out std_logic;
+  FF_RX_D_3_0             : out std_logic;
+  FF_RX_D_3_1             : out std_logic;
+  FF_RX_D_3_2             : out std_logic;
+  FF_RX_D_3_3             : out std_logic;
+  FF_RX_D_3_4             : out std_logic;
+  FF_RX_D_3_5             : out std_logic;
+  FF_RX_D_3_6             : out std_logic;
+  FF_RX_D_3_7             : out std_logic;
+  FF_RX_D_3_8             : out std_logic;
+  FF_RX_D_3_9             : out std_logic;
+  FF_RX_D_3_10             : out std_logic;
+  FF_RX_D_3_11             : out std_logic;
+  FF_RX_D_3_12             : out std_logic;
+  FF_RX_D_3_13             : out std_logic;
+  FF_RX_D_3_14             : out std_logic;
+  FF_RX_D_3_15             : out std_logic;
+  FF_RX_D_3_16             : out std_logic;
+  FF_RX_D_3_17             : out std_logic;
+  FF_RX_D_3_18             : out std_logic;
+  FF_RX_D_3_19             : out std_logic;
+  FF_RX_D_3_20             : out std_logic;
+  FF_RX_D_3_21             : out std_logic;
+  FF_RX_D_3_22             : out std_logic;
+  FF_RX_D_3_23             : out std_logic;
+  FF_RX_F_CLK_0             : out std_logic;
+  FF_RX_F_CLK_1             : out std_logic;
+  FF_RX_F_CLK_2             : out std_logic;
+  FF_RX_F_CLK_3             : out std_logic;
+  FF_RX_H_CLK_0             : out std_logic;
+  FF_RX_H_CLK_1             : out std_logic;
+  FF_RX_H_CLK_2             : out std_logic;
+  FF_RX_H_CLK_3             : out std_logic;
+  FF_TX_F_CLK_0             : out std_logic;
+  FF_TX_F_CLK_1             : out std_logic;
+  FF_TX_F_CLK_2             : out std_logic;
+  FF_TX_F_CLK_3             : out std_logic;
+  FF_TX_H_CLK_0             : out std_logic;
+  FF_TX_H_CLK_1             : out std_logic;
+  FF_TX_H_CLK_2             : out std_logic;
+  FF_TX_H_CLK_3             : out std_logic;
+  FFS_CC_OVERRUN_0             : out std_logic;
+  FFS_CC_OVERRUN_1             : out std_logic;
+  FFS_CC_OVERRUN_2             : out std_logic;
+  FFS_CC_OVERRUN_3             : out std_logic;
+  FFS_CC_UNDERRUN_0             : out std_logic;
+  FFS_CC_UNDERRUN_1             : out std_logic;
+  FFS_CC_UNDERRUN_2             : out std_logic;
+  FFS_CC_UNDERRUN_3             : out std_logic;
+  FFS_LS_SYNC_STATUS_0             : out std_logic;
+  FFS_LS_SYNC_STATUS_1             : out std_logic;
+  FFS_LS_SYNC_STATUS_2             : out std_logic;
+  FFS_LS_SYNC_STATUS_3             : out std_logic;
+  FFS_CDR_TRAIN_DONE_0             : out std_logic;
+  FFS_CDR_TRAIN_DONE_1             : out std_logic;
+  FFS_CDR_TRAIN_DONE_2             : out std_logic;
+  FFS_CDR_TRAIN_DONE_3             : out std_logic;
+  FFS_PCIE_CON_0             : out std_logic;
+  FFS_PCIE_CON_1             : out std_logic;
+  FFS_PCIE_CON_2             : out std_logic;
+  FFS_PCIE_CON_3             : out std_logic;
+  FFS_PCIE_DONE_0             : out std_logic;
+  FFS_PCIE_DONE_1             : out std_logic;
+  FFS_PCIE_DONE_2             : out std_logic;
+  FFS_PCIE_DONE_3             : out std_logic;
+  FFS_PLOL             : out std_logic;
+  FFS_RLOL_0             : out std_logic;
+  FFS_RLOL_1             : out std_logic;
+  FFS_RLOL_2             : out std_logic;
+  FFS_RLOL_3             : out std_logic;
+  FFS_RLOS_HI_0             : out std_logic;
+  FFS_RLOS_HI_1             : out std_logic;
+  FFS_RLOS_HI_2             : out std_logic;
+  FFS_RLOS_HI_3             : out std_logic;
+  FFS_RLOS_LO_0             : out std_logic;
+  FFS_RLOS_LO_1             : out std_logic;
+  FFS_RLOS_LO_2             : out std_logic;
+  FFS_RLOS_LO_3             : out std_logic;
+  FFS_RXFBFIFO_ERROR_0             : out std_logic;
+  FFS_RXFBFIFO_ERROR_1             : out std_logic;
+  FFS_RXFBFIFO_ERROR_2             : out std_logic;
+  FFS_RXFBFIFO_ERROR_3             : out std_logic;
+  FFS_TXFBFIFO_ERROR_0             : out std_logic;
+  FFS_TXFBFIFO_ERROR_1             : out std_logic;
+  FFS_TXFBFIFO_ERROR_2             : out std_logic;
+  FFS_TXFBFIFO_ERROR_3             : out std_logic;
+  PCIE_PHYSTATUS_0             : out std_logic;
+  PCIE_PHYSTATUS_1             : out std_logic;
+  PCIE_PHYSTATUS_2             : out std_logic;
+  PCIE_PHYSTATUS_3             : out std_logic;
+  PCIE_RXVALID_0               : out std_logic;
+  PCIE_RXVALID_1               : out std_logic;
+  PCIE_RXVALID_2               : out std_logic;
+  PCIE_RXVALID_3               : out std_logic;
+  FFS_SKP_ADDED_0                  : out std_logic;
+  FFS_SKP_ADDED_1                  : out std_logic;
+  FFS_SKP_ADDED_2                  : out std_logic;
+  FFS_SKP_ADDED_3                  : out std_logic;
+  FFS_SKP_DELETED_0                : out std_logic;
+  FFS_SKP_DELETED_1                : out std_logic;
+  FFS_SKP_DELETED_2                : out std_logic;
+  FFS_SKP_DELETED_3                : out std_logic;
+  LDR_RX2CORE_0                    : out std_logic;
+  LDR_RX2CORE_1                    : out std_logic;
+  LDR_RX2CORE_2                    : out std_logic;
+  LDR_RX2CORE_3                    : out std_logic;
+  REFCK2CORE             : out std_logic;
+  SCIINT                : out std_logic;
+  SCIRDATA0             : out std_logic;
+  SCIRDATA1             : out std_logic;
+  SCIRDATA2             : out std_logic;
+  SCIRDATA3             : out std_logic;
+  SCIRDATA4             : out std_logic;
+  SCIRDATA5             : out std_logic;
+  SCIRDATA6             : out std_logic;
+  SCIRDATA7             : out std_logic;
+  REFCLK_TO_NQ          : out std_logic
+);
+end component;
+   attribute CONFIG_FILE: string;
+   attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
+   attribute QUAD_MODE: string;
+   attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
+   attribute PLL_SRC: string;
+   attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
+   attribute CH1_CDR_SRC: string;
+   attribute CH1_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+   attribute CH3_CDR_SRC: string;
+   attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "250.000";
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "200";
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000";
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200";
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "125.000";
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "100";
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000";
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100";
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200";
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200";
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200";
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
+   attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "100";
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100";
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100";
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100";
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
+   attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "50";
+   attribute FREQUENCY_PIN_REFCK2CORE: string;
+   attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200";
+   attribute black_box_pad_pin: string;
+   attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
+
+signal refclk_from_nq : std_logic := '0';
+signal fpsc_vlo : std_logic := '0';
+signal fpsc_vhi : std_logic := '1';
+signal cin : std_logic_vector (11 downto 0) := "000000000000";
+signal cout : std_logic_vector (19 downto 0);
+signal    tx_full_clk_ch1_sig   :   std_logic;
+signal    tx_full_clk_ch3_sig   :   std_logic;
+
+signal    refclk2fpga_sig  :   std_logic;
+signal    tx_pll_lol_qd_sig  :   std_logic;
+signal    rx_los_low_ch0_sig  :   std_logic;
+signal    rx_los_low_ch1_sig  :   std_logic;
+signal    rx_los_low_ch2_sig  :   std_logic;
+signal    rx_los_low_ch3_sig  :   std_logic;
+signal    rx_cdr_lol_ch0_sig  :   std_logic;
+signal    rx_cdr_lol_ch1_sig  :   std_logic;
+signal    rx_cdr_lol_ch2_sig  :   std_logic;
+signal    rx_cdr_lol_ch3_sig  :   std_logic;
+
+signal    rx_serdes_rst_ch1_c  : std_logic;
+signal    rx_pcs_rst_ch1_c  : std_logic;
+
+-- reset sequence for rx
+signal    refclkdiv2_rx_ch1  :   std_logic;
+
+signal    refclkdiv2_tx_ch  :   std_logic;
+signal    tx_pcs_rst_ch_c   :   std_logic;
+signal    rst_qd_c   :   std_logic;
+
+
+begin
+
+vlo_inst : VLO port map(Z => fpsc_vlo);
+vhi_inst : VHI port map(Z => fpsc_vhi);
+
+  refclk2fpga <= refclk2fpga_sig;
+    rx_los_low_ch1_s <= rx_los_low_ch1_sig;
+    rx_cdr_lol_ch1_s <= rx_cdr_lol_ch1_sig;
+  tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
+  tx_full_clk_ch1 <= tx_full_clk_ch1_sig;
+  tx_full_clk_ch3 <= tx_full_clk_ch3_sig;
+
+-- pcs_quad instance
+PCSD_INST : PCSD
+--synopsys translate_off
+  generic map (CONFIG_FILE => USER_CONFIG_FILE,
+               QUAD_MODE => "SINGLE",
+               CH1_CDR_SRC => "REFCLK_CORE",
+               CH3_CDR_SRC => "REFCLK_CORE",
+               PLL_SRC  => "REFCLK_CORE"
+  )
+--synopsys translate_on
+port map  (
+  REFCLKP => fpsc_vlo,
+  REFCLKN => fpsc_vlo,
+
+----- CH0 -----
+  HDOUTP0 => open,
+  HDOUTN0 => open,
+  HDINP0 => fpsc_vlo,
+  HDINN0 => fpsc_vlo,
+  PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
+  PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
+  PCIE_RXPOLARITY_0 => fpsc_vlo,
+  PCIE_POWERDOWN_0_0 => fpsc_vlo,
+  PCIE_POWERDOWN_0_1 => fpsc_vlo,
+  PCIE_RXVALID_0 => open,
+  PCIE_PHYSTATUS_0 => open,
+  SCISELCH0 => fpsc_vlo,
+  SCIENCH0 => fpsc_vlo,
+  FF_RXI_CLK_0 => fpsc_vlo,
+  FF_TXI_CLK_0 => fpsc_vlo,
+  FF_EBRD_CLK_0 => fpsc_vlo,
+  FF_RX_F_CLK_0 => open,
+  FF_RX_H_CLK_0 => open,
+  FF_TX_F_CLK_0 => open,
+  FF_TX_H_CLK_0 => open,
+  FFC_CK_CORE_RX_0 => fpsc_vlo,
+  FF_TX_D_0_0 => fpsc_vlo,
+  FF_TX_D_0_1 => fpsc_vlo,
+  FF_TX_D_0_2 => fpsc_vlo,
+  FF_TX_D_0_3 => fpsc_vlo,
+  FF_TX_D_0_4 => fpsc_vlo,
+  FF_TX_D_0_5 => fpsc_vlo,
+  FF_TX_D_0_6 => fpsc_vlo,
+  FF_TX_D_0_7 => fpsc_vlo,
+  FF_TX_D_0_8 => fpsc_vlo,
+  FF_TX_D_0_9 => fpsc_vlo,
+  FF_TX_D_0_10 => fpsc_vlo,
+  FF_TX_D_0_11 => fpsc_vlo,
+  FF_TX_D_0_12 => fpsc_vlo,
+  FF_TX_D_0_13 => fpsc_vlo,
+  FF_TX_D_0_14 => fpsc_vlo,
+  FF_TX_D_0_15 => fpsc_vlo,
+  FF_TX_D_0_16 => fpsc_vlo,
+  FF_TX_D_0_17 => fpsc_vlo,
+  FF_TX_D_0_18 => fpsc_vlo,
+  FF_TX_D_0_19 => fpsc_vlo,
+  FF_TX_D_0_20 => fpsc_vlo,
+  FF_TX_D_0_21 => fpsc_vlo,
+  FF_TX_D_0_22 => fpsc_vlo,
+  FF_TX_D_0_23 => fpsc_vlo,
+  FF_RX_D_0_0 => open,
+  FF_RX_D_0_1 => open,
+  FF_RX_D_0_2 => open,
+  FF_RX_D_0_3 => open,
+  FF_RX_D_0_4 => open,
+  FF_RX_D_0_5 => open,
+  FF_RX_D_0_6 => open,
+  FF_RX_D_0_7 => open,
+  FF_RX_D_0_8 => open,
+  FF_RX_D_0_9 => open,
+  FF_RX_D_0_10 => open,
+  FF_RX_D_0_11 => open,
+  FF_RX_D_0_12 => open,
+  FF_RX_D_0_13 => open,
+  FF_RX_D_0_14 => open,
+  FF_RX_D_0_15 => open,
+  FF_RX_D_0_16 => open,
+  FF_RX_D_0_17 => open,
+  FF_RX_D_0_18 => open,
+  FF_RX_D_0_19 => open,
+  FF_RX_D_0_20 => open,
+  FF_RX_D_0_21 => open,
+  FF_RX_D_0_22 => open,
+  FF_RX_D_0_23 => open,
+
+  FFC_RRST_0 => fpsc_vlo,
+  FFC_SIGNAL_DETECT_0 => fpsc_vlo,
+  FFC_SB_PFIFO_LP_0 => fpsc_vlo,
+  FFC_PFIFO_CLR_0 => fpsc_vlo,
+  FFC_SB_INV_RX_0 => fpsc_vlo,
+  FFC_PCIE_CT_0 => fpsc_vlo,
+  FFC_PCI_DET_EN_0 => fpsc_vlo,
+  FFC_FB_LOOPBACK_0 => fpsc_vlo,
+  FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
+  FFC_EI_EN_0 => fpsc_vlo,
+  FFC_LANE_TX_RST_0 => fpsc_vlo,
+  FFC_TXPWDNB_0 => fpsc_vlo,
+  FFC_LANE_RX_RST_0 => fpsc_vlo,
+  FFC_RXPWDNB_0 => fpsc_vlo,
+  FFS_RLOS_LO_0 => open,
+  FFS_RLOS_HI_0 => open,
+  FFS_PCIE_CON_0 => open,
+  FFS_PCIE_DONE_0 => open,
+  FFS_LS_SYNC_STATUS_0 => open,
+  FFS_CC_OVERRUN_0 => open,
+  FFS_CC_UNDERRUN_0 => open,
+  FFS_SKP_ADDED_0 => open,
+  FFS_SKP_DELETED_0 => open,
+  FFS_RLOL_0 => open,
+  FFS_RXFBFIFO_ERROR_0 => open,
+  FFS_TXFBFIFO_ERROR_0 => open,
+  LDR_CORE2TX_0 => fpsc_vlo,
+  FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
+  LDR_RX2CORE_0 => open,
+  FFS_CDR_TRAIN_DONE_0 => open,
+  FFC_DIV11_MODE_TX_0 => fpsc_vlo,
+  FFC_RATE_MODE_TX_0 => fpsc_vlo,
+  FFC_DIV11_MODE_RX_0 => fpsc_vlo,
+  FFC_RATE_MODE_RX_0 => fpsc_vlo,
+
+----- CH1 -----
+  HDOUTP1 => hdoutp_ch1,
+  HDOUTN1 => hdoutn_ch1,
+  HDINP1 => hdinp_ch1,
+  HDINN1 => hdinn_ch1,
+  PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
+  PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
+  PCIE_RXPOLARITY_1 => fpsc_vlo,
+  PCIE_POWERDOWN_1_0 => fpsc_vlo,
+  PCIE_POWERDOWN_1_1 => fpsc_vlo,
+  PCIE_RXVALID_1 => open,
+  PCIE_PHYSTATUS_1 => open,
+  SCISELCH1 => sci_sel_ch1,
+  SCIENCH1 => fpsc_vhi,
+  FF_RXI_CLK_1 => rxiclk_ch1,
+  FF_TXI_CLK_1 => txiclk_ch1,
+  FF_EBRD_CLK_1 => fpsc_vlo,
+  FF_RX_F_CLK_1 => rx_full_clk_ch1,
+  FF_RX_H_CLK_1 => rx_half_clk_ch1,
+  FF_TX_F_CLK_1 => tx_full_clk_ch1_sig,
+  FF_TX_H_CLK_1 => tx_half_clk_ch1,
+  FFC_CK_CORE_RX_1 => fpga_rxrefclk_ch1,
+  FF_TX_D_1_0 => txdata_ch1(0),
+  FF_TX_D_1_1 => txdata_ch1(1),
+  FF_TX_D_1_2 => txdata_ch1(2),
+  FF_TX_D_1_3 => txdata_ch1(3),
+  FF_TX_D_1_4 => txdata_ch1(4),
+  FF_TX_D_1_5 => txdata_ch1(5),
+  FF_TX_D_1_6 => txdata_ch1(6),
+  FF_TX_D_1_7 => txdata_ch1(7),
+  FF_TX_D_1_8 => tx_k_ch1(0),
+  FF_TX_D_1_9 => tx_force_disp_ch1(0),
+  FF_TX_D_1_10 => tx_disp_sel_ch1(0),
+  FF_TX_D_1_11 => fpsc_vlo,
+  FF_TX_D_1_12 => txdata_ch1(8),
+  FF_TX_D_1_13 => txdata_ch1(9),
+  FF_TX_D_1_14 => txdata_ch1(10),
+  FF_TX_D_1_15 => txdata_ch1(11),
+  FF_TX_D_1_16 => txdata_ch1(12),
+  FF_TX_D_1_17 => txdata_ch1(13),
+  FF_TX_D_1_18 => txdata_ch1(14),
+  FF_TX_D_1_19 => txdata_ch1(15),
+  FF_TX_D_1_20 => tx_k_ch1(1),
+  FF_TX_D_1_21 => tx_force_disp_ch1(1),
+  FF_TX_D_1_22 => tx_disp_sel_ch1(1),
+  FF_TX_D_1_23 => fpsc_vlo,
+  FF_RX_D_1_0 => rxdata_ch1(0),
+  FF_RX_D_1_1 => rxdata_ch1(1),
+  FF_RX_D_1_2 => rxdata_ch1(2),
+  FF_RX_D_1_3 => rxdata_ch1(3),
+  FF_RX_D_1_4 => rxdata_ch1(4),
+  FF_RX_D_1_5 => rxdata_ch1(5),
+  FF_RX_D_1_6 => rxdata_ch1(6),
+  FF_RX_D_1_7 => rxdata_ch1(7),
+  FF_RX_D_1_8 => rx_k_ch1(0),
+  FF_RX_D_1_9 => rx_disp_err_ch1(0),
+  FF_RX_D_1_10 => rx_cv_err_ch1(0),
+  FF_RX_D_1_11 => open,
+  FF_RX_D_1_12 => rxdata_ch1(8),
+  FF_RX_D_1_13 => rxdata_ch1(9),
+  FF_RX_D_1_14 => rxdata_ch1(10),
+  FF_RX_D_1_15 => rxdata_ch1(11),
+  FF_RX_D_1_16 => rxdata_ch1(12),
+  FF_RX_D_1_17 => rxdata_ch1(13),
+  FF_RX_D_1_18 => rxdata_ch1(14),
+  FF_RX_D_1_19 => rxdata_ch1(15),
+  FF_RX_D_1_20 => rx_k_ch1(1),
+  FF_RX_D_1_21 => rx_disp_err_ch1(1),
+  FF_RX_D_1_22 => rx_cv_err_ch1(1),
+  FF_RX_D_1_23 => open,
+
+  FFC_RRST_1 => rx_serdes_rst_ch1_c,
+  FFC_SIGNAL_DETECT_1 => fpsc_vlo,
+  FFC_SB_PFIFO_LP_1 => sb_felb_ch1_c,
+  FFC_PFIFO_CLR_1 => sb_felb_rst_ch1_c,
+  FFC_SB_INV_RX_1 => fpsc_vlo,
+  FFC_PCIE_CT_1 => fpsc_vlo,
+  FFC_PCI_DET_EN_1 => fpsc_vlo,
+  FFC_FB_LOOPBACK_1 => fpsc_vlo,
+  FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
+  FFC_EI_EN_1 => fpsc_vlo,
+  FFC_LANE_TX_RST_1 => tx_pcs_rst_ch_c,
+  FFC_TXPWDNB_1 => tx_pwrup_ch1_c,
+  FFC_LANE_RX_RST_1 => rx_pcs_rst_ch1_c,
+  FFC_RXPWDNB_1 => rx_pwrup_ch1_c,
+  FFS_RLOS_LO_1 => rx_los_low_ch1_sig,
+  FFS_RLOS_HI_1 => open,
+  FFS_PCIE_CON_1 => open,
+  FFS_PCIE_DONE_1 => open,
+  FFS_LS_SYNC_STATUS_1 => lsm_status_ch1_s,
+  FFS_CC_OVERRUN_1 => open,
+  FFS_CC_UNDERRUN_1 => open,
+  FFS_SKP_ADDED_1 => open,
+  FFS_SKP_DELETED_1 => open,
+  FFS_RLOL_1 => rx_cdr_lol_ch1_sig,
+  FFS_RXFBFIFO_ERROR_1 => open,
+  FFS_TXFBFIFO_ERROR_1 => open,
+  LDR_CORE2TX_1 => fpsc_vlo,
+  FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
+  LDR_RX2CORE_1 => open,
+  FFS_CDR_TRAIN_DONE_1 => open,
+  FFC_DIV11_MODE_TX_1 => fpsc_vlo,
+  FFC_RATE_MODE_TX_1 => tx_div2_mode_ch1_c,
+  FFC_DIV11_MODE_RX_1 => fpsc_vlo,
+  FFC_RATE_MODE_RX_1 => rx_div2_mode_ch1_c,
+
+----- CH2 -----
+  HDOUTP2 => open,
+  HDOUTN2 => open,
+  HDINP2 => fpsc_vlo,
+  HDINN2 => fpsc_vlo,
+  PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
+  PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
+  PCIE_RXPOLARITY_2 => fpsc_vlo,
+  PCIE_POWERDOWN_2_0 => fpsc_vlo,
+  PCIE_POWERDOWN_2_1 => fpsc_vlo,
+  PCIE_RXVALID_2 => open,
+  PCIE_PHYSTATUS_2 => open,
+  SCISELCH2 => fpsc_vlo,
+  SCIENCH2 => fpsc_vlo,
+  FF_RXI_CLK_2 => fpsc_vlo,
+  FF_TXI_CLK_2 => fpsc_vlo,
+  FF_EBRD_CLK_2 => fpsc_vlo,
+  FF_RX_F_CLK_2 => open,
+  FF_RX_H_CLK_2 => open,
+  FF_TX_F_CLK_2 => open,
+  FF_TX_H_CLK_2 => open,
+  FFC_CK_CORE_RX_2 => fpsc_vlo,
+  FF_TX_D_2_0 => fpsc_vlo,
+  FF_TX_D_2_1 => fpsc_vlo,
+  FF_TX_D_2_2 => fpsc_vlo,
+  FF_TX_D_2_3 => fpsc_vlo,
+  FF_TX_D_2_4 => fpsc_vlo,
+  FF_TX_D_2_5 => fpsc_vlo,
+  FF_TX_D_2_6 => fpsc_vlo,
+  FF_TX_D_2_7 => fpsc_vlo,
+  FF_TX_D_2_8 => fpsc_vlo,
+  FF_TX_D_2_9 => fpsc_vlo,
+  FF_TX_D_2_10 => fpsc_vlo,
+  FF_TX_D_2_11 => fpsc_vlo,
+  FF_TX_D_2_12 => fpsc_vlo,
+  FF_TX_D_2_13 => fpsc_vlo,
+  FF_TX_D_2_14 => fpsc_vlo,
+  FF_TX_D_2_15 => fpsc_vlo,
+  FF_TX_D_2_16 => fpsc_vlo,
+  FF_TX_D_2_17 => fpsc_vlo,
+  FF_TX_D_2_18 => fpsc_vlo,
+  FF_TX_D_2_19 => fpsc_vlo,
+  FF_TX_D_2_20 => fpsc_vlo,
+  FF_TX_D_2_21 => fpsc_vlo,
+  FF_TX_D_2_22 => fpsc_vlo,
+  FF_TX_D_2_23 => fpsc_vlo,
+  FF_RX_D_2_0 => open,
+  FF_RX_D_2_1 => open,
+  FF_RX_D_2_2 => open,
+  FF_RX_D_2_3 => open,
+  FF_RX_D_2_4 => open,
+  FF_RX_D_2_5 => open,
+  FF_RX_D_2_6 => open,
+  FF_RX_D_2_7 => open,
+  FF_RX_D_2_8 => open,
+  FF_RX_D_2_9 => open,
+  FF_RX_D_2_10 => open,
+  FF_RX_D_2_11 => open,
+  FF_RX_D_2_12 => open,
+  FF_RX_D_2_13 => open,
+  FF_RX_D_2_14 => open,
+  FF_RX_D_2_15 => open,
+  FF_RX_D_2_16 => open,
+  FF_RX_D_2_17 => open,
+  FF_RX_D_2_18 => open,
+  FF_RX_D_2_19 => open,
+  FF_RX_D_2_20 => open,
+  FF_RX_D_2_21 => open,
+  FF_RX_D_2_22 => open,
+  FF_RX_D_2_23 => open,
+
+  FFC_RRST_2 => fpsc_vlo,
+  FFC_SIGNAL_DETECT_2 => fpsc_vlo,
+  FFC_SB_PFIFO_LP_2 => fpsc_vlo,
+  FFC_PFIFO_CLR_2 => fpsc_vlo,
+  FFC_SB_INV_RX_2 => fpsc_vlo,
+  FFC_PCIE_CT_2 => fpsc_vlo,
+  FFC_PCI_DET_EN_2 => fpsc_vlo,
+  FFC_FB_LOOPBACK_2 => fpsc_vlo,
+  FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
+  FFC_EI_EN_2 => fpsc_vlo,
+  FFC_LANE_TX_RST_2 => fpsc_vlo,
+  FFC_TXPWDNB_2 => fpsc_vlo,
+  FFC_LANE_RX_RST_2 => fpsc_vlo,
+  FFC_RXPWDNB_2 => fpsc_vlo,
+  FFS_RLOS_LO_2 => open,
+  FFS_RLOS_HI_2 => open,
+  FFS_PCIE_CON_2 => open,
+  FFS_PCIE_DONE_2 => open,
+  FFS_LS_SYNC_STATUS_2 => open,
+  FFS_CC_OVERRUN_2 => open,
+  FFS_CC_UNDERRUN_2 => open,
+  FFS_SKP_ADDED_2 => open,
+  FFS_SKP_DELETED_2 => open,
+  FFS_RLOL_2 => open,
+  FFS_RXFBFIFO_ERROR_2 => open,
+  FFS_TXFBFIFO_ERROR_2 => open,
+  LDR_CORE2TX_2 => fpsc_vlo,
+  FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
+  LDR_RX2CORE_2 => open,
+  FFS_CDR_TRAIN_DONE_2 => open,
+  FFC_DIV11_MODE_TX_2 => fpsc_vlo,
+  FFC_RATE_MODE_TX_2 => fpsc_vlo,
+  FFC_DIV11_MODE_RX_2 => fpsc_vlo,
+  FFC_RATE_MODE_RX_2 => fpsc_vlo,
+
+----- CH3 -----
+  HDOUTP3 => hdoutp_ch3,
+  HDOUTN3 => hdoutn_ch3,
+  HDINP3 => fpsc_vlo,
+  HDINN3 => fpsc_vlo,
+  PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
+  PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
+  PCIE_RXPOLARITY_3 => fpsc_vlo,
+  PCIE_POWERDOWN_3_0 => fpsc_vlo,
+  PCIE_POWERDOWN_3_1 => fpsc_vlo,
+  PCIE_RXVALID_3 => open,
+  PCIE_PHYSTATUS_3 => open,
+  SCISELCH3 => sci_sel_ch3,
+  SCIENCH3 => fpsc_vhi,
+  FF_RXI_CLK_3 => fpsc_vlo,
+  FF_TXI_CLK_3 => txiclk_ch3,
+  FF_EBRD_CLK_3 => fpsc_vlo,
+  FF_RX_F_CLK_3 => open,
+  FF_RX_H_CLK_3 => open,
+  FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,
+  FF_TX_H_CLK_3 => tx_half_clk_ch3,
+  FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3,
+  FF_TX_D_3_0 => txdata_ch3(0),
+  FF_TX_D_3_1 => txdata_ch3(1),
+  FF_TX_D_3_2 => txdata_ch3(2),
+  FF_TX_D_3_3 => txdata_ch3(3),
+  FF_TX_D_3_4 => txdata_ch3(4),
+  FF_TX_D_3_5 => txdata_ch3(5),
+  FF_TX_D_3_6 => txdata_ch3(6),
+  FF_TX_D_3_7 => txdata_ch3(7),
+  FF_TX_D_3_8 => tx_k_ch3,
+  FF_TX_D_3_9 => tx_force_disp_ch3,
+  FF_TX_D_3_10 => tx_disp_sel_ch3,
+  FF_TX_D_3_11 => fpsc_vlo,
+  FF_TX_D_3_12 => fpsc_vlo,
+  FF_TX_D_3_13 => fpsc_vlo,
+  FF_TX_D_3_14 => fpsc_vlo,
+  FF_TX_D_3_15 => fpsc_vlo,
+  FF_TX_D_3_16 => fpsc_vlo,
+  FF_TX_D_3_17 => fpsc_vlo,
+  FF_TX_D_3_18 => fpsc_vlo,
+  FF_TX_D_3_19 => fpsc_vlo,
+  FF_TX_D_3_20 => fpsc_vlo,
+  FF_TX_D_3_21 => fpsc_vlo,
+  FF_TX_D_3_22 => fpsc_vlo,
+  FF_TX_D_3_23 => fpsc_vlo,
+  FF_RX_D_3_0 => open,
+  FF_RX_D_3_1 => open,
+  FF_RX_D_3_2 => open,
+  FF_RX_D_3_3 => open,
+  FF_RX_D_3_4 => open,
+  FF_RX_D_3_5 => open,
+  FF_RX_D_3_6 => open,
+  FF_RX_D_3_7 => open,
+  FF_RX_D_3_8 => open,
+  FF_RX_D_3_9 => open,
+  FF_RX_D_3_10 => open,
+  FF_RX_D_3_11 => open,
+  FF_RX_D_3_12 => open,
+  FF_RX_D_3_13 => open,
+  FF_RX_D_3_14 => open,
+  FF_RX_D_3_15 => open,
+  FF_RX_D_3_16 => open,
+  FF_RX_D_3_17 => open,
+  FF_RX_D_3_18 => open,
+  FF_RX_D_3_19 => open,
+  FF_RX_D_3_20 => open,
+  FF_RX_D_3_21 => open,
+  FF_RX_D_3_22 => open,
+  FF_RX_D_3_23 => open,
+
+  FFC_RRST_3 => fpsc_vlo,
+  FFC_SIGNAL_DETECT_3 => fpsc_vlo,
+  FFC_SB_PFIFO_LP_3 => fpsc_vlo,
+  FFC_PFIFO_CLR_3 => fpsc_vlo,
+  FFC_SB_INV_RX_3 => fpsc_vlo,
+  FFC_PCIE_CT_3 => fpsc_vlo,
+  FFC_PCI_DET_EN_3 => fpsc_vlo,
+  FFC_FB_LOOPBACK_3 => fpsc_vlo,
+  FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
+  FFC_EI_EN_3 => fpsc_vlo,
+  FFC_LANE_TX_RST_3 => tx_pcs_rst_ch_c,
+  FFC_TXPWDNB_3 => tx_pwrup_ch3_c,
+  FFC_LANE_RX_RST_3 => fpsc_vlo,
+  FFC_RXPWDNB_3 => fpsc_vlo,
+  FFS_RLOS_LO_3 => open,
+  FFS_RLOS_HI_3 => open,
+  FFS_PCIE_CON_3 => open,
+  FFS_PCIE_DONE_3 => open,
+  FFS_LS_SYNC_STATUS_3 => open,
+  FFS_CC_OVERRUN_3 => open,
+  FFS_CC_UNDERRUN_3 => open,
+  FFS_SKP_ADDED_3 => open,
+  FFS_SKP_DELETED_3 => open,
+  FFS_RLOL_3 => open,
+  FFS_RXFBFIFO_ERROR_3 => open,
+  FFS_TXFBFIFO_ERROR_3 => open,
+  LDR_CORE2TX_3 => fpsc_vlo,
+  FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
+  LDR_RX2CORE_3 => open,
+  FFS_CDR_TRAIN_DONE_3 => open,
+  FFC_DIV11_MODE_TX_3 => fpsc_vlo,
+  FFC_RATE_MODE_TX_3 => tx_div2_mode_ch3_c,
+  FFC_DIV11_MODE_RX_3 => fpsc_vlo,
+  FFC_RATE_MODE_RX_3 => fpsc_vlo,
+
+----- Auxilliary ----
+  SCIWDATA7 => sci_wrdata(7),
+  SCIWDATA6 => sci_wrdata(6),
+  SCIWDATA5 => sci_wrdata(5),
+  SCIWDATA4 => sci_wrdata(4),
+  SCIWDATA3 => sci_wrdata(3),
+  SCIWDATA2 => sci_wrdata(2),
+  SCIWDATA1 => sci_wrdata(1),
+  SCIWDATA0 => sci_wrdata(0),
+  SCIADDR5 => sci_addr(5),
+  SCIADDR4 => sci_addr(4),
+  SCIADDR3 => sci_addr(3),
+  SCIADDR2 => sci_addr(2),
+  SCIADDR1 => sci_addr(1),
+  SCIADDR0 => sci_addr(0),
+  SCIRDATA7 => sci_rddata(7),
+  SCIRDATA6 => sci_rddata(6),
+  SCIRDATA5 => sci_rddata(5),
+  SCIRDATA4 => sci_rddata(4),
+  SCIRDATA3 => sci_rddata(3),
+  SCIRDATA2 => sci_rddata(2),
+  SCIRDATA1 => sci_rddata(1),
+  SCIRDATA0 => sci_rddata(0),
+  SCIENAUX => fpsc_vhi,
+  SCISELAUX => sci_sel_quad,
+  SCIRD => sci_rd,
+  SCIWSTN => sci_wrn,
+  CYAWSTN => fpsc_vlo,
+  SCIINT => open,
+  FFC_CK_CORE_TX => fpga_txrefclk,
+  FFC_MACRO_RST => serdes_rst_qd_c,
+  FFC_QUAD_RST => rst_qd_c,
+  FFC_TRST => tx_serdes_rst_c,
+  FFS_PLOL => tx_pll_lol_qd_sig,
+  FFC_SYNC_TOGGLE => tx_sync_qd_c,
+  REFCK2CORE => refclk2fpga_sig,
+  CIN0 => fpsc_vlo,
+  CIN1 => fpsc_vlo,
+  CIN2 => fpsc_vlo,
+  CIN3 => fpsc_vlo,
+  CIN4 => fpsc_vlo,
+  CIN5 => fpsc_vlo,
+  CIN6 => fpsc_vlo,
+  CIN7 => fpsc_vlo,
+  CIN8 => fpsc_vlo,
+  CIN9 => fpsc_vlo,
+  CIN10 => fpsc_vlo,
+  CIN11 => fpsc_vlo,
+  COUT0 => open,
+  COUT1 => open,
+  COUT2 => open,
+  COUT3 => open,
+  COUT4 => open,
+  COUT5 => open,
+  COUT6 => open,
+  COUT7 => open,
+  COUT8 => open,
+  COUT9 => open,
+  COUT10 => open,
+  COUT11 => open,
+  COUT12 => open,
+  COUT13 => open,
+  COUT14 => open,
+  COUT15 => open,
+  COUT16 => open,
+  COUT17 => open,
+  COUT18 => open,
+  COUT19 => open,
+  REFCLK_FROM_NQ => refclk_from_nq,
+  REFCLK_TO_NQ => open);
+
+-- reset sequence for rx
+                                                                                              
+  P2 : PROCESS(fpga_rxrefclk_ch1, rst_n)
+  BEGIN
+     IF (rst_n = '0') THEN
+         refclkdiv2_rx_ch1 <= '0';
+     ELSIF (fpga_rxrefclk_ch1'event and fpga_rxrefclk_ch1 = '1') THEN
+         refclkdiv2_rx_ch1 <= not refclkdiv2_rx_ch1;
+     END IF;
+  END PROCESS;
+                                                                                              
+rx_reset_sm_ch1 : sfp_1_3_200_intrx_reset_sm
+--synopsys translate_off
+  generic map (count_index => 4)
+--synopsys translate_on
+port map  (
+  refclkdiv2 => refclkdiv2_rx_ch1,
+  rst_n => rst_n,
+  rx_cdr_lol_ch_s => rx_cdr_lol_ch1_sig,
+  rx_los_low_ch_s => rx_los_low_ch1_sig,
+  tx_pll_lol_qd_s => tx_pll_lol_qd_sig,
+  rx_pcs_rst_ch_c => rx_pcs_rst_ch1_c,
+  rx_serdes_rst_ch_c => rx_serdes_rst_ch1_c);
+                                                                                              
+                                                                                              
+                                                                                              
+                                                                                              
+  P5 : PROCESS(fpga_txrefclk, rst_n)
+  BEGIN
+     IF (rst_n = '0') THEN
+         refclkdiv2_tx_ch <= '0';
+     ELSIF (fpga_txrefclk'event and fpga_txrefclk = '1') THEN
+         refclkdiv2_tx_ch <= not refclkdiv2_tx_ch;
+     END IF;
+  END PROCESS;
+
+-- reset sequence for tx
+tx_reset_sm_ch : sfp_1_3_200_inttx_reset_sm 
+--synopsys translate_off
+  generic map (count_index => 4)
+--synopsys translate_on
+port map  (
+  rst_n => rst_n,
+  refclkdiv2 => refclkdiv2_tx_ch,
+  tx_pll_lol_qd_s => tx_pll_lol_qd_sig,
+  rst_qd_c => rst_qd_c,
+  tx_pcs_rst_ch_c => tx_pcs_rst_ch_c
+  );
+                                                                                              
+                                                                                              
+--synopsys translate_off
+file_read : PROCESS
+VARIABLE open_status : file_open_status;
+FILE config : text;
+BEGIN
+   file_open (open_status, config, USER_CONFIG_FILE, read_mode);
+   IF (open_status = name_error) THEN
+      report "Auto configuration file for PCS module not found.  PCS internal configuration registers will not be initialized correctly during simulation!"
+      severity ERROR;
+   END IF;
+   wait;
+END PROCESS;
+--synopsys translate_on
+end sfp_1_3_200_int_arch ;
diff --git a/data_concentrator/sources/lattice/ecp3/sync_fifo_512x41_ecp3.ipx b/data_concentrator/sources/lattice/ecp3/sync_fifo_512x41_ecp3.ipx
new file mode 100644
index 0000000..2f5a191
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/sync_fifo_512x41_ecp3.ipx
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="sync_fifo_512x41_ecp3" module="FIFO" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 10 08 11:23:23.424" version="5.0" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="sync_fifo_512x41_ecp3.lpc" type="lpc" modified="2014 10 08 11:23:07.342"/>
+		<File name="sync_fifo_512x41_ecp3.vhd" type="top_level_vhdl" modified="2014 10 08 11:23:07.430"/>
+		<File name="sync_fifo_512x41_ecp3_tmpl.vhd" type="template_vhdl" modified="2014 10 08 11:23:07.430"/>
+		<File name="tb_sync_fifo_512x41_ecp3_tmpl.vhd" type="testbench_vhdl" modified="2014 10 08 11:23:07.441"/>
+  </Package>
+</DiamondModule>
diff --git a/data_concentrator/sources/lattice/ecp3/sync_fifo_512x41_ecp3.lpc b/data_concentrator/sources/lattice/ecp3/sync_fifo_512x41_ecp3.lpc
new file mode 100644
index 0000000..2802e86
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/sync_fifo_512x41_ecp3.lpc
@@ -0,0 +1,48 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO
+CoreRevision=5.0
+ModuleName=sync_fifo_512x41_ecp3
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=10/08/2014
+Time=11:23:07
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=512
+Width=41
+regout=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=0
+EnECC=0
+EnFWFT=0
+
+[Command]
+cmd_line= -w -n sync_fifo_512x41_ecp3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 9 -data_width 41 -num_words 512 -no_enable -pe -1 -pf -1
diff --git a/data_concentrator/sources/lattice/ecp3/sync_fifo_512x41_ecp3.vhd b/data_concentrator/sources/lattice/ecp3/sync_fifo_512x41_ecp3.vhd
new file mode 100644
index 0000000..feebd9e
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/sync_fifo_512x41_ecp3.vhd
@@ -0,0 +1,691 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.0
+--C:\Lattice\diamond\3.2_x64\ispfpga\bin\nt64\scuba.exe -w -n sync_fifo_512x41_ecp3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 41 -depth 512 -no_enable -pe -1 -pf -1 
+
+-- Wed Oct 08 11:23:07 2014
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity sync_fifo_512x41_ecp3 is
+    port (
+        Data: in  std_logic_vector(40 downto 0); 
+        Clock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        Q: out  std_logic_vector(40 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic);
+end sync_fifo_512x41_ecp3;
+
+architecture Structure of sync_fifo_512x41_ecp3 is
+
+    -- internal signal declarations
+    signal invout_1: std_logic;
+    signal invout_0: std_logic;
+    signal rden_i_inv: std_logic;
+    signal fcnt_en: std_logic;
+    signal empty_i: std_logic;
+    signal empty_d: std_logic;
+    signal full_i: std_logic;
+    signal full_d: std_logic;
+    signal ifcount_0: std_logic;
+    signal ifcount_1: std_logic;
+    signal bdcnt_bctr_ci: std_logic;
+    signal ifcount_2: std_logic;
+    signal ifcount_3: std_logic;
+    signal co0: std_logic;
+    signal ifcount_4: std_logic;
+    signal ifcount_5: std_logic;
+    signal co1: std_logic;
+    signal ifcount_6: std_logic;
+    signal ifcount_7: std_logic;
+    signal co2: std_logic;
+    signal ifcount_8: std_logic;
+    signal ifcount_9: std_logic;
+    signal co4: std_logic;
+    signal cnt_con: std_logic;
+    signal co3: std_logic;
+    signal cmp_ci: std_logic;
+    signal rden_i: std_logic;
+    signal co0_1: std_logic;
+    signal co1_1: std_logic;
+    signal co2_1: std_logic;
+    signal co3_1: std_logic;
+    signal cmp_le_1: std_logic;
+    signal cmp_le_1_c: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal fcount_0: std_logic;
+    signal fcount_1: std_logic;
+    signal co0_2: std_logic;
+    signal fcount_2: std_logic;
+    signal fcount_3: std_logic;
+    signal co1_2: std_logic;
+    signal fcount_4: std_logic;
+    signal fcount_5: std_logic;
+    signal co2_2: std_logic;
+    signal fcount_6: std_logic;
+    signal fcount_7: std_logic;
+    signal co3_2: std_logic;
+    signal wren_i: std_logic;
+    signal wren_i_inv: std_logic;
+    signal fcount_8: std_logic;
+    signal fcount_9: std_logic;
+    signal cmp_ge_d1: std_logic;
+    signal cmp_ge_d1_c: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_ctr_ci: std_logic;
+    signal wcount_0: std_logic;
+    signal wcount_1: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co0_3: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_3: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal co1_3: std_logic;
+    signal wcount_4: std_logic;
+    signal wcount_5: std_logic;
+    signal iwcount_6: std_logic;
+    signal iwcount_7: std_logic;
+    signal co2_3: std_logic;
+    signal wcount_6: std_logic;
+    signal wcount_7: std_logic;
+    signal iwcount_8: std_logic;
+    signal iwcount_9: std_logic;
+    signal co4_1: std_logic;
+    signal co3_3: std_logic;
+    signal wcount_8: std_logic;
+    signal wcount_9: std_logic;
+    signal scuba_vlo: std_logic;
+    signal scuba_vhi: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_ctr_ci: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co0_4: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal co1_4: std_logic;
+    signal rcount_4: std_logic;
+    signal rcount_5: std_logic;
+    signal ircount_6: std_logic;
+    signal ircount_7: std_logic;
+    signal co2_4: std_logic;
+    signal rcount_6: std_logic;
+    signal rcount_7: std_logic;
+    signal ircount_8: std_logic;
+    signal ircount_9: std_logic;
+    signal co4_2: std_logic;
+    signal co3_4: std_logic;
+    signal rcount_8: std_logic;
+    signal rcount_9: std_logic;
+
+    -- local component declarations
+    component AGEB2
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; GE: out  std_logic);
+    end component;
+    component ALEB2
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; LE: out  std_logic);
+    end component;
+    component AND2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component CU2
+        port (CI: in  std_logic; PC0: in  std_logic; PC1: in  std_logic; 
+            CO: out  std_logic; NC0: out  std_logic; NC1: out  std_logic);
+    end component;
+    component CB2
+        port (CI: in  std_logic; PC0: in  std_logic; PC1: in  std_logic; 
+            CON: in  std_logic; CO: out  std_logic; NC0: out  std_logic; 
+            NC1: out  std_logic);
+    end component;
+    component FADD2B
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; COUT: out  std_logic; 
+            S0: out  std_logic; S1: out  std_logic);
+    end component;
+    component FD1P3DX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            CD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1S3BX
+        port (D: in  std_logic; CK: in  std_logic; PD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component FD1S3DX
+        port (D: in  std_logic; CK: in  std_logic; CD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component INV
+        port (A: in  std_logic; Z: out  std_logic);
+    end component;
+    component ROM16X1A
+        generic (INITVAL : in std_logic_vector(15 downto 0));
+        port (AD3: in  std_logic; AD2: in  std_logic; AD1: in  std_logic; 
+            AD0: in  std_logic; DO0: out  std_logic);
+    end component;
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component XOR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component PDPW16KC
+        generic (GSR : in String; CSDECODE_R : in String; 
+                CSDECODE_W : in String; REGMODE : in String; 
+                DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+        port (DI0: in  std_logic; DI1: in  std_logic; DI2: in  std_logic; 
+            DI3: in  std_logic; DI4: in  std_logic; DI5: in  std_logic; 
+            DI6: in  std_logic; DI7: in  std_logic; DI8: in  std_logic; 
+            DI9: in  std_logic; DI10: in  std_logic; DI11: in  std_logic; 
+            DI12: in  std_logic; DI13: in  std_logic; 
+            DI14: in  std_logic; DI15: in  std_logic; 
+            DI16: in  std_logic; DI17: in  std_logic; 
+            DI18: in  std_logic; DI19: in  std_logic; 
+            DI20: in  std_logic; DI21: in  std_logic; 
+            DI22: in  std_logic; DI23: in  std_logic; 
+            DI24: in  std_logic; DI25: in  std_logic; 
+            DI26: in  std_logic; DI27: in  std_logic; 
+            DI28: in  std_logic; DI29: in  std_logic; 
+            DI30: in  std_logic; DI31: in  std_logic; 
+            DI32: in  std_logic; DI33: in  std_logic; 
+            DI34: in  std_logic; DI35: in  std_logic; 
+            ADW0: in  std_logic; ADW1: in  std_logic; 
+            ADW2: in  std_logic; ADW3: in  std_logic; 
+            ADW4: in  std_logic; ADW5: in  std_logic; 
+            ADW6: in  std_logic; ADW7: in  std_logic; 
+            ADW8: in  std_logic; BE0: in  std_logic; BE1: in  std_logic; 
+            BE2: in  std_logic; BE3: in  std_logic; CEW: in  std_logic; 
+            CLKW: in  std_logic; CSW0: in  std_logic; 
+            CSW1: in  std_logic; CSW2: in  std_logic; 
+            ADR0: in  std_logic; ADR1: in  std_logic; 
+            ADR2: in  std_logic; ADR3: in  std_logic; 
+            ADR4: in  std_logic; ADR5: in  std_logic; 
+            ADR6: in  std_logic; ADR7: in  std_logic; 
+            ADR8: in  std_logic; ADR9: in  std_logic; 
+            ADR10: in  std_logic; ADR11: in  std_logic; 
+            ADR12: in  std_logic; ADR13: in  std_logic; 
+            CER: in  std_logic; CLKR: in  std_logic; CSR0: in  std_logic; 
+            CSR1: in  std_logic; CSR2: in  std_logic; RST: in  std_logic; 
+            DO0: out  std_logic; DO1: out  std_logic; 
+            DO2: out  std_logic; DO3: out  std_logic; 
+            DO4: out  std_logic; DO5: out  std_logic; 
+            DO6: out  std_logic; DO7: out  std_logic; 
+            DO8: out  std_logic; DO9: out  std_logic; 
+            DO10: out  std_logic; DO11: out  std_logic; 
+            DO12: out  std_logic; DO13: out  std_logic; 
+            DO14: out  std_logic; DO15: out  std_logic; 
+            DO16: out  std_logic; DO17: out  std_logic; 
+            DO18: out  std_logic; DO19: out  std_logic; 
+            DO20: out  std_logic; DO21: out  std_logic; 
+            DO22: out  std_logic; DO23: out  std_logic; 
+            DO24: out  std_logic; DO25: out  std_logic; 
+            DO26: out  std_logic; DO27: out  std_logic; 
+            DO28: out  std_logic; DO29: out  std_logic; 
+            DO30: out  std_logic; DO31: out  std_logic; 
+            DO32: out  std_logic; DO33: out  std_logic; 
+            DO34: out  std_logic; DO35: out  std_logic);
+    end component;
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute RESETMODE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "sync_fifo_512x41_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
+    attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC";
+    attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "sync_fifo_512x41_ecp3.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
+    attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t3: AND2
+        port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+    INV_3: INV
+        port map (A=>full_i, Z=>invout_1);
+
+    AND2_t2: AND2
+        port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+    INV_2: INV
+        port map (A=>empty_i, Z=>invout_0);
+
+    AND2_t1: AND2
+        port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+    XOR2_t0: XOR2
+        port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+    INV_1: INV
+        port map (A=>rden_i, Z=>rden_i_inv);
+
+    INV_0: INV
+        port map (A=>wren_i, Z=>wren_i_inv);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, 
+            AD0=>empty_i, DO0=>empty_d);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, 
+            AD0=>full_i, DO0=>full_d);
+
+    pdp_ram_0_0_1: PDPW16KC
+        generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", 
+        REGMODE=> "NOREG", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
+        port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), 
+            DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), 
+            DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), 
+            DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), 
+            DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), 
+            DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), 
+            DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), 
+            DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), 
+            DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), 
+            DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), 
+            DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), 
+            ADW0=>wcount_0, ADW1=>wcount_1, ADW2=>wcount_2, 
+            ADW3=>wcount_3, ADW4=>wcount_4, ADW5=>wcount_5, 
+            ADW6=>wcount_6, ADW7=>wcount_7, ADW8=>wcount_8, 
+            BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, 
+            BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW0=>scuba_vhi, 
+            CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, 
+            ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, 
+            ADR4=>scuba_vlo, ADR5=>rcount_0, ADR6=>rcount_1, 
+            ADR7=>rcount_2, ADR8=>rcount_3, ADR9=>rcount_4, 
+            ADR10=>rcount_5, ADR11=>rcount_6, ADR12=>rcount_7, 
+            ADR13=>rcount_8, CER=>rden_i, CLKR=>Clock, CSR0=>scuba_vlo, 
+            CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), 
+            DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), 
+            DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), 
+            DO11=>Q(29), DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), 
+            DO15=>Q(33), DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), 
+            DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), 
+            DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), 
+            DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), 
+            DO33=>Q(15), DO34=>Q(16), DO35=>Q(17));
+
+    pdp_ram_0_1_0: PDPW16KC
+        generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", 
+        REGMODE=> "NOREG", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
+        port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), 
+            DI3=>Data(39), DI4=>Data(40), DI5=>scuba_vlo, DI6=>scuba_vlo, 
+            DI7=>scuba_vlo, DI8=>scuba_vlo, DI9=>scuba_vlo, 
+            DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo, 
+            DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo, 
+            DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo, 
+            DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo, 
+            DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo, 
+            DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo, 
+            DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo, 
+            DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo, 
+            DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>wcount_0, 
+            ADW1=>wcount_1, ADW2=>wcount_2, ADW3=>wcount_3, 
+            ADW4=>wcount_4, ADW5=>wcount_5, ADW6=>wcount_6, 
+            ADW7=>wcount_7, ADW8=>wcount_8, BE0=>scuba_vhi, 
+            BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, 
+            CLKW=>Clock, CSW0=>scuba_vhi, CSW1=>scuba_vlo, 
+            CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo, 
+            ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo, 
+            ADR5=>rcount_0, ADR6=>rcount_1, ADR7=>rcount_2, 
+            ADR8=>rcount_3, ADR9=>rcount_4, ADR10=>rcount_5, 
+            ADR11=>rcount_6, ADR12=>rcount_7, ADR13=>rcount_8, 
+            CER=>rden_i, CLKR=>Clock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, 
+            CSR2=>scuba_vlo, RST=>Reset, DO0=>open, DO1=>open, DO2=>open, 
+            DO3=>open, DO4=>open, DO5=>open, DO6=>open, DO7=>open, 
+            DO8=>open, DO9=>open, DO10=>open, DO11=>open, DO12=>open, 
+            DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open, 
+            DO18=>Q(36), DO19=>Q(37), DO20=>Q(38), DO21=>Q(39), 
+            DO22=>Q(40), DO23=>open, DO24=>open, DO25=>open, DO26=>open, 
+            DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open, 
+            DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+    FF_31: FD1P3DX
+        port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_0);
+
+    FF_30: FD1P3DX
+        port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_1);
+
+    FF_29: FD1P3DX
+        port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_2);
+
+    FF_28: FD1P3DX
+        port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_3);
+
+    FF_27: FD1P3DX
+        port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_4);
+
+    FF_26: FD1P3DX
+        port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_5);
+
+    FF_25: FD1P3DX
+        port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_6);
+
+    FF_24: FD1P3DX
+        port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_7);
+
+    FF_23: FD1P3DX
+        port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_8);
+
+    FF_22: FD1P3DX
+        port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_9);
+
+    FF_21: FD1S3BX
+        port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+    FF_20: FD1S3DX
+        port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+    FF_19: FD1P3DX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_0);
+
+    FF_18: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_17: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_16: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_15: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_14: FD1P3DX
+        port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_13: FD1P3DX
+        port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_6);
+
+    FF_12: FD1P3DX
+        port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_7);
+
+    FF_11: FD1P3DX
+        port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_8);
+
+    FF_10: FD1P3DX
+        port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_9);
+
+    FF_9: FD1P3DX
+        port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_0);
+
+    FF_8: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_1);
+
+    FF_7: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_2);
+
+    FF_6: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_3);
+
+    FF_5: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_4);
+
+    FF_4: FD1P3DX
+        port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_5);
+
+    FF_3: FD1P3DX
+        port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_6);
+
+    FF_2: FD1P3DX
+        port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_7);
+
+    FF_1: FD1P3DX
+        port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_8);
+
+    FF_0: FD1P3DX
+        port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_9);
+
+    bdcnt_bctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, 
+            CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
+
+    bdcnt_bctr_0: CB2
+        port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1, 
+            CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1);
+
+    bdcnt_bctr_1: CB2
+        port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con, 
+            CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3);
+
+    bdcnt_bctr_2: CB2
+        port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con, 
+            CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5);
+
+    bdcnt_bctr_3: CB2
+        port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con, 
+            CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7);
+
+    bdcnt_bctr_4: CB2
+        port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con, 
+            CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9);
+
+    e_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, 
+            S1=>open);
+
+    e_cmp_0: ALEB2
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo, 
+            CI=>cmp_ci, LE=>co0_1);
+
+    e_cmp_1: ALEB2
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+    e_cmp_2: ALEB2
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+    e_cmp_3: ALEB2
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+    e_cmp_4: ALEB2
+        port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>co3_1, LE=>cmp_le_1_c);
+
+    a0: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1, 
+            S1=>open);
+
+    g_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, 
+            S1=>open);
+
+    g_cmp_0: AGEB2
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, 
+            CI=>cmp_ci_1, GE=>co0_2);
+
+    g_cmp_1: AGEB2
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, 
+            CI=>co0_2, GE=>co1_2);
+
+    g_cmp_2: AGEB2
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, 
+            CI=>co1_2, GE=>co2_2);
+
+    g_cmp_3: AGEB2
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, 
+            CI=>co2_2, GE=>co3_2);
+
+    g_cmp_4: AGEB2
+        port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i_inv, 
+            CI=>co3_2, GE=>cmp_ge_d1_c);
+
+    a1: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1, 
+            S1=>open);
+
+    w_ctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open, 
+            S1=>open);
+
+    w_ctr_0: CU2
+        port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3, 
+            NC0=>iwcount_0, NC1=>iwcount_1);
+
+    w_ctr_1: CU2
+        port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3, 
+            NC0=>iwcount_2, NC1=>iwcount_3);
+
+    w_ctr_2: CU2
+        port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3, 
+            NC0=>iwcount_4, NC1=>iwcount_5);
+
+    w_ctr_3: CU2
+        port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3, 
+            NC0=>iwcount_6, NC1=>iwcount_7);
+
+    w_ctr_4: CU2
+        port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_1, 
+            NC0=>iwcount_8, NC1=>iwcount_9);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    r_ctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open, 
+            S1=>open);
+
+    r_ctr_0: CU2
+        port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4, 
+            NC0=>ircount_0, NC1=>ircount_1);
+
+    r_ctr_1: CU2
+        port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4, 
+            NC0=>ircount_2, NC1=>ircount_3);
+
+    r_ctr_2: CU2
+        port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4, 
+            NC0=>ircount_4, NC1=>ircount_5);
+
+    r_ctr_3: CU2
+        port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4, 
+            NC0=>ircount_6, NC1=>ircount_7);
+
+    r_ctr_4: CU2
+        port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_2, 
+            NC0=>ircount_8, NC1=>ircount_9);
+
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of sync_fifo_512x41_ecp3 is
+    for Structure
+        for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+        for all:ALEB2 use entity ecp3.ALEB2(V); end for;
+        for all:AND2 use entity ecp3.AND2(V); end for;
+        for all:CU2 use entity ecp3.CU2(V); end for;
+        for all:CB2 use entity ecp3.CB2(V); end for;
+        for all:FADD2B use entity ecp3.FADD2B(V); end for;
+        for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+        for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+        for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+        for all:INV use entity ecp3.INV(V); end for;
+        for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+        for all:VHI use entity ecp3.VHI(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+        for all:XOR2 use entity ecp3.XOR2(V); end for;
+        for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/data_concentrator/sources/lattice/ecp3/sync_fifo_512x41_ecp3_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/sync_fifo_512x41_ecp3_tmpl.vhd
new file mode 100644
index 0000000..29e9a24
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/sync_fifo_512x41_ecp3_tmpl.vhd
@@ -0,0 +1,16 @@
+-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.0
+-- Wed Oct 08 11:23:07 2014
+
+-- parameterized module component declaration
+component sync_fifo_512x41_ecp3
+    port (Data: in  std_logic_vector(40 downto 0); Clock: in  std_logic; 
+        WrEn: in  std_logic; RdEn: in  std_logic; Reset: in  std_logic; 
+        Q: out  std_logic_vector(40 downto 0); Empty: out  std_logic; 
+        Full: out  std_logic);
+end component;
+
+-- parameterized module component instance
+__ : sync_fifo_512x41_ecp3
+    port map (Data(40 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__, 
+        Reset=>__, Q(40 downto 0)=>__, Empty=>__, Full=>__);
diff --git a/data_concentrator/sources/lattice/ecp3/tb_async_fifo_16x32_ecp3_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/tb_async_fifo_16x32_ecp3_tmpl.vhd
new file mode 100644
index 0000000..01344da
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/tb_async_fifo_16x32_ecp3_tmpl.vhd
@@ -0,0 +1,106 @@
+-- VHDL testbench template generated by SCUBA Diamond_2.2_Production (99)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+use IEEE.math_real.all;
+
+use IEEE.numeric_std.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is 
+
+    component async_fifo_16x32_ecp3
+        port (Data : in std_logic_vector(31 downto 0); 
+        WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; 
+        RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; 
+        Q : out std_logic_vector(31 downto 0); Empty: out std_logic; 
+        Full: out std_logic
+    );
+    end component;
+
+    signal Data : std_logic_vector(31 downto 0) := (others => '0');
+    signal WrClock: std_logic := '0';
+    signal RdClock: std_logic := '0';
+    signal WrEn: std_logic := '0';
+    signal RdEn: std_logic := '0';
+    signal Reset: std_logic := '0';
+    signal RPReset: std_logic := '0';
+    signal Q : std_logic_vector(31 downto 0);
+    signal Empty: std_logic;
+    signal Full: std_logic;
+begin
+    u1 : async_fifo_16x32_ecp3
+        port map (Data => Data, WrClock => WrClock, RdClock => RdClock, 
+            WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, 
+            Q => Q, Empty => Empty, Full => Full
+        );
+
+    process
+
+    begin
+      Data <= (others => '0') ;
+      wait for 100 ns;
+      wait until Reset = '0';
+      for i in 0 to 19 loop
+        wait until WrClock'event and WrClock = '1';
+        Data <= Data + '1' after 1 ns;
+      end loop;
+      wait;
+    end process;
+
+    WrClock <= not WrClock after 5.00 ns;
+
+    RdClock <= not RdClock after 5.00 ns;
+
+    process
+
+    begin
+      WrEn <= '0' ;
+      wait for 100 ns;
+      wait until Reset = '0';
+      for i in 0 to 19 loop
+        wait until WrClock'event and WrClock = '1';
+        WrEn <= '1' after 1 ns;
+      end loop;
+      WrEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      RdEn <= '0' ;
+      wait until Reset = '0';
+      wait until WrEn = '1';
+      wait until WrEn = '0';
+      for i in 0 to 19 loop
+        wait until RdClock'event and RdClock = '1';
+        RdEn <= '1' after 1 ns;
+      end loop;
+      RdEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      Reset <= '1' ;
+      wait for 100 ns;
+      Reset <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      RPReset <= '1' ;
+      wait for 100 ns;
+      RPReset <= '0' ;
+      wait;
+    end process;
+
+end architecture test;
diff --git a/data_concentrator/sources/lattice/ecp3/tb_async_fifo_256x66_ecp3_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/tb_async_fifo_256x66_ecp3_tmpl.vhd
new file mode 100644
index 0000000..1a0963e
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/tb_async_fifo_256x66_ecp3_tmpl.vhd
@@ -0,0 +1,106 @@
+-- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.2.0.134
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+use IEEE.math_real.all;
+
+use IEEE.numeric_std.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is 
+
+    component async_fifo_256x66_ecp3
+        port (Data : in std_logic_vector(65 downto 0); 
+        WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; 
+        RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; 
+        Q : out std_logic_vector(65 downto 0); Empty: out std_logic; 
+        Full: out std_logic
+    );
+    end component;
+
+    signal Data : std_logic_vector(65 downto 0) := (others => '0');
+    signal WrClock: std_logic := '0';
+    signal RdClock: std_logic := '0';
+    signal WrEn: std_logic := '0';
+    signal RdEn: std_logic := '0';
+    signal Reset: std_logic := '0';
+    signal RPReset: std_logic := '0';
+    signal Q : std_logic_vector(65 downto 0);
+    signal Empty: std_logic;
+    signal Full: std_logic;
+begin
+    u1 : async_fifo_256x66_ecp3
+        port map (Data => Data, WrClock => WrClock, RdClock => RdClock, 
+            WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, 
+            Q => Q, Empty => Empty, Full => Full
+        );
+
+    process
+
+    begin
+      Data <= (others => '0') ;
+      wait for 100 ns;
+      wait until Reset = '0';
+      for i in 0 to 259 loop
+        wait until WrClock'event and WrClock = '1';
+        Data <= Data + '1' after 1 ns;
+      end loop;
+      wait;
+    end process;
+
+    WrClock <= not WrClock after 5.00 ns;
+
+    RdClock <= not RdClock after 5.00 ns;
+
+    process
+
+    begin
+      WrEn <= '0' ;
+      wait for 100 ns;
+      wait until Reset = '0';
+      for i in 0 to 259 loop
+        wait until WrClock'event and WrClock = '1';
+        WrEn <= '1' after 1 ns;
+      end loop;
+      WrEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      RdEn <= '0' ;
+      wait until Reset = '0';
+      wait until WrEn = '1';
+      wait until WrEn = '0';
+      for i in 0 to 259 loop
+        wait until RdClock'event and RdClock = '1';
+        RdEn <= '1' after 1 ns;
+      end loop;
+      RdEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      Reset <= '1' ;
+      wait for 100 ns;
+      Reset <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      RPReset <= '1' ;
+      wait for 100 ns;
+      RPReset <= '0' ;
+      wait;
+    end process;
+
+end architecture test;
diff --git a/data_concentrator/sources/lattice/ecp3/tb_async_fifo_512x32_ecp3_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/tb_async_fifo_512x32_ecp3_tmpl.vhd
new file mode 100644
index 0000000..1e3aa51
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/tb_async_fifo_512x32_ecp3_tmpl.vhd
@@ -0,0 +1,106 @@
+-- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.2.0.134
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+use IEEE.math_real.all;
+
+use IEEE.numeric_std.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is 
+
+    component async_fifo_512x32_ecp3
+        port (Data : in std_logic_vector(31 downto 0); 
+        WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; 
+        RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; 
+        Q : out std_logic_vector(31 downto 0); Empty: out std_logic; 
+        Full: out std_logic
+    );
+    end component;
+
+    signal Data : std_logic_vector(31 downto 0) := (others => '0');
+    signal WrClock: std_logic := '0';
+    signal RdClock: std_logic := '0';
+    signal WrEn: std_logic := '0';
+    signal RdEn: std_logic := '0';
+    signal Reset: std_logic := '0';
+    signal RPReset: std_logic := '0';
+    signal Q : std_logic_vector(31 downto 0);
+    signal Empty: std_logic;
+    signal Full: std_logic;
+begin
+    u1 : async_fifo_512x32_ecp3
+        port map (Data => Data, WrClock => WrClock, RdClock => RdClock, 
+            WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, 
+            Q => Q, Empty => Empty, Full => Full
+        );
+
+    process
+
+    begin
+      Data <= (others => '0') ;
+      wait for 100 ns;
+      wait until Reset = '0';
+      for i in 0 to 515 loop
+        wait until WrClock'event and WrClock = '1';
+        Data <= Data + '1' after 1 ns;
+      end loop;
+      wait;
+    end process;
+
+    WrClock <= not WrClock after 5.00 ns;
+
+    RdClock <= not RdClock after 5.00 ns;
+
+    process
+
+    begin
+      WrEn <= '0' ;
+      wait for 100 ns;
+      wait until Reset = '0';
+      for i in 0 to 515 loop
+        wait until WrClock'event and WrClock = '1';
+        WrEn <= '1' after 1 ns;
+      end loop;
+      WrEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      RdEn <= '0' ;
+      wait until Reset = '0';
+      wait until WrEn = '1';
+      wait until WrEn = '0';
+      for i in 0 to 515 loop
+        wait until RdClock'event and RdClock = '1';
+        RdEn <= '1' after 1 ns;
+      end loop;
+      RdEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      Reset <= '1' ;
+      wait for 100 ns;
+      Reset <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      RPReset <= '1' ;
+      wait for 100 ns;
+      RPReset <= '0' ;
+      wait;
+    end process;
+
+end architecture test;
diff --git a/data_concentrator/sources/lattice/ecp3/tb_async_fifo_512x99_ecp3_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/tb_async_fifo_512x99_ecp3_tmpl.vhd
new file mode 100644
index 0000000..fe3a7b8
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/tb_async_fifo_512x99_ecp3_tmpl.vhd
@@ -0,0 +1,106 @@
+-- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.2.0.134
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+use IEEE.math_real.all;
+
+use IEEE.numeric_std.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is 
+
+    component async_fifo_512x99_ecp3
+        port (Data : in std_logic_vector(98 downto 0); 
+        WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; 
+        RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; 
+        Q : out std_logic_vector(98 downto 0); Empty: out std_logic; 
+        Full: out std_logic
+    );
+    end component;
+
+    signal Data : std_logic_vector(98 downto 0) := (others => '0');
+    signal WrClock: std_logic := '0';
+    signal RdClock: std_logic := '0';
+    signal WrEn: std_logic := '0';
+    signal RdEn: std_logic := '0';
+    signal Reset: std_logic := '0';
+    signal RPReset: std_logic := '0';
+    signal Q : std_logic_vector(98 downto 0);
+    signal Empty: std_logic;
+    signal Full: std_logic;
+begin
+    u1 : async_fifo_512x99_ecp3
+        port map (Data => Data, WrClock => WrClock, RdClock => RdClock, 
+            WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, 
+            Q => Q, Empty => Empty, Full => Full
+        );
+
+    process
+
+    begin
+      Data <= (others => '0') ;
+      wait for 100 ns;
+      wait until Reset = '0';
+      for i in 0 to 515 loop
+        wait until WrClock'event and WrClock = '1';
+        Data <= Data + '1' after 1 ns;
+      end loop;
+      wait;
+    end process;
+
+    WrClock <= not WrClock after 5.00 ns;
+
+    RdClock <= not RdClock after 5.00 ns;
+
+    process
+
+    begin
+      WrEn <= '0' ;
+      wait for 100 ns;
+      wait until Reset = '0';
+      for i in 0 to 515 loop
+        wait until WrClock'event and WrClock = '1';
+        WrEn <= '1' after 1 ns;
+      end loop;
+      WrEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      RdEn <= '0' ;
+      wait until Reset = '0';
+      wait until WrEn = '1';
+      wait until WrEn = '0';
+      for i in 0 to 515 loop
+        wait until RdClock'event and RdClock = '1';
+        RdEn <= '1' after 1 ns;
+      end loop;
+      RdEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      Reset <= '1' ;
+      wait for 100 ns;
+      Reset <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      RPReset <= '1' ;
+      wait for 100 ns;
+      RPReset <= '0' ;
+      wait;
+    end process;
+
+end architecture test;
diff --git a/data_concentrator/sources/lattice/ecp3/tb_async_fifo_af_512x32_ecp3_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/tb_async_fifo_af_512x32_ecp3_tmpl.vhd
new file mode 100644
index 0000000..b35ce74
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/tb_async_fifo_af_512x32_ecp3_tmpl.vhd
@@ -0,0 +1,107 @@
+-- VHDL testbench template generated by SCUBA Diamond_2.1_Production (100)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+use IEEE.math_real.all;
+
+use IEEE.numeric_std.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is 
+
+    component async_fifo_af_512x32_ecp3
+        port (Data : in std_logic_vector(31 downto 0); 
+        WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; 
+        RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; 
+        Q : out std_logic_vector(31 downto 0); Empty: out std_logic; 
+        Full: out std_logic; AlmostFull: out std_logic
+    );
+    end component;
+
+    signal Data : std_logic_vector(31 downto 0) := (others => '0');
+    signal WrClock: std_logic := '0';
+    signal RdClock: std_logic := '0';
+    signal WrEn: std_logic := '0';
+    signal RdEn: std_logic := '0';
+    signal Reset: std_logic := '0';
+    signal RPReset: std_logic := '0';
+    signal Q : std_logic_vector(31 downto 0);
+    signal Empty: std_logic;
+    signal Full: std_logic;
+    signal AlmostFull: std_logic;
+begin
+    u1 : async_fifo_af_512x32_ecp3
+        port map (Data => Data, WrClock => WrClock, RdClock => RdClock, 
+            WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, 
+            Q => Q, Empty => Empty, Full => Full, AlmostFull => AlmostFull
+        );
+
+    process
+
+    begin
+      Data <= (others => '0') ;
+      wait for 100 ns;
+      wait until Reset = '0';
+      for i in 0 to 515 loop
+        wait until WrClock'event and WrClock = '1';
+        Data <= Data + '1' after 1 ns;
+      end loop;
+      wait;
+    end process;
+
+    WrClock <= not WrClock after 5.00 ns;
+
+    RdClock <= not RdClock after 5.00 ns;
+
+    process
+
+    begin
+      WrEn <= '0' ;
+      wait for 100 ns;
+      wait until Reset = '0';
+      for i in 0 to 515 loop
+        wait until WrClock'event and WrClock = '1';
+        WrEn <= '1' after 1 ns;
+      end loop;
+      WrEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      RdEn <= '0' ;
+      wait until Reset = '0';
+      wait until WrEn = '1';
+      wait until WrEn = '0';
+      for i in 0 to 515 loop
+        wait until RdClock'event and RdClock = '1';
+        RdEn <= '1' after 1 ns;
+      end loop;
+      RdEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      Reset <= '1' ;
+      wait for 100 ns;
+      Reset <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      RPReset <= '1' ;
+      wait for 100 ns;
+      RPReset <= '0' ;
+      wait;
+    end process;
+
+end architecture test;
diff --git a/data_concentrator/sources/lattice/ecp3/tb_async_fifo_af_512x36_ecp3_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/tb_async_fifo_af_512x36_ecp3_tmpl.vhd
new file mode 100644
index 0000000..6fd5d70
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/tb_async_fifo_af_512x36_ecp3_tmpl.vhd
@@ -0,0 +1,107 @@
+-- VHDL testbench template generated by SCUBA Diamond_2.1_Production (100)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+use IEEE.math_real.all;
+
+use IEEE.numeric_std.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is 
+
+    component async_fifo_af_512x36_ecp3
+        port (Data : in std_logic_vector(35 downto 0); 
+        WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; 
+        RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; 
+        Q : out std_logic_vector(35 downto 0); Empty: out std_logic; 
+        Full: out std_logic; AlmostFull: out std_logic
+    );
+    end component;
+
+    signal Data : std_logic_vector(35 downto 0) := (others => '0');
+    signal WrClock: std_logic := '0';
+    signal RdClock: std_logic := '0';
+    signal WrEn: std_logic := '0';
+    signal RdEn: std_logic := '0';
+    signal Reset: std_logic := '0';
+    signal RPReset: std_logic := '0';
+    signal Q : std_logic_vector(35 downto 0);
+    signal Empty: std_logic;
+    signal Full: std_logic;
+    signal AlmostFull: std_logic;
+begin
+    u1 : async_fifo_af_512x36_ecp3
+        port map (Data => Data, WrClock => WrClock, RdClock => RdClock, 
+            WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, 
+            Q => Q, Empty => Empty, Full => Full, AlmostFull => AlmostFull
+        );
+
+    process
+
+    begin
+      Data <= (others => '0') ;
+      wait for 100 ns;
+      wait until Reset = '0';
+      for i in 0 to 515 loop
+        wait until WrClock'event and WrClock = '1';
+        Data <= Data + '1' after 1 ns;
+      end loop;
+      wait;
+    end process;
+
+    WrClock <= not WrClock after 5.00 ns;
+
+    RdClock <= not RdClock after 5.00 ns;
+
+    process
+
+    begin
+      WrEn <= '0' ;
+      wait for 100 ns;
+      wait until Reset = '0';
+      for i in 0 to 515 loop
+        wait until WrClock'event and WrClock = '1';
+        WrEn <= '1' after 1 ns;
+      end loop;
+      WrEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      RdEn <= '0' ;
+      wait until Reset = '0';
+      wait until WrEn = '1';
+      wait until WrEn = '0';
+      for i in 0 to 515 loop
+        wait until RdClock'event and RdClock = '1';
+        RdEn <= '1' after 1 ns;
+      end loop;
+      RdEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      Reset <= '1' ;
+      wait for 100 ns;
+      Reset <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      RPReset <= '1' ;
+      wait for 100 ns;
+      RPReset <= '0' ;
+      wait;
+    end process;
+
+end architecture test;
diff --git a/data_concentrator/sources/lattice/ecp3/tb_async_fifo_nn_16384x36_ecp3_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/tb_async_fifo_nn_16384x36_ecp3_tmpl.vhd
new file mode 100644
index 0000000..b76e864
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/tb_async_fifo_nn_16384x36_ecp3_tmpl.vhd
@@ -0,0 +1,108 @@
+-- VHDL testbench template generated by SCUBA Diamond_2.1_Production (100)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+use IEEE.math_real.all;
+
+use IEEE.numeric_std.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is 
+
+    component async_fifo_nn_16384x36_ecp3
+        port (Data : in std_logic_vector(35 downto 0); 
+        WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; 
+        RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; 
+        Q : out std_logic_vector(35 downto 0); 
+        RCNT : out std_logic_vector(14 downto 0); Empty: out std_logic; 
+        Full: out std_logic
+    );
+    end component;
+
+    signal Data : std_logic_vector(35 downto 0) := (others => '0');
+    signal WrClock: std_logic := '0';
+    signal RdClock: std_logic := '0';
+    signal WrEn: std_logic := '0';
+    signal RdEn: std_logic := '0';
+    signal Reset: std_logic := '0';
+    signal RPReset: std_logic := '0';
+    signal Q : std_logic_vector(35 downto 0);
+    signal RCNT : std_logic_vector(14 downto 0);
+    signal Empty: std_logic;
+    signal Full: std_logic;
+begin
+    u1 : async_fifo_nn_16384x36_ecp3
+        port map (Data => Data, WrClock => WrClock, RdClock => RdClock, 
+            WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, 
+            Q => Q, RCNT => RCNT, Empty => Empty, Full => Full
+        );
+
+    process
+
+    begin
+      Data <= (others => '0') ;
+      wait for 100 ns;
+      wait until Reset = '0';
+      for i in 0 to 16387 loop
+        wait until WrClock'event and WrClock = '1';
+        Data <= Data + '1' after 1 ns;
+      end loop;
+      wait;
+    end process;
+
+    WrClock <= not WrClock after 5.00 ns;
+
+    RdClock <= not RdClock after 5.00 ns;
+
+    process
+
+    begin
+      WrEn <= '0' ;
+      wait for 100 ns;
+      wait until Reset = '0';
+      for i in 0 to 16387 loop
+        wait until WrClock'event and WrClock = '1';
+        WrEn <= '1' after 1 ns;
+      end loop;
+      WrEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      RdEn <= '0' ;
+      wait until Reset = '0';
+      wait until WrEn = '1';
+      wait until WrEn = '0';
+      for i in 0 to 16387 loop
+        wait until RdClock'event and RdClock = '1';
+        RdEn <= '1' after 1 ns;
+      end loop;
+      RdEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      Reset <= '1' ;
+      wait for 100 ns;
+      Reset <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      RPReset <= '1' ;
+      wait for 100 ns;
+      RPReset <= '0' ;
+      wait;
+    end process;
+
+end architecture test;
diff --git a/data_concentrator/sources/lattice/ecp3/tb_async_fifo_nn_4096x103_ecp3_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/tb_async_fifo_nn_4096x103_ecp3_tmpl.vhd
new file mode 100644
index 0000000..cf84e9e
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/tb_async_fifo_nn_4096x103_ecp3_tmpl.vhd
@@ -0,0 +1,108 @@
+-- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.2.0.134
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+use IEEE.math_real.all;
+
+use IEEE.numeric_std.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is 
+
+    component async_fifo_nn_4096x103_ecp3
+        port (Data : in std_logic_vector(102 downto 0); 
+        WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; 
+        RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; 
+        Q : out std_logic_vector(102 downto 0); 
+        WCNT : out std_logic_vector(12 downto 0); Empty: out std_logic; 
+        Full: out std_logic
+    );
+    end component;
+
+    signal Data : std_logic_vector(102 downto 0) := (others => '0');
+    signal WrClock: std_logic := '0';
+    signal RdClock: std_logic := '0';
+    signal WrEn: std_logic := '0';
+    signal RdEn: std_logic := '0';
+    signal Reset: std_logic := '0';
+    signal RPReset: std_logic := '0';
+    signal Q : std_logic_vector(102 downto 0);
+    signal WCNT : std_logic_vector(12 downto 0);
+    signal Empty: std_logic;
+    signal Full: std_logic;
+begin
+    u1 : async_fifo_nn_4096x103_ecp3
+        port map (Data => Data, WrClock => WrClock, RdClock => RdClock, 
+            WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, 
+            Q => Q, WCNT => WCNT, Empty => Empty, Full => Full
+        );
+
+    process
+
+    begin
+      Data <= (others => '0') ;
+      wait for 100 ns;
+      wait until Reset = '0';
+      for i in 0 to 4099 loop
+        wait until WrClock'event and WrClock = '1';
+        Data <= Data + '1' after 1 ns;
+      end loop;
+      wait;
+    end process;
+
+    WrClock <= not WrClock after 5.00 ns;
+
+    RdClock <= not RdClock after 5.00 ns;
+
+    process
+
+    begin
+      WrEn <= '0' ;
+      wait for 100 ns;
+      wait until Reset = '0';
+      for i in 0 to 4099 loop
+        wait until WrClock'event and WrClock = '1';
+        WrEn <= '1' after 1 ns;
+      end loop;
+      WrEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      RdEn <= '0' ;
+      wait until Reset = '0';
+      wait until WrEn = '1';
+      wait until WrEn = '0';
+      for i in 0 to 4099 loop
+        wait until RdClock'event and RdClock = '1';
+        RdEn <= '1' after 1 ns;
+      end loop;
+      RdEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      Reset <= '1' ;
+      wait for 100 ns;
+      Reset <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      RPReset <= '1' ;
+      wait for 100 ns;
+      RPReset <= '0' ;
+      wait;
+    end process;
+
+end architecture test;
diff --git a/data_concentrator/sources/lattice/ecp3/tb_async_fifo_nn_4096x36_ecp3_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/tb_async_fifo_nn_4096x36_ecp3_tmpl.vhd
new file mode 100644
index 0000000..0ae4f9c
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/tb_async_fifo_nn_4096x36_ecp3_tmpl.vhd
@@ -0,0 +1,108 @@
+-- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.2.0.134
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+use IEEE.math_real.all;
+
+use IEEE.numeric_std.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is 
+
+    component async_fifo_nn_4096x36_ecp3
+        port (Data : in std_logic_vector(35 downto 0); 
+        WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; 
+        RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; 
+        Q : out std_logic_vector(35 downto 0); 
+        WCNT : out std_logic_vector(12 downto 0); Empty: out std_logic; 
+        Full: out std_logic
+    );
+    end component;
+
+    signal Data : std_logic_vector(35 downto 0) := (others => '0');
+    signal WrClock: std_logic := '0';
+    signal RdClock: std_logic := '0';
+    signal WrEn: std_logic := '0';
+    signal RdEn: std_logic := '0';
+    signal Reset: std_logic := '0';
+    signal RPReset: std_logic := '0';
+    signal Q : std_logic_vector(35 downto 0);
+    signal WCNT : std_logic_vector(12 downto 0);
+    signal Empty: std_logic;
+    signal Full: std_logic;
+begin
+    u1 : async_fifo_nn_4096x36_ecp3
+        port map (Data => Data, WrClock => WrClock, RdClock => RdClock, 
+            WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, 
+            Q => Q, WCNT => WCNT, Empty => Empty, Full => Full
+        );
+
+    process
+
+    begin
+      Data <= (others => '0') ;
+      wait for 100 ns;
+      wait until Reset = '0';
+      for i in 0 to 4099 loop
+        wait until WrClock'event and WrClock = '1';
+        Data <= Data + '1' after 1 ns;
+      end loop;
+      wait;
+    end process;
+
+    WrClock <= not WrClock after 5.00 ns;
+
+    RdClock <= not RdClock after 5.00 ns;
+
+    process
+
+    begin
+      WrEn <= '0' ;
+      wait for 100 ns;
+      wait until Reset = '0';
+      for i in 0 to 4099 loop
+        wait until WrClock'event and WrClock = '1';
+        WrEn <= '1' after 1 ns;
+      end loop;
+      WrEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      RdEn <= '0' ;
+      wait until Reset = '0';
+      wait until WrEn = '1';
+      wait until WrEn = '0';
+      for i in 0 to 4099 loop
+        wait until RdClock'event and RdClock = '1';
+        RdEn <= '1' after 1 ns;
+      end loop;
+      RdEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      Reset <= '1' ;
+      wait for 100 ns;
+      Reset <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      RPReset <= '1' ;
+      wait for 100 ns;
+      RPReset <= '0' ;
+      wait;
+    end process;
+
+end architecture test;
diff --git a/data_concentrator/sources/lattice/ecp3/tb_async_fifo_nn_th_512x36_ecp3_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/tb_async_fifo_nn_th_512x36_ecp3_tmpl.vhd
new file mode 100644
index 0000000..5ed3164
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/tb_async_fifo_nn_th_512x36_ecp3_tmpl.vhd
@@ -0,0 +1,110 @@
+-- VHDL testbench template generated by SCUBA Diamond_2.1_Production (100)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+use IEEE.math_real.all;
+
+use IEEE.numeric_std.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is 
+
+    component async_fifo_nn_th_512x36_ecp3
+        port (Data : in std_logic_vector(35 downto 0); 
+        WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; 
+        RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; 
+        Q : out std_logic_vector(35 downto 0); 
+        RCNT : out std_logic_vector(9 downto 0); Empty: out std_logic; 
+        Full: out std_logic; AlmostEmpty: out std_logic
+    );
+    end component;
+
+    signal Data : std_logic_vector(35 downto 0) := (others => '0');
+    signal WrClock: std_logic := '0';
+    signal RdClock: std_logic := '0';
+    signal WrEn: std_logic := '0';
+    signal RdEn: std_logic := '0';
+    signal Reset: std_logic := '0';
+    signal RPReset: std_logic := '0';
+    signal Q : std_logic_vector(35 downto 0);
+    signal RCNT : std_logic_vector(9 downto 0);
+    signal Empty: std_logic;
+    signal Full: std_logic;
+    signal AlmostEmpty: std_logic;
+begin
+    u1 : async_fifo_nn_th_512x36_ecp3
+        port map (Data => Data, WrClock => WrClock, RdClock => RdClock, 
+            WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, 
+            Q => Q, RCNT => RCNT, Empty => Empty, Full => Full, 
+            AlmostEmpty => AlmostEmpty
+        );
+
+    process
+
+    begin
+      Data <= (others => '0') ;
+      wait for 100 ns;
+      wait until Reset = '0';
+      for i in 0 to 515 loop
+        wait until WrClock'event and WrClock = '1';
+        Data <= Data + '1' after 1 ns;
+      end loop;
+      wait;
+    end process;
+
+    WrClock <= not WrClock after 5.00 ns;
+
+    RdClock <= not RdClock after 5.00 ns;
+
+    process
+
+    begin
+      WrEn <= '0' ;
+      wait for 100 ns;
+      wait until Reset = '0';
+      for i in 0 to 515 loop
+        wait until WrClock'event and WrClock = '1';
+        WrEn <= '1' after 1 ns;
+      end loop;
+      WrEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      RdEn <= '0' ;
+      wait until Reset = '0';
+      wait until WrEn = '1';
+      wait until WrEn = '0';
+      for i in 0 to 515 loop
+        wait until RdClock'event and RdClock = '1';
+        RdEn <= '1' after 1 ns;
+      end loop;
+      RdEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      Reset <= '1' ;
+      wait for 100 ns;
+      Reset <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      RPReset <= '1' ;
+      wait for 100 ns;
+      RPReset <= '0' ;
+      wait;
+    end process;
+
+end architecture test;
diff --git a/data_concentrator/sources/lattice/ecp3/tb_async_fifo_nn_thfull_512x36_ecp3_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/tb_async_fifo_nn_thfull_512x36_ecp3_tmpl.vhd
new file mode 100644
index 0000000..eea72d1
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/tb_async_fifo_nn_thfull_512x36_ecp3_tmpl.vhd
@@ -0,0 +1,110 @@
+-- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.2.0.134
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+use IEEE.math_real.all;
+
+use IEEE.numeric_std.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is 
+
+    component async_fifo_nn_thfull_512x36_ecp3
+        port (Data : in std_logic_vector(35 downto 0); 
+        WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; 
+        RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; 
+        Q : out std_logic_vector(35 downto 0); 
+        RCNT : out std_logic_vector(9 downto 0); Empty: out std_logic; 
+        Full: out std_logic; AlmostFull: out std_logic
+    );
+    end component;
+
+    signal Data : std_logic_vector(35 downto 0) := (others => '0');
+    signal WrClock: std_logic := '0';
+    signal RdClock: std_logic := '0';
+    signal WrEn: std_logic := '0';
+    signal RdEn: std_logic := '0';
+    signal Reset: std_logic := '0';
+    signal RPReset: std_logic := '0';
+    signal Q : std_logic_vector(35 downto 0);
+    signal RCNT : std_logic_vector(9 downto 0);
+    signal Empty: std_logic;
+    signal Full: std_logic;
+    signal AlmostFull: std_logic;
+begin
+    u1 : async_fifo_nn_thfull_512x36_ecp3
+        port map (Data => Data, WrClock => WrClock, RdClock => RdClock, 
+            WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, 
+            Q => Q, RCNT => RCNT, Empty => Empty, Full => Full, 
+            AlmostFull => AlmostFull
+        );
+
+    process
+
+    begin
+      Data <= (others => '0') ;
+      wait for 100 ns;
+      wait until Reset = '0';
+      for i in 0 to 515 loop
+        wait until WrClock'event and WrClock = '1';
+        Data <= Data + '1' after 1 ns;
+      end loop;
+      wait;
+    end process;
+
+    WrClock <= not WrClock after 5.00 ns;
+
+    RdClock <= not RdClock after 5.00 ns;
+
+    process
+
+    begin
+      WrEn <= '0' ;
+      wait for 100 ns;
+      wait until Reset = '0';
+      for i in 0 to 515 loop
+        wait until WrClock'event and WrClock = '1';
+        WrEn <= '1' after 1 ns;
+      end loop;
+      WrEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      RdEn <= '0' ;
+      wait until Reset = '0';
+      wait until WrEn = '1';
+      wait until WrEn = '0';
+      for i in 0 to 515 loop
+        wait until RdClock'event and RdClock = '1';
+        RdEn <= '1' after 1 ns;
+      end loop;
+      RdEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      Reset <= '1' ;
+      wait for 100 ns;
+      Reset <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      RPReset <= '1' ;
+      wait for 100 ns;
+      RPReset <= '0' ;
+      wait;
+    end process;
+
+end architecture test;
diff --git a/data_concentrator/sources/lattice/ecp3/tb_async_fifo_nn_thfull_512x36_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/tb_async_fifo_nn_thfull_512x36_tmpl.vhd
new file mode 100644
index 0000000..cec3785
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/tb_async_fifo_nn_thfull_512x36_tmpl.vhd
@@ -0,0 +1,110 @@
+-- VHDL testbench template generated by SCUBA Diamond_2.1_Production (100)
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+use IEEE.math_real.all;
+
+use IEEE.numeric_std.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is 
+
+    component async_fifo_nn_thfull_512x36
+        port (Data : in std_logic_vector(35 downto 0); 
+        WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; 
+        RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; 
+        Q : out std_logic_vector(35 downto 0); 
+        RCNT : out std_logic_vector(9 downto 0); Empty: out std_logic; 
+        Full: out std_logic; AlmostFull: out std_logic
+    );
+    end component;
+
+    signal Data : std_logic_vector(35 downto 0) := (others => '0');
+    signal WrClock: std_logic := '0';
+    signal RdClock: std_logic := '0';
+    signal WrEn: std_logic := '0';
+    signal RdEn: std_logic := '0';
+    signal Reset: std_logic := '0';
+    signal RPReset: std_logic := '0';
+    signal Q : std_logic_vector(35 downto 0);
+    signal RCNT : std_logic_vector(9 downto 0);
+    signal Empty: std_logic;
+    signal Full: std_logic;
+    signal AlmostFull: std_logic;
+begin
+    u1 : async_fifo_nn_thfull_512x36
+        port map (Data => Data, WrClock => WrClock, RdClock => RdClock, 
+            WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, 
+            Q => Q, RCNT => RCNT, Empty => Empty, Full => Full, 
+            AlmostFull => AlmostFull
+        );
+
+    process
+
+    begin
+      Data <= (others => '0') ;
+      wait for 100 ns;
+      wait until Reset = '0';
+      for i in 0 to 515 loop
+        wait until WrClock'event and WrClock = '1';
+        Data <= Data + '1' after 1 ns;
+      end loop;
+      wait;
+    end process;
+
+    WrClock <= not WrClock after 5.00 ns;
+
+    RdClock <= not RdClock after 5.00 ns;
+
+    process
+
+    begin
+      WrEn <= '0' ;
+      wait for 100 ns;
+      wait until Reset = '0';
+      for i in 0 to 515 loop
+        wait until WrClock'event and WrClock = '1';
+        WrEn <= '1' after 1 ns;
+      end loop;
+      WrEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      RdEn <= '0' ;
+      wait until Reset = '0';
+      wait until WrEn = '1';
+      wait until WrEn = '0';
+      for i in 0 to 515 loop
+        wait until RdClock'event and RdClock = '1';
+        RdEn <= '1' after 1 ns;
+      end loop;
+      RdEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      Reset <= '1' ;
+      wait for 100 ns;
+      Reset <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      RPReset <= '1' ;
+      wait for 100 ns;
+      RPReset <= '0' ;
+      wait;
+    end process;
+
+end architecture test;
diff --git a/data_concentrator/sources/lattice/ecp3/tb_sync_fifo_512x41_ecp3_tmpl.vhd b/data_concentrator/sources/lattice/ecp3/tb_sync_fifo_512x41_ecp3_tmpl.vhd
new file mode 100644
index 0000000..6b419ba
--- /dev/null
+++ b/data_concentrator/sources/lattice/ecp3/tb_sync_fifo_512x41_ecp3_tmpl.vhd
@@ -0,0 +1,89 @@
+-- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.2.0.134
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+use IEEE.math_real.all;
+
+use IEEE.numeric_std.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is 
+
+    component sync_fifo_512x41_ecp3
+        port (Data : in std_logic_vector(40 downto 0); 
+        Clock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; 
+        Reset: in std_logic; Q : out std_logic_vector(40 downto 0); 
+        Empty: out std_logic; Full: out std_logic
+    );
+    end component;
+
+    signal Data : std_logic_vector(40 downto 0) := (others => '0');
+    signal Clock: std_logic := '0';
+    signal WrEn: std_logic := '0';
+    signal RdEn: std_logic := '0';
+    signal Reset: std_logic := '0';
+    signal Q : std_logic_vector(40 downto 0);
+    signal Empty: std_logic;
+    signal Full: std_logic;
+begin
+    u1 : sync_fifo_512x41_ecp3
+        port map (Data => Data, Clock => Clock, WrEn => WrEn, RdEn => RdEn, 
+            Reset => Reset, Q => Q, Empty => Empty, Full => Full
+        );
+
+    process
+
+    begin
+      Data <= (others => '0') ;
+      for i in 0 to 516 loop
+        wait until Clock'event and Clock = '1';
+        Data <= Data + '1' after 1 ns;
+      end loop;
+      wait;
+    end process;
+
+    Clock <= not Clock after 5.00 ns;
+
+    process
+
+    begin
+      WrEn <= '0' ;
+      wait for 100 ns;
+      wait until Reset = '0';
+      for i in 0 to 516 loop
+        wait until Clock'event and Clock = '1';
+        WrEn <= '1' after 1 ns;
+      end loop;
+      WrEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      RdEn <= '0' ;
+      wait until Reset = '0';
+      wait until WrEn = '1';
+      wait until WrEn = '0';
+      for i in 0 to 514 loop
+        wait until Clock'event and Clock = '1';
+        RdEn <= '1' after 1 ns;
+      end loop;
+      RdEn <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      Reset <= '1' ;
+      wait for 100 ns;
+      Reset <= '0' ;
+      wait;
+    end process;
+
+end architecture test;
diff --git a/data_concentrator/sources/lattice/fifo_FWFT.vhd b/data_concentrator/sources/lattice/fifo_FWFT.vhd
new file mode 100644
index 0000000..e99765d
--- /dev/null
+++ b/data_concentrator/sources/lattice/fifo_FWFT.vhd
@@ -0,0 +1,123 @@
+--------------------------------------------------------------------------------
+--
+-- File Type:    VHDL 
+-- Tool Version: verilog2vhdl 18.00j
+-- Input file was: fifo_FWFT.v.vpp
+-- Command line was: verilog2vhdl fifo_FWFT.v
+-- Date Created: Tue Aug 06 09:53:44 2013
+--
+--------------------------------------------------------------------------------
+
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY ASC;
+USE ASC.numeric_std.all;
+ENTITY fwft_fifo IS	-- 
+    PORT (
+        SIGNAL rst : IN std_logic;	
+        SIGNAL rd_clk : IN std_logic;	
+        SIGNAL rd_en : IN std_logic;	
+        SIGNAL dout : OUT std_logic_vector(35 DOWNTO 0);	
+        SIGNAL empty : OUT std_logic;	
+        SIGNAL wr_clk : IN std_logic;	
+        SIGNAL wr_en : IN std_logic;	
+        SIGNAL din : IN std_logic_vector(35 DOWNTO 0);	
+        SIGNAL full : OUT std_logic;	
+        SIGNAL prog_full : OUT std_logic);	
+END fwft_fifo;
+
+
+
+LIBRARY ASC;
+ARCHITECTURE VeriArch OF fwft_fifo IS
+    USE ASC.FUNCTIONS.ALL;
+    USE ASC.timing.ALL;
+-- Intermediate signal for empty
+    SIGNAL V2V_empty : std_logic;	
+-- Intermediate signal for full
+    SIGNAL V2V_full : std_logic;	
+-- Intermediate signal for prog_full
+    SIGNAL V2V_prog_full : std_logic;	
+-- Intermediate signal for dout
+    SIGNAL V2V_dout : std_logic_vector(35 DOWNTO 0) REGISTER ;	
+
+    SIGNAL fifo_valid : std_logic REGISTER ;	
+
+    SIGNAL middle_valid : std_logic REGISTER ;	
+
+    SIGNAL dout_valid : std_logic REGISTER ;	
+
+    SIGNAL middle_dout : std_logic_vector(35 DOWNTO 0) REGISTER ;	
+
+    SIGNAL fifo_dout : std_logic_vector(35 DOWNTO 0);	
+
+    SIGNAL fifo_empty : std_logic;	
+
+    SIGNAL fifo_rd_en : std_logic;	
+
+    SIGNAL will_update_middle : std_logic;	
+
+    SIGNAL will_update_dout : std_logic;	
+
+    SIGNAL GUARD : boolean:= TRUE;	
+BEGIN
+
+    PROCESS 
+    BEGIN
+        WAIT UNTIL POSEDGE(rd_clk);
+
+        IF to_boolean(rst) THEN
+
+        ELSE
+
+            IF to_boolean(will_update_middle) THEN
+                middle_dout <= fifo_dout;	
+
+            END IF;
+
+            IF to_boolean(will_update_dout) THEN
+                V2V_dout <= to_stdlogicvector(TERNARY(middle_valid, middle_dout, fifo_dout), 36);	
+
+            END IF;
+
+            IF to_boolean(fifo_rd_en) THEN
+                fifo_valid <= to_stdlogic(1);	
+
+            ELSIF to_boolean(To_bit(will_update_middle) /= '0' OR To_bit(will_update_dout) /= '0') THEN
+                fifo_valid <= to_stdlogic(0);	
+
+            END IF;
+
+            IF to_boolean(will_update_middle) THEN
+                middle_valid <= to_stdlogic(1);	
+
+            ELSIF to_boolean(will_update_dout) THEN
+                middle_valid <= to_stdlogic(0);	
+
+            END IF;
+
+            IF to_boolean(will_update_dout) THEN
+                dout_valid <= to_stdlogic(1);	
+
+            ELSIF to_boolean(rd_en) THEN
+                dout_valid <= to_stdlogic(0);	
+
+            END IF;
+        END IF;
+    END PROCESS;
+
+    dout <= V2V_dout;	
+    will_update_middle <= to_stdlogic(To_bit(fifo_valid) /= '0' AND middle_valid = will_update_dout);	
+    will_update_dout <= to_stdlogic((To_bit(middle_valid) /= '0' OR To_bit(fifo_valid) /= '0') AND 
+		(To_bit(rd_en) /= '0' OR NOT (To_bit(dout_valid) /= '0')));	
+    fifo_rd_en <= to_stdlogic(NOT (To_bit(fifo_empty) /= '0') AND NOT (To_bit(middle_valid) /= '0' AND 
+		To_bit(dout_valid) /= '0' AND To_bit(fifo_valid) /= '0'));	
+    V2V_empty <= to_stdlogic(NOT (To_bit(dout_valid) /= '0'));	
+    empty <= V2V_empty;	
+    full <= V2V_full;	
+    prog_full <= V2V_prog_full;	
+END VeriArch;
+
diff --git a/data_concentrator/sources/lattice/med_ecp3_quad_sfp_sync.vhd b/data_concentrator/sources/lattice/med_ecp3_quad_sfp_sync.vhd
new file mode 100644
index 0000000..0d2d3b8
--- /dev/null
+++ b/data_concentrator/sources/lattice/med_ecp3_quad_sfp_sync.vhd
@@ -0,0 +1,879 @@
+--Media interface for Lattice ECP3 using PCS at 2GHz
+
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+--USE IEEE.numeric_std.all;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.med_sync_define.all;
+
+entity med_ecp3_quad_sfp_sync is
+	generic (
+		RX_CLOCK_FROM_FABRIC    : boolean := TRUE
+	);
+  port(
+    CLOCK              : in  std_logic; -- serdes reference clock
+    CLOCKx2            : in  std_logic; -- serdes reference clock *2
+    SYSCLK             : in  std_logic; -- 100 MHz main clock net
+    RESET              : in  std_logic; -- synchronous reset
+    CLEAR              : in  std_logic; -- asynchronous reset
+
+    CLK_RX_HALF_OUT    : out std_logic_vector(0 to 3) := "0000";  --received clock/2
+    CLK_RX_FULL_OUT    : out std_logic_vector(0 to 3) := "0000";  --received clock
+	
+    TX_DATA0           : in std_logic_vector(7 downto 0); -- clock on CLOCK
+    TX_DATA1           : in std_logic_vector(7 downto 0);      
+    TX_DATA2           : in std_logic_vector(7 downto 0);      
+    TX_DATA3           : in std_logic_vector(7 downto 0);	
+    TX_CHAR_K0         : in std_logic;
+    TX_CHAR_K1         : in std_logic;
+    TX_CHAR_K2         : in std_logic;
+    TX_CHAR_K3         : in std_logic;
+    RX_DATA0           : out std_logic_vector(7 downto 0); -- clock on CLOCK
+    RX_DATA1           : out std_logic_vector(7 downto 0);      
+    RX_DATA2           : out std_logic_vector(7 downto 0);      
+    RX_DATA3           : out std_logic_vector(7 downto 0);	
+    RX_CHAR_K0         : out std_logic;
+    RX_CHAR_K1         : out std_logic;
+    RX_CHAR_K2         : out std_logic;
+    RX_CHAR_K3         : out std_logic;
+    RX_ERROR0          : out std_logic;
+    RX_ERROR1          : out std_logic;
+    RX_ERROR2          : out std_logic;
+    RX_ERROR3          : out std_logic;
+
+    --SFP Connection
+    SD_RXD_P_IN        : in std_logic_vector(0 to 3);
+    SD_RXD_N_IN        : in std_logic_vector(0 to 3);
+    SD_TXD_P_OUT       : out std_logic_vector(0 to 3);
+    SD_TXD_N_OUT       : out std_logic_vector(0 to 3);
+    SD_LOS_IN          : in std_logic_vector(0 to 3);  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+    SD_TXDIS_OUT       : out std_logic_vector(0 to 3); -- SFP disable
+	
+    --Control Interface
+    SCI_DATA_IN        : in  std_logic_vector(7 downto 0) := (others => '0');
+    SCI_DATA_OUT       : out std_logic_vector(7 downto 0) := (others => '0');
+    SCI_ADDR           : in  std_logic_vector(8 downto 0) := (others => '0');
+    SCI_READ           : in  std_logic := '0';
+    SCI_WRITE          : in  std_logic := '0';
+    SCI_ACK            : out std_logic := '0';
+    SCI_NACK           : out std_logic := '0';
+	
+    -- Status and control port
+	RESET_DONE         : out std_logic_vector (0 to 3);
+	RX_ALLOW           : out std_logic_vector (0 to 3);
+	TX_ALLOW           : out std_logic_vector (0 to 3);
+	txpll_clocks       : out std_logic_vector(3 downto 0);
+	LEDs_link_ok       : out std_logic_vector(0 to 3);
+	LEDs_rx            : out std_logic_vector(0 to 3); 
+	LEDs_tx            : out std_logic_vector(0 to 3);
+    STAT_OP            : out std_logic_vector (15 downto 0);
+    CTRL_OP            : in  std_logic_vector (15 downto 0) := (others => '0')
+   );
+end entity;
+
+
+architecture med_ecp3_quad_sfp_sync_arch of med_ecp3_quad_sfp_sync is
+
+component serdes_sync_200_full is
+   GENERIC (USER_CONFIG_FILE    :  String := "serdes_sync_200_full.txt");
+ port (
+-- CH0 --
+    hdinp_ch0, hdinn_ch0    :   in std_logic;
+    hdoutp_ch0, hdoutn_ch0   :   out std_logic;
+    sci_sel_ch0    :   in std_logic;
+    rxiclk_ch0    :   in std_logic;
+    txiclk_ch0    :   in std_logic;
+    rx_full_clk_ch0   :   out std_logic;
+    rx_half_clk_ch0   :   out std_logic;
+    tx_full_clk_ch0   :   out std_logic;
+    tx_half_clk_ch0   :   out std_logic;
+    fpga_rxrefclk_ch0    :   in std_logic;
+    txdata_ch0    :   in std_logic_vector (7 downto 0);
+    tx_k_ch0    :   in std_logic;
+    tx_force_disp_ch0    :   in std_logic;
+    tx_disp_sel_ch0    :   in std_logic;
+    rxdata_ch0   :   out std_logic_vector (7 downto 0);
+    rx_k_ch0   :   out std_logic;
+    rx_disp_err_ch0   :   out std_logic;
+    rx_cv_err_ch0   :   out std_logic;
+    rx_serdes_rst_ch0_c    :   in std_logic;
+    sb_felb_ch0_c    :   in std_logic;
+    sb_felb_rst_ch0_c    :   in std_logic;
+    tx_pcs_rst_ch0_c    :   in std_logic;
+    tx_pwrup_ch0_c    :   in std_logic;
+    rx_pcs_rst_ch0_c    :   in std_logic;
+    rx_pwrup_ch0_c    :   in std_logic;
+    rx_los_low_ch0_s   :   out std_logic;
+    lsm_status_ch0_s   :   out std_logic;
+    rx_cdr_lol_ch0_s   :   out std_logic;
+    tx_div2_mode_ch0_c   : in std_logic;
+    rx_div2_mode_ch0_c   : in std_logic;
+-- CH1 --
+    hdinp_ch1, hdinn_ch1    :   in std_logic;
+    hdoutp_ch1, hdoutn_ch1   :   out std_logic;
+    sci_sel_ch1    :   in std_logic;
+    rxiclk_ch1    :   in std_logic;
+    txiclk_ch1    :   in std_logic;
+    rx_full_clk_ch1   :   out std_logic;
+    rx_half_clk_ch1   :   out std_logic;
+    tx_full_clk_ch1   :   out std_logic;
+    tx_half_clk_ch1   :   out std_logic;
+    fpga_rxrefclk_ch1    :   in std_logic;
+    txdata_ch1    :   in std_logic_vector (7 downto 0);
+    tx_k_ch1    :   in std_logic;
+    tx_force_disp_ch1    :   in std_logic;
+    tx_disp_sel_ch1    :   in std_logic;
+    rxdata_ch1   :   out std_logic_vector (7 downto 0);
+    rx_k_ch1   :   out std_logic;
+    rx_disp_err_ch1   :   out std_logic;
+    rx_cv_err_ch1   :   out std_logic;
+    rx_serdes_rst_ch1_c    :   in std_logic;
+    sb_felb_ch1_c    :   in std_logic;
+    sb_felb_rst_ch1_c    :   in std_logic;
+    tx_pcs_rst_ch1_c    :   in std_logic;
+    tx_pwrup_ch1_c    :   in std_logic;
+    rx_pcs_rst_ch1_c    :   in std_logic;
+    rx_pwrup_ch1_c    :   in std_logic;
+    rx_los_low_ch1_s   :   out std_logic;
+    lsm_status_ch1_s   :   out std_logic;
+    rx_cdr_lol_ch1_s   :   out std_logic;
+    tx_div2_mode_ch1_c   : in std_logic;
+    rx_div2_mode_ch1_c   : in std_logic;
+-- CH2 --
+    hdinp_ch2, hdinn_ch2    :   in std_logic;
+    hdoutp_ch2, hdoutn_ch2   :   out std_logic;
+    sci_sel_ch2    :   in std_logic;
+    rxiclk_ch2    :   in std_logic;
+    txiclk_ch2    :   in std_logic;
+    rx_full_clk_ch2   :   out std_logic;
+    rx_half_clk_ch2   :   out std_logic;
+    tx_full_clk_ch2   :   out std_logic;
+    tx_half_clk_ch2   :   out std_logic;
+    fpga_rxrefclk_ch2    :   in std_logic;
+    txdata_ch2    :   in std_logic_vector (7 downto 0);
+    tx_k_ch2    :   in std_logic;
+    tx_force_disp_ch2    :   in std_logic;
+    tx_disp_sel_ch2    :   in std_logic;
+    rxdata_ch2   :   out std_logic_vector (7 downto 0);
+    rx_k_ch2   :   out std_logic;
+    rx_disp_err_ch2   :   out std_logic;
+    rx_cv_err_ch2   :   out std_logic;
+    rx_serdes_rst_ch2_c    :   in std_logic;
+    sb_felb_ch2_c    :   in std_logic;
+    sb_felb_rst_ch2_c    :   in std_logic;
+    tx_pcs_rst_ch2_c    :   in std_logic;
+    tx_pwrup_ch2_c    :   in std_logic;
+    rx_pcs_rst_ch2_c    :   in std_logic;
+    rx_pwrup_ch2_c    :   in std_logic;
+    rx_los_low_ch2_s   :   out std_logic;
+    lsm_status_ch2_s   :   out std_logic;
+    rx_cdr_lol_ch2_s   :   out std_logic;
+    tx_div2_mode_ch2_c   : in std_logic;
+    rx_div2_mode_ch2_c   : in std_logic;
+-- CH3 --
+    hdinp_ch3, hdinn_ch3    :   in std_logic;
+    hdoutp_ch3, hdoutn_ch3   :   out std_logic;
+    sci_sel_ch3    :   in std_logic;
+    rxiclk_ch3    :   in std_logic;
+    txiclk_ch3    :   in std_logic;
+    rx_full_clk_ch3   :   out std_logic;
+    rx_half_clk_ch3   :   out std_logic;
+    tx_full_clk_ch3   :   out std_logic;
+    tx_half_clk_ch3   :   out std_logic;
+    fpga_rxrefclk_ch3    :   in std_logic;
+    txdata_ch3    :   in std_logic_vector (7 downto 0);
+    tx_k_ch3    :   in std_logic;
+    tx_force_disp_ch3    :   in std_logic;
+    tx_disp_sel_ch3    :   in std_logic;
+    rxdata_ch3   :   out std_logic_vector (7 downto 0);
+    rx_k_ch3   :   out std_logic;
+    rx_disp_err_ch3   :   out std_logic;
+    rx_cv_err_ch3   :   out std_logic;
+    rx_serdes_rst_ch3_c    :   in std_logic;
+    sb_felb_ch3_c    :   in std_logic;
+    sb_felb_rst_ch3_c    :   in std_logic;
+    tx_pcs_rst_ch3_c    :   in std_logic;
+    tx_pwrup_ch3_c    :   in std_logic;
+    rx_pcs_rst_ch3_c    :   in std_logic;
+    rx_pwrup_ch3_c    :   in std_logic;
+    rx_los_low_ch3_s   :   out std_logic;
+    lsm_status_ch3_s   :   out std_logic;
+    rx_cdr_lol_ch3_s   :   out std_logic;
+    tx_div2_mode_ch3_c   : in std_logic;
+    rx_div2_mode_ch3_c   : in std_logic;
+---- Miscillaneous ports
+    sci_wrdata    :   in std_logic_vector (7 downto 0);
+    sci_addr    :   in std_logic_vector (5 downto 0);
+    sci_rddata   :   out std_logic_vector (7 downto 0);
+    sci_sel_quad    :   in std_logic;
+    sci_rd    :   in std_logic;
+    sci_wrn    :   in std_logic;
+    fpga_txrefclk  :   in std_logic;
+    tx_serdes_rst_c    :   in std_logic;
+    tx_pll_lol_qd_s   :   out std_logic;
+    tx_sync_qd_c    :   in std_logic;
+    rst_qd_c    :   in std_logic;
+    serdes_rst_qd_c    :   in std_logic);
+end component;
+
+component async_fifo_16x9 is
+port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(8 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(8 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic
+	);
+end component;
+
+
+-- Placer Directives
+attribute HGROUP : string;
+-- for whole architecture
+attribute HGROUP of med_ecp3_quad_sfp_sync_arch : architecture  is "media_interface_group";
+attribute syn_sharing : string;
+attribute syn_sharing of med_ecp3_quad_sfp_sync_arch : architecture is "off";
+attribute syn_keep     : boolean;
+attribute syn_preserve : boolean;
+
+type array_4x2_type is array(0 to 3) of std_logic_vector(1 downto 0);
+type array_4x4_type is array(0 to 3) of std_logic_vector(3 downto 0);
+type array_4x8_type is array(0 to 3) of std_logic_vector(7 downto 0);
+type array_4x16_type is array(0 to 3) of std_logic_vector(15 downto 0);
+type array_4x19_type is array(0 to 3) of std_logic_vector(18 downto 0);
+
+
+signal rxclk_i           : std_logic_vector(0 to 3);
+signal clk_rx_full       : std_logic_vector(0 to 3);
+signal clk_rx_half       : std_logic_vector(0 to 3);
+signal clk_rx_act_full   : std_logic_vector(0 to 3);
+signal clk_rx_act_half   : std_logic_vector(0 to 3);
+signal clk_tx_full0      : std_logic;
+signal clk_tx_full1      : std_logic;
+signal clk_tx_full2      : std_logic;
+signal clk_tx_full3      : std_logic;
+signal clk_tx_half       : std_logic_vector(0 to 3);
+
+signal rx_rst_n          : std_logic_vector(0 to 3);
+signal rx_rst            : std_logic_vector(0 to 3);
+signal tx_rst_n          : std_logic_vector(0 to 3);
+signal tx_rst            : std_logic_vector(0 to 3);
+signal rx_serdes_rst     : std_logic_vector(0 to 3);
+signal tx_serdes_rst     : std_logic;
+signal tx_pcs_rst        : std_logic_vector(0 to 3);
+signal rx_pcs_rst        : std_logic_vector(0 to 3);
+signal rst_qd            : std_logic;
+signal rst_qd_S          : std_logic_vector(0 to 3);
+signal serdes_rst_qd     : std_logic;
+signal sd_los_i          : std_logic_vector(0 to 3);
+
+signal rx_los_low        : std_logic_vector(0 to 3);
+signal lsm_status        : std_logic_vector(0 to 3);
+signal rx_cdr_lol        : std_logic_vector(0 to 3);
+signal tx_pll_lol        : std_logic;
+
+signal sci_ch_i          : std_logic_vector(3 downto 0);
+signal sci_qd_i          : std_logic;
+signal sci_reg_i         : std_logic;
+signal sci_addr_i        : std_logic_vector(8 downto 0);
+signal sci_data_in_i     : std_logic_vector(7 downto 0);
+signal sci_data_out_i    : std_logic_vector(7 downto 0);
+signal sci_read_i        : std_logic;
+signal sci_write_i       : std_logic;
+
+signal wa_position        : std_logic_vector(15 downto 0) := x"FFFF";
+signal tx_allow_i         : std_logic_vector(0 to 3);
+signal rx_allow_i         : std_logic_vector(0 to 3);
+signal tx_allow_q         : std_logic_vector(0 to 3);
+signal rx_allow_q         : std_logic_vector(0 to 3);
+
+signal rx_fsm_state       : array_4x4_type;
+signal tx_fsm_state       : array_4x4_type;
+signal debug_reg          : std_logic_vector(63 downto 0);
+
+type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
+signal sci_state          : sci_ctrl;
+signal sci_timer          : unsigned(12 downto 0) := (others => '0');
+signal start_timer        : array_4x19_type := (others => (others => '0'));
+
+signal led_ok                 : std_logic_vector(0 to 3);
+signal led_tx, last_led_tx    : std_logic_vector(0 to 3);
+signal led_rx, last_led_rx    : std_logic_vector(0 to 3);
+signal timer    : unsigned(20 downto 0);
+
+
+signal rx_rst_n_i                : std_logic_vector(0 to 3) := (others => '0');
+
+signal tx_char_k              : std_logic_vector(0 to 3) := (others => '0');
+signal tx_data_i              : array_4x8_type;
+signal tx_sync_qd_c           : std_logic;
+signal tx_sync_qd_c_S         : std_logic := '0';
+		
+signal rx_char_k              : std_logic_vector(0 to 3) := (others => '0');
+signal rx_data_i              : array_4x8_type;
+signal rx_error_i             : std_logic_vector(0 to 3) := (others => '0');
+
+signal txdelaycounter_i       : array_4x8_type := (others => (others => '0'));
+
+attribute syn_keep of tx_sync_qd_c     : signal is true; 
+attribute syn_preserve of tx_sync_qd_c     : signal is true; 
+
+attribute syn_keep of clk_tx_full0     : signal is true; 
+attribute syn_preserve of clk_tx_full0     : signal is true; 
+attribute syn_keep of clk_tx_full1     : signal is true; 
+attribute syn_preserve of clk_tx_full1     : signal is true; 
+attribute syn_keep of clk_tx_full2     : signal is true; 
+attribute syn_preserve of clk_tx_full2     : signal is true; 
+attribute syn_keep of clk_tx_full3     : signal is true; 
+attribute syn_preserve of clk_tx_full3     : signal is true; 
+
+
+begin
+
+txpll_clocks(0) <= clk_tx_full0;
+txpll_clocks(1) <= clk_tx_full1;
+txpll_clocks(2) <= clk_tx_full2;
+txpll_clocks(3) <= clk_tx_full3;
+
+-- txpll_clocks(0) <= clk_tx_half(0);
+-- txpll_clocks(1) <= clk_tx_half(1);
+-- txpll_clocks(2) <= clk_tx_half(2);
+-- txpll_clocks(3) <= clk_tx_half(3);
+
+rxclk_i <= CLOCKx2 & CLOCKx2 & CLOCKx2 & CLOCKx2; 
+clk_rx_act_half <= CLOCK & CLOCK & CLOCK & CLOCK;
+clk_rx_act_full <= CLOCKx2 & CLOCKx2 & CLOCKx2 & CLOCKx2;
+
+CLK_RX_HALF_OUT <= clk_rx_act_half;
+CLK_RX_FULL_OUT <= clk_rx_act_full;
+
+SD_TXDIS_OUT <= "0000"; 
+RX_ALLOW <= rx_allow_i;
+TX_ALLOW <= tx_allow_i;
+
+process(CLOCKx2)
+begin
+	if (rising_edge(CLOCKx2)) then 
+		tx_data_i(0) <= TX_DATA0;
+		tx_data_i(1) <= TX_DATA1;
+		tx_data_i(2) <= TX_DATA2;
+		tx_data_i(3) <= TX_DATA3;
+		tx_char_k(0) <= TX_CHAR_K0;
+		tx_char_k(1) <= TX_CHAR_K1;
+		tx_char_k(2) <= TX_CHAR_K2;
+		tx_char_k(3) <= TX_CHAR_K3;
+	end if;
+end process;
+
+
+process(clk_rx_act_full(0))
+begin
+	if (rising_edge(clk_rx_act_full(0))) then
+		RX_CHAR_K0 <= rx_char_k(0);
+		RX_DATA0 <= rx_data_i(0);
+		RX_ERROR0 <= rx_error_i(0);
+	end if;
+end process;
+process(clk_rx_act_full(1))
+begin
+	if (rising_edge(clk_rx_act_full(1))) then
+		RX_CHAR_K1 <= rx_char_k(1);
+		RX_DATA1 <= rx_data_i(1);
+		RX_ERROR1 <= rx_error_i(1);
+	end if;
+end process;
+process(clk_rx_act_full(2))
+begin
+	if (rising_edge(clk_rx_act_full(2))) then
+		RX_CHAR_K2 <= rx_char_k(2);
+		RX_DATA2 <= rx_data_i(2);
+		RX_ERROR2 <= rx_error_i(2);
+	end if;
+end process;
+process(clk_rx_act_full(3))
+begin
+	if (rising_edge(clk_rx_act_full(3))) then
+		RX_CHAR_K3 <= rx_char_k(3);
+		RX_DATA3 <= rx_data_i(3);
+		RX_ERROR3 <= rx_error_i(3);
+	end if;
+end process;
+		
+
+
+-------------------------------------------------      
+-- Serdes
+-------------------------------------------------      
+
+THE_SERDES : serdes_sync_200_full 
+  port map(
+    hdinp_ch0            => SD_RXD_P_IN(0),
+    hdinn_ch0            => SD_RXD_N_IN(0),
+    hdoutp_ch0           => SD_TXD_P_OUT(0),
+    hdoutn_ch0           => SD_TXD_N_OUT(0),
+    rxiclk_ch0           => rxclk_i(0),
+    txiclk_ch0           => CLOCKx2, -- clk_tx_full0, --// CLOCKx2,
+    rx_full_clk_ch0      => clk_rx_full(0),
+    rx_half_clk_ch0      => clk_rx_half(0),
+    tx_full_clk_ch0      => clk_tx_full0,
+    tx_half_clk_ch0      => clk_tx_half(0),
+    fpga_rxrefclk_ch0    => CLOCKx2,
+    txdata_ch0           => tx_data_i(0),
+    tx_k_ch0             => tx_char_k(0),
+    tx_force_disp_ch0    => '0',
+    tx_disp_sel_ch0      => '0',
+    rxdata_ch0           => rx_data_i(0),
+    rx_k_ch0             => rx_char_k(0),
+    rx_disp_err_ch0      => open,
+    rx_cv_err_ch0        => rx_error_i(0),
+    rx_serdes_rst_ch0_c  => rx_serdes_rst(0),
+    sb_felb_ch0_c        => '0',
+    sb_felb_rst_ch0_c    => '0',
+    tx_pcs_rst_ch0_c     => tx_pcs_rst(0),
+    tx_pwrup_ch0_c       => '1',
+    rx_pcs_rst_ch0_c     => rx_pcs_rst(0),
+    rx_pwrup_ch0_c       => '1',
+    rx_los_low_ch0_s     => rx_los_low(0),
+    lsm_status_ch0_s     => lsm_status(0),
+    rx_cdr_lol_ch0_s     => rx_cdr_lol(0),
+    tx_div2_mode_ch0_c   => '0',
+    rx_div2_mode_ch0_c   => '0',
+    
+    hdinp_ch1            => SD_RXD_P_IN(1),
+    hdinn_ch1            => SD_RXD_N_IN(1),
+    hdoutp_ch1           => SD_TXD_P_OUT(1),
+    hdoutn_ch1           => SD_TXD_N_OUT(1),
+    rxiclk_ch1           => rxclk_i(1),
+    txiclk_ch1           => CLOCKx2, -- clk_tx_full1, --// CLOCKx2,
+    rx_full_clk_ch1      => clk_rx_full(1),
+    rx_half_clk_ch1      => clk_rx_half(1),
+    tx_full_clk_ch1      => clk_tx_full1,
+    tx_half_clk_ch1      => clk_tx_half(1),
+    fpga_rxrefclk_ch1    => CLOCKx2,
+    txdata_ch1           => tx_data_i(1),
+    tx_k_ch1             => tx_char_k(1),
+    tx_force_disp_ch1    => '0',
+    tx_disp_sel_ch1      => '0',
+    rxdata_ch1           => rx_data_i(1),
+    rx_k_ch1             => rx_char_k(1),
+    rx_disp_err_ch1      => open,
+    rx_cv_err_ch1        => rx_error_i(1),
+    rx_serdes_rst_ch1_c  => rx_serdes_rst(1),
+    sb_felb_ch1_c        => '0',
+    sb_felb_rst_ch1_c    => '0',
+    tx_pcs_rst_ch1_c     => tx_pcs_rst(1),
+    tx_pwrup_ch1_c       => '1',
+    rx_pcs_rst_ch1_c     => rx_pcs_rst(1),
+    rx_pwrup_ch1_c       => '1',
+    rx_los_low_ch1_s     => rx_los_low(1),
+    lsm_status_ch1_s     => lsm_status(1),
+    rx_cdr_lol_ch1_s     => rx_cdr_lol(1),
+    tx_div2_mode_ch1_c   => '0',
+    rx_div2_mode_ch1_c   => '0',
+
+    hdinp_ch2            => SD_RXD_P_IN(2),
+    hdinn_ch2            => SD_RXD_N_IN(2),
+    hdoutp_ch2           => SD_TXD_P_OUT(2),
+    hdoutn_ch2           => SD_TXD_N_OUT(2),
+    rxiclk_ch2           => rxclk_i(2),
+    txiclk_ch2           => CLOCKx2, -- clk_tx_full2, --// ,
+    rx_full_clk_ch2      => clk_rx_full(2),
+    rx_half_clk_ch2      => clk_rx_half(2),
+    tx_full_clk_ch2      => clk_tx_full2,
+    tx_half_clk_ch2      => clk_tx_half(2),
+    fpga_rxrefclk_ch2    => CLOCKx2,
+    txdata_ch2           => tx_data_i(2),
+    tx_k_ch2             => tx_char_k(2),
+    tx_force_disp_ch2    => '0',
+    tx_disp_sel_ch2      => '0',
+    rxdata_ch2           => rx_data_i(2),
+    rx_k_ch2             => rx_char_k(2),
+    rx_disp_err_ch2      => open,
+    rx_cv_err_ch2        => rx_error_i(2),
+    rx_serdes_rst_ch2_c  => rx_serdes_rst(2),
+    sb_felb_ch2_c        => '0',
+    sb_felb_rst_ch2_c    => '0',
+    tx_pcs_rst_ch2_c     => tx_pcs_rst(2),
+    tx_pwrup_ch2_c       => '1',
+    rx_pcs_rst_ch2_c     => rx_pcs_rst(2),
+    rx_pwrup_ch2_c       => '1',
+    rx_los_low_ch2_s     => rx_los_low(2),
+    lsm_status_ch2_s     => lsm_status(2),
+    rx_cdr_lol_ch2_s     => rx_cdr_lol(2),
+    tx_div2_mode_ch2_c   => '0',
+    rx_div2_mode_ch2_c   => '0',
+    
+    hdinp_ch3            => SD_RXD_P_IN(3),
+    hdinn_ch3            => SD_RXD_N_IN(3),
+    hdoutp_ch3           => SD_TXD_P_OUT(3),
+    hdoutn_ch3           => SD_TXD_N_OUT(3),
+    rxiclk_ch3           => rxclk_i(3),
+    txiclk_ch3           => CLOCKx2, -- clk_tx_full3, --// CLOCKx2,
+    rx_full_clk_ch3      => clk_rx_full(3),
+    rx_half_clk_ch3      => clk_rx_half(3),
+    tx_full_clk_ch3      => clk_tx_full3,
+    tx_half_clk_ch3      => clk_tx_half(3),
+    fpga_rxrefclk_ch3    => CLOCKx2,
+    txdata_ch3           => tx_data_i(3),
+    tx_k_ch3             => tx_char_k(3),
+    tx_force_disp_ch3    => '0',
+    tx_disp_sel_ch3      => '0',
+    rxdata_ch3           => rx_data_i(3),
+    rx_k_ch3             => rx_char_k(3),
+    rx_disp_err_ch3      => open,
+    rx_cv_err_ch3        => rx_error_i(3),
+    rx_serdes_rst_ch3_c  => rx_serdes_rst(3),
+    sb_felb_ch3_c        => '0',
+    sb_felb_rst_ch3_c    => '0',
+    tx_pcs_rst_ch3_c     => tx_pcs_rst(3),
+    tx_pwrup_ch3_c       => '1',
+    rx_pcs_rst_ch3_c     => rx_pcs_rst(3),
+    rx_pwrup_ch3_c       => '1',
+    rx_los_low_ch3_s     => rx_los_low(3),
+    lsm_status_ch3_s     => lsm_status(3),
+    rx_cdr_lol_ch3_s     => rx_cdr_lol(3),
+    tx_div2_mode_ch3_c   => '0',
+    rx_div2_mode_ch3_c   => '0', 
+    
+    SCI_WRDATA           => sci_data_in_i,
+    SCI_RDDATA           => sci_data_out_i,
+    SCI_ADDR             => sci_addr_i(5 downto 0),
+    SCI_SEL_QUAD         => sci_qd_i,
+    SCI_SEL_CH0          => sci_ch_i(0),
+    SCI_SEL_CH1          => sci_ch_i(1),
+    SCI_SEL_CH2          => sci_ch_i(2),
+    SCI_SEL_CH3          => sci_ch_i(3),
+    SCI_RD               => sci_read_i,
+    SCI_WRN              => sci_write_i,
+    
+    fpga_txrefclk        => CLOCKx2,
+    tx_serdes_rst_c      => tx_serdes_rst,
+    tx_pll_lol_qd_s      => tx_pll_lol,
+    tx_sync_qd_c         => tx_sync_qd_c, -- ?? Multiple channel transmit synchronization
+    rst_qd_c             => rst_qd,
+    serdes_rst_qd_c      => serdes_rst_qd
+
+    );
+--	rst_qd <= CLEAR;
+    tx_serdes_rst <= '0'; --no function
+    serdes_rst_qd <= '0'; --included in rst_qd
+
+    
+-------------------------------------------------      
+-- Reset FSM & Link states
+-------------------------------------------------
+synctox2: process(CLOCKx2)
+begin
+	if (rising_edge(CLOCKx2)) then 
+		if rst_qd_S/="0000" then
+			rst_qd <= '1';
+		else
+			rst_qd <= '0';
+		end if;
+		tx_sync_qd_c <= tx_sync_qd_c_S;
+	end if;
+end process;
+
+process(CLOCK)
+variable prev_state_ok : std_logic_vector(0 to 3) := "0000";
+variable cntr : std_logic_vector(3 downto 0) := "0000";
+begin
+	if (rising_edge(CLOCK)) then 
+		if ((tx_fsm_state(0)=x"5") and (prev_state_ok(0)='0')) or
+		   ((tx_fsm_state(1)=x"5") and (prev_state_ok(1)='0')) or
+		   ((tx_fsm_state(2)=x"5") and (prev_state_ok(2)='0')) or
+		   ((tx_fsm_state(3)=x"5") and (prev_state_ok(3)='0')) then
+			tx_sync_qd_c_S <= not tx_sync_qd_c_S;
+			cntr := (others => '0');
+		else -- double toggle, necessary?
+			if cntr="1110" then
+				tx_sync_qd_c_S <= not tx_sync_qd_c_S;
+			end if;
+			if cntr/="1111" then
+				cntr := cntr+1;
+			end if;			
+		end if;
+		for i in 0 to 3 loop
+			if (tx_fsm_state(i)=x"5") then
+				prev_state_ok(i) := '1';
+			else
+				prev_state_ok(i) := '0';
+			end if;
+		end loop;
+	end if;
+end process;
+
+GENERATE_RESET_FSM: for i in 0 to 3 generate  
+
+tx_rst_n(i) <= not (CLEAR);
+tx_rst(i)   <=     (CLEAR);
+rx_rst_n(i) <= not (CLEAR or sd_los_i(i));
+rx_rst(i)   <=     (CLEAR or sd_los_i(i));
+sd_los_i(i) <= SD_LOS_IN(i); -- when rising_edge(SYSCLK);	
+
+PROC_ALLOW_TX : process(CLOCK)
+begin
+	if (rising_edge(CLOCK)) then 
+		tx_allow_i(i) <= '0';
+		if tx_fsm_state(i) = x"5" then
+			RESET_DONE(i) <= '1';
+			if txdelaycounter_i(i)(txdelaycounter_i(i)'left)='0' then
+				txdelaycounter_i(i) <= txdelaycounter_i(i)+1;
+			else
+				tx_allow_i(i) <= '1';
+			end if;
+		else
+			txdelaycounter_i(i) <= (others => '0');
+			RESET_DONE(i) <= '0';
+		end if;
+	end if;
+end process;
+
+THE_RX_FSM : rx_reset_fsm
+  port map(
+    RST_N               => rx_rst_n_i(i),
+    RX_REFCLK           => CLOCK,
+    TX_PLL_LOL_QD_S     => tx_pll_lol,
+    RX_SERDES_RST_CH_C  => rx_serdes_rst(i),
+    RX_CDR_LOL_CH_S     => rx_cdr_lol(i),
+    RX_LOS_LOW_CH_S     => rx_los_low(i),
+    RX_PCS_RST_CH_C     => rx_pcs_rst(i),
+    WA_POSITION         => "0000", -- for master
+    STATE_OUT           => rx_fsm_state(i) -- ready when x"6"
+    );
+
+rx_rst_n_i(i) <= '0' when rx_rst_n(i)='0' else '1';
+
+THE_TX_FSM : tx_reset_fsm
+  port map(
+    RST_N           => tx_rst_n(i),
+    TX_REFCLK       => CLOCK,
+    TX_PLL_LOL_QD_S => tx_pll_lol,
+    RST_QD_C        => rst_qd_S(i), -- //
+    TX_PCS_RST_CH_C => tx_pcs_rst(i),
+    STATE_OUT       => tx_fsm_state(i) -- ready when x"5"
+    );
+
+--Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable
+PROC_ALLOW : process(CLOCK)
+begin
+	if (rising_edge(CLOCK)) then 
+		if rx_fsm_state(i) = x"6" and (start_timer(i)(start_timer(i)'left) = '1') then
+			rx_allow_i(i) <= '1';
+		else
+			rx_allow_i(i) <= '0';
+		end if;
+		if rx_fsm_state(i) = x"6" and (start_timer(i)(start_timer(i)'left) = '1') then
+--			tx_allow_i(i) <= '1';
+		else
+--			tx_allow_i(i) <= '0';
+		end if;
+	end if;
+end process;
+
+PROC_START_TIMER : process(CLOCK)
+begin
+	if (rising_edge(CLOCK)) then 
+		if (rx_fsm_state(i) = x"6") then
+			if start_timer(i)(start_timer(i)'left) = '0' then
+				start_timer(i) <= start_timer(i) + 1;
+			end if;  
+		else
+			start_timer(i) <= (others => '0');
+		end if;
+	end if;
+end process;
+
+end generate;
+    
+	
+-------------------------------------------------      
+-- SCI
+-------------------------------------------------      
+--gives access to serdes config port from slow control and reads word alignment every ~ 40 us
+PROC_SCI_CTRL: process 
+  variable cnt : integer range 0 to 4 := 0;
+begin
+  wait until rising_edge(SYSCLK);
+  SCI_ACK <= '0';
+  case sci_state is
+    when IDLE =>
+      sci_ch_i        <= x"0";
+      sci_qd_i        <= '0';
+      sci_reg_i       <= '0';
+      sci_read_i      <= '0';
+      sci_write_i     <= '0';
+      sci_timer       <= sci_timer + 1;
+      if SCI_READ = '1' or SCI_WRITE = '1' then
+        sci_ch_i(0)   <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+        sci_ch_i(1)   <=     SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+        sci_ch_i(2)   <= not SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
+        sci_ch_i(3)   <=     SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
+        sci_qd_i      <= not SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
+        sci_reg_i     <=     SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
+        sci_addr_i    <= SCI_ADDR;
+        sci_data_in_i <= SCI_DATA_IN;
+        sci_read_i    <= SCI_READ  and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
+        sci_write_i   <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
+        sci_state     <= SCTRL;
+      elsif sci_timer(sci_timer'left) = '1' then
+        sci_timer     <= (others => '0');
+        sci_state     <= GET_WA;
+      end if;      
+    when SCTRL =>
+      if sci_reg_i = '1' then
+        SCI_DATA_OUT  <= debug_reg(8*(conv_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(conv_integer(unsigned(SCI_ADDR(3 downto 0)))));
+        SCI_ACK       <= '1';
+        sci_write_i   <= '0';
+        sci_read_i    <= '0';
+        sci_state     <= IDLE;
+      else
+        sci_state     <= SCTRL_WAIT;
+      end if;
+    when SCTRL_WAIT   =>
+      sci_state       <= SCTRL_WAIT2;
+    when SCTRL_WAIT2  =>
+      sci_state       <= SCTRL_FINISH;
+    when SCTRL_FINISH =>
+      SCI_DATA_OUT    <= sci_data_out_i;
+      SCI_ACK         <= '1';
+      sci_write_i     <= '0';
+      sci_read_i      <= '0';
+      sci_state       <= IDLE;
+    
+    when GET_WA =>
+      if cnt = 4 then
+        cnt           := 0;
+        sci_state     <= IDLE;
+      else
+        sci_state     <= GET_WA_WAIT;
+        sci_addr_i    <= '0' & x"22";
+        sci_ch_i      <= x"0";
+        sci_ch_i(cnt) <= '1';
+        sci_read_i    <= '1';
+      end if;
+    when GET_WA_WAIT  =>
+      sci_state       <= GET_WA_WAIT2;
+    when GET_WA_WAIT2 =>
+      sci_state       <= GET_WA_FINISH;
+    when GET_WA_FINISH =>
+      wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
+      sci_state       <= GET_WA;    
+      cnt             := cnt + 1;
+  end case;
+  
+  if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
+    SCI_NACK <= '1';
+  else
+    SCI_NACK <= '0';
+  end if;
+  
+end process;
+
+-------------------------------------------------      
+-- Generate LED signals
+------------------------------------------------- 
+
+
+-- GENERATE_LED_SIGNALS: for i in 0 to 3 generate  
+-- led_ok(i) <= rx_allow_i(i) and tx_allow_i(i); --  when rising_edge(SYSCLK); 
+-- led_rx(i) <= ((not rx_char_k(i)) or led_rx(i)) and not timer(20); --  when rising_edge(SYSCLK);
+-- led_tx(i) <= ((not tx_char_k(i)) or led_tx(i) or sd_los_i(i))  and not timer(20) when rising_edge(SYSCLK);
+-- -- led_dlm <= (led_dlm or rx_dlm_i) and not timer(20) when rising_edge(SYSCLK);
+-- LEDs_link_ok(i) <= not led_ok(i);
+-- LEDs_rx(i) <= not led_rx(i);
+-- LEDs_tx(i) <= not led_tx(i);
+-- end generate;
+
+-- rx_allow_q <= rx_allow_i when rising_edge(SYSCLK);
+-- tx_allow_q <= tx_allow_i when rising_edge(SYSCLK);
+
+-- ROC_TIMER : process begin
+  -- wait until rising_edge(SYSCLK);
+  -- timer <= timer + 1 ;
+  -- if timer(20) = '1' then
+    -- timer <= (others => '0');
+    -- last_led_rx <= led_rx ;
+    -- last_led_tx <= led_tx;
+  -- end if;
+-- end process;
+
+
+process(SYSCLK)
+begin
+	if rising_edge(SYSCLK) then
+		for i in 0 to 3 loop
+			led_ok(i) <= rx_allow_i(i) and tx_allow_i(i);
+			led_rx(i) <= ((not rx_char_k(i)) or led_rx(i)) and not timer(20); 
+			led_tx(i) <= ((not tx_char_k(i)) or led_tx(i) or sd_los_i(i))  and not timer(20);
+			-- led_dlm <= (led_dlm or rx_dlm_i) and not timer(20);
+			LEDs_link_ok(i) <= not led_ok(i);
+			LEDs_rx(i) <= not led_rx(i);
+			LEDs_tx(i) <= not led_tx(i);
+		end loop;
+
+		rx_allow_q <= rx_allow_i;
+		tx_allow_q <= tx_allow_i;
+	
+		timer <= timer + 1 ;
+		if timer(20) = '1' then
+			timer <= (others => '0');
+			last_led_rx <= led_rx ;
+			last_led_tx <= led_tx;
+		end if;
+	end if;
+end process;
+
+-------------------------------------------------      
+-- Debug Registers
+-------------------------------------------------            
+debug_reg(2 downto 0)   <= rx_fsm_state(0)(2 downto 0);
+debug_reg(3)            <= rx_serdes_rst(0);
+debug_reg(4)            <= CLEAR;
+debug_reg(5)            <= tx_allow_q(0);
+debug_reg(6)            <= rx_los_low(0);
+debug_reg(7)            <= rx_cdr_lol(0);
+
+debug_reg(8)            <= RESET;
+debug_reg(9)            <= tx_pll_lol;
+debug_reg(10)           <= rx_allow_q(0);
+debug_reg(11)           <= CTRL_OP(15);
+debug_reg(12)           <= '0';
+debug_reg(13)           <= '0';
+debug_reg(14)           <= sd_los_i(0);
+debug_reg(15)           <= rx_pcs_rst(0);
+-- debug_reg(31 downto 24) <= tx_data;
+
+debug_reg(16)           <= '0';
+debug_reg(17)           <= tx_allow_i(0);
+debug_reg(18)           <= RESET;
+debug_reg(19)           <= CLEAR;
+debug_reg(31 downto 20) <= (others => '0');
+
+debug_reg(35 downto 32) <= wa_position(3 downto 0);
+debug_reg(36)           <= '0';
+debug_reg(39 downto 37) <= "000";
+debug_reg(63 downto 40) <= (others => '0');
+
+STAT_OP(15) <= '0';
+STAT_OP(14) <= '0';
+STAT_OP(13) <= '0';
+STAT_OP(12) <= '0'; -- led_dlm or last_led_dlm;
+STAT_OP(11) <= led_tx(0) or last_led_tx(0);
+STAT_OP(10) <= led_rx(0) or last_led_rx(0);
+STAT_OP(9)  <= led_ok(0);
+STAT_OP(8 downto 4) <= (others => '0');
+STAT_OP(3 downto 0) <= x"0" when rx_allow_q(0) = '1' and tx_allow_q(0) = '1' else x"7";
+--STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else ("01" & tx_pll_lol & rx_cdr_lol);
+end architecture;
+
diff --git a/data_concentrator/sources/lattice/phase_measurement.vhd b/data_concentrator/sources/lattice/phase_measurement.vhd
new file mode 100644
index 0000000..3bce582
--- /dev/null
+++ b/data_concentrator/sources/lattice/phase_measurement.vhd
@@ -0,0 +1,225 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   22-08-2014
+-- Module Name:   phase_measurement
+-- Description:   Measure phase
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+USE ieee.std_logic_1164.all ;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+----------------------------------------------------------------------------------
+-- phase_measurement
+-- Module to measure phase difference between 2 clocks, using PLL that shift phase
+--
+-- Library
+-- 
+-- Generics:
+-- 
+-- Inputs:
+--     clock : clock
+--     clear : starts clearing the histogram. Clearing takes 2^HISTOGRAM_SIZEBITS clockcycles
+--     datain : values for the histogram
+--     writerequest : write for the datain values
+--     address : address (index in histogram) that has to be read
+--     readrequest : request the histogram value at address
+-- 
+-- Outputs:
+--     dataout : resulting histogram data, some time after the readrequest
+--     dataout_valid : valid signal for dataout
+-- 
+-- Components:
+--     pll_in125_outshift : Lattice phase shifter
+--
+----------------------------------------------------------------------------------
+entity phase_measurement is
+	port (
+		clock1                  : in std_logic;
+		clock_out               : out std_logic;
+		clock2                  : in std_logic;
+		reset                   : in std_logic;
+		phasearray              : out std_logic_vector(15 downto 0);
+		errorarray              : out std_logic_vector(15 downto 0)
+		);
+end phase_measurement;
+
+architecture behavioral of phase_measurement is
+
+component pll_in125_outshift is
+    port (
+        CLK: in std_logic; 
+        FINEDELB0: in std_logic; 
+        FINEDELB1: in std_logic; 
+        FINEDELB2: in std_logic; 
+        FINEDELB3: in std_logic; 
+        DPHASE0: in std_logic; 
+        DPHASE1: in std_logic; 
+        DPHASE2: in std_logic; 
+        DPHASE3: in std_logic; 
+        CLKOP: out std_logic; 
+        CLKOS: out std_logic; 
+        LOCK: out std_logic);
+end component;
+
+component pll_in62M5_outshift is
+    port (
+        CLK: in std_logic; 
+        FINEDELB0: in std_logic; 
+        FINEDELB1: in std_logic; 
+        FINEDELB2: in std_logic; 
+        FINEDELB3: in std_logic; 
+        DPHASE0: in std_logic; 
+        DPHASE1: in std_logic; 
+        DPHASE2: in std_logic; 
+        DPHASE3: in std_logic; 
+        CLKOP: out std_logic; 
+        CLKOS: out std_logic; 
+        LOCK: out std_logic);
+end component;
+
+constant NROFMEASURES      : integer := 2**8;
+constant STABLETIME        : integer := 2**8;
+
+signal clock_S             : std_logic;
+signal clock_shifted_S     : std_logic;
+signal plllocked_S         : std_logic;
+signal finedelay_S         : std_logic_vector(3 downto 0);
+signal setphase_S          : std_logic_vector(3 downto 0);
+type phase_type is (STARTING,WAITSTABLE,MEASURE,ADDRESULT,FINALRESULT);
+signal mode_S              : phase_type := STARTING;
+
+signal clock2div2r_S       : std_logic := '0';
+signal clock2div2f_S       : std_logic := '0';
+signal clock2_S            : std_logic;
+
+signal phasearray_S        : std_logic_vector(15 downto 0);
+signal errorarray_S        : std_logic_vector(15 downto 0);
+signal results_S           : std_logic_vector(15 downto 0);
+signal errors_S            : std_logic_vector(15 downto 0);
+signal clock2measured0_S   : std_logic := '0';
+signal clock2measured_S    : std_logic := '0';
+
+signal nrofones_S          : integer range 0 to NROFMEASURES-1;
+signal countmeasures_S     : integer range 0 to NROFMEASURES-1;
+signal countstable_S       : integer range 0 to STABLETIME-1;
+
+
+begin
+
+phasearray <= phasearray_S;
+errorarray <= errorarray_S;
+
+process(clock2)
+begin
+	if (rising_edge(clock2)) then
+		clock2div2r_S <= not clock2div2r_S;
+	end if;
+end process;
+process(clock2)
+begin
+	if (falling_edge(clock2)) then
+		clock2div2f_S <= not clock2div2f_S;
+	end if;
+end process;
+clock2_S <= clock2div2r_S xor clock2div2f_S;
+	
+clock_out <= clock_S;
+finedelay_S <= "0000";
+
+--pll_in125_outshift1: pll_in125_outshift port map(
+pll_in62M5_outshift1: pll_in62M5_outshift port map(
+        CLK => clock1,
+        FINEDELB0 => finedelay_S(0),
+        FINEDELB1 => finedelay_S(1),
+        FINEDELB2 => finedelay_S(2),
+        FINEDELB3 => finedelay_S(3),
+        DPHASE0 => setphase_S(0),
+        DPHASE1 => setphase_S(1),
+        DPHASE2 => setphase_S(2), 
+        DPHASE3 => setphase_S(3), 
+        CLKOP => clock_S,
+        CLKOS => clock_shifted_S,
+        LOCK => plllocked_S);
+
+		
+process(clock_shifted_S)
+begin
+	if (rising_edge(clock_shifted_S)) then 
+		clock2measured0_S <= clock2; -- clock2_S;
+	end if;
+end process;
+
+process(clock1)
+begin
+	if (rising_edge(clock1)) then 
+		clock2measured_S <= clock2measured0_S;
+	end if;
+end process;
+
+
+process(clock1,plllocked_S)
+begin
+	if plllocked_S='0' then
+		mode_S <= STARTING;
+	elsif (rising_edge(clock1)) then 
+		case mode_S is
+			when STARTING =>
+				nrofones_S <= 0;
+				countmeasures_S <= 0;
+				countstable_S <= 0;
+				setphase_S <= "0000";
+				mode_S <= WAITSTABLE;
+			when WAITSTABLE =>
+				nrofones_S <= 0;
+				countmeasures_S <= 0;
+				if countstable_S<STABLETIME-1 then
+					countstable_S <= countstable_S+1;
+				else
+					countstable_S <= 0;
+					mode_S <= MEASURE;
+				end if;
+			when MEASURE =>
+				if clock2measured_S='1' then
+					nrofones_S <= nrofones_S+1;
+				end if;
+				if countmeasures_S<NROFMEASURES-1 then
+					countmeasures_S <= countmeasures_S+1;
+				else
+					countmeasures_S <= 0;
+					mode_S <= ADDRESULT;
+				end if;
+			when ADDRESULT =>
+				if nrofones_S<NROFMEASURES/2 then
+					results_S(conv_integer(setphase_S)) <= '0';
+				else
+					results_S(conv_integer(setphase_S)) <= '1';
+				end if;
+				if (nrofones_S>NROFMEASURES/4) and ((nrofones_S<(3*NROFMEASURES)/4))  then
+					errors_S(conv_integer(setphase_S)) <= '1';
+				else
+					errors_S(conv_integer(setphase_S)) <= '0';
+				end if;
+				if setphase_S="1111" then
+					setphase_S <= "0000";
+					mode_S <= FINALRESULT;
+				else
+					setphase_S <= setphase_S+1;
+					mode_S <= WAITSTABLE;
+				end if;
+			when FINALRESULT =>
+				phasearray_S <= results_S;
+				errorarray_S <= errors_S;			
+				setphase_S <= "0000";
+				mode_S <= STARTING;
+			when others =>
+				mode_S <= STARTING;
+		end case;
+	end if;
+end process;
+
+
+end architecture behavioral;
diff --git a/data_concentrator/sources/lattice/rx_reset_sm.vhd b/data_concentrator/sources/lattice/rx_reset_sm.vhd
new file mode 100644
index 0000000..7010919
--- /dev/null
+++ b/data_concentrator/sources/lattice/rx_reset_sm.vhd
@@ -0,0 +1,196 @@
+--Reset Sequence Generator
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity rx_reset_sm is
+port (
+	rst_n			: in std_logic;
+	refclkdiv2        : in std_logic;
+	tx_pll_lol_qd_s	: in std_logic;
+	rx_serdes_rst_ch_c: out std_logic;
+	rx_cdr_lol_ch_s	: in std_logic;
+	rx_los_low_ch_s	: in std_logic;
+	rx_pcs_rst_ch_c	: out std_logic;
+    STATE_OUT         : out std_logic_vector(3 downto 0)
+);
+end rx_reset_sm ;
+
+architecture rx_reset_sm_arch of rx_reset_sm is
+
+type statetype is (WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_LOS, WAIT_FOR_TIMER2, NORMAL);
+
+signal	cs:		statetype; 	-- current state of lsm
+signal	ns:		statetype;	-- next state of lsm
+
+signal	tx_pll_lol_qd_s_int:	std_logic;
+signal	rx_los_low_int:			std_logic;
+signal	plol_los_int:			std_logic;
+signal	rx_lol_los	:	std_logic;
+signal	rx_lol_los_int:		std_logic;
+signal	rx_lol_los_del:		std_logic;
+signal	rx_pcs_rst_ch_c_int:	std_logic;      
+signal	rx_serdes_rst_ch_c_int:	std_logic;
+
+signal	reset_timer1:	std_logic;
+signal	reset_timer2:	std_logic;
+
+signal	counter1:	std_logic_vector(1 downto 0);
+signal	TIMER1:	std_logic;
+
+signal	counter2: std_logic_vector(18 downto 0);
+signal	TIMER2	: std_logic;
+
+begin
+
+rx_lol_los <= rx_cdr_lol_ch_s or rx_los_low_ch_s ;
+
+process(refclkdiv2,rst_n) 
+begin
+	if rising_edge(refclkdiv2) then
+		if rst_n = '0' then 
+			cs <= WAIT_FOR_PLOL;
+			rx_lol_los_int <= '1';
+			rx_lol_los_del <= '1';
+			tx_pll_lol_qd_s_int <= '1';
+			rx_pcs_rst_ch_c <= '1';
+			rx_serdes_rst_ch_c <= '0';
+			rx_los_low_int <= '1';
+		else 
+			cs <= ns;
+			rx_lol_los_del <= rx_lol_los;
+			rx_lol_los_int <= rx_lol_los_del;
+			tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
+			rx_pcs_rst_ch_c <= rx_pcs_rst_ch_c_int;
+			rx_serdes_rst_ch_c <= rx_serdes_rst_ch_c_int;
+			rx_los_low_int <= rx_los_low_ch_s;
+		end if;
+	end if;
+end process;
+
+--TIMER1 = 3NS;
+--Fastest REFCLK = 312 MHz, or 3ns. We need 1 REFCLK cycles or 2 REFCLKDIV2 cycles
+--A 1 bit counter  counts 2 cycles, so a 2 bit ([1:0]) counter will do if we set TIMER1 = bit[1]
+
+process(refclkdiv2, reset_timer1) 
+begin 
+	if rising_edge(refclkdiv2) then
+		if reset_timer1 = '1' then 
+			counter1 <= "00";
+			TIMER1 <= '0';
+		else 
+			if counter1(1) = '1' then
+				TIMER1 <='1';
+			else
+				TIMER1 <='0';
+				counter1 <= counter1 + 1 ;
+			end if;
+		end if;
+	end if;
+end process;
+
+--TIMER2 = 400,000 Refclk cycles or 200,000 REFCLKDIV2 cycles
+--An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
+
+process(refclkdiv2, reset_timer2) 
+begin
+	if rising_edge(refclkdiv2) then
+		if reset_timer2 = '1' then 
+			counter2 <= "0000000000000000000";
+			TIMER2 <= '0';
+		else 
+			if counter2(18) = '1' then
+--			if counter2(4) = '1' then -- for simulation
+				TIMER2 <='1';
+			else
+				TIMER2 <='0';
+				counter2 <= counter2 + 1 ;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+process(cs, tx_pll_lol_qd_s_int, rx_los_low_int, TIMER1, rx_lol_los_int, TIMER2)
+begin
+		reset_timer1 <= '0';        
+		reset_timer2 <= '0';        
+
+	case cs is
+		when WAIT_FOR_PLOL => 
+			rx_pcs_rst_ch_c_int <= '1';        
+			rx_serdes_rst_ch_c_int <= '0';
+			if (tx_pll_lol_qd_s_int = '1' or rx_los_low_int = '1') then  --Also make sure A Signal       
+				ns <= WAIT_FOR_PLOL;    			--is Present prior to moving to the next 
+			else	
+				ns <= RX_SERDES_RESET;
+      		end if;
+          		
+	    when RX_SERDES_RESET => 
+			rx_pcs_rst_ch_c_int <= '1';        
+			rx_serdes_rst_ch_c_int <= '1';        
+			reset_timer1 <= '1';        
+      		ns <= WAIT_FOR_TIMER1;
+
+		when WAIT_FOR_TIMER1 => 
+			rx_pcs_rst_ch_c_int <= '1';        
+			rx_serdes_rst_ch_c_int <= '1';
+			if TIMER1 = '1' then 
+				ns <= CHECK_LOL_LOS;
+			else	
+				ns <= WAIT_FOR_TIMER1;
+      		end if;
+      
+		when CHECK_LOL_LOS =>
+			rx_pcs_rst_ch_c_int <= '1';        
+			rx_serdes_rst_ch_c_int <= '0';        
+			reset_timer2 <= '1';        
+      		ns <= WAIT_FOR_TIMER2;
+        		
+		when WAIT_FOR_TIMER2 =>
+			rx_pcs_rst_ch_c_int <= '1';        
+			rx_serdes_rst_ch_c_int <= '0';
+			if rx_lol_los_int = rx_lol_los_del then 	--NO RISING OR FALLING EDGES
+				if TIMER2 = '1' then
+					if rx_lol_los_int = '1' then 
+						ns <= WAIT_FOR_PLOL;
+					else
+						ns <= NORMAL;
+					end if;
+				else
+					ns <= WAIT_FOR_TIMER2;
+				end if;
+			else
+	   			ns <= CHECK_LOL_LOS; 	--RESET TIMER2					
+			end if;
+
+		when NORMAL =>  
+			rx_pcs_rst_ch_c_int <= '0';        
+			rx_serdes_rst_ch_c_int <= '0';
+			if rx_lol_los_int = '1' then
+				ns <= WAIT_FOR_PLOL;
+			else	
+				ns <= NORMAL;
+			end if;
+
+		when others =>
+			ns <= WAIT_FOR_PLOL;
+
+		end case;
+
+end process;
+
+
+
+STATE_OUT <= 
+	x"1" when cs=WAIT_FOR_PLOL else
+	x"2" when cs=RX_SERDES_RESET else
+	x"3" when cs=WAIT_FOR_timer1 else
+	x"4" when cs=CHECK_LOL_LOS else
+	x"5" when cs=WAIT_FOR_timer2 else
+	x"6" when cs=NORMAL else
+	x"f";
+			
+end rx_reset_sm_arch;
diff --git a/data_concentrator/sources/lattice/sync_fifo_512x41.vhd b/data_concentrator/sources/lattice/sync_fifo_512x41.vhd
new file mode 100644
index 0000000..9c97029
--- /dev/null
+++ b/data_concentrator/sources/lattice/sync_fifo_512x41.vhd
@@ -0,0 +1,46 @@
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+entity sync_fifo_512x41 is
+port (
+		rst                     : in std_logic;
+		clk                     : in std_logic;
+		din                     : in std_logic_vector(40 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(40 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic
+	);
+end sync_fifo_512x41;
+	
+architecture Behavioral of sync_fifo_512x41 is
+
+component sync_fifo_512x41_ecp3 is
+    port (
+        Data: in  std_logic_vector(40 downto 0); 
+        Clock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        Q: out  std_logic_vector(40 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic);
+end component;
+
+begin
+
+sync_fifo_512x41_ecp3_1: sync_fifo_512x41_ecp3 port map(
+        Data => din,
+        Clock => clk,
+        WrEn => wr_en,
+        RdEn => rd_en,
+        Reset => rst,
+        Q => dout,
+        Empty => empty,
+        Full => full);
+
+end Behavioral;
+
diff --git a/data_concentrator/sources/lattice/trb_net16_med_1_2sync_3_ecp3_sfp.vhd b/data_concentrator/sources/lattice/trb_net16_med_1_2sync_3_ecp3_sfp.vhd
new file mode 100644
index 0000000..c906573
--- /dev/null
+++ b/data_concentrator/sources/lattice/trb_net16_med_1_2sync_3_ecp3_sfp.vhd
@@ -0,0 +1,1216 @@
+--Media interface for Lattice ECP3 using PCS at 2GHz
+--Three channels are used:
+--  ch1 : for TRBnet at 200MHz (2 Gbit/s fiber speed)
+--  ch2 : SODA, synchronized on incoming fiber-bits, 200MHz (2 Gbit/s fiber speed)
+--  ch3 : fiber to UDP converter, only output, 100MHz with 200MHz reference clock  (1 Gbit/s fiber speed)
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.med_sync_define.all;
+
+entity trb_net16_med_1_2sync_3_ecp3_sfp is
+  port(
+    CLK                : in  std_logic; -- SerDes clock
+    SYSCLK             : in  std_logic; -- fabric clock
+    RESET              : in  std_logic; -- synchronous reset
+    CLEAR              : in  std_logic; -- asynchronous reset
+    CLK_EN             : in  std_logic;
+    --Internal Connection
+    MED_DATA_IN        : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_IN  : in  std_logic_vector(c_NUM_WIDTH-1 downto 0);
+    MED_DATAREADY_IN   : in  std_logic;
+    MED_READ_OUT       : out std_logic;
+    MED_DATA_OUT       : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+    MED_DATAREADY_OUT  : out std_logic;
+    MED_READ_IN        : in  std_logic;
+    REFCLK2CORE_OUT    : out std_logic;
+    CLK_RX_HALF_OUT    : out std_logic;
+    CLK_RX_FULL_OUT    : out std_logic;
+    --SFP Connection
+    SD_RXD_P_IN        : in  std_logic;
+    SD_RXD_N_IN        : in  std_logic;
+    SD_TXD_P_OUT       : out std_logic;
+    SD_TXD_N_OUT       : out std_logic;
+    SD_REFCLK_P_IN     : in  std_logic;
+    SD_REFCLK_N_IN     : in  std_logic;
+    SD_PRSNT_N_IN      : in  std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+    SD_LOS_IN          : in  std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+    SD_TXDIS_OUT       : out  std_logic; -- SFP disable
+    --Control Interface
+    SCI_DATA_IN        : in  std_logic_vector(7 downto 0) := (others => '0');
+    SCI_DATA_OUT       : out std_logic_vector(7 downto 0) := (others => '0');
+    SCI_ADDR           : in  std_logic_vector(8 downto 0) := (others => '0');
+    SCI_READ           : in  std_logic := '0';
+    SCI_WRITE          : in  std_logic := '0';
+    SCI_ACK            : out std_logic := '0';
+    SCI_NACK           : out std_logic := '0';
+	-- SODA serdes channel
+    SODA_RXD_P_IN      : in  std_logic;
+    SODA_RXD_N_IN      : in  std_logic;
+    SODA_TXD_P_OUT     : out std_logic;
+    SODA_TXD_N_OUT     : out std_logic;
+	SODA_DLM_IN        : in  std_logic;
+	SODA_DLM_WORD_IN   : in  std_logic_vector(7 downto 0);
+	SODA_DLM_OUT       : out  std_logic;
+	SODA_DLM_WORD_OUT  : out  std_logic_vector(7 downto 0);
+    SODA_CLOCK_OUT     : out  std_logic; -- 200MHz
+	
+    -- Connection to addon interface        
+    DOUT_TXD_P_OUT     : out  std_logic;
+    DOUT_TXD_N_OUT     : out  std_logic;
+    SFP_MOD0_5         : in  std_logic;
+    SFP_MOD0_3         : in  std_logic;          
+    SFP_LOS_5          : in  std_logic;          
+    SFP_LOS_3          : in  std_logic;
+	TX_READY_CH3       : out std_logic;
+    TX_DATA_CH3        : in std_logic_vector(7 downto 0);
+    TX_K_CH3           : in std_logic;
+    -- Status and control port
+    STAT_OP            : out std_logic_vector (15 downto 0);
+    CTRL_OP            : in  std_logic_vector (15 downto 0);
+    STAT_DEBUG         : out std_logic_vector (63 downto 0);
+    CTRL_DEBUG         : in  std_logic_vector (63 downto 0)
+   );
+end entity;
+
+architecture trb_net16_med_1_2sync_3_ecp3_sfp_arch of trb_net16_med_1_2sync_3_ecp3_sfp is
+
+
+  -- Placer Directives
+  attribute HGROUP : string;
+  -- for whole architecture
+  attribute HGROUP of trb_net16_med_1_2sync_3_ecp3_sfp_arch : architecture  is "media_interface_group";
+  attribute syn_sharing : string;
+  attribute syn_sharing of trb_net16_med_1_2sync_3_ecp3_sfp_arch : architecture is "off";
+
+  --OJK 29-nov-2013
+	component sfp_1_3_200_int
+	port(
+		hdinp_ch1          : IN std_logic;
+		hdinn_ch1          : IN std_logic;
+		sci_sel_ch1        : IN std_logic;
+		rxiclk_ch1         : IN std_logic;
+		txiclk_ch1         : IN std_logic;
+		fpga_rxrefclk_ch1  : IN std_logic;
+		txdata_ch1         : IN std_logic_vector(15 downto 0);
+		tx_k_ch1           : IN std_logic_vector(1 downto 0);
+		tx_force_disp_ch1  : IN std_logic_vector(1 downto 0);
+		tx_disp_sel_ch1    : IN std_logic_vector(1 downto 0);
+		sb_felb_ch1_c      : IN std_logic;
+		sb_felb_rst_ch1_c  : IN std_logic;
+		tx_pwrup_ch1_c     : IN std_logic;
+		rx_pwrup_ch1_c     : IN std_logic;
+		tx_div2_mode_ch1_c : IN std_logic;
+		rx_div2_mode_ch1_c : IN std_logic;
+		sci_sel_ch3        : IN std_logic;
+		txiclk_ch3         : IN std_logic;
+		fpga_rxrefclk_ch3  : IN std_logic;
+		txdata_ch3         : IN std_logic_vector(7 downto 0);
+		tx_k_ch3           : IN std_logic;
+		tx_force_disp_ch3  : IN std_logic;
+		tx_disp_sel_ch3    : IN std_logic;
+		tx_pwrup_ch3_c     : IN std_logic;
+		tx_div2_mode_ch3_c : IN std_logic;
+		sci_wrdata         : IN std_logic_vector(7 downto 0);
+		sci_addr           : IN std_logic_vector(5 downto 0);
+		sci_sel_quad       : IN std_logic;
+		sci_rd             : IN std_logic;
+		sci_wrn            : IN std_logic;
+		fpga_txrefclk      : IN std_logic;
+		tx_serdes_rst_c    : IN std_logic;
+		tx_sync_qd_c       : IN std_logic;
+		rst_n              : IN std_logic;
+		serdes_rst_qd_c    : IN std_logic;          
+		hdoutp_ch1         : OUT std_logic;
+		hdoutn_ch1         : OUT std_logic;
+		rx_full_clk_ch1    : OUT std_logic;
+		rx_half_clk_ch1    : OUT std_logic;
+		tx_full_clk_ch1    : OUT std_logic;
+		tx_half_clk_ch1    : OUT std_logic;
+		rxdata_ch1         : OUT std_logic_vector(15 downto 0);
+		rx_k_ch1           : OUT std_logic_vector(1 downto 0);
+		rx_disp_err_ch1    : OUT std_logic_vector(1 downto 0);
+		rx_cv_err_ch1      : OUT std_logic_vector(1 downto 0);
+		rx_los_low_ch1_s   : OUT std_logic;
+		lsm_status_ch1_s   : OUT std_logic;
+		rx_cdr_lol_ch1_s   : OUT std_logic;
+		hdoutp_ch3         : OUT std_logic;
+		hdoutn_ch3         : OUT std_logic;
+		tx_full_clk_ch3    : OUT std_logic;
+		tx_half_clk_ch3    : OUT std_logic;
+		sci_rddata         : OUT std_logic_vector(7 downto 0);
+		tx_pll_lol_qd_s    : OUT std_logic;
+		refclk2fpga        : OUT std_logic
+			);
+	end component;
+  
+-- Peter Schakel 02-12-14
+component sfp_1_2sync_3_200_int is
+ port (
+------------------
+-- CH0 --
+-- CH1 --
+    hdinp_ch1, hdinn_ch1    :   in std_logic;
+    hdoutp_ch1, hdoutn_ch1   :   out std_logic;
+    sci_sel_ch1    :   in std_logic;
+    rxiclk_ch1    :   in std_logic;
+    txiclk_ch1    :   in std_logic;
+    rx_full_clk_ch1   :   out std_logic;
+    rx_half_clk_ch1   :   out std_logic;
+    tx_full_clk_ch1   :   out std_logic;
+    tx_half_clk_ch1   :   out std_logic;
+    fpga_rxrefclk_ch1    :   in std_logic;
+    txdata_ch1    :   in std_logic_vector (15 downto 0);
+    tx_k_ch1    :   in std_logic_vector (1 downto 0);
+    tx_force_disp_ch1    :   in std_logic_vector (1 downto 0);
+    tx_disp_sel_ch1    :   in std_logic_vector (1 downto 0);
+    rxdata_ch1   :   out std_logic_vector (15 downto 0);
+    rx_k_ch1   :   out std_logic_vector (1 downto 0);
+    rx_disp_err_ch1   :   out std_logic_vector (1 downto 0);
+    rx_cv_err_ch1   :   out std_logic_vector (1 downto 0);
+    rx_serdes_rst_ch1_c    :   in std_logic;
+    sb_felb_ch1_c    :   in std_logic;
+    sb_felb_rst_ch1_c    :   in std_logic;
+    tx_pcs_rst_ch1_c    :   in std_logic;
+    tx_pwrup_ch1_c    :   in std_logic;
+    rx_pcs_rst_ch1_c    :   in std_logic;
+    rx_pwrup_ch1_c    :   in std_logic;
+    rx_los_low_ch1_s   :   out std_logic;
+    lsm_status_ch1_s   :   out std_logic;
+    rx_cdr_lol_ch1_s   :   out std_logic;
+    tx_div2_mode_ch1_c   : in std_logic;
+    rx_div2_mode_ch1_c   : in std_logic;
+-- CH2 --
+    hdinp_ch2, hdinn_ch2    :   in std_logic;
+    hdoutp_ch2, hdoutn_ch2   :   out std_logic;
+    sci_sel_ch2    :   in std_logic;
+    rxiclk_ch2    :   in std_logic;
+    txiclk_ch2    :   in std_logic;
+    rx_full_clk_ch2   :   out std_logic;
+    rx_half_clk_ch2   :   out std_logic;
+    tx_full_clk_ch2   :   out std_logic;
+    tx_half_clk_ch2   :   out std_logic;
+    fpga_rxrefclk_ch2    :   in std_logic;
+    txdata_ch2    :   in std_logic_vector (7 downto 0);
+    tx_k_ch2    :   in std_logic;
+    tx_force_disp_ch2    :   in std_logic;
+    tx_disp_sel_ch2    :   in std_logic;
+    rxdata_ch2   :   out std_logic_vector (7 downto 0);
+    rx_k_ch2   :   out std_logic;
+    rx_disp_err_ch2   :   out std_logic;
+    rx_cv_err_ch2   :   out std_logic;
+    rx_serdes_rst_ch2_c    :   in std_logic;
+    sb_felb_ch2_c    :   in std_logic;
+    sb_felb_rst_ch2_c    :   in std_logic;
+    tx_pcs_rst_ch2_c    :   in std_logic;
+    tx_pwrup_ch2_c    :   in std_logic;
+    rx_pcs_rst_ch2_c    :   in std_logic;
+    rx_pwrup_ch2_c    :   in std_logic;
+    rx_los_low_ch2_s   :   out std_logic;
+    lsm_status_ch2_s   :   out std_logic;
+    rx_cdr_lol_ch2_s   :   out std_logic;
+    tx_div2_mode_ch2_c   : in std_logic;
+    rx_div2_mode_ch2_c   : in std_logic;
+-- CH3 --
+    hdoutp_ch3, hdoutn_ch3   :   out std_logic;
+    sci_sel_ch3    :   in std_logic;
+    txiclk_ch3    :   in std_logic;
+    tx_full_clk_ch3   :   out std_logic;
+    tx_half_clk_ch3   :   out std_logic;
+    txdata_ch3    :   in std_logic_vector (7 downto 0);
+    tx_k_ch3    :   in std_logic;
+    tx_force_disp_ch3    :   in std_logic;
+    tx_disp_sel_ch3    :   in std_logic;
+    tx_pcs_rst_ch3_c    :   in std_logic;
+    tx_pwrup_ch3_c    :   in std_logic;
+    tx_div2_mode_ch3_c   : in std_logic;
+---- Miscillaneous ports
+    sci_wrdata    :   in std_logic_vector (7 downto 0);
+    sci_addr    :   in std_logic_vector (5 downto 0);
+    sci_rddata   :   out std_logic_vector (7 downto 0);
+    sci_sel_quad    :   in std_logic;
+    sci_rd    :   in std_logic;
+    sci_wrn    :   in std_logic;
+    fpga_txrefclk  :   in std_logic;
+    tx_serdes_rst_c    :   in std_logic;
+    tx_pll_lol_qd_s   :   out std_logic;
+    tx_sync_qd_c    :   in std_logic;
+    rst_qd_c    :   in std_logic;
+    serdes_rst_qd_c    :   in std_logic);
+
+end component;
+
+component rx_reset_sm is
+port (
+	rst_n			: in std_logic;
+	refclkdiv2        : in std_logic;
+	tx_pll_lol_qd_s	: in std_logic;
+	rx_serdes_rst_ch_c: out std_logic;
+	rx_cdr_lol_ch_s	: in std_logic;
+	rx_los_low_ch_s	: in std_logic;
+	rx_pcs_rst_ch_c	: out std_logic;
+    STATE_OUT         : out std_logic_vector(3 downto 0));
+end component ;
+component tx_reset_sm is
+port (
+	rst_n 			: in std_logic;
+	refclkdiv2      : in std_logic;
+	tx_pll_lol_qd_s : in std_logic;
+	rst_qd_c		: out std_logic;
+	tx_pcs_rst_ch_c : out std_logic_vector(3 downto 0);
+	STATE_OUT       : out std_logic_vector(3 downto 0)
+	);
+end component;
+  
+  signal refck2core             : std_logic;
+--  signal clock                  : std_logic;
+  --reset signals
+  signal ffc_quad_rst           : std_logic;
+  signal ffc_lane_tx_rst        : std_logic;
+  signal ffc_lane_rx_rst        : std_logic;
+  --serdes connections
+  signal tx_data                : std_logic_vector(15 downto 0);
+  signal tx_k                   : std_logic_vector(1 downto 0);
+  signal rx_data                : std_logic_vector(15 downto 0); -- delayed signals
+  signal rx_k                   : std_logic_vector(1 downto 0);  -- delayed signals
+  signal comb_rx_data           : std_logic_vector(15 downto 0); -- original signals from SFP
+  signal comb_rx_k              : std_logic_vector(1 downto 0);  -- original signals from SFP
+  signal link_ok                : std_logic_vector(1 downto 0); -- OJK 02-dec-2013: Changed width from 1 bit to 2 bits
+  signal link_error             : std_logic_vector(10 downto 0);-- OJK 02-dec-2013: Changed width from 10 bits to 11 bits
+  signal ff_txhalfclk           : std_logic;
+  signal ff_rxhalfclk			      : std_logic;
+  signal ff_rxfullclk           : std_logic;
+  --rx fifo signals
+  signal fifo_rx_rd_en          : std_logic;
+  signal fifo_rx_wr_en          : std_logic;
+  signal fifo_rx_reset          : std_logic;
+  signal fifo_rx_din            : std_logic_vector(17 downto 0);
+  signal fifo_rx_dout           : std_logic_vector(17 downto 0);
+  signal fifo_rx_full           : std_logic;
+  signal fifo_rx_empty          : std_logic;
+  --tx fifo signals
+  signal fifo_tx_rd_en          : std_logic;
+  signal fifo_tx_wr_en          : std_logic;
+  signal fifo_tx_reset          : std_logic;
+  signal fifo_tx_din            : std_logic_vector(17 downto 0);
+  signal fifo_tx_dout           : std_logic_vector(17 downto 0);
+  signal fifo_tx_full           : std_logic;
+  signal fifo_tx_empty          : std_logic;
+  signal fifo_tx_almost_full    : std_logic;
+  --rx path
+  signal rx_counter             : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+  signal buf_med_dataready_out  : std_logic;
+  signal buf_med_data_out       : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+  signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+  signal last_rx                : std_logic_vector(8 downto 0);
+  signal last_fifo_rx_empty     : std_logic;
+  --tx path
+  signal last_fifo_tx_empty     : std_logic;
+  --link status
+  signal rx_k_q                 : std_logic_vector(1 downto 0);
+
+  signal quad_rst               : std_logic;
+  signal lane_rst               : std_logic;
+  signal tx_allow               : std_logic;
+  signal tx_allow0              : std_logic;
+  signal rx_allow               : std_logic;
+  signal tx_allow_qtx           : std_logic;
+
+  signal rx_allow_q             : std_logic; -- clock domain changed signal
+  signal tx_allow_q             : std_logic;
+  signal swap_bytes             : std_logic;
+  signal buf_stat_debug         : std_logic_vector(31 downto 0);
+
+  -- status inputs from SFP
+  signal sfp_prsnt_n            : std_logic; -- synchronized input signals
+  signal sfp_los                : std_logic; -- synchronized input signals
+
+  signal buf_STAT_OP            : std_logic_vector(15 downto 0);
+
+  signal led_counter            : unsigned(16 downto 0);
+  signal rx_led                 : std_logic;
+  signal tx_led                 : std_logic;
+
+
+  signal tx_correct             : std_logic_vector(1 downto 0); -- GbE mode SERDES: automatic IDLE2 -> IDLE1 conversion
+  signal first_idle             : std_logic; -- tag the first IDLE2 after data
+
+  signal reset_word_cnt    : unsigned(4 downto 0);
+  signal make_trbnet_reset : std_logic;
+  signal make_trbnet_reset_q : std_logic;
+  signal send_reset_words  : std_logic;
+  signal send_reset_words_q : std_logic;
+  signal send_reset_in      : std_logic;
+  signal send_reset_in_qtx  : std_logic;
+  signal reset_i                : std_logic;
+  signal reset_i_rx             : std_logic;
+  signal pwr_up                 : std_logic;
+  signal clear_n   : std_logic;
+
+  signal clk_sys : std_logic;
+  signal clk_tx  : std_logic;
+  signal clk_rx  : std_logic;
+  signal clk_rxref : std_logic;
+  signal clk_txref : std_logic;
+
+type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
+signal sci_state         : sci_ctrl;
+  signal sci_ch_i        : std_logic_vector(3 downto 0);
+  signal sci_qd_i        : std_logic;
+  signal sci_reg_i       : std_logic;
+  signal sci_addr_i      : std_logic_vector(8 downto 0);
+  signal sci_data_in_i   : std_logic_vector(7 downto 0);
+  signal sci_data_out_i  : std_logic_vector(7 downto 0);
+  signal sci_read_i      : std_logic;
+  signal sci_write_i     : std_logic;
+--  signal sci_write_shift_i : std_logic_vector(2 downto 0);
+--  signal sci_read_shift_i  : std_logic_vector(2 downto 0);  
+  
+  --OJK 13-dec-2013
+  signal cnt             : integer range 0 to 10000;
+  signal tx_pll_lol_qd_i : std_logic;
+  -- Peter Schakel 3-dec-2014
+ 	
+  signal sci_timer            : unsigned(12 downto 0) := (others => '0');
+  signal trb_reset_n          : std_logic;
+  signal sync_reset_n         : std_logic;
+  signal CH3_reset_n          : std_logic;
+  signal trb_rx_serdes_rst    : std_logic;
+  signal trb_rx_cdr_lol       : std_logic;
+  signal trb_rx_los_low       : std_logic;
+  signal trb_rx_pcs_rst       : std_logic;
+  signal trb_tx_pcs_rst       : std_logic;
+  signal trb_tx_pcs_rst_all   : std_logic_vector(3 downto 0);
+  signal rst_qd               : std_logic;
+  signal link_RXOK_S          : std_logic;
+  signal link_TXOK_S          : std_logic;
+  signal trb_rx_fsm_state     : std_logic_vector(3 downto 0);
+  signal trb_tx_fsm_state     : std_logic_vector(3 downto 0);
+  
+  signal sync_clk_rx_full     : std_logic;
+  signal sync_clk_rx_half     : std_logic;
+  signal sync_clk_tx_full     : std_logic;
+  signal sync_clk_tx_half     : std_logic;
+  signal sync_tx_k            : std_logic;
+  signal sync_tx_data         : std_logic_vector(7 downto 0);
+
+  signal syncfifo_din         : std_logic_vector(17 downto 0);
+  signal syncfifo_dout        : std_logic_vector(17 downto 0);
+	  
+  signal sync_rx_k            : std_logic;
+  signal sync_rx_data         : std_logic_vector(7 downto 0);
+  signal sync_rx_serdes_rst   : std_logic;
+  signal sync_rx_cdr_lol      : std_logic;
+  signal sync_tx_pcs_rst      : std_logic;
+  signal sync_rx_pcs_rst      : std_logic;
+  signal sync_rx_los_low      : std_logic;
+  signal sync_lsm_status      : std_logic;
+  signal SD_tx_pcs_rst        : std_logic;
+  signal DLM_fifo_rd_en       : std_logic;
+  signal DLM_fifo_empty       : std_logic;
+  signal DLM_fifo_reading     : std_logic := '0';  
+  signal SODA_dlm_word_S      : std_logic_vector(7 downto 0);
+  signal DLM_received_S       : std_logic;
+  signal sync_wa_position_rx  : std_logic_vector(15 downto 0) := x"FFFF";
+  signal wa_position          : std_logic_vector(15 downto 0) := x"FFFF";
+  signal sync_rx_fsm_state    : std_logic_vector(3 downto 0);
+  signal sync_tx_fsm_state    : std_logic_vector(3 downto 0);
+  signal CH3_tx_fsm_state     : std_logic_vector(3 downto 0);
+
+  signal CLKdiv100_S          : std_logic;
+  signal sync_clk_rx_fulldiv100_S     : std_logic;
+			
+  attribute syn_keep : boolean;
+  attribute syn_preserve : boolean;
+  attribute syn_keep of led_counter : signal is true;
+  attribute syn_keep of send_reset_in : signal is true;
+  attribute syn_keep of reset_i : signal is true;
+  attribute syn_preserve of reset_i : signal is true;
+
+begin
+
+--------------------------------------------------------------------------
+-- Select proper clock configuration
+--------------------------------------------------------------------------
+  clk_sys <= SYSCLK;
+  clk_tx  <= SYSCLK;
+  clk_rx  <= ff_rxhalfclk;
+  clk_rxref <= CLK;
+  clk_txref <= CLK;
+
+
+
+
+--------------------------------------------------------------------------
+-- Internal Lane Resets
+--------------------------------------------------------------------------
+  clear_n <= not clear;
+
+
+  PROC_RESET : process(clk_sys)
+    begin
+      if rising_edge(clk_sys) then
+        reset_i <= RESET;
+        send_reset_in <= ctrl_op(15);
+        pwr_up  <= '1'; --not CTRL_OP(i*16+14);
+      end if;
+    end process;
+
+--------------------------------------------------------------------------
+-- Synchronizer stages
+--------------------------------------------------------------------------
+
+-- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)
+THE_SFP_STATUS_SYNC: signal_sync
+  generic map(
+    DEPTH => 3,
+    WIDTH => 2
+    )
+  port map(
+    RESET    => '0',
+    D_IN(0)  => sd_prsnt_n_in,
+    D_IN(1)  => sd_los_in,
+    CLK0     => clk_sys,
+    CLK1     => clk_sys,
+    D_OUT(0) => sfp_prsnt_n,
+    D_OUT(1) => sfp_los
+    );
+
+
+THE_RX_K_SYNC: signal_sync
+  generic map(
+    DEPTH => 1,
+    WIDTH => 4
+    )
+  port map(
+    RESET             => reset_i,
+    D_IN(1 downto 0)  => comb_rx_k,
+    D_IN(2)           => send_reset_words,
+    D_IN(3)           => make_trbnet_reset,
+    CLK0              => clk_rx, -- CHANGED
+    CLK1              => clk_sys,
+    D_OUT(1 downto 0) => rx_k_q,
+    D_OUT(2)          => send_reset_words_q,
+    D_OUT(3)          => make_trbnet_reset_q
+    );
+
+THE_RX_DATA_DELAY: signal_sync
+  generic map(
+    DEPTH => 2,
+    WIDTH => 16
+    )
+  port map(
+    RESET    => reset_i,
+    D_IN     => comb_rx_data,
+    CLK0     => clk_rx,
+    CLK1     => clk_rx,
+    D_OUT    => rx_data
+    );
+
+THE_RX_K_DELAY: signal_sync
+  generic map(
+    DEPTH => 2,
+    WIDTH => 2
+    )
+  port map(
+    RESET    => reset_i,
+    D_IN     => comb_rx_k,
+    CLK0     => clk_rx,
+    CLK1     => clk_rx,
+    D_OUT    => rx_k
+    );
+
+THE_RX_RESET: signal_sync
+  generic map(
+    DEPTH => 1,
+    WIDTH => 1
+    )
+  port map(
+    RESET    => '0',
+    D_IN(0)  => reset_i,
+    CLK0     => clk_rx,
+    CLK1     => clk_rx,
+    D_OUT(0) => reset_i_rx
+    );
+
+-- Delay for ALLOW signals
+THE_RX_ALLOW_SYNC: signal_sync
+  generic map(
+    DEPTH => 2,
+    WIDTH => 2
+    )
+  port map(
+    RESET    => reset_i,
+    D_IN(0)  => rx_allow,
+    D_IN(1)  => tx_allow,
+    CLK0     => clk_sys,
+    CLK1     => clk_sys,
+    D_OUT(0) => rx_allow_q,
+    D_OUT(1) => tx_allow_q
+    );
+
+THE_TX_SYNC: signal_sync
+  generic map(
+    DEPTH => 1,
+    WIDTH => 2
+    )
+  port map(
+    RESET    => '0',
+    D_IN(0)  => send_reset_in,
+    D_IN(1)  => tx_allow,
+    CLK0     => clk_tx,
+    CLK1     => clk_tx,
+    D_OUT(0) => send_reset_in_qtx,
+    D_OUT(1) => tx_allow_qtx
+    );
+
+
+--------------------------------------------------------------------------
+-- Main control state machine, startup control for SFP
+--------------------------------------------------------------------------
+
+THE_SFP_LSM: trb_net16_lsm_sfp
+    generic map (
+      HIGHSPEED_STARTUP => c_YES
+      )
+    port map(
+      SYSCLK            => clk_sys,
+      RESET             => reset_i,
+      CLEAR             => clear,
+      SFP_MISSING_IN    => sfp_prsnt_n,
+      SFP_LOS_IN        => sfp_los,
+      SD_LINK_OK_IN     => link_ok(0), -- apparently not used
+      SD_LOS_IN         => link_error(8), -- apparently not used
+      SD_TXCLK_BAD_IN   => link_error(5),
+      SD_RXCLK_BAD_IN   => link_error(4),
+      SD_RETRY_IN       => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
+      SD_ALIGNMENT_IN	=> rx_k_q,
+      SD_CV_IN          => link_error(7 downto 6),
+      FULL_RESET_OUT    => quad_rst,
+      LANE_RESET_OUT    => lane_rst, -- apparently not used
+      TX_ALLOW_OUT      => tx_allow,
+      RX_ALLOW_OUT      => rx_allow,
+      SWAP_BYTES_OUT    => swap_bytes,
+      STAT_OP           => buf_stat_op,
+      CTRL_OP           => ctrl_op,
+      STAT_DEBUG        => buf_stat_debug
+      );
+--//sd_txdis_out <= quad_rst or reset_i;
+sd_txdis_out <= '1' when (quad_rst='1') or (reset_i='1') or (link_RXOK_S='0') or (link_TXOK_S='0') else '0';
+--------------------------------------------------------------------------
+--------------------------------------------------------------------------
+
+--//?? ffc_quad_rst         <= quad_rst;
+ffc_lane_tx_rst      <= lane_rst;
+
+
+ffc_lane_rx_rst      <= lane_rst;
+
+-- SerDes clock output to FPGA fabric
+REFCLK2CORE_OUT <= ff_rxhalfclk;
+CLK_RX_HALF_OUT <= ff_rxhalfclk;
+CLK_RX_FULL_OUT <= ff_rxfullclk;
+
+THE_SERDES: sfp_1_2sync_3_200_int port map(
+------------------
+-- CH0 --
+		-- not used
+-- CH1 --
+		hdinp_ch1          => sd_rxd_p_in,                
+		hdinn_ch1          => sd_rxd_n_in,                
+		hdoutp_ch1         => sd_txd_p_out,              
+		hdoutn_ch1         => sd_txd_n_out,              
+
+		sci_sel_ch1        => sci_ch_i(1),
+		rxiclk_ch1         => clk_rx,                
+		txiclk_ch1         => clk_tx,                
+		rx_full_clk_ch1    => ff_rxfullclk,          
+		rx_half_clk_ch1    => ff_rxhalfclk,          
+		tx_full_clk_ch1    => open,                  
+		tx_half_clk_ch1    => ff_txhalfclk,          
+		fpga_rxrefclk_ch1  => clk_rxref,             
+		txdata_ch1         => tx_data,               
+		tx_k_ch1           => tx_k,                  
+		tx_force_disp_ch1  => tx_correct,            
+		tx_disp_sel_ch1    => "00",                  
+		rxdata_ch1         => comb_rx_data,          
+		rx_k_ch1           => comb_rx_k,             
+		rx_disp_err_ch1    => open,            
+		rx_cv_err_ch1      => link_error(7 downto 6),
+		rx_serdes_rst_ch1_c => trb_rx_serdes_rst,
+		sb_felb_ch1_c      => '0',                   
+		sb_felb_rst_ch1_c  => '0',                
+		tx_pcs_rst_ch1_c   => trb_tx_pcs_rst,
+		tx_pwrup_ch1_c     => '1',                   
+		rx_pcs_rst_ch1_c   => trb_rx_pcs_rst,
+		rx_pwrup_ch1_c     => '1',                   
+		rx_los_low_ch1_s   => trb_rx_los_low, -- link_error(8),         
+		lsm_status_ch1_s   => link_ok(0),            
+		rx_cdr_lol_ch1_s   => trb_rx_cdr_lol, -- link_error(4),         
+		tx_div2_mode_ch1_c => '0',                   
+		rx_div2_mode_ch1_c => '0',
+
+-- CH2 --
+		hdinp_ch2            => SODA_RXD_P_IN,
+		hdinn_ch2            => SODA_RXD_N_IN,
+		hdoutp_ch2           => SODA_TXD_P_OUT,
+		hdoutn_ch2           => SODA_TXD_N_OUT,
+		sci_sel_ch2          => sci_ch_i(2),
+		rxiclk_ch2           => sync_clk_rx_full, -- ?? CLK,
+		txiclk_ch2           => sync_clk_tx_full, -- ??CLK, --????? clk_txref
+		rx_full_clk_ch2      => sync_clk_rx_full,
+		rx_half_clk_ch2      => sync_clk_rx_half,
+		tx_full_clk_ch2      => sync_clk_tx_full,
+		tx_half_clk_ch2      => sync_clk_tx_half,
+		fpga_rxrefclk_ch2    => CLK,
+		txdata_ch2           => sync_tx_data,
+		tx_k_ch2             => sync_tx_k,
+		tx_force_disp_ch2    => '0',
+		tx_disp_sel_ch2      => '0',
+		rxdata_ch2           => sync_rx_data,
+		rx_k_ch2             => sync_rx_k,
+		rx_disp_err_ch2      => open,
+		rx_cv_err_ch2        => open,
+		rx_serdes_rst_ch2_c  => sync_rx_serdes_rst,
+		sb_felb_ch2_c        => '0',
+		sb_felb_rst_ch2_c    => '0',
+		tx_pcs_rst_ch2_c     => sync_tx_pcs_rst,
+		tx_pwrup_ch2_c       => '1',
+		rx_pcs_rst_ch2_c     => sync_rx_pcs_rst,
+		rx_pwrup_ch2_c       => '1',
+		rx_los_low_ch2_s     => sync_rx_los_low,
+		lsm_status_ch2_s     => sync_lsm_status,
+		rx_cdr_lol_ch2_s     => sync_rx_cdr_lol,
+		tx_div2_mode_ch2_c   => '0',
+		rx_div2_mode_ch2_c   => '0',
+		
+-- CH3 --
+		hdoutp_ch3         => DOUT_TXD_P_OUT,             
+		hdoutn_ch3         => DOUT_TXD_N_OUT,             
+		sci_sel_ch3        => '0', --disable access to channel 3 registers
+		txiclk_ch3         => clk_tx,             
+		tx_full_clk_ch3    => open,                
+		tx_half_clk_ch3    => open,        
+		txdata_ch3         => tx_data_ch3,             
+		tx_k_ch3           => tx_k_ch3,
+		tx_force_disp_ch3  => '0',      
+		tx_disp_sel_ch3    => '0',        
+		tx_pcs_rst_ch3_c   => SD_tx_pcs_rst,
+		tx_pwrup_ch3_c     => '1',         
+		tx_div2_mode_ch3_c => '1', 
+
+		---- Miscillaneous ports
+		sci_wrdata         => sci_data_in_i,
+		sci_addr           => sci_addr_i(5 downto 0),
+		sci_rddata         => sci_data_out_i,
+		sci_sel_quad       => sci_qd_i,
+		sci_rd             => sci_read_i,
+		sci_wrn            => sci_write_i,
+		fpga_txrefclk      => clk_txref,               
+		tx_serdes_rst_c    => CLEAR,          
+		tx_pll_lol_qd_s    => tx_pll_lol_qd_i,          
+		tx_sync_qd_c       => '0',             -- Multiple channel transmit synchronization is not needed
+		rst_qd_c => rst_qd,
+		serdes_rst_qd_c    => ffc_quad_rst        
+	);
+
+--------------------------------------------------------------------------
+-- FIFO and additional logic to synchronize SODA (DLM signals) to the transceiver clock
+--------------------------------------------------------------------------
+syncfifo_din(7 downto 0)  <= SODA_DLM_WORD_IN;
+syncfifo_din(17 downto 8) <= (others => '0');
+SODA_dlm_word_S <= syncfifo_dout(7 downto 0);
+
+sync_DLM_tx: trb_net_fifo_16bit_bram_dualport
+	generic map(
+		USE_STATUS_FLAGS => c_NO
+       )
+	port map( 
+		read_clock_in  => sync_clk_tx_full,
+		write_clock_in     => sync_clk_rx_full, 
+		read_enable_in     => DLM_fifo_rd_en,
+		write_enable_in    => SODA_DLM_IN,
+		fifo_gsr_in        => reset,
+		write_data_in      => syncfifo_din,
+		read_data_out      => syncfifo_dout,
+		full_out           => open,
+		empty_out          => DLM_fifo_empty
+	);
+
+-- write DLM data in fifo
+process(sync_clk_rx_full)
+begin
+  if rising_edge(sync_clk_rx_full) then
+	SODA_DLM_OUT <= '0';
+	if DLM_received_S='1' then
+		DLM_received_S <= '0';
+		SODA_DLM_OUT <= '1';
+		SODA_DLM_WORD_OUT <= sync_rx_data;
+	elsif (sync_rx_data=x"DC") and (sync_rx_k='1') then
+		DLM_received_S <= '1';
+	end if;
+  end if;
+end process;  
+
+-- read DLM data from fifo and pass on as k-character 28.6 (0xDC) followed by DLM databyte
+-- no other data, only idles (k-character 2.85)
+-- First DLM in burst is delayed to prevent missing DLMs due to asynchronous clock
+process(sync_clk_tx_full)
+begin
+  if rising_edge(sync_clk_tx_full) then
+	if DLM_fifo_rd_en='1' then
+		DLM_fifo_rd_en <= '0';
+		sync_tx_data <= SODA_dlm_word_S;
+		sync_tx_k <= '0';
+	elsif (DLM_fifo_empty='0') and (DLM_fifo_reading='1') then
+		DLM_fifo_rd_en <= '1';
+		sync_tx_data <= x"DC";
+		sync_tx_k <= '1';
+	elsif DLM_fifo_empty='0' then
+		DLM_fifo_reading <= '1';
+		DLM_fifo_rd_en <= '0';
+		sync_tx_data <= x"BC"; -- idle
+		sync_tx_k <= '1';		
+	else
+		DLM_fifo_reading <= '0';
+		DLM_fifo_rd_en <= '0';
+		sync_tx_data <= x"BC"; -- idle
+		sync_tx_k <= '1';
+	end if;
+  end if;
+end process;  
+SODA_CLOCK_OUT <= sync_clk_rx_full;
+
+
+-------------------------------------------------      
+-- Error and status signal from serdes
+------------------------------------------------- 
+link_error(8) <= trb_rx_los_low; -- loss of signal
+link_error(4) <= '1' when (trb_rx_cdr_lol='1') or (link_RXOK_S='0') else '0'; -- loss of lock 
+link_error(5) <= '1' when (tx_pll_lol_qd_i='1') or (link_TXOK_S='0') else '0';
+
+--//reset_n <= '0' when (RESET='1') or (CLEAR='1') or (sfp_los='1') or (ffc_quad_rst='1') else '1';
+trb_reset_n <= '0' when (RESET='1') or (CLEAR='1') or (sfp_los='1') or (ffc_quad_rst='1')  or (quad_rst='1') else '1';
+ffc_quad_rst <= '1' when (RESET='1') or (CLEAR='1') or (quad_rst='1') else '0'; --// quad_rst???????
+-------------------------------------------------      
+-- Reset FSM & Link states
+------------------------------------------------- 
+THE_RX_FSM1:  rx_reset_sm   -- original from Lattice
+  port map(
+    RST_N               => trb_reset_n,
+	refclkdiv2          => SYSCLK,
+    TX_PLL_LOL_QD_S     => tx_pll_lol_qd_i,
+    RX_SERDES_RST_CH_C  => trb_rx_serdes_rst,
+    RX_CDR_LOL_CH_S     => trb_rx_cdr_lol,
+    RX_LOS_LOW_CH_S     => trb_rx_los_low,
+    RX_PCS_RST_CH_C     => trb_rx_pcs_rst,
+    STATE_OUT           => trb_rx_fsm_state
+	);
+
+
+-- THE_RX_FSM1: rx_reset_fsm -- reset FSM for receiver channel 1 (TRBnet)
+  -- port map(
+    -- RST_N               => trb_reset_n,
+    -- RX_REFCLK           => CLK,
+    -- TX_PLL_LOL_QD_S     => tx_pll_lol_qd_i,
+    -- RX_SERDES_RST_CH_C  => trb_rx_serdes_rst,
+    -- RX_CDR_LOL_CH_S     => trb_rx_cdr_lol,
+    -- RX_LOS_LOW_CH_S     => trb_rx_los_low,
+    -- RX_PCS_RST_CH_C     => trb_rx_pcs_rst,
+    -- WA_POSITION         => "0000",
+    -- STATE_OUT           => trb_rx_fsm_state
+    -- );
+link_RXOK_S <= '1' when (trb_rx_fsm_state = x"6") else '0';
+
+THE_TX_FSM1: tx_reset_sm   -- original from Lattice
+  port map(
+    RST_N           => trb_reset_n,
+	refclkdiv2      => SYSCLK,
+    TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
+    RST_QD_C        => rst_qd,
+    TX_PCS_RST_CH_C => trb_tx_pcs_rst_all,
+    STATE_OUT       => trb_tx_fsm_state);
+trb_tx_pcs_rst <= trb_tx_pcs_rst_all(1);
+
+-- THE_TX_FSM1: tx_reset_fsm -- reset FSM for transmit channel 1 (TRBnet)
+  -- port map(
+    -- RST_N           => trb_reset_n,
+    -- TX_REFCLK       => CLK,
+    -- TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
+    -- RST_QD_C        => rst_qd,
+    -- TX_PCS_RST_CH_C => trb_tx_pcs_rst,
+    -- STATE_OUT       => trb_tx_fsm_state
+    -- );
+link_TXOK_S <= '1' when (trb_tx_fsm_state = x"5") else '0';
+
+sync_reset_n <= '0' when (RESET='1') or (CLEAR='1') else '1';
+THE_RX_FSM2: rx_reset_fsm -- reset FSM for receiver channel 2 (SODA), synchronize to fiber bit with wa_position
+  port map(
+    RST_N               => sync_reset_n,
+    RX_REFCLK           => sync_clk_rx_full, --??CLK,
+    TX_PLL_LOL_QD_S     => tx_pll_lol_qd_i,
+    RX_SERDES_RST_CH_C  => sync_rx_serdes_rst,
+    RX_CDR_LOL_CH_S     => sync_rx_cdr_lol,
+    RX_LOS_LOW_CH_S     => sync_rx_los_low,
+    RX_PCS_RST_CH_C     => sync_rx_pcs_rst,
+    WA_POSITION         => sync_wa_position_rx(11 downto 8),
+    STATE_OUT           => sync_rx_fsm_state
+    );
+SYNC_WA_POSITION : process(sync_clk_rx_full) --??CLK)
+begin
+  if rising_edge(sync_clk_rx_full) then
+    sync_wa_position_rx <= wa_position;
+  end if;
+end process;
+    
+THE_TX_FSM2: tx_reset_fsm -- reset FSM for transmit channel 2 (SODA)
+  port map(
+    RST_N           => sync_reset_n,
+    TX_REFCLK       => CLK,
+    TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
+    RST_QD_C        => open, --??
+    TX_PCS_RST_CH_C => sync_tx_pcs_rst,
+    STATE_OUT       => sync_tx_fsm_state
+    );
+	
+CH3_reset_n <= '0' when (RESET='1') or (CLEAR='1') else '1';
+THE_TX_FSM3 : tx_reset_fsm -- reset FSM for transmit channel 3 (data to UDP core)
+  port map(
+    RST_N           => CH3_reset_n,
+    TX_REFCLK       => CLK,
+    TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
+    RST_QD_C        => open, --??
+    TX_PCS_RST_CH_C => SD_tx_pcs_rst,
+    STATE_OUT       => CH3_tx_fsm_state
+    );
+TX_READY_CH3 <= '1' when (CH3_tx_fsm_state=x"5") and (tx_pll_lol_qd_i='0') else '0';
+	
+	
+-------------------------------------------------------------------------
+-- RX Fifo & Data output
+-------------------------------------------------------------------------
+THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport
+generic map(
+  USE_STATUS_FLAGS => c_NO
+       )
+port map( read_clock_in  => clk_sys,
+      write_clock_in     => clk_rx, -- CHANGED
+      read_enable_in     => fifo_rx_rd_en,
+      write_enable_in    => fifo_rx_wr_en,
+      fifo_gsr_in        => fifo_rx_reset,
+      write_data_in      => fifo_rx_din,
+      read_data_out      => fifo_rx_dout,
+      full_out           => fifo_rx_full,
+      empty_out          => fifo_rx_empty
+    );
+
+fifo_rx_reset <= reset_i or not rx_allow_q;
+fifo_rx_rd_en <= not fifo_rx_empty;
+
+-- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path
+THE_BYTE_SWAP_PROC: process(clk_rx)
+  begin
+    if rising_edge(clk_rx) then
+		last_rx <= rx_k(1) & rx_data(15 downto 8);
+		if( swap_bytes = '0' ) then
+		  fifo_rx_din   <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0);
+		  fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok(0);
+		else
+		  fifo_rx_din   <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0);
+		  fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok(0);
+		end if;
+	end if;
+  end process THE_BYTE_SWAP_PROC;
+
+buf_med_data_out          <= fifo_rx_dout(15 downto 0);
+buf_med_dataready_out     <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q;
+buf_med_packet_num_out    <= rx_counter;
+med_read_out              <= tx_allow_q and not fifo_tx_almost_full;
+
+
+THE_CNT_RESET_PROC : process(clk_rx)
+  begin
+    if rising_edge(clk_rx) then
+		if reset_i_rx = '1' then
+		  send_reset_words  <= '0';
+		  make_trbnet_reset <= '0';
+		  reset_word_cnt    <= (others => '0');
+		else
+		  send_reset_words   <= '0';
+		  make_trbnet_reset  <= '0';
+		  if fifo_rx_din = "11" & x"FEFE" then
+			if reset_word_cnt(4) = '0' then
+			  reset_word_cnt <= reset_word_cnt + to_unsigned(1,1);
+			else
+			  send_reset_words <= '1';
+			end if;
+		  else
+			reset_word_cnt    <= (others => '0');
+			make_trbnet_reset <= reset_word_cnt(4);
+		  end if;
+		end if;
+	end if;
+  end process;
+
+
+THE_SYNC_PROC: process(clk_rx)
+  begin
+    if rising_edge(clk_rx) then
+		med_dataready_out     <= buf_med_dataready_out;
+		med_data_out          <= buf_med_data_out;
+		med_packet_num_out    <= buf_med_packet_num_out;
+		if reset_i = '1' then
+		  med_dataready_out <= '0';
+		end if;
+	end if;
+  end process;
+
+
+--rx packet counter
+---------------------
+THE_RX_PACKETS_PROC: process( clk_sys )
+  begin
+    if( rising_edge(clk_sys) ) then
+      last_fifo_rx_empty <= fifo_rx_empty;
+      if reset_i = '1' or rx_allow_q = '0' then
+        rx_counter <= c_H0;
+      else
+        if( buf_med_dataready_out = '1' ) then
+          if( rx_counter = c_max_word_number ) then
+            rx_counter <= (others => '0');
+          else
+            rx_counter <= std_logic_vector(unsigned(rx_counter) + to_unsigned(1,1));
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+--TX Fifo & Data output to Serdes
+---------------------
+THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport
+  generic map(
+    USE_STATUS_FLAGS => c_NO
+        )
+  port map( read_clock_in => clk_tx,
+        write_clock_in    => clk_sys,
+        read_enable_in    => fifo_tx_rd_en,
+        write_enable_in   => fifo_tx_wr_en,
+        fifo_gsr_in       => fifo_tx_reset,
+        write_data_in     => fifo_tx_din,
+        read_data_out     => fifo_tx_dout,
+        full_out          => fifo_tx_full,
+        empty_out         => fifo_tx_empty,
+        almost_full_out   => fifo_tx_almost_full
+      );
+
+fifo_tx_reset <= reset_i or not tx_allow_q;
+fifo_tx_din   <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in;
+fifo_tx_wr_en <= med_dataready_in and tx_allow_q;
+fifo_tx_rd_en <= tx_allow_qtx;
+
+
+THE_SERDES_INPUT_PROC: process( clk_tx )
+  begin
+    if( rising_edge(clk_tx) ) then
+      last_fifo_tx_empty <= fifo_tx_empty;
+      first_idle <= not last_fifo_tx_empty and fifo_tx_empty;
+      if send_reset_in = '1' then
+        tx_data <= x"FEFE";
+        tx_k <= "11";
+      elsif( (last_fifo_tx_empty = '1') or (tx_allow_qtx = '0') ) then
+        tx_data <= x"50bc";
+        tx_k <= "01";
+        tx_correct <= first_idle & '0';
+      else
+        tx_data <= fifo_tx_dout(15 downto 0);
+        tx_k <= "00";
+        tx_correct <= "00";
+      end if;
+    end if;
+  end process THE_SERDES_INPUT_PROC;
+
+-------------------------------------------------      
+-- SCI
+-------------------------------------------------      
+--gives access to serdes config port from slow control and reads word alignment every ~ 40 us
+PROC_SCI_CTRL: process(clk_sys)
+  variable cnt : integer range 0 to 4 := 0;
+begin
+  if( rising_edge(clk_sys) ) then
+	  SCI_ACK <= '0';
+	  case sci_state is
+		when IDLE =>
+		  sci_ch_i        <= x"0";
+		  sci_qd_i        <= '0';
+		  sci_reg_i       <= '0';
+		  sci_read_i      <= '0';
+		  sci_write_i     <= '0';
+		  sci_timer       <= sci_timer + 1;
+		  if SCI_READ = '1' or SCI_WRITE = '1' then
+			sci_ch_i(0)   <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+			sci_ch_i(1)   <=     SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+			sci_ch_i(2)   <= not SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
+			sci_ch_i(3)   <=     SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
+			sci_qd_i      <= not SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
+			sci_reg_i     <=     SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
+			sci_addr_i    <= SCI_ADDR;
+			sci_data_in_i <= SCI_DATA_IN;
+			sci_read_i    <= SCI_READ  and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
+			sci_write_i   <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
+			sci_state     <= SCTRL;
+		  elsif sci_timer(sci_timer'left) = '1' then
+			sci_timer     <= (others => '0');
+			sci_state     <= GET_WA;
+		  end if;      
+		when SCTRL =>
+		  if sci_reg_i = '1' then
+--//			SCI_DATA_OUT  <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
+			SCI_DATA_OUT  <= (others => '0');
+			SCI_ACK       <= '1';
+			sci_write_i   <= '0';
+			sci_read_i    <= '0';
+			sci_state     <= IDLE;
+		  else
+			sci_state     <= SCTRL_WAIT;
+		  end if;
+		when SCTRL_WAIT   =>
+		  sci_state       <= SCTRL_WAIT2;
+		when SCTRL_WAIT2  =>
+		  sci_state       <= SCTRL_FINISH;
+		when SCTRL_FINISH =>
+		  SCI_DATA_OUT    <= sci_data_out_i;
+		  SCI_ACK         <= '1';
+		  sci_write_i     <= '0';
+		  sci_read_i      <= '0';
+		  sci_state       <= IDLE;
+		
+		when GET_WA =>
+		  if cnt = 4 then
+			cnt           := 0;
+			sci_state     <= IDLE;
+		  else
+			sci_state     <= GET_WA_WAIT;
+			sci_addr_i    <= '0' & x"22";
+			sci_ch_i      <= x"0";
+			sci_ch_i(cnt) <= '1';
+			sci_read_i    <= '1';
+		  end if;
+		when GET_WA_WAIT  =>
+		  sci_state       <= GET_WA_WAIT2;
+		when GET_WA_WAIT2 =>
+		  sci_state       <= GET_WA_FINISH;
+		when GET_WA_FINISH =>
+		  wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
+		  sci_state       <= GET_WA;    
+		  cnt             := cnt + 1;
+	  end case;
+	  
+	  if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
+		SCI_NACK <= '1';
+	  else
+		SCI_NACK <= '0';
+	  end if;
+  end if;
+end process;
+    
+  
+
+--Generate LED signals
+----------------------
+process( clk_sys )
+  begin
+    if rising_edge(clk_sys) then
+      led_counter <= led_counter + to_unsigned(1,1);
+
+      if buf_med_dataready_out = '1' then
+        rx_led <= '1';
+      elsif led_counter = 0 then
+        rx_led <= '0';
+      end if;
+
+      if tx_k(0) = '0' then
+        tx_led <= '1';
+      elsif led_counter = 0 then
+        tx_led <= '0';
+      end if;
+
+    end if;
+  end process;
+
+stat_op(15)           <= send_reset_words_q;
+stat_op(14)           <= buf_stat_op(14);
+stat_op(13)           <= make_trbnet_reset_q;
+stat_op(12)           <= '0';
+stat_op(11)           <= tx_led; --tx led
+stat_op(10)           <= rx_led; --rx led
+stat_op(9 downto 0)   <= buf_stat_op(9 downto 0);
+
+-- Debug output
+stat_debug(15 downto 0)  <= rx_data;
+stat_debug(17 downto 16) <= rx_k;
+stat_debug(19 downto 18) <= (others => '0');
+stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0);
+stat_debug(24)           <= fifo_rx_rd_en;
+stat_debug(25)           <= fifo_rx_wr_en;
+stat_debug(26)           <= fifo_rx_reset;
+stat_debug(27)           <= fifo_rx_empty;
+stat_debug(28)           <= fifo_rx_full;
+stat_debug(29)           <= last_rx(8);
+stat_debug(30)           <= rx_allow_q;
+stat_debug(41 downto 31) <= (others => '0');
+stat_debug(42)           <= clk_sys;
+stat_debug(43)           <= clk_sys;
+stat_debug(59 downto 44) <= (others => '0');
+stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0);
+
+--stat_debug(3 downto 0)   <= buf_stat_debug(3 downto 0); -- state_bits
+--stat_debug(4)            <= buf_stat_debug(4); -- alignme
+--stat_debug(5)            <= sfp_prsnt_n;
+--stat_debug(6)            <= tx_k(0);
+--stat_debug(7)            <= tx_k(1);
+--stat_debug(8)            <= rx_k_q(0);
+--stat_debug(9)            <= rx_k_q(1);
+--stat_debug(18 downto 10) <= link_error;
+--stat_debug(19)           <= '0';
+--stat_debug(20)           <= link_ok(0);
+--stat_debug(38 downto 21) <= fifo_rx_din;
+--stat_debug(39)           <= swap_bytes;
+--stat_debug(40)           <= buf_stat_debug(7); -- sfp_missing_in
+--stat_debug(41)           <= buf_stat_debug(8); -- sfp_los_in
+--stat_debug(42)           <= buf_stat_debug(6); -- resync
+--stat_debug(59 downto 43) <= (others => '0');
+--stat_debug(63 downto 60) <= link_error(3 downto 0);
+
+CLKdiv100_process: process(CLK)
+variable counter_V : integer range 0 to 99 := 0;
+begin
+	if (rising_edge(CLK)) then 
+		if counter_V<49 then -- 99 for 125MHz
+			counter_V := counter_V+1;
+		else
+			counter_V := 0;
+			CLKdiv100_S <= not CLKdiv100_S;
+		end if;
+	end if;
+end process;
+sync_clk_rx_fulldiv100_process: process(sync_clk_rx_full)
+variable counter_V : integer range 0 to 99 := 0;
+begin
+	if (rising_edge(sync_clk_rx_full)) then 
+		if counter_V<49 then -- 99 for 125MHz
+			counter_V := counter_V+1;
+		else
+			counter_V := 0;
+			sync_clk_rx_fulldiv100_S <= not sync_clk_rx_fulldiv100_S;
+		end if;
+	end if;
+end process;
+
+end architecture;
\ No newline at end of file
diff --git a/data_concentrator/sources/lattice/trb_net16_med_1_2sync_3_ecp3_sfp_old.vhd b/data_concentrator/sources/lattice/trb_net16_med_1_2sync_3_ecp3_sfp_old.vhd
new file mode 100644
index 0000000..15f7d37
--- /dev/null
+++ b/data_concentrator/sources/lattice/trb_net16_med_1_2sync_3_ecp3_sfp_old.vhd
@@ -0,0 +1,1151 @@
+--Media interface for Lattice ECP3 using PCS at 2GHz
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.med_sync_define.all;
+
+entity trb_net16_med_1_2sync_3_ecp3_sfp is
+  port(
+    CLK                : in  std_logic; -- SerDes clock
+    SYSCLK             : in  std_logic; -- fabric clock
+    RESET              : in  std_logic; -- synchronous reset
+    CLEAR              : in  std_logic; -- asynchronous reset
+    CLK_EN             : in  std_logic;
+    --Internal Connection
+    MED_DATA_IN        : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_IN  : in  std_logic_vector(c_NUM_WIDTH-1 downto 0);
+    MED_DATAREADY_IN   : in  std_logic;
+    MED_READ_OUT       : out std_logic;
+    MED_DATA_OUT       : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+    MED_DATAREADY_OUT  : out std_logic;
+    MED_READ_IN        : in  std_logic;
+    REFCLK2CORE_OUT    : out std_logic;
+    CLK_RX_HALF_OUT    : out std_logic;
+    CLK_RX_FULL_OUT    : out std_logic;
+    --SFP Connection
+    SD_RXD_P_IN        : in  std_logic;
+    SD_RXD_N_IN        : in  std_logic;
+    SD_TXD_P_OUT       : out std_logic;
+    SD_TXD_N_OUT       : out std_logic;
+    SD_REFCLK_P_IN     : in  std_logic;
+    SD_REFCLK_N_IN     : in  std_logic;
+    SD_PRSNT_N_IN      : in  std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+    SD_LOS_IN          : in  std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+    SD_TXDIS_OUT       : out  std_logic; -- SFP disable
+    --Control Interface
+    SCI_DATA_IN        : in  std_logic_vector(7 downto 0) := (others => '0');
+    SCI_DATA_OUT       : out std_logic_vector(7 downto 0) := (others => '0');
+    SCI_ADDR           : in  std_logic_vector(8 downto 0) := (others => '0');
+    SCI_READ           : in  std_logic := '0';
+    SCI_WRITE          : in  std_logic := '0';
+    SCI_ACK            : out std_logic := '0';
+    SCI_NACK           : out std_logic := '0';
+	-- SODA serdes channel
+    SODA_RXD_P_IN      : in  std_logic;
+    SODA_RXD_N_IN      : in  std_logic;
+    SODA_TXD_P_OUT     : out std_logic;
+    SODA_TXD_N_OUT     : out std_logic;
+	SODA_DLM_IN        : in  std_logic;
+	SODA_DLM_WORD_IN   : in  std_logic_vector(7 downto 0);
+	SODA_DLM_OUT       : out  std_logic;
+	SODA_DLM_WORD_OUT  : out  std_logic_vector(7 downto 0);
+    SODA_CLOCK_OUT     : out  std_logic; -- 200MHz
+	
+    -- Connection to addon interface        
+    DOUT_TXD_P_OUT     : out  std_logic;
+    DOUT_TXD_N_OUT     : out  std_logic;
+    SFP_MOD0_5         : in  std_logic;
+    SFP_MOD0_3         : in  std_logic;          
+    SFP_LOS_5          : in  std_logic;          
+    SFP_LOS_3          : in  std_logic;
+	TX_READY_CH3       : out std_logic;
+    TX_DATA_CH3        : in std_logic_vector(7 downto 0);
+    TX_K_CH3           : in std_logic;
+    -- Status and control port
+    STAT_OP            : out std_logic_vector (15 downto 0);
+    CTRL_OP            : in  std_logic_vector (15 downto 0);
+    STAT_DEBUG         : out std_logic_vector (63 downto 0);
+    CTRL_DEBUG         : in  std_logic_vector (63 downto 0)
+   );
+end entity;
+
+architecture trb_net16_med_1_2sync_3_ecp3_sfp_arch of trb_net16_med_1_2sync_3_ecp3_sfp is
+
+
+  -- Placer Directives
+  attribute HGROUP : string;
+  -- for whole architecture
+  attribute HGROUP of trb_net16_med_1_2sync_3_ecp3_sfp_arch : architecture  is "media_interface_group";
+  attribute syn_sharing : string;
+  attribute syn_sharing of trb_net16_med_1_2sync_3_ecp3_sfp_arch : architecture is "off";
+
+  --OJK 29-nov-2013
+	component sfp_1_3_200_int
+	port(
+		hdinp_ch1          : IN std_logic;
+		hdinn_ch1          : IN std_logic;
+		sci_sel_ch1        : IN std_logic;
+		rxiclk_ch1         : IN std_logic;
+		txiclk_ch1         : IN std_logic;
+		fpga_rxrefclk_ch1  : IN std_logic;
+		txdata_ch1         : IN std_logic_vector(15 downto 0);
+		tx_k_ch1           : IN std_logic_vector(1 downto 0);
+		tx_force_disp_ch1  : IN std_logic_vector(1 downto 0);
+		tx_disp_sel_ch1    : IN std_logic_vector(1 downto 0);
+		sb_felb_ch1_c      : IN std_logic;
+		sb_felb_rst_ch1_c  : IN std_logic;
+		tx_pwrup_ch1_c     : IN std_logic;
+		rx_pwrup_ch1_c     : IN std_logic;
+		tx_div2_mode_ch1_c : IN std_logic;
+		rx_div2_mode_ch1_c : IN std_logic;
+		sci_sel_ch3        : IN std_logic;
+		txiclk_ch3         : IN std_logic;
+		fpga_rxrefclk_ch3  : IN std_logic;
+		txdata_ch3         : IN std_logic_vector(7 downto 0);
+		tx_k_ch3           : IN std_logic;
+		tx_force_disp_ch3  : IN std_logic;
+		tx_disp_sel_ch3    : IN std_logic;
+		tx_pwrup_ch3_c     : IN std_logic;
+		tx_div2_mode_ch3_c : IN std_logic;
+		sci_wrdata         : IN std_logic_vector(7 downto 0);
+		sci_addr           : IN std_logic_vector(5 downto 0);
+		sci_sel_quad       : IN std_logic;
+		sci_rd             : IN std_logic;
+		sci_wrn            : IN std_logic;
+		fpga_txrefclk      : IN std_logic;
+		tx_serdes_rst_c    : IN std_logic;
+		tx_sync_qd_c       : IN std_logic;
+		rst_n              : IN std_logic;
+		serdes_rst_qd_c    : IN std_logic;          
+		hdoutp_ch1         : OUT std_logic;
+		hdoutn_ch1         : OUT std_logic;
+		rx_full_clk_ch1    : OUT std_logic;
+		rx_half_clk_ch1    : OUT std_logic;
+		tx_full_clk_ch1    : OUT std_logic;
+		tx_half_clk_ch1    : OUT std_logic;
+		rxdata_ch1         : OUT std_logic_vector(15 downto 0);
+		rx_k_ch1           : OUT std_logic_vector(1 downto 0);
+		rx_disp_err_ch1    : OUT std_logic_vector(1 downto 0);
+		rx_cv_err_ch1      : OUT std_logic_vector(1 downto 0);
+		rx_los_low_ch1_s   : OUT std_logic;
+		lsm_status_ch1_s   : OUT std_logic;
+		rx_cdr_lol_ch1_s   : OUT std_logic;
+		hdoutp_ch3         : OUT std_logic;
+		hdoutn_ch3         : OUT std_logic;
+		tx_full_clk_ch3    : OUT std_logic;
+		tx_half_clk_ch3    : OUT std_logic;
+		sci_rddata         : OUT std_logic_vector(7 downto 0);
+		tx_pll_lol_qd_s    : OUT std_logic;
+		refclk2fpga        : OUT std_logic
+			);
+	end component;
+  
+-- Peter Schakel 02-12-14
+component sfp_1_2sync_3_200_int is
+ port (
+------------------
+-- CH0 --
+-- CH1 --
+    hdinp_ch1, hdinn_ch1    :   in std_logic;
+    hdoutp_ch1, hdoutn_ch1   :   out std_logic;
+    sci_sel_ch1    :   in std_logic;
+    rxiclk_ch1    :   in std_logic;
+    txiclk_ch1    :   in std_logic;
+    rx_full_clk_ch1   :   out std_logic;
+    rx_half_clk_ch1   :   out std_logic;
+    tx_full_clk_ch1   :   out std_logic;
+    tx_half_clk_ch1   :   out std_logic;
+    fpga_rxrefclk_ch1    :   in std_logic;
+    txdata_ch1    :   in std_logic_vector (15 downto 0);
+    tx_k_ch1    :   in std_logic_vector (1 downto 0);
+    tx_force_disp_ch1    :   in std_logic_vector (1 downto 0);
+    tx_disp_sel_ch1    :   in std_logic_vector (1 downto 0);
+    rxdata_ch1   :   out std_logic_vector (15 downto 0);
+    rx_k_ch1   :   out std_logic_vector (1 downto 0);
+    rx_disp_err_ch1   :   out std_logic_vector (1 downto 0);
+    rx_cv_err_ch1   :   out std_logic_vector (1 downto 0);
+    rx_serdes_rst_ch1_c    :   in std_logic;
+    sb_felb_ch1_c    :   in std_logic;
+    sb_felb_rst_ch1_c    :   in std_logic;
+    tx_pcs_rst_ch1_c    :   in std_logic;
+    tx_pwrup_ch1_c    :   in std_logic;
+    rx_pcs_rst_ch1_c    :   in std_logic;
+    rx_pwrup_ch1_c    :   in std_logic;
+    rx_los_low_ch1_s   :   out std_logic;
+    lsm_status_ch1_s   :   out std_logic;
+    rx_cdr_lol_ch1_s   :   out std_logic;
+    tx_div2_mode_ch1_c   : in std_logic;
+    rx_div2_mode_ch1_c   : in std_logic;
+-- CH2 --
+    hdinp_ch2, hdinn_ch2    :   in std_logic;
+    hdoutp_ch2, hdoutn_ch2   :   out std_logic;
+    sci_sel_ch2    :   in std_logic;
+    rxiclk_ch2    :   in std_logic;
+    txiclk_ch2    :   in std_logic;
+    rx_full_clk_ch2   :   out std_logic;
+    rx_half_clk_ch2   :   out std_logic;
+    tx_full_clk_ch2   :   out std_logic;
+    tx_half_clk_ch2   :   out std_logic;
+    fpga_rxrefclk_ch2    :   in std_logic;
+    txdata_ch2    :   in std_logic_vector (7 downto 0);
+    tx_k_ch2    :   in std_logic;
+    tx_force_disp_ch2    :   in std_logic;
+    tx_disp_sel_ch2    :   in std_logic;
+    rxdata_ch2   :   out std_logic_vector (7 downto 0);
+    rx_k_ch2   :   out std_logic;
+    rx_disp_err_ch2   :   out std_logic;
+    rx_cv_err_ch2   :   out std_logic;
+    rx_serdes_rst_ch2_c    :   in std_logic;
+    sb_felb_ch2_c    :   in std_logic;
+    sb_felb_rst_ch2_c    :   in std_logic;
+    tx_pcs_rst_ch2_c    :   in std_logic;
+    tx_pwrup_ch2_c    :   in std_logic;
+    rx_pcs_rst_ch2_c    :   in std_logic;
+    rx_pwrup_ch2_c    :   in std_logic;
+    rx_los_low_ch2_s   :   out std_logic;
+    lsm_status_ch2_s   :   out std_logic;
+    rx_cdr_lol_ch2_s   :   out std_logic;
+    tx_div2_mode_ch2_c   : in std_logic;
+    rx_div2_mode_ch2_c   : in std_logic;
+-- CH3 --
+    hdoutp_ch3, hdoutn_ch3   :   out std_logic;
+    sci_sel_ch3    :   in std_logic;
+    txiclk_ch3    :   in std_logic;
+    tx_full_clk_ch3   :   out std_logic;
+    tx_half_clk_ch3   :   out std_logic;
+    txdata_ch3    :   in std_logic_vector (7 downto 0);
+    tx_k_ch3    :   in std_logic;
+    tx_force_disp_ch3    :   in std_logic;
+    tx_disp_sel_ch3    :   in std_logic;
+    tx_pcs_rst_ch3_c    :   in std_logic;
+    tx_pwrup_ch3_c    :   in std_logic;
+    tx_div2_mode_ch3_c   : in std_logic;
+---- Miscillaneous ports
+    sci_wrdata    :   in std_logic_vector (7 downto 0);
+    sci_addr    :   in std_logic_vector (5 downto 0);
+    sci_rddata   :   out std_logic_vector (7 downto 0);
+    sci_sel_quad    :   in std_logic;
+    sci_rd    :   in std_logic;
+    sci_wrn    :   in std_logic;
+    fpga_txrefclk  :   in std_logic;
+    tx_serdes_rst_c    :   in std_logic;
+    tx_pll_lol_qd_s   :   out std_logic;
+    tx_sync_qd_c    :   in std_logic;
+    rst_qd_c    :   in std_logic;
+    serdes_rst_qd_c    :   in std_logic);
+
+end component;
+
+ 
+  
+  signal refck2core             : std_logic;
+--  signal clock                  : std_logic;
+  --reset signals
+  signal ffc_quad_rst           : std_logic;
+  signal ffc_lane_tx_rst        : std_logic;
+  signal ffc_lane_rx_rst        : std_logic;
+  --serdes connections
+  signal tx_data                : std_logic_vector(15 downto 0);
+  signal tx_k                   : std_logic_vector(1 downto 0);
+  signal rx_data                : std_logic_vector(15 downto 0); -- delayed signals
+  signal rx_k                   : std_logic_vector(1 downto 0);  -- delayed signals
+  signal comb_rx_data           : std_logic_vector(15 downto 0); -- original signals from SFP
+  signal comb_rx_k              : std_logic_vector(1 downto 0);  -- original signals from SFP
+  signal link_ok                : std_logic_vector(1 downto 0); -- OJK 02-dec-2013: Changed width from 1 bit to 2 bits
+  signal link_error             : std_logic_vector(10 downto 0);-- OJK 02-dec-2013: Changed width from 10 bits to 11 bits
+  signal ff_txhalfclk           : std_logic;
+  signal ff_rxhalfclk			      : std_logic;
+  signal ff_rxfullclk           : std_logic;
+  --rx fifo signals
+  signal fifo_rx_rd_en          : std_logic;
+  signal fifo_rx_wr_en          : std_logic;
+  signal fifo_rx_reset          : std_logic;
+  signal fifo_rx_din            : std_logic_vector(17 downto 0);
+  signal fifo_rx_dout           : std_logic_vector(17 downto 0);
+  signal fifo_rx_full           : std_logic;
+  signal fifo_rx_empty          : std_logic;
+  --tx fifo signals
+  signal fifo_tx_rd_en          : std_logic;
+  signal fifo_tx_wr_en          : std_logic;
+  signal fifo_tx_reset          : std_logic;
+  signal fifo_tx_din            : std_logic_vector(17 downto 0);
+  signal fifo_tx_dout           : std_logic_vector(17 downto 0);
+  signal fifo_tx_full           : std_logic;
+  signal fifo_tx_empty          : std_logic;
+  signal fifo_tx_almost_full    : std_logic;
+  --rx path
+  signal rx_counter             : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+  signal buf_med_dataready_out  : std_logic;
+  signal buf_med_data_out       : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+  signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+  signal last_rx                : std_logic_vector(8 downto 0);
+  signal last_fifo_rx_empty     : std_logic;
+  --tx path
+  signal last_fifo_tx_empty     : std_logic;
+  --link status
+  signal rx_k_q                 : std_logic_vector(1 downto 0);
+
+  signal quad_rst               : std_logic;
+  signal lane_rst               : std_logic;
+  signal tx_allow               : std_logic;
+  signal rx_allow               : std_logic;
+  signal tx_allow_qtx           : std_logic;
+
+  signal rx_allow_q             : std_logic; -- clock domain changed signal
+  signal tx_allow_q             : std_logic;
+  signal swap_bytes             : std_logic;
+  signal buf_stat_debug         : std_logic_vector(31 downto 0);
+
+  -- status inputs from SFP
+  signal sfp_prsnt_n            : std_logic; -- synchronized input signals
+  signal sfp_los                : std_logic; -- synchronized input signals
+
+  signal buf_STAT_OP            : std_logic_vector(15 downto 0);
+
+  signal led_counter            : unsigned(16 downto 0);
+  signal rx_led                 : std_logic;
+  signal tx_led                 : std_logic;
+
+
+  signal tx_correct             : std_logic_vector(1 downto 0); -- GbE mode SERDES: automatic IDLE2 -> IDLE1 conversion
+  signal first_idle             : std_logic; -- tag the first IDLE2 after data
+
+  signal reset_word_cnt    : unsigned(4 downto 0);
+  signal make_trbnet_reset : std_logic;
+  signal make_trbnet_reset_q : std_logic;
+  signal send_reset_words  : std_logic;
+  signal send_reset_words_q : std_logic;
+  signal send_reset_in      : std_logic;
+  signal send_reset_in_qtx  : std_logic;
+  signal reset_i                : std_logic;
+  signal reset_i_rx             : std_logic;
+  signal pwr_up                 : std_logic;
+  signal clear_n   : std_logic;
+
+  signal clk_sys : std_logic;
+  signal clk_tx  : std_logic;
+  signal clk_rx  : std_logic;
+  signal clk_rxref : std_logic;
+  signal clk_txref : std_logic;
+
+type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
+signal sci_state         : sci_ctrl;
+  signal sci_ch_i        : std_logic_vector(3 downto 0);
+  signal sci_qd_i        : std_logic;
+  signal sci_reg_i       : std_logic;
+  signal sci_addr_i      : std_logic_vector(8 downto 0);
+  signal sci_data_in_i   : std_logic_vector(7 downto 0);
+  signal sci_data_out_i  : std_logic_vector(7 downto 0);
+  signal sci_read_i      : std_logic;
+  signal sci_write_i     : std_logic;
+--  signal sci_write_shift_i : std_logic_vector(2 downto 0);
+--  signal sci_read_shift_i  : std_logic_vector(2 downto 0);  
+  
+  --OJK 13-dec-2013
+  signal cnt             : integer range 0 to 10000;
+  signal tx_pll_lol_qd_i : std_logic;
+  -- Peter Schakel 3-dec-2014
+ 	
+  signal sci_timer            : unsigned(12 downto 0) := (others => '0');
+  signal reset_n              : std_logic;
+  signal trb_rx_serdes_rst    : std_logic;
+  signal trb_rx_cdr_lol       : std_logic;
+  signal trb_rx_los_low       : std_logic;
+  signal trb_rx_pcs_rst       : std_logic;
+  signal trb_tx_pcs_rst       : std_logic;
+  signal rst_qd               : std_logic;
+  signal link_OK_S            : std_logic;
+  signal trb_tx_fsm_state     : std_logic_vector(3 downto 0);
+  signal trb_rx_fsm_state     : std_logic_vector(3 downto 0);
+  
+  signal sync_clk_rx_full     : std_logic;
+  signal sync_clk_rx_half     : std_logic;
+  signal sync_clk_tx_full     : std_logic;
+  signal sync_clk_tx_half     : std_logic;
+  signal sync_tx_k            : std_logic;
+  signal sync_tx_data         : std_logic_vector(7 downto 0);
+
+  signal syncfifo_din         : std_logic_vector(17 downto 0);
+  signal syncfifo_dout        : std_logic_vector(17 downto 0);
+	  
+  signal sync_rx_k            : std_logic;
+  signal sync_rx_data         : std_logic_vector(7 downto 0);
+  signal sync_rx_serdes_rst   : std_logic;
+  signal sync_rx_cdr_lol      : std_logic;
+  signal sync_tx_pcs_rst      : std_logic;
+  signal sync_rx_pcs_rst      : std_logic;
+  signal sync_rx_los_low      : std_logic;
+  signal sync_lsm_status      : std_logic;
+  signal SD_tx_pcs_rst        : std_logic;
+  signal DLM_fifo_rd_en       : std_logic;
+  signal DLM_fifo_empty       : std_logic;
+  signal DLM_fifo_reading     : std_logic := '0';  
+  signal SODA_dlm_word_S      : std_logic_vector(7 downto 0);
+  signal DLM_received_S       : std_logic;
+  signal sync_wa_position_rx  : std_logic_vector(15 downto 0) := x"FFFF";
+  signal wa_position          : std_logic_vector(15 downto 0) := x"FFFF";
+  signal sync_rx_fsm_state    : std_logic_vector(3 downto 0);
+  signal sync_tx_fsm_state    : std_logic_vector(3 downto 0);
+  signal CH3_tx_fsm_state     : std_logic_vector(3 downto 0);
+
+  signal CLKdiv100_S          : std_logic;
+  signal sync_clk_rx_fulldiv100_S     : std_logic;
+			
+  attribute syn_keep : boolean;
+  attribute syn_preserve : boolean;
+  attribute syn_keep of led_counter : signal is true;
+  attribute syn_keep of send_reset_in : signal is true;
+  attribute syn_keep of reset_i : signal is true;
+  attribute syn_preserve of reset_i : signal is true;
+
+begin
+
+--------------------------------------------------------------------------
+-- Select proper clock configuration
+--------------------------------------------------------------------------
+  clk_sys <= SYSCLK;
+  clk_tx  <= SYSCLK;
+  clk_rx  <= ff_rxhalfclk;
+  clk_rxref <= CLK;
+  clk_txref <= CLK;
+
+
+
+
+--------------------------------------------------------------------------
+-- Internal Lane Resets
+--------------------------------------------------------------------------
+  clear_n <= not clear;
+
+
+  PROC_RESET : process(clk_sys)
+    begin
+      if rising_edge(clk_sys) then
+        reset_i <= RESET;
+        send_reset_in <= ctrl_op(15);
+        pwr_up  <= '1'; --not CTRL_OP(i*16+14);
+      end if;
+    end process;
+
+--------------------------------------------------------------------------
+-- Synchronizer stages
+--------------------------------------------------------------------------
+
+-- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)
+THE_SFP_STATUS_SYNC: signal_sync
+  generic map(
+    DEPTH => 3,
+    WIDTH => 2
+    )
+  port map(
+    RESET    => '0',
+    D_IN(0)  => sd_prsnt_n_in,
+    D_IN(1)  => sd_los_in,
+    CLK0     => clk_sys,
+    CLK1     => clk_sys,
+    D_OUT(0) => sfp_prsnt_n,
+    D_OUT(1) => sfp_los
+    );
+
+
+THE_RX_K_SYNC: signal_sync
+  generic map(
+    DEPTH => 1,
+    WIDTH => 4
+    )
+  port map(
+    RESET             => reset_i,
+    D_IN(1 downto 0)  => comb_rx_k,
+    D_IN(2)           => send_reset_words,
+    D_IN(3)           => make_trbnet_reset,
+    CLK0              => clk_rx, -- CHANGED
+    CLK1              => clk_sys,
+    D_OUT(1 downto 0) => rx_k_q,
+    D_OUT(2)          => send_reset_words_q,
+    D_OUT(3)          => make_trbnet_reset_q
+    );
+
+THE_RX_DATA_DELAY: signal_sync
+  generic map(
+    DEPTH => 2,
+    WIDTH => 16
+    )
+  port map(
+    RESET    => reset_i,
+    D_IN     => comb_rx_data,
+    CLK0     => clk_rx,
+    CLK1     => clk_rx,
+    D_OUT    => rx_data
+    );
+
+THE_RX_K_DELAY: signal_sync
+  generic map(
+    DEPTH => 2,
+    WIDTH => 2
+    )
+  port map(
+    RESET    => reset_i,
+    D_IN     => comb_rx_k,
+    CLK0     => clk_rx,
+    CLK1     => clk_rx,
+    D_OUT    => rx_k
+    );
+
+THE_RX_RESET: signal_sync
+  generic map(
+    DEPTH => 1,
+    WIDTH => 1
+    )
+  port map(
+    RESET    => '0',
+    D_IN(0)  => reset_i,
+    CLK0     => clk_rx,
+    CLK1     => clk_rx,
+    D_OUT(0) => reset_i_rx
+    );
+
+-- Delay for ALLOW signals
+THE_RX_ALLOW_SYNC: signal_sync
+  generic map(
+    DEPTH => 2,
+    WIDTH => 2
+    )
+  port map(
+    RESET    => reset_i,
+    D_IN(0)  => rx_allow,
+    D_IN(1)  => tx_allow,
+    CLK0     => clk_sys,
+    CLK1     => clk_sys,
+    D_OUT(0) => rx_allow_q,
+    D_OUT(1) => tx_allow_q
+    );
+
+THE_TX_SYNC: signal_sync
+  generic map(
+    DEPTH => 1,
+    WIDTH => 2
+    )
+  port map(
+    RESET    => '0',
+    D_IN(0)  => send_reset_in,
+    D_IN(1)  => tx_allow,
+    CLK0     => clk_tx,
+    CLK1     => clk_tx,
+    D_OUT(0) => send_reset_in_qtx,
+    D_OUT(1) => tx_allow_qtx
+    );
+
+
+--------------------------------------------------------------------------
+-- Main control state machine, startup control for SFP
+--------------------------------------------------------------------------
+
+THE_SFP_LSM: trb_net16_lsm_sfp
+    generic map (
+      HIGHSPEED_STARTUP => c_YES
+      )
+    port map(
+      SYSCLK            => clk_sys,
+      RESET             => reset_i,
+      CLEAR             => clear,
+      SFP_MISSING_IN    => sfp_prsnt_n,
+      SFP_LOS_IN        => sfp_los,
+      SD_LINK_OK_IN     => link_OK_S, --//  ?? link_ok(0),
+      SD_LOS_IN         => link_error(8),
+      SD_TXCLK_BAD_IN   => link_error(5),
+      SD_RXCLK_BAD_IN   => link_error(4),
+      SD_RETRY_IN       => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
+      SD_ALIGNMENT_IN	=> rx_k_q,
+      SD_CV_IN          => link_error(7 downto 6),
+      FULL_RESET_OUT    => quad_rst,
+      LANE_RESET_OUT    => lane_rst,
+      TX_ALLOW_OUT      => tx_allow,
+      RX_ALLOW_OUT      => rx_allow,
+      SWAP_BYTES_OUT    => swap_bytes,
+      STAT_OP           => buf_stat_op,
+      CTRL_OP           => ctrl_op,
+      STAT_DEBUG        => buf_stat_debug
+      );
+
+sd_txdis_out <= quad_rst or reset_i;
+
+--------------------------------------------------------------------------
+--------------------------------------------------------------------------
+
+ffc_quad_rst         <= quad_rst;
+ffc_lane_tx_rst      <= lane_rst;
+
+
+ffc_lane_rx_rst      <= lane_rst;
+
+-- SerDes clock output to FPGA fabric
+REFCLK2CORE_OUT <= ff_rxhalfclk;
+CLK_RX_HALF_OUT <= ff_rxhalfclk;
+CLK_RX_FULL_OUT <= ff_rxfullclk;
+
+THE_SERDES: sfp_1_2sync_3_200_int port map(
+------------------
+-- CH0 --
+-- CH1 --
+      hdinp_ch1          => sd_rxd_p_in,                
+      hdinn_ch1          => sd_rxd_n_in,                
+      hdoutp_ch1         => sd_txd_p_out,              
+      hdoutn_ch1         => sd_txd_n_out,              
+
+      sci_sel_ch1        => sci_ch_i(1),
+      rxiclk_ch1         => clk_rx,                
+      txiclk_ch1         => clk_tx,                
+      rx_full_clk_ch1    => ff_rxfullclk,          
+      rx_half_clk_ch1    => ff_rxhalfclk,          
+      tx_full_clk_ch1    => open,                  
+      tx_half_clk_ch1    => ff_txhalfclk,          
+      fpga_rxrefclk_ch1  => clk_rxref,             
+      txdata_ch1         => tx_data,               
+      tx_k_ch1           => tx_k,                  
+      tx_force_disp_ch1  => tx_correct,            
+      tx_disp_sel_ch1    => "00",                  
+      rxdata_ch1         => comb_rx_data,          
+      rx_k_ch1           => comb_rx_k,             
+      rx_disp_err_ch1    => open,            
+      rx_cv_err_ch1      => link_error(7 downto 6),
+      rx_serdes_rst_ch1_c => trb_rx_serdes_rst,
+      sb_felb_ch1_c      => '0',                   
+      sb_felb_rst_ch1_c  => '0',                
+      tx_pcs_rst_ch1_c   => trb_tx_pcs_rst,
+      tx_pwrup_ch1_c     => '1',                   
+      rx_pcs_rst_ch1_c   => trb_rx_pcs_rst,
+      rx_pwrup_ch1_c     => '1',                   
+      rx_los_low_ch1_s   => trb_rx_los_low, -- link_error(8),         
+      lsm_status_ch1_s   => link_ok(0),            
+      rx_cdr_lol_ch1_s   => trb_rx_cdr_lol, -- link_error(4),         
+      tx_div2_mode_ch1_c => '0',                   
+      rx_div2_mode_ch1_c => '0',
+
+-- CH2 --
+    hdinp_ch2            => SODA_RXD_P_IN,
+    hdinn_ch2            => SODA_RXD_N_IN,
+    hdoutp_ch2           => SODA_TXD_P_OUT,
+    hdoutn_ch2           => SODA_TXD_N_OUT,
+    sci_sel_ch2          => sci_ch_i(2),
+    rxiclk_ch2           => sync_clk_rx_full, -- ?? CLK,
+    txiclk_ch2           => sync_clk_tx_full, -- ??CLK, --????? clk_txref
+    rx_full_clk_ch2      => sync_clk_rx_full,
+    rx_half_clk_ch2      => sync_clk_rx_half,
+    tx_full_clk_ch2      => sync_clk_tx_full,
+    tx_half_clk_ch2      => sync_clk_tx_half,
+    fpga_rxrefclk_ch2    => CLK,
+    txdata_ch2           => sync_tx_data,
+    tx_k_ch2             => sync_tx_k,
+    tx_force_disp_ch2    => '0',
+    tx_disp_sel_ch2      => '0',
+    rxdata_ch2           => sync_rx_data,
+    rx_k_ch2             => sync_rx_k,
+    rx_disp_err_ch2      => open,
+    rx_cv_err_ch2        => open,
+    rx_serdes_rst_ch2_c  => sync_rx_serdes_rst,
+    sb_felb_ch2_c        => '0',
+    sb_felb_rst_ch2_c    => '0',
+    tx_pcs_rst_ch2_c     => sync_tx_pcs_rst,
+    tx_pwrup_ch2_c       => '1',
+    rx_pcs_rst_ch2_c     => sync_rx_pcs_rst,
+    rx_pwrup_ch2_c       => '1',
+    rx_los_low_ch2_s     => sync_rx_los_low,
+    lsm_status_ch2_s     => sync_lsm_status,
+    rx_cdr_lol_ch2_s     => sync_rx_cdr_lol,
+    tx_div2_mode_ch2_c   => '0',
+    rx_div2_mode_ch2_c   => '0',
+		
+-- CH3 --
+      hdoutp_ch3         => DOUT_TXD_P_OUT,             
+      hdoutn_ch3         => DOUT_TXD_N_OUT,             
+      sci_sel_ch3        => '0', --disable access to channel 3 registers
+      txiclk_ch3         => clk_tx,             
+      tx_full_clk_ch3    => open,                
+      tx_half_clk_ch3    => open,        
+--//????      fpga_rxrefclk_ch3  => clk_rxref,      
+      txdata_ch3         => tx_data_ch3,             
+      tx_k_ch3           => tx_k_ch3,
+      tx_force_disp_ch3  => '0',      
+      tx_disp_sel_ch3    => '0',        
+      tx_pcs_rst_ch3_c   => SD_tx_pcs_rst,
+      tx_pwrup_ch3_c     => '1',         
+      tx_div2_mode_ch3_c => '1', 
+
+---- Miscillaneous ports
+      sci_wrdata         => sci_data_in_i,
+      sci_addr           => sci_addr_i(5 downto 0),
+      sci_rddata         => sci_data_out_i,
+      sci_sel_quad       => sci_qd_i,
+      sci_rd             => sci_read_i,
+      sci_wrn            => sci_write_i,
+      fpga_txrefclk      => clk_txref,               
+      tx_serdes_rst_c    => CLEAR,          
+      tx_pll_lol_qd_s    => tx_pll_lol_qd_i,          
+      tx_sync_qd_c       => '0',             -- Multiple channel transmit synchronization is not needed?
+--//      refclk2fpga        => open,              -- Not needed?
+      rst_qd_c => rst_qd,
+--//??      rst_n              => '1',                   
+      serdes_rst_qd_c    => ffc_quad_rst        
+	);
+
+      syncfifo_din(7 downto 0)  <= SODA_DLM_WORD_IN;
+      syncfifo_din(17 downto 8) <= (others => '0');
+	  SODA_dlm_word_S <= syncfifo_dout(7 downto 0);
+sync_DLM_tx: trb_net_fifo_16bit_bram_dualport
+generic map(
+  USE_STATUS_FLAGS => c_NO
+       )
+port map( read_clock_in  => sync_clk_tx_full,
+      write_clock_in     => sync_clk_rx_full, 
+      read_enable_in     => DLM_fifo_rd_en,
+      write_enable_in    => SODA_DLM_IN,
+      fifo_gsr_in        => reset,
+      write_data_in      => syncfifo_din,
+      read_data_out      => syncfifo_dout,
+      full_out           => open,
+      empty_out          => DLM_fifo_empty
+    );
+
+process(sync_clk_rx_full)
+begin
+  if rising_edge(sync_clk_rx_full) then
+	SODA_DLM_OUT <= '0';
+	if DLM_received_S='1' then
+		DLM_received_S <= '0';
+		SODA_DLM_OUT <= '1';
+		SODA_DLM_WORD_OUT <= sync_rx_data;
+	elsif (sync_rx_data=x"DC") and (sync_rx_k='1') then
+		DLM_received_S <= '1';
+	end if;
+  end if;
+end process;  
+
+process(sync_clk_tx_full)
+begin
+  if rising_edge(sync_clk_tx_full) then
+	if DLM_fifo_rd_en='1' then
+		DLM_fifo_rd_en <= '0';
+		sync_tx_data <= SODA_dlm_word_S;
+		sync_tx_k <= '0';
+	elsif (DLM_fifo_empty='0') and (DLM_fifo_reading='1') then
+		DLM_fifo_rd_en <= '1';
+		sync_tx_data <= x"DC";
+		sync_tx_k <= '1';
+	elsif DLM_fifo_empty='0' then
+		DLM_fifo_reading <= '1';
+		DLM_fifo_rd_en <= '0';
+		sync_tx_data <= x"BC"; -- idle
+		sync_tx_k <= '1';		
+	else
+		DLM_fifo_reading <= '0';
+		DLM_fifo_rd_en <= '0';
+		sync_tx_data <= x"BC"; -- idle
+		sync_tx_k <= '1';
+	end if;
+  end if;
+end process;  
+SODA_CLOCK_OUT <= sync_clk_rx_full;
+
+
+link_error(8) <= trb_rx_los_low; -- loss of signal
+link_error(4) <= '1' when (trb_rx_cdr_lol='1') or (link_OK_S='0') else '0'; -- loss of lock 
+link_error(5) <= tx_pll_lol_qd_i; -- transmit loss of lock
+
+reset_n <= '0' when (RESET='1') or (CLEAR='1')  else '1';
+
+-------------------------------------------------      
+-- Reset FSM & Link states
+------------------------------------------------- 
+THE_RX_FSM1: rx_reset_fsm
+  port map(
+    RST_N               => reset_n,
+    RX_REFCLK           => CLK,
+    TX_PLL_LOL_QD_S     => tx_pll_lol_qd_i,
+    RX_SERDES_RST_CH_C  => trb_rx_serdes_rst,
+    RX_CDR_LOL_CH_S     => trb_rx_cdr_lol,
+    RX_LOS_LOW_CH_S     => trb_rx_los_low,
+    RX_PCS_RST_CH_C     => trb_rx_pcs_rst,
+    WA_POSITION         => "0000",
+    STATE_OUT           => trb_rx_fsm_state
+    );
+
+link_OK_S <= '1' when (link_ok(0)='1') and (trb_rx_fsm_state = x"6") else '0';
+THE_TX_FSM1: tx_reset_fsm
+  port map(
+    RST_N           => reset_n,
+    TX_REFCLK       => CLK,
+    TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
+    RST_QD_C        => rst_qd,
+    TX_PCS_RST_CH_C => trb_tx_pcs_rst,
+    STATE_OUT       => trb_tx_fsm_state
+    );
+
+THE_RX_FSM2: rx_reset_fsm
+  port map(
+    RST_N               => reset_n,
+    RX_REFCLK           => sync_clk_rx_full, --??CLK,
+    TX_PLL_LOL_QD_S     => tx_pll_lol_qd_i,
+    RX_SERDES_RST_CH_C  => sync_rx_serdes_rst,
+    RX_CDR_LOL_CH_S     => sync_rx_cdr_lol,
+    RX_LOS_LOW_CH_S     => sync_rx_los_low,
+    RX_PCS_RST_CH_C     => sync_rx_pcs_rst,
+    WA_POSITION         => sync_wa_position_rx(11 downto 8),
+    STATE_OUT           => sync_rx_fsm_state
+    );
+SYNC_WA_POSITION : process(sync_clk_rx_full) --??CLK)
+begin
+  if rising_edge(sync_clk_rx_full) then
+    sync_wa_position_rx <= wa_position;
+  end if;
+end process;
+    
+THE_TX_FSM2: tx_reset_fsm
+  port map(
+    RST_N           => reset_n,
+    TX_REFCLK       => CLK,
+    TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
+    RST_QD_C        => open, --??
+    TX_PCS_RST_CH_C => sync_tx_pcs_rst,
+    STATE_OUT       => sync_tx_fsm_state
+    );
+	
+THE_TX_FSM3 : tx_reset_fsm
+  port map(
+    RST_N           => reset_n,
+    TX_REFCLK       => CLK,
+    TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
+    RST_QD_C        => open, --??
+    TX_PCS_RST_CH_C => SD_tx_pcs_rst,
+    STATE_OUT       => CH3_tx_fsm_state
+    );
+TX_READY_CH3 <= '1' when (CH3_tx_fsm_state=x"5") and (tx_pll_lol_qd_i='0') else '0';
+	
+	
+-------------------------------------------------------------------------
+-- RX Fifo & Data output
+-------------------------------------------------------------------------
+THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport
+generic map(
+  USE_STATUS_FLAGS => c_NO
+       )
+port map( read_clock_in  => clk_sys,
+      write_clock_in     => clk_rx, -- CHANGED
+      read_enable_in     => fifo_rx_rd_en,
+      write_enable_in    => fifo_rx_wr_en,
+      fifo_gsr_in        => fifo_rx_reset,
+      write_data_in      => fifo_rx_din,
+      read_data_out      => fifo_rx_dout,
+      full_out           => fifo_rx_full,
+      empty_out          => fifo_rx_empty
+    );
+
+fifo_rx_reset <= reset_i or not rx_allow_q;
+fifo_rx_rd_en <= not fifo_rx_empty;
+
+-- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path
+THE_BYTE_SWAP_PROC: process(clk_rx)
+  begin
+    if rising_edge(clk_rx) then
+		last_rx <= rx_k(1) & rx_data(15 downto 8);
+		if( swap_bytes = '0' ) then
+		  fifo_rx_din   <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0);
+		  fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok(0);
+		else
+		  fifo_rx_din   <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0);
+		  fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok(0);
+		end if;
+	end if;
+  end process THE_BYTE_SWAP_PROC;
+
+buf_med_data_out          <= fifo_rx_dout(15 downto 0);
+buf_med_dataready_out     <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q;
+buf_med_packet_num_out    <= rx_counter;
+med_read_out              <= tx_allow_q and not fifo_tx_almost_full;
+
+
+THE_CNT_RESET_PROC : process(clk_rx)
+  begin
+    if rising_edge(clk_rx) then
+		if reset_i_rx = '1' then
+		  send_reset_words  <= '0';
+		  make_trbnet_reset <= '0';
+		  reset_word_cnt    <= (others => '0');
+		else
+		  send_reset_words   <= '0';
+		  make_trbnet_reset  <= '0';
+		  if fifo_rx_din = "11" & x"FEFE" then
+			if reset_word_cnt(4) = '0' then
+			  reset_word_cnt <= reset_word_cnt + to_unsigned(1,1);
+			else
+			  send_reset_words <= '1';
+			end if;
+		  else
+			reset_word_cnt    <= (others => '0');
+			make_trbnet_reset <= reset_word_cnt(4);
+		  end if;
+		end if;
+	end if;
+  end process;
+
+
+THE_SYNC_PROC: process(clk_rx)
+  begin
+    if rising_edge(clk_rx) then
+		med_dataready_out     <= buf_med_dataready_out;
+		med_data_out          <= buf_med_data_out;
+		med_packet_num_out    <= buf_med_packet_num_out;
+		if reset_i = '1' then
+		  med_dataready_out <= '0';
+		end if;
+	end if;
+  end process;
+
+
+--rx packet counter
+---------------------
+THE_RX_PACKETS_PROC: process( clk_sys )
+  begin
+    if( rising_edge(clk_sys) ) then
+      last_fifo_rx_empty <= fifo_rx_empty;
+      if reset_i = '1' or rx_allow_q = '0' then
+        rx_counter <= c_H0;
+      else
+        if( buf_med_dataready_out = '1' ) then
+          if( rx_counter = c_max_word_number ) then
+            rx_counter <= (others => '0');
+          else
+            rx_counter <= std_logic_vector(unsigned(rx_counter) + to_unsigned(1,1));
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+--TX Fifo & Data output to Serdes
+---------------------
+THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport
+  generic map(
+    USE_STATUS_FLAGS => c_NO
+        )
+  port map( read_clock_in => clk_tx,
+        write_clock_in    => clk_sys,
+        read_enable_in    => fifo_tx_rd_en,
+        write_enable_in   => fifo_tx_wr_en,
+        fifo_gsr_in       => fifo_tx_reset,
+        write_data_in     => fifo_tx_din,
+        read_data_out     => fifo_tx_dout,
+        full_out          => fifo_tx_full,
+        empty_out         => fifo_tx_empty,
+        almost_full_out   => fifo_tx_almost_full
+      );
+
+fifo_tx_reset <= reset_i or not tx_allow_q;
+fifo_tx_din   <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in;
+fifo_tx_wr_en <= med_dataready_in and tx_allow_q;
+fifo_tx_rd_en <= tx_allow_qtx;
+
+
+THE_SERDES_INPUT_PROC: process( clk_tx )
+  begin
+    if( rising_edge(clk_tx) ) then
+      last_fifo_tx_empty <= fifo_tx_empty;
+      first_idle <= not last_fifo_tx_empty and fifo_tx_empty;
+      if send_reset_in = '1' then
+        tx_data <= x"FEFE";
+        tx_k <= "11";
+      elsif( (last_fifo_tx_empty = '1') or (tx_allow_qtx = '0') ) then
+        tx_data <= x"50bc";
+        tx_k <= "01";
+        tx_correct <= first_idle & '0';
+      else
+        tx_data <= fifo_tx_dout(15 downto 0);
+        tx_k <= "00";
+        tx_correct <= "00";
+      end if;
+    end if;
+  end process THE_SERDES_INPUT_PROC;
+
+-------------------------------------------------      
+-- SCI
+-------------------------------------------------      
+--gives access to serdes config port from slow control and reads word alignment every ~ 40 us
+PROC_SCI_CTRL: process(clk_sys)
+  variable cnt : integer range 0 to 4 := 0;
+begin
+  if( rising_edge(clk_sys) ) then
+	  SCI_ACK <= '0';
+	  case sci_state is
+		when IDLE =>
+		  sci_ch_i        <= x"0";
+		  sci_qd_i        <= '0';
+		  sci_reg_i       <= '0';
+		  sci_read_i      <= '0';
+		  sci_write_i     <= '0';
+		  sci_timer       <= sci_timer + 1;
+		  if SCI_READ = '1' or SCI_WRITE = '1' then
+			sci_ch_i(0)   <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+			sci_ch_i(1)   <=     SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+			sci_ch_i(2)   <= not SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
+			sci_ch_i(3)   <=     SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
+			sci_qd_i      <= not SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
+			sci_reg_i     <=     SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
+			sci_addr_i    <= SCI_ADDR;
+			sci_data_in_i <= SCI_DATA_IN;
+			sci_read_i    <= SCI_READ  and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
+			sci_write_i   <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
+			sci_state     <= SCTRL;
+		  elsif sci_timer(sci_timer'left) = '1' then
+			sci_timer     <= (others => '0');
+			sci_state     <= GET_WA;
+		  end if;      
+		when SCTRL =>
+		  if sci_reg_i = '1' then
+--//			SCI_DATA_OUT  <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
+			SCI_DATA_OUT  <= (others => '0');
+			SCI_ACK       <= '1';
+			sci_write_i   <= '0';
+			sci_read_i    <= '0';
+			sci_state     <= IDLE;
+		  else
+			sci_state     <= SCTRL_WAIT;
+		  end if;
+		when SCTRL_WAIT   =>
+		  sci_state       <= SCTRL_WAIT2;
+		when SCTRL_WAIT2  =>
+		  sci_state       <= SCTRL_FINISH;
+		when SCTRL_FINISH =>
+		  SCI_DATA_OUT    <= sci_data_out_i;
+		  SCI_ACK         <= '1';
+		  sci_write_i     <= '0';
+		  sci_read_i      <= '0';
+		  sci_state       <= IDLE;
+		
+		when GET_WA =>
+		  if cnt = 4 then
+			cnt           := 0;
+			sci_state     <= IDLE;
+		  else
+			sci_state     <= GET_WA_WAIT;
+			sci_addr_i    <= '0' & x"22";
+			sci_ch_i      <= x"0";
+			sci_ch_i(cnt) <= '1';
+			sci_read_i    <= '1';
+		  end if;
+		when GET_WA_WAIT  =>
+		  sci_state       <= GET_WA_WAIT2;
+		when GET_WA_WAIT2 =>
+		  sci_state       <= GET_WA_FINISH;
+		when GET_WA_FINISH =>
+		  wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
+		  sci_state       <= GET_WA;    
+		  cnt             := cnt + 1;
+	  end case;
+	  
+	  if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
+		SCI_NACK <= '1';
+	  else
+		SCI_NACK <= '0';
+	  end if;
+  end if;
+end process;
+    
+  
+
+--Generate LED signals
+----------------------
+process( clk_sys )
+  begin
+    if rising_edge(clk_sys) then
+      led_counter <= led_counter + to_unsigned(1,1);
+
+      if buf_med_dataready_out = '1' then
+        rx_led <= '1';
+      elsif led_counter = 0 then
+        rx_led <= '0';
+      end if;
+
+      if tx_k(0) = '0' then
+        tx_led <= '1';
+      elsif led_counter = 0 then
+        tx_led <= '0';
+      end if;
+
+    end if;
+  end process;
+
+stat_op(15)           <= send_reset_words_q;
+stat_op(14)           <= buf_stat_op(14);
+stat_op(13)           <= make_trbnet_reset_q;
+stat_op(12)           <= '0';
+stat_op(11)           <= tx_led; --tx led
+stat_op(10)           <= rx_led; --rx led
+stat_op(9 downto 0)   <= buf_stat_op(9 downto 0);
+
+-- Debug output
+stat_debug(15 downto 0)  <= rx_data;
+stat_debug(17 downto 16) <= rx_k;
+stat_debug(19 downto 18) <= (others => '0');
+stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0);
+stat_debug(24)           <= fifo_rx_rd_en;
+stat_debug(25)           <= fifo_rx_wr_en;
+stat_debug(26)           <= fifo_rx_reset;
+stat_debug(27)           <= fifo_rx_empty;
+stat_debug(28)           <= fifo_rx_full;
+stat_debug(29)           <= last_rx(8);
+stat_debug(30)           <= rx_allow_q;
+stat_debug(41 downto 31) <= (others => '0');
+stat_debug(42)           <= clk_sys;
+stat_debug(43)           <= clk_sys;
+stat_debug(59 downto 44) <= (others => '0');
+stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0);
+
+--stat_debug(3 downto 0)   <= buf_stat_debug(3 downto 0); -- state_bits
+--stat_debug(4)            <= buf_stat_debug(4); -- alignme
+--stat_debug(5)            <= sfp_prsnt_n;
+--stat_debug(6)            <= tx_k(0);
+--stat_debug(7)            <= tx_k(1);
+--stat_debug(8)            <= rx_k_q(0);
+--stat_debug(9)            <= rx_k_q(1);
+--stat_debug(18 downto 10) <= link_error;
+--stat_debug(19)           <= '0';
+--stat_debug(20)           <= link_ok(0);
+--stat_debug(38 downto 21) <= fifo_rx_din;
+--stat_debug(39)           <= swap_bytes;
+--stat_debug(40)           <= buf_stat_debug(7); -- sfp_missing_in
+--stat_debug(41)           <= buf_stat_debug(8); -- sfp_los_in
+--stat_debug(42)           <= buf_stat_debug(6); -- resync
+--stat_debug(59 downto 43) <= (others => '0');
+--stat_debug(63 downto 60) <= link_error(3 downto 0);
+
+CLKdiv100_process: process(CLK)
+variable counter_V : integer range 0 to 99 := 0;
+begin
+	if (rising_edge(CLK)) then 
+		if counter_V<49 then -- 99 for 125MHz
+			counter_V := counter_V+1;
+		else
+			counter_V := 0;
+			CLKdiv100_S <= not CLKdiv100_S;
+		end if;
+	end if;
+end process;
+sync_clk_rx_fulldiv100_process: process(sync_clk_rx_full)
+variable counter_V : integer range 0 to 99 := 0;
+begin
+	if (rising_edge(sync_clk_rx_full)) then 
+		if counter_V<49 then -- 99 for 125MHz
+			counter_V := counter_V+1;
+		else
+			counter_V := 0;
+			sync_clk_rx_fulldiv100_S <= not sync_clk_rx_fulldiv100_S;
+		end if;
+	end if;
+end process;
+
+end architecture;
\ No newline at end of file
diff --git a/data_concentrator/sources/lattice/trb_net16_med_1_3_ecp3_sfp.vhd b/data_concentrator/sources/lattice/trb_net16_med_1_3_ecp3_sfp.vhd
new file mode 100644
index 0000000..c2de098
--- /dev/null
+++ b/data_concentrator/sources/lattice/trb_net16_med_1_3_ecp3_sfp.vhd
@@ -0,0 +1,1154 @@
+--Media interface for Lattice ECP3 using PCS at 2GHz
+
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+entity trb_net16_med_1_3_ecp3_sfp is
+  generic(
+    SERDES_NUM : integer range 0 to 3 := 0;
+    EXT_CLOCK  : integer range 0 to 1 := c_NO;
+    USE_200_MHZ: integer range 0 to 1 := c_YES;
+    USE_125_MHZ: integer range 0 to 1 := c_NO;
+    USE_CTC    : integer range 0 to 1 := c_YES;
+    USE_SLAVE  : integer range 0 to 1 := c_NO
+    );
+  port(
+    CLK                : in  std_logic; -- SerDes clock
+    SYSCLK             : in  std_logic; -- fabric clock
+    RESET              : in  std_logic; -- synchronous reset
+    CLEAR              : in  std_logic; -- asynchronous reset
+    CLK_EN             : in  std_logic;
+    --Internal Connection
+    MED_DATA_IN        : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_IN  : in  std_logic_vector(c_NUM_WIDTH-1 downto 0);
+    MED_DATAREADY_IN   : in  std_logic;
+    MED_READ_OUT       : out std_logic;
+    MED_DATA_OUT       : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+    MED_DATAREADY_OUT  : out std_logic;
+    MED_READ_IN        : in  std_logic;
+    REFCLK2CORE_OUT    : out std_logic;
+    CLK_RX_HALF_OUT    : out std_logic;
+    CLK_RX_FULL_OUT    : out std_logic;
+    --SFP Connection
+    SD_RXD_P_IN        : in  std_logic;
+    SD_RXD_N_IN        : in  std_logic;
+    SD_TXD_P_OUT       : out std_logic;
+    SD_TXD_N_OUT       : out std_logic;
+    SD_REFCLK_P_IN     : in  std_logic;
+    SD_REFCLK_N_IN     : in  std_logic;
+    SD_PRSNT_N_IN      : in  std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+    SD_LOS_IN          : in  std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+    SD_TXDIS_OUT       : out  std_logic; -- SFP disable
+    --Control Interface
+    SCI_DATA_IN        : in  std_logic_vector(7 downto 0) := (others => '0');
+    SCI_DATA_OUT       : out std_logic_vector(7 downto 0) := (others => '0');
+    SCI_ADDR           : in  std_logic_vector(8 downto 0) := (others => '0');
+    SCI_READ           : in  std_logic := '0';
+    SCI_WRITE          : in  std_logic := '0';
+    SCI_ACK            : out std_logic := '0';
+    -- Connection to addon interface        
+    SERDES_ADDON_TX    : out std_logic_vector(11 downto 8);
+    SERDES_ADDON_RX    : in  std_logic_vector(11 downto 8);
+    SFP_MOD0_5         : in  std_logic;
+    SFP_MOD0_3         : in  std_logic;          
+    SFP_LOS_5          : in  std_logic;          
+    SFP_LOS_3          : in  std_logic;
+	TX_PLL_LOL_QD      : out std_logic;
+    TX_DATA_CH3        : in std_logic_vector(7 downto 0);
+    TX_K_CH3           : in std_logic;
+    -- Status and control port
+    STAT_OP            : out std_logic_vector (15 downto 0);
+    CTRL_OP            : in  std_logic_vector (15 downto 0);
+    STAT_DEBUG         : out std_logic_vector (63 downto 0);
+    CTRL_DEBUG         : in  std_logic_vector (63 downto 0)
+   );
+end entity;
+
+architecture trb_net16_med_1_3_ecp3_sfp_arch of trb_net16_med_1_3_ecp3_sfp is
+
+
+  -- Placer Directives
+  attribute HGROUP : string;
+  -- for whole architecture
+  attribute HGROUP of trb_net16_med_1_3_ecp3_sfp_arch : architecture  is "media_interface_group";
+  attribute syn_sharing : string;
+  attribute syn_sharing of trb_net16_med_1_3_ecp3_sfp_arch : architecture is "off";
+
+  component sfp_0_200_ctc
+    port(
+      HDINP_CH0          : in std_logic;
+      HDINN_CH0          : in std_logic;
+      HDOUTP_CH0         : out std_logic;
+      HDOUTN_CH0         : out std_logic;
+      
+      RXICLK_CH0         : in std_logic;
+      TXICLK_CH0         : in std_logic;
+      FPGA_RXREFCLK_CH0  : in std_logic;
+      FPGA_TXREFCLK      : in std_logic;
+      RX_FULL_CLK_CH0    : out std_logic;
+      RX_HALF_CLK_CH0    : out std_logic;
+      TX_FULL_CLK_CH0    : out std_logic;
+      TX_HALF_CLK_CH0    : out std_logic;
+
+      TXDATA_CH0         : in std_logic_vector(15 downto 0);
+      TX_K_CH0           : in std_logic_vector(1 downto 0);
+      TX_FORCE_DISP_CH0  : in std_logic_vector(1 downto 0);
+      TX_DISP_SEL_CH0    : in std_logic_vector(1 downto 0);
+      
+      SB_FELB_CH0_C      : in std_logic;
+      SB_FELB_RST_CH0_C  : in std_logic;
+      
+      TX_PWRUP_CH0_C     : in std_logic;
+      RX_PWRUP_CH0_C     : in std_logic;
+      TX_DIV2_MODE_CH0_C : in std_logic;
+      RX_DIV2_MODE_CH0_C : in std_logic;
+      
+      SCI_WRDATA         : in std_logic_vector(7 downto 0);
+      SCI_RDDATA         : out std_logic_vector(7 downto 0);
+      SCI_ADDR           : in std_logic_vector(5 downto 0);
+      SCI_SEL_QUAD       : in std_logic;
+      SCI_RD             : in std_logic;
+      SCI_WRN            : in std_logic;
+      SCI_SEL_CH0        : in std_logic;
+
+      TX_SERDES_RST_C    : in std_logic;
+      RST_N              : in std_logic;
+      SERDES_RST_QD_C    : in std_logic;          
+      
+      RXDATA_CH0         : out std_logic_vector(15 downto 0);
+      RX_K_CH0           : out std_logic_vector(1 downto 0);
+      RX_DISP_ERR_CH0    : out std_logic_vector(1 downto 0);
+      RX_CV_ERR_CH0      : out std_logic_vector(1 downto 0);
+      
+      RX_LOS_LOW_CH0_S   : out std_logic;
+      LSM_STATUS_CH0_S   : out std_logic;
+      RX_CDR_LOL_CH0_S   : out std_logic;
+      TX_PLL_LOL_QD_S    : out std_logic
+      );
+  end component;  
+  
+  component sfp_0_200_int
+    port(
+      HDINP_CH0          : in std_logic;
+      HDINN_CH0          : in std_logic;
+      HDOUTP_CH0         : out std_logic;
+      HDOUTN_CH0         : out std_logic;
+      
+      RXICLK_CH0         : in std_logic;
+      TXICLK_CH0         : in std_logic;
+      FPGA_RXREFCLK_CH0  : in std_logic;
+      FPGA_TXREFCLK      : in std_logic;
+      RX_FULL_CLK_CH0    : out std_logic;
+      RX_HALF_CLK_CH0    : out std_logic;
+      TX_FULL_CLK_CH0    : out std_logic;
+      TX_HALF_CLK_CH0    : out std_logic;
+
+      TXDATA_CH0         : in std_logic_vector(15 downto 0);
+      TX_K_CH0           : in std_logic_vector(1 downto 0);
+      TX_FORCE_DISP_CH0  : in std_logic_vector(1 downto 0);
+      TX_DISP_SEL_CH0    : in std_logic_vector(1 downto 0);
+      
+      SB_FELB_CH0_C      : in std_logic;
+      SB_FELB_RST_CH0_C  : in std_logic;
+      
+      TX_PWRUP_CH0_C     : in std_logic;
+      RX_PWRUP_CH0_C     : in std_logic;
+      TX_DIV2_MODE_CH0_C : in std_logic;
+      RX_DIV2_MODE_CH0_C : in std_logic;
+      
+      SCI_WRDATA         : in std_logic_vector(7 downto 0);
+      SCI_RDDATA         : out std_logic_vector(7 downto 0);
+      SCI_ADDR           : in std_logic_vector(5 downto 0);
+      SCI_SEL_QUAD       : in std_logic;
+      SCI_RD             : in std_logic;
+      SCI_WRN            : in std_logic;
+      SCI_SEL_CH0        : in std_logic;
+
+      TX_SERDES_RST_C    : in std_logic;
+      RST_N              : in std_logic;
+      SERDES_RST_QD_C    : in std_logic;          
+      
+      RXDATA_CH0         : out std_logic_vector(15 downto 0);
+      RX_K_CH0           : out std_logic_vector(1 downto 0);
+      RX_DISP_ERR_CH0    : out std_logic_vector(1 downto 0);
+      RX_CV_ERR_CH0      : out std_logic_vector(1 downto 0);
+      
+      RX_LOS_LOW_CH0_S   : out std_logic;
+      LSM_STATUS_CH0_S   : out std_logic;
+      RX_CDR_LOL_CH0_S   : out std_logic;
+      TX_PLL_LOL_QD_S    : out std_logic
+      );
+  end component;
+
+  component sfp_1_200_int
+    port(
+      HDINP_CH1          : in std_logic;
+      HDINN_CH1          : in std_logic;
+      HDOUTP_CH1         : out std_logic;
+      HDOUTN_CH1         : out std_logic;
+      
+      RXICLK_CH1         : in std_logic;
+      TXICLK_CH1         : in std_logic;
+      FPGA_RXREFCLK_CH1  : in std_logic;
+      FPGA_TXREFCLK      : in std_logic;
+      RX_FULL_CLK_CH1    : out std_logic;
+      RX_HALF_CLK_CH1    : out std_logic;
+      TX_FULL_CLK_CH1    : out std_logic;
+      TX_HALF_CLK_CH1    : out std_logic;
+
+      TXDATA_CH1         : in std_logic_vector(15 downto 0);
+      TX_K_CH1           : in std_logic_vector(1 downto 0);
+      TX_FORCE_DISP_CH1  : in std_logic_vector(1 downto 0);
+      TX_DISP_SEL_CH1    : in std_logic_vector(1 downto 0);
+      
+      SB_FELB_CH1_C      : in std_logic;
+      SB_FELB_RST_CH1_C  : in std_logic;
+      
+      TX_PWRUP_CH1_C     : in std_logic;
+      RX_PWRUP_CH1_C     : in std_logic;
+      TX_DIV2_MODE_CH1_C : in std_logic;
+      RX_DIV2_MODE_CH1_C : in std_logic;
+      
+      SCI_WRDATA         : in std_logic_vector(7 downto 0);
+      SCI_RDDATA         : out std_logic_vector(7 downto 0);
+      SCI_ADDR           : in std_logic_vector(5 downto 0);
+      SCI_SEL_QUAD       : in std_logic;
+      SCI_RD             : in std_logic;
+      SCI_WRN            : in std_logic;
+      SCI_SEL_CH1        : in std_logic;
+
+      TX_SERDES_RST_C    : in std_logic;
+      RST_N              : in std_logic;
+      SERDES_RST_QD_C    : in std_logic;          
+      
+      RXDATA_CH1         : out std_logic_vector(15 downto 0);
+      RX_K_CH1           : out std_logic_vector(1 downto 0);
+      RX_DISP_ERR_CH1    : out std_logic_vector(1 downto 0);
+      RX_CV_ERR_CH1      : out std_logic_vector(1 downto 0);
+      
+      RX_LOS_LOW_CH1_S   : out std_logic;
+      LSM_STATUS_CH1_S   : out std_logic;
+      RX_CDR_LOL_CH1_S   : out std_logic;
+      TX_PLL_LOL_QD_S    : out std_logic
+      );
+  end component;  
+  
+  --OJK 29-nov-2013
+	component sfp_1_3_200_int
+	port(
+		hdinp_ch1          : IN std_logic;
+		hdinn_ch1          : IN std_logic;
+		sci_sel_ch1        : IN std_logic;
+		rxiclk_ch1         : IN std_logic;
+		txiclk_ch1         : IN std_logic;
+		fpga_rxrefclk_ch1  : IN std_logic;
+		txdata_ch1         : IN std_logic_vector(15 downto 0);
+		tx_k_ch1           : IN std_logic_vector(1 downto 0);
+		tx_force_disp_ch1  : IN std_logic_vector(1 downto 0);
+		tx_disp_sel_ch1    : IN std_logic_vector(1 downto 0);
+		sb_felb_ch1_c      : IN std_logic;
+		sb_felb_rst_ch1_c  : IN std_logic;
+		tx_pwrup_ch1_c     : IN std_logic;
+		rx_pwrup_ch1_c     : IN std_logic;
+		tx_div2_mode_ch1_c : IN std_logic;
+		rx_div2_mode_ch1_c : IN std_logic;
+		sci_sel_ch3        : IN std_logic;
+		txiclk_ch3         : IN std_logic;
+		fpga_rxrefclk_ch3  : IN std_logic;
+		txdata_ch3         : IN std_logic_vector(7 downto 0);
+		tx_k_ch3           : IN std_logic;
+		tx_force_disp_ch3  : IN std_logic;
+		tx_disp_sel_ch3    : IN std_logic;
+		tx_pwrup_ch3_c     : IN std_logic;
+		tx_div2_mode_ch3_c : IN std_logic;
+		sci_wrdata         : IN std_logic_vector(7 downto 0);
+		sci_addr           : IN std_logic_vector(5 downto 0);
+		sci_sel_quad       : IN std_logic;
+		sci_rd             : IN std_logic;
+		sci_wrn            : IN std_logic;
+		fpga_txrefclk      : IN std_logic;
+		tx_serdes_rst_c    : IN std_logic;
+		tx_sync_qd_c       : IN std_logic;
+		rst_n              : IN std_logic;
+		serdes_rst_qd_c    : IN std_logic;          
+		hdoutp_ch1         : OUT std_logic;
+		hdoutn_ch1         : OUT std_logic;
+		rx_full_clk_ch1    : OUT std_logic;
+		rx_half_clk_ch1    : OUT std_logic;
+		tx_full_clk_ch1    : OUT std_logic;
+		tx_half_clk_ch1    : OUT std_logic;
+		rxdata_ch1         : OUT std_logic_vector(15 downto 0);
+		rx_k_ch1           : OUT std_logic_vector(1 downto 0);
+		rx_disp_err_ch1    : OUT std_logic_vector(1 downto 0);
+		rx_cv_err_ch1      : OUT std_logic_vector(1 downto 0);
+		rx_los_low_ch1_s   : OUT std_logic;
+		lsm_status_ch1_s   : OUT std_logic;
+		rx_cdr_lol_ch1_s   : OUT std_logic;
+		hdoutp_ch3         : OUT std_logic;
+		hdoutn_ch3         : OUT std_logic;
+		tx_full_clk_ch3    : OUT std_logic;
+		tx_half_clk_ch3    : OUT std_logic;
+		sci_rddata         : OUT std_logic_vector(7 downto 0);
+		tx_pll_lol_qd_s    : OUT std_logic;
+		refclk2fpga        : OUT std_logic
+			);
+	end component;
+  
+  
+  
+  signal refck2core             : std_logic;
+--  signal clock                  : std_logic;
+  --reset signals
+  signal ffc_quad_rst           : std_logic;
+  signal ffc_lane_tx_rst        : std_logic;
+  signal ffc_lane_rx_rst        : std_logic;
+  --serdes connections
+  signal tx_data                : std_logic_vector(15 downto 0);
+  signal tx_k                   : std_logic_vector(1 downto 0);
+  signal rx_data                : std_logic_vector(15 downto 0); -- delayed signals
+  signal rx_k                   : std_logic_vector(1 downto 0);  -- delayed signals
+  signal comb_rx_data           : std_logic_vector(15 downto 0); -- original signals from SFP
+  signal comb_rx_k              : std_logic_vector(1 downto 0);  -- original signals from SFP
+  signal link_ok                : std_logic_vector(1 downto 0); -- OJK 02-dec-2013: Changed width from 1 bit to 2 bits
+  signal link_error             : std_logic_vector(10 downto 0);-- OJK 02-dec-2013: Changed width from 10 bits to 11 bits
+  signal ff_txhalfclk           : std_logic;
+  signal ff_rxhalfclk			      : std_logic;
+  signal ff_rxfullclk           : std_logic;
+  --rx fifo signals
+  signal fifo_rx_rd_en          : std_logic;
+  signal fifo_rx_wr_en          : std_logic;
+  signal fifo_rx_reset          : std_logic;
+  signal fifo_rx_din            : std_logic_vector(17 downto 0);
+  signal fifo_rx_dout           : std_logic_vector(17 downto 0);
+  signal fifo_rx_full           : std_logic;
+  signal fifo_rx_empty          : std_logic;
+  --tx fifo signals
+  signal fifo_tx_rd_en          : std_logic;
+  signal fifo_tx_wr_en          : std_logic;
+  signal fifo_tx_reset          : std_logic;
+  signal fifo_tx_din            : std_logic_vector(17 downto 0);
+  signal fifo_tx_dout           : std_logic_vector(17 downto 0);
+  signal fifo_tx_full           : std_logic;
+  signal fifo_tx_empty          : std_logic;
+  signal fifo_tx_almost_full    : std_logic;
+  --rx path
+  signal rx_counter             : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+  signal buf_med_dataready_out  : std_logic;
+  signal buf_med_data_out       : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+  signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+  signal last_rx                : std_logic_vector(8 downto 0);
+  signal last_fifo_rx_empty     : std_logic;
+  --tx path
+  signal last_fifo_tx_empty     : std_logic;
+  --link status
+  signal rx_k_q                 : std_logic_vector(1 downto 0);
+
+  signal quad_rst               : std_logic;
+  signal lane_rst               : std_logic;
+  signal tx_allow               : std_logic;
+  signal rx_allow               : std_logic;
+  signal tx_allow_qtx           : std_logic;
+
+  signal rx_allow_q             : std_logic; -- clock domain changed signal
+  signal tx_allow_q             : std_logic;
+  signal swap_bytes             : std_logic;
+  signal buf_stat_debug         : std_logic_vector(31 downto 0);
+
+  -- status inputs from SFP
+  signal sfp_prsnt_n            : std_logic; -- synchronized input signals
+  signal sfp_los                : std_logic; -- synchronized input signals
+
+  signal buf_STAT_OP            : std_logic_vector(15 downto 0);
+
+  signal led_counter            : unsigned(16 downto 0);
+  signal rx_led                 : std_logic;
+  signal tx_led                 : std_logic;
+
+
+  signal tx_correct             : std_logic_vector(1 downto 0); -- GbE mode SERDES: automatic IDLE2 -> IDLE1 conversion
+  signal first_idle             : std_logic; -- tag the first IDLE2 after data
+
+  signal reset_word_cnt    : unsigned(4 downto 0);
+  signal make_trbnet_reset : std_logic;
+  signal make_trbnet_reset_q : std_logic;
+  signal send_reset_words  : std_logic;
+  signal send_reset_words_q : std_logic;
+  signal send_reset_in      : std_logic;
+  signal send_reset_in_qtx  : std_logic;
+  signal reset_i                : std_logic;
+  signal reset_i_rx             : std_logic;
+  signal pwr_up                 : std_logic;
+  signal clear_n   : std_logic;
+
+  signal clk_sys : std_logic;
+  signal clk_tx  : std_logic;
+  signal clk_rx  : std_logic;
+  signal clk_rxref : std_logic;
+  signal clk_txref : std_logic;
+
+  signal sci_ch_i       : std_logic_vector(3 downto 0);
+  signal sci_addr_i     : std_logic_vector(8 downto 0);
+  signal sci_data_in_i  : std_logic_vector(7 downto 0);
+  signal sci_data_out_i : std_logic_vector(7 downto 0);
+  signal sci_read_i     : std_logic;
+  signal sci_write_i    : std_logic;
+  signal sci_write_shift_i : std_logic_vector(2 downto 0);
+  signal sci_read_shift_i  : std_logic_vector(2 downto 0);  
+  
+  --OJK 13-dec-2013
+  signal cnt             : integer range 0 to 10000;
+  signal tx_pll_lol_qd_i : std_logic;
+  
+  attribute syn_keep : boolean;
+  attribute syn_preserve : boolean;
+  attribute syn_keep of led_counter : signal is true;
+  attribute syn_keep of send_reset_in : signal is true;
+  attribute syn_keep of reset_i : signal is true;
+  attribute syn_preserve of reset_i : signal is true;
+
+begin
+
+
+--------------------------------------------------------------------------
+-- Select proper clock configuration
+--------------------------------------------------------------------------
+gen_clocks_200_ctc : if USE_200_MHZ = c_YES and USE_CTC = c_YES and USE_SLAVE = c_NO generate
+  clk_sys <= SYSCLK;
+  clk_tx  <= SYSCLK;
+  clk_rx  <= SYSCLK;
+  clk_rxref <= CLK;
+  clk_txref <= CLK;
+end generate;
+
+
+gen_clocks_200_noctc : if USE_200_MHZ = c_YES and USE_CTC = c_NO and USE_SLAVE = c_NO  generate --OJK <== We're using this one!
+  clk_sys <= SYSCLK;
+  clk_tx  <= SYSCLK;
+  clk_rx  <= ff_rxhalfclk;
+  clk_rxref <= CLK;
+  clk_txref <= CLK;
+end generate;
+
+
+gen_clocks_200_ctc_sync : if USE_200_MHZ = c_YES and USE_CTC = c_YES and USE_SLAVE = c_YES generate
+  clk_sys <= SYSCLK;
+  clk_tx  <= ff_rxhalfclk;
+  clk_rx  <= ff_rxhalfclk;
+  clk_rxref <= CLK;
+  clk_txref <= ff_rxfullclk;
+end generate;
+
+
+gen_clocks_200_noctc_sync : if USE_200_MHZ = c_YES and USE_CTC = c_NO and USE_SLAVE = c_YES  generate
+  clk_sys <= SYSCLK;
+  clk_tx  <= ff_rxhalfclk;
+  clk_rx  <= ff_rxhalfclk;
+  clk_rxref <= CLK;
+  clk_txref <= ff_rxfullclk;
+end generate;
+
+
+gen_clocks_125_noctc : if USE_125_MHZ = c_YES and USE_CTC = c_NO and USE_SLAVE = c_NO  generate
+  clk_sys <= SYSCLK;
+  clk_tx  <= SYSCLK;
+  clk_rx  <= ff_rxhalfclk;
+  clk_rxref <= CLK;
+  clk_txref <= CLK;
+end generate;
+
+--------------------------------------------------------------------------
+-- Internal Lane Resets
+--------------------------------------------------------------------------
+  clear_n <= not clear;
+
+
+  PROC_RESET : process(clk_sys)
+    begin
+      if rising_edge(clk_sys) then
+        reset_i <= RESET;
+        send_reset_in <= ctrl_op(15);
+        pwr_up  <= '1'; --not CTRL_OP(i*16+14);
+      end if;
+    end process;
+
+--------------------------------------------------------------------------
+-- Synchronizer stages
+--------------------------------------------------------------------------
+
+-- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)
+THE_SFP_STATUS_SYNC: signal_sync
+  generic map(
+    DEPTH => 3,
+    WIDTH => 2
+    )
+  port map(
+    RESET    => '0',
+    D_IN(0)  => sd_prsnt_n_in,
+    D_IN(1)  => sd_los_in,
+    CLK0     => clk_sys,
+    CLK1     => clk_sys,
+    D_OUT(0) => sfp_prsnt_n,
+    D_OUT(1) => sfp_los
+    );
+
+
+THE_RX_K_SYNC: signal_sync
+  generic map(
+    DEPTH => 1,
+    WIDTH => 4
+    )
+  port map(
+    RESET             => reset_i,
+    D_IN(1 downto 0)  => comb_rx_k,
+    D_IN(2)           => send_reset_words,
+    D_IN(3)           => make_trbnet_reset,
+    CLK0              => clk_rx, -- CHANGED
+    CLK1              => clk_sys,
+    D_OUT(1 downto 0) => rx_k_q,
+    D_OUT(2)          => send_reset_words_q,
+    D_OUT(3)          => make_trbnet_reset_q
+    );
+
+THE_RX_DATA_DELAY: signal_sync
+  generic map(
+    DEPTH => 2,
+    WIDTH => 16
+    )
+  port map(
+    RESET    => reset_i,
+    D_IN     => comb_rx_data,
+    CLK0     => clk_rx,
+    CLK1     => clk_rx,
+    D_OUT    => rx_data
+    );
+
+THE_RX_K_DELAY: signal_sync
+  generic map(
+    DEPTH => 2,
+    WIDTH => 2
+    )
+  port map(
+    RESET    => reset_i,
+    D_IN     => comb_rx_k,
+    CLK0     => clk_rx,
+    CLK1     => clk_rx,
+    D_OUT    => rx_k
+    );
+
+THE_RX_RESET: signal_sync
+  generic map(
+    DEPTH => 1,
+    WIDTH => 1
+    )
+  port map(
+    RESET    => '0',
+    D_IN(0)  => reset_i,
+    CLK0     => clk_rx,
+    CLK1     => clk_rx,
+    D_OUT(0) => reset_i_rx
+    );
+
+-- Delay for ALLOW signals
+THE_RX_ALLOW_SYNC: signal_sync
+  generic map(
+    DEPTH => 2,
+    WIDTH => 2
+    )
+  port map(
+    RESET    => reset_i,
+    D_IN(0)  => rx_allow,
+    D_IN(1)  => tx_allow,
+    CLK0     => clk_sys,
+    CLK1     => clk_sys,
+    D_OUT(0) => rx_allow_q,
+    D_OUT(1) => tx_allow_q
+    );
+
+THE_TX_SYNC: signal_sync
+  generic map(
+    DEPTH => 1,
+    WIDTH => 2
+    )
+  port map(
+    RESET    => '0',
+    D_IN(0)  => send_reset_in,
+    D_IN(1)  => tx_allow,
+    CLK0     => clk_tx,
+    CLK1     => clk_tx,
+    D_OUT(0) => send_reset_in_qtx,
+    D_OUT(1) => tx_allow_qtx
+    );
+
+
+--------------------------------------------------------------------------
+-- Main control state machine, startup control for SFP
+--------------------------------------------------------------------------
+
+THE_SFP_LSM: trb_net16_lsm_sfp
+    generic map (
+      HIGHSPEED_STARTUP => c_YES
+      )
+    port map(
+      SYSCLK            => clk_sys,
+      RESET             => reset_i,
+      CLEAR             => clear,
+      SFP_MISSING_IN    => sfp_prsnt_n,
+      SFP_LOS_IN        => sfp_los,
+      SD_LINK_OK_IN     => link_ok(0),
+      SD_LOS_IN         => link_error(8),
+      SD_TXCLK_BAD_IN   => link_error(5),
+      SD_RXCLK_BAD_IN   => link_error(4),
+      SD_RETRY_IN       => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
+      SD_ALIGNMENT_IN	=> rx_k_q,
+      SD_CV_IN          => link_error(7 downto 6),
+      FULL_RESET_OUT    => quad_rst,
+      LANE_RESET_OUT    => lane_rst,
+      TX_ALLOW_OUT      => tx_allow,
+      RX_ALLOW_OUT      => rx_allow,
+      SWAP_BYTES_OUT    => swap_bytes,
+      STAT_OP           => buf_stat_op,
+      CTRL_OP           => ctrl_op,
+      STAT_DEBUG        => buf_stat_debug
+      );
+
+sd_txdis_out <= quad_rst or reset_i;
+
+--------------------------------------------------------------------------
+--------------------------------------------------------------------------
+
+ffc_quad_rst         <= quad_rst;
+ffc_lane_tx_rst      <= lane_rst;
+
+
+ffc_lane_rx_rst      <= lane_rst;
+
+-- SerDes clock output to FPGA fabric
+REFCLK2CORE_OUT <= ff_rxhalfclk;
+CLK_RX_HALF_OUT <= ff_rxhalfclk;
+CLK_RX_FULL_OUT <= ff_rxfullclk;
+
+
+-- Instantiation of serdes module
+
+  gen_serdes_0_200_ctc : if SERDES_NUM = 0 and EXT_CLOCK = c_NO and USE_200_MHZ = c_YES and USE_CTC = c_YES generate
+    THE_SERDES: sfp_0_200_ctc
+      port map(
+        HDINP_CH0           => sd_rxd_p_in,
+        HDINN_CH0           => sd_rxd_n_in,
+        HDOUTP_CH0          => sd_txd_p_out,
+        HDOUTN_CH0          => sd_txd_n_out,
+
+        RXICLK_CH0          => clk_rx,
+        TXICLK_CH0          => clk_tx,
+        FPGA_RXREFCLK_CH0   => clk_rxref,
+        FPGA_TXREFCLK       => clk_txref,
+        RX_FULL_CLK_CH0     => ff_rxfullclk,
+        RX_HALF_CLK_CH0     => ff_rxhalfclk,
+        TX_FULL_CLK_CH0     => open,
+        TX_HALF_CLK_CH0     => ff_txhalfclk,
+
+        TXDATA_CH0          => tx_data,
+        TX_K_CH0            => tx_k,
+        TX_FORCE_DISP_CH0   => tx_correct,
+        TX_DISP_SEL_CH0     => "00",
+
+        SB_FELB_CH0_C       => '0', --loopback enable
+        SB_FELB_RST_CH0_C   => '0', --loopback reset
+
+        TX_PWRUP_CH0_C      => '1', --tx power up
+        RX_PWRUP_CH0_C      => '1', --rx power up
+        TX_DIV2_MODE_CH0_C  => '0', --full rate
+        RX_DIV2_MODE_CH0_C  => '0', --full rate
+
+        SCI_WRDATA          => sci_data_in_i,
+        SCI_RDDATA          => sci_data_out_i,
+        SCI_ADDR            => sci_addr_i(5 downto 0),
+        SCI_SEL_QUAD        => sci_addr_i(8),
+        SCI_SEL_CH0         => sci_ch_i(0),
+        SCI_RD              => sci_read_i,
+        SCI_WRN             => sci_write_i,
+
+        TX_SERDES_RST_C     => CLEAR,
+        RST_N               => '1',
+        SERDES_RST_QD_C     => ffc_quad_rst,
+
+        RXDATA_CH0          => comb_rx_data,
+        RX_K_CH0            => comb_rx_k,
+        RX_DISP_ERR_CH0     => open,
+        RX_CV_ERR_CH0       => link_error(7 downto 6),
+
+        RX_LOS_LOW_CH0_S    => link_error(8),
+        LSM_STATUS_CH0_S    => link_ok(0),
+        RX_CDR_LOL_CH0_S    => link_error(4),
+        TX_PLL_LOL_QD_S     => link_error(5)    
+        );
+  end generate;
+
+  gen_serdes_0_200 : if SERDES_NUM = 0 and EXT_CLOCK = c_NO and USE_200_MHZ = c_YES and USE_CTC = c_NO generate
+    THE_SERDES: sfp_0_200_int
+      port map(
+        HDINP_CH0           => sd_rxd_p_in,
+        HDINN_CH0           => sd_rxd_n_in,
+        HDOUTP_CH0          => sd_txd_p_out,
+        HDOUTN_CH0          => sd_txd_n_out,
+
+        RXICLK_CH0          => clk_rx,
+        TXICLK_CH0          => clk_tx,
+        FPGA_RXREFCLK_CH0   => clk_rxref,
+        FPGA_TXREFCLK       => clk_txref,
+        RX_FULL_CLK_CH0     => ff_rxfullclk,
+        RX_HALF_CLK_CH0     => ff_rxhalfclk,
+        TX_FULL_CLK_CH0     => open,
+        TX_HALF_CLK_CH0     => ff_txhalfclk,
+
+        TXDATA_CH0          => tx_data,
+        TX_K_CH0            => tx_k,
+        TX_FORCE_DISP_CH0   => tx_correct,
+        TX_DISP_SEL_CH0     => "00",
+
+        SB_FELB_CH0_C       => '0', --loopback enable
+        SB_FELB_RST_CH0_C   => '0', --loopback reset
+
+        TX_PWRUP_CH0_C      => '1', --tx power up
+        RX_PWRUP_CH0_C      => '1', --rx power up
+        TX_DIV2_MODE_CH0_C  => '0', --full rate
+        RX_DIV2_MODE_CH0_C  => '0', --full rate
+
+        SCI_WRDATA          => sci_data_in_i,
+        SCI_RDDATA          => sci_data_out_i,
+        SCI_ADDR            => sci_addr_i(5 downto 0),
+        SCI_SEL_QUAD        => sci_addr_i(8),
+        SCI_SEL_CH0         => sci_ch_i(0),
+        SCI_RD              => sci_read_i,
+        SCI_WRN             => sci_write_i,
+
+        TX_SERDES_RST_C     => CLEAR,
+        RST_N               => '1',
+        SERDES_RST_QD_C     => ffc_quad_rst,
+
+        RXDATA_CH0          => comb_rx_data,
+        RX_K_CH0            => comb_rx_k,
+        RX_DISP_ERR_CH0     => open,
+        RX_CV_ERR_CH0       => link_error(7 downto 6),
+
+        RX_LOS_LOW_CH0_S    => link_error(8),
+        LSM_STATUS_CH0_S    => link_ok(0),
+        RX_CDR_LOL_CH0_S    => link_error(4),
+        TX_PLL_LOL_QD_S     => link_error(5)    
+        );
+  end generate;
+
+  gen_serdes_1_200 : if SERDES_NUM = 1 and EXT_CLOCK = c_NO and USE_200_MHZ = c_YES and USE_CTC = c_NO generate
+    --OJK 29-nov-2013
+    THE_SERDES: sfp_1_3_200_int port map(
+      hdinp_ch1          => sd_rxd_p_in,                
+      hdinn_ch1          => sd_rxd_n_in,                
+      hdoutp_ch1         => sd_txd_p_out,              
+      hdoutn_ch1         => sd_txd_n_out,              
+
+      sci_sel_ch1        => sci_ch_i(1),
+      rxiclk_ch1         => clk_rx,                
+      txiclk_ch1         => clk_tx,                
+      rx_full_clk_ch1    => ff_rxfullclk,          
+      rx_half_clk_ch1    => ff_rxhalfclk,          
+      tx_full_clk_ch1    => open,                  
+      tx_half_clk_ch1    => ff_txhalfclk,          
+      fpga_rxrefclk_ch1  => clk_rxref,             
+      txdata_ch1         => tx_data,               
+      tx_k_ch1           => tx_k,                  
+      tx_force_disp_ch1  => tx_correct,            
+      tx_disp_sel_ch1    => "00",                  
+      rxdata_ch1         => comb_rx_data,          
+      rx_k_ch1           => comb_rx_k,             
+      rx_disp_err_ch1    => open,            
+      rx_cv_err_ch1      => link_error(7 downto 6),
+      sb_felb_ch1_c      => '0',                   
+      sb_felb_rst_ch1_c  => '0',                
+      tx_pwrup_ch1_c     => '1',                   
+      rx_pwrup_ch1_c     => '1',                   
+      rx_los_low_ch1_s   => link_error(8),         
+      lsm_status_ch1_s   => link_ok(0),            
+      rx_cdr_lol_ch1_s   => link_error(4),         
+      tx_div2_mode_ch1_c => '0',                   
+      rx_div2_mode_ch1_c => '0',
+      
+      hdoutp_ch3         => SERDES_ADDON_TX(10),             
+      hdoutn_ch3         => SERDES_ADDON_TX(11),             
+      sci_sel_ch3        => '0', --disable access to channel 3 registers
+      txiclk_ch3         => clk_tx,             
+      tx_full_clk_ch3    => open,                
+      tx_half_clk_ch3    => open,        
+      fpga_rxrefclk_ch3  => clk_rxref,      
+      txdata_ch3         => tx_data_ch3,             
+      tx_k_ch3           => tx_k_ch3,
+      tx_force_disp_ch3  => '0',      
+      tx_disp_sel_ch3    => '0',        
+      tx_pwrup_ch3_c     => '1',         
+      tx_div2_mode_ch3_c => '1', 
+      
+      sci_wrdata         => sci_data_in_i,
+      sci_addr           => sci_addr_i(5 downto 0),
+      sci_rddata         => sci_data_out_i,
+      sci_sel_quad       => sci_addr_i(8),
+      sci_rd             => sci_read_i,
+      sci_wrn            => sci_write_i,
+      fpga_txrefclk      => clk_txref,               
+      tx_serdes_rst_c    => CLEAR,          
+      tx_pll_lol_qd_s    => tx_pll_lol_qd_i,          
+      tx_sync_qd_c       => '0',             -- Multiple channel transmit synchronization is not needed?
+      refclk2fpga        => open,              -- Not needed?
+      rst_n              => '1',                   
+      serdes_rst_qd_c    => ffc_quad_rst        
+    );                     
+	
+    link_error(5) <= tx_pll_lol_qd_i;
+	TX_PLL_LOL_QD <= tx_pll_lol_qd_i;
+	
+      -- THE_SERDES: sfp_1_200_int
+      -- port map(
+        -- HDINP_CH1           => sd_rxd_p_in,
+        -- HDINN_CH1           => sd_rxd_n_in,
+        -- HDOUTP_CH1          => sd_txd_p_out,
+        -- HDOUTN_CH1          => sd_txd_n_out,
+
+        -- RXICLK_CH1          => clk_rx,
+        -- TXICLK_CH1          => clk_tx,
+        -- FPGA_RXREFCLK_CH1   => clk_rxref,
+        -- FPGA_TXREFCLK       => clk_txref,
+        -- RX_FULL_CLK_CH1     => ff_rxfullclk,
+        -- RX_HALF_CLK_CH1     => ff_rxhalfclk,
+        -- TX_FULL_CLK_CH1     => open,
+        -- TX_HALF_CLK_CH1     => ff_txhalfclk,
+
+        -- TXDATA_CH1          => tx_data,
+        -- TX_K_CH1            => tx_k,
+        -- TX_FORCE_DISP_CH1   => tx_correct,
+        -- TX_DISP_SEL_CH1     => "00",
+
+        -- SB_FELB_CH1_C       => '0', --loopback enable
+        -- SB_FELB_RST_CH1_C   => '0', --loopback reset
+
+        -- TX_PWRUP_CH1_C      => '1', --tx power up
+        -- RX_PWRUP_CH1_C      => '1', --rx power up
+        -- TX_DIV2_MODE_CH1_C  => '0', --full rate
+        -- RX_DIV2_MODE_CH1_C  => '0', --full rate
+
+        -- SCI_WRDATA          => sci_data_in_i,
+        -- SCI_RDDATA          => sci_data_out_i,
+        -- SCI_ADDR            => sci_addr_i(5 downto 0),
+        -- SCI_SEL_QUAD        => sci_addr_i(8),
+        -- SCI_SEL_CH1         => sci_ch_i(1),
+        -- SCI_RD              => sci_read_i,
+        -- SCI_WRN             => sci_write_i,
+
+
+        -- TX_SERDES_RST_C     => CLEAR,
+        -- RST_N               => '1',
+        -- SERDES_RST_QD_C     => ffc_quad_rst,
+
+        -- RXDATA_CH1          => comb_rx_data,
+        -- RX_K_CH1            => comb_rx_k,
+        -- RX_DISP_ERR_CH1     => open,
+        -- RX_CV_ERR_CH1       => link_error(7 downto 6),
+
+        -- RX_LOS_LOW_CH1_S    => link_error(8),
+        -- LSM_STATUS_CH1_S    => link_ok(0),
+        -- RX_CDR_LOL_CH1_S    => link_error(4),
+        -- TX_PLL_LOL_QD_S     => link_error(5)    
+        -- );
+  end generate;
+  
+  gen_serdes_1_125 : if SERDES_NUM = 1 and EXT_CLOCK = c_NO and USE_125_MHZ = c_YES and USE_CTC = c_NO generate
+    THE_SERDES: entity work.sfp_1_125_int
+      port map(
+        HDINP_CH1           => sd_rxd_p_in,
+        HDINN_CH1           => sd_rxd_n_in,
+        HDOUTP_CH1          => sd_txd_p_out,
+        HDOUTN_CH1          => sd_txd_n_out,
+
+        RXICLK_CH1          => clk_rx,
+        TXICLK_CH1          => clk_tx,
+        FPGA_RXREFCLK_CH1   => clk_rxref,
+        FPGA_TXREFCLK       => clk_txref,
+        RX_FULL_CLK_CH1     => ff_rxfullclk,
+        RX_HALF_CLK_CH1     => ff_rxhalfclk,
+        TX_FULL_CLK_CH1     => open,
+        TX_HALF_CLK_CH1     => ff_txhalfclk,
+
+        TXDATA_CH1          => tx_data,
+        TX_K_CH1            => tx_k,
+        TX_FORCE_DISP_CH1   => tx_correct,
+        TX_DISP_SEL_CH1     => "00",
+
+        SB_FELB_CH1_C       => '0', --loopback enable
+        SB_FELB_RST_CH1_C   => '0', --loopback reset
+
+        TX_PWRUP_CH1_C      => '1', --tx power up
+        RX_PWRUP_CH1_C      => '1', --rx power up
+        TX_DIV2_MODE_CH1_C  => '0', --full rate
+        RX_DIV2_MODE_CH1_C  => '0', --full rate
+
+        SCI_WRDATA          => sci_data_in_i,
+        SCI_RDDATA          => sci_data_out_i,
+        SCI_ADDR            => sci_addr_i(5 downto 0),
+        SCI_SEL_QUAD        => sci_addr_i(8),
+        SCI_SEL_CH1         => sci_ch_i(1),
+        SCI_RD              => sci_read_i,
+        SCI_WRN             => sci_write_i,
+
+
+        TX_SERDES_RST_C     => CLEAR,
+        RST_N               => '1',
+        SERDES_RST_QD_C     => ffc_quad_rst,
+
+        RXDATA_CH1          => comb_rx_data,
+        RX_K_CH1            => comb_rx_k,
+        RX_DISP_ERR_CH1     => open,
+        RX_CV_ERR_CH1       => link_error(7 downto 6),
+
+        RX_LOS_LOW_CH1_S    => link_error(8),
+        LSM_STATUS_CH1_S    => link_ok(0),
+        RX_CDR_LOL_CH1_S    => link_error(4),
+        TX_PLL_LOL_QD_S     => link_error(5)    
+        );
+  end generate;  
+-------------------------------------------------------------------------
+-- RX Fifo & Data output
+-------------------------------------------------------------------------
+THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport
+generic map(
+  USE_STATUS_FLAGS => c_NO
+       )
+port map( read_clock_in  => clk_sys,
+      write_clock_in     => clk_rx, -- CHANGED
+      read_enable_in     => fifo_rx_rd_en,
+      write_enable_in    => fifo_rx_wr_en,
+      fifo_gsr_in        => fifo_rx_reset,
+      write_data_in      => fifo_rx_din,
+      read_data_out      => fifo_rx_dout,
+      full_out           => fifo_rx_full,
+      empty_out          => fifo_rx_empty
+    );
+
+fifo_rx_reset <= reset_i or not rx_allow_q;
+fifo_rx_rd_en <= not fifo_rx_empty;
+
+-- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path
+THE_BYTE_SWAP_PROC: process
+  begin
+    wait until rising_edge(clk_rx);  --CHANGED
+    last_rx <= rx_k(1) & rx_data(15 downto 8);
+    if( swap_bytes = '0' ) then
+      fifo_rx_din   <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0);
+      fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok(0);
+    else
+      fifo_rx_din   <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0);
+      fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok(0);
+    end if;
+  end process THE_BYTE_SWAP_PROC;
+
+buf_med_data_out          <= fifo_rx_dout(15 downto 0);
+buf_med_dataready_out     <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q;
+buf_med_packet_num_out    <= rx_counter;
+med_read_out              <= tx_allow_q and not fifo_tx_almost_full;
+
+
+THE_CNT_RESET_PROC : process
+  begin
+    wait until rising_edge(clk_rx);  --CHANGED
+    if reset_i_rx = '1' then
+      send_reset_words  <= '0';
+      make_trbnet_reset <= '0';
+      reset_word_cnt    <= (others => '0');
+    else
+      send_reset_words   <= '0';
+      make_trbnet_reset  <= '0';
+      if fifo_rx_din = "11" & x"FEFE" then
+        if reset_word_cnt(4) = '0' then
+          reset_word_cnt <= reset_word_cnt + to_unsigned(1,1);
+        else
+          send_reset_words <= '1';
+        end if;
+      else
+        reset_word_cnt    <= (others => '0');
+        make_trbnet_reset <= reset_word_cnt(4);
+      end if;
+    end if;
+  end process;
+
+
+THE_SYNC_PROC: process
+  begin
+    wait until rising_edge(clk_sys);
+    med_dataready_out     <= buf_med_dataready_out;
+    med_data_out          <= buf_med_data_out;
+    med_packet_num_out    <= buf_med_packet_num_out;
+    if reset_i = '1' then
+      med_dataready_out <= '0';
+    end if;
+  end process;
+
+
+--rx packet counter
+---------------------
+THE_RX_PACKETS_PROC: process( clk_sys )
+  begin
+    if( rising_edge(clk_sys) ) then
+      last_fifo_rx_empty <= fifo_rx_empty;
+      if reset_i = '1' or rx_allow_q = '0' then
+        rx_counter <= c_H0;
+      else
+        if( buf_med_dataready_out = '1' ) then
+          if( rx_counter = c_max_word_number ) then
+            rx_counter <= (others => '0');
+          else
+            rx_counter <= std_logic_vector(unsigned(rx_counter) + to_unsigned(1,1));
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+--TX Fifo & Data output to Serdes
+---------------------
+THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport
+  generic map(
+    USE_STATUS_FLAGS => c_NO
+        )
+  port map( read_clock_in => clk_tx,
+        write_clock_in    => clk_sys,
+        read_enable_in    => fifo_tx_rd_en,
+        write_enable_in   => fifo_tx_wr_en,
+        fifo_gsr_in       => fifo_tx_reset,
+        write_data_in     => fifo_tx_din,
+        read_data_out     => fifo_tx_dout,
+        full_out          => fifo_tx_full,
+        empty_out         => fifo_tx_empty,
+        almost_full_out   => fifo_tx_almost_full
+      );
+
+fifo_tx_reset <= reset_i or not tx_allow_q;
+fifo_tx_din   <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in;
+fifo_tx_wr_en <= med_dataready_in and tx_allow_q;
+fifo_tx_rd_en <= tx_allow_qtx;
+
+
+THE_SERDES_INPUT_PROC: process( clk_tx )
+  begin
+    if( rising_edge(clk_tx) ) then
+      last_fifo_tx_empty <= fifo_tx_empty;
+      first_idle <= not last_fifo_tx_empty and fifo_tx_empty;
+      if send_reset_in = '1' then
+        tx_data <= x"FEFE";
+        tx_k <= "11";
+      elsif( (last_fifo_tx_empty = '1') or (tx_allow_qtx = '0') ) then
+        tx_data <= x"50bc";
+        tx_k <= "01";
+        tx_correct <= first_idle & '0';
+      else
+        tx_data <= fifo_tx_dout(15 downto 0);
+        tx_k <= "00";
+        tx_correct <= "00";
+      end if;
+    end if;
+  end process THE_SERDES_INPUT_PROC;
+
+  
+--SCI
+----------------------
+PROC_SCI : process begin
+  wait until rising_edge(clk_sys);
+  if SCI_READ = '1' or SCI_WRITE = '1' then
+    sci_ch_i(0)   <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+    sci_ch_i(1)   <=     SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+    sci_ch_i(2)   <= not SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
+    sci_ch_i(3)   <=     SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
+    sci_addr_i    <= SCI_ADDR;
+    sci_data_in_i <= SCI_DATA_IN;
+  end if;
+  sci_read_shift_i  <= sci_read_shift_i(1 downto 0) & SCI_READ;
+  sci_write_shift_i <= sci_write_shift_i(1 downto 0) & SCI_WRITE;
+  SCI_DATA_OUT      <= sci_data_out_i;
+end process;
+
+sci_write_i <= or_all(sci_write_shift_i);
+sci_read_i  <= or_all(sci_read_shift_i);
+SCI_ACK     <= sci_write_shift_i(2) or sci_read_shift_i(2);
+  
+    
+  
+
+--Generate LED signals
+----------------------
+process( clk_sys )
+  begin
+    if rising_edge(clk_sys) then
+      led_counter <= led_counter + to_unsigned(1,1);
+
+      if buf_med_dataready_out = '1' then
+        rx_led <= '1';
+      elsif led_counter = 0 then
+        rx_led <= '0';
+      end if;
+
+      if tx_k(0) = '0' then
+        tx_led <= '1';
+      elsif led_counter = 0 then
+        tx_led <= '0';
+      end if;
+
+    end if;
+  end process;
+
+stat_op(15)           <= send_reset_words_q;
+stat_op(14)           <= buf_stat_op(14);
+stat_op(13)           <= make_trbnet_reset_q;
+stat_op(12)           <= '0';
+stat_op(11)           <= tx_led; --tx led
+stat_op(10)           <= rx_led; --rx led
+stat_op(9 downto 0)   <= buf_stat_op(9 downto 0);
+
+-- Debug output
+stat_debug(15 downto 0)  <= rx_data;
+stat_debug(17 downto 16) <= rx_k;
+stat_debug(19 downto 18) <= (others => '0');
+stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0);
+stat_debug(24)           <= fifo_rx_rd_en;
+stat_debug(25)           <= fifo_rx_wr_en;
+stat_debug(26)           <= fifo_rx_reset;
+stat_debug(27)           <= fifo_rx_empty;
+stat_debug(28)           <= fifo_rx_full;
+stat_debug(29)           <= last_rx(8);
+stat_debug(30)           <= rx_allow_q;
+stat_debug(41 downto 31) <= (others => '0');
+stat_debug(42)           <= clk_sys;
+stat_debug(43)           <= clk_sys;
+stat_debug(59 downto 44) <= (others => '0');
+stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0);
+
+--stat_debug(3 downto 0)   <= buf_stat_debug(3 downto 0); -- state_bits
+--stat_debug(4)            <= buf_stat_debug(4); -- alignme
+--stat_debug(5)            <= sfp_prsnt_n;
+--stat_debug(6)            <= tx_k(0);
+--stat_debug(7)            <= tx_k(1);
+--stat_debug(8)            <= rx_k_q(0);
+--stat_debug(9)            <= rx_k_q(1);
+--stat_debug(18 downto 10) <= link_error;
+--stat_debug(19)           <= '0';
+--stat_debug(20)           <= link_ok(0);
+--stat_debug(38 downto 21) <= fifo_rx_din;
+--stat_debug(39)           <= swap_bytes;
+--stat_debug(40)           <= buf_stat_debug(7); -- sfp_missing_in
+--stat_debug(41)           <= buf_stat_debug(8); -- sfp_los_in
+--stat_debug(42)           <= buf_stat_debug(6); -- resync
+--stat_debug(59 downto 43) <= (others => '0');
+--stat_debug(63 downto 60) <= link_error(3 downto 0);
+
+end architecture;
\ No newline at end of file
diff --git a/data_concentrator/sources/lattice/tx_reset_sm.vhd b/data_concentrator/sources/lattice/tx_reset_sm.vhd
new file mode 100644
index 0000000..763d5e3
--- /dev/null
+++ b/data_concentrator/sources/lattice/tx_reset_sm.vhd
@@ -0,0 +1,174 @@
+--TX Reset Sequence state machine--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity tx_reset_sm is
+port (
+	rst_n 			: in std_logic;
+	refclkdiv2      : in std_logic;
+	tx_pll_lol_qd_s : in std_logic;
+	rst_qd_c		: out std_logic;
+	tx_pcs_rst_ch_c : out std_logic_vector(3 downto 0);
+	STATE_OUT       : out std_logic_vector(3 downto 0)
+	);
+end tx_reset_sm;
+
+architecture tx_reset_sm_arch of tx_reset_sm is
+
+type statetype is (QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NORMAL);
+
+signal	cs:		statetype;	-- current state of lsm
+signal	ns:		statetype;	-- next state of lsm
+
+signal 	tx_pll_lol_qd_s_int	: std_logic;
+signal 	tx_pcs_rst_ch_c_int	: std_logic_vector(3 downto 0);
+signal 	rst_qd_c_int		: std_logic;
+	
+signal 	reset_timer1:	std_logic;
+signal	reset_timer2:	std_logic;
+
+signal	counter1:		std_logic_vector(2 downto 0);
+signal	TIMER1:			std_logic;
+
+signal	counter2:		std_logic_vector(18 downto 0);
+signal	TIMER2:			std_logic;
+
+begin
+
+process (refclkdiv2, rst_n) 
+begin
+	if rst_n = '0' then 
+		cs <= QUAD_RESET;
+		tx_pll_lol_qd_s_int <= '1';
+		tx_pcs_rst_ch_c <= "1111";
+		rst_qd_c <= '1';
+	else if rising_edge(refclkdiv2) then
+		cs <= ns;
+		tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
+		tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int;
+		rst_qd_c <= rst_qd_c_int;
+	end if;
+	end if;
+end process;
+
+
+--TIMER1 = 20ns;
+--Fastest REFLCK =312 MHZ, or 3 ns. We need 8 REFCLK cycles or 4 REFCLKDIV2 cycles
+-- A 2 bit counter ([1:0]) counts 4 cycles, so a 3 bit ([2:0]) counter will do if we set TIMER1 = bit[2]
+
+
+process (refclkdiv2, reset_timer1) 
+begin
+	if rising_edge(refclkdiv2) then
+		if reset_timer1 = '1' then
+			counter1 <= "000";
+			TIMER1 <= '0';
+		else 				
+			if counter1(2) = '1' then
+				TIMER1 <= '1';
+			else
+				TIMER1 <='0';
+				counter1 <= counter1 + 1 ;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+--TIMER2 = 1,400,000 UI;
+--WORST CASE CYCLES is with smallest multipier factor.
+-- This would be with X8 clock multiplier in DIV2 mode
+-- IN this casse, 1 UI = 2/8 REFCLK  CYCLES = 1/8 REFCLKDIV2 CYCLES
+-- SO 1,400,000 UI =1,400,000/8 = 175,000 REFCLKDIV2 CYCLES
+-- An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
+
+
+process(refclkdiv2, reset_timer2) 
+begin
+	if rising_edge(refclkdiv2) then
+		if reset_timer2 = '1' then 
+			counter2 <= "0000000000000000000";
+			TIMER2 <= '0';
+		else 
+			if counter2(18) = '1' then
+--			if counter2(4) = '1' then		-- for simulation
+				TIMER2 <='1';
+			else
+				TIMER2 <='0';
+				counter2 <= counter2 + 1 ;
+			end if;
+		end if;
+	end if;
+end process;
+
+process(cs, TIMER1, TIMER2, tx_pll_lol_qd_s_int)
+begin
+
+		reset_timer1 <= '0';        
+		reset_timer2 <= '0';        
+
+	case cs is     
+  	
+      when QUAD_RESET	=> 
+		tx_pcs_rst_ch_c_int <= "1111";        
+		rst_qd_c_int <= '1';        
+		reset_timer1 <= '1';        
+      	ns <= WAIT_FOR_TIMER1;
+                		
+      when WAIT_FOR_TIMER1	=> 
+		tx_pcs_rst_ch_c_int <= "1111";        
+		rst_qd_c_int <= '1';
+		if TIMER1 = '1' then 
+			ns <= CHECK_PLOL;
+		else	
+			ns <= WAIT_FOR_TIMER1;
+      	end if;
+
+      when CHECK_PLOL	=> 
+		tx_pcs_rst_ch_c_int <= "1111";        
+		rst_qd_c_int <= '0';        
+		reset_timer2 <= '1';        
+      	ns <= WAIT_FOR_TIMER2;
+      	    		
+      when WAIT_FOR_TIMER2	=> 
+		tx_pcs_rst_ch_c_int <= "1111";        
+		rst_qd_c_int <= '0';
+		if TIMER2 = '1' then 
+			if tx_pll_lol_qd_s_int = '1' then
+				ns <= QUAD_RESET;
+			else
+				ns <= NORMAL;
+			end if;
+		else
+	   		ns <= WAIT_FOR_TIMER2;					
+     	    	end if;
+     	
+	when NORMAL	=> 
+		tx_pcs_rst_ch_c_int <= "0000";        
+		rst_qd_c_int <= '0';
+		if tx_pll_lol_qd_s_int = '1' then 
+			ns <= QUAD_RESET;
+		else	
+			ns <= NORMAL;
+      	end if;
+
+	when others =>
+		ns <= 	QUAD_RESET;
+	
+	end case;
+
+end process;
+
+STATE_OUT <= 
+	x"1" when cs=QUAD_RESET else
+	x"2" when cs=WAIT_FOR_TIMER1 else
+	x"3" when cs=CHECK_PLOL else
+	x"4" when cs=WAIT_FOR_TIMER2 else
+	x"5" when cs=NORMAL else
+	x"f";
+
+	
+end tx_reset_sm_arch;	
diff --git a/data_concentrator/sources/posedge_to_pulse.vhd b/data_concentrator/sources/posedge_to_pulse.vhd
new file mode 100644
index 0000000..ee1437f
--- /dev/null
+++ b/data_concentrator/sources/posedge_to_pulse.vhd
@@ -0,0 +1,72 @@
+-----------------------------------------------------------------------------------
+-- posedge_to_pulse
+--		Makes pulse with duration 1 clock-cycle from positive edge
+--	
+-- inputs
+--		clock_in : clock input for input signal
+--		clock_out : clock input to synchronize to
+--		en_clk : clock enable
+--		signal_in : rising edge of this signal will result in pulse
+--
+--	output
+--		pulse : pulse output : one clock cycle '1'
+--
+-----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity posedge_to_pulse is
+	port (
+		clock_in     : in  std_logic;
+		clock_out     : in  std_logic;
+		en_clk    : in  std_logic;
+		signal_in : in  std_logic;
+		pulse     : out std_logic
+	);
+end posedge_to_pulse;
+
+architecture behavioral of posedge_to_pulse is
+
+  signal resetff	: std_logic := '0';
+  signal last_signal_in	: std_logic := '0';
+  signal qff	: std_logic := '0'; 
+  signal qff1	: std_logic := '0'; 
+  signal qff2	: std_logic := '0'; 
+  signal qff3	: std_logic := '0'; 
+begin  
+
+process (clock_in)
+begin
+	if rising_edge(clock_in) then
+		if resetff='1' then
+			qff <= '0';
+		elsif (en_clk='1') and ((signal_in='1') and (qff='0') and (last_signal_in='0')) then 
+			qff <= '1';
+		else
+			qff <= qff;
+		end if;
+		last_signal_in <= signal_in;
+	end if;
+end process;
+resetff <= qff2;
+
+process (clock_out)
+begin
+	if rising_edge(clock_out) then
+		if qff3='0' and qff2='1' then 
+			pulse <= '1'; 
+		else 
+			pulse <= '0';
+		end if;
+		qff3 <= qff2;
+		qff2 <= qff1;
+		qff1 <= qff;
+	end if;
+end process; 
+
+
+end behavioral;
+
diff --git a/data_concentrator/sources/rxFifo_MUX.vhd b/data_concentrator/sources/rxFifo_MUX.vhd
new file mode 100644
index 0000000..fe7e722
--- /dev/null
+++ b/data_concentrator/sources/rxFifo_MUX.vhd
@@ -0,0 +1,144 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   23-08-2013
+-- Module Name:   rxFifo_MUX
+-- Description:   FIFO with 16 bits to 32 bits conversion and SODA signal extraction
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use work.gtpBufLayer.All;
+
+----------------------------------------------------------------------------------
+-- rxFifo_MUX
+-- FIFO with 16 bits to 32 bits conversion and SODA
+-- Data is first converted to 32-bits, alignment is done with check on first word after idles
+-- The resulting 32-bits word is written in an asynchronous 32-bits fifo.
+--
+-- Library
+--     work.gtpBufLayer : for GTP/GTX/serdes constants
+--
+-- Generics:
+-- 
+-- Inputs:
+--     write_clock : clock for the 32-bits input data
+--     read_clock : clock for the 16-bits output data
+--     reset : reset
+--     data_in : 16-bits input data
+--     char_is_k : corresponding input byte is K-character
+--     data_read : read signal for 32-bits output data
+-- 
+-- Outputs:
+--     RX_DLM : SODA signal found in the stream
+--     RX_DLM_WORD : SODA signal : 1 byte
+--     data_out : 32-bits output data
+--     data_available : data available in the output fifo
+--     overflow : fifo buffer overflow: some input data is lost
+--     error : error in input data (invalid k-characters)
+-- 
+-- Components:
+--     async_fifo_512x32 : 32-bits asynchronous fifo
+--
+----------------------------------------------------------------------------------
+
+
+entity rxFifo_MUX is
+	port ( 
+		write_clock             : in std_logic;
+		read_clock              : in std_logic;
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(15 downto 0);
+		char_is_k               : in std_logic_vector(1 downto 0);
+		RX_DLM                  : out std_logic;
+		RX_DLM_WORD             : out std_logic_vector(7 downto 0);
+		data_out                : out std_logic_vector(31 downto 0);
+		data_read               : in std_logic;
+		data_available          : out std_logic;
+		overflow                : out std_logic;
+		error                   : out std_logic		
+	);
+end rxFifo_MUX;
+
+architecture Behavioral of rxFifo_MUX is
+
+component async_fifo_512x32
+	port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(31 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(31 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic);
+end component;
+
+signal fifo_write_S             : std_logic;
+signal fifo_datain_S            : std_logic_vector(31 downto 0);
+signal data_in_S                : std_logic_vector(31 downto 16);
+signal fifo_full_S              : std_logic;
+signal fifo_empty_S             : std_logic;
+signal error_S                  : std_logic := '0';
+signal nextword_low_S           : std_logic := '0';
+signal RX_DLM_S                 : std_logic;
+signal RX_DLM_WORD_S            : std_logic_vector(7 downto 0);
+
+begin
+
+error <= error_S;
+
+fifo: async_fifo_512x32 port map(
+		rst => reset,
+		wr_clk => write_clock,
+		rd_clk => read_clock,
+		din(15 downto 0) => fifo_datain_S(31 downto 16),
+		din(31 downto 16) => fifo_datain_S(15 downto 0),
+		wr_en => fifo_write_S, 
+		rd_en => data_read,
+		dout => data_out,
+		full => fifo_full_S,
+		empty => fifo_empty_S);
+data_available <= '1' when fifo_empty_S='0' else '0';
+
+RX_DLM_S <= '1' when (char_is_k="01") and (data_in(7 downto 0)=KCHARSODA) else '0';
+RX_DLM <= RX_DLM_S;
+RX_DLM_WORD <= data_in(15 downto 8) when RX_DLM_S='1' else RX_DLM_WORD_S;
+
+fifo_write_S <= '1' when (nextword_low_S='1') and (char_is_k="00") and (fifo_full_S='0') else '0';
+overflow <= '1' when (nextword_low_S='1') and (char_is_k="00") and (fifo_full_S='1') else '0';
+fifo_datain_S <= data_in_S(31 downto 16) & data_in; 
+
+rx_process : process(write_clock)
+begin
+	if rising_edge(write_clock) then
+		error_S <= '0';
+		if reset='1' then
+			nextword_low_S <= '0';
+		else
+			if char_is_k="11" then -- idle
+				if data_in/=KCHARIDLE then
+					error_S <= '1';
+				end if;
+				nextword_low_S <= '0';
+			elsif (char_is_k="01") and (data_in(7 downto 0)=KCHARSODA) then
+				RX_DLM_WORD_S <= data_in(15 downto 8); -- keep DLM value
+			elsif char_is_k="00" then -- data
+				if nextword_low_S='0' then
+					data_in_S(31 downto 16) <= data_in;
+					nextword_low_S <= '1';
+				else
+					nextword_low_S <= '0';
+				end if;
+			else
+				error_S <= '1';
+			end if;
+		end if;
+	end if;
+end process;
+
+
+
+end Behavioral;
+
diff --git a/data_concentrator/sources/serdesQuadBufLayerMUX.vhd b/data_concentrator/sources/serdesQuadBufLayerMUX.vhd
new file mode 100644
index 0000000..cd971e1
--- /dev/null
+++ b/data_concentrator/sources/serdesQuadBufLayerMUX.vhd
@@ -0,0 +1,695 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel / Michel Hevinga
+-- Create Date:   18-07-2013
+-- Module Name:   serdesQuadBufLayerMUX
+-- Description:   Module to use 2 GTP/GTX with synchronized transmit frequency and 16 bits bus
+-- Modifications:
+--   29-08-2014   ADCCLOCKFREQUENCY added: SODA clock at 80MHz 
+--   20-11-2014   Data width to/from serdesQuadMUXwrapper
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+USE work.gtpBufLayer.all;
+
+----------------------------------------------------------------------------------
+-- serdesQuadBufLayerMUX
+-- Dual GTP/GTX tranceiver for PANDA Front End Electronics and Multiplexer with synchronised transmitted data.
+--
+-- Synchronous data (SODA) is combined with asynchrounous data (used for Slow-control) and transmitted.
+-- Synchrounous data will always be sent immmidiately. Asynchronous data is buffered in a fifo first.
+-- Received data is also buffered in a fifo.
+--
+-- SODA packages starts with 2 K2.80 characters (0x1C,0x1C) and ends with 2 K28.1 characters (0x3C,0x3C)
+-- Idle's consists of K2.81 & K2.85 characters (0x3c,0xBC)
+--
+--
+-- Library
+--     work.gtpBufLayer : for GTP/GTX constants
+--
+-- Generics:
+-- 
+-- Inputs:
+--     gtpClk : Reference clock for GTP/GTX, synchronous with transmitted data
+--     sysClk : Local bus system clock for serdes control interface and LEDs
+--     reset : reset
+--     reset_fibers : reset fiber connections (serdes or GTP/GTX)
+--     txAsyncClk : clock for the asynchronous 32-bits data to be transmitted
+--     rxAsyncClk : Clock for the asynchronous (32-bits) received data
+--     txUsrClkDiv2 : clock div 2 for the synchronous data to be transmitted 
+--   For channel0 in quad serdes :
+--     G0_txAsyncData : asynchronous 32-bits data to be transmitted
+--     G0_txAsyncDataWrite : write signal for asynchronous 32-bits data to be transmitted
+--     G0_rxAsyncDataRead : read signal for asynchronous 32-bits received data
+--     G0_TX_DLM : transmit SODA character
+--     G0_TX_DLM_WORD : SODA character to be transmitted
+--     G0_LOS : no fiber signal detected
+--     G0_rxP,G0_rxN :  differential input to the serdes
+--   For channel1 in quad serdes :
+--     G1_txAsyncData : asynchronous 32-bits data to be transmitted
+--     G1_txAsyncDataWrite : write signal for asynchronous 32-bits data to be transmitted
+--     G1_rxAsyncDataRead : read signal for asynchronous 32-bits received data
+--     G1_TX_DLM : transmit SODA character
+--     G1_TX_DLM_WORD : SODA character to be transmitted
+--     G1_LOS : no fiber signal detected
+--     G1_rxP,G1_rxN :  differential input to the serdes
+--   For channel2 in quad serdes :
+--     G2_txAsyncData : asynchronous 32-bits data to be transmitted
+--     G2_txAsyncDataWrite : write signal for asynchronous 32-bits data to be transmitted
+--     G2_rxAsyncDataRead : read signal for asynchronous 32-bits received data
+--     G2_TX_DLM : transmit SODA character
+--     G2_TX_DLM_WORD : SODA character to be transmitted
+--     G2_LOS : no fiber signal detected
+--     G2_rxP,G1_rxN :  differential input to the serdes
+--   For channel3 in quad serdes :
+--     G3_txAsyncData : asynchronous 32-bits data to be transmitted
+--     G3_txAsyncDataWrite : write signal for asynchronous 32-bits data to be transmitted
+--     G3_rxAsyncDataRead : read signal for asynchronous 32-bits received data
+--     G3_TX_DLM : transmit SODA character
+--     G3_TX_DLM_WORD : SODA character to be transmitted
+--     G3_LOS : no fiber signal detected
+--     G3_rxP,G1_rxN :  differential input to the serdes
+--     SCI_DATA_IN : serdes control interface : data
+--     SCI_ADDR : serdes control interface : address
+--     SCI_READ : serdes control interface : read
+--     SCI_WRITE : serdes control interface : write
+-- 
+-- Outputs:
+--     refClkOut : buffered reference clock from the GP/GTX
+--     refClk_OK : indicates if refClkOut is stable (PLL locked)
+--     txpll_clocks : clock from serdes for transmit data, not used for synchronous outpu
+--   For channel0 in dual GTP/GTX  :
+--     G0_txAsyncFifoFull : Fifo buffer for asynchronous 32-bits data is full
+--     G0_rxAsyncData : Received 32-bits asynchronous data
+--     G0_rxAsyncDataOverflow : Overflow in fifo for received 32-bits asynchronous data: error, data lost
+--     G0_rxAsyncDataPresent : Received 32-bits asynchronous data is available
+--     G0_status : status of serdes:
+--        bit 0 : Resetting ready
+--        bit 1 : Transmitter clock locked
+--        bit 2 : Receiver clock locked
+--        bit 3 : Received character is invalid (not in table)
+--     G0_RX_DLM : SODA character received
+--     G0_RX_DLM_WORD : SODA character 
+--     G0_txP,G0_txN : differential transmit outputs of the serdes
+--   For channel1 in dual serdes  :
+--     G1_txAsyncFifoFull : Fifo buffer for asynchronous 32-bits data is full
+--     G1_rxAsyncData : Received 32-bits asynchronous data
+--     G1_rxAsyncDataOverflow : Overflow in fifo for received 32-bits asynchronous data: error, data lost
+--     G1_rxAsyncDataPresent : Received 32-bits asynchronous data is available
+--     G1_status : status of serdes:
+--        bit 0 : Resetting ready
+--        bit 1 : Transmitter clock locked
+--        bit 2 : Receiver clock locked
+--        bit 3 : Received character is invalid (not in table)
+--     G1_RX_DLM : SODA character received
+--     G1_RX_DLM_WORD : SODA character 
+--     G1_txP,G1_txN : differential transmit outputs of the serdes
+--   For channel2 in dual serdes  :
+--     G2_txAsyncFifoFull : Fifo buffer for asynchronous 32-bits data is full
+--     G2_rxAsyncData : Received 32-bits asynchronous data
+--     G2_rxAsyncDataOverflow : Overflow in fifo for received 32-bits asynchronous data: error, data lost
+--     G2_rxAsyncDataPresent : Received 32-bits asynchronous data is available
+--     G2_status : status of serdes:
+--        bit 0 : Resetting ready
+--        bit 1 : Transmitter clock locked
+--        bit 2 : Receiver clock locked
+--        bit 3 : Received character is invalid (not in table)
+--     G2_RX_DLM : SODA character received
+--     G2_RX_DLM_WORD : SODA character 
+--     G2_txP,G2_txN : differential transmit outputs of the serdes
+--   For channel3 in dual serdes  :
+--     G3_txAsyncFifoFull : Fifo buffer for asynchronous 32-bits data is full
+--     G3_rxAsyncData : Received 32-bits asynchronous data
+--     G3_rxAsyncDataOverflow : Overflow in fifo for received 32-bits asynchronous data: error, data lost
+--     G3_rxAsyncDataPresent : Received 32-bits asynchronous data is available
+--     G3_status : status of serdes:
+--        bit 0 : Resetting ready
+--        bit 1 : Transmitter clock locked
+--        bit 2 : Receiver clock locked
+--        bit 3 : Received character is invalid (not in table)
+--     G3_RX_DLM : SODA character received
+--     G3_RX_DLM_WORD : SODA character 
+--     G3_txP,G3_txN : differential transmit outputs of the serdes
+--     SCI_DATA_OUT : serdes control interface : data
+--     SCI_ACK : serdes control interface : acknowledge
+--     SCI_NACK : serdes control interface : not acknowledge
+--     LEDs_link_ok : serdes status for LED on extension board : link ok
+--     LEDs_rx : serdes status for LED on extension board : receive
+--     LEDs_tx : serdes status for LED on extension board : transmit
+-- 
+-- Components:
+--     serdesQuadMUXwrapper : module with the quad serdes interface
+--     txFifo_MUX : fifo for data to be transmitted, converts data from 32-bits to 16-bits
+--     rxFifo_MUX : fifo for received asynchronous data, converts data from 16-bits to 32-bits
+--
+----------------------------------------------------------------------------------
+
+entity serdesQuadBufLayerMUX is 
+	port (
+		gtpClk                  : in std_logic;
+		sysClk                  : in  std_logic;
+		reset                   : in std_logic;
+		reset_fibers            : in std_logic;
+		txAsyncClk              : in std_logic;
+		rxAsyncClk              : in std_logic;
+
+		txUsrClkDiv2            : in std_logic;
+		refClkOut               : out std_logic;
+		refClk_OK               : out std_logic;
+		txpll_clocks            : out std_logic_vector(3 downto 0);
+
+		G0_txAsyncData          : in std_logic_vector (31 downto 0);
+		G0_txAsyncDataWrite     : in std_logic;
+		G0_txAsyncFifoFull      : out std_logic;
+		G0_rxAsyncData          : out std_logic_vector (31 downto 0);
+		G0_rxAsyncDataRead      : in std_logic;
+		G0_rxAsyncDataOverflow  : out std_logic;
+		G0_rxAsyncDataPresent   : out std_logic;
+		G0_status               : out std_logic_vector (7 downto 0);
+		G0_TX_DLM               : in  std_logic;
+		G0_TX_DLM_WORD          : in  std_logic_vector(7 downto 0); 
+		G0_RX_DLM               : out std_logic;
+		G0_RX_DLM_WORD          : out std_logic_vector(7 downto 0);
+		G0_LOS                  : in std_logic;
+		G0_txP                  : out std_logic;
+		G0_txN                  : out std_logic;
+		G0_rxP                  : in std_logic;
+		G0_rxN                  : in std_logic;
+  
+		G1_txAsyncData          : in std_logic_vector (31 downto 0);
+		G1_txAsyncDataWrite     : in std_logic;
+		G1_txAsyncFifoFull      : out std_logic;
+		G1_rxAsyncData          : out std_logic_vector (31 downto 0);
+		G1_rxAsyncDataRead      : in std_logic;
+		G1_rxAsyncDataOverflow  : out std_logic;
+		G1_rxAsyncDataPresent   : out std_logic;
+		G1_status               : out std_logic_vector (7 downto 0);
+		G1_TX_DLM               : in  std_logic;
+		G1_TX_DLM_WORD          : in  std_logic_vector(7 downto 0);   
+		G1_RX_DLM               : out std_logic;
+		G1_RX_DLM_WORD          : out std_logic_vector(7 downto 0);
+		G1_LOS                  : in std_logic;
+		G1_txP                  : out std_logic;
+		G1_txN                  : out std_logic;
+		G1_rxP                  : in std_logic;
+		G1_rxN                  : in std_logic;
+
+		G2_txAsyncData          : in std_logic_vector (31 downto 0);
+		G2_txAsyncDataWrite     : in std_logic;
+		G2_txAsyncFifoFull      : out std_logic;
+		G2_rxAsyncData          : out std_logic_vector (31 downto 0);
+		G2_rxAsyncDataRead      : in std_logic;
+		G2_rxAsyncDataOverflow  : out std_logic;
+		G2_rxAsyncDataPresent   : out std_logic;
+		G2_status               : out std_logic_vector (7 downto 0);
+		G2_TX_DLM               : in  std_logic;
+		G2_TX_DLM_WORD          : in  std_logic_vector(7 downto 0);  
+		G2_RX_DLM               : out std_logic;
+		G2_RX_DLM_WORD          : out std_logic_vector(7 downto 0);
+		G2_LOS                  : in std_logic;
+		G2_txP                  : out std_logic;
+		G2_txN                  : out std_logic;
+		G2_rxP                  : in std_logic;
+		G2_rxN                  : in std_logic;
+
+		G3_txAsyncData          : in std_logic_vector (31 downto 0);
+		G3_txAsyncDataWrite     : in std_logic;
+		G3_txAsyncFifoFull      : out std_logic;
+		G3_rxAsyncData          : out std_logic_vector (31 downto 0);
+		G3_rxAsyncDataRead      : in std_logic;
+		G3_rxAsyncDataOverflow  : out std_logic;
+		G3_rxAsyncDataPresent   : out std_logic;
+		G3_status               : out std_logic_vector (7 downto 0);
+		G3_TX_DLM               : in  std_logic;
+		G3_TX_DLM_WORD          : in  std_logic_vector(7 downto 0);   
+		G3_RX_DLM               : out std_logic;
+		G3_RX_DLM_WORD          : out std_logic_vector(7 downto 0);
+		G3_LOS                  : in std_logic;
+		G3_txP                  : out std_logic;
+		G3_txN                  : out std_logic;
+		G3_rxP                  : in std_logic;
+		G3_rxN                  : in std_logic;
+
+		--Control Interface
+		SCI_DATA_IN             : in  std_logic_vector(7 downto 0) := (others => '0');
+		SCI_DATA_OUT            : out std_logic_vector(7 downto 0) := (others => '0');
+		SCI_ADDR                : in  std_logic_vector(8 downto 0) := (others => '0');
+		SCI_READ                : in  std_logic := '0';
+		SCI_WRITE               : in  std_logic := '0';
+		SCI_ACK                 : out std_logic := '0';
+		SCI_NACK                : out std_logic := '0';
+
+		LEDs_link_ok            : out std_logic_vector(0 to 3);
+		LEDs_rx                 : out std_logic_vector(0 to 3); 
+		LEDs_tx                 : out std_logic_vector(0 to 3);
+
+		testPin                 : out  std_logic_vector(3 downto 0);
+		testword0               : out std_logic_vector (35 downto 0); 
+		testword0clock          : out std_logic
+	);
+end serdesQuadBufLayerMUX;
+
+architecture Behavioral of serdesQuadBufLayerMUX is
+
+component serdesQuadMUXwrapper is
+	port ( 	
+		gtpClk                  : in  std_logic;
+		sysClk                  : in  std_logic;
+		gtpReset                : in  std_logic;
+		
+		txUsrClkDiv2            : in std_logic;
+		refClkOut               : out std_logic;
+		refClk_OK               : out std_logic;
+		txpll_clocks            : out std_logic_vector(3 downto 0);
+		
+		G0_txData               : in  std_logic_vector (7 downto 0);
+		G0_rxData               : out  std_logic_vector (7 downto 0);
+		G0_txP                  : out  std_logic;
+		G0_txN                  : out  std_logic;
+		G0_rxP                  : in  std_logic;
+		G0_rxN                  : in  std_logic;
+		G0_LOS                  : in std_logic;
+		G0_rxUsrClk             : out  std_logic;
+		G0_resetDone            : out  std_logic;
+		G0_rxLocked             : out  std_logic;
+		G0_rxNotInTable         : out  std_logic;
+		G0_txLocked             : out  std_logic;
+		G0_txCharIsK0           : in  std_logic;
+		G0_rxCharIsK0           : out  std_logic;
+
+		G1_txData               : in  std_logic_vector (7 downto 0);
+		G1_rxData               : out  std_logic_vector (7 downto 0);
+		G1_txP                  : out  std_logic;
+		G1_txN                  : out  std_logic;
+		G1_rxP                  : in  std_logic;
+		G1_rxN                  : in  std_logic;
+		G1_LOS                  : in std_logic;
+		G1_rxUsrClk             : out  std_logic;
+		G1_resetDone            : out  std_logic;
+		G1_rxLocked             : out  std_logic;
+		G1_rxNotInTable         : out  std_logic;
+		G1_txLocked             : out  std_logic;
+		G1_txCharIsK0           : in  std_logic;
+		G1_rxCharIsK0           : out  std_logic;
+		
+		G2_txData               : in  std_logic_vector (7 downto 0);
+		G2_rxData               : out  std_logic_vector (7 downto 0);
+		G2_txP                  : out  std_logic;
+		G2_txN                  : out  std_logic;
+		G2_rxP                  : in  std_logic;
+		G2_rxN                  : in  std_logic;
+		G2_LOS                  : in std_logic;
+		G2_rxUsrClk             : out  std_logic;
+		G2_resetDone            : out  std_logic;
+		G2_rxLocked             : out  std_logic;
+		G2_rxNotInTable         : out  std_logic;
+		G2_txLocked             : out  std_logic;
+		G2_txCharIsK0           : in  std_logic;
+		G2_rxCharIsK0           : out  std_logic;		
+		
+		G3_txData               : in  std_logic_vector (7 downto 0);
+		G3_rxData               : out  std_logic_vector (7 downto 0);
+		G3_txP                  : out  std_logic;
+		G3_txN                  : out  std_logic;
+		G3_rxP                  : in  std_logic;
+		G3_rxN                  : in  std_logic;
+		G3_LOS                  : in std_logic;
+		G3_rxUsrClk             : out  std_logic;
+		G3_resetDone            : out  std_logic;
+		G3_rxLocked             : out  std_logic;
+		G3_rxNotInTable         : out  std_logic;
+		G3_txLocked             : out  std_logic;
+		G3_txCharIsK0           : in  std_logic;
+		G3_rxCharIsK0           : out  std_logic;
+		
+		--Control Interface
+		SCI_DATA_IN             : in  std_logic_vector(7 downto 0) := (others => '0');
+		SCI_DATA_OUT            : out std_logic_vector(7 downto 0) := (others => '0');
+		SCI_ADDR                : in  std_logic_vector(8 downto 0) := (others => '0');
+		SCI_READ                : in  std_logic := '0';
+		SCI_WRITE               : in  std_logic := '0';
+		SCI_ACK                 : out std_logic := '0';
+		SCI_NACK                : out std_logic := '0';
+
+		LEDs_link_ok            : out std_logic_vector(0 to 3);
+		LEDs_rx                 : out std_logic_vector(0 to 3); 
+		LEDs_tx                 : out std_logic_vector(0 to 3);
+
+		testword0               : out std_logic_vector (35 downto 0); 
+		testword0clock          : out std_logic
+	);
+end component;
+
+component txFifo_MUX is
+	port ( 
+		write_clock             : in std_logic;
+		read_clock              : in std_logic;
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(31 downto 0);
+		data_write              : in std_logic;
+		full                    : out std_logic;
+		TX_DLM                  : in  std_logic;
+		TX_DLM_WORD             : in  std_logic_vector(7 downto 0);
+		data_out                : out std_logic_vector(15 downto 0);
+		char_is_k               : out std_logic_vector(1 downto 0)
+	);
+end component;
+
+component rxFifo_MUX is
+	port ( 
+		write_clock             : in std_logic;
+		read_clock              : in std_logic;
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(15 downto 0);
+		char_is_k               : in std_logic_vector(1 downto 0);
+		RX_DLM                  : out std_logic;
+		RX_DLM_WORD             : out std_logic_vector(7 downto 0);
+		data_out                : out std_logic_vector(31 downto 0);
+		data_read               : in std_logic;
+		data_available          : out std_logic;
+		overflow                : out std_logic;
+		error                   : out std_logic		
+	);
+end component;
+
+component DC_fifo8to32_SODA is
+	port ( 
+		write_clock             : in std_logic;
+		read_clock              : in std_logic;
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(7 downto 0);
+		char_is_k               : in std_logic;
+		RX_DLM                  : out std_logic;
+		RX_DLM_WORD             : out std_logic_vector(7 downto 0);
+		data_out                : out std_logic_vector(31 downto 0);
+		data_read               : in std_logic;
+		data_available          : out std_logic;
+		overflow                : out std_logic;
+		error                   : out std_logic		
+	);
+end component;
+
+component DC_fifo32to8_SODA is
+	port ( 
+		write_clock             : in std_logic;
+		read_clock              : in std_logic;
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(31 downto 0);
+		data_write              : in std_logic;
+		full                    : out std_logic;
+		TX_DLM                  : in std_logic;
+		TX_DLM_WORD             : in std_logic_vector(7 downto 0);
+		data_out                : out std_logic_vector(7 downto 0);
+		char_is_k               : out std_logic
+	);
+end component;
+
+
+signal G0_txData_S               : std_logic_vector(7 downto 0) :=(others=>'0');
+signal G0_rxData_S               : std_logic_vector(7 downto 0) :=(others=>'0');
+signal G0_rxUsrClk_S             : std_logic := '0';
+signal G0_resetDone_S            : std_logic:='0';
+signal G0_rxLocked_S             : std_logic := '0';
+signal G0_txLocked_S             : std_logic := '0';
+signal G0_rxNotInTable_S         : std_logic := '0';
+signal G0_txCharIsK0_S           : std_logic;
+signal G0_rxCharIsK0_S           : std_logic;
+signal G0_error                  : std_logic := '0';
+signal G0_recLocked_S            : std_logic := '0';
+
+signal G1_txData_S               : std_logic_vector(7 downto 0) :=(others=>'0');
+signal G1_rxData_S               : std_logic_vector(7 downto 0) :=(others=>'0');
+signal G1_rxUsrClk_S             : std_logic := '0';
+signal G1_resetDone_S            : std_logic:='0';
+signal G1_rxLocked_S             : std_logic := '0';
+signal G1_txLocked_S             : std_logic := '0';
+signal G1_rxNotInTable_S         : std_logic := '0'; 
+signal G1_txCharIsK0_S           : std_logic;
+signal G1_rxCharIsK0_S           : std_logic;
+signal G1_error                  : std_logic := '0';
+signal G1_recLocked_S            : std_logic := '0';
+	
+signal G2_txData_S               : std_logic_vector(7 downto 0) :=(others=>'0');
+signal G2_rxData_S               : std_logic_vector(7 downto 0) :=(others=>'0');
+signal G2_rxUsrClk_S             : std_logic := '0';
+signal G2_resetDone_S            : std_logic:='0';
+signal G2_rxLocked_S             : std_logic := '0';
+signal G2_txLocked_S             : std_logic := '0';
+signal G2_rxNotInTable_S         : std_logic := '0'; 
+signal G2_txCharIsK0_S           : std_logic;
+signal G2_rxCharIsK0_S           : std_logic;
+signal G2_error                  : std_logic := '0';
+signal G2_recLocked_S            : std_logic := '0';
+	
+signal G3_txData_S               : std_logic_vector(7 downto 0) :=(others=>'0');
+signal G3_rxData_S               : std_logic_vector(7 downto 0) :=(others=>'0');
+signal G3_rxUsrClk_S             : std_logic := '0';
+signal G3_resetDone_S            : std_logic:='0';
+signal G3_rxLocked_S             : std_logic := '0';
+signal G3_txLocked_S             : std_logic := '0';
+signal G3_rxNotInTable_S         : std_logic := '0'; 
+signal G3_txCharIsK0_S           : std_logic;
+signal G3_rxCharIsK0_S           : std_logic;
+signal G3_error                  : std_logic := '0';
+signal G3_recLocked_S            : std_logic := '0';
+	
+signal reset_gtpClk_S            : std_logic := '0';
+
+begin
+	
+serdesQuadMUXwrapper1: serdesQuadMUXwrapper port map(
+		gtpClk => gtpClk,
+		sysClk => sysClk,
+		gtpReset => reset_fibers,
+		
+		txUsrClkDiv2 => txUsrClkDiv2,
+		refClkOut => refClkOut,
+		refClk_OK => refClk_OK,
+		txpll_clocks => txpll_clocks,
+		
+		G0_txData => G0_txData_S,
+		G0_rxData => G0_rxData_S,
+		G0_txP => G0_txP,
+		G0_txN => G0_txN,
+		G0_rxP => G0_rxP,
+		G0_rxN => G0_rxN,
+		G0_LOS => G0_LOS,
+		G0_rxUsrClk => G0_rxUsrClk_S,
+		G0_resetDone => G0_resetDone_S,
+		G0_rxLocked => G0_recLocked_S,
+		G0_rxNotInTable => G0_rxNotInTable_S,
+		G0_txLocked => G0_txLocked_S,
+		G0_txCharIsK0 => G0_txCharIsK0_S,
+		G0_rxCharIsK0 => G0_rxCharIsK0_S,
+
+		G1_txData => G1_txData_S,
+		G1_rxData => G1_rxData_S,
+		G1_txP => G1_txP,
+		G1_txN => G1_txN,
+		G1_rxP => G1_rxP,
+		G1_rxN => G1_rxN,
+		G1_LOS => G1_LOS,
+		G1_rxUsrClk => G1_rxUsrClk_S,
+		G1_resetDone => G1_resetDone_S,
+		G1_rxLocked => G1_recLocked_S,
+		G1_rxNotInTable => G1_rxNotInTable_S,
+		G1_txLocked => G1_txLocked_S,
+		G1_txCharIsK0 => G1_txCharIsK0_S,
+		G1_rxCharIsK0 => G1_rxCharIsK0_S,
+
+		G2_txData => G2_txData_S,
+		G2_rxData => G2_rxData_S,
+		G2_txP => G2_txP,
+		G2_txN => G2_txN,
+		G2_rxP => G2_rxP,
+		G2_rxN => G2_rxN,
+		G2_LOS => G2_LOS,
+		G2_rxUsrClk => G2_rxUsrClk_S,
+		G2_resetDone => G2_resetDone_S,
+		G2_rxLocked => G2_recLocked_S,
+		G2_rxNotInTable => G2_rxNotInTable_S,
+		G2_txLocked => G2_txLocked_S,
+		G2_txCharIsK0 => G2_txCharIsK0_S,
+		G2_rxCharIsK0 => G2_rxCharIsK0_S,
+
+		G3_txData => G3_txData_S,
+		G3_rxData => G3_rxData_S,
+		G3_txP => G3_txP,
+		G3_txN => G3_txN,
+		G3_rxP => G3_rxP,
+		G3_rxN => G3_rxN,
+		G3_LOS => G3_LOS,
+		G3_rxUsrClk => G3_rxUsrClk_S,
+		G3_resetDone => G3_resetDone_S,
+		G3_rxLocked => G3_recLocked_S,
+		G3_rxNotInTable => G3_rxNotInTable_S,
+		G3_txLocked => G3_txLocked_S,
+		G3_txCharIsK0 => G3_txCharIsK0_S,
+		G3_rxCharIsK0 => G3_rxCharIsK0_S,
+		
+		--Control Interface
+		SCI_DATA_IN => SCI_DATA_IN,
+		SCI_DATA_OUT => SCI_DATA_OUT,
+		SCI_ADDR => SCI_ADDR,
+		SCI_READ => SCI_READ,
+		SCI_WRITE => SCI_READ,
+		SCI_ACK => SCI_ACK,
+		SCI_NACK => SCI_NACK,
+		
+		LEDs_link_ok => LEDs_link_ok,
+		LEDs_rx => LEDs_rx,
+		LEDs_tx => LEDs_tx,
+
+		testword0 => open,
+		testword0clock => testword0clock
+		);
+
+
+					
+	G0_status(0) <= G0_resetDone_S; -- '1' => OK
+	G0_status(1) <= '1' when (G0_txLocked_S='1') and (G0_LOS='0') else '0'; -- '1' => OK
+	G0_status(2) <= G0_rxLocked_S; -- '1' => OK
+	G0_status(3) <= G0_rxNotInTable_S or G0_error; -- '1' => error
+	G0_status(7 downto 4) <= (others => '0'); -- not used
+
+	G1_status(0) <= G1_resetDone_S; -- '1' => OK
+	G1_status(1) <= '1' when (G1_txLocked_S='1') and (G1_LOS='0') else '0'; -- '1' => OK
+	G1_status(2) <= G1_rxLocked_S; -- '1' => OK
+	G1_status(3) <= G1_rxNotInTable_S or G1_error; -- '1' => error
+	G1_status(7 downto 4) <= (others => '0'); -- not used
+					
+	G2_status(0) <= G2_resetDone_S; -- '1' => OK
+	G2_status(1) <= '1' when (G2_txLocked_S='1') and (G2_LOS='0') else '0'; -- '1' => OK
+	G2_status(2) <= G2_rxLocked_S; -- '1' => OK
+	G2_status(3) <= G2_rxNotInTable_S or G2_error; -- '1' => error 
+	G2_status(7 downto 4) <= (others => '0'); -- not used
+
+	G3_status(0) <= G3_resetDone_S; -- '1' => OK
+	G3_status(1) <= '1' when (G3_txLocked_S='1') and (G3_LOS='0') else '0'; -- '1' => OK
+	G3_status(2) <= G3_rxLocked_S; -- '1' => OK
+	G3_status(3) <= G3_rxNotInTable_S or G3_error; -- '1' => error
+	G3_status(7 downto 4) <= (others => '0'); -- not used
+	
+	testPin(0) <= G0_txCharIsK0_S;
+	testPin(1) <= G0_rxCharIsK0_S;
+	testPin(2) <= '0';
+	testPin(3) <= '0';
+
+process (gtpClk)
+begin
+	if rising_edge(gtpClk) then
+		reset_gtpClk_S <= reset;
+	end if;
+end process;
+
+DC_fifo32to8_SODA0: DC_fifo32to8_SODA port map(
+		write_clock => txAsyncClk,
+		read_clock => gtpClk,
+		reset => reset_gtpClk_S,
+		data_in => G0_txAsyncData,
+		data_write => G0_txAsyncDataWrite,
+		full => G0_txAsyncFifoFull,
+		TX_DLM => G0_TX_DLM,
+		TX_DLM_WORD => G0_TX_DLM_WORD,
+		data_out => G0_txData_S,
+		char_is_k => G0_txCharIsK0_S);
+DC_fifo32to8_SODA1: DC_fifo32to8_SODA port map(
+		write_clock => txAsyncClk,
+		read_clock => gtpClk,
+		reset => reset_gtpClk_S,
+		data_in => G1_txAsyncData,
+		data_write => G1_txAsyncDataWrite,
+		full => G1_txAsyncFifoFull,
+		TX_DLM => G1_TX_DLM,
+		TX_DLM_WORD => G1_TX_DLM_WORD,
+		data_out => G1_txData_S,
+		char_is_k => G1_txCharIsK0_S);
+DC_fifo32to8_SODA2: DC_fifo32to8_SODA port map(
+		write_clock => txAsyncClk,
+		read_clock => gtpClk,
+		reset => reset_gtpClk_S,
+		data_in => G2_txAsyncData,
+		data_write => G2_txAsyncDataWrite,
+		full => G2_txAsyncFifoFull,
+		TX_DLM => G2_TX_DLM,
+		TX_DLM_WORD => G2_TX_DLM_WORD,
+		data_out => G2_txData_S,
+		char_is_k => G2_txCharIsK0_S);
+DC_fifo32to8_SODA3: DC_fifo32to8_SODA port map(
+		write_clock => txAsyncClk,
+		read_clock => gtpClk,
+		reset => reset_gtpClk_S,
+		data_in => G3_txAsyncData,
+		data_write => G3_txAsyncDataWrite,
+		full => G3_txAsyncFifoFull,
+		TX_DLM => G3_TX_DLM,
+		TX_DLM_WORD => G3_TX_DLM_WORD,
+		data_out => G3_txData_S,
+		char_is_k => G3_txCharIsK0_S);
+		
+DC_fifo8to32_SODA0: DC_fifo8to32_SODA port map(
+		write_clock => G0_rxUsrClk_S,
+		read_clock => rxAsyncClk,
+		reset => not G0_recLocked_S,
+		data_in => G0_rxData_S,
+		char_is_k => G0_rxCharIsK0_S,
+		RX_DLM => G0_RX_DLM,
+		RX_DLM_WORD => G0_RX_DLM_WORD,
+		data_out => G0_rxAsyncData,
+		data_read => G0_rxAsyncDataRead,
+		data_available => G0_rxAsyncDataPresent,
+		overflow => G0_rxAsyncDataOverflow,
+		error => G0_error);
+DC_fifo8to32_SODA1: DC_fifo8to32_SODA port map(
+		write_clock => G1_rxUsrClk_S,
+		read_clock => rxAsyncClk,
+		reset => not G1_recLocked_S,
+		data_in => G1_rxData_S,
+		char_is_k => G1_rxCharIsK0_S,
+		RX_DLM => G1_RX_DLM,
+		RX_DLM_WORD => G1_RX_DLM_WORD,
+		data_out => G1_rxAsyncData,
+		data_read => G1_rxAsyncDataRead,
+		data_available => G1_rxAsyncDataPresent,
+		overflow => G1_rxAsyncDataOverflow,
+		error => G1_error);
+DC_fifo8to32_SODA2: DC_fifo8to32_SODA port map(
+		write_clock => G2_rxUsrClk_S,
+		read_clock => rxAsyncClk,
+		reset => not G2_recLocked_S,
+		data_in => G2_rxData_S,
+		char_is_k => G2_rxCharIsK0_S,
+		RX_DLM => G2_RX_DLM,
+		RX_DLM_WORD => G2_RX_DLM_WORD,
+		data_out => G2_rxAsyncData,
+		data_read => G2_rxAsyncDataRead,
+		data_available => G2_rxAsyncDataPresent,
+		overflow => G2_rxAsyncDataOverflow,
+		error => G2_error);
+DC_fifo8to32_SODA3: DC_fifo8to32_SODA port map(
+		write_clock => G3_rxUsrClk_S,
+		read_clock => rxAsyncClk,
+		reset => not G3_recLocked_S,
+		data_in => G3_rxData_S,
+		char_is_k => G3_rxCharIsK0_S,
+		RX_DLM => G3_RX_DLM,
+		RX_DLM_WORD => G3_RX_DLM_WORD,
+		data_out => G3_rxAsyncData,
+		data_read => G3_rxAsyncDataRead,
+		data_available => G3_rxAsyncDataPresent,
+		overflow => G3_rxAsyncDataOverflow,
+		error => G3_error);
+
+G0_rxLocked_S <= '1' when (G0_recLocked_S='1') and (G0_LOS='0') else '0';
+G1_rxLocked_S <= '1' when (G1_recLocked_S='1') and (G1_LOS='0')  else '0';
+G2_rxLocked_S <= '1' when (G2_recLocked_S='1') and (G2_LOS='0') else '0';
+G3_rxLocked_S <= '1' when (G3_recLocked_S='1') and (G3_LOS='0')  else '0';
+
+-- testword0clock <= G0_rxUsrClk_S;
+testword0 <= (others => '0');
+
+end Behavioral;
+
+
+
diff --git a/data_concentrator/sources/serdesQuadMUXwrapper.vhd b/data_concentrator/sources/serdesQuadMUXwrapper.vhd
new file mode 100644
index 0000000..cff2ddc
--- /dev/null
+++ b/data_concentrator/sources/serdesQuadMUXwrapper.vhd
@@ -0,0 +1,370 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   18-07-2013
+-- Module Name:   serdesQuadMUXwrapper
+-- Description:   Module with a quad serdes with synchronized transmit frequency and 16 bits bus
+-- Modifications:
+--   29-08-2014   ADCCLOCKFREQUENCY added: SODA clock at 80MHz 
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+----------------------------------------------------------------------------------
+-- serdesQuadMUXwrapper
+-- Quad serdes tranceiver for PANDA Front End Electronics and Multiplexer with synchronised transmitted data.
+--
+--
+--
+--
+-- Library
+--     work.gtpBufLayer : for GTP/GTX constants
+--
+-- Generics:
+-- 
+-- Inputs:
+--     gtpClk : Reference clock for the serdes, synchronous with transmitted data
+--     sysClk : Local bus system clock for serdes control interface and LEDs
+--     gtpReset : reset serdes
+--     txUsrClk : clock for the synchronous data to be transmitted, SODA clock
+--     txUsrClkDiv2 : clock div 2 for the synchronous data to be transmitted 
+--   For channel0 in quad serdes :
+--     G0_txData : transmit data, clocked with gtpClk that is synchrouous with SODA
+--     G0_rxP,G0_rxN :  differential input to the serdes
+--     G0_LOS : no fiber signal detected
+--     G0_txCharIsK0 : data is K-character
+--   For channel1 in quad serdes :
+--     G1_txData : transmit data, clocked with gtpClk that is synchrouous with SODA
+--     G1_rxP,G0_rxN :  differential input to the serdes
+--     G1_LOS : no fiber signal detected
+--     G1_txCharIsK0 : data is K-character
+--   For channel2 in quad serdes :
+--     G2_txData : transmit data, clocked with gtpClk that is synchrouous with SODA
+--     G2_rxP,G0_rxN :  differential input to the serdes
+--     G2_LOS : no fiber signal detected
+--     G2_txCharIsK0 : data is K-character
+--   For channel3 in quad serdes :
+--     G3_txData : transmit data, clocked with gtpClk that is synchrouous with SODA
+--     G3_rxP,G0_rxN :  differential input to the serdes
+--     G3_LOS : no fiber signal detected
+--     G3_txCharIsK0 : data is K-character
+--     SCI_DATA_IN : serdes control interface : data
+--     SCI_ADDR : serdes control interface : address
+--     SCI_READ : serdes control interface : read
+--     SCI_WRITE : serdes control interface : write
+-- 
+-- Outputs:
+--     refClkOut : reference clock output
+--     refClk_OK : indicates if refClkOut is stable (PLL locked) (always 1 for Lattice serdes)
+--   For channel0 in quad serdes  :
+--     G0_rxData : Data received, clocked with G0_rxUsrClk
+--     G0_txP,G0_txN : differential transmit outputs of the serdes
+--     G0_rxUsrClk : recovered clock for received data
+--     G0_resetDone : Resetting is finished
+--     G0_rxLocked : Receiver is locked to incomming data
+--     G0_rxNotInTable : Error in received data
+--     G0_txLocked : Transmitter is locked to reference clock (synchronous with SODA)
+--     G0_rxCharIsK0 : received data is K-character
+--     G1_rxData : Data received, clocked with G1_rxUsrClk
+--     G1_txP,G0_txN : differential transmit outputs of the serdes
+--     G1_rxUsrClk : recovered clock for received data
+--     G1_resetDone : Resetting is finished
+--     G1_rxLocked : Receiver is locked to incomming data
+--     G1_rxNotInTable : Error in received data
+--     G1_txLocked : Transmitter is locked to reference clock (synchronous with SODA)
+--     G1_rxCharIsK0 : received data is K-character
+--     G2_rxData : Data received, clocked with G2_rxUsrClk
+--     G2_txP,G0_txN : differential transmit outputs of the serdes
+--     G2_rxUsrClk : recovered clock for received data
+--     G2_resetDone : Resetting is finished
+--     G2_rxLocked : Receiver is locked to incomming data
+--     G2_rxNotInTable : Error in received data
+--     G2_txLocked : Transmitter is locked to reference clock (synchronous with SODA)
+--     G2_rxCharIsK0 : received data is K-character
+--     G3_rxData : Data received, clocked with G3_rxUsrClk
+--     G3_txP,G0_txN : differential transmit outputs of the serdes
+--     G3_rxUsrClk : recovered clock for received data
+--     G3_resetDone : Resetting is finished
+--     G3_rxLocked : Receiver is locked to incomming data
+--     G3_rxNotInTable : Error in received data
+--     G3_txLocked : Transmitter is locked to reference clock (synchronous with SODA)
+--     G3_rxCharIsK0 : received data is K-character
+--     SCI_DATA_OUT : serdes control interface : data
+--     SCI_ACK : serdes control interface : acknowledge
+--     SCI_NACK : serdes control interface : not acknowledge
+--     LEDs_link_ok : serdes status for LED on extension board : link ok
+--     LEDs_rx : serdes status for LED on extension board : receive
+--     LEDs_tx : serdes status for LED on extension board : transmit
+-- 
+-- 
+-- Components:
+--     med_ecp3_quad_sfp_sync : module with the quad serdes interface
+--
+----------------------------------------------------------------------------------
+
+entity serdesQuadMUXwrapper is 
+	port ( 	
+		gtpClk                  : in  std_logic;
+		sysClk                  : in  std_logic;
+		gtpReset                : in  std_logic;
+		
+		txUsrClkDiv2            : in std_logic;
+		refClkOut               : out std_logic;
+		refClk_OK               : out std_logic;
+		txpll_clocks            : out std_logic_vector(3 downto 0);
+		
+		G0_txData               : in  std_logic_vector (7 downto 0);
+		G0_rxData               : out  std_logic_vector (7 downto 0);
+		G0_txP                  : out  std_logic;
+		G0_txN                  : out  std_logic;
+		G0_rxP                  : in  std_logic;
+		G0_rxN                  : in  std_logic;
+		G0_LOS                  : in std_logic;
+		G0_rxUsrClk             : out  std_logic; -- 200MHz
+		G0_resetDone            : out  std_logic;
+		G0_rxLocked             : out  std_logic;
+		G0_rxNotInTable         : out  std_logic;
+		G0_txLocked             : out  std_logic;
+		G0_txCharIsK0           : in  std_logic;
+		G0_rxCharIsK0           : out  std_logic;
+
+		G1_txData               : in  std_logic_vector (7 downto 0);
+		G1_rxData               : out  std_logic_vector (7 downto 0);
+		G1_txP                  : out  std_logic;
+		G1_txN                  : out  std_logic;
+		G1_rxP                  : in  std_logic;
+		G1_rxN                  : in  std_logic;
+		G1_LOS                  : in std_logic;
+		G1_rxUsrClk             : out  std_logic; -- 200MHz
+		G1_resetDone            : out  std_logic;
+		G1_rxLocked             : out  std_logic;
+		G1_rxNotInTable         : out  std_logic;
+		G1_txLocked             : out  std_logic;
+		G1_txCharIsK0           : in  std_logic;
+		G1_rxCharIsK0           : out  std_logic;
+		
+		G2_txData               : in  std_logic_vector (7 downto 0);
+		G2_rxData               : out  std_logic_vector (7 downto 0);
+		G2_txP                  : out  std_logic;
+		G2_txN                  : out  std_logic;
+		G2_rxP                  : in  std_logic;
+		G2_rxN                  : in  std_logic;
+		G2_LOS                  : in std_logic;
+		G2_rxUsrClk             : out  std_logic; -- 200MHz
+		G2_resetDone            : out  std_logic;
+		G2_rxLocked             : out  std_logic;
+		G2_rxNotInTable         : out  std_logic;
+		G2_txLocked             : out  std_logic;
+		G2_txCharIsK0           : in  std_logic;
+		G2_rxCharIsK0           : out  std_logic;		
+		
+		G3_txData               : in  std_logic_vector (7 downto 0);
+		G3_rxData               : out  std_logic_vector (7 downto 0);
+		G3_txP                  : out  std_logic;
+		G3_txN                  : out  std_logic;
+		G3_rxP                  : in  std_logic;
+		G3_rxN                  : in  std_logic;
+		G3_LOS                  : in std_logic;
+		G3_rxUsrClk             : out  std_logic; -- 200MHz
+		G3_resetDone            : out  std_logic;
+		G3_rxLocked             : out  std_logic;
+		G3_rxNotInTable         : out  std_logic;
+		G3_txLocked             : out  std_logic;
+		G3_txCharIsK0           : in  std_logic;
+		G3_rxCharIsK0           : out  std_logic;
+		
+		--Control Interface
+		SCI_DATA_IN             : in  std_logic_vector(7 downto 0) := (others => '0');
+		SCI_DATA_OUT            : out std_logic_vector(7 downto 0) := (others => '0');
+		SCI_ADDR                : in  std_logic_vector(8 downto 0) := (others => '0');
+		SCI_READ                : in  std_logic := '0';
+		SCI_WRITE               : in  std_logic := '0';
+		SCI_ACK                 : out std_logic := '0';
+		SCI_NACK                : out std_logic := '0';
+
+		LEDs_link_ok            : out std_logic_vector(0 to 3);
+		LEDs_rx                 : out std_logic_vector(0 to 3); 
+		LEDs_tx                 : out std_logic_vector(0 to 3);
+
+		testword0               : out std_logic_vector (35 downto 0); 
+		testword0clock          : out std_logic
+		);
+end serdesQuadMUXwrapper;
+
+architecture Behavioral of serdesQuadMUXwrapper is
+
+component med_ecp3_quad_sfp_sync is
+  port(
+    CLOCK              : in  std_logic; -- serdes reference clock
+    CLOCKx2            : in  std_logic; -- serdes reference clock *2
+    SYSCLK             : in  std_logic; -- 100 MHz main clock net
+    RESET              : in  std_logic; -- synchronous reset
+    CLEAR              : in  std_logic; -- asynchronous reset
+
+    CLK_RX_HALF_OUT    : out std_logic_vector(0 to 3) := "0000";  --received clock/2
+    CLK_RX_FULL_OUT    : out std_logic_vector(0 to 3) := "0000";  --received clock
+	
+    TX_DATA0           : in std_logic_vector(7 downto 0); -- clock on CLOCK
+    TX_DATA1           : in std_logic_vector(7 downto 0);      
+    TX_DATA2           : in std_logic_vector(7 downto 0);      
+    TX_DATA3           : in std_logic_vector(7 downto 0);	
+    TX_CHAR_K0         : in std_logic;
+    TX_CHAR_K1         : in std_logic;
+    TX_CHAR_K2         : in std_logic;
+    TX_CHAR_K3         : in std_logic;
+    RX_DATA0           : out std_logic_vector(7 downto 0); -- clock on CLOCK
+    RX_DATA1           : out std_logic_vector(7 downto 0);      
+    RX_DATA2           : out std_logic_vector(7 downto 0);      
+    RX_DATA3           : out std_logic_vector(7 downto 0);	
+    RX_CHAR_K0         : out std_logic;
+    RX_CHAR_K1         : out std_logic;
+    RX_CHAR_K2         : out std_logic;
+    RX_CHAR_K3         : out std_logic;
+    RX_ERROR0          : out std_logic;
+    RX_ERROR1          : out std_logic;
+    RX_ERROR2          : out std_logic;
+    RX_ERROR3          : out std_logic;
+
+    --SFP Connection
+    SD_RXD_P_IN        : in std_logic_vector(0 to 3);
+    SD_RXD_N_IN        : in std_logic_vector(0 to 3);
+    SD_TXD_P_OUT       : out std_logic_vector(0 to 3);
+    SD_TXD_N_OUT       : out std_logic_vector(0 to 3);
+    SD_LOS_IN          : in std_logic_vector(0 to 3);  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+    SD_TXDIS_OUT       : out std_logic_vector(0 to 3); -- SFP disable
+	
+    --Control Interface
+    SCI_DATA_IN        : in  std_logic_vector(7 downto 0) := (others => '0');
+    SCI_DATA_OUT       : out std_logic_vector(7 downto 0) := (others => '0');
+    SCI_ADDR           : in  std_logic_vector(8 downto 0) := (others => '0');
+    SCI_READ           : in  std_logic := '0';
+    SCI_WRITE          : in  std_logic := '0';
+    SCI_ACK            : out std_logic := '0';
+    SCI_NACK           : out std_logic := '0';
+	
+    -- Status and control port
+	RESET_DONE         : out std_logic_vector (0 to 3);
+	RX_ALLOW           : out std_logic_vector (0 to 3);
+	TX_ALLOW           : out std_logic_vector (0 to 3);
+	txpll_clocks       : out std_logic_vector(3 downto 0);
+	LEDs_link_ok       : out std_logic_vector(0 to 3);
+	LEDs_rx            : out std_logic_vector(0 to 3); 
+	LEDs_tx            : out std_logic_vector(0 to 3);
+    STAT_OP            : out std_logic_vector (15 downto 0);
+    CTRL_OP            : in  std_logic_vector (15 downto 0) := (others => '0')
+   );
+end component;
+
+signal tx_allow_i      : std_logic_vector (0 to 3);
+signal rx_allow_i      : std_logic_vector (0 to 3);
+
+signal rxUsrClk_i      : std_logic_vector (0 to 3);
+signal rxUsrClk2_i     : std_logic_vector (0 to 3);
+
+	
+begin
+
+G0_rxUsrClk <= rxUsrClk_i(0); 
+G1_rxUsrClk <= rxUsrClk_i(1);
+G2_rxUsrClk <= rxUsrClk_i(2);
+G3_rxUsrClk <= rxUsrClk_i(3);
+refClkOut <= gtpClk;
+refClk_OK <= '1';
+
+med_ecp3_quad_sfp_sync1: med_ecp3_quad_sfp_sync port map(
+    CLOCK => txUsrClkDiv2,
+    CLOCKx2 => gtpClk,
+    SYSCLK => sysClk,
+    RESET => gtpReset,
+    CLEAR => gtpReset,
+    CLK_RX_HALF_OUT => rxUsrClk2_i,
+    CLK_RX_FULL_OUT => rxUsrClk_i,
+		
+    TX_DATA0 => G0_txData,
+    TX_DATA1 => G1_txData,
+    TX_DATA2 => G2_txData,  
+    TX_DATA3 => G3_txData,  
+    TX_CHAR_K0 => G0_txCharIsK0,
+    TX_CHAR_K1 => G1_txCharIsK0,
+    TX_CHAR_K2 => G2_txCharIsK0,
+    TX_CHAR_K3 => G3_txCharIsK0,
+    RX_DATA0 => G0_rxData,
+    RX_DATA1 => G1_rxData,   
+    RX_DATA2 => G2_rxData,    
+    RX_DATA3 => G3_rxData,
+    RX_CHAR_K0 => G0_rxCharIsK0,
+    RX_CHAR_K1 => G1_rxCharIsK0,
+    RX_CHAR_K2 => G2_rxCharIsK0,
+    RX_CHAR_K3 => G3_rxCharIsK0,
+    RX_ERROR0 => G0_rxNotInTable,
+    RX_ERROR1 => G1_rxNotInTable,
+    RX_ERROR2 => G2_rxNotInTable,
+    RX_ERROR3 => G3_rxNotInTable,
+
+    --SFP Connection
+    SD_RXD_P_IN(0) => G0_rxP,
+    SD_RXD_P_IN(1) => G1_rxP,
+    SD_RXD_P_IN(2) => G2_rxP,
+    SD_RXD_P_IN(3) => G3_rxP,
+    SD_RXD_N_IN(0) => G0_rxN,
+    SD_RXD_N_IN(1) => G1_rxN,
+    SD_RXD_N_IN(2) => G2_rxN,
+    SD_RXD_N_IN(3) => G3_rxN,
+	
+    SD_TXD_P_OUT(0) => G0_txP,
+    SD_TXD_P_OUT(1) => G1_txP,
+    SD_TXD_P_OUT(2) => G2_txP,
+    SD_TXD_P_OUT(3) => G3_txP,
+    SD_TXD_N_OUT(0) => G0_txN,
+    SD_TXD_N_OUT(1) => G1_txN,
+    SD_TXD_N_OUT(2) => G2_txN,
+    SD_TXD_N_OUT(3) => G3_txN,
+	
+    SD_LOS_IN(0) => G0_LOS,
+    SD_LOS_IN(1) => G1_LOS,
+    SD_LOS_IN(2) => G2_LOS,
+    SD_LOS_IN(3) => G3_LOS,
+	SD_TXDIS_OUT => open,
+	
+	--Control Interface
+	SCI_DATA_IN => SCI_DATA_IN,
+	SCI_DATA_OUT => SCI_DATA_OUT,
+	SCI_ADDR => SCI_ADDR,
+	SCI_READ => SCI_READ,
+	SCI_WRITE => SCI_WRITE,
+	SCI_ACK => SCI_ACK,
+	SCI_NACK => SCI_NACK,
+	
+    -- Status and control port
+	RESET_DONE(0) => G0_resetDone,
+	RESET_DONE(1) => G1_resetDone,
+	RESET_DONE(2) => G2_resetDone,
+	RESET_DONE(3) => G3_resetDone,
+	RX_ALLOW => rx_allow_i,
+	TX_ALLOW => tx_allow_i,
+	txpll_clocks => txpll_clocks,
+	LEDs_link_ok => LEDs_link_ok,
+	LEDs_rx => LEDs_rx,
+	LEDs_tx => LEDs_tx,
+    STAT_OP => open,
+    CTRL_OP => x"0000"
+   );
+
+
+G0_rxLocked <= '1' when rx_allow_i(0)='1' else '0';
+G1_rxLocked <= '1' when rx_allow_i(1)='1' else '0';
+G2_rxLocked <= '1' when rx_allow_i(2)='1' else '0';
+G3_rxLocked <= '1' when rx_allow_i(3)='1' else '0';
+G0_txLocked <= '1' when tx_allow_i(0)='1' else '0';
+G1_txLocked <= '1' when tx_allow_i(1)='1' else '0';
+G2_txLocked <= '1' when tx_allow_i(2)='1' else '0';
+G3_txLocked <= '1' when tx_allow_i(3)='1' else '0';
+
+testword0clock <= rxUsrClk_i(0);
+testword0 <= (others => '0');
+		
+end Behavioral;
+
+
+
diff --git a/data_concentrator/sources/shift_register.vhd b/data_concentrator/sources/shift_register.vhd
new file mode 100644
index 0000000..8b99229
--- /dev/null
+++ b/data_concentrator/sources/shift_register.vhd
@@ -0,0 +1,88 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   22-02-2009
+-- Module Name:   shift_register 
+-- Description:   Shifts data for an adjustable number of clock cycles
+----------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+------------------------------------------------------------------------------------------------------
+-- shift_register
+--		Shifts data for an adjustable number of clock cycles
+--
+-- generics
+--		width : number of bits for the data to shift
+--		depthbits : number of bits for the number of clock cycles to shift
+--		
+-- inputs
+--		clock : ADC sampling clock 
+--		reset : synchrounous reset
+--		hold : hold all values
+--		data_in : data to shift
+--		depth : number of clock cycles to shift for
+--
+-- outputs
+--		data_out : shifted data
+--
+------------------------------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity shift_register is
+	generic (
+		width                   : natural := 16;
+		depthbits               : natural := 9
+		);
+    port (
+		clock                   : in  std_logic; 
+		reset                   : in  std_logic; 
+		hold                    : in  std_logic; 
+		data_in                 : in std_logic_vector((width-1) downto 0); 
+		depth                   : in std_logic_vector((depthbits-1) downto 0);
+		data_out                : out  std_logic_vector((width-1) downto 0));
+end shift_register;
+
+architecture behavior of shift_register is
+
+type arrtype is array((2**depthbits-1) downto 0) of std_logic_vector((width-1) downto 0);
+signal mem : arrtype; -- := (others => (others => '0'));
+signal outptr : std_logic_vector((depthbits-1) downto 0) := (others => '0');
+signal mem_out : std_logic_vector((width-1) downto 0) := (others => '0');
+signal lastreset : std_logic := '0';
+
+attribute syn_ramstyle : string; 
+attribute syn_ramstyle of mem : signal is "block_ram"; 
+
+begin
+
+data_out <= mem_out;
+process (clock)
+begin
+	if rising_edge(clock) then
+		if hold='0' then
+			mem(conv_integer(unsigned(outptr + depth))) <= data_in;
+			if reset = '1' then
+				mem_out <= (others => '0');
+				if lastreset='0' then 
+					outptr <= (others => '0');
+				else
+					outptr <= outptr+1;
+				end if;
+			else
+				mem_out <= mem(conv_integer(unsigned(outptr)));
+				outptr <= outptr+1;
+			end if;		
+			lastreset <= reset;
+		end if;
+	end if;
+end process;
+
+end behavior;
diff --git a/data_concentrator/sources/synchronizer_to_other_clock.vhd b/data_concentrator/sources/synchronizer_to_other_clock.vhd
new file mode 100644
index 0000000..472c9a1
--- /dev/null
+++ b/data_concentrator/sources/synchronizer_to_other_clock.vhd
@@ -0,0 +1,91 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   11-08-2009
+-- Module Name:   synchronize_to_other_clock
+-- Description:   Synchronize parallel data to another clock
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+----------------------------------------------------------------------------------
+-- Random_energy
+-- Synchronise parallel data to a other clock.
+-- Not all data is guaranteed to be passed through, but the output data is always valid.
+-- 
+-- Library
+-- 
+-- Generics:
+--     DATA_WIDTH : width of data input/output data
+--
+-- Inputs:
+--     data_in_clock : slower input clock 
+--     data_in_clock : slower input clock 
+--     data_out_clock : faster clock for output data
+-- 
+-- Outputs:
+--     data_out : synchronised output data
+-- 
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity synchronize_to_other_clock is
+    generic (
+        DATA_WIDTH : natural := 8
+    );
+    port (
+		data_in_clock : in std_logic;
+		data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
+		data_out_clock : in std_logic;
+		data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
+    );
+end entity;
+
+architecture behavioral of synchronize_to_other_clock is
+signal register1 : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
+signal busy : std_logic := '0';
+signal busy_clkin : std_logic := '0';
+signal busy_clkout : std_logic := '0';
+signal available : std_logic := '0';
+signal available_clkin : std_logic := '0';
+signal available_clkout : std_logic := '0';
+
+begin
+
+process (data_in_clock)
+begin
+	if rising_edge(data_in_clock) then
+		if (busy_clkin='0') and (available_clkin='0') then
+			available_clkin <= '1';
+			register1 <= data_in;
+		elsif busy_clkin='1' then
+			available_clkin <= '0';
+		end if;
+		busy_clkin <= busy;
+		available <= available_clkin;
+	end if;
+end process;
+
+process (data_out_clock)
+begin
+	if rising_edge(data_out_clock) then
+		if (available_clkout='1') and (busy_clkout='0') then
+			busy_clkout <= '1';
+			data_out <= register1;
+		elsif available_clkout='0' then
+			busy_clkout <= '0';
+		end if;
+		available_clkout <= available;
+		busy <= busy_clkout;
+	end if;
+end process;
+
+
+
+end architecture behavioral;
+
+
diff --git a/data_concentrator/sources/txFifo_MUX.vhd b/data_concentrator/sources/txFifo_MUX.vhd
new file mode 100644
index 0000000..1fbb625
--- /dev/null
+++ b/data_concentrator/sources/txFifo_MUX.vhd
@@ -0,0 +1,144 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   23-08-2013
+-- Module Name:   txFifo_MUX
+-- Description:   FIFO with 32 bits to 16 bits conversion and SODA signals insertion
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use work.gtpBufLayer.All;
+
+----------------------------------------------------------------------------------
+-- txFifo_MUX
+-- FIFO with 32 bits to 16 bits conversion and insertion of SODA signals
+-- Data is written in asynchronous 32-bits fifo
+-- After reading the data is splitted in 2 16-bits words.
+-- If no data is available a Idle 16-bits word is put on the output (3CBC and the K-character signal).
+-- The data stream to the output is put to hold if a SODA signals arrives. Then this SODA signal is 
+-- forwarded with a fixed delay, and the high Byte position with the SODA K-character (K28.6=x"dc") in Low byte.
+--
+-- Library
+--     work.gtpBufLayer : for GTP/GTX/serdes constants
+--
+-- Generics:
+-- 
+-- Inputs:
+--     write_clock : clock for the 32-bits input data
+--     read_clock : clock for the 16-bits output data
+--     reset : reset
+--     data_in : 32-bits input data
+--     data_write : write signal for 32-bits input data
+--     TX_DLM : insert SODA signal in data stream
+--     TX_DLM_WORD : SODA signal to be inserted
+-- 
+-- Outputs:
+--     full : fifo is full : wait 
+--     data_out : 16-bits output data
+--     char_is_k : 16-bits output data is K-character
+-- 
+-- Components:
+--     async_fifo_512x32 : 32-bits asynchronous fifo
+--
+----------------------------------------------------------------------------------
+
+
+entity txFifo_MUX is
+	port ( 
+		write_clock             : in std_logic;
+		read_clock              : in std_logic;
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(31 downto 0);
+		data_write              : in std_logic;
+		full                    : out std_logic;
+		TX_DLM                  : in std_logic;
+		TX_DLM_WORD             : in std_logic_vector(7 downto 0);
+		data_out                : out std_logic_vector(15 downto 0);
+		char_is_k               : out std_logic_vector(1 downto 0)
+	);
+end txFifo_MUX;
+
+architecture Behavioral of txFifo_MUX is
+
+component async_fifo_512x32
+	port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(31 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(31 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic);
+end component;
+
+signal fifo_read_S              : std_logic;
+signal fifo_dataout_S           : std_logic_vector(31 downto 0);
+signal fifo_databuf_S           : std_logic_vector(31 downto 0);
+signal fifo_empty_S             : std_logic;
+signal fifo_buffilled_S         : integer range 0 to 2 := 0;
+signal fifo_read_after1clk_S    : std_logic := '0';
+	
+begin
+
+fifo: async_fifo_512x32 port map(
+		rst => reset,
+		wr_clk => write_clock,
+		rd_clk => read_clock,
+		din(15 downto 0) => data_in(31 downto 16),
+		din(31 downto 16) => data_in(15 downto 0),
+		wr_en => data_write, 
+		rd_en => fifo_read_S,
+		dout => fifo_dataout_S,
+		full => full,
+		empty => fifo_empty_S);
+
+fifo_read_S <= '1' when (fifo_empty_S='0') and (TX_DLM='0') 
+		and (fifo_buffilled_S/=1) and (fifo_read_after1clk_S='0') 
+	else '0';
+data_out <= 
+	TX_DLM_WORD & KCHARSODA when (TX_DLM='1')
+	else fifo_databuf_S(31 downto 16) when (fifo_buffilled_S=1)
+	else fifo_databuf_S(15 downto 0) when (fifo_buffilled_S=2)
+	else fifo_dataout_S(31 downto 16) when (fifo_read_after1clk_S='1')
+	else KCHARIDLE;
+char_is_k <=
+	"01" when (TX_DLM='1')
+	else "00" when (fifo_buffilled_S=1)
+	else "00" when (fifo_buffilled_S=2)
+	else "00" when (fifo_read_after1clk_S='1')
+	else "11";
+
+tx_process : process (read_clock)
+begin
+	if rising_edge(read_clock) then
+		if reset='1' then
+			fifo_read_after1clk_S <= '0';
+			fifo_buffilled_S <= 0;
+		else
+			fifo_read_after1clk_S <= fifo_read_S;
+			if (fifo_read_after1clk_S='1') then
+				fifo_databuf_S <= fifo_dataout_S;
+			end if;
+			if (TX_DLM='1') then
+				if (fifo_read_after1clk_S='1') then
+					fifo_buffilled_S <= 1;
+				end if;
+			else
+				if (fifo_read_after1clk_S='1') then
+					fifo_buffilled_S <= 2;
+				elsif (fifo_buffilled_S=1) then
+					fifo_buffilled_S <= 2;
+				elsif (fifo_buffilled_S=2) then
+					fifo_buffilled_S <= 0;
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+end Behavioral;
+
diff --git a/data_concentrator/test_module.vhd b/data_concentrator/test_module.vhd
new file mode 100644
index 0000000..b52c213
--- /dev/null
+++ b/data_concentrator/test_module.vhd
@@ -0,0 +1,174 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+  entity test_module is
+    port (
+      CLK_IN            : in  std_logic;
+      RESET_IN          : in  std_logic;
+      -- Slave bus
+      BUS_READ_IN       : in   std_logic;
+      BUS_WRITE_IN      : in   std_logic;
+      BUS_BUSY_OUT      : out  std_logic;
+      BUS_ACK_OUT       : out  std_logic;
+      BUS_ADDR_IN       : in   std_logic_vector(1 downto 0);
+      BUS_DATA_IN       : in   std_logic_vector(31 downto 0);
+      BUS_DATA_OUT      : out  std_logic_vector(31 downto 0);
+      LEDS_ACT_OUT      : out  std_logic;
+      LEDS_OUT          : out  std_logic_vector(3 downto 0);
+      SPARE_LINE        : in  std_logic_vector(5 downto 0);
+      TEST_LINE         : out  std_logic_vector(15 downto 0);
+      -- Status lines
+      STAT              : out  std_logic_vector(31 downto 0) -- DEBUG
+	  );
+end entity;
+
+architecture Behavioral of test_module is
+-- Signals
+  type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);
+  signal CURRENT_STATE, NEXT_STATE: STATES;
+
+  -- slave bus signals
+  signal bus_ack_x        : std_logic;
+  signal bus_ack          : std_logic;
+  signal store_wr_x       : std_logic;
+  signal store_wr         : std_logic;
+  signal store_rd_x       : std_logic;
+  signal store_rd         : std_logic;
+  signal buf_bus_data_out : std_logic_vector(31 downto 0);
+
+  signal LEDregister_i    : std_logic_vector(31 downto 0);
+  signal TEST_LINE_i      : std_logic_vector(31 downto 0);
+			  
+begin
+
+---------------------------------------------------------
+-- Debugging                                           --
+---------------------------------------------------------
+stat(31 downto 0)  <= (others => '0');
+
+---------------------------------------------------------
+-- Statemachine                                        --
+---------------------------------------------------------
+  STATE_MEM: process( clk_in)
+    begin
+      if( rising_edge(clk_in) ) then
+        if( RESET_IN = '1' ) then
+          CURRENT_STATE <= SLEEP;
+          bus_ack       <= '0';
+          store_wr      <= '0';
+          store_rd      <= '0';
+        else
+          CURRENT_STATE <= NEXT_STATE;
+          bus_ack       <= bus_ack_x;
+          store_wr      <= store_wr_x;
+          store_rd      <= store_rd_x;
+        end if;
+      end if;
+    end process STATE_MEM;
+
+-- Transition matrix
+  TRANSFORM: process(CURRENT_STATE, BUS_read_in, BUS_write_in )
+    begin
+      NEXT_STATE <= SLEEP;
+      bus_ack_x  <= '0';
+      store_wr_x <= '0';
+      store_rd_x <= '0';
+      case CURRENT_STATE is
+        when SLEEP    =>
+          if   ( (BUS_read_in = '1') ) then
+            NEXT_STATE <= RD_RDY;
+            store_rd_x <= '1';
+          elsif( (BUS_write_in = '1') ) then
+            NEXT_STATE <= WR_RDY;
+            store_wr_x <= '1';
+          else
+            NEXT_STATE <= SLEEP;
+          end if;
+
+        when RD_RDY    =>
+          NEXT_STATE <= RD_ACK;
+
+        when WR_RDY    =>
+          NEXT_STATE <= WR_ACK;
+
+        when RD_ACK    =>
+          if( BUS_read_in = '0' ) then
+            NEXT_STATE <= DONE;
+            bus_ack_x  <= '1';
+          else
+            NEXT_STATE <= RD_ACK;
+            bus_ack_x  <= '1';
+          end if;
+
+        when WR_ACK    =>
+          if( BUS_write_in = '0' ) then
+            NEXT_STATE <= DONE;
+            bus_ack_x  <= '1';
+          else
+            NEXT_STATE <= WR_ACK;
+            bus_ack_x  <= '1';
+          end if;
+
+        when DONE    =>
+          NEXT_STATE <= SLEEP;
+
+        when others    =>
+          NEXT_STATE <= SLEEP;
+  end case;
+end process TRANSFORM;
+
+
+---------------------------------------------------------
+-- data handling                                       --
+---------------------------------------------------------
+
+-- register write
+THE_WRITE_REG_PROC: process( clk_in )
+  begin
+      if( rising_edge(clk_in) ) then
+          if   ( RESET_IN = '1' ) then
+              LEDregister_i <= (others => '0');
+              TEST_LINE_i <= (others => '0');
+           elsif( (store_wr = '1') and (bus_addr_in = "00") ) then
+              LEDregister_i <= bus_data_in;
+           elsif( (store_wr = '1') and (bus_addr_in = "01") ) then
+              TEST_LINE_i <= bus_data_in;
+          else
+          end if;
+      end if;
+  end process THE_WRITE_REG_PROC;
+  
+LEDS_OUT <= LEDregister_i(3 downto 0);
+LEDS_ACT_OUT <= LEDregister_i(4);
+TEST_LINE <= TEST_LINE_i(15 downto 0);  
+
+-- register read
+THE_READ_REG_PROC: process( clk_in )
+  begin
+      if( rising_edge(clk_in) ) then
+          if   ( RESET_IN = '1' ) then
+              buf_bus_data_out <= (others => '0');
+          elsif( (store_rd = '1') and (bus_addr_in = "00") ) then
+              buf_bus_data_out <= LEDregister_i;
+          elsif( (store_rd = '1') and (bus_addr_in = "01") ) then
+              buf_bus_data_out <= TEST_LINE_i;
+          elsif( (store_rd = '1') and (bus_addr_in = "10") ) then
+              buf_bus_data_out(5 downto 0) <= SPARE_LINE;
+              buf_bus_data_out(31 downto 6) <= (others => '0');
+          end if;
+      end if;
+  end process THE_READ_REG_PROC;
+ 
+
+-- output signals
+BUS_DATA_OUT <= buf_bus_data_out;
+BUS_ACK_OUT  <= bus_ack;
+BUS_BUSY_OUT <= '0';
+
+end Behavioral;
diff --git a/data_concentrator/trb3_periph_data_concentrator.lpf b/data_concentrator/trb3_periph_data_concentrator.lpf
new file mode 100644
index 0000000..58fe4e4
--- /dev/null
+++ b/data_concentrator/trb3_periph_data_concentrator.lpf
@@ -0,0 +1,294 @@
+rvl_alias "SODA_clock" "SODA_clock";
+#RVL_ALIAS "clk_62M5_i" "clk_62M5_i"; 
+#RVL_ALIAS "clk_62M5_i" "clk_62M5_i"; 
+RVL_ALIAS "clk_100_i" "clk_100_i"; 
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+#################################################################
+# Basic Settings
+#################################################################
+SYSCONFIG MCCLK_FREQ=2.5 ;
+FREQUENCY PORT "CLK_PCLK_RIGHT" 200.000000 MHz ;
+FREQUENCY PORT "CLK_PCLK_LEFT" 200.000000 MHz ;
+FREQUENCY PORT "CLK_GPLL_RIGHT" 200.000000 MHz ;
+FREQUENCY PORT "CLK_GPLL_LEFT" 125.000000 MHz ;
+#################################################################
+# Clock I/O
+#################################################################
+LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
+LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
+LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18" ;
+LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10" ;
+LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;
+LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;
+DEFINE PORT GROUP "CLK_group" "CLK*" ;
+IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
+#################################################################
+# Trigger I/O
+#################################################################
+#Trigger from fan-out
+LOCATE COMP "TRIGGER_LEFT" SITE "V3" ;
+LOCATE COMP "TRIGGER_RIGHT" SITE "N24" ;
+IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ;
+#################################################################
+# To central FPGA
+#################################################################
+LOCATE COMP "FPGA5_COMM[0]" SITE "AD4" ;
+LOCATE COMP "FPGA5_COMM[1]" SITE "AE3" ;
+LOCATE COMP "FPGA5_COMM[2]" SITE "AA7" ;
+LOCATE COMP "FPGA5_COMM[3]" SITE "AB7" ;
+LOCATE COMP "FPGA5_COMM[4]" SITE "AD3" ;
+LOCATE COMP "FPGA5_COMM[5]" SITE "AC4" ;
+LOCATE COMP "FPGA5_COMM[6]" SITE "AE2" ;
+LOCATE COMP "FPGA5_COMM[7]" SITE "AF3" ;
+LOCATE COMP "FPGA5_COMM[8]" SITE "AE4" ;
+LOCATE COMP "FPGA5_COMM[9]" SITE "AF4" ;
+LOCATE COMP "FPGA5_COMM[10]" SITE "V10" ;
+LOCATE COMP "FPGA5_COMM[11]" SITE "W10" ;
+DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
+IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+LOCATE COMP "TEST_LINE[0]" SITE "A5" ;
+LOCATE COMP "TEST_LINE[1]" SITE "A6" ;
+LOCATE COMP "TEST_LINE[2]" SITE "G8" ;
+LOCATE COMP "TEST_LINE[3]" SITE "F9" ;
+LOCATE COMP "TEST_LINE[4]" SITE "D9" ;
+LOCATE COMP "TEST_LINE[5]" SITE "D10" ;
+LOCATE COMP "TEST_LINE[6]" SITE "F10" ;
+LOCATE COMP "TEST_LINE[7]" SITE "E10" ;
+LOCATE COMP "TEST_LINE[8]" SITE "A8" ;
+LOCATE COMP "TEST_LINE[9]" SITE "B8" ;
+LOCATE COMP "TEST_LINE[10]" SITE "G10" ;
+LOCATE COMP "TEST_LINE[11]" SITE "G9" ;
+LOCATE COMP "TEST_LINE[12]" SITE "C9" ;
+LOCATE COMP "TEST_LINE[13]" SITE "C10" ;
+LOCATE COMP "TEST_LINE[14]" SITE "H10" ;
+LOCATE COMP "TEST_LINE[15]" SITE "H11" ;
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
+#################################################################
+# Connection to AddOn
+#################################################################
+LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0   #1
+LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1   #3
+LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2   #5
+LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3   #7
+LOCATE COMP "SFP_MOD1_1" SITE "R1" ;#DQLL0_4   #9
+LOCATE COMP "SFP_MOD2_1" SITE "R2" ;#DQLL0_5   #11
+LOCATE COMP "SFP_RATESEL_1" SITE "N3" ;#DQSLL0_T  #13
+LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C  #15
+LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6   #17
+LOCATE COMP "SFP_TXFAULT_1" SITE "P6" ;#DQLL0_7   #19
+LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8   #21
+LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9   #23
+LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0   #25
+LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1   #27
+LOCATE COMP "SFP_MOD1_2" SITE "AB1" ;#DQLL2_2   #29
+LOCATE COMP "SFP_MOD2_2" SITE "AC1" ;#DQLL2_3   #31
+LOCATE COMP "SFP_RATESEL_2" SITE "AA1" ;#DQLL2_4   #33
+LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5   #35
+LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T   #37  #should be DQSLL2
+LOCATE COMP "SFP_TXFAULT_2" SITE "W6" ;#DQLL2_C   #39  #should be DQSLL2
+LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0   #2
+LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1   #4
+LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2   #6
+LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3   #8
+LOCATE COMP "SFP_MOD1_3" SITE "AB3" ;#DQLL3_4   #10
+LOCATE COMP "SFP_MOD2_3" SITE "AB4" ;#DQLL3_5   #12
+LOCATE COMP "SFP_RATESEL_3" SITE "Y6" ;#DQLL3_T   #14  #should be DQSLL3
+LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C   #16  #should be DQSLL3
+LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6   #18
+LOCATE COMP "SFP_TXFAULT_3" SITE "AA4" ;#DQLL3_7   #20
+LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8   #22
+LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9   #24
+LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0   #26
+LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1   #28
+LOCATE COMP "SFP_MOD1_4" SITE "T1" ;#DQLL1_2   #30
+LOCATE COMP "SFP_MOD2_4" SITE "U1" ;#DQLL1_3   #32
+LOCATE COMP "SFP_RATESEL_4" SITE "P4" ;#DQLL1_4   #34
+LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5   #36
+LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T  #38
+LOCATE COMP "SFP_TXFAULT_4" SITE "R4" ;#DQSLL1_C  #40
+LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0   #169
+LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1   #171
+LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2   #173
+LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3   #175
+LOCATE COMP "SFP_MOD1_5" SITE "AA26" ;#DQLR1_4   #177
+LOCATE COMP "SFP_MOD2_5" SITE "AB26" ;#DQLR1_5   #179
+LOCATE COMP "SFP_RATESEL_5" SITE "W21" ;#DQSLR1_T  #181
+LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C  #183
+LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6   #185
+LOCATE COMP "SFP_TXFAULT_5" SITE "AA23" ;#DQLR1_7   #187
+LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0   #170
+LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1   #172
+LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2   #174
+LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3   #176
+LOCATE COMP "SFP_MOD1_6" SITE "T26" ;#DQLR2_4   #178
+LOCATE COMP "SFP_MOD2_6" SITE "U26" ;#DQLR2_5   #180
+LOCATE COMP "SFP_RATESEL_6" SITE "V21" ;#DQSLR2_T  #182
+LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C  #184
+LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6   #186
+LOCATE COMP "SFP_TXFAULT_6" SITE "V24" ;#DQLR2_7   #188
+DEFINE PORT GROUP "SFP_group" "SFP*" ;
+IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+#################################################################
+# Additional Lines to AddOn
+#################################################################
+#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
+#all lines are input only
+#line 4/5 go to PLL input
+LOCATE COMP "SPARE_LINE[0]" SITE "M25" ;#194
+LOCATE COMP "SPARE_LINE[1]" SITE "M26" ;#196
+LOCATE COMP "SPARE_LINE[2]" SITE "W4" ;#198
+LOCATE COMP "SPARE_LINE[3]" SITE "W5" ;#200
+LOCATE COMP "SPARE_LINE[4]" SITE "M3" ;#DQUL3_8_OUTOFLANE_FPGA__3 #69
+LOCATE COMP "SPARE_LINE[5]" SITE "M2" ;#DQUL3_9_OUTOFLANE_FPGA__3 #71  
+#################################################################
+# Flash ROM and Reboot
+#################################################################
+LOCATE COMP "FLASH_CLK" SITE "B12" ;
+LOCATE COMP "FLASH_CS" SITE "E11" ;
+LOCATE COMP "FLASH_DIN" SITE "E12" ;
+LOCATE COMP "FLASH_DOUT" SITE "A12" ;
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
+IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
+LOCATE COMP "PROGRAMN" SITE "B11" ;
+IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+#################################################################
+# Misc
+#################################################################
+LOCATE COMP "TEMPSENS" SITE "A13" ;
+IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+#coding of FPGA number
+LOCATE COMP "CODE_LINE[1]" SITE "AA20" ;
+LOCATE COMP "CODE_LINE[0]" SITE "Y21" ;
+IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+#terminated differential pair to pads
+LOCATE COMP "SUPPL" SITE "C14" ;
+IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
+#################################################################
+# LED
+#################################################################
+LOCATE COMP "LED_GREEN" SITE "F12" ;
+LOCATE COMP "LED_ORANGE" SITE "G13" ;
+LOCATE COMP "LED_RED" SITE "A15" ;
+LOCATE COMP "LED_YELLOW" SITE "A16" ;
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+MULTICYCLE TO GROUP "LED_group" 100.000000 ns ;
+#################################################################
+# Basic Settings
+#################################################################
+SYSCONFIG MCCLK_FREQ=20 ;
+FREQUENCY PORT "CLK_PCLK_RIGHT" 200.000000 MHz ;
+FREQUENCY PORT "CLK_PCLK_LEFT" 200.000000 MHz ;
+FREQUENCY PORT "CLK_GPLL_RIGHT" 200.000000 MHz ;
+FREQUENCY PORT "CLK_GPLL_LEFT" 125.000000 MHz ;
+#################################################################
+# Reset Nets
+#################################################################  
+GSR_NET NET "GSR_N";
+#################################################################
+# Locate Serdes and media interfaces
+#################################################################
+#//?   LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_0_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+#//?   LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_0_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_125_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/THE_SERDES/PCSD_INST" SITE "PCSB" ;
+#####REGION "MEDIA_UPLINK" "R90C95D" 13 25;
+#####REGION "MEDIA_DOWNLINK" "R90C120D" 25 35;
+REGION "REGION_SPI" "R13C150D" 12 16 DEVSIZE;
+#####REGION "REGION_IOBUF" "R10C43D"  88 86 DEVSIZE;
+LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ;
+LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
+#####LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
+#####LOCATE UGROUP "THE_SODA_SOURCE/media_interface_group" REGION "MEDIA_DOWNLINK" ;
+MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
+MULTICYCLE TO CELL "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/SCI_DATA_OUT*" 20.000000 ns ;
+MULTICYCLE TO CELL "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/sci*" 20.000000 ns ;
+MULTICYCLE FROM CELL "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/sci*" 20.000000 ns ;
+MULTICYCLE TO CELL "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/wa_pos*" 20.000000 ns ;
+#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50.000000 ns ;
+  
+MAXSKEW NET "clk_SODA200_i" 1.000000 nS ;
+#related:
+#clk_100_i <-> clk_200_i
+MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "clk_200_i" 5 ns ;
+MULTICYCLE FROM CLKNET "clk_200_i" TO CLKNET "clk_100_i" 5 ns ;
+#clk_SODA100_i <-> clk_SODA200_i
+MULTICYCLE FROM CLKNET "clk_SODA100_i" TO CLKNET "clk_SODA200_i" 5 ns ;
+MULTICYCLE FROM CLKNET "clk_SODA200_i" TO CLKNET "clk_SODA100_i" 5 ns ;
+
+#not releated:  
+#clk_100_i <-> clk_80_i
+MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "clk_80_i" 200 ns ;
+MULTICYCLE FROM CLKNET "clk_80_i" TO CLKNET "clk_100_i" 200 ns ;
+#clk_200_i <-> clk_80_i
+MULTICYCLE FROM CLKNET "clk_200_i" TO CLKNET "clk_80_i" 200 ns ;
+MULTICYCLE FROM CLKNET "clk_80_i" TO CLKNET "clk_200_i" 200 ns ;
+#clk_100_i <-> clk_160div3_i
+MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "clk_160div3_i" 200 ns ;
+MULTICYCLE FROM CLKNET "clk_160div3_i" TO CLKNET "clk_100_i" 200 ns ;
+#clk_200_i <-> clk_160div3_i
+MULTICYCLE FROM CLKNET "clk_200_i" TO CLKNET "clk_160div3_i" 200 ns ;
+MULTICYCLE FROM CLKNET "clk_160div3_i" TO CLKNET "clk_200_i" 200 ns ;
+#clk_100_i <-> clk_SODA100_i
+MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "clk_SODA100_i" 200 ns ;
+MULTICYCLE FROM CLKNET "clk_SODA100_i" TO CLKNET "clk_100_i" 200 ns ;
+#clk_200_i <-> clk_SODA100_i
+MULTICYCLE FROM CLKNET "clk_200_i" TO CLKNET "clk_SODA100_i" 200 ns ;
+MULTICYCLE FROM CLKNET "clk_SODA100_i" TO CLKNET "clk_200_i" 200 ns ;
+#clk_100_i <-> clk_SODA200_i
+MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "clk_SODA200_i" 200 ns ;
+MULTICYCLE FROM CLKNET "clk_SODA200_i" TO CLKNET "clk_100_i" 200 ns ;
+#clk_200_i <-> clk_SODA200_i
+MULTICYCLE FROM CLKNET "clk_200_i" TO CLKNET "clk_SODA200_i" 200 ns ;
+MULTICYCLE FROM CLKNET "clk_SODA200_i" TO CLKNET "clk_200_i" 200 ns ;
+#clk_SODA100_i <-> clk_80_i
+MULTICYCLE FROM CLKNET "clk_SODA100_i" TO CLKNET "clk_80_i" 200 ns ;
+MULTICYCLE FROM CLKNET "clk_80_i" TO CLKNET "clk_SODA100_i" 200 ns ;
+#clk_SODA200_i <-> clk_80_i
+MULTICYCLE FROM CLKNET "clk_SODA200_i" TO CLKNET "clk_80_i" 200 ns ;
+MULTICYCLE FROM CLKNET "clk_80_i" TO CLKNET "clk_SODA200_i" 200 ns ;
+#clk_SODA100_i <-> clk_160div3_i
+MULTICYCLE FROM CLKNET "clk_SODA100_i" TO CLKNET "clk_160div3_i" 200 ns ;
+MULTICYCLE FROM CLKNET "clk_160div3_i" TO CLKNET "clk_SODA100_i" 200 ns ;
+#clk_SODA200_i <-> clk_160div3_i
+MULTICYCLE FROM CLKNET "clk_SODA200_i" TO CLKNET "clk_160div3_i" 200 ns ;
+MULTICYCLE FROM CLKNET "clk_160div3_i" TO CLKNET "clk_SODA200_i" 200 ns ;
+#clk_80_i <-> clk_160div3_i
+MULTICYCLE FROM CLKNET "clk_80_i" TO CLKNET "clk_160div3_i" 200 ns ;
+MULTICYCLE FROM CLKNET "clk_160div3_i" TO CLKNET "clk_80_i" 200 ns ;
+
+
+
+
+BLOCK JTAGPATHS ;
+#MAXSKEW NET "the_dataconcentrator/dc_quad_fiber_module_all/serdesquadbuflayermux1/serdesquadmuxwrapper1/med_ecp3_quad_sfp_sync1/tx_sync_qd_c" 1.000000 nS ;
+#MULTICYCLE FROM CLKNET "clk_125_i_c" TO CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full0" 0.100000 ns ;
+#MULTICYCLE FROM CLKNET "clk_125_i_c" TO CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full1" 0.100000 ns ;
+#MULTICYCLE FROM CLKNET "clk_125_i_c" TO CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full2" 0.100000 ns ;
+#MULTICYCLE FROM CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full0" TO CLKNET "clk_125_i_c" 0.200000 ns ;
+#MULTICYCLE FROM CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full1" TO CLKNET "clk_125_i_c" 0.200000 ns ;
+#MULTICYCLE FROM CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full2" TO CLKNET "clk_125_i_c" 0.200000 ns ;
+#MULTICYCLE FROM CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full3" TO CLKNET "clk_125_i_c" 0.200000 ns ;
+#MAXSKEW NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full0" 1.000000 nS ;
+#MAXSKEW NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full1" 1.000000 nS ;
+#MAXSKEW NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full2" 1.000000 nS ;
+#MAXSKEW NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full3" 1.000000 nS ;
+#MAXDELAY FROM CELL "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/tx_sync_qd_c" TO ASIC "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/THE_SERDES/PCSD_INST" PIN "FFC_SYNC_TOGGLE" 1.200000 ns ;
+#MULTICYCLE FROM CLKNET "clk_125_i_c" TO CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full3" 0.100000 ns ;
+#PERIOD NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full0" 1.000000 nS  ;
+#PERIOD NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full1" 1.000000 nS  ;
+#PERIOD NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full2" 1.000000 nS  ;
+#PERIOD NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full3" 1.000000 nS  ;
+#FREQUENCY NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full1" 1000.000000 MHz ;
+#FREQUENCY NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full2" 1000.000000 MHz ;
+#FREQUENCY NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full3" 1000.000000 MHz ;
+#FREQUENCY NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full0" 1000.000000 MHz ;
diff --git a/data_concentrator/trb3_periph_data_concentrator.vhd b/data_concentrator/trb3_periph_data_concentrator.vhd
new file mode 100644
index 0000000..6b6063c
--- /dev/null
+++ b/data_concentrator/trb3_periph_data_concentrator.vhd
@@ -0,0 +1,1480 @@
+library ieee;
+use ieee.std_logic_1164.all;
+--use ieee.numeric_std.all;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.soda_components.all;
+use work.version.all;
+use work.panda_package.all; 
+
+entity trb3_periph_data_concentrator is
+  port(
+    --Clocks
+    CLK_GPLL_LEFT  : in std_logic;      --Clock Manager 1/(2468), 125 MHz
+    CLK_GPLL_RIGHT : in std_logic;  --Clock Manager 2/(2468), 200 MHz  <-- MAIN CLOCK for FPGA
+    CLK_PCLK_LEFT  : in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+    CLK_PCLK_RIGHT : in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+
+    --Trigger
+    TRIGGER_LEFT  : in std_logic;       --left side trigger input from fan-out
+    TRIGGER_RIGHT : in std_logic;       --right side trigger input from fan-out
+
+    --Serdes
+    CLK_SERDES_INT_LEFT  : in  std_logic;  --Clock Manager 1/(1357), off, 125 MHz possible
+    CLK_SERDES_INT_RIGHT : in  std_logic;  --Clock Manager 2/(1357), 200 MHz, only in case of problems
+    SERDES_INT_TX        : out std_logic_vector(3 downto 0);
+    SERDES_INT_RX        : in  std_logic_vector(3 downto 0);
+    SERDES_ADDON_TX      : out std_logic_vector(11 downto 0);
+    SERDES_ADDON_RX      : in  std_logic_vector(11 downto 0);
+
+    --Inter-FPGA Communication
+    FPGA5_COMM : inout std_logic_vector(11 downto 0);
+                                                      --Bit 0/1 input, serial link RX active
+                                                      --Bit 2/3 output, serial link TX active
+                                                      --others yet undefined
+    --Connection to AddOn
+    LED_LINKOK : out std_logic_vector(6 downto 1);
+    LED_RX     : out std_logic_vector(6 downto 1); 
+    LED_TX     : out std_logic_vector(6 downto 1);
+    SFP_MOD0   : in  std_logic_vector(6 downto 1);
+    SFP_TXDIS  : out std_logic_vector(6 downto 1); 
+    SFP_LOS    : in  std_logic_vector(6 downto 1);
+    --SFP_MOD1   : inout std_logic_vector(6 downto 1); 
+    --SFP_MOD2   : inout std_logic_vector(6 downto 1); 
+    --SFP_RATESEL : out std_logic_vector(6 downto 1);
+    --SFP_TXFAULT : in  std_logic_vector(6 downto 1);
+    SPARE_LINE : inout std_logic_vector(5 downto 0);  --inputs only
+	
+
+--Flash ROM & Reboot
+    FLASH_CLK  : out   std_logic;
+    FLASH_CS   : out   std_logic;
+    FLASH_DIN  : out   std_logic;
+    FLASH_DOUT : in    std_logic;
+    PROGRAMN   : out   std_logic;                     --reboot FPGA
+
+    --Misc
+    TEMPSENS   : inout std_logic;       --Temperature Sensor
+    CODE_LINE  : in    std_logic_vector(1 downto 0);
+    LED_GREEN  : out   std_logic;
+    LED_ORANGE : out   std_logic;
+    LED_RED    : out   std_logic;
+    LED_YELLOW : out   std_logic;
+    SUPPL      : in    std_logic;       --terminated diff pair, PCLK, Pads
+
+    --Test Connectors
+    TEST_LINE : out std_logic_vector(15 downto 0)
+    );
+
+
+  attribute syn_useioff                  : boolean;
+  --no IO-FF for LEDs relaxes timing constraints
+  attribute syn_useioff of LED_GREEN     : signal is false;
+  attribute syn_useioff of LED_ORANGE    : signal is false;
+  attribute syn_useioff of LED_RED       : signal is false;
+  attribute syn_useioff of LED_YELLOW    : signal is false;
+  attribute syn_useioff of TEMPSENS      : signal is false;
+  attribute syn_useioff of PROGRAMN      : signal is false;
+  attribute syn_useioff of CODE_LINE     : signal is false;
+  attribute syn_useioff of TRIGGER_LEFT  : signal is false;
+  attribute syn_useioff of TRIGGER_RIGHT : signal is false;
+
+  --important signals _with_ IO-FF
+  attribute syn_useioff of FLASH_CLK  : signal is true;
+  attribute syn_useioff of FLASH_CS   : signal is true;
+  attribute syn_useioff of FLASH_DIN  : signal is true;
+  attribute syn_useioff of FLASH_DOUT : signal is true;
+  attribute syn_useioff of FPGA5_COMM : signal is true;
+  attribute syn_useioff of TEST_LINE  : signal is true;
+
+  attribute syn_useioff of SPARE_LINE : signal is true;
+
+
+end entity;
+
+architecture trb3_periph_data_concentrator_arch of trb3_periph_data_concentrator is
+
+component pll_in200_out125_62M5 is
+    port (
+        CLK: in std_logic; 
+        CLKOP: out std_logic; -- 125M
+        CLKOS: out std_logic; -- 200M
+        CLKOK: out std_logic; -- 62M5
+        LOCK: out std_logic);
+end component;
+
+component pll_in125_out125_62M5 is
+    port (
+		CLK: in std_logic; 
+		CLKOP: out std_logic; 
+		CLKOK: out std_logic; 
+		LOCK: out std_logic);
+ end component;
+
+component pll_in200_out160M_80M is
+    port (
+		CLK: in std_logic; 
+		CLKOP: out std_logic; 
+		CLKOK: out std_logic; 
+		LOCK: out std_logic);
+ end component;
+
+component pll_in200_out200M_100M is
+    port (
+		CLK: in std_logic;  -- 200MHz
+		CLKOP: out std_logic; -- 100MHz
+		CLKOS: out std_logic; -- 200MHz
+		LOCK: out std_logic);
+ end component;
+
+component pll_in100_out80M is
+    port (
+		CLK: in std_logic;  -- 100MHz
+		CLKOP: out std_logic; -- 160MHz
+		CLKOK: out std_logic; -- 80MHz
+		CLKOK2: out std_logic; -- 160/3MHz
+		LOCK: out std_logic);
+ end component;
+
+component trb_net16_endpoint_data_concentrator_handler is
+  generic (
+    IBUF_DEPTH                   : channel_config_t              := (6,6,6,6);
+    FIFO_TO_INT_DEPTH            : channel_config_t              := (6,6,6,6);
+    FIFO_TO_APL_DEPTH            : channel_config_t              := (1,1,1,1);
+    APL_WRITE_ALL_WORDS          : channel_config_t              := (c_NO,c_NO,c_NO,c_NO);
+    ADDRESS_MASK                 : std_logic_vector(15 downto 0) := x"FFFF";
+    BROADCAST_BITMASK            : std_logic_vector(7 downto 0)  := x"FF";
+    BROADCAST_SPECIAL_ADDR       : std_logic_vector(7 downto 0)  := x"FF";
+    REGIO_NUM_STAT_REGS          : integer range 0 to 6          := 3; --log2 of number of status registers
+    REGIO_NUM_CTRL_REGS          : integer range 0 to 6          := 3; --log2 of number of ctrl registers
+    REGIO_INIT_CTRL_REGS         : std_logic_vector(16*32-1 downto 0) := (others => '0');
+    REGIO_INIT_ADDRESS           : std_logic_vector(15 downto 0) := x"FFFF";
+    REGIO_INIT_BOARD_INFO        : std_logic_vector(31 downto 0) := x"1111_2222";
+    REGIO_INIT_ENDPOINT_ID       : std_logic_vector(15 downto 0) := x"0001";
+    REGIO_COMPILE_TIME           : std_logic_vector(31 downto 0) := x"00000000";
+    REGIO_COMPILE_VERSION        : std_logic_vector(15 downto 0) := x"0001";
+    REGIO_HARDWARE_VERSION       : std_logic_vector(31 downto 0) := x"91000000";
+    REGIO_USE_1WIRE_INTERFACE    : integer := c_YES; --c_YES,c_NO,c_MONITOR
+    REGIO_USE_VAR_ENDPOINT_ID    : integer range c_NO to c_YES   := c_NO;
+    CLOCK_FREQUENCY              : integer range 1 to 200        := 100;
+    TIMING_TRIGGER_RAW           : integer range 0 to 1 := c_YES;
+    --Configure data handler
+    DATA_INTERFACE_NUMBER        : integer range 1 to 16         := 1;
+    DATA_BUFFER_DEPTH            : integer range 9 to 14         := 9;
+    DATA_BUFFER_WIDTH            : integer range 1 to 32         := 32;
+    DATA_BUFFER_FULL_THRESH      : integer range 0 to 2**14-2    := 2**8;
+    TRG_RELEASE_AFTER_DATA       : integer range 0 to 1          := c_YES;
+    HEADER_BUFFER_DEPTH          : integer range 9 to 14         := 9;
+    HEADER_BUFFER_FULL_THRESH    : integer range 2**8 to 2**14-2 := 2**8
+    );
+
+  port(
+    --  Misc
+    CLK                          : in  std_logic;
+    RESET                        : in  std_logic;
+    CLK_EN                       : in  std_logic := '1';
+
+    --  Media direction port
+    MED_DATAREADY_OUT            : out std_logic;
+    MED_DATA_OUT                 : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_OUT           : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+    MED_READ_IN                  : in  std_logic;
+    MED_DATAREADY_IN             : in  std_logic;
+    MED_DATA_IN                  : in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_IN            : in  std_logic_vector (c_NUM_WIDTH-1 downto 0);
+    MED_READ_OUT                 : out std_logic;
+    MED_STAT_OP_IN               : in  std_logic_vector(15 downto 0);
+    MED_CTRL_OP_OUT              : out std_logic_vector(15 downto 0);
+
+    --Timing trigger in
+    TRG_TIMING_TRG_RECEIVED_IN   : in  std_logic;
+    --LVL1 trigger to FEE
+    LVL1_TRG_DATA_VALID_OUT      : out std_logic;    --trigger type, number, code, information are valid
+    LVL1_VALID_TIMING_TRG_OUT    : out std_logic;    --valid timing trigger has been received
+    LVL1_VALID_NOTIMING_TRG_OUT  : out std_logic;    --valid trigger without timing trigger has been received
+    LVL1_INVALID_TRG_OUT         : out std_logic;    --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
+
+    LVL1_TRG_TYPE_OUT            : out std_logic_vector(3 downto 0);
+    LVL1_TRG_NUMBER_OUT          : out std_logic_vector(15 downto 0);
+    LVL1_TRG_CODE_OUT            : out std_logic_vector(7 downto 0);
+    LVL1_TRG_INFORMATION_OUT     : out std_logic_vector(23 downto 0);
+    LVL1_INT_TRG_NUMBER_OUT      : out std_logic_vector(15 downto 0);  --internally generated trigger number, for informational uses only
+
+    --Information about trigger handler errors
+    TRG_MULTIPLE_TRG_OUT         : out std_logic;
+    TRG_TIMEOUT_DETECTED_OUT     : out std_logic;
+    TRG_SPURIOUS_TRG_OUT         : out std_logic;
+    TRG_MISSING_TMG_TRG_OUT      : out std_logic;
+    TRG_SPIKE_DETECTED_OUT       : out std_logic;
+
+    --Response from FEE
+    FEE_TRG_RELEASE_IN           : in  std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+    FEE_TRG_STATUSBITS_IN        : in  std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
+    FEE_DATA_IN                  : in  std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
+    FEE_DATA_WRITE_IN            : in  std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+    FEE_DATA_FINISHED_IN         : in  std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+    FEE_DATA_ALMOST_FULL_OUT     : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+
+    --Slow Control Port
+    --common registers
+    REGIO_COMMON_STAT_REG_IN     : in  std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+    REGIO_COMMON_CTRL_REG_OUT    : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+    REGIO_COMMON_STAT_STROBE_OUT : out std_logic_vector(std_COMSTATREG-1 downto 0);
+    REGIO_COMMON_CTRL_STROBE_OUT : out std_logic_vector(std_COMCTRLREG-1 downto 0);
+    --user defined registers
+    REGIO_STAT_REG_IN            : in  std_logic_vector(2**(REGIO_NUM_STAT_REGS)*32-1 downto 0) := (others => '0');
+    REGIO_CTRL_REG_OUT           : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)*32-1 downto 0);
+    REGIO_STAT_STROBE_OUT        : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
+    REGIO_CTRL_STROBE_OUT        : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+    --internal data port
+    BUS_ADDR_OUT                 : out std_logic_vector(16-1 downto 0);
+    BUS_DATA_OUT                 : out std_logic_vector(32-1 downto 0);
+    BUS_READ_ENABLE_OUT          : out std_logic;
+    BUS_WRITE_ENABLE_OUT         : out std_logic;
+    BUS_TIMEOUT_OUT              : out std_logic;
+    BUS_DATA_IN                  : in  std_logic_vector(32-1 downto 0) := (others => '0');
+    BUS_DATAREADY_IN             : in  std_logic                       := '0';
+    BUS_WRITE_ACK_IN             : in  std_logic                       := '0';
+    BUS_NO_MORE_DATA_IN          : in  std_logic                       := '0';
+    BUS_UNKNOWN_ADDR_IN          : in  std_logic                       := '0';
+    --Onewire
+    ONEWIRE_INOUT                : inout std_logic;  --temperature sensor
+    ONEWIRE_MONITOR_IN           : in  std_logic := '0';
+    ONEWIRE_MONITOR_OUT          : out std_logic;
+    --Config endpoint id, if not statically assigned
+    REGIO_VAR_ENDPOINT_ID        : in  std_logic_vector (15 downto 0) := (others => '0');
+
+    --Timing registers
+    TIME_GLOBAL_OUT              : out std_logic_vector (31 downto 0); --global time, microseconds
+    TIME_LOCAL_OUT               : out std_logic_vector ( 7 downto 0); --local time running with chip frequency
+    TIME_SINCE_LAST_TRG_OUT      : out std_logic_vector (31 downto 0); --local time, resetted with each trigger
+    TIME_TICKS_OUT               : out std_logic_vector ( 1 downto 0); --bit 1 ms-tick, 0 us-tick
+
+    --Debugging & Status information
+    STAT_DEBUG_IPU               : out std_logic_vector (31 downto 0);
+    STAT_DEBUG_1                 : out std_logic_vector (31 downto 0);
+    STAT_DEBUG_2                 : out std_logic_vector (31 downto 0);
+    STAT_DEBUG_DATA_HANDLER_OUT  : out std_logic_vector (31 downto 0);
+    STAT_DEBUG_IPU_HANDLER_OUT   : out std_logic_vector (31 downto 0);
+    CTRL_MPLEX                   : in  std_logic_vector (31 downto 0) := (others => '0');
+    IOBUF_CTRL_GEN               : in  std_logic_vector (4*32-1 downto 0) := (others => '0');
+    STAT_ONEWIRE                 : out std_logic_vector (31 downto 0);
+    STAT_ADDR_DEBUG              : out std_logic_vector (15 downto 0);
+    STAT_TRIGGER_OUT             : out std_logic_vector (79 downto 0);
+    DEBUG_LVL1_HANDLER_OUT       : out std_logic_vector (15 downto 0)
+    );
+end component;
+
+component trb_net16_med_1_2sync_3_ecp3_sfp is
+  port(
+    CLK                : in  std_logic; -- SerDes clock
+    SYSCLK             : in  std_logic; -- fabric clock
+    RESET              : in  std_logic; -- synchronous reset
+    CLEAR              : in  std_logic; -- asynchronous reset
+    CLK_EN             : in  std_logic;
+    --Internal Connection
+    MED_DATA_IN        : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_IN  : in  std_logic_vector(c_NUM_WIDTH-1 downto 0);
+    MED_DATAREADY_IN   : in  std_logic;
+    MED_READ_OUT       : out std_logic;
+    MED_DATA_OUT       : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+    MED_DATAREADY_OUT  : out std_logic;
+    MED_READ_IN        : in  std_logic;
+    REFCLK2CORE_OUT    : out std_logic;
+    CLK_RX_HALF_OUT    : out std_logic;
+    CLK_RX_FULL_OUT    : out std_logic;
+    --SFP Connection
+    SD_RXD_P_IN        : in  std_logic;
+    SD_RXD_N_IN        : in  std_logic;
+    SD_TXD_P_OUT       : out std_logic;
+    SD_TXD_N_OUT       : out std_logic;
+    SD_REFCLK_P_IN     : in  std_logic;
+    SD_REFCLK_N_IN     : in  std_logic;
+    SD_PRSNT_N_IN      : in  std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+    SD_LOS_IN          : in  std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+    SD_TXDIS_OUT       : out  std_logic; -- SFP disable
+    --Control Interface
+    SCI_DATA_IN        : in  std_logic_vector(7 downto 0) := (others => '0');
+    SCI_DATA_OUT       : out std_logic_vector(7 downto 0) := (others => '0');
+    SCI_ADDR           : in  std_logic_vector(8 downto 0) := (others => '0');
+    SCI_READ           : in  std_logic := '0';
+    SCI_WRITE          : in  std_logic := '0';
+    SCI_ACK            : out std_logic := '0';
+    SCI_NACK           : out std_logic := '0';
+	-- SODA serdes channel
+    SODA_RXD_P_IN      : in  std_logic;
+    SODA_RXD_N_IN      : in  std_logic;
+    SODA_TXD_P_OUT     : out std_logic;
+    SODA_TXD_N_OUT     : out std_logic;
+	SODA_DLM_IN        : in  std_logic;
+	SODA_DLM_WORD_IN   : in  std_logic_vector(7 downto 0);
+	SODA_DLM_OUT       : out  std_logic;
+	SODA_DLM_WORD_OUT  : out  std_logic_vector(7 downto 0);
+    SODA_CLOCK_OUT     : out  std_logic; -- 200MHz
+    -- Connection to addon interface        
+    DOUT_TXD_P_OUT     : out  std_logic;
+    DOUT_TXD_N_OUT     : out  std_logic;
+    SFP_MOD0_5         : in  std_logic;
+    SFP_MOD0_3         : in  std_logic;          
+    SFP_LOS_5          : in  std_logic;          
+    SFP_LOS_3          : in  std_logic;
+	TX_READY_CH3       : out std_logic;
+    TX_DATA_CH3        : in std_logic_vector(7 downto 0);
+    TX_K_CH3           : in std_logic;
+    -- Status and control port
+    STAT_OP            : out std_logic_vector (15 downto 0);
+    CTRL_OP            : in  std_logic_vector (15 downto 0);
+    STAT_DEBUG         : out std_logic_vector (63 downto 0);
+    CTRL_DEBUG         : in  std_logic_vector (63 downto 0)
+   );
+end component;
+
+component dataconversion_for_serdes is
+  port (
+    DATA_CLK        : in  std_logic;
+    CLK             : in  std_logic;
+    RESET           : in  std_logic;
+    TX_READY        : in  std_logic;
+    SFP_MOD0        : in  std_logic;
+    SFP_LOS         : in  std_logic;
+    TX_DATA         : out std_logic_vector(7 downto 0);
+    TX_K            : out std_logic;
+    DATA_IN_ALLOWED : out std_logic;
+    DATA_IN         : in  std_logic_vector(63 downto 0);
+    DATA_IN_WRITE   : in  std_logic;
+    DATA_IN_FIRST   : in  std_logic;
+    DATA_IN_LAST    : in  std_logic;
+    DATA_IN_ERROR   : in  std_logic);
+end component;
+
+component DC_module_TRB3 is
+	generic (
+		NROFFIBERS              : natural := NROFFIBERS;
+		NROFADCS                : natural := NROFADCS;
+		ADCBITS                 : natural := ADCBITS;
+		SODAPERIOD_IN_PS        : natural := 8000; -- SODA clock period in ps 155.52MHz=6430, 125MHz=8000
+		SODACLOCKDIV            : natural := 2; -- 1,2,4 : SODA clock divide factor
+		SODA_16BIT_INTERFACE	: boolean := FALSE;
+		ADCCLOCKFREQUENCY       : natural := ADCCLOCKFREQUENCY;
+		MAX_DIVIDERSCALEBITS    : natural := 12;
+		MAX_LUTSIZEBITS         : natural := 9;
+		MAX_LUTSCALEBITS        : natural := 14;
+		HISTOGRAM_SIZEBITS      : natural := 12;
+		MUXINFIFOSIZE           : natural := 9;
+		TRANSFERFIFOSIZE        : natural := 12;
+		CF_FRACTIONBIT          : natural := 11;
+		ADCINDEXSHIFT           : natural := 1;
+		TRANSITIONBUFFERBITS    : natural := 9;
+		PANDAPACKETBUFFERBITS   : natural := 13;
+		ENERGYSCALINGBITS       : natural := 13;
+		COMBINEPULSESMEMSIZE    : natural := 10;
+		COMBINETIMEDIFFERENCE   : natural := 5000;
+		SYSTEM_ID               : std_logic_vector(15 downto 0) := x"5555"
+		);
+	port ( 
+		slowcontrol_clock       : in std_logic;
+		packet_in_clock         : in std_logic;
+		MUX_clock               : in std_logic;
+		packet_out_clock        : in std_logic;
+		SODA_clock              : in std_logic;
+		reset                   : in std_logic;
+
+-- Slave bus
+		BUS_READ_IN             : in   std_logic;
+		BUS_WRITE_IN            : in   std_logic;
+		BUS_BUSY_OUT            : out  std_logic;
+		BUS_ACK_OUT             : out  std_logic;
+		BUS_ADDR_IN             : in   std_logic_vector(1 downto 0);
+		BUS_DATA_IN             : in   std_logic_vector(31 downto 0);
+		BUS_DATA_OUT            : out  std_logic_vector(31 downto 0);
+		
+-- fiber interface signals:
+		gtpClk                  : in std_logic; -- 200MHz
+		gtpClkDiv2              : in std_logic; -- 100MHz
+		refClkOut               : out std_logic;
+		refClk_OK               : out std_logic;
+		gtpLOS                  : in std_logic_vector(0 to NROFFIBERS-1);
+		gtpTxP0                 : out std_logic_vector(0 to NROFFIBERS-1);
+		gtpTxN0                 : out std_logic_vector(0 to NROFFIBERS-1);
+		gtpRxP0                 : in std_logic_vector(0 to NROFFIBERS-1);
+		gtpRxN0                 : in std_logic_vector(0 to NROFFIBERS-1);
+
+-- 64 bits data output
+		data_out_allowed        : in std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_write          : out std_logic;
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_error          : out std_logic;
+		
+-- SODA signals
+		TX_DLM                  : in std_logic_vector(0 to NROFFIBERS-1);
+		TX_DLM_WORD             : in array_fiber8bits_type;  
+		RX_DLM                  : out std_logic_vector(0 to NROFFIBERS-1);
+		RX_DLM_WORD             : out array_fiber8bits_type;
+		EnableExternalSODA      : out std_logic;
+		
+-- Control Interface
+		SCI_DATA_IN             : in  std_logic_vector(7 downto 0) := (others => '0');
+		SCI_DATA_OUT            : out std_logic_vector(7 downto 0) := (others => '0');
+		SCI_ADDR                : in  std_logic_vector(8 downto 0) := (others => '0');
+		SCI_READ                : in  std_logic := '0';
+		SCI_WRITE               : in  std_logic := '0';
+		SCI_ACK                 : out std_logic := '0';
+		SCI_NACK                : out std_logic := '0';
+		
+-- testpoints
+		txpll_clocks            : out std_logic_vector(3 downto 0); 
+		LEDs_link_ok            : out std_logic_vector(0 to 3);
+		LEDs_rx                 : out std_logic_vector(0 to 3); 
+		LEDs_tx                 : out std_logic_vector(0 to 3);
+		testword0               : out std_logic_vector (35 downto 0);
+		testword0clock          : out std_logic;
+		testword1               : out std_logic_vector (35 downto 0);
+		testword2               : out std_logic_vector (35 downto 0)
+
+		);
+end component;
+
+component DCS
+-- synthesis translate_off
+	GENERIC (
+		DCSMODE : string := "POS");
+-- synthesis translate_on
+	PORT (
+		CLK0 :IN std_logic ;
+		CLK1 :IN std_logic ;
+		SEL :IN std_logic ;
+		DCSOUT :OUT std_logic) ;
+	END COMPONENT;
+attribute DCSMODE : string;
+attribute DCSMODE of SODAclockswitch : label is "POS";
+
+
+--Constants
+  constant REGIO_NUM_STAT_REGS : integer := 2;
+  constant REGIO_NUM_CTRL_REGS : integer := 2;
+
+  attribute syn_keep     : boolean;
+  attribute syn_preserve : boolean;
+
+  --Clock / Reset
+  signal clk_100_i                : std_logic;  --clock for main logic, 100 MHz, via Clock Manager and internal PLL
+  signal clk_200_i                : std_logic;  --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+ 
+  signal clk_160_i                : std_logic;
+  signal clk_160div3_i            : std_logic;
+  signal clk_80_i                 : std_logic;
+  signal pll_lock                 : std_logic;  --Internal PLL locked. E.g. used to reset all internal logic.
+  signal clk_SODA100_i            : std_logic;
+  signal clk_SODA200_i            : std_logic;
+  
+  
+  signal clear_i                  : std_logic;
+  signal reset_i                  : std_logic;
+  signal GSR_N                    : std_logic;
+  attribute syn_keep of GSR_N     : signal is true;
+  attribute syn_preserve of GSR_N : signal is true;
+
+  --Media Interface
+  signal med_stat_op        : std_logic_vector (1*16-1 downto 0);
+  signal med_ctrl_op        : std_logic_vector (1*16-1 downto 0);
+  signal med_stat_debug     : std_logic_vector (1*64-1 downto 0);
+  signal med_ctrl_debug     : std_logic_vector (1*64-1 downto 0);
+  signal med_data_out       : std_logic_vector (1*16-1 downto 0);
+  signal med_packet_num_out : std_logic_vector (1*3-1 downto 0);
+  signal med_dataready_out  : std_logic;
+  signal med_read_out       : std_logic;
+  signal med_data_in        : std_logic_vector (1*16-1 downto 0);
+  signal med_packet_num_in  : std_logic_vector (1*3-1 downto 0);
+  signal med_dataready_in   : std_logic;
+  signal med_read_in        : std_logic;
+
+  --LVL1 channel
+  signal timing_trg_received_i : std_logic;
+  signal trg_data_valid_i      : std_logic;
+  signal trg_timing_valid_i    : std_logic;
+  signal trg_notiming_valid_i  : std_logic;
+  signal trg_invalid_i         : std_logic;
+  signal trg_type_i            : std_logic_vector(3 downto 0);
+  signal trg_number_i          : std_logic_vector(15 downto 0);
+  signal trg_code_i            : std_logic_vector(7 downto 0);
+  signal trg_information_i     : std_logic_vector(23 downto 0);
+  signal trg_int_number_i      : std_logic_vector(15 downto 0);
+  signal trg_multiple_trg_i    : std_logic;
+  signal trg_timeout_detected_i: std_logic;
+  signal trg_spurious_trg_i    : std_logic;
+  signal trg_missing_tmg_trg_i : std_logic;
+  signal trg_spike_detected_i  : std_logic;
+  
+  --Data channel
+  signal fee_trg_release_i    : std_logic;
+  signal fee_trg_statusbits_i : std_logic_vector(31 downto 0);
+  signal fee_data_i           : std_logic_vector(31 downto 0);
+  signal fee_data_write_i     : std_logic;
+  signal fee_data_finished_i  : std_logic;
+  signal fee_almost_full_i    : std_logic;
+
+  --Slow Control channel
+  signal common_stat_reg        : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+  signal common_ctrl_reg        : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+  signal stat_reg               : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
+  signal ctrl_reg               : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
+  signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
+  signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
+  signal stat_reg_strobe        : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
+  signal ctrl_reg_strobe        : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
+
+  --RegIO
+  signal my_address             : std_logic_vector (15 downto 0);
+  signal regio_addr_out         : std_logic_vector (15 downto 0);
+  signal regio_read_enable_out  : std_logic;
+  signal regio_write_enable_out : std_logic;
+  signal regio_data_out         : std_logic_vector (31 downto 0);
+  signal regio_data_in          : std_logic_vector (31 downto 0);
+  signal regio_dataready_in     : std_logic;
+  signal regio_no_more_data_in  : std_logic;
+  signal regio_write_ack_in     : std_logic;
+  signal regio_unknown_addr_in  : std_logic;
+  signal regio_timeout_out      : std_logic;
+
+  --Timer
+  signal global_time         : std_logic_vector(31 downto 0);
+  signal local_time          : std_logic_vector(7 downto 0);
+  signal time_since_last_trg : std_logic_vector(31 downto 0);
+  signal timer_ticks         : std_logic_vector(1 downto 0);
+
+  --Flash
+  signal spictrl_read_en  : std_logic;
+  signal spictrl_write_en : std_logic;
+  signal spictrl_data_in  : std_logic_vector(31 downto 0);
+  signal spictrl_addr     : std_logic;
+  signal spictrl_data_out : std_logic_vector(31 downto 0);
+  signal spictrl_ack      : std_logic;
+  signal spictrl_busy     : std_logic;
+  signal spimem_read_en   : std_logic;
+  signal spimem_write_en  : std_logic;
+  signal spimem_data_in   : std_logic_vector(31 downto 0);
+  signal spimem_addr      : std_logic_vector(5 downto 0);
+  signal spimem_data_out  : std_logic_vector(31 downto 0);
+  signal spimem_ack       : std_logic;
+
+  signal spi_bram_addr    : std_logic_vector(7 downto 0);
+  signal spi_bram_wr_d    : std_logic_vector(7 downto 0);
+  signal spi_bram_rd_d    : std_logic_vector(7 downto 0);
+  signal spi_bram_we      : std_logic;
+
+  signal TXfee_DLM_S      : std_logic_vector(0 to NROFFIBERS-1);
+  signal TXfee_DLM_word_S : array_fiber8bits_type;  
+  signal RXfee_DLM_S      : std_logic_vector(0 to NROFFIBERS-1);
+  signal RXfee_DLM_word_S : array_fiber8bits_type;
+		
+  signal RXBTM_DLM_S      : t_HUB_DLM;
+  signal RXBTM_DLM_WORD_S : t_HUB_DLM_WORD;
+  signal TXBTM_DLM_S      : t_HUB_DLM;
+  signal TXBTM_DLM_WORD_S : t_HUB_DLM_WORD;
+
+  signal RXtop_DLM_S      : std_logic;
+  signal RXtop_DLM_word_S : std_logic_vector(7 downto 0) := (others => '0');
+  signal TXtop_DLM_S      : std_logic;
+  signal TXtop_DLM_word_S : std_logic_vector(7 downto 0) := (others => '0');
+
+  signal sodasrc_TX_DLM_S : std_logic;
+  signal sodasrc_TX_DLM_word_S : std_logic_vector(7 downto 0) := (others => '0');
+  signal sodasrc_TXtop_DLM_S : std_logic;
+  signal sodasrc_TXtop_DLM_word_S : std_logic_vector(7 downto 0) := (others => '0');
+  signal ext_sodasrc_TX_DLM_S : std_logic;
+  signal ext_sodasrc_TX_DLM_word_S : std_logic_vector(7 downto 0) := (others => '0');
+
+  signal SODA_burst_pulse_S : std_logic;
+  signal EnableExternalSODA_S : std_logic;
+
+  signal tx_data_ch3            : std_logic_vector(7 downto 0);
+  signal tx_k_ch3               : std_logic;
+  signal tx_ready_ch3           : std_logic;
+  signal data64b_muxed_allowed  : std_logic;
+  signal data64b_muxed          : std_logic_vector(63 downto 0);
+  signal data64b_muxed_write    : std_logic;
+  signal data64b_muxed_first    : std_logic;
+  signal data64b_muxed_last     : std_logic;
+  signal data64b_muxed_error    : std_logic;
+  signal data64b_muxed_error_S  : std_logic;
+  signal data64b_muxed_allowed0_S: std_logic;
+  signal data64b_muxed_allowed_S: std_logic;
+  signal data64b_muxed_busy_S   : std_logic;
+ 
+  
+  --FPGA Test
+  signal time_counter : unsigned(31 downto 0);
+
+  --TDC component
+  component TDC
+    generic (
+      CHANNEL_NUMBER : integer range 0 to 64);
+    port (
+      RESET             : in  std_logic;
+      CLK_TDC           : in  std_logic;
+      CLK_READOUT       : in  std_logic;
+      HIT_IN            : in  std_logic_vector(CHANNEL_NUMBER-1 downto 0);
+      TRIGGER_IN        : in  std_logic;
+      TRIGGER_WIN_IN    : in  std_logic_vector(31 downto 0);
+      DATA_OUT          : out std_logic_vector(31 downto 0);
+      TRB_WR_CLK_OUT    : out std_logic;
+      DATA_VALID_OUT    : out std_logic;
+      DATA_FINISHED_OUT : out std_logic;
+      READY_OUT         : out std_logic;
+      TDC_DEBUG_00      : out std_logic_vector(31 downto 0));
+  end component;
+ 
+   -- data_concentrator
+  signal SODA_clock        : std_logic;
+  signal SODAdiv2_clock    : std_logic;
+  signal PACKETIN_clock    : std_logic;
+  signal MUX_clock         : std_logic;
+  signal PACKETOUT_clock   : std_logic;
+  signal dc_read_en        : std_logic := '0';
+  signal dc_write_en       : std_logic := '0';
+  signal dc_busy           : std_logic := '0';
+  signal dc_ack            : std_logic := '0';
+  signal dc_addr           : std_logic_vector(1 downto 0);
+  signal dc_data_in        : std_logic_vector(31 downto 0);
+  signal dc_data_out       : std_logic_vector(31 downto 0);
+
+    -- soda hub
+  signal soda_read_en      : std_logic;
+  signal soda_write_en     : std_logic;
+  signal soda_ack          : std_logic;
+  signal soda_addr         : std_logic_vector(3 downto 0);
+  signal soda_data_in      : std_logic_vector(31 downto 0);
+  signal soda_data_out     : std_logic_vector(31 downto 0);
+		
+    -- soda source
+  signal sodasrc_read_en   : std_logic;
+  signal sodasrc_write_en  : std_logic;
+  signal sodasrc_ack       : std_logic;
+  signal sodasrc_addr      : std_logic_vector(3 downto 0);
+  signal sodasrc_data_in   : std_logic_vector(31 downto 0);
+  signal sodasrc_data_out  : std_logic_vector(31 downto 0);
+
+  signal SODA_clock_rx     : std_logic;
+
+  -- LEDs
+  signal LEDs_link_ok_i    : std_logic_vector(0 to 3);
+  signal LEDs_rx_i         : std_logic_vector(0 to 3);
+  signal LEDs_tx_i         : std_logic_vector(0 to 3);
+
+  signal txpll_clocks_S         : std_logic_vector(3 downto 0) := (others => '0');
+--  signal txpll_clocks_div2_S    : std_logic_vector(3 downto 0) := (others => '0');
+--  signal SODA_clock_div2_S      : std_logic := '0';
+--  signal clock125_div2_S        : std_logic := '0';
+ 		
+  signal testword0clock_i    : std_logic;
+  attribute syn_keep of testword0clock_i     : signal is true; 
+  attribute syn_preserve of testword0clock_i     : signal is true; 
+
+  attribute syn_keep of clk_100_i : signal is true;
+  attribute syn_keep of clk_200_i : signal is true;
+  attribute syn_keep of clk_160_i : signal is true;
+  attribute syn_keep of clk_160div3_i : signal is true;
+  
+  attribute syn_keep of clk_80_i : signal is true;
+  attribute syn_keep of clk_SODA100_i : signal is true;
+  attribute syn_keep of clk_SODA200_i : signal is true;
+
+  attribute syn_preserve of clk_100_i : signal is true;
+  attribute syn_preserve of clk_200_i : signal is true;
+  attribute syn_preserve of clk_160_i : signal is true;
+  attribute syn_preserve of clk_160div3_i : signal is true;
+  attribute syn_preserve of clk_80_i : signal is true;
+  attribute syn_preserve of clk_SODA100_i : signal is true;
+  attribute syn_preserve of clk_SODA200_i : signal is true;
+
+  type debug_superbursts_type is array(7 downto 0) of std_logic_vector(7 downto 0);
+  signal debug_nextsuperburst_S   : std_logic := '0';
+  signal debug_counter_S          : integer := 0;
+  signal debug_superburst_error_S : std_logic := '0';
+  signal debug_emptypacket_S      : std_logic := '0';
+  signal debug_superburst_S       : std_logic_vector(30 downto 0);
+  signal debug_superbursts_S      : debug_superbursts_type := (others => (others => '0'));
+  signal debug_nrofbytes_S        : std_logic_vector(15 downto 0);
+ 
+			
+  attribute syn_keep of debug_nextsuperburst_S : signal is true;
+  attribute syn_keep of debug_counter_S : signal is true;
+  attribute syn_keep of debug_superburst_S : signal is true;
+  attribute syn_keep of debug_superburst_error_S : signal is true;
+  attribute syn_keep of debug_emptypacket_S : signal is true;
+  attribute syn_keep of data64b_muxed_error_S : signal is true;
+  attribute syn_keep of data64b_muxed_busy_S : signal is true;
+  attribute syn_keep of debug_nrofbytes_S : signal is true;
+  attribute syn_preserve of debug_nextsuperburst_S : signal is true;
+  attribute syn_preserve of debug_counter_S : signal is true;
+  attribute syn_preserve of debug_superburst_S : signal is true;
+  attribute syn_preserve of debug_superburst_error_S : signal is true;
+  attribute syn_preserve of debug_emptypacket_S : signal is true;
+  attribute syn_preserve of data64b_muxed_error_S : signal is true;
+  attribute syn_preserve of data64b_muxed_busy_S : signal is true;
+  attribute syn_preserve of debug_nrofbytes_S : signal is true;
+
+  attribute syn_keep of SODA_clock_rx : signal is true;
+  attribute syn_preserve of SODA_clock_rx : signal is true;
+
+				
+begin
+
+
+
+
+---------------------------------------------------------------------------
+-- Reset Generation
+---------------------------------------------------------------------------
+
+  GSR_N <= pll_lock;
+
+  THE_RESET_HANDLER : trb_net_reset_handler
+    generic map(
+      RESET_DELAY => x"FEEE"
+      )
+    port map(
+      CLEAR_IN      => '0',              -- reset input (high active, async)
+      CLEAR_N_IN    => '1',              -- reset input (low active, async)
+      CLK_IN        => clk_200_i,        -- raw master clock, NOT from PLL/DLL!
+      SYSCLK_IN     => clk_100_i,        -- PLL/DLL remastered clock
+      PLL_LOCKED_IN => pll_lock,         -- master PLL lock signal (async)
+      RESET_IN      => '0',              -- general reset signal (SYSCLK)
+      TRB_RESET_IN  => med_stat_op(13),  -- TRBnet reset signal (SYSCLK)
+      CLEAR_OUT     => clear_i,          -- async reset out, USE WITH CARE!
+      RESET_OUT     => reset_i,          -- synchronous reset out (SYSCLK)
+      DEBUG_OUT     => open
+      );  
+
+---------------------------------------------------------------------------
+-- Clock Handling
+---------------------------------------------------------------------------
+
+  THE_MAIN_PLL : pll_in200_out100
+    port map(
+      CLK   => CLK_GPLL_RIGHT,
+      CLKOP => clk_100_i,
+      CLKOK => clk_200_i,
+      LOCK  => pll_lock
+      );
+	  
+ THE_SODA_CLOCK : pll_in200_out200M_100M 
+   port map(
+		CLK => CLK_GPLL_RIGHT,
+		CLKOP => clk_SODA100_i,
+		CLKOS => clk_SODA200_i,
+		LOCK => open);
+--	SODA_clock <= clk_SODA200_i;
+	SODAdiv2_clock <= clk_SODA100_i;
+
+ THE_CLOCK80 : pll_in100_out80M 
+    port map(
+		CLK => clk_100_i,
+		CLKOP => clk_160_i, -- 160MHz
+		CLKOK => clk_80_i, -- 80MHz
+		CLKOK2 => clk_160div3_i, -- 160/3MHz
+		LOCK => open);
+	PACKETIN_clock <= clk_160div3_i;
+	MUX_clock <= clk_100_i;
+	PACKETOUT_clock <= clk_80_i;
+
+---------------------------------------------------------------------------
+-- The TrbNet media interface (to other FPGA)
+---------------------------------------------------------------------------
+  THE_MEDIA_UPLINK : trb_net16_med_1_2sync_3_ecp3_sfp
+    port map(
+      CLK                => clk_200_i,
+      SYSCLK             => clk_100_i,
+      RESET              => reset_i,
+      CLEAR              => clear_i,
+      CLK_EN             => '1',
+      --Internal Connection
+      MED_DATA_IN        => med_data_out,
+      MED_PACKET_NUM_IN  => med_packet_num_out,
+      MED_DATAREADY_IN   => med_dataready_out,
+      MED_READ_OUT       => med_read_in,
+      MED_DATA_OUT       => med_data_in,
+      MED_PACKET_NUM_OUT => med_packet_num_in,
+      MED_DATAREADY_OUT  => med_dataready_in,
+      MED_READ_IN        => med_read_out,
+      REFCLK2CORE_OUT    => open,
+      --SFP Connection
+      SD_RXD_P_IN        => SERDES_INT_RX(2),
+      SD_RXD_N_IN        => SERDES_INT_RX(3),
+      SD_TXD_P_OUT       => SERDES_INT_TX(2),
+      SD_TXD_N_OUT       => SERDES_INT_TX(3),
+      SD_REFCLK_P_IN     => '0',
+      SD_REFCLK_N_IN     => '1',
+      SD_PRSNT_N_IN      => FPGA5_COMM(0),
+      SD_LOS_IN          => FPGA5_COMM(0),
+      SD_TXDIS_OUT       => FPGA5_COMM(2),
+	-- SODA serdes channel
+      SODA_RXD_P_IN      => SERDES_ADDON_RX(8),
+      SODA_RXD_N_IN      => SERDES_ADDON_RX(9),
+      SODA_TXD_P_OUT     => SERDES_ADDON_TX(8),
+      SODA_TXD_N_OUT     => SERDES_ADDON_TX(9),
+      SODA_DLM_IN        => TXtop_DLM_S,
+      SODA_DLM_WORD_IN   => TXtop_DLM_word_S,
+      SODA_DLM_OUT       => ext_sodasrc_TX_DLM_S,
+      SODA_DLM_WORD_OUT  => ext_sodasrc_TX_DLM_WORD_S,
+      SODA_CLOCK_OUT     => SODA_clock_rx,
+      -- Connection to addon interface
+      DOUT_TXD_P_OUT     => SERDES_ADDON_TX(10),
+      DOUT_TXD_N_OUT     => SERDES_ADDON_TX(11),
+      SFP_MOD0_5         => SFP_MOD0(5),
+      SFP_MOD0_3         => SFP_MOD0(3),
+      SFP_LOS_5          => SFP_LOS(5),
+      SFP_LOS_3          => SFP_LOS(3),
+      TX_READY_CH3       => tx_ready_ch3,
+      TX_DATA_CH3        => tx_data_ch3,
+      TX_K_CH3           => tx_k_ch3,
+	  -- Status and control port
+      STAT_OP            => med_stat_op,
+      CTRL_OP            => med_ctrl_op,
+      STAT_DEBUG         => med_stat_debug,
+      CTRL_DEBUG         => (others => '0')
+      );
+
+dataconversion_for_serdes_inst : dataconversion_for_serdes
+	port map (
+		DATA_CLK         => PACKETOUT_clock,
+		CLK              => clk_100_i,
+		RESET            => reset_i,
+		TX_READY         => tx_ready_ch3,
+		SFP_MOD0         => SFP_MOD0(3),
+		SFP_LOS          => SFP_LOS(3),
+		TX_DATA          => tx_data_ch3,
+		TX_K             => tx_k_ch3,
+		DATA_IN_ALLOWED  => data64b_muxed_allowed,
+		DATA_IN          => data64b_muxed,
+		DATA_IN_WRITE    => data64b_muxed_write,
+		DATA_IN_FIRST    => data64b_muxed_first,
+		DATA_IN_LAST     => data64b_muxed_last,
+		DATA_IN_ERROR    => data64b_muxed_error
+	);
+
+data64b_muxed_allowed_S <= '1' when (data64b_muxed_allowed='1') and (data64b_muxed_allowed0_S='1') else '0';
+
+process(PACKETOUT_clock)
+constant MINCLOCKSBETWEENPACKETS : integer := ADCCLOCKFREQUENCY/500000; -- 2048;
+variable counting : boolean := FALSE;
+variable counterpacket : integer range 0 to 65535 := 0;
+variable counterwait : integer range 0 to 65535 := 0;
+begin
+	if (rising_edge(PACKETOUT_clock)) then
+		data64b_muxed_error_S <= '0';
+		if (data64b_muxed_write='1') and (data64b_muxed_last='1') then
+			data64b_muxed_allowed0_S <= '0';
+			counterwait := counterpacket;
+		elsif counterwait<MINCLOCKSBETWEENPACKETS then
+			data64b_muxed_allowed0_S <= '0';
+			counterwait := counterwait+1;
+		else
+			data64b_muxed_allowed0_S <= data64b_muxed_allowed;
+		end if;
+		if (data64b_muxed_write='1') and (data64b_muxed_first='1') then
+			counting := TRUE;
+			counterpacket := 0;
+		elsif (data64b_muxed_write='1') and (data64b_muxed_last='1') then
+			counting := FALSE;
+		else
+			if (counting) and (counterpacket<65535) then
+				counterpacket := counterpacket+1;
+			end if;
+		end if;
+		if (data64b_muxed_write='1') then
+			if (data64b_muxed_first='1') and (data64b_muxed_last='1') then
+				data64b_muxed_error_S <= '1';
+			elsif data64b_muxed_first='1' then
+				if data64b_muxed_busy_S='1' then
+					data64b_muxed_error_S <= '1';
+				end if;
+				data64b_muxed_busy_S <= '1';
+			elsif data64b_muxed_last='1' then
+				if data64b_muxed_busy_S='0' then
+					data64b_muxed_error_S <= '1';
+				end if;
+				data64b_muxed_busy_S <= '0';
+			else
+			end if;
+		end if;
+	end if;
+end process;
+
+process(PACKETOUT_clock)
+begin
+	if (rising_edge(PACKETOUT_clock)) then
+		debug_nextsuperburst_S <= '0';
+		debug_superburst_error_S <= '0';
+		if data64b_muxed_write='1' then
+			if data64b_muxed_first='1' then
+				debug_counter_S <= 0;
+				if data64b_muxed(47 downto 32) = conv_std_logic_vector(16,16) then
+					debug_emptypacket_S <= '1';
+				else
+					debug_emptypacket_S <= '0';
+				end if;
+				debug_nrofbytes_S <= data64b_muxed(47 downto 32);
+			elsif debug_counter_S=0 then
+				if data64b_muxed(63)='0' then -- pulse data
+					if (debug_superburst_S+1) /= data64b_muxed(30 downto 0) then
+						debug_superburst_error_S <= '1';
+					end if;
+					debug_nextsuperburst_S <= '1';
+					debug_superburst_S <= data64b_muxed(30 downto 0);
+					for i in 1 to 7 loop
+						debug_superbursts_S(i) <= debug_superbursts_S(i-1);
+					end loop;
+					debug_superbursts_S(0) <= data64b_muxed(7 downto 0);
+				end if;
+				if data64b_muxed_last='1' then
+					if debug_nrofbytes_S /= conv_std_logic_vector((debug_counter_S+2)*8,16) then
+						debug_superburst_error_S <= '1';
+					end if;
+				end if;
+				debug_counter_S <= debug_counter_S+1;
+			elsif data64b_muxed_last='1' then
+				if debug_nrofbytes_S /= conv_std_logic_vector((debug_counter_S+2)*8,16) then
+					debug_superburst_error_S <= '1';
+				end if;
+				debug_counter_S <= debug_counter_S+1;
+			else
+				debug_counter_S <= debug_counter_S+1;
+			end if;
+		end if;
+	end if;
+end process;
+
+    
+---------------------------------------------------------------------------
+-- Endpoint
+---------------------------------------------------------------------------
+
+ THE_ENDPOINT : trb_net16_endpoint_data_concentrator_handler -- trb_net16_endpoint_hades_full_handler
+   generic map(
+     REGIO_NUM_STAT_REGS       => REGIO_NUM_STAT_REGS,  --4,    --16 stat reg
+     REGIO_NUM_CTRL_REGS       => REGIO_NUM_CTRL_REGS,  --3,    --8 cotrol reg
+     ADDRESS_MASK              => x"FFFF",
+     BROADCAST_BITMASK         => x"FF",
+     BROADCAST_SPECIAL_ADDR    => x"45",
+     REGIO_COMPILE_TIME        => conv_std_logic_vector(VERSION_NUMBER_TIME, 32),
+     REGIO_HARDWARE_VERSION    => x"91000001",
+     REGIO_INIT_ADDRESS        => x"f300",
+     REGIO_USE_VAR_ENDPOINT_ID => c_YES,
+     CLOCK_FREQUENCY           => 125,
+     TIMING_TRIGGER_RAW        => c_YES,
+     --Configure data handler
+     DATA_INTERFACE_NUMBER     => 1,
+     DATA_BUFFER_DEPTH         => 13,         --13
+     DATA_BUFFER_WIDTH         => 32,
+     DATA_BUFFER_FULL_THRESH   => 2**13-800,  --2**13-1024
+     TRG_RELEASE_AFTER_DATA    => c_YES,
+     HEADER_BUFFER_DEPTH       => 9,
+     HEADER_BUFFER_FULL_THRESH => 2**9-16
+     )
+   port map(
+     CLK                => clk_100_i,
+     RESET              => reset_i,
+     CLK_EN             => '1',
+     MED_DATAREADY_OUT  => med_dataready_out,  -- open, --
+     MED_DATA_OUT       => med_data_out,  -- open, --
+     MED_PACKET_NUM_OUT => med_packet_num_out,  -- open, --
+     MED_READ_IN        => med_read_in,
+     MED_DATAREADY_IN   => med_dataready_in,
+     MED_DATA_IN        => med_data_in,
+     MED_PACKET_NUM_IN  => med_packet_num_in,
+     MED_READ_OUT       => med_read_out,  -- open, --
+     MED_STAT_OP_IN     => med_stat_op,
+     MED_CTRL_OP_OUT    => med_ctrl_op,
+
+     --Timing trigger in
+     TRG_TIMING_TRG_RECEIVED_IN  => timing_trg_received_i,
+     --LVL1 trigger to FEE
+     LVL1_TRG_DATA_VALID_OUT     => trg_data_valid_i,
+     LVL1_VALID_TIMING_TRG_OUT   => trg_timing_valid_i,
+     LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i,
+     LVL1_INVALID_TRG_OUT        => trg_invalid_i,
+
+     LVL1_TRG_TYPE_OUT        => trg_type_i,
+     LVL1_TRG_NUMBER_OUT      => trg_number_i,
+     LVL1_TRG_CODE_OUT        => trg_code_i,
+     LVL1_TRG_INFORMATION_OUT => trg_information_i,
+     LVL1_INT_TRG_NUMBER_OUT  => trg_int_number_i,
+
+     --Information about trigger handler errors
+     TRG_MULTIPLE_TRG_OUT         => trg_multiple_trg_i,
+     TRG_TIMEOUT_DETECTED_OUT     => trg_timeout_detected_i,
+     TRG_SPURIOUS_TRG_OUT         => trg_spurious_trg_i,
+     TRG_MISSING_TMG_TRG_OUT      => trg_missing_tmg_trg_i,
+     TRG_SPIKE_DETECTED_OUT       => trg_spike_detected_i,
+     
+     --Response from FEE
+     FEE_TRG_RELEASE_IN(0)       => fee_trg_release_i,
+     FEE_TRG_STATUSBITS_IN       => fee_trg_statusbits_i,
+     FEE_DATA_IN                 => fee_data_i,
+     FEE_DATA_WRITE_IN(0)        => fee_data_write_i,
+     FEE_DATA_FINISHED_IN(0)     => fee_data_finished_i,
+     FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i,
+
+     -- Slow Control Data Port
+     REGIO_COMMON_STAT_REG_IN           => common_stat_reg,  --0x00
+     REGIO_COMMON_CTRL_REG_OUT          => common_ctrl_reg,  --0x20
+     REGIO_COMMON_STAT_STROBE_OUT       => common_stat_reg_strobe,
+     REGIO_COMMON_CTRL_STROBE_OUT       => common_ctrl_reg_strobe,
+     REGIO_STAT_REG_IN                  => stat_reg,         --start 0x80
+     REGIO_CTRL_REG_OUT                 => ctrl_reg,         --start 0xc0
+     REGIO_STAT_STROBE_OUT              => stat_reg_strobe,
+     REGIO_CTRL_STROBE_OUT              => ctrl_reg_strobe,
+     REGIO_VAR_ENDPOINT_ID(1 downto 0)  => CODE_LINE,
+     REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
+
+     BUS_ADDR_OUT         => regio_addr_out,
+     BUS_READ_ENABLE_OUT  => regio_read_enable_out,
+     BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
+     BUS_DATA_OUT         => regio_data_out,
+     BUS_DATA_IN          => regio_data_in,
+     BUS_DATAREADY_IN     => regio_dataready_in,
+     BUS_NO_MORE_DATA_IN  => regio_no_more_data_in,
+     BUS_WRITE_ACK_IN     => regio_write_ack_in,
+     BUS_UNKNOWN_ADDR_IN  => regio_unknown_addr_in,
+     BUS_TIMEOUT_OUT      => regio_timeout_out,
+     ONEWIRE_INOUT        => TEMPSENS,
+     ONEWIRE_MONITOR_OUT  => open,
+
+     TIME_GLOBAL_OUT         => global_time,
+     TIME_LOCAL_OUT          => local_time,
+     TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
+     TIME_TICKS_OUT          => timer_ticks,
+
+     STAT_DEBUG_IPU              => open,
+     STAT_DEBUG_1                => open,
+     STAT_DEBUG_2                => open,
+     STAT_DEBUG_DATA_HANDLER_OUT => open,
+     STAT_DEBUG_IPU_HANDLER_OUT  => open,
+     STAT_TRIGGER_OUT            => open,
+     CTRL_MPLEX                  => (others => '0'),
+     IOBUF_CTRL_GEN              => (others => '0'),
+     STAT_ONEWIRE                => open,
+     STAT_ADDR_DEBUG             => open,
+     DEBUG_LVL1_HANDLER_OUT      => open
+     );
+
+
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+ THE_BUS_HANDLER : trb_net16_regio_bus_handler
+   generic map(
+     PORT_NUMBER    => 5,
+     PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"e000", 3 => x"e100", 4 => x"e200", others => x"0000"),
+     PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 2, 3 => 4, 4 => 4, others => 0)
+--     PORT_MASK_ENABLE => 0
+     )
+   port map(
+     CLK   => clk_100_i,
+     RESET => reset_i,
+
+     DAT_ADDR_IN          => regio_addr_out,
+     DAT_DATA_IN          => regio_data_out,
+     DAT_DATA_OUT         => regio_data_in,
+     DAT_READ_ENABLE_IN   => regio_read_enable_out,
+     DAT_WRITE_ENABLE_IN  => regio_write_enable_out,
+     DAT_TIMEOUT_IN       => regio_timeout_out,
+     DAT_DATAREADY_OUT    => regio_dataready_in,
+     DAT_WRITE_ACK_OUT    => regio_write_ack_in,
+     DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
+     DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
+		
+     BUS_READ_ENABLE_OUT(0)              => spictrl_read_en,
+     BUS_READ_ENABLE_OUT(1)              => spimem_read_en,
+     BUS_READ_ENABLE_OUT(2)              => dc_read_en,
+     BUS_READ_ENABLE_OUT(3)              => soda_read_en,
+     BUS_READ_ENABLE_OUT(4)              => sodasrc_read_en,
+     BUS_WRITE_ENABLE_OUT(0)             => spictrl_write_en,
+     BUS_WRITE_ENABLE_OUT(1)             => spimem_write_en,
+     BUS_WRITE_ENABLE_OUT(2)             => dc_write_en,
+     BUS_WRITE_ENABLE_OUT(3)             => soda_write_en,
+     BUS_WRITE_ENABLE_OUT(4)             => sodasrc_write_en,
+     BUS_DATA_OUT(0*32+31 downto 0*32)   => spictrl_data_in,
+     BUS_DATA_OUT(1*32+31 downto 1*32)   => spimem_data_in,
+     BUS_DATA_OUT(2*32+31 downto 2*32)   => dc_data_in,
+     BUS_DATA_OUT(3*32+31 downto 3*32)   => soda_data_in,
+     BUS_DATA_OUT(4*32+31 downto 4*32)   => sodasrc_data_in,
+     BUS_ADDR_OUT(0*16)                  => spictrl_addr,
+     BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,
+     BUS_ADDR_OUT(1*16+5 downto 1*16)    => spimem_addr,
+     BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
+     BUS_ADDR_OUT(2*16+1 downto 2*16)    => dc_addr,
+     BUS_ADDR_OUT(2*16+15 downto 2*16+2) => open,
+     BUS_ADDR_OUT(3*16+3 downto 3*16)    => soda_addr,
+     BUS_ADDR_OUT(3*16+15 downto 3*16+4) => open,
+     BUS_ADDR_OUT(4*16+3 downto 4*16)    => sodasrc_addr,
+     BUS_ADDR_OUT(4*16+15 downto 4*16+4) => open,
+     BUS_DATA_IN(0*32+31 downto 0*32)    => spictrl_data_out,
+     BUS_DATA_IN(1*32+31 downto 1*32)    => spimem_data_out,
+     BUS_DATA_IN(2*32+31 downto 2*32)    => dc_data_out,
+     BUS_DATA_IN(3*32+31 downto 3*32)    => soda_data_out,
+     BUS_DATA_IN(4*32+31 downto 4*32)    => sodasrc_data_out,
+     BUS_DATAREADY_IN(0)                 => spictrl_ack,
+     BUS_DATAREADY_IN(1)                 => spimem_ack,
+     BUS_DATAREADY_IN(2)                 => dc_ack,
+     BUS_DATAREADY_IN(3)                 => soda_ack,
+     BUS_DATAREADY_IN(4)                 => sodasrc_ack,
+     BUS_WRITE_ACK_IN(0)                 => spictrl_ack,
+     BUS_WRITE_ACK_IN(1)                 => spimem_ack,
+     BUS_WRITE_ACK_IN(2)                 => dc_ack,
+     BUS_WRITE_ACK_IN(3)                 => soda_ack,
+     BUS_WRITE_ACK_IN(4)                 => sodasrc_ack,
+     BUS_NO_MORE_DATA_IN(0)              => spictrl_busy,
+     BUS_NO_MORE_DATA_IN(1)              => '0',
+     BUS_NO_MORE_DATA_IN(2)              => dc_busy,
+     BUS_NO_MORE_DATA_IN(3)              => '0',
+     BUS_NO_MORE_DATA_IN(4)              => '0',
+     BUS_UNKNOWN_ADDR_IN(0)              => '0',
+     BUS_UNKNOWN_ADDR_IN(1)              => '0',
+     BUS_UNKNOWN_ADDR_IN(2)              => '0',
+     BUS_UNKNOWN_ADDR_IN(3)              => '0',
+     BUS_UNKNOWN_ADDR_IN(4)              => '0',
+     BUS_TIMEOUT_OUT(0)                  => open,
+     BUS_TIMEOUT_OUT(1)                  => open,
+     BUS_TIMEOUT_OUT(2)                  => open,
+     BUS_TIMEOUT_OUT(3)                  => open,
+     BUS_TIMEOUT_OUT(4)                  => open,
+
+     --Bus Handler (SPI CTRL)
+     --Bus Handler (SPI Memory)
+     --Bus Handler (test port)
+
+     STAT_DEBUG => open
+     );
+
+---------------------------------------------------------------------------
+-- SPI / Flash
+---------------------------------------------------------------------------
+
+ THE_SPI_MASTER : spi_master
+   port map(
+     CLK_IN         => clk_100_i,
+     RESET_IN       => reset_i,
+     -- Slave bus
+     BUS_READ_IN    => spictrl_read_en,
+     BUS_WRITE_IN   => spictrl_write_en,
+     BUS_BUSY_OUT   => spictrl_busy,
+     BUS_ACK_OUT    => spictrl_ack,
+     BUS_ADDR_IN(0) => spictrl_addr,
+     BUS_DATA_IN    => spictrl_data_in,
+     BUS_DATA_OUT   => spictrl_data_out,
+     -- SPI connections
+     SPI_CS_OUT     => FLASH_CS,
+     SPI_SDI_IN     => FLASH_DOUT,
+     SPI_SDO_OUT    => FLASH_DIN,
+     SPI_SCK_OUT    => FLASH_CLK,
+     -- BRAM for read/write data
+     BRAM_A_OUT     => spi_bram_addr,
+     BRAM_WR_D_IN   => spi_bram_wr_d,
+     BRAM_RD_D_OUT  => spi_bram_rd_d,
+     BRAM_WE_OUT    => spi_bram_we,
+     -- Status lines
+     STAT           => open
+     );
+
+-- data memory for SPI accesses
+ THE_SPI_MEMORY : spi_databus_memory
+   port map(
+     CLK_IN        => clk_100_i,
+     RESET_IN      => reset_i,
+     -- Slave bus
+     BUS_ADDR_IN   => spimem_addr,
+     BUS_READ_IN   => spimem_read_en,
+     BUS_WRITE_IN  => spimem_write_en,
+     BUS_ACK_OUT   => spimem_ack,
+     BUS_DATA_IN   => spimem_data_in,
+     BUS_DATA_OUT  => spimem_data_out,
+     -- state machine connections
+     BRAM_ADDR_IN  => spi_bram_addr,
+     BRAM_WR_D_OUT => spi_bram_wr_d,
+     BRAM_RD_D_IN  => spi_bram_rd_d,
+     BRAM_WE_IN    => spi_bram_we,
+     -- Status lines
+     STAT          => open
+     );
+
+
+---------------------------------------------------------------------------
+-- Reboot FPGA
+---------------------------------------------------------------------------
+  THE_FPGA_REBOOT : fpga_reboot
+    port map(
+      CLK       => clk_100_i,
+      RESET     => reset_i,
+      DO_REBOOT => common_ctrl_reg(15),
+      PROGRAMN  => PROGRAMN
+      );
+
+
+
+	
+MUX_checkwave_all: for i in 1 to 6 generate
+	SFP_TXDIS(i) <= reset_i;
+--   SFP_MOD0 -- 0= sfp present?
+--LED_LINKOK : out std_logic_vector(6 downto 1);
+--LED_RX     : out std_logic_vector(6 downto 1); 
+--LED_TX     : out std_logic_vector(6 downto 1);
+end generate;	
+
+THE_DATACONCENTRATOR: DC_module_TRB3 port map(
+		slowcontrol_clock  => clk_100_i,
+		packet_in_clock => PACKETIN_clock,
+		MUX_clock  => MUX_clock,
+		packet_out_clock => PACKETOUT_clock,
+		SODA_clock => SODA_clock,
+		reset => reset_i,
+
+		-- Slave bus
+		BUS_READ_IN => dc_read_en,
+		BUS_WRITE_IN => dc_write_en,
+		BUS_BUSY_OUT => dc_busy,
+		BUS_ACK_OUT => dc_ack,
+		BUS_ADDR_IN => dc_addr,
+		BUS_DATA_IN => dc_data_in,
+		BUS_DATA_OUT => dc_data_out,
+
+		-- fiber interface signals:
+		gtpClk => SODA_clock,
+		gtpClkDiv2 => SODAdiv2_clock,
+		refClkOut => open,
+		refClk_OK => open,
+		gtpLOS(0) => SFP_LOS(1), --??
+		gtpLOS(1) => SFP_LOS(6), --??
+		gtpLOS(2) => SFP_LOS(2), --??
+		gtpLOS(3) => SFP_LOS(4), --??
+		gtpTxP0(0) => SERDES_ADDON_TX(0), 
+		gtpTxP0(1) => SERDES_ADDON_TX(2), 
+		gtpTxP0(2) => SERDES_ADDON_TX(4), 
+		gtpTxP0(3) => SERDES_ADDON_TX(6), 
+		gtpTxN0(0) => SERDES_ADDON_TX(1), 
+		gtpTxN0(1) => SERDES_ADDON_TX(3), 
+		gtpTxN0(2) => SERDES_ADDON_TX(5), 
+		gtpTxN0(3) => SERDES_ADDON_TX(7), 
+		gtpRxP0(0) => SERDES_ADDON_RX(0), 
+		gtpRxP0(1) => SERDES_ADDON_RX(2), 
+		gtpRxP0(2) => SERDES_ADDON_RX(4), 
+		gtpRxP0(3) => SERDES_ADDON_RX(6), 
+		gtpRxN0(0) => SERDES_ADDON_RX(1), 
+		gtpRxN0(1) => SERDES_ADDON_RX(3), 
+		gtpRxN0(2) => SERDES_ADDON_RX(5), 
+		gtpRxN0(3) => SERDES_ADDON_RX(7), 
+
+-- 64 bits data output
+		data_out_allowed => data64b_muxed_allowed_S, 
+		data_out         => data64b_muxed,        
+		data_out_write   => data64b_muxed_write, 
+		data_out_first   => data64b_muxed_first,
+		data_out_last    => data64b_muxed_last, 
+		data_out_error   => data64b_muxed_error,   
+
+-- SODA signals
+		TX_DLM => TXfee_DLM_S,
+		TX_DLM_WORD => TXfee_DLM_word_S,
+		RX_DLM => RXfee_DLM_S,
+		RX_DLM_WORD => RXfee_DLM_word_S,
+		EnableExternalSODA => EnableExternalSODA_S,
+		
+		--Control Interface
+		--		SCI_DATA_IN             : in  std_logic_vector(7 downto 0) := (others => '0');
+		--		SCI_DATA_OUT            : out std_logic_vector(7 downto 0) := (others => '0');
+		--		SCI_ADDR                : in  std_logic_vector(8 downto 0) := (others => '0');
+		--		SCI_READ                : in  std_logic := '0';
+		--		SCI_WRITE               : in  std_logic := '0';
+		--		SCI_ACK                 : out std_logic := '0';
+		--		SCI_NACK                : out std_logic := '0';
+
+		-- testpoints
+		txpll_clocks => txpll_clocks_S, 
+		LEDs_link_ok => LEDs_link_ok_i,
+		LEDs_rx => LEDs_rx_i,
+		LEDs_tx => LEDs_tx_i,
+		testword0 => open,
+		testword0clock => testword0clock_i,
+		testword1 => open,
+		testword2 => open
+		);
+
+
+TEST_LINE(15 downto 0) <= (OTHERS => '0');
+
+
+generate_DLM_signals: for i in 0 to NROFFIBERS-1 generate -- change from to --> downto
+	TXfee_DLM_S(i) <= TXBTM_DLM_S(i);
+	TXfee_DLM_word_S(i) <= TXBTM_DLM_WORD_S(i);
+	RXBTM_DLM_S(i) <= RXfee_DLM_S(i);
+	RXBTM_DLM_WORD_S(i) <= RXfee_DLM_word_S(i); 
+end generate;
+
+-- soda_hub1: soda_hub 
+	-- generic map (
+		-- SODA_16BIT_INTERFACE => false
+	-- )
+	-- port map(
+		-- SYSCLK => clk_100_i,
+		-- SODACLK => SODA_clock,
+		-- RESET => reset_i,
+		-- CLEAR => '0',
+		-- CLK_EN => '1',
+	-- --	SINGLE DUBPLEX LINK TO THE TOP
+		-- RXTOP_DLM_IN => RXtop_DLM_S,
+		-- RXTOP_DLM_WORD_IN => RXtop_DLM_word_S,
+		-- TXTOP_DLM_OUT => TXtop_DLM_S,
+		-- TXTOP_DLM_WORD_OUT => TXtop_DLM_word_S,
+	-- --	MULTIPLE DUPLEX LINKS TO THE BOTTOM
+		-- RXBTM_DLM_IN => RXBTM_DLM_S,
+		-- RXBTM_DLM_WORD_IN => RXBTM_DLM_WORD_S,
+		-- TXBTM_DLM_OUT => TXBTM_DLM_S,
+		-- TXBTM_DLM_WORD_OUT => TXBTM_DLM_WORD_S,
+
+		-- SODA_DATA_IN => soda_data_in,
+		-- SODA_DATA_OUT => soda_data_out,
+		-- SODA_ADDR_IN => soda_addr,
+		-- SODA_READ_IN => soda_read_en,
+		-- SODA_WRITE_IN => soda_write_en,
+		-- SODA_ACK_OUT => soda_ack,
+		-- STAT => open
+	-- );
+ generate_DLM_hub: for i in 0 to NROFFIBERS-1 generate -- change from to --> downto
+	 TXBTM_DLM_S(i) <= RXtop_DLM_S;
+	 TXBTM_DLM_WORD_S(i) <= RXtop_DLM_word_S;
+ end generate;
+	 TXtop_DLM_S <= RXBTM_DLM_S(0);
+	 TXtop_DLM_word_S <= RXBTM_DLM_WORD_S(0); 
+
+RXtop_DLM_S <= ext_sodasrc_TX_DLM_S when EnableExternalSODA_S='1' else sodasrc_TX_DLM_S;
+RXtop_DLM_word_S <= ext_sodasrc_TX_DLM_word_S when EnableExternalSODA_S='1' else sodasrc_TX_DLM_word_S;
+
+SODAclockswitch: dcs
+-- synthesis translate_off
+	generic map (
+		DCSMODE => "POS")
+-- synthesis translate_on
+	port map (
+        clk0 => clk_SODA200_i,
+        clk1 => SODA_clock_rx,
+        sel => EnableExternalSODA_S,
+        dcsout => SODA_clock);
+
+soda_source1: soda_source 
+	generic map (
+		SODA_16BIT_INTERFACE => false
+	)
+	port map(
+		SYSCLK => clk_100_i,
+		SODACLK => SODA_clock,
+		RESET => reset_i,
+		CLEAR => '0',
+		CLK_EN => '1',
+		--Internal Connection
+		SODA_BURST_PULSE_IN	=> SODA_burst_pulse_S,
+
+		RX_DLM_WORD_IN => TXtop_DLM_word_S,
+		RX_DLM_IN => TXtop_DLM_S,
+		TX_DLM_OUT => sodasrc_TX_DLM_S,
+		TX_DLM_WORD_OUT => sodasrc_TX_DLM_word_S,
+
+		SODA_DATA_IN => sodasrc_data_in,
+		SODA_DATA_OUT => sodasrc_data_out,
+		SODA_ADDR_IN => sodasrc_addr,
+		SODA_READ_IN => sodasrc_read_en,
+		SODA_WRITE_IN => sodasrc_write_en,
+		SODA_ACK_OUT => sodasrc_ack,
+
+		LEDS_OUT => open
+	);
+
+soda_start_of_burst_faker1: soda_start_of_burst_faker 
+	generic map (
+		cCLOCK_PERIOD => 5, -- clock-period in ns
+		cBURST_PERIOD => 2400 -- burst-period in ns
+		)
+	port map(
+		SYSCLK => SODA_clock,
+		RESET => reset_i,
+		SODA_BURST_PULSE_OUT => SODA_burst_pulse_S
+	);
+
+		
+LED_LINKOK(1) <= not LEDs_link_ok_i(0);
+LED_LINKOK(6) <= not LEDs_link_ok_i(1);
+LED_LINKOK(2) <= not LEDs_link_ok_i(2);
+LED_LINKOK(4) <= not LEDs_link_ok_i(3);
+LED_LINKOK(3) <= '1';
+LED_LINKOK(5) <= '1';
+
+LED_RX(1) <= not LEDs_rx_i(0);
+LED_RX(6) <= not LEDs_rx_i(1);
+LED_RX(2) <= not LEDs_rx_i(2);
+LED_RX(4) <= not LEDs_rx_i(3);
+LED_RX(3) <= '1';
+LED_RX(5) <= '1';
+
+LED_TX(1) <= not LEDs_tx_i(0);
+LED_TX(6) <= not LEDs_tx_i(1);
+LED_TX(2) <= not LEDs_tx_i(2);
+LED_TX(4) <= not LEDs_tx_i(3);
+LED_TX(3) <= '1';
+LED_TX(5) <= '1';
+
+-- LED_TX(5) <= '1' when debug_superburst_S/=data64b_muxed(50 downto 20) else '0';
+-- TEST_LINE <= debug_superburst_S(15 downto 0) when data64b_muxed(40)='1' else '1' & debug_superburst_S(30 downto 16);
+
+--process(SODA_clock)
+--begin
+	--if rising_edge(SODA_clock) then
+		--if test_LEDs_active_i='0' then LED_ORANGE <= not med_stat_op(10); else LED_ORANGE <= test_LEDs(1); end if;
+		--if test_LEDs_active_i='0' then LED_GREEN  <= not med_stat_op(9); else LED_GREEN  <= test_LEDs(0); end if;
+		--if test_LEDs_active_i='0' then LED_RED    <= not time_counter(26); else LED_RED    <= test_LEDs(2); end if;
+		--LED_YELLOW <= test_LEDs(3); ---- not med_stat_op(11);
+	--end if;
+--end process;
+		--LED_ORANGE <= not med_stat_op(10) when test_LEDs_active_i='0' else test_LEDs(1);
+		--LED_GREEN  <= not med_stat_op(9) when test_LEDs_active_i='0' else test_LEDs(0);
+		--LED_RED    <= not time_counter(26) when test_LEDs_active_i='0' else test_LEDs(2);
+		--LED_YELLOW <= test_LEDs(3); ---- not med_stat_op(11);
+
+  
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+LED_GREEN  <= not med_stat_op(9);
+LED_ORANGE <= not med_stat_op(10);
+LED_RED    <= not time_counter(26);
+LED_YELLOW <= not med_stat_op(11);
+
+
+---------------------------------------------------------------------------
+-- Test Connector
+---------------------------------------------------------------------------    
+  --TEST_LINE(7 downto 0)   <= med_data_in(7 downto 0);
+  --TEST_LINE(8)            <= med_dataready_in;
+  --TEST_LINE(9)            <= med_dataready_out;
+  --TEST_LINE(10)           <= stat_reg_strobe(0);
+  --TEST_LINE(15 downto 11) <= (others => '0');
+
+
+---------------------------------------------------------------------------
+-- Test Circuits
+---------------------------------------------------------------------------
+process
+  begin
+    wait until rising_edge(clk_100_i);
+    time_counter <= time_counter + 1;
+  end process;
+
+end architecture;
\ No newline at end of file
diff --git a/data_concentrator/trb3_periph_data_concentrator_only1error_200MHz.lpf b/data_concentrator/trb3_periph_data_concentrator_only1error_200MHz.lpf
new file mode 100644
index 0000000..cdb9c4c
--- /dev/null
+++ b/data_concentrator/trb3_periph_data_concentrator_only1error_200MHz.lpf
@@ -0,0 +1,268 @@
+rvl_alias "clk_80_i" "clk_80_i";
+RVL_ALIAS "clk_62M5_i" "clk_62M5_i"; 
+RVL_ALIAS "clk_62M5_i" "clk_62M5_i"; 
+RVL_ALIAS "clk_100_i" "clk_100_i"; 
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+#################################################################
+# Basic Settings
+#################################################################
+SYSCONFIG MCCLK_FREQ=2.5 ;
+FREQUENCY PORT "CLK_PCLK_RIGHT" 200.000000 MHz ;
+FREQUENCY PORT "CLK_PCLK_LEFT" 200.000000 MHz ;
+FREQUENCY PORT "CLK_GPLL_RIGHT" 200.000000 MHz ;
+FREQUENCY PORT "CLK_GPLL_LEFT" 125.000000 MHz ;
+#################################################################
+# Clock I/O
+#################################################################
+LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
+LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
+LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18" ;
+LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10" ;
+LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;
+LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;
+DEFINE PORT GROUP "CLK_group" "CLK*" ;
+IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
+#################################################################
+# Trigger I/O
+#################################################################
+#Trigger from fan-out
+LOCATE COMP "TRIGGER_LEFT" SITE "V3" ;
+LOCATE COMP "TRIGGER_RIGHT" SITE "N24" ;
+IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ;
+#################################################################
+# To central FPGA
+#################################################################
+LOCATE COMP "FPGA5_COMM[0]" SITE "AD4" ;
+LOCATE COMP "FPGA5_COMM[1]" SITE "AE3" ;
+LOCATE COMP "FPGA5_COMM[2]" SITE "AA7" ;
+LOCATE COMP "FPGA5_COMM[3]" SITE "AB7" ;
+LOCATE COMP "FPGA5_COMM[4]" SITE "AD3" ;
+LOCATE COMP "FPGA5_COMM[5]" SITE "AC4" ;
+LOCATE COMP "FPGA5_COMM[6]" SITE "AE2" ;
+LOCATE COMP "FPGA5_COMM[7]" SITE "AF3" ;
+LOCATE COMP "FPGA5_COMM[8]" SITE "AE4" ;
+LOCATE COMP "FPGA5_COMM[9]" SITE "AF4" ;
+LOCATE COMP "FPGA5_COMM[10]" SITE "V10" ;
+LOCATE COMP "FPGA5_COMM[11]" SITE "W10" ;
+DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
+IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+LOCATE COMP "TEST_LINE[0]" SITE "A5" ;
+LOCATE COMP "TEST_LINE[1]" SITE "A6" ;
+LOCATE COMP "TEST_LINE[2]" SITE "G8" ;
+LOCATE COMP "TEST_LINE[3]" SITE "F9" ;
+LOCATE COMP "TEST_LINE[4]" SITE "D9" ;
+LOCATE COMP "TEST_LINE[5]" SITE "D10" ;
+LOCATE COMP "TEST_LINE[6]" SITE "F10" ;
+LOCATE COMP "TEST_LINE[7]" SITE "E10" ;
+LOCATE COMP "TEST_LINE[8]" SITE "A8" ;
+LOCATE COMP "TEST_LINE[9]" SITE "B8" ;
+LOCATE COMP "TEST_LINE[10]" SITE "G10" ;
+LOCATE COMP "TEST_LINE[11]" SITE "G9" ;
+LOCATE COMP "TEST_LINE[12]" SITE "C9" ;
+LOCATE COMP "TEST_LINE[13]" SITE "C10" ;
+LOCATE COMP "TEST_LINE[14]" SITE "H10" ;
+LOCATE COMP "TEST_LINE[15]" SITE "H11" ;
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
+#################################################################
+# Connection to AddOn
+#################################################################
+LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0   #1
+LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1   #3
+LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2   #5
+LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3   #7
+LOCATE COMP "SFP_MOD1_1" SITE "R1" ;#DQLL0_4   #9
+LOCATE COMP "SFP_MOD2_1" SITE "R2" ;#DQLL0_5   #11
+LOCATE COMP "SFP_RATESEL_1" SITE "N3" ;#DQSLL0_T  #13
+LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C  #15
+LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6   #17
+LOCATE COMP "SFP_TXFAULT_1" SITE "P6" ;#DQLL0_7   #19
+LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8   #21
+LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9   #23
+LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0   #25
+LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1   #27
+LOCATE COMP "SFP_MOD1_2" SITE "AB1" ;#DQLL2_2   #29
+LOCATE COMP "SFP_MOD2_2" SITE "AC1" ;#DQLL2_3   #31
+LOCATE COMP "SFP_RATESEL_2" SITE "AA1" ;#DQLL2_4   #33
+LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5   #35
+LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T   #37  #should be DQSLL2
+LOCATE COMP "SFP_TXFAULT_2" SITE "W6" ;#DQLL2_C   #39  #should be DQSLL2
+LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0   #2
+LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1   #4
+LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2   #6
+LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3   #8
+LOCATE COMP "SFP_MOD1_3" SITE "AB3" ;#DQLL3_4   #10
+LOCATE COMP "SFP_MOD2_3" SITE "AB4" ;#DQLL3_5   #12
+LOCATE COMP "SFP_RATESEL_3" SITE "Y6" ;#DQLL3_T   #14  #should be DQSLL3
+LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C   #16  #should be DQSLL3
+LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6   #18
+LOCATE COMP "SFP_TXFAULT_3" SITE "AA4" ;#DQLL3_7   #20
+LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8   #22
+LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9   #24
+LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0   #26
+LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1   #28
+LOCATE COMP "SFP_MOD1_4" SITE "T1" ;#DQLL1_2   #30
+LOCATE COMP "SFP_MOD2_4" SITE "U1" ;#DQLL1_3   #32
+LOCATE COMP "SFP_RATESEL_4" SITE "P4" ;#DQLL1_4   #34
+LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5   #36
+LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T  #38
+LOCATE COMP "SFP_TXFAULT_4" SITE "R4" ;#DQSLL1_C  #40
+LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0   #169
+LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1   #171
+LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2   #173
+LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3   #175
+LOCATE COMP "SFP_MOD1_5" SITE "AA26" ;#DQLR1_4   #177
+LOCATE COMP "SFP_MOD2_5" SITE "AB26" ;#DQLR1_5   #179
+LOCATE COMP "SFP_RATESEL_5" SITE "W21" ;#DQSLR1_T  #181
+LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C  #183
+LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6   #185
+LOCATE COMP "SFP_TXFAULT_5" SITE "AA23" ;#DQLR1_7   #187
+LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0   #170
+LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1   #172
+LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2   #174
+LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3   #176
+LOCATE COMP "SFP_MOD1_6" SITE "T26" ;#DQLR2_4   #178
+LOCATE COMP "SFP_MOD2_6" SITE "U26" ;#DQLR2_5   #180
+LOCATE COMP "SFP_RATESEL_6" SITE "V21" ;#DQSLR2_T  #182
+LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C  #184
+LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6   #186
+LOCATE COMP "SFP_TXFAULT_6" SITE "V24" ;#DQLR2_7   #188
+DEFINE PORT GROUP "SFP_group" "SFP*" ;
+IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+#################################################################
+# Additional Lines to AddOn
+#################################################################
+#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
+#all lines are input only
+#line 4/5 go to PLL input
+LOCATE COMP "SPARE_LINE[0]" SITE "M25" ;#194
+LOCATE COMP "SPARE_LINE[1]" SITE "M26" ;#196
+LOCATE COMP "SPARE_LINE[2]" SITE "W4" ;#198
+LOCATE COMP "SPARE_LINE[3]" SITE "W5" ;#200
+LOCATE COMP "SPARE_LINE[4]" SITE "M3" ;#DQUL3_8_OUTOFLANE_FPGA__3 #69
+LOCATE COMP "SPARE_LINE[5]" SITE "M2" ;#DQUL3_9_OUTOFLANE_FPGA__3 #71  
+#################################################################
+# Flash ROM and Reboot
+#################################################################
+LOCATE COMP "FLASH_CLK" SITE "B12" ;
+LOCATE COMP "FLASH_CS" SITE "E11" ;
+LOCATE COMP "FLASH_DIN" SITE "E12" ;
+LOCATE COMP "FLASH_DOUT" SITE "A12" ;
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
+IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
+LOCATE COMP "PROGRAMN" SITE "B11" ;
+IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+#################################################################
+# Misc
+#################################################################
+LOCATE COMP "TEMPSENS" SITE "A13" ;
+IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+#coding of FPGA number
+LOCATE COMP "CODE_LINE[1]" SITE "AA20" ;
+LOCATE COMP "CODE_LINE[0]" SITE "Y21" ;
+IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+#terminated differential pair to pads
+LOCATE COMP "SUPPL" SITE "C14" ;
+IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
+#################################################################
+# LED
+#################################################################
+LOCATE COMP "LED_GREEN" SITE "F12" ;
+LOCATE COMP "LED_ORANGE" SITE "G13" ;
+LOCATE COMP "LED_RED" SITE "A15" ;
+LOCATE COMP "LED_YELLOW" SITE "A16" ;
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+MULTICYCLE TO GROUP "LED_group" 100.000000 ns ;
+#################################################################
+# Basic Settings
+#################################################################
+SYSCONFIG MCCLK_FREQ=20 ;
+FREQUENCY PORT "CLK_PCLK_RIGHT" 200.000000 MHz ;
+FREQUENCY PORT "CLK_PCLK_LEFT" 200.000000 MHz ;
+FREQUENCY PORT "CLK_GPLL_RIGHT" 200.000000 MHz ;
+FREQUENCY PORT "CLK_GPLL_LEFT" 125.000000 MHz ;
+#################################################################
+# Reset Nets
+#################################################################  
+GSR_NET NET "GSR_N";
+#################################################################
+# Locate Serdes and media interfaces
+#################################################################
+#//?   LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_0_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+#//?   LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_0_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_125_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/THE_SERDES/PCSD_INST" SITE "PCSB" ;
+#####REGION "MEDIA_UPLINK" "R90C95D" 13 25;
+#####REGION "MEDIA_DOWNLINK" "R90C120D" 25 35;
+REGION "REGION_SPI" "R13C150D" 12 16 DEVSIZE;
+#####REGION "REGION_IOBUF" "R10C43D"  88 86 DEVSIZE;
+LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ;
+LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
+#####LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
+#####LOCATE UGROUP "THE_SODA_SOURCE/media_interface_group" REGION "MEDIA_DOWNLINK" ;
+MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
+MULTICYCLE TO CELL "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/SCI_DATA_OUT*" 20.000000 ns ;
+MULTICYCLE TO CELL "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/sci*" 20.000000 ns ;
+MULTICYCLE FROM CELL "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/sci*" 20.000000 ns ;
+MULTICYCLE TO CELL "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/wa_pos*" 20.000000 ns ;
+#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50.000000 ns ;
+MAXSKEW NET "clk_125_i" 1.000000 nS ;
+MAXSKEW NET "clk_160_i" 1.000000 nS ;
+MULTICYCLE FROM CLKNET "clk_125_i" TO CLKNET "clk_62M5_i" 8.000000 ns ;
+MULTICYCLE FROM CLKNET "clk_62M5_i" TO CLKNET "clk_125_i" 8.000000 ns ;
+MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "clk_62M5_i" 200.000000 ns ;
+MULTICYCLE FROM CLKNET "clk_62M5_i" TO CLKNET "clk_100_i" 200.000000 ns ;
+MULTICYCLE FROM CLKNET "clk_200_i" TO CLKNET "clk_62M5_i" 200.000000 ns ;
+MULTICYCLE FROM CLKNET "clk_62M5_i" TO CLKNET "clk_200_i" 200.000000 ns ;
+MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "clk_125_i" 200.000000 ns ;
+MULTICYCLE FROM CLKNET "clk_125_i" TO CLKNET "clk_100_i" 200.000000 ns ;
+MULTICYCLE FROM CLKNET "clk_200_i" TO CLKNET "clk_125_i" 200.000000 ns ;
+MULTICYCLE FROM CLKNET "clk_125_i" TO CLKNET "clk_200_i" 200.000000 ns ;
+MULTICYCLE FROM CLKNET "clk_160_i" TO CLKNET "clk_80_i" 6.250000 ns ;
+MULTICYCLE FROM CLKNET "clk_80_i" TO CLKNET "clk_160_i" 6.250000 ns ;
+MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "clk_80_i" 200.000000 ns ;
+MULTICYCLE FROM CLKNET "clk_80_i" TO CLKNET "clk_100_i" 200.000000 ns ;
+MULTICYCLE FROM CLKNET "clk_200_i" TO CLKNET "clk_80_i" 200.000000 ns ;
+MULTICYCLE FROM CLKNET "clk_80_i" TO CLKNET "clk_200_i" 200.000000 ns ;
+MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "clk_160_i" 200.000000 ns ;
+MULTICYCLE FROM CLKNET "clk_160_i" TO CLKNET "clk_100_i" 200.000000 ns ;
+MULTICYCLE FROM CLKNET "clk_200_i" TO CLKNET "clk_160_i" 200.000000 ns ;
+MULTICYCLE FROM CLKNET "clk_160_i" TO CLKNET "clk_200_i" 200.000000 ns ;
+MULTICYCLE FROM CLKNET "clk_80_i" TO CLKNET "clk_62M5_i" 200.000000 ns ;
+MULTICYCLE FROM CLKNET "clk_62M5_i" TO CLKNET "clk_80_i" 200.000000 ns ;
+MULTICYCLE FROM CLKNET "clk_125_i" TO CLKNET "clk_80_i" 200.000000 ns ;
+MULTICYCLE FROM CLKNET "clk_80_i" TO CLKNET "clk_125_i" 200.000000 ns ;
+
+
+BLOCK JTAGPATHS ;
+#MAXSKEW NET "the_dataconcentrator/dc_quad_fiber_module_all/serdesquadbuflayermux1/serdesquadmuxwrapper1/med_ecp3_quad_sfp_sync1/tx_sync_qd_c" 1.000000 nS ;
+#MULTICYCLE FROM CLKNET "clk_125_i_c" TO CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full0" 0.100000 ns ;
+#MULTICYCLE FROM CLKNET "clk_125_i_c" TO CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full1" 0.100000 ns ;
+#MULTICYCLE FROM CLKNET "clk_125_i_c" TO CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full2" 0.100000 ns ;
+#MULTICYCLE FROM CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full0" TO CLKNET "clk_125_i_c" 0.200000 ns ;
+#MULTICYCLE FROM CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full1" TO CLKNET "clk_125_i_c" 0.200000 ns ;
+#MULTICYCLE FROM CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full2" TO CLKNET "clk_125_i_c" 0.200000 ns ;
+#MULTICYCLE FROM CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full3" TO CLKNET "clk_125_i_c" 0.200000 ns ;
+#MAXSKEW NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full0" 1.000000 nS ;
+#MAXSKEW NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full1" 1.000000 nS ;
+#MAXSKEW NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full2" 1.000000 nS ;
+#MAXSKEW NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full3" 1.000000 nS ;
+#MAXDELAY FROM CELL "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/tx_sync_qd_c" TO ASIC "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/THE_SERDES/PCSD_INST" PIN "FFC_SYNC_TOGGLE" 1.200000 ns ;
+#MULTICYCLE FROM CLKNET "clk_125_i_c" TO CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full3" 0.100000 ns ;
+#PERIOD NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full0" 1.000000 nS  ;
+#PERIOD NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full1" 1.000000 nS  ;
+#PERIOD NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full2" 1.000000 nS  ;
+#PERIOD NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full3" 1.000000 nS  ;
+#FREQUENCY NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full1" 1000.000000 MHz ;
+#FREQUENCY NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full2" 1000.000000 MHz ;
+#FREQUENCY NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full3" 1000.000000 MHz ;
+#FREQUENCY NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full0" 1000.000000 MHz ;
diff --git a/data_concentrator/trb3_periph_sodasource_constraints.lpf b/data_concentrator/trb3_periph_sodasource_constraints.lpf
new file mode 100644
index 0000000..8f46c35
--- /dev/null
+++ b/data_concentrator/trb3_periph_sodasource_constraints.lpf
@@ -0,0 +1,53 @@
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+
+#################################################################
+# Basic Settings
+#################################################################
+
+  SYSCONFIG MCCLK_FREQ = 20;
+
+  FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+  FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
+  FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
+  FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
+  
+#################################################################
+# Reset Nets
+#################################################################  
+GSR_NET NET "GSR_N";  
+
+
+
+
+#################################################################
+# Locate Serdes and media interfaces
+#################################################################
+LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_200/PCSD_INST" SITE "PCSA" ;
+
+LOCATE COMP   "THE_SODA_SOURCE/THE_SERDES/PCSD_INST" SITE "PCSB" ;
+
+
+REGION "MEDIA_UPLINK" "R90C95D" 13 25;
+REGION "MEDIA_DOWNLINK" "R90C120D" 25 35;
+REGION "REGION_SPI"   "R13C150D" 12 16 DEVSIZE;
+REGION "REGION_IOBUF" "R10C43D"  88 86 DEVSIZE;
+
+LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; 
+LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
+
+LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
+LOCATE UGROUP "THE_SODA_SOURCE/media_interface_group" REGION "MEDIA_DOWNLINK" ;
+
+
+MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20 ns;
+MULTICYCLE TO CELL "THE_SODA_SOURCE/SCI_DATA_OUT*" 20 ns;
+MULTICYCLE TO CELL "THE_SODA_SOURCE/sci*" 20 ns;
+MULTICYCLE FROM CELL "THE_SODA_SOURCE/sci*" 20 ns;
+MULTICYCLE TO CELL "THE_SODA_SOURCE/wa_pos*" 20 ns;
+
+MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
+
diff --git a/data_concentrator/trb_net16_endpoint_data_concentrator.vhd b/data_concentrator/trb_net16_endpoint_data_concentrator.vhd
new file mode 100644
index 0000000..199637d
--- /dev/null
+++ b/data_concentrator/trb_net16_endpoint_data_concentrator.vhd
@@ -0,0 +1,1079 @@
+-- the full endpoint for HADES: trg, data, unused, regio
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+
+entity trb_net16_endpoint_data_concentrator is
+  generic (
+    USE_CHANNEL                  : channel_config_t := (c_YES,c_YES,c_NO,c_YES);
+    IBUF_DEPTH                   : channel_config_t := (6,6,6,6);
+    FIFO_TO_INT_DEPTH            : channel_config_t := (6,6,6,6);
+    FIFO_TO_APL_DEPTH            : channel_config_t := (1,1,1,1);
+    IBUF_SECURE_MODE             : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
+    API_SECURE_MODE_TO_APL       : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
+    API_SECURE_MODE_TO_INT       : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
+    OBUF_DATA_COUNT_WIDTH        : integer range 0 to 7 := std_DATA_COUNT_WIDTH;
+    INIT_CAN_SEND_DATA           : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
+    REPLY_CAN_SEND_DATA          : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
+    REPLY_CAN_RECEIVE_DATA       : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
+    USE_CHECKSUM                 : channel_config_t := (c_NO,c_YES,c_YES,c_YES);
+    APL_WRITE_ALL_WORDS          : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
+    ADDRESS_MASK                 : std_logic_vector(15 downto 0) := x"FFFF";
+    BROADCAST_BITMASK            : std_logic_vector(7 downto 0) := x"FF";
+    BROADCAST_SPECIAL_ADDR       : std_logic_vector(7 downto 0) := x"FF";
+    TIMING_TRIGGER_RAW           : integer range 0 to 1 := c_YES;
+    REGIO_NUM_STAT_REGS          : integer range 0 to 6 := 3; --log2 of number of status registers
+    REGIO_NUM_CTRL_REGS          : integer range 0 to 6 := 3; --log2 of number of ctrl registers
+    --standard values for output registers
+    REGIO_INIT_CTRL_REGS         : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0');
+    --set to 0 for unused ctrl registers to save resources
+    REGIO_USED_CTRL_REGS         : std_logic_vector(2**(4)-1 downto 0)    := (others => '1');
+    --set to 0 for each unused bit in a register
+    REGIO_USED_CTRL_BITMASK      : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1');
+    REGIO_USE_DAT_PORT           : integer range 0 to 1 := c_YES;  --internal data port
+    REGIO_INIT_ADDRESS           : std_logic_vector(15 downto 0) := x"FFFF";
+    REGIO_INIT_UNIQUE_ID         : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
+    REGIO_INIT_BOARD_INFO        : std_logic_vector(31 downto 0) := x"1111_2222";
+    REGIO_INIT_ENDPOINT_ID       : std_logic_vector(15 downto 0) := x"0001";
+    REGIO_COMPILE_TIME           : std_logic_vector(31 downto 0) := x"00000000";
+    REGIO_COMPILE_VERSION        : std_logic_vector(15 downto 0) := x"0001";
+    REGIO_HARDWARE_VERSION       : std_logic_vector(31 downto 0) := x"12345678";
+    REGIO_USE_1WIRE_INTERFACE    : integer := c_YES; --c_YES,c_NO,c_MONITOR
+    REGIO_USE_VAR_ENDPOINT_ID    : integer range c_NO to c_YES := c_NO;
+    CLOCK_FREQUENCY              : integer range 1 to 200 := 100
+    );
+
+  port(
+    --  Misc
+    CLK                          : in std_logic;
+    RESET                        : in std_logic;
+    CLK_EN                       : in std_logic := '1';
+
+    --  Media direction port
+    MED_DATAREADY_OUT            : out std_logic;
+    MED_DATA_OUT                 : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_OUT           : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+    MED_READ_IN                  : in  std_logic;
+    MED_DATAREADY_IN             : in  std_logic;
+    MED_DATA_IN                  : in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_IN            : in  std_logic_vector (c_NUM_WIDTH-1 downto 0);
+    MED_READ_OUT                 : out std_logic;
+    MED_STAT_OP_IN               : in  std_logic_vector(15 downto 0);
+    MED_CTRL_OP_OUT              : out std_logic_vector(15 downto 0);
+
+    -- LVL1 trigger APL
+    TRG_TIMING_TRG_RECEIVED_IN   : in  std_logic;    --strobe when timing trigger received or real timing trigger signal
+
+    LVL1_TRG_DATA_VALID_OUT      : out std_logic;    --trigger type, number, code, information are valid
+    LVL1_TRG_VALID_TIMING_OUT    : out std_logic;    --valid timing trigger has been received
+    LVL1_TRG_VALID_NOTIMING_OUT  : out std_logic;    --valid trigger without timing trigger has been received
+    LVL1_TRG_INVALID_OUT         : out std_logic;    --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
+
+    LVL1_TRG_TYPE_OUT            : out std_logic_vector(3 downto 0);
+    LVL1_TRG_NUMBER_OUT          : out std_logic_vector(15 downto 0);
+    LVL1_TRG_CODE_OUT            : out std_logic_vector(7 downto 0);
+    LVL1_TRG_INFORMATION_OUT     : out std_logic_vector(23 downto 0);
+
+    LVL1_ERROR_PATTERN_IN        : in  std_logic_vector(31 downto 0) := x"00000000";
+    LVL1_TRG_RELEASE_IN          : in  std_logic := '0';
+    LVL1_INT_TRG_NUMBER_OUT      : out std_logic_vector(15 downto 0);  --internally generated trigger number, for informational uses only
+
+    --Information about trigger handler errors
+    TRG_MULTIPLE_TRG_OUT         : out std_logic;
+    TRG_TIMEOUT_DETECTED_OUT     : out std_logic;
+    TRG_SPURIOUS_TRG_OUT         : out std_logic;
+    TRG_MISSING_TMG_TRG_OUT      : out std_logic;
+    TRG_SPIKE_DETECTED_OUT       : out std_logic;
+    TRG_LONG_TRG_OUT             : out std_logic;
+
+    --Data Port
+    IPU_NUMBER_OUT               : out std_logic_vector (15 downto 0);
+    IPU_READOUT_TYPE_OUT         : out std_logic_vector (3 downto 0);
+    IPU_INFORMATION_OUT          : out std_logic_vector (7 downto 0);
+    --start strobe
+    IPU_START_READOUT_OUT        : out std_logic;
+    --detector data, equipped with DHDR
+    IPU_DATA_IN                  : in  std_logic_vector (31 downto 0);
+    IPU_DATAREADY_IN             : in  std_logic;
+    --no more data, end transfer, send TRM
+    IPU_READOUT_FINISHED_IN      : in  std_logic;
+    --will be low every second cycle due to 32bit -> 16bit conversion
+    IPU_READ_OUT                 : out std_logic;
+    IPU_LENGTH_IN                : in  std_logic_vector (15 downto 0);
+    IPU_ERROR_PATTERN_IN         : in  std_logic_vector (31 downto 0);
+
+
+    -- Slow Control Data Port
+    REGIO_COMMON_STAT_REG_IN  : in  std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+    REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+    REGIO_REGISTERS_IN        : in  std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
+    REGIO_REGISTERS_OUT       : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+    COMMON_STAT_REG_STROBE    : out std_logic_vector(std_COMSTATREG-1 downto 0);
+    COMMON_CTRL_REG_STROBE    : out std_logic_vector(std_COMCTRLREG-1 downto 0);
+    STAT_REG_STROBE           : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
+    CTRL_REG_STROBE           : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+    --following ports only used when using internal data port
+    REGIO_ADDR_OUT            : out std_logic_vector(16-1 downto 0);
+    REGIO_READ_ENABLE_OUT     : out std_logic;
+    REGIO_WRITE_ENABLE_OUT    : out std_logic;
+    REGIO_DATA_OUT            : out std_logic_vector(32-1 downto 0);
+    REGIO_DATA_IN             : in  std_logic_vector(32-1 downto 0) := (others => '0');
+    REGIO_DATAREADY_IN        : in  std_logic := '0';
+    REGIO_NO_MORE_DATA_IN     : in  std_logic := '0';
+    REGIO_WRITE_ACK_IN        : in  std_logic := '0';
+    REGIO_UNKNOWN_ADDR_IN     : in  std_logic := '0';
+    REGIO_TIMEOUT_OUT         : out std_logic;
+    --IDRAM is used if no 1-wire interface, onewire used otherwise
+    REGIO_IDRAM_DATA_IN       : in  std_logic_vector(15 downto 0) := (others => '0');
+    REGIO_IDRAM_DATA_OUT      : out std_logic_vector(15 downto 0);
+    REGIO_IDRAM_ADDR_IN       : in  std_logic_vector(2 downto 0) := "000";
+    REGIO_IDRAM_WR_IN         : in  std_logic := '0';
+    REGIO_ONEWIRE_INOUT       : inout std_logic;  --temperature sensor
+    REGIO_ONEWIRE_MONITOR_IN  : in  std_logic := '0';
+    REGIO_ONEWIRE_MONITOR_OUT : out std_logic;
+    REGIO_VAR_ENDPOINT_ID     : in  std_logic_vector(15 downto 0) := (others => '0');
+
+    GLOBAL_TIME_OUT           : out std_logic_vector(31 downto 0); --global time, microseconds
+    LOCAL_TIME_OUT            : out std_logic_vector(7 downto 0);  --local time running with chip frequency
+    TIME_SINCE_LAST_TRG_OUT   : out std_logic_vector(31 downto 0); --local time, resetted with each trigger
+    TIMER_TICKS_OUT           : out std_logic_vector(1 downto 0);  --bit 1 ms-tick, 0 us-tick
+    --Debugging & Status information
+    STAT_DEBUG_IPU            : out std_logic_vector (31 downto 0);
+    STAT_DEBUG_1              : out std_logic_vector (31 downto 0);
+    STAT_DEBUG_2              : out std_logic_vector (31 downto 0);
+    MED_STAT_OP               : out std_logic_vector (15 downto 0);
+    CTRL_MPLEX                : in  std_logic_vector (31 downto 0) := (others => '0');
+    IOBUF_CTRL_GEN            : in  std_logic_vector (4*32-1 downto 0) := (others => '0');
+    STAT_ONEWIRE              : out std_logic_vector (31 downto 0);
+    STAT_ADDR_DEBUG           : out std_logic_vector (15 downto 0);
+    STAT_TRIGGER_OUT          : out std_logic_vector (79 downto 0);
+    DEBUG_LVL1_HANDLER_OUT    : out std_logic_vector (15 downto 0)
+    );
+end trb_net16_endpoint_data_concentrator;
+
+
+
+
+
+architecture trb_net16_endpoint_data_concentrator_arch of trb_net16_endpoint_data_concentrator is
+
+
+  signal apl_to_buf_INIT_DATAREADY: std_logic_vector(3 downto 0);
+  signal apl_to_buf_INIT_DATA     : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
+  signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
+  signal apl_to_buf_INIT_READ     : std_logic_vector(3 downto 0);
+
+  signal buf_to_apl_INIT_DATAREADY: std_logic_vector(3 downto 0);
+  signal buf_to_apl_INIT_DATA     : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
+  signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
+  signal buf_to_apl_INIT_READ     : std_logic_vector(3 downto 0);
+
+  signal apl_to_buf_REPLY_DATAREADY: std_logic_vector(3 downto 0);
+  signal apl_to_buf_REPLY_DATA     : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
+  signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
+  signal apl_to_buf_REPLY_READ     : std_logic_vector(3 downto 0);
+
+  signal buf_to_apl_REPLY_DATAREADY: std_logic_vector(3 downto 0);
+  signal buf_to_apl_REPLY_DATA     : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
+  signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
+  signal buf_to_apl_REPLY_READ     : std_logic_vector(3 downto 0);
+
+  -- for the connection to the multiplexer
+  signal MED_IO_DATAREADY_IN  : std_logic_vector(3 downto 0);
+  signal MED_IO_DATA_IN       : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
+  signal MED_IO_PACKET_NUM_IN : std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
+  signal MED_IO_READ_OUT      : std_logic_vector(3 downto 0);
+
+  signal MED_IO_DATAREADY_OUT  : std_logic_vector(7 downto 0);
+  signal MED_IO_DATA_OUT       : std_logic_vector (8*c_DATA_WIDTH-1 downto 0);
+  signal MED_IO_PACKET_NUM_OUT : std_logic_vector (8*c_NUM_WIDTH-1 downto 0);
+  signal MED_IO_READ_IN        : std_logic_vector(7 downto 0);
+
+  signal buf_APL_DATA_IN : std_logic_vector(4*c_DATA_WIDTH-1 downto 0);
+  signal buf_APL_PACKET_NUM_IN : std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
+  signal buf_APL_DATAREADY_IN : std_logic_vector(3 downto 0);
+  signal buf_APL_READ_OUT : std_logic_vector(3 downto 0);
+  signal buf_APL_SHORT_TRANSFER_IN : std_logic_vector(3 downto 0);
+  signal buf_APL_DTYPE_IN : std_logic_vector(4*4-1 downto 0);
+  signal buf_APL_ERROR_PATTERN_IN : std_logic_vector(4*32-1 downto 0);
+  signal buf_APL_SEND_IN : std_logic_vector(3 downto 0);
+  signal buf_APL_DATA_OUT : std_logic_vector(4*c_DATA_WIDTH-1 downto 0);
+  signal buf_APL_PACKET_NUM_OUT : std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
+  signal buf_APL_DATAREADY_OUT : std_logic_vector(3 downto 0);
+  signal buf_APL_READ_IN : std_logic_vector(3 downto 0);
+  signal buf_APL_TYP_OUT : std_logic_vector(4*3-1 downto 0);
+  signal buf_APL_RUN_OUT : std_logic_vector(3 downto 0);
+  signal buf_APL_SEQNR_OUT : std_logic_vector(4*8-1 downto 0);
+  signal buf_APL_LENGTH_IN : std_logic_vector(16*4-1 downto 0);
+
+  signal MY_ADDRESS : std_logic_vector(15 downto 0);
+
+  signal buf_api_stat_fifo_to_apl, buf_api_stat_fifo_to_int : std_logic_vector (4*32-1 downto 0);
+  signal buf_STAT_GEN : std_logic_vector(32*4-1 downto 0);
+  signal buf_STAT_INIT_BUFFER : std_logic_vector(32*4-1 downto 0);
+  signal buf_CTRL_GEN : std_logic_vector(32*4-1 downto 0);
+  signal buf_STAT_INIT_OBUF_DEBUG      : std_logic_vector (32*4-1 downto 0);
+  signal buf_STAT_REPLY_OBUF_DEBUG     : std_logic_vector (32*4-1 downto 0);
+
+  signal REGIO_REGIO_STAT : std_logic_vector(31 downto 0);
+
+  signal buf_COMMON_STAT_REG_IN: std_logic_vector(std_COMSTATREG*32-1 downto 0);
+  signal buf_REGIO_COMMON_CTRL_REG_OUT : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+
+  signal buf_IDRAM_DATA_IN       :  std_logic_vector(15 downto 0);
+  signal buf_IDRAM_DATA_OUT      :  std_logic_vector(15 downto 0);
+  signal buf_IDRAM_ADDR_IN       :  std_logic_vector(2 downto 0);
+  signal buf_IDRAM_WR_IN         :  std_logic;
+  signal reset_no_link           :  std_logic;
+  signal ONEWIRE_DATA            :  std_logic_vector(15 downto 0);
+  signal ONEWIRE_ADDR            :  std_logic_vector(2 downto 0);
+  signal ONEWIRE_WRITE           :  std_logic;
+
+  signal buf_COMMON_STAT_REG_STROBE :  std_logic_vector((std_COMSTATREG)-1 downto 0);
+  signal buf_COMMON_CTRL_REG_STROBE :  std_logic_vector((std_COMCTRLREG)-1 downto 0);
+  signal buf_STAT_REG_STROBE        :  std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
+  signal buf_CTRL_REG_STROBE        :  std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+  signal int_trigger_num            : std_logic_vector(15 downto 0);
+
+  signal buf_LVL1_TRG_TYPE_OUT        : std_logic_vector(3 downto 0);
+  signal buf_LVL1_TRG_RECEIVED_OUT    : std_logic;
+  signal buf_LVL1_TRG_NUMBER_OUT      : std_logic_vector(15 downto 0);
+  signal buf_LVL1_TRG_CODE_OUT        : std_logic_vector(7 downto 0);
+  signal buf_LVL1_TRG_INFORMATION_OUT : std_logic_vector(23 downto 0);
+  signal last_LVL1_TRG_RECEIVED_OUT   : std_logic;
+  signal LVL1_TRG_RECEIVED_OUT_rising : std_logic;
+  signal LVL1_TRG_RECEIVED_OUT_falling: std_logic;
+  signal buf_LVL1_ERROR_PATTERN_IN    : std_logic_vector(31 downto 0);
+
+  signal temperature                  : std_logic_vector(11 downto 0);
+  signal got_timing_trigger           : std_logic;
+  signal got_timingless_trigger       : std_logic;
+  signal trigger_number_match         : std_logic;
+  signal buf_TIMER_TICKS_OUT          : std_logic_vector(1 downto 0);
+--   signal timing_trigger_missing       : std_logic;
+
+  signal buf_LVL1_VALID_TIMING_TRG_OUT    : std_logic;
+  signal buf_LVL1_VALID_NOTIMING_TRG_OUT  : std_logic;
+  signal buf_LVL1_INVALID_TRG_OUT         : std_logic;
+  signal buf_LVL1_TRG_RELEASE_IN          : std_logic;
+  signal buf_LVL1_TRG_DATA_VALID_OUT      : std_logic;
+
+  signal int_lvl1_delay            : std_logic_vector(15 downto 0);
+  signal int_trg_reset             : std_logic;
+  signal reset_trg_logic           : std_logic;
+  signal stat_lvl1_handler         : std_logic_vector(63 downto 0);
+  signal stat_counters_lvl1_handler: std_logic_vector(79 downto 0);
+  signal trg_invert_i              : std_logic;
+  signal int_multiple_trg          : std_logic;
+  signal int_lvl1_timeout_detected : std_logic;
+  signal int_lvl1_spurious_trg     : std_logic;
+  signal int_lvl1_missing_tmg_trg  : std_logic;
+  signal int_spike_detected        : std_logic;
+  signal int_lvl1_long_trg         : std_logic;
+
+
+  signal last_TRG_TIMING_TRG_RECEIVED_IN : std_logic;
+  signal last_timingtrg_counter_write    : std_logic;
+  signal last_timingtrg_counter_read     : std_logic;
+
+  signal reg_timing_trigger : std_logic;
+  signal trigger_timing_rising : std_logic;
+  signal last_reg_timing_trigger : std_logic;
+--   signal timing_trigger_missing_stat : std_logic;
+
+  signal link_error_i            : std_logic;
+  signal link_and_reset_status   : std_logic_vector(31 downto 0);
+
+  signal make_trbnet_reset       : std_logic;
+  signal last_make_trbnet_reset  : std_logic;
+  signal lvl1_tmg_trg_missing_flag : std_logic;
+
+  component edge_to_pulse is
+    port (
+      clock     : in  std_logic;
+      en_clk    : in  std_logic;
+      signal_in : in  std_logic;
+      pulse     : out std_logic);
+  end component;
+
+begin
+
+  process(CLK)
+    begin
+      if rising_edge(CLK) then
+        reset_no_link  <= MED_STAT_OP_IN(14) or RESET;
+        reset_trg_logic <= RESET or buf_REGIO_COMMON_CTRL_REG_OUT(1);
+      end if;
+    end process;
+
+  MED_CTRL_OP_OUT(7 downto 0)  <= (others => '0');
+  MED_CTRL_OP_OUT(8)           <= buf_REGIO_COMMON_CTRL_REG_OUT(64+27);
+  MED_CTRL_OP_OUT(15 downto 9) <= (others => '0');
+  MED_STAT_OP <= MED_STAT_OP_IN;
+
+  --Connections for data channel
+    genbuffers : for i in 0 to 3 generate
+      geniobuf: if USE_CHANNEL(i) = c_YES generate
+        IOBUF: trb_net16_iobuf
+          generic map (
+            IBUF_DEPTH          => IBUF_DEPTH(i),
+            IBUF_SECURE_MODE    => IBUF_SECURE_MODE(i),
+            SBUF_VERSION        => 0,
+            SBUF_VERSION_OBUF   => 6,
+            OBUF_DATA_COUNT_WIDTH => std_DATA_COUNT_WIDTH,
+            USE_ACKNOWLEDGE     => cfg_USE_ACKNOWLEDGE(i),
+            USE_CHECKSUM        => USE_CHECKSUM(i),
+            USE_VENDOR_CORES    => c_YES,
+            INIT_CAN_SEND_DATA  => INIT_CAN_SEND_DATA(i),
+            REPLY_CAN_SEND_DATA => REPLY_CAN_SEND_DATA(i),
+            REPLY_CAN_RECEIVE_DATA => REPLY_CAN_RECEIVE_DATA(i)
+            )
+          port map (
+            --  Misc
+            CLK     => CLK ,
+            RESET   => reset_no_link,
+            CLK_EN  => CLK_EN,
+            --  Media direction port
+            MED_INIT_DATAREADY_OUT  => MED_IO_DATAREADY_OUT(i*2),
+            MED_INIT_DATA_OUT       => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH),
+            MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH),
+            MED_INIT_READ_IN        => MED_IO_READ_IN(i*2),
+
+            MED_DATAREADY_IN   => MED_IO_DATAREADY_IN(i),
+            MED_DATA_IN        => MED_IO_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+            MED_PACKET_NUM_IN  => MED_IO_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+            MED_READ_OUT       => MED_IO_READ_OUT(i),
+            MED_ERROR_IN       => MED_STAT_OP_IN(2 downto 0),
+
+            MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1),
+            MED_REPLY_DATA_OUT      => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH),
+            MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH),
+            MED_REPLY_READ_IN       => MED_IO_READ_IN(i*2+1),
+
+            -- Internal direction port
+
+            INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY(i),
+            INT_INIT_DATA_OUT      => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+            INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+            INT_INIT_READ_IN       => buf_to_apl_INIT_READ(i),
+
+            INT_INIT_DATAREADY_IN  => apl_to_buf_INIT_DATAREADY(i),
+            INT_INIT_DATA_IN       => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+            INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+            INT_INIT_READ_OUT      => apl_to_buf_INIT_READ(i),
+
+            INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY(i),
+            INT_REPLY_DATA_OUT      => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+            INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+            INT_REPLY_READ_IN       => buf_to_apl_REPLY_READ(i),
+
+            INT_REPLY_DATAREADY_IN  => apl_to_buf_REPLY_DATAREADY(i),
+            INT_REPLY_DATA_IN       => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+            INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+            INT_REPLY_READ_OUT      => apl_to_buf_REPLY_READ(i),
+
+            -- Status and control port
+            STAT_GEN               => buf_STAT_GEN(32*(i+1)-1 downto i*32),
+            STAT_IBUF_BUFFER       => buf_STAT_INIT_BUFFER(32*(i+1)-1 downto i*32),
+            CTRL_GEN               => buf_CTRL_GEN(32*(i+1)-1 downto i*32),
+            STAT_INIT_OBUF_DEBUG   => buf_STAT_INIT_OBUF_DEBUG(32*(i+1)-1 downto i*32),
+            STAT_REPLY_OBUF_DEBUG  => buf_STAT_REPLY_OBUF_DEBUG(32*(i+1)-1 downto i*32),
+            TIMER_TICKS_IN         => buf_TIMER_TICKS_OUT,
+            CTRL_STAT              => x"0000"
+            );
+
+      gen_api : if i /= c_TRG_LVL1_CHANNEL generate
+        constant j : integer := i;
+      begin
+        DAT_PASSIVE_API: trb_net16_api_base
+          generic map (
+            API_TYPE          => c_API_PASSIVE,
+            FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH(i),
+            FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH(i),
+            FORCE_REPLY       => cfg_FORCE_REPLY(i),
+            SBUF_VERSION      => 0,
+            USE_VENDOR_CORES   => c_YES,
+            SECURE_MODE_TO_APL => API_SECURE_MODE_TO_APL(i),
+            SECURE_MODE_TO_INT => API_SECURE_MODE_TO_INT(i),
+            APL_WRITE_ALL_WORDS=> APL_WRITE_ALL_WORDS(i),
+            ADDRESS_MASK       => ADDRESS_MASK,
+            BROADCAST_BITMASK  => BROADCAST_BITMASK,
+            BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR
+            )
+          port map (
+            --  Misc
+            CLK    => CLK,
+            RESET  => RESET,
+            CLK_EN => CLK_EN,
+            -- APL Transmitter port
+            APL_DATA_IN           => buf_APL_DATA_IN((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH),
+            APL_PACKET_NUM_IN     => buf_APL_PACKET_NUM_IN((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH),
+            APL_DATAREADY_IN      => buf_APL_DATAREADY_IN(j),
+            APL_READ_OUT          => buf_APL_READ_OUT(j),
+            APL_SHORT_TRANSFER_IN => buf_APL_SHORT_TRANSFER_IN(j),
+            APL_DTYPE_IN          => buf_APL_DTYPE_IN((j+1)*4-1 downto j*4),
+            APL_ERROR_PATTERN_IN  => buf_APL_ERROR_PATTERN_IN((j+1)*32-1 downto j*32),
+            APL_SEND_IN           => buf_APL_SEND_IN(j),
+            APL_TARGET_ADDRESS_IN => (others => '0'),
+            -- Receiver port
+            APL_DATA_OUT      => buf_APL_DATA_OUT((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH),
+            APL_PACKET_NUM_OUT=> buf_APL_PACKET_NUM_OUT((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH),
+            APL_TYP_OUT       => buf_APL_TYP_OUT((j+1)*3-1 downto j*3),
+            APL_DATAREADY_OUT => buf_APL_DATAREADY_OUT(j),
+            APL_READ_IN       => buf_APL_READ_IN(j),
+            -- APL Control port
+            APL_RUN_OUT       => buf_APL_RUN_OUT(j),
+            APL_MY_ADDRESS_IN => MY_ADDRESS,
+            APL_SEQNR_OUT     => buf_APL_SEQNR_OUT((j+1)*8-1 downto j*8),
+            APL_LENGTH_IN     => buf_APL_LENGTH_IN((j+1)*16-1 downto j*16),
+            -- Internal direction port
+            INT_MASTER_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
+            INT_MASTER_DATA_OUT      => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+            INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+            INT_MASTER_READ_IN       => apl_to_buf_REPLY_READ(i),
+            INT_MASTER_DATAREADY_IN  => buf_to_apl_REPLY_DATAREADY(i),
+            INT_MASTER_DATA_IN       => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+            INT_MASTER_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+            INT_MASTER_READ_OUT      => buf_to_apl_REPLY_READ(i),
+            INT_SLAVE_DATAREADY_OUT  => apl_to_buf_INIT_DATAREADY(i),
+            INT_SLAVE_DATA_OUT       => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+            INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+            INT_SLAVE_READ_IN        => apl_to_buf_INIT_READ(i),
+            INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
+            INT_SLAVE_DATA_IN      => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+            INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+            INT_SLAVE_READ_OUT     => buf_to_apl_INIT_READ(i),
+            -- Status and control port
+            CTRL_SEQNR_RESET =>  buf_REGIO_COMMON_CTRL_REG_OUT(10),
+            STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32),
+            STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32)
+            );
+        end generate;
+
+        gentrgapi : if i = c_TRG_LVL1_CHANNEL generate
+          buf_APL_READ_OUT(i) <= '0';
+          buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
+          buf_APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
+          buf_APL_DATAREADY_OUT(i) <= '0';
+          buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8) <= (others => '0');
+          buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+          buf_APL_DTYPE_IN((i+1)*4-1 downto i*4) <= (others => '0');
+          buf_APL_LENGTH_IN((i+1)*16-1 downto i*16) <= (others => '1');
+          buf_APL_RUN_OUT(i) <= '0';
+          buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32) <= (others => '0');
+          buf_APL_READ_IN(i) <= '0';
+          buf_APL_SHORT_TRANSFER_IN(i) <= '0';
+          buf_APL_TYP_OUT((i+1)*3-1 downto i*3) <= (others => '0');
+          buf_APL_DATAREADY_IN(i) <= '0';
+          buf_APL_SEND_IN(i) <= '0';
+          buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+
+          apl_to_buf_INIT_DATAREADY(i) <= '0';
+          apl_to_buf_INIT_DATA((i+1)*16-1 downto i*16) <= (others => '0');
+          apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+          apl_to_buf_INIT_READ(i) <= '0';
+
+          buf_to_apl_REPLY_READ(i) <= '1';
+          buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+          buf_to_apl_REPLY_DATAREADY(i) <= '0';
+          buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
+
+          buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32) <= (others => '0');
+          buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32) <= (others => '0');
+
+
+          the_trigger_apl : trb_net16_trigger
+            generic map(
+              USE_TRG_PORT => c_YES,
+              SECURE_MODE  => std_TERM_SECURE_MODE
+              )
+            port map(
+              --  Misc
+              CLK    => CLK,
+              RESET  => RESET,
+              CLK_EN => CLK_EN,
+              INT_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
+              INT_DATA_OUT      => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+              INT_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+              INT_READ_IN       => apl_to_buf_REPLY_READ(i),
+              INT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
+              INT_DATA_IN      => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+              INT_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+              INT_READ_OUT     => buf_to_apl_INIT_READ(i),
+              TRG_RECEIVED_OUT      => buf_LVL1_TRG_RECEIVED_OUT,
+              TRG_TYPE_OUT          => buf_LVL1_TRG_TYPE_OUT,
+              TRG_NUMBER_OUT        => buf_LVL1_TRG_NUMBER_OUT,
+              TRG_CODE_OUT          => buf_LVL1_TRG_CODE_OUT,
+              TRG_INFORMATION_OUT   => buf_LVL1_TRG_INFORMATION_OUT,
+              TRG_RELEASE_IN        => buf_LVL1_TRG_RELEASE_IN,
+              TRG_ERROR_PATTERN_IN  => buf_LVL1_ERROR_PATTERN_IN
+              );
+        end generate;
+
+        gen_ipu_apl : if i = c_DATA_CHANNEL generate
+          the_ipudata_apl : trb_net16_ipudata
+            port map(
+              CLK    => CLK,
+              RESET  => RESET,
+              CLK_EN => CLK_EN,
+              API_DATA_OUT           => buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+              API_PACKET_NUM_OUT     => buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+              API_DATAREADY_OUT      => buf_APL_DATAREADY_IN(i),
+              API_READ_IN            => buf_APL_READ_OUT(i),
+              API_SHORT_TRANSFER_OUT => buf_APL_SHORT_TRANSFER_IN(i),
+              API_DTYPE_OUT          => buf_APL_DTYPE_IN((i+1)*4-1 downto i*4),
+              API_ERROR_PATTERN_OUT  => buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32),
+              API_SEND_OUT           => buf_APL_SEND_IN(i),
+              API_DATA_IN            => buf_APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+              API_PACKET_NUM_IN      => buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+              API_TYP_IN             => buf_APL_TYP_OUT((i+1)*3-1 downto i*3),
+              API_DATAREADY_IN       => buf_APL_DATAREADY_OUT(i),
+              API_READ_OUT           => buf_APL_READ_IN(i),
+              API_RUN_IN             => buf_APL_RUN_OUT(i),
+              API_SEQNR_IN           => buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8),
+              API_LENGTH_OUT         => buf_APL_LENGTH_IN((i+1)*16-1 downto i*16),
+              MY_ADDRESS_IN          => MY_ADDRESS,
+              --Information received with request
+              IPU_NUMBER_OUT         => IPU_NUMBER_OUT,
+              IPU_READOUT_TYPE_OUT   => IPU_READOUT_TYPE_OUT,
+              IPU_INFORMATION_OUT    => IPU_INFORMATION_OUT,
+              --start strobe
+              IPU_START_READOUT_OUT  => IPU_START_READOUT_OUT,
+              --detector data, equipped with DHDR
+              IPU_DATA_IN            => IPU_DATA_IN,
+              IPU_DATAREADY_IN       => IPU_DATAREADY_IN,
+              --no more data, end transfer, send TRM
+              IPU_READOUT_FINISHED_IN=> IPU_READOUT_FINISHED_IN,
+              --will be low every second cycle due to 32bit -> 16bit conversion
+              IPU_READ_OUT           => IPU_READ_OUT,
+              IPU_LENGTH_IN          => IPU_LENGTH_IN,
+              IPU_ERROR_PATTERN_IN   => IPU_ERROR_PATTERN_IN,
+              STAT_DEBUG             => STAT_DEBUG_IPU
+              );
+        end generate;
+
+        gen_regio : if i = c_SLOW_CTRL_CHANNEL generate
+          buf_APL_LENGTH_IN((i+1)*16-1 downto i*16) <= (others => '1');
+
+          regIO : trb_net16_regIO
+            generic map(
+              NUM_STAT_REGS      => REGIO_NUM_STAT_REGS,
+              NUM_CTRL_REGS      => REGIO_NUM_CTRL_REGS,
+              --standard values for output registers
+              INIT_CTRL_REGS     => REGIO_INIT_CTRL_REGS,
+              --set to 0 for unused ctrl registers to save resources
+              USED_CTRL_REGS     => REGIO_USED_CTRL_REGS,
+              --set to 0 for each unused bit in a register
+              USED_CTRL_BITMASK  => REGIO_USED_CTRL_BITMASK,
+              --no data / address out?
+              USE_DAT_PORT       => REGIO_USE_DAT_PORT,
+              INIT_ADDRESS       => REGIO_INIT_ADDRESS,
+              INIT_UNIQUE_ID     => REGIO_INIT_UNIQUE_ID,
+              INIT_ENDPOINT_ID   => REGIO_INIT_ENDPOINT_ID,
+              COMPILE_TIME       => REGIO_COMPILE_TIME,
+              COMPILE_VERSION    => REGIO_COMPILE_VERSION,
+              HARDWARE_VERSION   => REGIO_HARDWARE_VERSION,
+              CLOCK_FREQ         => CLOCK_FREQUENCY
+              )
+            port map(
+            --  Misc
+              CLK      => CLK,
+              RESET    => RESET,
+              CLK_EN   => CLK_EN,
+            -- Port to API
+              API_DATA_OUT           => buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+              API_PACKET_NUM_OUT     => buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+              API_DATAREADY_OUT      => buf_APL_DATAREADY_IN(i),
+              API_READ_IN            => buf_APL_READ_OUT(i),
+              API_SHORT_TRANSFER_OUT => buf_APL_SHORT_TRANSFER_IN(i),
+              API_DTYPE_OUT          => buf_APL_DTYPE_IN((i+1)*4-1 downto i*4),
+              API_ERROR_PATTERN_OUT  => buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32),
+              API_SEND_OUT           => buf_APL_SEND_IN(3),
+              API_DATA_IN            => buf_APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+              API_PACKET_NUM_IN      => buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+              API_TYP_IN             => buf_APL_TYP_OUT((i+1)*3-1 downto i*3),
+              API_DATAREADY_IN       => buf_APL_DATAREADY_OUT(i),
+              API_READ_OUT           => buf_APL_READ_IN(i),
+              API_RUN_IN             => buf_APL_RUN_OUT(i),
+              API_SEQNR_IN           => buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8),
+            --Port to write Unique ID
+              IDRAM_DATA_IN          => buf_IDRAM_DATA_IN,
+              IDRAM_DATA_OUT         => buf_IDRAM_DATA_OUT,
+              IDRAM_ADDR_IN          => buf_IDRAM_ADDR_IN,
+              IDRAM_WR_IN            => buf_IDRAM_WR_IN,
+              MY_ADDRESS_OUT         => MY_ADDRESS,
+              TRIGGER_MONITOR        => buf_LVL1_VALID_TIMING_TRG_OUT,
+              GLOBAL_TIME            => GLOBAL_TIME_OUT,
+              LOCAL_TIME             => LOCAL_TIME_OUT,
+              TIME_SINCE_LAST_TRG    => TIME_SINCE_LAST_TRG_OUT,
+              TIMER_US_TICK          => buf_TIMER_TICKS_OUT(0),
+              TIMER_MS_TICK          => buf_TIMER_TICKS_OUT(1),
+            --Common Register in / out
+              COMMON_STAT_REG_IN     => buf_COMMON_STAT_REG_IN,
+              COMMON_CTRL_REG_OUT    => buf_REGIO_COMMON_CTRL_REG_OUT,
+            --Custom Register in / out
+              REGISTERS_IN           => REGIO_REGISTERS_IN,
+              REGISTERS_OUT          => REGIO_REGISTERS_OUT,
+              COMMON_STAT_REG_STROBE => buf_COMMON_STAT_REG_STROBE,
+              COMMON_CTRL_REG_STROBE => buf_COMMON_CTRL_REG_STROBE,
+              STAT_REG_STROBE        => buf_STAT_REG_STROBE,
+              CTRL_REG_STROBE        => buf_CTRL_REG_STROBE,
+            --following ports only used when no internal register is accessed
+              DAT_ADDR_OUT           => REGIO_ADDR_OUT,
+              DAT_READ_ENABLE_OUT    => REGIO_READ_ENABLE_OUT,
+              DAT_WRITE_ENABLE_OUT   => REGIO_WRITE_ENABLE_OUT,
+              DAT_DATA_OUT           => REGIO_DATA_OUT,
+              DAT_DATA_IN            => REGIO_DATA_IN,
+              DAT_DATAREADY_IN       => REGIO_DATAREADY_IN,
+              DAT_NO_MORE_DATA_IN    => REGIO_NO_MORE_DATA_IN,
+              DAT_UNKNOWN_ADDR_IN    => REGIO_UNKNOWN_ADDR_IN,
+              DAT_TIMEOUT_OUT        => REGIO_TIMEOUT_OUT,
+              DAT_WRITE_ACK_IN       => REGIO_WRITE_ACK_IN,
+              STAT                   => REGIO_REGIO_STAT,
+              STAT_ADDR_DEBUG        => STAT_ADDR_DEBUG
+              );
+          gen_no1wire : if REGIO_USE_1WIRE_INTERFACE = c_NO generate
+            ONEWIRE_DATA  <= REGIO_IDRAM_DATA_IN;
+            ONEWIRE_ADDR  <= REGIO_IDRAM_ADDR_IN;
+            ONEWIRE_WRITE <= REGIO_IDRAM_WR_IN;
+            REGIO_IDRAM_DATA_OUT <= buf_IDRAM_DATA_OUT;
+            REGIO_ONEWIRE_INOUT <= '0';
+            REGIO_ONEWIRE_MONITOR_OUT <= '0';
+
+          end generate;
+          gen_1wire : if REGIO_USE_1WIRE_INTERFACE = c_YES generate
+
+
+            REGIO_IDRAM_DATA_OUT <= (others => '0');
+
+            onewire_interface : trb_net_onewire
+              generic map(
+                USE_TEMPERATURE_READOUT => c_YES,
+                CLK_PERIOD => 10
+                )
+              port map(
+                CLK      => CLK,
+                RESET    => RESET,
+                --connection to 1-wire interface
+                ONEWIRE  => REGIO_ONEWIRE_INOUT,
+                MONITOR_OUT => REGIO_ONEWIRE_MONITOR_OUT,
+                --connection to id ram, according to memory map in TrbNetRegIO
+                DATA_OUT => ONEWIRE_DATA,
+                ADDR_OUT => ONEWIRE_ADDR,
+                WRITE_OUT=> ONEWIRE_WRITE,
+                TEMP_OUT => temperature,
+                STAT     => STAT_ONEWIRE
+                );
+          end generate;
+          gen_1wire_monitor : if REGIO_USE_1WIRE_INTERFACE = c_MONITOR generate
+            REGIO_IDRAM_DATA_OUT <= (others => '0');
+            REGIO_ONEWIRE_MONITOR_OUT <= '0';
+
+            onewire_interface : trb_net_onewire_listener
+              port map(
+                CLK      => CLK,
+                CLK_EN   => CLK_EN,
+                RESET    => RESET,
+                --connection to 1-wire interface
+                MONITOR_IN => REGIO_ONEWIRE_MONITOR_IN,
+                --connection to id ram, according to memory map in TrbNetRegIO
+                DATA_OUT => ONEWIRE_DATA,
+                ADDR_OUT => ONEWIRE_ADDR,
+                WRITE_OUT=> ONEWIRE_WRITE,
+                TEMP_OUT => temperature,
+                STAT     => STAT_ONEWIRE
+                );
+          end generate;
+        end generate;
+      end generate;
+      gentermbuf: if USE_CHANNEL(i) = c_NO generate
+        buf_APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
+        buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+        buf_APL_READ_OUT(i) <= '0';
+        buf_APL_DATAREADY_OUT(i) <= '0';
+        buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
+        buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8) <= (others => '0');
+        buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+        buf_APL_DTYPE_IN((i+1)*4-1 downto i*4) <= (others => '0');
+        buf_APL_LENGTH_IN((i+1)*16-1 downto i*16) <= (others => '1');
+        buf_APL_RUN_OUT(i) <= '0';
+        buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32) <= (others => '0');
+        buf_APL_READ_IN(i) <= '0';
+        buf_APL_SHORT_TRANSFER_IN(i) <= '0';
+        buf_APL_TYP_OUT((i+1)*3-1 downto i*3) <= (others => '0');
+        buf_APL_DATAREADY_IN(i) <= '0';
+        buf_APL_SEND_IN(i) <= '0';
+
+        apl_to_buf_INIT_READ(i) <= '0';
+        apl_to_buf_INIT_DATAREADY(i) <= '0';
+        apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
+        apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+        apl_to_buf_REPLY_DATAREADY(i) <= '0';
+        apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
+        apl_to_buf_REPLY_READ(i) <= '0';
+        apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+
+        buf_to_apl_INIT_READ(i) <= '0';
+        buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+        buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
+        buf_to_apl_INIT_DATAREADY(i) <= '0';
+        buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
+        buf_to_apl_REPLY_DATAREADY(i) <= '0';
+        buf_to_apl_REPLY_READ(i) <= '0';
+        buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
+
+        buf_STAT_INIT_OBUF_DEBUG((i+1)*32-1 downto i*32) <= (others => '0');
+        buf_STAT_GEN((i+1)*32-1 downto i*32) <= (others => '0');
+        buf_STAT_REPLY_OBUF_DEBUG((i+1)*32-1 downto i*32) <= (others => '0');
+        buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32) <= (others => '0');
+        buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32) <= (others => '0');
+        buf_STAT_INIT_BUFFER((i+1)*32-1 downto i*32) <= (others => '0');
+
+        termbuf: trb_net16_term_buf
+          port map(
+            CLK    => CLK,
+            RESET  => reset_no_link,
+            CLK_EN => CLK_EN,
+            MED_DATAREADY_IN       => MED_IO_DATAREADY_IN(i),
+            MED_DATA_IN            => MED_IO_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+            MED_PACKET_NUM_IN      => MED_IO_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+            MED_READ_OUT           => MED_IO_READ_OUT(i),
+
+            MED_INIT_DATAREADY_OUT  => MED_IO_DATAREADY_OUT(i*2),
+            MED_INIT_DATA_OUT       => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH),
+            MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH),
+            MED_INIT_READ_IN        => MED_IO_READ_IN(i*2),
+            MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1),
+            MED_REPLY_DATA_OUT      => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH),
+            MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH),
+            MED_REPLY_READ_IN       => MED_IO_READ_IN(i*2+1)
+            );
+      end generate;
+    end generate;
+
+
+  MPLEX: trb_net16_io_multiplexer
+    generic map(
+      USE_INPUT_SBUF => (1,1,1,1,0,0,1,1)
+      )
+    port map (
+      CLK      => CLK,
+      RESET    => reset_no_link,
+      CLK_EN   => CLK_EN,
+      MED_DATAREADY_IN   => MED_DATAREADY_IN,
+      MED_DATA_IN        => MED_DATA_IN,
+      MED_PACKET_NUM_IN  => MED_PACKET_NUM_IN,
+      MED_READ_OUT       => MED_READ_OUT,
+      MED_DATAREADY_OUT  => MED_DATAREADY_OUT,
+      MED_DATA_OUT       => MED_DATA_OUT,
+      MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
+      MED_READ_IN        => MED_READ_IN,
+      INT_DATAREADY_OUT  => MED_IO_DATAREADY_IN,
+      INT_DATA_OUT       => MED_IO_DATA_IN,
+      INT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_IN,
+      INT_READ_IN        => MED_IO_READ_OUT,
+      INT_DATAREADY_IN   => MED_IO_DATAREADY_OUT,
+      INT_DATA_IN        => MED_IO_DATA_OUT,
+      INT_PACKET_NUM_IN  => MED_IO_PACKET_NUM_OUT,
+      INT_READ_OUT       => MED_IO_READ_IN,
+      STAT               => open,
+      CTRL               => CTRL_MPLEX
+      );
+
+-------------------------------------------------
+-- Include variable Endpoint ID
+-------------------------------------------------
+  gen_var_endpoint_id : if REGIO_USE_VAR_ENDPOINT_ID = c_YES generate
+    buf_IDRAM_DATA_IN  <= REGIO_VAR_ENDPOINT_ID when RESET = '1' else ONEWIRE_DATA;
+    buf_IDRAM_ADDR_IN  <= "100"                 when RESET = '1' else ONEWIRE_ADDR;
+    buf_IDRAM_WR_IN    <= '1'                   when RESET = '1' else ONEWIRE_WRITE;
+  end generate;
+
+  gen_no_var_endpoint_id : if REGIO_USE_VAR_ENDPOINT_ID = c_NO generate
+    buf_IDRAM_DATA_IN  <= ONEWIRE_DATA;
+    buf_IDRAM_ADDR_IN  <= ONEWIRE_ADDR;
+    buf_IDRAM_WR_IN    <= ONEWIRE_WRITE;
+  end generate;
+
+
+
+-------------------------------------------------
+-- Common Status Register
+-------------------------------------------------
+  proc_gen_common_stat_regs : process(REGIO_COMMON_STAT_REG_IN, trigger_number_match, temperature, int_trigger_num,
+                                      link_error_i, link_and_reset_status, stat_lvl1_handler)
+    begin
+      buf_COMMON_STAT_REG_IN               <= REGIO_COMMON_STAT_REG_IN;
+      buf_COMMON_STAT_REG_IN(4)            <= stat_lvl1_handler(12);
+      buf_COMMON_STAT_REG_IN(8)            <= lvl1_tmg_trg_missing_flag;
+      buf_COMMON_STAT_REG_IN(13)           <= stat_lvl1_handler(7);
+      buf_COMMON_STAT_REG_IN(15)           <= link_error_i;
+      if REGIO_USE_1WIRE_INTERFACE = c_YES then
+        buf_COMMON_STAT_REG_IN(31 downto 20) <= temperature;
+      end if;
+      buf_COMMON_STAT_REG_IN(47 downto 32)   <= int_trigger_num;
+      buf_COMMON_STAT_REG_IN(127 downto 64)  <= stat_lvl1_handler;
+      buf_COMMON_STAT_REG_IN(159 downto 128) <= link_and_reset_status(31 downto 0);
+      buf_COMMON_STAT_REG_IN(175 downto 160) <= buf_LVL1_TRG_INFORMATION_OUT(15 downto 0);
+      buf_COMMON_STAT_REG_IN(179 downto 176) <= buf_LVL1_TRG_TYPE_OUT;
+      buf_COMMON_STAT_REG_IN(183 downto 180) <= buf_LVL1_TRG_NUMBER_OUT(3 downto 0);
+      buf_COMMON_STAT_REG_IN(191 downto 184) <= buf_LVL1_TRG_CODE_OUT;
+      buf_COMMON_STAT_REG_IN(271 downto 192) <= stat_counters_lvl1_handler;
+      buf_COMMON_STAT_REG_IN(287 downto 272) <= (others => '0');
+    end process;
+
+
+
+  REG_LINK_ERROR : process(CLK)
+    begin
+      if rising_edge(CLK) then
+        if buf_REGIO_COMMON_CTRL_REG_OUT(4) = '1' then
+          link_error_i <= '0';
+        elsif MED_STAT_OP_IN(15) = '0' and MED_STAT_OP_IN(13) = '0' and MED_STAT_OP_IN(7 downto 4) = "0111" then
+          link_error_i <= '1';
+        end if;
+
+        if buf_REGIO_COMMON_CTRL_REG_OUT(4) = '1' then
+          lvl1_tmg_trg_missing_flag <= '0';
+        elsif int_lvl1_missing_tmg_trg = '1' or int_lvl1_spurious_trg = '1' or int_spike_detected = '1' then
+          lvl1_tmg_trg_missing_flag <= '1';
+        end if;
+
+--         if LVL1_TRG_RECEIVED_OUT_falling = '1' then
+--           timing_trigger_missing_stat <= timing_trigger_missing;
+--         end if;
+
+        if make_trbnet_reset = '1' then
+          link_and_reset_status(3 downto 0) <= link_and_reset_status(3 downto 0) + '1';
+        end if;
+
+        if MED_STAT_OP_IN(12) = '1' then
+          link_and_reset_status(31 downto 24) <= link_and_reset_status(31 downto 24) + '1';
+        end if;
+
+        if MED_STAT_OP_IN(8) = '1' then
+          link_and_reset_status(23 downto 16) <= link_and_reset_status(23 downto 16) + '1';
+        end if;
+
+        if buf_REGIO_COMMON_CTRL_REG_OUT(5) = '1' then
+          link_and_reset_status <= (others => '0');
+        end if;
+
+      end if;
+    end process;
+
+  PROC_FIND_TRBNET_RESET : process(CLK)
+    begin
+      if rising_edge(CLK) then
+        last_make_trbnet_reset <= MED_STAT_OP_IN(13);
+        make_trbnet_reset      <= MED_STAT_OP_IN(13) and not last_make_trbnet_reset;
+      end if;
+    end process;
+
+-------------------------------------------------
+-- Check LVL1 trigger number
+-------------------------------------------------
+
+  THE_LVL1_HANDLER : handler_lvl1
+    generic map (
+      TIMING_TRIGGER_RAW           => TIMING_TRIGGER_RAW
+    )
+    port map(
+      RESET                        => reset_trg_logic,
+      RESET_FLAGS_IN               => buf_REGIO_COMMON_CTRL_REG_OUT(4),
+      RESET_STATS_IN               => buf_REGIO_COMMON_CTRL_REG_OUT(5),
+      CLOCK                        => CLK,
+      --Timing Trigger
+      LVL1_TIMING_TRG_IN           => TRG_TIMING_TRG_RECEIVED_IN,
+      LVL1_PSEUDO_TMG_TRG_IN       => buf_REGIO_COMMON_CTRL_REG_OUT(16),
+      --LVL1_handler connection
+      LVL1_TRG_RECEIVED_IN         => buf_LVL1_TRG_RECEIVED_OUT,
+      LVL1_TRG_TYPE_IN             => buf_LVL1_TRG_TYPE_OUT,
+      LVL1_TRG_NUMBER_IN           => buf_LVL1_TRG_NUMBER_OUT,
+      LVL1_TRG_CODE_IN             => buf_LVL1_TRG_CODE_OUT,
+      LVL1_TRG_INFORMATION_IN      => buf_LVL1_TRG_INFORMATION_OUT,
+      LVL1_ERROR_PATTERN_OUT       => buf_LVL1_ERROR_PATTERN_IN,
+      LVL1_TRG_RELEASE_OUT         => buf_LVL1_TRG_RELEASE_IN,
+
+      LVL1_INT_TRG_NUMBER_OUT      => int_trigger_num,
+      LVL1_INT_TRG_LOAD_IN         => buf_COMMON_CTRL_REG_STROBE(1),
+      LVL1_INT_TRG_COUNTER_IN      => buf_REGIO_COMMON_CTRL_REG_OUT(47 downto 32),
+
+      --FEE logic / Data Handler
+      LVL1_TRG_DATA_VALID_OUT      => buf_LVL1_TRG_DATA_VALID_OUT,
+      LVL1_VALID_TIMING_TRG_OUT    => buf_LVL1_VALID_TIMING_TRG_OUT,
+      LVL1_VALID_NOTIMING_TRG_OUT  => buf_LVL1_VALID_NOTIMING_TRG_OUT,
+      LVL1_INVALID_TRG_OUT         => buf_LVL1_INVALID_TRG_OUT,
+      LVL1_MULTIPLE_TRG_OUT        => int_multiple_trg,
+      LVL1_DELAY_OUT               => int_lvl1_delay,
+      LVL1_TIMEOUT_DETECTED_OUT    => int_lvl1_timeout_detected,
+      LVL1_SPURIOUS_TRG_OUT        => int_lvl1_spurious_trg,
+      LVL1_MISSING_TMG_TRG_OUT     => int_lvl1_missing_tmg_trg,
+      LVL1_LONG_TRG_OUT            => int_lvl1_long_trg,
+      SPIKE_DETECTED_OUT           => int_spike_detected,
+
+      LVL1_ERROR_PATTERN_IN        => LVL1_ERROR_PATTERN_IN,
+      LVL1_TRG_RELEASE_IN          => LVL1_TRG_RELEASE_IN,
+
+      --Stat/Control
+      STATUS_OUT                   => stat_lvl1_handler,
+      TRG_ENABLE_IN                => buf_REGIO_COMMON_CTRL_REG_OUT(95),
+      TRG_INVERT_IN                => buf_REGIO_COMMON_CTRL_REG_OUT(93),
+      COUNTERS_STATUS_OUT          => stat_counters_lvl1_handler,
+      --Debug
+      DEBUG_OUT                    => DEBUG_LVL1_HANDLER_OUT
+    );
+
+  TRG_SPIKE_DETECTED_OUT   <= int_spike_detected;
+  TRG_SPURIOUS_TRG_OUT     <= int_lvl1_spurious_trg;
+  TRG_TIMEOUT_DETECTED_OUT <= int_lvl1_timeout_detected;
+  TRG_MULTIPLE_TRG_OUT     <= int_multiple_trg;
+  TRG_MISSING_TMG_TRG_OUT  <= int_lvl1_missing_tmg_trg;
+  TRG_LONG_TRG_OUT         <= int_lvl1_long_trg;
+
+  
+
+--   THE_TRG_SYNC : signal_sync
+--      generic map(
+--        DEPTH => 2,
+--        WIDTH => 1
+--        )
+--      port map(
+--        RESET    => RESET,
+--        D_IN(0)  => TRG_TIMING_TRG_RECEIVED_IN,
+--        CLK0     => CLK,
+--        CLK1     => CLK,
+--        D_OUT(0) => reg_timing_trigger
+--        );
+--
+--
+--
+--
+--   proc_internal_trigger_number : process(CLK)
+--     begin
+--       if rising_edge(CLK) then
+--         if reset_no_link = '1' then
+--           int_trigger_num <= (others => '0');
+--         elsif LVL1_TRG_RECEIVED_OUT_falling = '1' then
+--           int_trigger_num <= int_trigger_num + 1;
+--         elsif buf_COMMON_CTRL_REG_STROBE(1) = '1' then
+--           int_trigger_num <= buf_REGIO_COMMON_CTRL_REG_OUT(47 downto 32);
+--         end if;
+--       end if;
+--     end process;
+--
+--   proc_check_trigger_number : process(CLK)
+--     begin
+--       if rising_edge(CLK) then
+--         if reset_no_link = '1' or LVL1_TRG_RECEIVED_OUT_falling = '1' then
+--           trigger_number_match <= '1';
+--         elsif LVL1_TRG_RECEIVED_OUT_rising = '1' then
+--           if int_trigger_num = buf_LVL1_TRG_NUMBER_OUT  then
+--             trigger_number_match <= '1';
+--           else
+--             trigger_number_match <= '0';
+--           end if;
+--         end if;
+--       end if;
+--     end process;
+--
+--
+--   proc_detect_trigger_receive : process(CLK)
+--     begin
+--       if rising_edge(CLK) then
+--         last_reg_timing_trigger <= reg_timing_trigger;
+--         trigger_timing_rising   <= reg_timing_trigger and not last_reg_timing_trigger; -- and buf_REGIO_COMMON_CTRL_REG_OUT(95);
+--
+--         last_LVL1_TRG_RECEIVED_OUT <= buf_LVL1_TRG_RECEIVED_OUT;
+--         LVL1_TRG_RECEIVED_OUT_rising <= buf_LVL1_TRG_RECEIVED_OUT and not last_LVL1_TRG_RECEIVED_OUT;
+--         LVL1_TRG_RECEIVED_OUT_falling <= not buf_LVL1_TRG_RECEIVED_OUT and last_LVL1_TRG_RECEIVED_OUT;
+--
+--         if reset_no_link = '1' or LVL1_TRG_RECEIVED_OUT_falling = '1' then
+--           got_timing_trigger <= '0';
+--           got_timingless_trigger <= '0';
+--           timing_trigger_missing <= '0';
+--         elsif trigger_timing_rising = '1' then --TRG_TIMING_TRG_RECEIVED_IN
+--           got_timing_trigger <= '1';
+--         elsif (LVL1_TRG_RECEIVED_OUT_rising = '1' and buf_LVL1_TRG_TYPE_OUT >= x"8" and buf_LVL1_TRG_INFORMATION_OUT(7) = '1') then
+--           got_timingless_trigger <= '1';
+--         elsif (LVL1_TRG_RECEIVED_OUT_rising = '1' and not (buf_LVL1_TRG_TYPE_OUT >= x"8" and buf_LVL1_TRG_INFORMATION_OUT(7) = '1') and got_timing_trigger = '0') then
+--           timing_trigger_missing <= '1';
+--         end if;
+--       end if;
+--     end process;
+--
+--
+--   proc_gen_lvl1_error_pattern : process(LVL1_ERROR_PATTERN_IN, trigger_number_match, got_timing_trigger,got_timingless_trigger )
+--     begin
+--       buf_LVL1_ERROR_PATTERN_IN     <= LVL1_ERROR_PATTERN_IN;
+--       buf_LVL1_ERROR_PATTERN_IN(16) <= not trigger_number_match or LVL1_ERROR_PATTERN_IN(16);
+--       buf_LVL1_ERROR_PATTERN_IN(17) <= (not got_timing_trigger and not got_timingless_trigger) or LVL1_ERROR_PATTERN_IN(17);
+--     end process;
+--
+--   buf_LVL1_VALID_TIMING_TRG_OUT    <= trigger_timing_rising; --TRG_TIMING_TRG_RECEIVED_IN;
+--   buf_LVL1_VALID_NOTIMING_TRG_OUT  <= LVL1_TRG_RECEIVED_OUT_rising and not got_timing_trigger
+--                                         and buf_LVL1_TRG_TYPE_OUT(3) and buf_LVL1_TRG_INFORMATION_OUT(7);
+--   buf_LVL1_INVALID_TRG_OUT         <= '0';
+
+--   proc_count_timing_trg : process(CLK)
+--     begin
+--       if rising_edge(CLK) then
+--         last_TRG_TIMING_TRG_RECEIVED_IN <= TRG_TIMING_TRG_RECEIVED_IN;
+--         last_timingtrg_counter_write <= timingtrg_counter_write;
+--         last_timingtrg_counter_read <= timingtrg_counter_read;
+--         if RESET = '1' or timingtrg_counter_write = '1' then
+--           timingtrg_counter <= (others => '0');
+--         elsif TRG_TIMING_TRG_RECEIVED_IN = '1' and last_TRG_TIMING_TRG_RECEIVED_IN = '0' then
+--           timingtrg_counter <= (others => '0');
+--         end if;
+--       end if;
+--     end process;
+
+
+
+-------------------------------------------------
+-- Connect Outputs
+-------------------------------------------------
+--   buf_LVL1_TRG_RELEASE_IN        <= LVL1_TRG_RELEASE_IN;           --changed back
+--   LVL1_TRG_DATA_VALID_OUT        <= buf_LVL1_TRG_RECEIVED_OUT;     --changed back
+  LVL1_TRG_DATA_VALID_OUT        <= buf_LVL1_TRG_DATA_VALID_OUT;  --changed back
+
+  LVL1_TRG_VALID_TIMING_OUT      <= buf_LVL1_VALID_TIMING_TRG_OUT;
+  LVL1_TRG_VALID_NOTIMING_OUT    <= buf_LVL1_VALID_NOTIMING_TRG_OUT;
+  LVL1_TRG_INVALID_OUT           <= buf_LVL1_INVALID_TRG_OUT;
+
+  LVL1_TRG_TYPE_OUT              <= buf_LVL1_TRG_TYPE_OUT;
+  LVL1_TRG_NUMBER_OUT            <= buf_LVL1_TRG_NUMBER_OUT;
+  LVL1_TRG_CODE_OUT              <= buf_LVL1_TRG_CODE_OUT;
+  LVL1_TRG_INFORMATION_OUT       <= buf_LVL1_TRG_INFORMATION_OUT;
+  LVL1_INT_TRG_NUMBER_OUT        <= int_trigger_num;
+
+  COMMON_STAT_REG_STROBE         <= buf_COMMON_STAT_REG_STROBE;
+  COMMON_CTRL_REG_STROBE         <= buf_COMMON_CTRL_REG_STROBE;
+  STAT_REG_STROBE                <= buf_STAT_REG_STROBE;
+  CTRL_REG_STROBE                <= buf_CTRL_REG_STROBE;
+
+  TIMER_TICKS_OUT                <= buf_TIMER_TICKS_OUT;
+
+  buf_CTRL_GEN                   <= IOBUF_CTRL_GEN;
+  REGIO_COMMON_CTRL_REG_OUT      <= buf_REGIO_COMMON_CTRL_REG_OUT;
+
+  STAT_DEBUG_1                   <= REGIO_REGIO_STAT;
+  STAT_DEBUG_2(3 downto 0)       <= MED_IO_DATA_OUT(7*16+3 downto 7*16);
+  STAT_DEBUG_2(7 downto 4)       <= apl_to_buf_REPLY_DATA(3*16+3 downto 3*16);
+  STAT_DEBUG_2(8)                <= apl_to_buf_REPLY_DATAREADY(3);
+  STAT_DEBUG_2(11 downto 9)      <= apl_to_buf_REPLY_PACKET_NUM(3*3+2 downto 3*3);
+  STAT_DEBUG_2(15 downto 12)     <= (others => '0');
+  STAT_DEBUG_2(31 downto 16)     <= buf_STAT_INIT_BUFFER(3*32+15 downto 3*32);
+
+  STAT_TRIGGER_OUT               <= stat_counters_lvl1_handler;
+
+end architecture;
+
diff --git a/data_concentrator/trb_net16_endpoint_data_concentrator_handler.vhd b/data_concentrator/trb_net16_endpoint_data_concentrator_handler.vhd
new file mode 100644
index 0000000..f9f7cd4
--- /dev/null
+++ b/data_concentrator/trb_net16_endpoint_data_concentrator_handler.vhd
@@ -0,0 +1,801 @@
+-- the full endpoint for HADES: trg, data, unused, regio including data buffer & handling
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+
+entity trb_net16_endpoint_data_concentrator_handler is
+  generic (
+    IBUF_DEPTH                   : channel_config_t              := (6,6,6,6);
+    FIFO_TO_INT_DEPTH            : channel_config_t              := (6,6,6,6);
+    FIFO_TO_APL_DEPTH            : channel_config_t              := (1,1,1,1);
+    APL_WRITE_ALL_WORDS          : channel_config_t              := (c_NO,c_NO,c_NO,c_NO);
+    ADDRESS_MASK                 : std_logic_vector(15 downto 0) := x"FFFF";
+    BROADCAST_BITMASK            : std_logic_vector(7 downto 0)  := x"FF";
+    BROADCAST_SPECIAL_ADDR       : std_logic_vector(7 downto 0)  := x"FF";
+    REGIO_NUM_STAT_REGS          : integer range 0 to 6          := 3; --log2 of number of status registers
+    REGIO_NUM_CTRL_REGS          : integer range 0 to 6          := 3; --log2 of number of ctrl registers
+    REGIO_INIT_CTRL_REGS         : std_logic_vector(16*32-1 downto 0) := (others => '0');
+    REGIO_INIT_ADDRESS           : std_logic_vector(15 downto 0) := x"FFFF";
+    REGIO_INIT_BOARD_INFO        : std_logic_vector(31 downto 0) := x"1111_2222";
+    REGIO_INIT_ENDPOINT_ID       : std_logic_vector(15 downto 0) := x"0001";
+    REGIO_COMPILE_TIME           : std_logic_vector(31 downto 0) := x"00000000";
+    REGIO_COMPILE_VERSION        : std_logic_vector(15 downto 0) := x"0001";
+    REGIO_HARDWARE_VERSION       : std_logic_vector(31 downto 0) := x"12345678";
+    REGIO_USE_1WIRE_INTERFACE    : integer := c_YES; --c_YES,c_NO,c_MONITOR
+    REGIO_USE_VAR_ENDPOINT_ID    : integer range c_NO to c_YES   := c_NO;
+    CLOCK_FREQUENCY              : integer range 1 to 200        := 100;
+    TIMING_TRIGGER_RAW           : integer range 0 to 1 := c_YES;
+    --Configure data handler
+    DATA_INTERFACE_NUMBER        : integer range 1 to 16         := 1;
+    DATA_BUFFER_DEPTH            : integer range 9 to 14         := 9;
+    DATA_BUFFER_WIDTH            : integer range 1 to 32         := 32;
+    DATA_BUFFER_FULL_THRESH      : integer range 0 to 2**14-2    := 2**8;
+    TRG_RELEASE_AFTER_DATA       : integer range 0 to 1          := c_YES;
+    HEADER_BUFFER_DEPTH          : integer range 9 to 14         := 9;
+    HEADER_BUFFER_FULL_THRESH    : integer range 2**8 to 2**14-2 := 2**8
+    );
+
+  port(
+    --  Misc
+    CLK                          : in  std_logic;
+    RESET                        : in  std_logic;
+    CLK_EN                       : in  std_logic := '1';
+
+    --  Media direction port
+    MED_DATAREADY_OUT            : out std_logic;
+    MED_DATA_OUT                 : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_OUT           : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+    MED_READ_IN                  : in  std_logic;
+    MED_DATAREADY_IN             : in  std_logic;
+    MED_DATA_IN                  : in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_IN            : in  std_logic_vector (c_NUM_WIDTH-1 downto 0);
+    MED_READ_OUT                 : out std_logic;
+    MED_STAT_OP_IN               : in  std_logic_vector(15 downto 0);
+    MED_CTRL_OP_OUT              : out std_logic_vector(15 downto 0);
+
+    --Timing trigger in
+    TRG_TIMING_TRG_RECEIVED_IN   : in  std_logic;
+    --LVL1 trigger to FEE
+    LVL1_TRG_DATA_VALID_OUT      : out std_logic;    --trigger type, number, code, information are valid
+    LVL1_VALID_TIMING_TRG_OUT    : out std_logic;    --valid timing trigger has been received
+    LVL1_VALID_NOTIMING_TRG_OUT  : out std_logic;    --valid trigger without timing trigger has been received
+    LVL1_INVALID_TRG_OUT         : out std_logic;    --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
+
+    LVL1_TRG_TYPE_OUT            : out std_logic_vector(3 downto 0);
+    LVL1_TRG_NUMBER_OUT          : out std_logic_vector(15 downto 0);
+    LVL1_TRG_CODE_OUT            : out std_logic_vector(7 downto 0);
+    LVL1_TRG_INFORMATION_OUT     : out std_logic_vector(23 downto 0);
+    LVL1_INT_TRG_NUMBER_OUT      : out std_logic_vector(15 downto 0);  --internally generated trigger number, for informational uses only
+
+    --Information about trigger handler errors
+    TRG_MULTIPLE_TRG_OUT         : out std_logic;
+    TRG_TIMEOUT_DETECTED_OUT     : out std_logic;
+    TRG_SPURIOUS_TRG_OUT         : out std_logic;
+    TRG_MISSING_TMG_TRG_OUT      : out std_logic;
+    TRG_SPIKE_DETECTED_OUT       : out std_logic;
+
+    --Response from FEE
+    FEE_TRG_RELEASE_IN           : in  std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+    FEE_TRG_STATUSBITS_IN        : in  std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
+    FEE_DATA_IN                  : in  std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
+    FEE_DATA_WRITE_IN            : in  std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+    FEE_DATA_FINISHED_IN         : in  std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+    FEE_DATA_ALMOST_FULL_OUT     : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+
+    --Slow Control Port
+    --common registers
+    REGIO_COMMON_STAT_REG_IN     : in  std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+    REGIO_COMMON_CTRL_REG_OUT    : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+    REGIO_COMMON_STAT_STROBE_OUT : out std_logic_vector(std_COMSTATREG-1 downto 0);
+    REGIO_COMMON_CTRL_STROBE_OUT : out std_logic_vector(std_COMCTRLREG-1 downto 0);
+    --user defined registers
+    REGIO_STAT_REG_IN            : in  std_logic_vector(2**(REGIO_NUM_STAT_REGS)*32-1 downto 0) := (others => '0');
+    REGIO_CTRL_REG_OUT           : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)*32-1 downto 0);
+    REGIO_STAT_STROBE_OUT        : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
+    REGIO_CTRL_STROBE_OUT        : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+    --internal data port
+    BUS_ADDR_OUT                 : out std_logic_vector(16-1 downto 0);
+    BUS_DATA_OUT                 : out std_logic_vector(32-1 downto 0);
+    BUS_READ_ENABLE_OUT          : out std_logic;
+    BUS_WRITE_ENABLE_OUT         : out std_logic;
+    BUS_TIMEOUT_OUT              : out std_logic;
+    BUS_DATA_IN                  : in  std_logic_vector(32-1 downto 0) := (others => '0');
+    BUS_DATAREADY_IN             : in  std_logic                       := '0';
+    BUS_WRITE_ACK_IN             : in  std_logic                       := '0';
+    BUS_NO_MORE_DATA_IN          : in  std_logic                       := '0';
+    BUS_UNKNOWN_ADDR_IN          : in  std_logic                       := '0';
+    --Onewire
+    ONEWIRE_INOUT                : inout std_logic;  --temperature sensor
+    ONEWIRE_MONITOR_IN           : in  std_logic := '0';
+    ONEWIRE_MONITOR_OUT          : out std_logic;
+    --Config endpoint id, if not statically assigned
+    REGIO_VAR_ENDPOINT_ID        : in  std_logic_vector (15 downto 0) := (others => '0');
+
+    --Timing registers
+    TIME_GLOBAL_OUT              : out std_logic_vector (31 downto 0); --global time, microseconds
+    TIME_LOCAL_OUT               : out std_logic_vector ( 7 downto 0); --local time running with chip frequency
+    TIME_SINCE_LAST_TRG_OUT      : out std_logic_vector (31 downto 0); --local time, resetted with each trigger
+    TIME_TICKS_OUT               : out std_logic_vector ( 1 downto 0); --bit 1 ms-tick, 0 us-tick
+
+    --Debugging & Status information
+    STAT_DEBUG_IPU               : out std_logic_vector (31 downto 0);
+    STAT_DEBUG_1                 : out std_logic_vector (31 downto 0);
+    STAT_DEBUG_2                 : out std_logic_vector (31 downto 0);
+    STAT_DEBUG_DATA_HANDLER_OUT  : out std_logic_vector (31 downto 0);
+    STAT_DEBUG_IPU_HANDLER_OUT   : out std_logic_vector (31 downto 0);
+    CTRL_MPLEX                   : in  std_logic_vector (31 downto 0) := (others => '0');
+    IOBUF_CTRL_GEN               : in  std_logic_vector (4*32-1 downto 0) := (others => '0');
+    STAT_ONEWIRE                 : out std_logic_vector (31 downto 0);
+    STAT_ADDR_DEBUG              : out std_logic_vector (15 downto 0);
+    STAT_TRIGGER_OUT             : out std_logic_vector (79 downto 0);
+    DEBUG_LVL1_HANDLER_OUT       : out std_logic_vector (15 downto 0)
+    );
+end entity;
+
+
+
+
+
+architecture trb_net16_endpoint_data_concentrator_handler_arch of trb_net16_endpoint_data_concentrator_handler is
+
+component trb_net16_endpoint_data_concentrator is
+  generic (
+    USE_CHANNEL                  : channel_config_t := (c_NO,c_NO,c_NO,c_YES);
+    IBUF_DEPTH                   : channel_config_t := (6,6,6,6);
+    FIFO_TO_INT_DEPTH            : channel_config_t := (6,6,6,6);
+    FIFO_TO_APL_DEPTH            : channel_config_t := (1,1,1,1);
+    IBUF_SECURE_MODE             : channel_config_t := (c_NO,c_NO,c_NO,c_YES);
+    API_SECURE_MODE_TO_APL       : channel_config_t := (c_NO,c_NO,c_NO,c_YES);
+    API_SECURE_MODE_TO_INT       : channel_config_t := (c_NO,c_NO,c_NO,c_YES);
+    OBUF_DATA_COUNT_WIDTH        : integer range 0 to 7 := std_DATA_COUNT_WIDTH;
+    INIT_CAN_SEND_DATA           : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
+    REPLY_CAN_SEND_DATA          : channel_config_t := (c_NO,c_NO,c_NO,c_YES);
+    REPLY_CAN_RECEIVE_DATA       : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
+    USE_CHECKSUM                 : channel_config_t := (c_NO,c_NO,c_NO,c_YES);
+    APL_WRITE_ALL_WORDS          : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
+    ADDRESS_MASK                 : std_logic_vector(15 downto 0) := x"FFFF";
+    BROADCAST_BITMASK            : std_logic_vector(7 downto 0) := x"FF";
+    BROADCAST_SPECIAL_ADDR       : std_logic_vector(7 downto 0) := x"FF";
+    TIMING_TRIGGER_RAW           : integer range 0 to 1 := c_YES;
+    REGIO_NUM_STAT_REGS          : integer range 0 to 6 := 3; --log2 of number of status registers
+    REGIO_NUM_CTRL_REGS          : integer range 0 to 6 := 3; --log2 of number of ctrl registers
+    --standard values for output registers
+    REGIO_INIT_CTRL_REGS         : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0');
+    --set to 0 for unused ctrl registers to save resources
+    REGIO_USED_CTRL_REGS         : std_logic_vector(2**(4)-1 downto 0)    := (others => '1');
+    --set to 0 for each unused bit in a register
+    REGIO_USED_CTRL_BITMASK      : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1');
+    REGIO_USE_DAT_PORT           : integer range 0 to 1 := c_YES;  --internal data port
+    REGIO_INIT_ADDRESS           : std_logic_vector(15 downto 0) := x"FFFF";
+    REGIO_INIT_UNIQUE_ID         : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
+    REGIO_INIT_BOARD_INFO        : std_logic_vector(31 downto 0) := x"1111_2222";
+    REGIO_INIT_ENDPOINT_ID       : std_logic_vector(15 downto 0) := x"0001";
+    REGIO_COMPILE_TIME           : std_logic_vector(31 downto 0) := x"00000000";
+    REGIO_COMPILE_VERSION        : std_logic_vector(15 downto 0) := x"0001";
+    REGIO_HARDWARE_VERSION       : std_logic_vector(31 downto 0) := x"12345678";
+    REGIO_USE_1WIRE_INTERFACE    : integer := c_YES; --c_YES,c_NO,c_MONITOR
+    REGIO_USE_VAR_ENDPOINT_ID    : integer range c_NO to c_YES := c_NO;
+    CLOCK_FREQUENCY              : integer range 1 to 200 := 100
+    );
+
+  port(
+    --  Misc
+    CLK                          : in std_logic;
+    RESET                        : in std_logic;
+    CLK_EN                       : in std_logic := '1';
+
+    --  Media direction port
+    MED_DATAREADY_OUT            : out std_logic;
+    MED_DATA_OUT                 : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_OUT           : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+    MED_READ_IN                  : in  std_logic;
+    MED_DATAREADY_IN             : in  std_logic;
+    MED_DATA_IN                  : in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_IN            : in  std_logic_vector (c_NUM_WIDTH-1 downto 0);
+    MED_READ_OUT                 : out std_logic;
+    MED_STAT_OP_IN               : in  std_logic_vector(15 downto 0);
+    MED_CTRL_OP_OUT              : out std_logic_vector(15 downto 0);
+
+    -- LVL1 trigger APL
+    TRG_TIMING_TRG_RECEIVED_IN   : in  std_logic;    --strobe when timing trigger received or real timing trigger signal
+
+    LVL1_TRG_DATA_VALID_OUT      : out std_logic;    --trigger type, number, code, information are valid
+    LVL1_TRG_VALID_TIMING_OUT    : out std_logic;    --valid timing trigger has been received
+    LVL1_TRG_VALID_NOTIMING_OUT  : out std_logic;    --valid trigger without timing trigger has been received
+    LVL1_TRG_INVALID_OUT         : out std_logic;    --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
+
+    LVL1_TRG_TYPE_OUT            : out std_logic_vector(3 downto 0);
+    LVL1_TRG_NUMBER_OUT          : out std_logic_vector(15 downto 0);
+    LVL1_TRG_CODE_OUT            : out std_logic_vector(7 downto 0);
+    LVL1_TRG_INFORMATION_OUT     : out std_logic_vector(23 downto 0);
+
+    LVL1_ERROR_PATTERN_IN        : in  std_logic_vector(31 downto 0) := x"00000000";
+    LVL1_TRG_RELEASE_IN          : in  std_logic := '0';
+    LVL1_INT_TRG_NUMBER_OUT      : out std_logic_vector(15 downto 0);  --internally generated trigger number, for informational uses only
+
+    --Information about trigger handler errors
+    TRG_MULTIPLE_TRG_OUT         : out std_logic;
+    TRG_TIMEOUT_DETECTED_OUT     : out std_logic;
+    TRG_SPURIOUS_TRG_OUT         : out std_logic;
+    TRG_MISSING_TMG_TRG_OUT      : out std_logic;
+    TRG_SPIKE_DETECTED_OUT       : out std_logic;
+    TRG_LONG_TRG_OUT             : out std_logic;
+
+    --Data Port
+    IPU_NUMBER_OUT               : out std_logic_vector (15 downto 0);
+    IPU_READOUT_TYPE_OUT         : out std_logic_vector (3 downto 0);
+    IPU_INFORMATION_OUT          : out std_logic_vector (7 downto 0);
+    --start strobe
+    IPU_START_READOUT_OUT        : out std_logic;
+    --detector data, equipped with DHDR
+    IPU_DATA_IN                  : in  std_logic_vector (31 downto 0);
+    IPU_DATAREADY_IN             : in  std_logic;
+    --no more data, end transfer, send TRM
+    IPU_READOUT_FINISHED_IN      : in  std_logic;
+    --will be low every second cycle due to 32bit -> 16bit conversion
+    IPU_READ_OUT                 : out std_logic;
+    IPU_LENGTH_IN                : in  std_logic_vector (15 downto 0);
+    IPU_ERROR_PATTERN_IN         : in  std_logic_vector (31 downto 0);
+
+
+    -- Slow Control Data Port
+    REGIO_COMMON_STAT_REG_IN  : in  std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+    REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+    REGIO_REGISTERS_IN        : in  std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
+    REGIO_REGISTERS_OUT       : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+    COMMON_STAT_REG_STROBE    : out std_logic_vector(std_COMSTATREG-1 downto 0);
+    COMMON_CTRL_REG_STROBE    : out std_logic_vector(std_COMCTRLREG-1 downto 0);
+    STAT_REG_STROBE           : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
+    CTRL_REG_STROBE           : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+    --following ports only used when using internal data port
+    REGIO_ADDR_OUT            : out std_logic_vector(16-1 downto 0);
+    REGIO_READ_ENABLE_OUT     : out std_logic;
+    REGIO_WRITE_ENABLE_OUT    : out std_logic;
+    REGIO_DATA_OUT            : out std_logic_vector(32-1 downto 0);
+    REGIO_DATA_IN             : in  std_logic_vector(32-1 downto 0) := (others => '0');
+    REGIO_DATAREADY_IN        : in  std_logic := '0';
+    REGIO_NO_MORE_DATA_IN     : in  std_logic := '0';
+    REGIO_WRITE_ACK_IN        : in  std_logic := '0';
+    REGIO_UNKNOWN_ADDR_IN     : in  std_logic := '0';
+    REGIO_TIMEOUT_OUT         : out std_logic;
+    --IDRAM is used if no 1-wire interface, onewire used otherwise
+    REGIO_IDRAM_DATA_IN       : in  std_logic_vector(15 downto 0) := (others => '0');
+    REGIO_IDRAM_DATA_OUT      : out std_logic_vector(15 downto 0);
+    REGIO_IDRAM_ADDR_IN       : in  std_logic_vector(2 downto 0) := "000";
+    REGIO_IDRAM_WR_IN         : in  std_logic := '0';
+    REGIO_ONEWIRE_INOUT       : inout std_logic;  --temperature sensor
+    REGIO_ONEWIRE_MONITOR_IN  : in  std_logic := '0';
+    REGIO_ONEWIRE_MONITOR_OUT : out std_logic;
+    REGIO_VAR_ENDPOINT_ID     : in  std_logic_vector(15 downto 0) := (others => '0');
+
+    GLOBAL_TIME_OUT           : out std_logic_vector(31 downto 0); --global time, microseconds
+    LOCAL_TIME_OUT            : out std_logic_vector(7 downto 0);  --local time running with chip frequency
+    TIME_SINCE_LAST_TRG_OUT   : out std_logic_vector(31 downto 0); --local time, resetted with each trigger
+    TIMER_TICKS_OUT           : out std_logic_vector(1 downto 0);  --bit 1 ms-tick, 0 us-tick
+    --Debugging & Status information
+    STAT_DEBUG_IPU            : out std_logic_vector (31 downto 0);
+    STAT_DEBUG_1              : out std_logic_vector (31 downto 0);
+    STAT_DEBUG_2              : out std_logic_vector (31 downto 0);
+    MED_STAT_OP               : out std_logic_vector (15 downto 0);
+    CTRL_MPLEX                : in  std_logic_vector (31 downto 0) := (others => '0');
+    IOBUF_CTRL_GEN            : in  std_logic_vector (4*32-1 downto 0) := (others => '0');
+    STAT_ONEWIRE              : out std_logic_vector (31 downto 0);
+    STAT_ADDR_DEBUG           : out std_logic_vector (15 downto 0);
+    STAT_TRIGGER_OUT          : out std_logic_vector (79 downto 0);
+    DEBUG_LVL1_HANDLER_OUT    : out std_logic_vector (15 downto 0)
+    );
+end component;
+
+
+  signal lvl1_data_valid_i       : std_logic;
+  signal lvl1_valid_i            : std_logic;
+  signal lvl1_valid_timing_i     : std_logic;
+  signal lvl1_valid_notiming_i   : std_logic;
+  signal lvl1_invalid_i          : std_logic;
+  signal lvl1_type_i             : std_logic_vector ( 3 downto 0);
+  signal lvl1_number_i           : std_logic_vector (15 downto 0);
+  signal lvl1_code_i             : std_logic_vector ( 7 downto 0);
+  signal lvl1_information_i      : std_logic_vector (23 downto 0);
+  signal lvl1_error_pattern_i    : std_logic_vector (31 downto 0);
+  signal lvl1_release_i          : std_logic;
+  signal lvl1_int_trg_number_i   : std_logic_vector (15 downto 0);
+
+  signal ipu_number_i            : std_logic_vector (15 downto 0);
+  signal ipu_readout_type_i      : std_logic_vector ( 3 downto 0);
+  signal ipu_information_i       : std_logic_vector ( 7 downto 0);
+  signal ipu_start_readout_i     : std_logic;
+  signal ipu_data_i              : std_logic_vector (31 downto 0);
+  signal ipu_dataready_i         : std_logic;
+  signal ipu_readout_finished_i  : std_logic;
+  signal ipu_read_i              : std_logic;
+  signal ipu_length_i            : std_logic_vector (15 downto 0);
+  signal ipu_error_pattern_i     : std_logic_vector (31 downto 0);
+  signal reset_ipu_i             : std_logic;
+
+  signal common_stat_reg_i       : std_logic_vector (std_COMSTATREG*32-1 downto 0);
+  signal common_ctrl_reg_i       : std_logic_vector (std_COMCTRLREG*32-1 downto 0);
+  signal common_stat_strobe_i    : std_logic_vector (std_COMSTATREG-1 downto 0);
+  signal common_ctrl_strobe_i    : std_logic_vector (std_COMCTRLREG-1 downto 0);
+  signal stat_reg_i              : std_logic_vector (2**(REGIO_NUM_STAT_REGS)*32-1 downto 0);
+  signal ctrl_reg_i              : std_logic_vector (2**(REGIO_NUM_CTRL_REGS)*32-1 downto 0);
+  signal stat_strobe_i           : std_logic_vector (2**(REGIO_NUM_STAT_REGS)-1 downto 0);
+  signal ctrl_strobe_i           : std_logic_vector (2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+
+  signal regio_addr_i            : std_logic_vector (15 downto 0);
+  signal regio_read_enable_i     : std_logic;
+  signal regio_write_enable_i    : std_logic;
+  signal regio_data_out_i        : std_logic_vector (31 downto 0);
+  signal regio_data_in_i         : std_logic_vector (31 downto 0);
+  signal regio_dataready_i       : std_logic;
+  signal regio_nomoredata_i      : std_logic;
+  signal regio_write_ack_i       : std_logic;
+  signal regio_unknown_addr_i    : std_logic;
+  signal regio_timeout_i         : std_logic;
+
+  signal time_global_i           : std_logic_vector (31 downto 0);
+  signal time_local_i            : std_logic_vector ( 7 downto 0);
+  signal time_since_last_trg_i   : std_logic_vector (31 downto 0);
+  signal time_ticks_i            : std_logic_vector ( 1 downto 0);
+
+  signal stat_handler_i          : std_logic_vector (127 downto 0);
+  signal stat_data_buffer_level  : std_logic_vector (DATA_INTERFACE_NUMBER*32-1 downto 0);
+  signal stat_header_buffer_level: std_logic_vector (31 downto 0);
+
+  signal dbuf_read_enable        : std_logic;
+  signal dbuf_addr               : std_logic_vector (3 downto 0);
+  signal dbuf_data_in            : std_logic_vector (31 downto 0);
+  signal dbuf_dataready          : std_logic;
+  signal dbuf_unknown_addr       : std_logic;
+
+  signal tbuf_dataready          : std_logic;
+  signal tbuf_read_enable        : std_logic;
+
+  signal dummy                   : std_logic_vector(300 downto 0);
+  signal write_enable            : std_logic_vector(6 downto 0);
+  signal read_enable             : std_logic_vector(6 downto 0);
+  signal last_write_enable       : std_logic_vector(6 downto 0);
+  signal last_read_enable        : std_logic_vector(6 downto 0);
+
+  signal debug_data_handler_i    : std_logic_vector(31 downto 0);
+  signal debug_ipu_handler_i     : std_logic_vector(31 downto 0);
+
+  signal int_multiple_trg          : std_logic;
+  signal int_lvl1_timeout_detected : std_logic;
+  signal int_lvl1_spurious_trg     : std_logic;
+  signal int_lvl1_missing_tmg_trg  : std_logic;
+  signal int_spike_detected        : std_logic;
+  signal int_lvl1_long_trg         : std_logic;
+  signal tmg_trg_error_i           : std_logic;
+
+  signal stat_buffer_i             : std_logic_vector(31 downto 0);
+  signal stat_buffer_read          : std_logic;
+  signal stat_buffer_ready         : std_logic;
+  signal stat_buffer_unknown       : std_logic;
+  signal stat_buffer_address       : std_logic_vector(4 downto 0);
+
+
+begin
+---------------------------------------------------------------------------
+-- TrbNet Endpoint
+---------------------------------------------------------------------------
+
+  THE_ENDPOINT: trb_net16_endpoint_data_concentrator ---- trb_net16_endpoint_hades_full
+    generic map(
+      IBUF_DEPTH                 => IBUF_DEPTH,
+      FIFO_TO_INT_DEPTH          => FIFO_TO_INT_DEPTH,
+      FIFO_TO_APL_DEPTH          => FIFO_TO_APL_DEPTH,
+      APL_WRITE_ALL_WORDS        => APL_WRITE_ALL_WORDS,
+      ADDRESS_MASK               => ADDRESS_MASK,
+      BROADCAST_BITMASK          => BROADCAST_BITMASK,
+      BROADCAST_SPECIAL_ADDR     => BROADCAST_SPECIAL_ADDR,
+      REGIO_NUM_STAT_REGS        => REGIO_NUM_STAT_REGS,
+      REGIO_NUM_CTRL_REGS        => REGIO_NUM_CTRL_REGS,
+      REGIO_INIT_CTRL_REGS       => REGIO_INIT_CTRL_REGS,
+      REGIO_INIT_ADDRESS         => REGIO_INIT_ADDRESS,
+      REGIO_INIT_BOARD_INFO      => REGIO_INIT_BOARD_INFO,
+      REGIO_INIT_ENDPOINT_ID     => REGIO_INIT_ENDPOINT_ID,
+      REGIO_COMPILE_TIME         => REGIO_COMPILE_TIME,
+      REGIO_COMPILE_VERSION      => REGIO_COMPILE_VERSION,
+      REGIO_HARDWARE_VERSION     => REGIO_HARDWARE_VERSION,
+      REGIO_USE_1WIRE_INTERFACE  => REGIO_USE_1WIRE_INTERFACE,
+      REGIO_USE_VAR_ENDPOINT_ID  => REGIO_USE_VAR_ENDPOINT_ID,
+      TIMING_TRIGGER_RAW         => TIMING_TRIGGER_RAW,
+      CLOCK_FREQUENCY            => CLOCK_FREQUENCY
+      )
+    port map(
+      CLK                        => CLK,
+      RESET                      => RESET,
+      CLK_EN                     => CLK_EN,
+
+      MED_DATAREADY_OUT          => MED_DATAREADY_OUT,
+      MED_DATA_OUT               => MED_DATA_OUT,
+      MED_PACKET_NUM_OUT         => MED_PACKET_NUM_OUT,
+      MED_READ_IN                => MED_READ_IN,
+      MED_DATAREADY_IN           => MED_DATAREADY_IN,
+      MED_DATA_IN                => MED_DATA_IN,
+      MED_PACKET_NUM_IN          => MED_PACKET_NUM_IN,
+      MED_READ_OUT               => MED_READ_OUT,
+      MED_STAT_OP_IN             => MED_STAT_OP_IN,
+      MED_CTRL_OP_OUT            => MED_CTRL_OP_OUT,
+
+      -- LVL1 trigger APL
+      TRG_TIMING_TRG_RECEIVED_IN => TRG_TIMING_TRG_RECEIVED_IN,
+      LVL1_TRG_DATA_VALID_OUT    => lvl1_data_valid_i,
+      LVL1_TRG_VALID_TIMING_OUT  => lvl1_valid_timing_i,
+      LVL1_TRG_VALID_NOTIMING_OUT=> lvl1_valid_notiming_i,
+      LVL1_TRG_INVALID_OUT       => lvl1_invalid_i,
+      LVL1_TRG_TYPE_OUT          => lvl1_type_i,
+      LVL1_TRG_NUMBER_OUT        => lvl1_number_i,
+      LVL1_TRG_CODE_OUT          => lvl1_code_i,
+      LVL1_TRG_INFORMATION_OUT   => lvl1_information_i,
+      LVL1_ERROR_PATTERN_IN      => lvl1_error_pattern_i,
+      LVL1_TRG_RELEASE_IN        => lvl1_release_i,
+      LVL1_INT_TRG_NUMBER_OUT    => lvl1_int_trg_number_i,
+
+      --Information about trigger handler errors
+      TRG_SPIKE_DETECTED_OUT     => int_spike_detected,
+      TRG_SPURIOUS_TRG_OUT       => int_lvl1_spurious_trg,
+      TRG_TIMEOUT_DETECTED_OUT   => int_lvl1_timeout_detected,
+      TRG_MULTIPLE_TRG_OUT       => int_multiple_trg,
+      TRG_MISSING_TMG_TRG_OUT    => int_lvl1_missing_tmg_trg,
+      TRG_LONG_TRG_OUT           => int_lvl1_long_trg,
+      --Data Port
+      IPU_NUMBER_OUT             => ipu_number_i,
+      IPU_READOUT_TYPE_OUT       => ipu_readout_type_i,
+      IPU_INFORMATION_OUT        => ipu_information_i,
+      IPU_START_READOUT_OUT      => ipu_start_readout_i,
+      IPU_DATA_IN                => ipu_data_i,
+      IPU_DATAREADY_IN           => ipu_dataready_i,
+      IPU_READOUT_FINISHED_IN    => ipu_readout_finished_i,
+      IPU_READ_OUT               => ipu_read_i,
+      IPU_LENGTH_IN              => ipu_length_i,
+      IPU_ERROR_PATTERN_IN       => ipu_error_pattern_i,
+
+      -- Slow Control Data Port
+      REGIO_COMMON_STAT_REG_IN   => common_stat_reg_i,
+      REGIO_COMMON_CTRL_REG_OUT  => common_ctrl_reg_i,
+      REGIO_REGISTERS_IN         => stat_reg_i,
+      REGIO_REGISTERS_OUT        => ctrl_reg_i,
+      COMMON_STAT_REG_STROBE     => common_stat_strobe_i,
+      COMMON_CTRL_REG_STROBE     => common_ctrl_strobe_i,
+      STAT_REG_STROBE            => stat_strobe_i,
+      CTRL_REG_STROBE            => ctrl_strobe_i,
+
+      REGIO_ADDR_OUT             => regio_addr_i,
+      REGIO_READ_ENABLE_OUT      => regio_read_enable_i,
+      REGIO_WRITE_ENABLE_OUT     => regio_write_enable_i,
+      REGIO_DATA_OUT             => regio_data_out_i,
+      REGIO_DATA_IN              => regio_data_in_i,
+      REGIO_DATAREADY_IN         => regio_dataready_i,
+      REGIO_NO_MORE_DATA_IN      => regio_nomoredata_i,
+      REGIO_WRITE_ACK_IN         => regio_write_ack_i,
+      REGIO_UNKNOWN_ADDR_IN      => regio_unknown_addr_i,
+      REGIO_TIMEOUT_OUT          => regio_timeout_i,
+
+      REGIO_ONEWIRE_INOUT        => ONEWIRE_INOUT,
+      REGIO_ONEWIRE_MONITOR_IN   => ONEWIRE_MONITOR_IN,
+      REGIO_ONEWIRE_MONITOR_OUT  => ONEWIRE_MONITOR_OUT,
+      REGIO_VAR_ENDPOINT_ID      => REGIO_VAR_ENDPOINT_ID,
+
+      GLOBAL_TIME_OUT            => time_global_i,
+      LOCAL_TIME_OUT             => time_local_i,
+      TIME_SINCE_LAST_TRG_OUT    => time_since_last_trg_i,
+      TIMER_TICKS_OUT            => time_ticks_i,
+
+      STAT_DEBUG_IPU             => open,
+      STAT_DEBUG_1               => open,
+      STAT_DEBUG_2               => open,
+      MED_STAT_OP                => open,
+      CTRL_MPLEX                 => (others => '0'),
+      IOBUF_CTRL_GEN             => (others => '0'),
+      STAT_ONEWIRE               => open,
+      STAT_ADDR_DEBUG            => open,
+      STAT_TRIGGER_OUT           => STAT_TRIGGER_OUT,      
+      DEBUG_LVL1_HANDLER_OUT     => DEBUG_LVL1_HANDLER_OUT
+      );
+
+---------------------------------------------------------------------------
+-- RegIO Bus Handler
+---------------------------------------------------------------------------
+
+  THE_INTERNAL_BUS_HANDLER : trb_net16_regio_bus_handler
+    generic map(
+      PORT_NUMBER                => 7,
+      PORT_ADDRESSES             => (0 => x"8000", 1 => x"7100", 2 => x"7110", 3 => x"7200", 4 => x"7201", 5 => x"7202", 6 => x"7300", others => x"0000"),
+      PORT_ADDR_MASK             => (0 => 15,      1 => 4,       2 => 0,       3 => 0,       4 => 0,       5 => 0,       6 => 5,       others => 0)
+      )
+    port map(
+      CLK                        => CLK,
+      RESET                      => RESET,
+
+      DAT_ADDR_IN                => regio_addr_i,
+      DAT_DATA_IN                => regio_data_out_i,
+      DAT_DATA_OUT               => regio_data_in_i,
+      DAT_READ_ENABLE_IN         => regio_read_enable_i,
+      DAT_WRITE_ENABLE_IN        => regio_write_enable_i,
+      DAT_TIMEOUT_IN             => regio_timeout_i,
+      DAT_DATAREADY_OUT          => regio_dataready_i,
+      DAT_WRITE_ACK_OUT          => regio_write_ack_i,
+      DAT_NO_MORE_DATA_OUT       => regio_nomoredata_i,
+      DAT_UNKNOWN_ADDR_OUT       => regio_unknown_addr_i,
+
+--       BUS_READ_ENABLE_OUT(0)     => BUS_READ_ENABLE_OUT,
+--       BUS_WRITE_ENABLE_OUT(0)    => BUS_WRITE_ENABLE_OUT,
+--       BUS_DATA_OUT(31 downto 0)  => BUS_DATA_OUT,
+--       BUS_ADDR_OUT(15 downto 0)  => BUS_ADDR_OUT,
+--       BUS_TIMEOUT_OUT(0)         => BUS_TIMEOUT_OUT,
+--       BUS_DATA_IN(31 downto 0)   => BUS_DATA_IN,
+--       BUS_DATAREADY_IN(0)        => BUS_DATAREADY_IN,
+--       BUS_WRITE_ACK_IN(0)        => BUS_WRITE_ACK_IN,
+--       BUS_NO_MORE_DATA_IN(0)     => BUS_NO_MORE_DATA_IN,
+--       BUS_UNKNOWN_ADDR_IN(0)     => BUS_UNKNOWN_ADDR_IN,
+--
+--       BUS_READ_ENABLE_OUT(1)     => dbuf_read_enable,
+--       BUS_WRITE_ENABLE_OUT(1)    => open,
+--       BUS_DATA_OUT(63 downto 32) => open,
+--       BUS_ADDR_OUT(19 downto 16) => dbuf_addr,
+--       BUS_ADDR_OUT(31 downto 20) => open,
+--       BUS_TIMEOUT_OUT(1)         => open,
+--       BUS_DATA_IN(63 downto 32)  => dbuf_data_in,
+--       BUS_DATAREADY_IN(1)        => dbuf_dataready,
+--       BUS_WRITE_ACK_IN(1)        => '0',
+--       BUS_NO_MORE_DATA_IN(1)     => '0',
+--       BUS_UNKNOWN_ADDR_IN(1)     => dbuf_unknown_addr,
+--
+--       BUS_READ_ENABLE_OUT(2)     => tbuf_read_enable,
+--       BUS_WRITE_ENABLE_OUT(2)    => open,
+--       BUS_DATA_OUT(95 downto 64) => open,
+--       BUS_ADDR_OUT(47 downto 32) => open,
+--       BUS_TIMEOUT_OUT(1)         => open,
+--       BUS_DATA_IN(95 downto 64)  => stat_header_buffer_level,
+--       BUS_DATAREADY_IN(2)        => tbuf_dataready,
+--       BUS_WRITE_ACK_IN(2)        => '0',
+--       BUS_NO_MORE_DATA_IN(2)     => '0',
+--       BUS_UNKNOWN_ADDR_IN(2)     => '0'
+
+--Fucking Modelsim wants it like this...
+      BUS_READ_ENABLE_OUT(0)     => BUS_READ_ENABLE_OUT,
+      BUS_READ_ENABLE_OUT(1)     => dbuf_read_enable,
+      BUS_READ_ENABLE_OUT(2)     => tbuf_read_enable,
+      BUS_READ_ENABLE_OUT(3)     => read_enable(3),
+      BUS_READ_ENABLE_OUT(4)     => read_enable(4),
+      BUS_READ_ENABLE_OUT(5)     => read_enable(5),
+      BUS_READ_ENABLE_OUT(6)     => stat_buffer_read,
+      BUS_WRITE_ENABLE_OUT(0)    => BUS_WRITE_ENABLE_OUT,
+      BUS_WRITE_ENABLE_OUT(1)    => dummy(0),
+      BUS_WRITE_ENABLE_OUT(2)    => write_enable(2),
+      BUS_WRITE_ENABLE_OUT(3)    => write_enable(3),
+      BUS_WRITE_ENABLE_OUT(4)    => write_enable(4),
+      BUS_WRITE_ENABLE_OUT(5)    => write_enable(5),
+      BUS_WRITE_ENABLE_OUT(6)    => write_enable(6),
+      BUS_DATA_OUT(31 downto 0)  => BUS_DATA_OUT,
+      BUS_DATA_OUT(63 downto 32) => dummy(33 downto 2),
+      BUS_DATA_OUT(95 downto 64) => dummy(65 downto 34),
+      BUS_DATA_OUT(191 downto 96) => dummy(191 downto 96),
+      BUS_DATA_OUT(223 downto 192)=> dummy(291 downto 260),
+      BUS_ADDR_OUT(15 downto 0)  => BUS_ADDR_OUT,
+      BUS_ADDR_OUT(19 downto 16) => dbuf_addr,
+      BUS_ADDR_OUT(31 downto 20) => dummy(77 downto 66),
+      BUS_ADDR_OUT(47 downto 32) => dummy(93 downto 78),
+      BUS_ADDR_OUT(95 downto 48) => dummy(242 downto 195),
+      BUS_ADDR_OUT(100 downto 96)=> stat_buffer_address,
+      BUS_ADDR_OUT(111 downto 101)=> dummy(259 downto 249),
+      BUS_TIMEOUT_OUT(0)         => BUS_TIMEOUT_OUT,
+      BUS_TIMEOUT_OUT(1)         => dummy(94),
+      BUS_TIMEOUT_OUT(2)         => dummy(95),
+      BUS_TIMEOUT_OUT(3)         => dummy(192),
+      BUS_TIMEOUT_OUT(4)         => dummy(193),
+      BUS_TIMEOUT_OUT(5)         => dummy(194),
+      BUS_TIMEOUT_OUT(6)         => dummy(243),
+      BUS_DATA_IN(31 downto 0)   => BUS_DATA_IN,
+      BUS_DATA_IN(63 downto 32)  => dbuf_data_in,
+      BUS_DATA_IN(95 downto 64)  => stat_header_buffer_level,
+      BUS_DATA_IN(191 downto 96) => stat_handler_i(95 downto 0),
+      BUS_DATA_IN(223 downto 192)=> stat_buffer_i,
+      BUS_DATAREADY_IN(0)        => BUS_DATAREADY_IN,
+      BUS_DATAREADY_IN(1)        => dbuf_dataready,
+      BUS_DATAREADY_IN(2)        => tbuf_dataready,
+      BUS_DATAREADY_IN(3)        => last_read_enable(3),
+      BUS_DATAREADY_IN(4)        => last_read_enable(4),
+      BUS_DATAREADY_IN(5)        => last_read_enable(5),
+      BUS_DATAREADY_IN(6)        => stat_buffer_ready,
+      BUS_WRITE_ACK_IN(0)        => BUS_WRITE_ACK_IN,
+      BUS_WRITE_ACK_IN(1)        => '0',
+      BUS_WRITE_ACK_IN(2)        => '0',
+      BUS_WRITE_ACK_IN(3)        => '0',
+      BUS_WRITE_ACK_IN(4)        => '0',
+      BUS_WRITE_ACK_IN(5)        => '0',
+      BUS_WRITE_ACK_IN(6)        => '0',
+      BUS_NO_MORE_DATA_IN(0)     => BUS_NO_MORE_DATA_IN,
+      BUS_NO_MORE_DATA_IN(1)     => '0',
+      BUS_NO_MORE_DATA_IN(2)     => '0',
+      BUS_NO_MORE_DATA_IN(3)     => '0',
+      BUS_NO_MORE_DATA_IN(4)     => '0',
+      BUS_NO_MORE_DATA_IN(5)     => '0',
+      BUS_NO_MORE_DATA_IN(6)     => '0',
+      BUS_UNKNOWN_ADDR_IN(0)     => BUS_UNKNOWN_ADDR_IN,
+      BUS_UNKNOWN_ADDR_IN(1)     => dbuf_unknown_addr,
+      BUS_UNKNOWN_ADDR_IN(2)     => last_write_enable(2),
+      BUS_UNKNOWN_ADDR_IN(3)     => last_write_enable(3),
+      BUS_UNKNOWN_ADDR_IN(4)     => last_write_enable(4),
+      BUS_UNKNOWN_ADDR_IN(5)     => last_write_enable(5),
+      BUS_UNKNOWN_ADDR_IN(6)     => stat_buffer_unknown
+      );
+
+  proc_ack_strobes : process(CLK)
+    begin
+      if rising_edge(CLK) then
+        last_write_enable <= write_enable;
+        last_read_enable  <= read_enable;
+      end if;
+    end process;
+
+
+---------------------------------------------------------------------------
+-- Data and IPU Handler
+---------------------------------------------------------------------------
+
+  THE_HANDLER_TRIGGER_DATA : handler_trigger_and_data
+    generic map(
+      DATA_INTERFACE_NUMBER      => DATA_INTERFACE_NUMBER,
+      DATA_BUFFER_DEPTH          => DATA_BUFFER_DEPTH,
+      DATA_BUFFER_WIDTH          => DATA_BUFFER_WIDTH,
+      DATA_BUFFER_FULL_THRESH    => DATA_BUFFER_FULL_THRESH,
+      TRG_RELEASE_AFTER_DATA     => TRG_RELEASE_AFTER_DATA,
+      HEADER_BUFFER_DEPTH        => HEADER_BUFFER_DEPTH,
+      HEADER_BUFFER_FULL_THRESH  => HEADER_BUFFER_FULL_THRESH
+      )
+    port map(
+      CLOCK                      => CLK,
+      RESET                      => RESET,
+      RESET_IPU                  => reset_ipu_i,
+      --LVL1 channel
+      LVL1_VALID_TRIGGER_IN      => lvl1_valid_i,
+      LVL1_INT_TRG_NUMBER_IN     => lvl1_int_trg_number_i,
+      LVL1_TRG_DATA_VALID_IN     => lvl1_data_valid_i,
+      LVL1_TRG_TYPE_IN           => lvl1_type_i,
+      LVL1_TRG_NUMBER_IN         => lvl1_number_i,
+      LVL1_TRG_CODE_IN           => lvl1_code_i,
+      LVL1_TRG_INFORMATION_IN    => lvl1_information_i,
+      LVL1_ERROR_PATTERN_OUT     => lvl1_error_pattern_i,
+      LVL1_TRG_RELEASE_OUT       => lvl1_release_i,
+
+      --IPU channel
+      IPU_NUMBER_IN              => ipu_number_i,
+      IPU_INFORMATION_IN         => ipu_information_i,
+      IPU_READOUT_TYPE_IN        => ipu_readout_type_i,
+      IPU_START_READOUT_IN       => ipu_start_readout_i,
+      IPU_DATA_OUT               => ipu_data_i,
+      IPU_DATAREADY_OUT          => ipu_dataready_i,
+      IPU_READOUT_FINISHED_OUT   => ipu_readout_finished_i,
+      IPU_READ_IN                => ipu_read_i,
+      IPU_LENGTH_OUT             => ipu_length_i,
+      IPU_ERROR_PATTERN_OUT      => ipu_error_pattern_i,
+
+      --FEE Input
+      FEE_TRG_RELEASE_IN         => FEE_TRG_RELEASE_IN,
+      FEE_TRG_STATUSBITS_IN      => FEE_TRG_STATUSBITS_IN,
+      FEE_DATA_IN                => FEE_DATA_IN,
+      FEE_DATA_WRITE_IN          => FEE_DATA_WRITE_IN,
+      FEE_DATA_FINISHED_IN       => FEE_DATA_FINISHED_IN,
+      FEE_DATA_ALMOST_FULL_OUT   => FEE_DATA_ALMOST_FULL_OUT,
+
+      TMG_TRG_ERROR_IN           => tmg_trg_error_i,
+      --Status Registers
+      STAT_DATA_BUFFER_LEVEL     => stat_data_buffer_level,
+      STAT_HEADER_BUFFER_LEVEL   => stat_header_buffer_level,
+      STATUS_OUT                 => stat_handler_i,
+      TIMER_TICKS_IN             => time_ticks_i,
+      STATISTICS_DATA_OUT        => stat_buffer_i,
+      STATISTICS_UNKNOWN_OUT     => stat_buffer_unknown,
+      STATISTICS_READY_OUT       => stat_buffer_ready,
+      STATISTICS_READ_IN         => stat_buffer_read,
+      STATISTICS_ADDR_IN         => stat_buffer_address,
+
+
+      --Debug
+      DEBUG_DATA_HANDLER_OUT     => debug_data_handler_i,
+      DEBUG_IPU_HANDLER_OUT      => debug_ipu_handler_i
+
+      );
+
+  reset_ipu_i                  <= RESET or common_ctrl_reg_i(2);
+  lvl1_valid_i                 <= lvl1_valid_timing_i or lvl1_valid_notiming_i or lvl1_invalid_i;
+  STAT_DEBUG_IPU_HANDLER_OUT   <= debug_ipu_handler_i;
+  STAT_DEBUG_DATA_HANDLER_OUT  <= debug_data_handler_i;
+  tmg_trg_error_i              <= int_lvl1_missing_tmg_trg or int_lvl1_spurious_trg or int_lvl1_timeout_detected or int_multiple_trg
+                                  or int_spike_detected or int_lvl1_long_trg;
+
+---------------------------------------------------------------------------
+-- Connect Status Registers
+---------------------------------------------------------------------------
+  proc_buf_status : process(CLK)
+    variable tmp : integer range 0 to 15;
+    begin
+      if rising_edge(CLK) then
+        dbuf_unknown_addr        <= '0';
+        dbuf_dataready           <= '0';
+        tbuf_dataready           <= tbuf_read_enable;
+        if dbuf_read_enable = '1' then
+          tmp := to_integer(unsigned(dbuf_addr));
+          if tmp < DATA_INTERFACE_NUMBER then
+            dbuf_data_in         <= stat_data_buffer_level(tmp*32+31 downto tmp*32);
+            dbuf_dataready       <= '1';
+          else
+            dbuf_data_in         <= (others => '0');
+            dbuf_unknown_addr    <= '1';
+          end if;
+        end if;
+      end if;
+    end process;
+
+
+
+---------------------------------------------------------------------------
+-- Connect I/O Ports
+---------------------------------------------------------------------------
+
+  TRG_SPIKE_DETECTED_OUT   <= int_spike_detected;
+  TRG_SPURIOUS_TRG_OUT     <= int_lvl1_spurious_trg;
+  TRG_TIMEOUT_DETECTED_OUT <= int_lvl1_timeout_detected;
+  TRG_MULTIPLE_TRG_OUT     <= int_multiple_trg;
+  TRG_MISSING_TMG_TRG_OUT  <= int_lvl1_missing_tmg_trg;
+
+  LVL1_TRG_DATA_VALID_OUT        <= lvl1_data_valid_i;
+  LVL1_VALID_TIMING_TRG_OUT      <= lvl1_valid_timing_i;
+  LVL1_VALID_NOTIMING_TRG_OUT    <= lvl1_valid_notiming_i;
+  LVL1_INVALID_TRG_OUT           <= lvl1_invalid_i;
+  LVL1_TRG_TYPE_OUT              <= lvl1_type_i;
+  LVL1_TRG_NUMBER_OUT            <= lvl1_number_i;
+  LVL1_TRG_CODE_OUT              <= lvl1_code_i;
+  LVL1_TRG_INFORMATION_OUT       <= lvl1_information_i;
+  LVL1_INT_TRG_NUMBER_OUT        <= lvl1_int_trg_number_i;
+
+  REGIO_COMMON_CTRL_REG_OUT      <= common_ctrl_reg_i;
+  REGIO_COMMON_STAT_STROBE_OUT   <= common_stat_strobe_i;
+  REGIO_COMMON_CTRL_STROBE_OUT   <= common_ctrl_strobe_i;
+  REGIO_CTRL_REG_OUT             <= ctrl_reg_i;
+  REGIO_STAT_STROBE_OUT          <= stat_strobe_i;
+  REGIO_CTRL_STROBE_OUT          <= ctrl_strobe_i;
+
+  stat_reg_i                     <= REGIO_STAT_REG_IN;
+
+  TIME_GLOBAL_OUT                <= time_global_i;
+  TIME_LOCAL_OUT                 <= time_local_i;
+  TIME_SINCE_LAST_TRG_OUT        <= time_since_last_trg_i;
+  TIME_TICKS_OUT                 <= time_ticks_i;
+
+  process(REGIO_COMMON_STAT_REG_IN, debug_ipu_handler_i,common_ctrl_reg_i, common_stat_reg_i)
+    begin
+      common_stat_reg_i(8 downto 0) <= REGIO_COMMON_STAT_REG_IN(8 downto 0);
+      common_stat_reg_i(47 downto 12) <= REGIO_COMMON_STAT_REG_IN(47 downto 12);
+      common_stat_reg_i(6)       <= debug_ipu_handler_i(15) or REGIO_COMMON_STAT_REG_IN(6);
+
+      if rising_edge(CLK) then
+        if common_ctrl_reg_i(4) = '1' then 
+          common_stat_reg_i(11 downto 9) <= "000";
+        else 
+          common_stat_reg_i(9)       <= debug_ipu_handler_i(12) or REGIO_COMMON_STAT_REG_IN(9) or common_stat_reg_i(9);
+          common_stat_reg_i(10)      <= debug_ipu_handler_i(13) or REGIO_COMMON_STAT_REG_IN(10) or common_stat_reg_i(10);
+          common_stat_reg_i(11)      <= debug_ipu_handler_i(14) or REGIO_COMMON_STAT_REG_IN(11) or common_stat_reg_i(11);      
+        end if;
+      end if;
+      common_stat_reg_i(159 downto 64) <= REGIO_COMMON_STAT_REG_IN(159 downto 64);
+    end process;
+
+  process(CLK)
+    begin
+      if rising_edge(CLK) then
+        if ipu_start_readout_i = '1' then
+          common_stat_reg_i(63 downto 48) <= ipu_number_i;
+        end if;
+      end if;
+    end process;
+
+end architecture;
\ No newline at end of file
diff --git a/data_concentrator/version.vhd b/data_concentrator/version.vhd
new file mode 100644
index 0000000..5512fae
--- /dev/null
+++ b/data_concentrator/version.vhd
@@ -0,0 +1,11 @@
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+package version is
+
+    constant VERSION_NUMBER_TIME  : integer   := 5555;
+
+end package version;
-- 
2.43.0