From 40a56afa6ef30cae213dc15116b7c208be703a1b Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 9 Aug 2022 09:52:34 +0200 Subject: [PATCH] Move 'gbe' project to old directory --- .../syn_results/synlog/extref_compiler.srr | 46 - .../syn_results/synlog/extref_compiler.srr.db | Bin 8192 -> 0 bytes .../synlog/extref_compiler.srr.rptmap | 1 - .../syn_results/synlog/extref_fpga_mapper.srr | 201 ----- .../synlog/extref_fpga_mapper.srr.db | Bin 8192 -> 0 bytes .../syn_results/synlog/extref_fpga_mapper.szr | Bin 5141 -> 0 bytes .../synlog/extref_multi_srs_gen.srr | 11 - .../synlog/extref_multi_srs_gen.srr.db | Bin 8192 -> 0 bytes .../syn_results/synlog/extref_premap.srr | 62 -- .../syn_results/synlog/extref_premap.srr.db | Bin 8192 -> 0 bytes .../syn_results/synlog/extref_premap.szr | Bin 2533 -> 0 bytes .../syn_results/synlog/layer0.tlg.rptmap | 1 - .../synlog/report/extref_compiler_notes.txt | 8 - .../report/extref_compiler_runstatus.xml | 41 - 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{gbe/cores/sgmii/pll_in125_out125_out33 => old/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1}/syn_results/syntmp/closed.png (100%) rename {gbe/cores/sgmii/pll_in125_out125_out33 => old/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1}/syn_results/syntmp/open.png (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/run_option.xml (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1.plg (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_toc.htm (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/statusReport.html (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/.cckTransfer (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/_mh_info (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/_verilog_hintfile (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.fdep (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.fdeporig (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.srs (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.tlg (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.tlg.db (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.fdep (100%) rename {gbe/cores/sgmii/sgmii_ecp5 => old/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1}/syn_results/synwork/layer1.fdepxmr (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.info (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.srs (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.tlg (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.tlg.db (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/modulechange.db (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/modulechange_mixhdl/layer0/modulechange.db (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/modulechange_mixhdl/layer1/modulechange.db (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.fdep (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.linkerlog (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.srs (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_m.srm (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_m_srm/1.srm (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_m_srm/fileinfo.srm (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_mult.srs (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_mult_srs/1.srs (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_mult_srs/fileinfo.srs (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_mult_srs/skeleton.srs (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_prem.fse (100%) rename {gbe => old/gbe}/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_prem.srd (100%) rename {gbe => old/gbe}/create_project.pl (100%) rename {gbe => old/gbe}/par.p2t (100%) rename {gbe => old/gbe}/tdc_release (100%) rename {gbe => old/gbe}/trb5sc_gbe.lpf (100%) rename {gbe => old/gbe}/trb5sc_gbe.prj (100%) rename {gbe => old/gbe}/trb5sc_gbe.vhd (100%) diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_compiler.srr b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_compiler.srr deleted file mode 100644 index c36cce0..0000000 --- a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_compiler.srr +++ /dev/null @@ -1,46 +0,0 @@ -Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. - -Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. - -Running on host :lxhadeb07 -@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps -@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":18:7:18:12|Top entity is set to extref. -VHDL syntax check successful! -@N: CD630 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":18:7:18:12|Synthesizing work.extref.v1. -@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2147:10:2147:16|Synthesizing ecp5um.extrefb.syn_black_box. -Post processing for ecp5um.extrefb.syn_black_box -Post processing for work.extref.v1 - -At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Mon May 13 09:10:14 2019 - -###########################################################] -Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Mon May 13 09:10:14 2019 - -###########################################################] -@END - -At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Mon May 13 09:10:14 2019 - -###########################################################] diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_compiler.srr.db b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_compiler.srr.db deleted file mode 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100644 index 3e8860c..0000000 --- a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_multi_srs_gen.srr +++ /dev/null @@ -1,11 +0,0 @@ -Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Mon May 13 09:10:15 2019 - -###########################################################] diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_multi_srs_gen.srr.db b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_multi_srs_gen.srr.db deleted file mode 100644 index 029fa7a6cf9014af50ee9d4aa843536a1f7b5c42..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8192 zcmeI#JqyA>3DEQgKL*xDXO@ z%d=&(imfwzIG4G0Jf%J073BwWN1`{~f``Krs^Nta{J wY>_tId!-qqw)j}S$WL3iQGJ`s(T{)t1Rwwb2tWV=5P$##AOHafK;VZ3UKAiP82|tP diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.srr b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.srr deleted file mode 100644 index 27b114b..0000000 --- a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.srr +++ /dev/null @@ -1,62 +0,0 @@ -# Mon May 13 09:10:15 2019 - -Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. -Product Version M-2017.03L-SP1-1 - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) - -Reading constraint file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc -@L: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt -Printing clock summary report in "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt" file -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB) - -ICG Latch Removal Summary: -Number of ICG latches removed: 0 -Number of ICG latches not removed: 0 -syn_allowed_resources : blockrams=56 set on top level netlist extref - -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) - - - -Clock Summary -****************** - - Start Requested Requested Clock Clock Clock -Level Clock Frequency Period Type Group Load -------------------------------------------------------------------------- -========================================================================= - -Finished Pre Mapping Phase. - -Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) - - -Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) - -None -None - -Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) - -Pre-mapping successful! - -At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 142MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Mon May 13 09:10:16 2019 - -###########################################################] diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.srr.db b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.srr.db deleted file mode 100644 index 4dd9838c94d7e3005cdc2c470cfbe338a4b457d4..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8192 zcmeI#F;Buk6bJBYV`L(@7$%YzCP;)tC5;J-NN~bIWMgPb`zR;$j0+3$}A zz43s?y_?~H_PY(4&^pTFd6b{gQmVzF+O-@u7E=9aUfDOLGEFy|`<02PyxRo<0SG_< z0uX=z1Rwwb2tWV=5P-m61z!A8wY-^}`ggZM5cHQiUQn#nn)5W}Ds}xqr!|#^GM#YyyYmanA8M`u diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.szr b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.szr deleted file mode 100644 index e4da5e4149a0131bb9984e345a8d72e1b101e717..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2533 zcmV3|-4G(Gra8XPQxH?46ATuYJp9Jo!F>{#m`1Zc_lBl4gRJLZ z7aD_-a=#NtiaAHCprXDMH641KoU{*R3@%;?Um|%f9YbzWW#uCNEnQ~JHgDy{RnvX| z00960#8_=_+%^*ay!sWnP(b3sGHFZM@-|IT?@(MiSd#V>RX^l|V6KZ85^v>#-gOi7 z$KObfgI;?DdKWh#U|6QL^FGf!vu9bRWtthDUe%x@Pfi-{?7)o>^R#Bdb5JojE+D)~ z8n_p?yEXU~dm@?yo~s$8l>pZ8JlPf$>xE}oG*Vd(_c9x%h2u(iVZdnLnM^*?m;AIr=Z*}n+gG^dL9?-HpG|J?u4H~ep zxlf@G7%=I=re2~+Jk}Z{cgY%ZVK96x(ws9d0z?H)a2?VcL2kh9diTV$6^PW#ydrm3 zi9^HMoFoBLC|Hq#6L)y?WIuo3-W|=+6~PZP2e-ICTK+J{R16L!6vY-}<5q5Nv0G!I zX4<1Jnq)obG%z$pvl4>?CB0^ThDC+VU{;VUI7!BMrDqjG{INJ#`Wj{j|FW)%NO9-^ z+VQQ}w#Gsu&G^|LMKW|ReNqm*Y)5^}wpvv=;(4J#C8J@$$+uXZk9RdnHRbKRDeEF4 zi+yxW$_*-bw3ui?yFK9!U??JR}~pe*xX~`!E6K~Y>Q;QaVIj9`aEz~&;a>HmM8MpK{ydhCAuF_maFl~{ zP5mA8;9_!*9S6Zj&iUDJ253;!Td~2~C6Mn}hIX$p-#f(Ws;k~Ey7{8Q>Zp5r zoMm~inqkgvgcAlmT-M;N)@s=0m?9L8?6No<{zOPc!M9Pl;7}Z%(qNR&v3h&BJwS8X ztDgn-IN+wkqpEw3Z?}u9MRqk`=G5%98N?D_oV=y?k2Xbz)$?PW+rU_UXz{{dmRO@< z4|h1u=5*%3qLT`pV(6IBew;(-rS2(X!Z@Lw#T0;|se^HpKtZLLIYWP8ONBqHNhGBHkO66-2TcQ&pOxu*#eT~IVbcmn;#-wM9=uw&xMDtTxW%U8)etz=N;u2H$VJp4|+Ss6^-4lH-(8*kfr?i&K9@ZU-eRXqIeqY`BWPOEDqL6 zz9?}SbsYQPDN&PFP+w8c7pum!BR6!CD6niFIAN>3@;GCad5U)Iqp|)*>^0b^6DTvt zzGl`87%ptT6rZQQjvnfZ%6kL{b76%tG)8}Mqc6*#iGu*O(Tf9jss2>Y5_j(}!4Ncq z3X*zx(cPQ)vSS$cpfTnBc%OWqs2Ax&Rfqf2FatL}AD!$^Gs4%gw+O-XRO?YpcspT4X80Ufyo-XMeMo->$;bK`hx$&qXcHt^VR<3 zF3ZOH(3avr`0{L=oeZcR8=*$L=N@Dga z44_;fUTaqObk&#%n`kD3_9ETopQa1=U`e8HxPmzE+vaFqQoNoyY-nwR#WhLok@=>c zYM%B(G@ksXIArS10Kpe2$A;sx|7pMDW<3Dd#EE;&8|aT>JKr|NU)F81J6jtPBvBhD ztr)2Dq8Y{>Kwytv>qk}fvDWAGJl6Ur`oA(p*{c<2+fWqbcS(8q9C4>TIuf1tUnIw( zDJkw>q^=9G{cE}}@@#o?i>{{qEFOSX=MLj>A9I%$eRdtwda~&Pm$%A0A_>5Vna1-4 z$nUSatcSQx4avK`SR!#_&uW5StC2Xhrfp-9ecz3{meWd|wIJ!UtS3`xj4jsVJfr=A zZC}k1kkKsDNP97kd$Fa;HbOCi(P>7FI72{B`Xv!1f`3L_jBF9T?`<-}-+*HGCJd2JD%Oo;IH!RtKT2YGJH7hm^hz6JU|3^O~Q#Ojpy|Nj0-d61#yWueNQr; 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(Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. -@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref.edn -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_opt_report.xml b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_opt_report.xml deleted file mode 100644 index 1ad405d..0000000 --- a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_opt_report.xml +++ /dev/null @@ -1,14 +0,0 @@ - - - - -0 / 0 - -/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_combined_clk.rpt -START OF CLOCK OPTIMIZATION REPORT - - - diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_runstatus.xml b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_runstatus.xml deleted file mode 100644 index 68def92..0000000 --- a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_runstatus.xml +++ /dev/null @@ -1,46 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/extref_fpga_mapper.srr -Synopsys Lattice Technology Mapper - - -Completed - - - -7 - -/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_notes.txt - - - -1 - -/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_warnings.txt - - - -0 - -/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_errors.txt - - - -0h:00m:02s - - -0h:00m:02s - - -146MB - - -1557731418 - - - diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_timing_report.xml b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_timing_report.xml deleted file mode 100644 index 52701c6..0000000 --- a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_timing_report.xml +++ /dev/null @@ -1,23 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/extref_fpga_mapper.srr -START OF TIMING REPORT - - -Clock Name -Req Freq -Est Freq -Slack - - -System -100.0 MHz -NA -NA - - diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_warnings.txt b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_warnings.txt deleted file mode 100644 index b99a088..0000000 --- a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_warnings.txt +++ /dev/null @@ -1 +0,0 @@ -@W: MT246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":31:4:31:15|Blackbox EXTREFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_errors.txt b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_errors.txt deleted file mode 100644 index e69de29..0000000 diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_notes.txt b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_notes.txt deleted file mode 100644 index eed8756..0000000 --- a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_notes.txt +++ /dev/null @@ -1,2 +0,0 @@ -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_runstatus.xml b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_runstatus.xml deleted file mode 100644 index 963604b..0000000 --- a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_runstatus.xml +++ /dev/null @@ -1,46 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.srr -Synopsys Lattice Technology Pre-mapping - - -Completed - - - -2 - -/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_notes.txt - - - -0 - -/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_warnings.txt - - - -0 - -/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_errors.txt - - - -0h:00m:00s - - -0h:00m:00s - - -142MB - - -1557731416 - - - diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_warnings.txt b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_warnings.txt deleted file mode 100644 index e69de29..0000000 diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/metrics.db b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/metrics.db deleted file mode 100644 index 145597c4adc4b482a47f9aed0f9a755098cda8f8..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 20480 zcmeI3%Wm676oyG#wkQ}q$DyhyiwgKoQNv+WDyC9=!mMK{-RlXhVw{RbjBmvep|ec`s;cSJ3p ztbH0cA4%VczNh^IPk$yNX>{O^#(gjB$inOsq(_ol6`zJ`vABfHng4Gh!# z-(iWxf9KEm=W~C|{WN!xJ*NpY5C8!X009sH0T2KI5C8!X0D=EX;77+{Tbxx7D}hRk zr+k?-RBZAM`9`+Z#uCl%hwqpZ`M5`W{R4XOJaiMGY#Y&2L)W`yhi#Db!!haM;#=qr zeHycs^xbsz$gXreimj1<4bY_!PM6EpMY=9pI_OI!nomULy4sOS>QqGJMn+4Sd`p@1 zD&640gnqVk`VG#|>XeFL=PQ2t;lsZRR>i8G-z4ju7W6$z*3+On6ZbhI=r_>(k}~_t zoGsq11b(NXrSSqq&q7`u7(E8x+`277&-e#25%kaqDjvjr*}6{oewDm$7v9
-
-#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
-#install: /home/soft/lattice/diamond/3.10_x64/synpbase
-#OS: Linux 
-#Hostname: lxhadeb07
-
-# Mon May 13 09:10:13 2019
-
-#Implementation: syn_results
-
-Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
-@N: :  | Running in 64-bit mode 
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
-@N: :  | Running in 64-bit mode 
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Running on host :lxhadeb07
-@N:CD720 : std.vhd(123) | Setting time resolution to ps
-@N: : extref.vhd(18) | Top entity is set to extref.
-VHDL syntax check successful!
-@N:CD630 : extref.vhd(18) | Synthesizing work.extref.v1.
-@N:CD630 : ecp5um.vhd(2147) | Synthesizing ecp5um.extrefb.syn_black_box.
-Post processing for ecp5um.extrefb.syn_black_box
-Post processing for work.extref.v1
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Mon May 13 09:10:14 2019
-
-###########################################################]
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
-@N: :  | Running in 64-bit mode 
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Mon May 13 09:10:14 2019
-
-###########################################################]
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Mon May 13 09:10:14 2019
-
-###########################################################]
-
-
 -
-
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
-@N: :  | Running in 64-bit mode 
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Mon May 13 09:10:15 2019
-
-###########################################################]
-
-
 -
-
-Pre-mapping Report
-
-
-
 -
-
-# Mon May 13 09:10:15 2019
-
-Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
-
-Reading constraint file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc
-Linked File: extref_scck.rpt
-Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt" file 
-@N:MF248 :  | Running in 64-bit mode. 
-@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
-
-ICG Latch Removal Summary:
-Number of ICG latches removed:	0
-Number of ICG latches not removed:	0
-syn_allowed_resources : blockrams=56  set on top level netlist extref
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
-
-
-
-Clock Summary
-******************
-
-          Start     Requested     Requested     Clock     Clock     Clock
-Level     Clock     Frequency     Period        Type      Group     Load 
--------------------------------------------------------------------------
-=========================================================================
-
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
-
-None
-None
-
-Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 142MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Mon May 13 09:10:16 2019
-
-###########################################################]
-
-
 -
-
-Map & Optimize Report
-
-
-
 -
-
-# Mon May 13 09:10:16 2019
-
-Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
-
-@N:MF248 :  | Running in 64-bit mode. 
-@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Available hyper_sources - for debug and ip models
-	None Found
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-Pass		 CPU time		Worst Slack		Luts / Registers
-------------------------------------------------------------
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-
-@S |Clock Optimization Summary
-
-
-#### START OF CLOCK OPTIMIZATION REPORT #####[
-
-0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######]
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB)
-
-Writing Analyst data base /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/extref_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 143MB)
-
-Writing EDIF Netlist and constraint files
-@N:FX1056 :  | Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref.edn 
-M-2017.03L-SP1-1
-@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
-
-Writing Verilog Simulation files
-
-Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
-
-Writing VHDL Simulation files
-
-Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
-
-@W:MT246 : extref.vhd(31) | Blackbox EXTREFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
-
-
-##### START OF TIMING REPORT #####[
-# Timing Report written on Mon May 13 09:10:18 2019
-#
-
-
-Top view:               extref
-Requested Frequency:    100.0 MHz
-Wire load mode:         top
-Paths requested:        5
-Constraint File(s):    /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc
-                       
-@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
-
-@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: NA
-
-                   Requested     Estimated     Requested     Estimated               Clock      Clock          
-Starting Clock     Frequency     Frequency     Period        Period        Slack     Type       Group          
----------------------------------------------------------------------------------------------------------------
-System             100.0 MHz     NA            10.000        NA            NA        system     system_clkgroup
-===============================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-
-
-
-Clock Relationships
-*******************
-
-Clocks            |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------
-Starting  Ending  |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------
-========================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
-       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information 
-*********************
-
-No IO constraint found
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-None
-
-Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
-
----------------------------------------
-Resource Usage Report
-Part: lfe5um_25f-6
-
-Register bits: 0 of 24288 (0%)
-PIC Latch:       0
-I/O cells:       0
-
-
-Details:
-EXTREFB:        1
-GSR:            1
-PUR:            1
-VHI:            1
-VLO:            1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB)
-
-Process took 0h:00m:02s realtime, 0h:00m:02s cputime
-# Mon May 13 09:10:18 2019
-
-###########################################################]
-
-
 diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/extref_toc.htm b/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/extref_toc.htm deleted file mode 100644 index 88bb149..0000000 --- a/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/extref_toc.htm +++ /dev/null @@ -1,38 +0,0 @@ - - - - - - - - - - - - - - \ No newline at end of file diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/run_option.xml b/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/run_option.xml deleted file mode 100644 index e23ec94..0000000 --- a/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/run_option.xml +++ /dev/null @@ -1,24 +0,0 @@ - - - - - - - - - - - - - - - - - diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/statusReport.html b/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/statusReport.html deleted file mode 100644 index 0991010..0000000 --- a/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/statusReport.html +++ /dev/null @@ -1,112 +0,0 @@ - - - Project Status Summary Page - - - - - - -
- - - - - - - - - - -
Project Settings
Project Name extref Device Name syn_results: Lattice ECP5UM : LFE5UM_25F
Implementation Name syn_results Top Module extref
Pipelining 0 Retiming 0
Resource Sharing 1 Fanout Guide 50
Disable I/O Insertion 1 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Run Status
Job NameStatusCPU TimeReal TimeMemoryDate/Time
(compiler)Complete700-00m:01s-5/13/19
9:10 AM
(premap)Complete2000m:00s0m:00s142MB5/13/19
9:10 AM
(fpga_mapper)Complete7100m:02s0m:02s146MB5/13/19
9:10 AM
Multi-srs GeneratorComplete5/13/19
9:10 AM
-
- - - - - - - - - - - - - - - - -
Area Summary
Register bits 0I/O cells 0
Block RAMs -(v_ram) 0DSPs -(dsp_used) 0
ORCA LUTs -(total_luts) 0

- - - - - - - - -
Timing Summary
Clock NameReq FreqEst FreqSlack
System100.0 MHzNANA
-
- - - - - - -
Optimizations Summary
Combined Clock Conversion 0 / 0

-
-
- \ No newline at end of file diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/.cckTransfer b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/.cckTransfer deleted file mode 100644 index c1fdce9c6c2e00fb7113a52ec7bc7ef7408be070..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 457 zcmV;)0XF_0iwFP!0000015#C0RVXORFG)=2EhIrB{)TUz(B^hy5^YeW6txxuBnMKLC*4s|Ec1cT^M4s+2$*`f=p?4Amk=gNGqJ@h*FljT zX_v@n46^H0OHR$Ds-O>OV|NjF3NAbfmtpWf5d_LNA diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/_mh_info b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/_mh_info deleted file mode 100644 index 37bc105..0000000 --- a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/_mh_info +++ /dev/null @@ -1 +0,0 @@ -|1| diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_comp.fdep b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_comp.fdep deleted file mode 100644 index 3c02189..0000000 --- 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-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610 -#CUR:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":1557731412 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599 -0 "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd" vhdl -#Dependency Lists(Uses List) -0 -1 -#Dependency Lists(Users Of) -0 -1 -#Design Unit to File Association -module work extref 0 -arch work extref v1 0 diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_comp.srs b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_comp.srs deleted file mode 100644 index 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f50b372..0000000 --- a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.fdep +++ /dev/null @@ -1,28 +0,0 @@ -#defaultlanguage:vhdl -#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/extref_comp.srs|-top|extref|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work" -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610 -#CUR:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":1557731412 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599 -0 "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd" vhdl - -# Dependency Lists (Uses list) -0 -1 - -# Dependency Lists (Users Of) -0 -1 - -# Design Unit to File Association -arch work extref v1 0 -module work extref 0 - - -# Configuration files used diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.fdeporig b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.fdeporig deleted file mode 100644 index 79d35eb..0000000 --- a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.fdeporig +++ /dev/null @@ -1,24 +0,0 @@ -#defaultlanguage:vhdl -#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/extref_comp.srs|-top|extref|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work" -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610 -#CUR:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":1557731412 -0 "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd" vhdl - -# Dependency Lists (Uses list) -0 -1 - -# Dependency Lists (Users Of) -0 -1 - -# Design Unit to File Association -arch work extref v1 0 -module work extref 0 diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.srs b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.srs deleted file mode 100644 index a94cc5b5f880a789a49d583a873e3fc76f206d0b..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2552 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a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt +++ /dev/null @@ -1,16 +0,0 @@ -@N|Running in 64-bit mode -@N|Running in 64-bit mode -@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps -@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. -@N|Running in 64-bit mode -@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps -@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. -@N: CD630 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1. -@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. -@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work. -@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment. -@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment. -@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work. -@N: CL201 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state. -@N|Running in 64-bit mode - diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml deleted file mode 100644 index 978b9de..0000000 --- a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml +++ /dev/null @@ -1,41 +0,0 @@ - - - - - - /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr - Synopsys HDL Compiler - - - Completed - - - - 15 - /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt - - - 76 - /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt - - - 0 - /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_errors.txt - - - - - - - 00h:00m:02s - - - - - - - 1557731345 - - - \ No newline at end of file diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt deleted file mode 100644 index 8e5c4f5..0000000 --- a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt +++ /dev/null @@ -1,77 +0,0 @@ -@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers. - diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml deleted file mode 100644 index c262d0f..0000000 --- a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml +++ /dev/null @@ -1,26 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_resourceusage.rpt -Resource Usage - - -221 - - -0 - - -0 - - -0 - - -154 - - diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt deleted file mode 100644 index e69de29..0000000 diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt deleted file mode 100644 index b2d9ac0..0000000 --- a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt +++ /dev/null @@ -1,22 +0,0 @@ -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) -@N: MO225 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. -@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. -@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.edn -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml deleted file mode 100644 index 68d4e92..0000000 --- a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml +++ /dev/null @@ -1,14 +0,0 @@ - - - - -3 / 0 - -/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_combined_clk.rpt -START OF CLOCK OPTIMIZATION REPORT - - - diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml deleted file mode 100644 index 686a424..0000000 --- a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml +++ /dev/null @@ -1,46 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr -Synopsys Lattice Technology Mapper - - -Completed - - - -22 - -/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt - - - -4 - -/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt - - - -0 - -/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt - - - -0h:00m:03s - - -0h:00m:03s - - -153MB - - -1557731351 - - - diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml deleted file mode 100644 index 92b3753..0000000 --- a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml +++ /dev/null @@ -1,41 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr -START OF TIMING REPORT - - -Clock Name -Req Freq -Est Freq -Slack - - -sgmii_ecp5|pll_refclki -100.0 MHz -168.9 MHz -4.079 - - -sgmii_ecp5|rxrefclk -100.0 MHz -167.9 MHz -4.043 - - -sgmii_ecp5|tx_pclk_inferred_clock -100.0 MHz -237.5 MHz -5.789 - - -System -100.0 MHz -840.7 MHz -8.810 - - diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt deleted file mode 100644 index a40a3f6..0000000 --- a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt +++ /dev/null @@ -1,4 +0,0 @@ -@W: MT246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) -@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" -@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" -@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt deleted file mode 100644 index e69de29..0000000 diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt deleted file mode 100644 index 958d4b4..0000000 --- a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt +++ /dev/null @@ -1,9 +0,0 @@ -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) -@N: BN362 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. -@N: MO225 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml deleted file mode 100644 index 552c1b6..0000000 --- a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml +++ /dev/null @@ -1,46 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr -Synopsys Lattice Technology Pre-mapping - - -Completed - - - -9 - -/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt - - - -3 - -/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt - - - -0 - -/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt - - - -0h:00m:00s - - -0h:00m:00s - - -144MB - - -1557731347 - - - diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt deleted file mode 100644 index 71c6352..0000000 --- a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt +++ /dev/null @@ -1,3 +0,0 @@ -@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr deleted file mode 100644 index 7b9d5ac..0000000 --- a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr +++ /dev/null @@ -1,351 +0,0 @@ -Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. - -Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. - -Running on host :lxhadeb07 -@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps -@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. -VHDL syntax check successful! - -At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) - - -Process completed successfully. -# Mon May 13 09:09:04 2019 - -###########################################################] -Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. - -Running on host :lxhadeb07 -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) -@I::"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work) -Verilog syntax check successful! - -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) - - -Process completed successfully. -# Mon May 13 09:09:04 2019 - -###########################################################] -Running on host :lxhadeb07 -@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps -@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. -VHDL syntax check successful! -@N: CD630 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1. -Post processing for work.sgmii_ecp5.v1 - -At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) - - -Process completed successfully. -# Mon May 13 09:09:04 2019 - -###########################################################] -Running on host :lxhadeb07 -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) -@I::"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work) -Verilog syntax check successful! -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. - - PDATA_RST_VAL=32'b00000000000000000000000000000000 - Generated name = sync_0s -@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work. - - PPROTOCOL=24'b010001110100001001000101 - PLOL_SETTING=32'b00000000000000000000000000000000 - PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100 - PPCIE_MAX_RATE=24'b001100100010111000110101 - PDIFF_VAL_LOCK=32'b00000000000000000000000000100111 - PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110 - PPCLK_TC=32'b00000000000000100000000000000000 - PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000 - PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000 - PPCLK_DIV11_TC=32'b00000000000000000000000000000000 - LPLL_LOSS_ST=2'b00 - LPLL_PRELOSS_ST=2'b01 - LPLL_PRELOCK_ST=2'b10 - LPLL_LOCK_ST=2'b11 - LRCLK_TC=16'b1111111111111111 - LRCLK_TC_PUL_WIDTH=16'b0000000000110010 - LHB_WAIT_CNT=8'b11111111 - LPCLK_TC_0=32'b00000000000000001000000000000000 - LPCLK_TC_1=32'b00000000000000010000000000000000 - LPCLK_TC_2=32'b00000000000000100000000000000000 - LPCLK_TC_3=32'b00000000000000101000000000000000 - LPCLK_TC_4=32'b00000000000000010000000000000000 - LPDIFF_LOCK_00=32'b00000000000000000000000000001001 - LPDIFF_LOCK_10=32'b00000000000000000000000000010011 - LPDIFF_LOCK_20=32'b00000000000000000000000000100111 - LPDIFF_LOCK_30=32'b00000000000000000000000000110001 - LPDIFF_LOCK_40=32'b00000000000000000000000000010011 - LPDIFF_LOCK_01=32'b00000000000000000000000000001001 - LPDIFF_LOCK_11=32'b00000000000000000000000000010011 - LPDIFF_LOCK_21=32'b00000000000000000000000000100111 - LPDIFF_LOCK_31=32'b00000000000000000000000000110001 - LPDIFF_LOCK_41=32'b00000000000000000000000000010011 - LPDIFF_LOCK_02=32'b00000000000000000000000000110001 - LPDIFF_LOCK_12=32'b00000000000000000000000001100010 - LPDIFF_LOCK_22=32'b00000000000000000000000011000100 - LPDIFF_LOCK_32=32'b00000000000000000000000011110101 - LPDIFF_LOCK_42=32'b00000000000000000000000001100010 - LPDIFF_LOCK_03=32'b00000000000000000000000010000011 - LPDIFF_LOCK_13=32'b00000000000000000000000100000110 - LPDIFF_LOCK_23=32'b00000000000000000000001000001100 - LPDIFF_LOCK_33=32'b00000000000000000000001010001111 - LPDIFF_LOCK_43=32'b00000000000000000000000100000110 - LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011 - LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111 - LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110 - LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010 - LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111 - LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001 - LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011 - LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110 - LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111 - LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011 - LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000 - LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000 - LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000 - LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000 - LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000 - LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100 - LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001 - LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010 - LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111 - LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001 - Generated name = sgmii_ecp5sll_core_Z1_layer1 -@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment. -@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work. - - pnum_channels=32'b00000000000000000000000000000001 - pprotocol=24'b010001110100001001000101 - pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 - pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100 - pwait_tx_rdy=32'b00000000000000000000101110111000 - pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100 - pwait_rx_rdy=32'b00000000000000000000101110111000 - wa_num_cycles=32'b00000000000000000000010000000000 - dac_num_cycles=32'b00000000000000000000000000000011 - lreset_pwidth=32'b00000000000000000000000000000011 - lwait_b4_trst=32'b00000000000010111110101111000010 - lwait_b4_trst_s=32'b00000000000000000000001100001101 - lplol_cnt_width=32'b00000000000000000000000000010100 - lwait_after_plol0=32'b00000000000000000000000000000100 - lwait_b4_rrst=32'b00000000000000101100000000000000 - lrrst_wait_width=32'b00000000000000000000000000010100 - lwait_after_rrst=32'b00000000000011000011010100000000 - lwait_b4_rrst_s=32'b00000000000000000000000111001100 - lrlol_cnt_width=32'b00000000000000000000000000010011 - lwait_after_lols=32'b00000000000000001100010000000000 - lwait_after_lols_s=32'b00000000000000000000000010010110 - llols_cnt_width=32'b00000000000000000000000000010010 - lrdb_max=32'b00000000000000000000000000001111 - ltxr_wait_width=32'b00000000000000000000000000001100 - lrxr_wait_width=32'b00000000000000000000000000001100 - Generated name = sgmii_ecp5rsl_core_Z2_layer1 -@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers. -@N: CL201 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state. -Extracted state machine for register sll_state -State machine has 4 reachable states with original encodings of: - 00 - 01 - 10 - 11 - -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB) - - -Process completed successfully. -# Mon May 13 09:09:05 2019 - -###########################################################] -Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode - -======================================================================================= -For a summary of linker messages for components that did not bind, please see log file: -@L: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog -======================================================================================= - - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Mon May 13 09:09:05 2019 - -###########################################################] -@END - -At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Mon May 13 09:09:05 2019 - -###########################################################] diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.db b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.db deleted file mode 100644 index 22032b27c0e6d592fd8ff3ba504bfa3cf705b99a..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 28672 zcmeI5-ESLN6~OI$Ip1zmN*0#DrMt9UNbUJ_Z1-cg+f74gLc47dXrp!*k8hH($1~HJ zalY0FITF$eUJ<mpSGt>6Xm1_&YT9{>;V#?!v^WyOkp;M_ZL>|yJ++00Duim{Tp zi9L4i@7%9*&b{a4&YLT`htay_G*l0XsS~MmI`tYtsZ?qhzBBOMd8FZoq0TQ*lHZ^9 z7*1XI_?;=ZE1msm3civ@B7sB#i3Ab}Boas@kVqhrKq7%e0*M3?2_zEuKbL@)&dkou zrP~)hwPN4~c3pJ?yPb02+U>=wcNfv!tFNytqRzAD^(xv@9c@!}=8>VB_3m#6w{)MV z>t@f*HoQ|ey;q2lKa~BD$Uc+(PxhniqwI$hAB_KN?9u2aqnXUi$lUPxAz|>+!1eU4 z)LTbsqPBZ#bhfRvAG|nlZAIXUXY!j?1LxJMqpN0qL-+EYQ;}UQ@8O1Rs2d{7E1K1?m8NM}T78X|%iO(#HzIBx zK5RpGJ?y{_4QmTmQDqldwx>7rJ=N1KGqtSJRn6sOjn|)bx#l$b~H7+}39GOj+chesJLn!P-%Qb!D2{ z;(hVWv<9F~=axvF7KBcnh_uXS+AbXwGcB6t=-&H|G28%pLa(&4aJ8%iK>fKQ{AM*=6o` zZs^#|bL=t)=jiSUv12oTgdy%!D%iO+C00o!L>US+8n#I!DTxX z+6(N`2Hgjt(9W|<8+06mLi;UtX~WkpYTu-^Ebdi=uUyn#VHP%g-J*7$S=gY1AdEp< zJI5?+_8{T9bd6`1|CM8L0OwJ{Y0p<*2UM*+ z1_Ku&>!KaFqAZq0_<}+zbmRWEb%>vccLwEHHQ{; z!qiD$qCyH7qluB#$zDPy7XR)4o4jQGH46Ftcp!Nnk}pdOkAWmzFf!0fuTs##c={vf zgL0%b594HMe{>Fp+7UbBl`FLRnOLeX!5RR=2@0tv%-65JVHxfoX{jRusFx|gYAhX1 zf~k)H6v~p&>1fVj%_Hk$7cWu9bUcmZ&v_EedBWrS*b!Uk{zY2*rFdG%pYJ3nN{1~3 zL&I^Sn*#2a;{^2QIthvZV3c#*4@(sAMl3BT6zLd)LgEiw5SmZfRzXjWYQ4Htq=@lM z4*8Efi%RkoelM1U3MB!;{^9b}WD1V^ zUuv4eyoiTBVSXVbJMh6B3QJG3M{V*R5w?5u z^Wad87!LFP+1rG9pBPmuLeyD#0(mey4Sbk%2z*v9l8J2_bR>4!=}|ekECBoRI#`OZ za#PcoCL|&mL$O&UMkn4>w{#1#jzT)mEt0Z`IJfL3eEc?8pTy*(sY$``bmxibdGO-8 zV>Rf_o@FBgZ(*ZrV(*`SlL~5$6+snOw~XA<<TBe)UdXrg#T`w z@G{Zr1x|hne3Q1kt+~WvQ?$rh{zt2Hh8T{g+k^j~z)NMBe^R&i;lXiV#ZmL`t;E^* z)NLhj;I?|=um^r`M~S@g_h)Yayt03pHh#oDq7-xNy#XCqBtY1@K{jW1a8WNa)osdL_f>Jm0^0u#@l{B(of&WCU new code - 00 -> 00 - 01 -> 01 - 10 -> 10 - 11 -> 11 -@N: MO225 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. -@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] - -Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) - - -Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - -Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - -Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - -Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) - - -Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) - - -Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) - - -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) - - -Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) - -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). - -Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB) - -Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------- - 1 0h:00m:01s 4.90ns 155 / 221 -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). - -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB) - -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. - -Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 148MB peak: 149MB) - - - -@S |Clock Optimization Summary - - -#### START OF CLOCK OPTIMIZATION REPORT #####[ - -3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s) -0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) -0 instances converted, 0 sequential instances remain driven by gated/generated clocks - -============================================= Non-Gated/Non-Generated Clocks ============================================= -Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------------------------------------------- -@K:CKID0001 pll_refclki port 91 rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0] -@K:CKID0002 rxrefclk port 77 rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] -@K:CKID0003 DCU0_inst DCUA 53 sll_inst.pcount[21] -========================================================================================================================== - - -##### END OF CLOCK OPTIMIZATION REPORT ######] - - -Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 112MB peak: 149MB) - -Writing Analyst data base /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm - -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 149MB) - -Writing EDIF Netlist and constraint files -@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.edn -M-2017.03L-SP1-1 -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF - -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB) - -Writing Verilog Simulation files - -Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) - -Writing VHDL Simulation files - -Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) - - -Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) - -@W: MT246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) -@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" -@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" -@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" - - -##### START OF TIMING REPORT #####[ -# Timing Report written on Mon May 13 09:09:11 2019 -# - - -Top view: sgmii_ecp5 -Requested Frequency: 100.0 MHz -Wire load mode: top -Paths requested: 5 -Constraint File(s): /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc - -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. - -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. - - - -Performance Summary -******************* - - -Worst slack in design: 4.043 - - Requested Estimated Requested Estimated Clock Clock -Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------------- -sgmii_ecp5|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0 -sgmii_ecp5|rxrefclk 100.0 MHz 167.9 MHz 10.000 5.957 4.043 inferred Inferred_clkgroup_1 -sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 237.5 MHz 10.000 4.211 5.789 inferred Inferred_clkgroup_2 -System 100.0 MHz 840.7 MHz 10.000 1.190 8.810 system system_clkgroup -======================================================================================================================================== - - - - - -Clock Relationships -******************* - -Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------- -Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------- -System sgmii_ecp5|rxrefclk | 10.000 8.811 | No paths - | No paths - | No paths - -sgmii_ecp5|pll_refclki System | 10.000 8.253 | No paths - | No paths - | No paths - -sgmii_ecp5|pll_refclki sgmii_ecp5|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths - -sgmii_ecp5|pll_refclki sgmii_ecp5|tx_pclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - -sgmii_ecp5|rxrefclk System | 10.000 8.277 | No paths - | No paths - | No paths - -sgmii_ecp5|rxrefclk sgmii_ecp5|rxrefclk | 10.000 4.043 | No paths - | No paths - | No paths - -sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|pll_refclki | Diff grp - | No paths - | No paths - | No paths - -sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|tx_pclk_inferred_clock | 10.000 5.789 | No paths - | No paths - | No paths - -============================================================================================================================================================ - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - - -Interface Information -********************* - -No IO constraint found - - - -==================================== -Detailed Report for Clock: sgmii_ecp5|pll_refclki -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock --------------------------------------------------------------------------------------------------------------------- -rsl_inst.genblk1\.plol_cnt[2] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.079 -rsl_inst.genblk1\.plol_cnt[3] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.079 -rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[17] 0.907 4.079 -rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[19] 0.907 4.079 -rsl_inst.genblk1\.plol_cnt[1] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.684 -rsl_inst.genblk1\.plol_cnt[4] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684 -rsl_inst.genblk1\.plol_cnt[5] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684 -rsl_inst.genblk1\.plol_cnt[6] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.684 -rsl_inst.genblk1\.plol_cnt[7] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.684 -rsl_inst.genblk1\.plol_cnt[8] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684 -==================================================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------------ -rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079 -rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139 -rsl_inst.genblk1\.plol_cnt[18] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139 -rsl_inst.genblk1\.plol_cnt[15] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200 -rsl_inst.genblk1\.plol_cnt[16] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200 -rsl_inst.genblk1\.plol_cnt[13] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261 -rsl_inst.genblk1\.plol_cnt[14] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261 -rsl_inst.genblk1\.plol_cnt[11] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322 -rsl_inst.genblk1\.plol_cnt[12] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322 -rsl_inst.genblk1\.plol_cnt[9] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383 -======================================================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.054 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 9.946 - - - Propagation time: 5.867 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.079 - - Number of logic level(s): 15 - Starting point: rsl_inst.genblk1\.plol_cnt[2] / Q - Ending point: rsl_inst.genblk1\.plol_cnt[19] / D - The start point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK - The end point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------- -rsl_inst.genblk1\.plol_cnt[2] FD1S3DX Q Out 0.907 0.907 - -plol_cnt[2] Net - - - - 2 -rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 - -rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 - -un1_plol_cnt_tc_10 Net - - - - 1 -rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 - -rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 - -un1_plol_cnt_tc_14 Net - - - - 1 -rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 - -rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 - -un1_plol_cnt_tc Net - - - - 5 -rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 - -rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 - -plol_cnt Net - - - - 21 -rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 - -rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 - -plol_cnt_cry[0] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 - -rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 - -plol_cnt_cry[2] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 - -rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 - -plol_cnt_cry[4] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 - -rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 - -plol_cnt_cry[6] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 - -rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 - -plol_cnt_cry[8] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 - -rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 - -plol_cnt_cry[10] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 - -rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 - -plol_cnt_cry[12] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 - -rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 - -plol_cnt_cry[14] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 - -rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 - -plol_cnt_cry[16] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 - -rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 - -plol_cnt_cry[18] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 - -rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 - -plol_cnt_s[19] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 - -======================================================================================================= - - - - -==================================== -Detailed Report for Clock: sgmii_ecp5|rxrefclk -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock -------------------------------------------------------------------------------------------------------------------- -rsl_inst.genblk2\.rxs_rst sgmii_ecp5|rxrefclk FD1P3DX Q rxs_rst 1.015 4.043 -rsl_inst.genblk2\.rlol1_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[7] 0.907 4.136 -rsl_inst.genblk2\.rlol1_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[8] 0.907 4.136 -rsl_inst.genblk2\.rlol1_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[9] 0.907 4.136 -rsl_inst.genblk2\.rlol1_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[10] 0.907 4.136 -rsl_inst.genblk2\.rlols0_cnt[1] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[1] 0.907 4.170 -rsl_inst.genblk2\.rlols0_cnt[2] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[2] 0.907 4.170 -rsl_inst.genblk2\.rlols0_cnt[3] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[3] 0.907 4.170 -rsl_inst.genblk2\.rlols0_cnt[4] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[4] 0.907 4.170 -rsl_inst.genblk2\.rlol1_cnt[0] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742 -=================================================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------------------------------------- -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[11] 9.946 4.043 -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[9] 9.946 4.104 -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[10] 9.946 4.104 -rsl_inst.genblk2\.rlol1_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136 -rsl_inst.genblk2\.rlol1_cnt[18] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136 -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[7] 9.946 4.165 -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[8] 9.946 4.165 -rsl_inst.genblk2\.rlols0_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170 -rsl_inst.genblk2\.rlol1_cnt[15] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197 -rsl_inst.genblk2\.rlol1_cnt[16] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197 -================================================================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.054 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 9.946 - - - Propagation time: 5.902 - - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : 4.043 - - Number of logic level(s): 11 - Starting point: rsl_inst.genblk2\.rxs_rst / Q - Ending point: rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] / D - The start point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK - The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------ -rsl_inst.genblk2\.rxs_rst FD1P3DX Q Out 1.015 1.015 - -rxs_rst Net - - - - 6 -rsl_inst.rdo_rx_serdes_rst_c_1[0] ORCALUT4 B In 0.000 1.015 - -rsl_inst.rdo_rx_serdes_rst_c_1[0] ORCALUT4 Z Out 0.708 1.723 - -rsl_rx_serdes_rst_c Net - - - - 3 -rsl_inst.dual_or_rserd_rst ORCALUT4 A In 0.000 1.723 - -rsl_inst.dual_or_rserd_rst ORCALUT4 Z Out 0.798 2.521 - -dual_or_rserd_rst Net - - - - 9 -rsl_inst.rx_any_rst ORCALUT4 A In 0.000 2.521 - -rsl_inst.rx_any_rst ORCALUT4 Z Out 0.660 3.181 - -rx_any_rst Net - - - - 2 -rsl_inst.rx_any_rst_RNIFD021 ORCALUT4 A In 0.000 3.181 - -rsl_inst.rx_any_rst_RNIFD021 ORCALUT4 Z Out 0.819 4.000 - -rxr_wt_cnt9 Net - - - - 14 -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0] CCU2C A1 In 0.000 4.000 - -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0] CCU2C COUT Out 0.900 4.900 - -rxr_wt_cnt_cry[0] Net - - - - 1 -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1] CCU2C CIN In 0.000 4.900 - -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1] CCU2C COUT Out 0.061 4.961 - -rxr_wt_cnt_cry[2] Net - - - - 1 -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3] CCU2C CIN In 0.000 4.961 - -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3] CCU2C COUT Out 0.061 5.022 - -rxr_wt_cnt_cry[4] Net - - - - 1 -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5] CCU2C CIN In 0.000 5.022 - -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5] CCU2C COUT Out 0.061 5.083 - -rxr_wt_cnt_cry[6] Net - - - - 1 -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7] CCU2C CIN In 0.000 5.083 - -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7] CCU2C COUT Out 0.061 5.144 - -rxr_wt_cnt_cry[8] Net - - - - 1 -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9] CCU2C CIN In 0.000 5.144 - -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9] CCU2C COUT Out 0.061 5.205 - -rxr_wt_cnt_cry[10] Net - - - - 1 -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11] CCU2C CIN In 0.000 5.205 - -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11] CCU2C S0 Out 0.698 5.902 - -rxr_wt_cnt_s[11] Net - - - - 1 -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] FD1P3DX D In 0.000 5.902 - -================================================================================================================= - - - - -==================================== -Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------------- -sll_inst.ppul_sync_p1 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p1 1.098 5.789 -sll_inst.ppul_sync_p2 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p2 1.098 5.789 -sll_inst.pcount_diff[0] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_0 0.985 6.147 -sll_inst.pcount[0] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[0] 0.955 6.178 -sll_inst.pcount_diff[1] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_1 0.955 6.239 -sll_inst.pcount_diff[2] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_2 0.955 6.239 -sll_inst.pcount[1] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[1] 0.907 6.287 -sll_inst.pcount[2] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[2] 0.907 6.287 -sll_inst.pcount_diff[3] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_3 0.955 6.300 -sll_inst.pcount_diff[4] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_4 0.955 6.300 -======================================================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------------------------------ -sll_inst.pcount[21] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[21] 9.946 5.789 -sll_inst.pcount[19] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[19] 9.946 5.850 -sll_inst.pcount[20] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[20] 9.946 5.850 -sll_inst.pcount[17] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[17] 9.946 5.911 -sll_inst.pcount[18] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[18] 9.946 5.911 -sll_inst.pcount[15] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[15] 9.946 5.972 -sll_inst.pcount[16] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[16] 9.946 5.972 -sll_inst.pcount[13] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[13] 9.946 6.033 -sll_inst.pcount[14] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[14] 9.946 6.033 -sll_inst.pcount_diff[21] sgmii_ecp5|tx_pclk_inferred_clock FD1P3DX D un1_pcount_diff_1_s_21_0_S0 9.946 6.034 -========================================================================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.054 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 9.946 - - - Propagation time: 4.157 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 5.789 - - Number of logic level(s): 13 - Starting point: sll_inst.ppul_sync_p1 / Q - Ending point: sll_inst.pcount[21] / D - The start point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK - The end point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- -sll_inst.ppul_sync_p1 FD1S3DX Q Out 1.098 1.098 - -ppul_sync_p1 Net - - - - 25 -sll_inst.pcount10_0_o3 ORCALUT4 A In 0.000 1.098 - -sll_inst.pcount10_0_o3 ORCALUT4 Z Out 0.851 1.950 - -N_8 Net - - - - 25 -sll_inst.pcount_cry_0[0] CCU2C A1 In 0.000 1.950 - -sll_inst.pcount_cry_0[0] CCU2C COUT Out 0.900 2.850 - -pcount_cry[0] Net - - - - 1 -sll_inst.pcount_cry_0[1] CCU2C CIN In 0.000 2.850 - -sll_inst.pcount_cry_0[1] CCU2C COUT Out 0.061 2.911 - -pcount_cry[2] Net - - - - 1 -sll_inst.pcount_cry_0[3] CCU2C CIN In 0.000 2.911 - -sll_inst.pcount_cry_0[3] CCU2C COUT Out 0.061 2.972 - -pcount_cry[4] Net - - - - 1 -sll_inst.pcount_cry_0[5] CCU2C CIN In 0.000 2.972 - -sll_inst.pcount_cry_0[5] CCU2C COUT Out 0.061 3.033 - -pcount_cry[6] Net - - - - 1 -sll_inst.pcount_cry_0[7] CCU2C CIN In 0.000 3.033 - -sll_inst.pcount_cry_0[7] CCU2C COUT Out 0.061 3.094 - -pcount_cry[8] Net - - - - 1 -sll_inst.pcount_cry_0[9] CCU2C CIN In 0.000 3.094 - -sll_inst.pcount_cry_0[9] CCU2C COUT Out 0.061 3.155 - -pcount_cry[10] Net - - - - 1 -sll_inst.pcount_cry_0[11] CCU2C CIN In 0.000 3.155 - -sll_inst.pcount_cry_0[11] CCU2C COUT Out 0.061 3.216 - -pcount_cry[12] Net - - - - 1 -sll_inst.pcount_cry_0[13] CCU2C CIN In 0.000 3.216 - -sll_inst.pcount_cry_0[13] CCU2C COUT Out 0.061 3.277 - -pcount_cry[14] Net - - - - 1 -sll_inst.pcount_cry_0[15] CCU2C CIN In 0.000 3.277 - -sll_inst.pcount_cry_0[15] CCU2C COUT Out 0.061 3.338 - -pcount_cry[16] Net - - - - 1 -sll_inst.pcount_cry_0[17] CCU2C CIN In 0.000 3.338 - -sll_inst.pcount_cry_0[17] CCU2C COUT Out 0.061 3.399 - -pcount_cry[18] Net - - - - 1 -sll_inst.pcount_cry_0[19] CCU2C CIN In 0.000 3.399 - -sll_inst.pcount_cry_0[19] CCU2C COUT Out 0.061 3.460 - -pcount_cry[20] Net - - - - 1 -sll_inst.pcount_s_0[21] CCU2C CIN In 0.000 3.460 - -sll_inst.pcount_s_0[21] CCU2C S0 Out 0.698 4.157 - -pcount_s[21] Net - - - - 1 -sll_inst.pcount[21] FD1S3DX D In 0.000 4.157 - -============================================================================================ - - - - -==================================== -Detailed Report for Clock: System -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ----------------------------------------------------------------------------------------- -DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 8.810 -DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 8.810 -======================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------------------------------------------------- -rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX SP un2_rdo_serdes_rst_dual_c_2_i 9.806 8.810 -rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX D rxpr_appd_RNO[0] 9.946 9.556 -rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946 -rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946 -============================================================================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.194 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 9.806 - - - Propagation time: 0.996 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (non-critical) : 8.810 - - Number of logic level(s): 2 - Starting point: DCU0_inst / CH0_FFS_RLOL - Ending point: rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP - The start point is clocked by System [rising] - The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------ -DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 - -rx_cdr_lol_s Net - - - - 4 -rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 A In 0.000 0.000 - -rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 Z Out 0.606 0.606 - -un2_rdo_serdes_rst_dual_c_1_1 Net - - - - 1 -rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 B In 0.000 0.606 - -rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 Z Out 0.390 0.996 - -un2_rdo_serdes_rst_dual_c_2_i Net - - - - 1 -rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] FD1P3DX SP In 0.000 0.996 - -=================================================================================================================================== - - - -##### END OF TIMING REPORT #####] - -Timing exceptions that could not be applied -None - -Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) - - -Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) - ---------------------------------------- -Resource Usage Report -Part: lfe5um_25f-6 - -Register bits: 221 of 24288 (1%) -PIC Latch: 0 -I/O cells: 0 - - -Details: -CCU2C: 113 -DCUA: 1 -FD1P3BX: 20 -FD1P3DX: 92 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z%d=&(imfwzIG4G0Jf%J073BwWN1`{~f``Krs^Nta{J wY>_tId!-qqw)j}S$WL3iQGJ`s(T{)t1Rwwb2tWV=5P$##AOHafK;VZ3UKAiP82|tP diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr deleted file mode 100644 index 919edaa..0000000 --- a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr +++ /dev/null @@ -1,86 +0,0 @@ -# Mon May 13 09:09:07 2019 - -Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. -Product Version M-2017.03L-SP1-1 - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) - -Reading constraint file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc -@L: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt -Printing clock summary report in "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB) - -@N: BN362 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. -ICG Latch Removal Summary: -Number of ICG latches removed: 0 -Number of ICG latches not removed: 0 -syn_allowed_resources : blockrams=56 set on top level netlist sgmii_ecp5 - -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) - - - -Clock Summary -****************** - - Start Requested Requested Clock Clock Clock -Level Clock Frequency Period Type Group Load ----------------------------------------------------------------------------------------------------------------------- -0 - System 100.0 MHz 10.000 system system_clkgroup 0 - -0 - sgmii_ecp5|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 93 - -0 - sgmii_ecp5|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 77 - -0 - sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 53 -====================================================================================================================== - -@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. - -Finished Pre Mapping Phase. - -Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) - -Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) -original code -> new code - 00 -> 00 - 01 -> 01 - 10 -> 10 - 11 -> 11 -@N: MO225 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. - -Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) - -None -None - -Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 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zbJy+oWE?(|GmW&?R@GFF!+z%}lScPT>gA9KDkb(gko9ksZVN@6RSj P4@G|$duS$b_|X3WREeG! diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.tlg b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.tlg deleted file mode 100644 index f6f3666..0000000 --- a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.tlg +++ /dev/null @@ -1,252 +0,0 @@ -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. - - PDATA_RST_VAL=32'b00000000000000000000000000000000 - Generated name = sync_0s -@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work. - - PPROTOCOL=24'b010001110100001001000101 - PLOL_SETTING=32'b00000000000000000000000000000000 - PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100 - PPCIE_MAX_RATE=24'b001100100010111000110101 - PDIFF_VAL_LOCK=32'b00000000000000000000000000100111 - PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110 - PPCLK_TC=32'b00000000000000100000000000000000 - PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000 - PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000 - PPCLK_DIV11_TC=32'b00000000000000000000000000000000 - LPLL_LOSS_ST=2'b00 - LPLL_PRELOSS_ST=2'b01 - LPLL_PRELOCK_ST=2'b10 - LPLL_LOCK_ST=2'b11 - LRCLK_TC=16'b1111111111111111 - LRCLK_TC_PUL_WIDTH=16'b0000000000110010 - LHB_WAIT_CNT=8'b11111111 - LPCLK_TC_0=32'b00000000000000001000000000000000 - LPCLK_TC_1=32'b00000000000000010000000000000000 - LPCLK_TC_2=32'b00000000000000100000000000000000 - LPCLK_TC_3=32'b00000000000000101000000000000000 - LPCLK_TC_4=32'b00000000000000010000000000000000 - LPDIFF_LOCK_00=32'b00000000000000000000000000001001 - LPDIFF_LOCK_10=32'b00000000000000000000000000010011 - LPDIFF_LOCK_20=32'b00000000000000000000000000100111 - LPDIFF_LOCK_30=32'b00000000000000000000000000110001 - LPDIFF_LOCK_40=32'b00000000000000000000000000010011 - LPDIFF_LOCK_01=32'b00000000000000000000000000001001 - LPDIFF_LOCK_11=32'b00000000000000000000000000010011 - LPDIFF_LOCK_21=32'b00000000000000000000000000100111 - LPDIFF_LOCK_31=32'b00000000000000000000000000110001 - LPDIFF_LOCK_41=32'b00000000000000000000000000010011 - LPDIFF_LOCK_02=32'b00000000000000000000000000110001 - LPDIFF_LOCK_12=32'b00000000000000000000000001100010 - LPDIFF_LOCK_22=32'b00000000000000000000000011000100 - LPDIFF_LOCK_32=32'b00000000000000000000000011110101 - LPDIFF_LOCK_42=32'b00000000000000000000000001100010 - LPDIFF_LOCK_03=32'b00000000000000000000000010000011 - LPDIFF_LOCK_13=32'b00000000000000000000000100000110 - LPDIFF_LOCK_23=32'b00000000000000000000001000001100 - LPDIFF_LOCK_33=32'b00000000000000000000001010001111 - LPDIFF_LOCK_43=32'b00000000000000000000000100000110 - LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011 - LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111 - LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110 - LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010 - LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111 - LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001 - LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011 - LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110 - LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111 - LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011 - LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000 - LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000 - LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000 - LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000 - LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000 - LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100 - LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001 - LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010 - LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111 - LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001 - Generated name = sgmii_ecp5sll_core_Z1_layer1 -@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment. -@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work. - - pnum_channels=32'b00000000000000000000000000000001 - pprotocol=24'b010001110100001001000101 - pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 - pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100 - pwait_tx_rdy=32'b00000000000000000000101110111000 - pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100 - pwait_rx_rdy=32'b00000000000000000000101110111000 - wa_num_cycles=32'b00000000000000000000010000000000 - dac_num_cycles=32'b00000000000000000000000000000011 - lreset_pwidth=32'b00000000000000000000000000000011 - lwait_b4_trst=32'b00000000000010111110101111000010 - lwait_b4_trst_s=32'b00000000000000000000001100001101 - lplol_cnt_width=32'b00000000000000000000000000010100 - lwait_after_plol0=32'b00000000000000000000000000000100 - lwait_b4_rrst=32'b00000000000000101100000000000000 - lrrst_wait_width=32'b00000000000000000000000000010100 - lwait_after_rrst=32'b00000000000011000011010100000000 - lwait_b4_rrst_s=32'b00000000000000000000000111001100 - lrlol_cnt_width=32'b00000000000000000000000000010011 - lwait_after_lols=32'b00000000000000001100010000000000 - lwait_after_lols_s=32'b00000000000000000000000010010110 - llols_cnt_width=32'b00000000000000000000000000010010 - lrdb_max=32'b00000000000000000000000000001111 - ltxr_wait_width=32'b00000000000000000000000000001100 - lrxr_wait_width=32'b00000000000000000000000000001100 - Generated name = sgmii_ecp5rsl_core_Z2_layer1 -@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. 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/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/dm -lite -ui -fid2 -ram -sharing on -ll 2000 -autosm -ignore_undefined_lib -lib work /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd -jobname "compiler" \ No newline at end of file diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/_cmd._cml b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/_cmd._cml deleted file mode 100644 index 60abe88..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/_cmd._cml +++ /dev/null @@ -1 +0,0 @@ --link -encrypt -top pll_200_125_100 -osyn /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_comp.srs /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.srs \ No newline at end of file diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/dm/layer0.xdm b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/dm/layer0.xdm deleted file mode 100644 index 8d0ce64..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/dm/layer0.xdm +++ /dev/null @@ -1,163 +0,0 @@ -%%% protect protected_file -@EG -- -]17p0Osk0CksRsPC#MHF=3"4j -"> -!S<-1-RFOksCHRVDRC#O0FMskHL0oHMRR0F0REC8HC#o-MR-S> -S -SS1SS1SS -SS1SS1SS1S -SF<1kCsOR"b=/lEFCF/#VD0/NH00O8C/HFNlMd8/3_4jG/nc#b$MLCN#/LDH/8PE/bE$CMsC0P#3ER8"N(=""=RD"8PEDO"RD0H#=4"-"DRbH=#0""-4/S> -SF<1kCsOR"b=/lEFC8/NsMHN/0oH/L0s6/#O0bClDCN0/Fbs[0CO/DbD_j.j_j.j_64._j4j/DbD_j.j_64._j4j/DbD_j.j_64._j4j38PE"=RN"RU"DP="E"8DRHOD#"0=-R4"b#DH0-="4>"/ -"/ -/S<1sFkO>C# -< -S!R--vkF8DsCRFRF0- -->SF<)FM0R=F"Isb 3D.D_j4j_.46_j#j30Osk0Cks" -/> -< -S!R--vkF8D7CRCMVHHF0HM-R->< -S7RCVMC="Okb6lp3em$3#MD_LN_O L"FGR"D=PDE8"S> -SR -SRS -SSqS -SRSqS -SRSqSSqSSqS -SRS -S -/S<7>CV -< -S!R--vkF8D7CRCMVHHF0HM-R->< -S7RCVMC="Okb6l]3 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@@ ----------------------------------------------------------------------- -Report for cell pll_200_125_100.structure - -Register bits: 0 of 24288 (0%) -PIC Latch: 0 -I/O cells: 0 - Cell usage: - cell count Res Usage(%) - EHXPLLL 1 100.0 - GSR 1 100.0 - PUR 1 100.0 - VHI 1 100.0 - VLO 1 100.0 - - TOTAL 5 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.fse b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.fse deleted file mode 100644 index e69de29..0000000 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.htm b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.htm deleted file mode 100644 index a052015..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.htm +++ /dev/null @@ -1,9 +0,0 @@ - - - syntmp/pll_200_125_100_srr.htm log file - - - - - - diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.prj b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.prj deleted file mode 100644 index 63c7206..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.prj +++ /dev/null @@ -1,46 +0,0 @@ -#-- Lattice Semiconductor Corporation Ltd. -#-- Synplify OEM project file /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.prj -#-- Written on Fri May 10 14:33:10 2019 - - -#device options -set_option -technology ecp5um -set_option -part LFE5UM-85F -set_option -speed_grade 8 - -#use verilog 2001 standard option -set_option -vlog_std v2001 - -#map options -set_option -frequency 100 -set_option -fanout_limit 50 -set_option -disable_io_insertion true -set_option -retiming false -set_option -pipe false -set_option -pipe false -set_option -force_gsr false - -#simulation options -set_option -write_verilog true -set_option -write_vhdl true - -#timing analysis options - -#automatic place and route (vendor) options -set_option -write_apr_constraint 1 - -#-- add_file options -add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd" -add_file -constraint {"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc"} - -#-- top module name -set_option -top_module pll_200_125_100 - -#-- set result format/file last -project -result_file "pll_200_125_100.edn" - -#-- error message log file -project -log_file pll_200_125_100.srf - -#-- run Synplify with 'arrange VHDL file' -project -run diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srd b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srd deleted file mode 100644 index c0e0a024e460d4f9a39619b05aeb8edef0bcb16e..0000000000000000000000000000000000000000 GIT binary patch literal 0 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zD`k4>Mm>k;SeV{#eN)S7cVQXa3-2wicVWF#p5-~4L;Tmc))mYKlSeYOL(kBU!bb0O zznov})NiZLG@p0U%7&r5S5N`zTyC6H#dYi)95eU#zdF_-wwB*gRWCv7)js`eUGM9k zz`UQ=|BHN~X1MwPj>yPXB3OkMH;<#@rv3i_00960;&M>n0ssI2|NjF3D2_O~voQbw DI{7Xh diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srf b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srf deleted file mode 100644 index dac1f38..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srf +++ /dev/null @@ -1,403 +0,0 @@ -#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug 4 2017 -#install: /home/soft/lattice/diamond/3.10_x64/synpbase -#OS: Linux -#Hostname: lxhadeb07 - -# Fri May 10 14:33:10 2019 - -#Implementation: syn_results - -Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. - -Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. - -Running on host :lxhadeb07 -@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps -@N:"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Top entity is set to pll_200_125_100. -VHDL syntax check successful! -@N: CD630 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Synthesizing work.pll_200_125_100.structure. -@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box. -Post processing for ecp5um.ehxplll.syn_black_box -@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box. -Post processing for ecp5um.vlo.syn_black_box -@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box. -Post processing for ecp5um.vhi.syn_black_box -Post processing for work.pll_200_125_100.structure -@W: CL168 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":50:4:50:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. - -At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Fri May 10 14:33:11 2019 - -###########################################################] -Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Fri May 10 14:33:11 2019 - -###########################################################] -@END - -At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Fri May 10 14:33:11 2019 - -###########################################################] -Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Fri May 10 14:33:12 2019 - -###########################################################] -Pre-mapping Report - -# Fri May 10 14:33:12 2019 - -Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. -Product Version M-2017.03L-SP1-1 - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) - -Reading constraint file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc -@L: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt -Printing clock summary report in "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt" file -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB) - -ICG Latch Removal Summary: -Number of ICG latches removed: 0 -Number of ICG latches not removed: 0 -syn_allowed_resources : blockrams=56 set on top level netlist pll_200_125_100 - -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - - -Clock Summary -****************** - - Start Requested Requested Clock Clock Clock -Level Clock Frequency Period Type Group Load -------------------------------------------------------------------------------------- -0 - System 100.0 MHz 10.000 system system_clkgroup 0 -===================================================================================== - -Finished Pre Mapping Phase. - -Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - -None -None - -Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - -Pre-mapping successful! - -At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Fri May 10 14:33:13 2019 - -###########################################################] -Map & Optimize Report - -# Fri May 10 14:33:13 2019 - -Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. -Product Version M-2017.03L-SP1-1 - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) - -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) - - - -Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - -Available hyper_sources - for debug and ip models - None Found - - -Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - -Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - -Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - -Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - -Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - -Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - -Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------- - -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. - -Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - - -@S |Clock Optimization Summary - - -#### START OF CLOCK OPTIMIZATION REPORT #####[ - -0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) -0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) -0 instances converted, 0 sequential instances remain driven by gated/generated clocks - - - -##### END OF CLOCK OPTIMIZATION REPORT ######] - - -Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB) - -Writing Analyst data base /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_m.srm - -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - -Writing EDIF Netlist and constraint files -@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.edn -M-2017.03L-SP1-1 -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF - -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) - -Writing Verilog Simulation files - -Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) - -Writing VHDL Simulation files - -Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) - - -Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB) - -@W: MT246 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":56:4:56:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) - - -##### START OF TIMING REPORT #####[ -# Timing Report written on Fri May 10 14:33:15 2019 -# - - -Top view: pll_200_125_100 -Requested Frequency: 100.0 MHz -Wire load mode: top -Paths requested: 5 -Constraint File(s): /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc - -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. - -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. - - - -Performance Summary -******************* - - -Worst slack in design: 10.000 - -@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. - Requested Estimated Requested Estimated Clock Clock -Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------- -System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup -================================================================================================================ -Estimated period and frequency reported as NA means no slack depends directly on the clock waveform - - - - - -Clock Relationships -******************* - -Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------- -Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------- -System System | 10.000 10.000 | No paths - | No paths - | No paths - -========================================================================================================= - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - - -Interface Information -********************* - -No IO constraint found - - - -==================================== -Detailed Report for Clock: System -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------ -PLLInst_0 System EHXPLLL CLKINTFB CLKFB_t 0.000 10.000 -=================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------- -PLLInst_0 System EHXPLLL CLKFB CLKFB_t 10.000 10.000 -================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.000 - + Clock delay at ending point: 0.000 (ideal) - + Estimated clock delay at ending point: 0.000 - = Required time: 10.000 - - - Propagation time: 0.000 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (critical) : 10.000 - - Number of logic level(s): 0 - Starting point: PLLInst_0 / CLKINTFB - Ending point: PLLInst_0 / CLKFB - The start point is clocked by System [rising] - The end point is clocked by System [rising] - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------- -PLLInst_0 EHXPLLL CLKINTFB Out 0.000 0.000 - -CLKFB_t Net - - - - 1 -PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 - -==================================================================================== - - - -##### END OF TIMING REPORT #####] - -Timing exceptions that could not be applied -None - -Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB) - - -Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB) - ---------------------------------------- -Resource Usage Report -Part: lfe5um_25f-6 - -Register bits: 0 of 24288 (0%) -PIC Latch: 0 -I/O cells: 0 - - -Details: -EHXPLLL: 1 -GSR: 1 -PUR: 1 -VHI: 1 -VLO: 1 -Mapper successful! - -At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB) - -Process took 0h:00m:02s realtime, 0h:00m:02s cputime -# Fri May 10 14:33:15 2019 - -###########################################################] diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srm b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srm deleted file mode 100644 index cbb05bb7b732d977f12e9578bc15a1d612001329..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 5633 zcmV+c7XIlUiwFP!0000015#C0RVXORFG)=OcNV;JpN4zcQ2s${|u_%{Ey{7~JeKmn6)XEmfnA zoy`ple?tJ?V^G|IRL-)^4FN`WZZ=DdaUC1#O}udceh(i54nvnenH+`eJno!@@Xi=C{>zYPUDDzG= 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/dev/null @@ -1,403 +0,0 @@ -#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug 4 2017 -#install: /home/soft/lattice/diamond/3.10_x64/synpbase -#OS: Linux -#Hostname: lxhadeb07 - -# Fri May 10 14:33:10 2019 - -#Implementation: syn_results - -Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. - -Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. - -Running on host :lxhadeb07 -@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps -@N:"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Top entity is set to pll_200_125_100. -VHDL syntax check successful! -@N: CD630 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Synthesizing work.pll_200_125_100.structure. -@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box. -Post processing for ecp5um.ehxplll.syn_black_box -@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box. -Post processing for ecp5um.vlo.syn_black_box -@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box. -Post processing for ecp5um.vhi.syn_black_box -Post processing for work.pll_200_125_100.structure -@W: CL168 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":50:4:50:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. - -At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Fri May 10 14:33:11 2019 - -###########################################################] -Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Fri May 10 14:33:11 2019 - -###########################################################] -@END - -At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Fri May 10 14:33:11 2019 - -###########################################################] -Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Fri May 10 14:33:12 2019 - -###########################################################] -Pre-mapping Report - -# Fri May 10 14:33:12 2019 - -Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. -Product Version M-2017.03L-SP1-1 - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) - -Reading constraint file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc -@L: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt -Printing clock summary report in "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt" file -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB) - -ICG Latch Removal Summary: -Number of ICG latches removed: 0 -Number of ICG latches not removed: 0 -syn_allowed_resources : blockrams=56 set on top level netlist pll_200_125_100 - -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - - -Clock Summary -****************** - - Start Requested Requested Clock Clock Clock -Level Clock Frequency Period Type Group Load -------------------------------------------------------------------------------------- -0 - System 100.0 MHz 10.000 system system_clkgroup 0 -===================================================================================== - -Finished Pre Mapping Phase. - -Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - -None -None - -Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - -Pre-mapping successful! - -At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Fri May 10 14:33:13 2019 - -###########################################################] -Map & Optimize Report - -# Fri May 10 14:33:13 2019 - -Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. -Product Version M-2017.03L-SP1-1 - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) - -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) - - - -Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - -Available hyper_sources - for debug and ip models - None Found - - -Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - -Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - -Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - -Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - -Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - -Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - -Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------- - -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. - -Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - - -@S |Clock Optimization Summary - - -#### START OF CLOCK OPTIMIZATION REPORT #####[ - -0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) -0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) -0 instances converted, 0 sequential instances remain driven by gated/generated clocks - - - -##### END OF CLOCK OPTIMIZATION REPORT ######] - - -Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB) - -Writing Analyst data base /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_m.srm - -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - -Writing EDIF Netlist and constraint files -@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.edn -M-2017.03L-SP1-1 -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF - -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) - -Writing Verilog Simulation files - -Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) - -Writing VHDL Simulation files - -Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) - - -Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB) - -@W: MT246 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":56:4:56:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) - - -##### START OF TIMING REPORT #####[ -# Timing Report written on Fri May 10 14:33:15 2019 -# - - -Top view: pll_200_125_100 -Requested Frequency: 100.0 MHz -Wire load mode: top -Paths requested: 5 -Constraint File(s): /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc - -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. - -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. - - - -Performance Summary -******************* - - -Worst slack in design: 10.000 - -@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. - Requested Estimated Requested Estimated Clock Clock -Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------- -System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup -================================================================================================================ -Estimated period and frequency reported as NA means no slack depends directly on the clock waveform - - - - - -Clock Relationships -******************* - -Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------- -Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------- -System System | 10.000 10.000 | No paths - | No paths - | No paths - -========================================================================================================= - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - - -Interface Information -********************* - -No IO constraint found - - - -==================================== -Detailed Report for Clock: System -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------ -PLLInst_0 System EHXPLLL CLKINTFB CLKFB_t 0.000 10.000 -=================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------- -PLLInst_0 System EHXPLLL CLKFB CLKFB_t 10.000 10.000 -================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.000 - + Clock delay at ending point: 0.000 (ideal) - + Estimated clock delay at ending point: 0.000 - = Required time: 10.000 - - - Propagation time: 0.000 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (critical) : 10.000 - - Number of logic level(s): 0 - Starting point: PLLInst_0 / CLKINTFB - Ending point: PLLInst_0 / CLKFB - The start point is clocked by System [rising] - The end point is clocked by System [rising] - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------- -PLLInst_0 EHXPLLL CLKINTFB Out 0.000 0.000 - -CLKFB_t Net - - - - 1 -PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 - -==================================================================================== - - - -##### END OF TIMING REPORT #####] - -Timing exceptions that could not be applied -None - -Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB) - - -Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB) - 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a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.vhm b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.vhm deleted file mode 100644 index 6274441..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.vhm +++ /dev/null @@ -1,108 +0,0 @@ --- --- Written by Synplicity --- Product Version "M-2017.03L-SP1-1" --- Program "Synplify Pro", Mapper "maplat, Build 1796R" --- Fri May 10 14:33:15 2019 --- - --- --- Written by Synplify Pro version Build 1796R --- Fri May 10 14:33:15 2019 --- - --- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -library synplify; -use synplify.components.all; -library pmi; -use pmi.pmi_components.all; -library ecp5um; -use ecp5um.components.all; - -entity pll_200_125_100 is -port( - CLKI : in std_logic; - CLKOP : out std_logic; - CLKOS : out std_logic; - CLKOS2 : out std_logic; - LOCK : out std_logic); -end pll_200_125_100; - -architecture beh of pll_200_125_100 is - signal CLKOS3 : std_logic ; - signal INTLOCK : std_logic ; - signal CLKFB_T : std_logic ; - signal REFCLK : std_logic ; - signal GND : std_logic ; - signal VCC : std_logic ; -begin -GND_0: VLO port map ( - Z => GND); -VCC_0: VHI port map ( - Z => VCC); -PUR_INST: PUR port map ( - PUR => VCC); -GSR_INST: GSR port map ( - GSR => VCC); -PLLINST_0: EHXPLLL - generic map( - CLKI_DIV => 2, - CLKFB_DIV => 1, - CLKOP_DIV => 1, - CLKOS_DIV => 5, - CLKOS2_DIV => 4, - CLKOS3_DIV => 1, - CLKOP_ENABLE => "ENABLED", - CLKOS_ENABLE => "ENABLED", - CLKOS2_ENABLE => "ENABLED", - CLKOS3_ENABLE => "DISABLED", - CLKOP_CPHASE => 0, - CLKOS_CPHASE => 4, - CLKOS2_CPHASE => 3, - CLKOS3_CPHASE => 0, - CLKOP_FPHASE => 0, - CLKOS_FPHASE => 0, - CLKOS2_FPHASE => 0, - CLKOS3_FPHASE => 0, - FEEDBK_PATH => "INT_OS", - CLKOP_TRIM_POL => "FALLING", - CLKOP_TRIM_DELAY => 0, - CLKOS_TRIM_POL => "FALLING", - CLKOS_TRIM_DELAY => 0, - OUTDIVIDER_MUXA => "REFCLK", - OUTDIVIDER_MUXB => "DIVB", - OUTDIVIDER_MUXC => "DIVC", - OUTDIVIDER_MUXD => "DIVD", - PLL_LOCK_MODE => 0, - STDBY_ENABLE => "DISABLED", - DPHASE_SOURCE => "DISABLED", - PLLRST_ENA => "DISABLED", - INTFB_WAKE => "DISABLED" - ) - port map ( - CLKI => CLKI, - CLKFB => CLKFB_T, - PHASESEL1 => GND, - PHASESEL0 => GND, - PHASEDIR => GND, - PHASESTEP => GND, - PHASELOADREG => GND, - STDBY => GND, - PLLWAKESYNC => GND, - RST => GND, - ENCLKOP => GND, - ENCLKOS => GND, - ENCLKOS2 => GND, - ENCLKOS3 => GND, - CLKOP => CLKOP, - CLKOS => CLKOS, - CLKOS2 => CLKOS2, - CLKOS3 => CLKOS3, - LOCK => LOCK, - INTLOCK => INTLOCK, - REFCLK => REFCLK, - CLKINTFB => CLKFB_T); -end beh; - diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.vm b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.vm deleted file mode 100644 index bae9f65..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.vm +++ /dev/null @@ -1,117 +0,0 @@ -// -// Written by Synplify Pro -// Product Version "M-2017.03L-SP1-1" -// Program "Synplify Pro", Mapper "maplat, Build 1796R" -// Fri May 10 14:33:14 2019 -// -// Source file index table: -// Object locations will have the form : -// file 0 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd " -// file 1 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd " -// file 2 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd " -// file 3 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd " -// file 4 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd " -// file 5 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd " -// file 6 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd " -// file 7 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd " -// file 8 "\/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd " -// file 9 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd " -// file 10 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/nlconst.dat " -// file 11 "\/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc " - -`timescale 100 ps/100 ps -(* NGD_DRC_MASK=1 *)module pll_200_125_100 ( - CLKI, - CLKOP, - CLKOS, - CLKOS2, - LOCK -) -; -input CLKI ; -output CLKOP ; -output CLKOS ; -output CLKOS2 ; -output LOCK ; -wire CLKI ; -wire CLKOP ; -wire CLKOS ; -wire CLKOS2 ; -wire LOCK ; -wire CLKOS3 ; -wire INTLOCK ; -wire CLKFB_t ; -wire REFCLK ; -wire GND ; -wire VCC ; - VLO GND_0 ( - .Z(GND) -); - VHI VCC_0 ( - .Z(VCC) -); - PUR PUR_INST ( - .PUR(VCC) -); - GSR GSR_INST ( - .GSR(VCC) -); -// @8:56 -(* LPF_RESISTOR="24" , ICP_CURRENT="13" , FREQUENCY_PIN_CLKI="200.000000" , FREQUENCY_PIN_CLKOP="200.000000" , FREQUENCY_PIN_CLKOS="100.000000" , FREQUENCY_PIN_CLKOS2="125.000000" *) EHXPLLL PLLInst_0 ( - .CLKI(CLKI), - .CLKFB(CLKFB_t), - .PHASESEL1(GND), - .PHASESEL0(GND), - .PHASEDIR(GND), - .PHASESTEP(GND), - .PHASELOADREG(GND), - .STDBY(GND), - .PLLWAKESYNC(GND), - .RST(GND), - .ENCLKOP(GND), - .ENCLKOS(GND), - .ENCLKOS2(GND), - .ENCLKOS3(GND), - .CLKOP(CLKOP), - .CLKOS(CLKOS), - .CLKOS2(CLKOS2), - .CLKOS3(CLKOS3), - .LOCK(LOCK), - .INTLOCK(INTLOCK), - .REFCLK(REFCLK), - .CLKINTFB(CLKFB_t) -); -defparam PLLInst_0.CLKI_DIV = 2; -defparam PLLInst_0.CLKFB_DIV = 1; -defparam PLLInst_0.CLKOP_DIV = 1; -defparam PLLInst_0.CLKOS_DIV = 5; -defparam PLLInst_0.CLKOS2_DIV = 4; -defparam PLLInst_0.CLKOS3_DIV = 1; -defparam PLLInst_0.CLKOP_ENABLE = "ENABLED"; -defparam PLLInst_0.CLKOS_ENABLE = "ENABLED"; -defparam PLLInst_0.CLKOS2_ENABLE = "ENABLED"; -defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED"; -defparam PLLInst_0.CLKOP_CPHASE = 0; -defparam PLLInst_0.CLKOS_CPHASE = 4; -defparam PLLInst_0.CLKOS2_CPHASE = 3; -defparam PLLInst_0.CLKOS3_CPHASE = 0; -defparam PLLInst_0.CLKOP_FPHASE = 0; -defparam PLLInst_0.CLKOS_FPHASE = 0; -defparam PLLInst_0.CLKOS2_FPHASE = 0; -defparam PLLInst_0.CLKOS3_FPHASE = 0; -defparam PLLInst_0.FEEDBK_PATH = "INT_OS"; -defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING"; -defparam PLLInst_0.CLKOP_TRIM_DELAY = 0; -defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING"; -defparam PLLInst_0.CLKOS_TRIM_DELAY = 0; -defparam PLLInst_0.OUTDIVIDER_MUXA = "REFCLK"; -defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB"; -defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC"; -defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD"; -defparam PLLInst_0.PLL_LOCK_MODE = 0; -defparam PLLInst_0.STDBY_ENABLE = "DISABLED"; -defparam PLLInst_0.DPHASE_SOURCE = "DISABLED"; -defparam PLLInst_0.PLLRST_ENA = "DISABLED"; -defparam PLLInst_0.INTFB_WAKE = "DISABLED"; -endmodule /* pll_200_125_100 */ - diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_cck.rpt.db b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_cck.rpt.db deleted file mode 100644 index 029fa7a6cf9014af50ee9d4aa843536a1f7b5c42..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8192 zcmeI#JqyA>3DEQgKL*xDXO@ z%d=&(imfwzIG4G0Jf%J073BwWN1`{~f``Krs^Nta{J wY>_tId!-qqw)j}S$WL3iQGJ`s(T{)t1Rwwb2tWV=5P$##AOHafK;VZ3UKAiP82|tP diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt.db b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt.db deleted file mode 100644 index 029fa7a6cf9014af50ee9d4aa843536a1f7b5c42..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8192 zcmeI#JqyA>3DEQgKL*xDXO@ z%d=&(imfwzIG4G0Jf%J073BwWN1`{~f``Krs^Nta{J wY>_tId!-qqw)j}S$WL3iQGJ`s(T{)t1Rwwb2tWV=5P$##AOHafK;VZ3UKAiP82|tP diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify.lpf b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify.lpf deleted file mode 100644 index 8e445e1..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify.lpf +++ /dev/null @@ -1,20 +0,0 @@ -# -# Logical Preferences generated for Lattice by Synplify maplat, Build 1796R. -# - -# Period Constraints - - -# Output Constraints - -# Input Constraints - -# Point-to-point Delay Constraints - - - -# Block Path Constraints - -BLOCK ASYNCPATHS; - -# End of generated Logical Preferences. diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify_tmp2.lpf b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify_tmp2.lpf deleted file mode 100644 index e69de29..0000000 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify_tmp4.lpf b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify_tmp4.lpf deleted file mode 100644 index e69de29..0000000 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify_tmp8.lpf b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify_tmp8.lpf deleted file mode 100644 index e69de29..0000000 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/run_options.txt b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/run_options.txt deleted file mode 100644 index f45a913..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/run_options.txt +++ /dev/null @@ -1,75 +0,0 @@ -#-- Synopsys, Inc. -#-- Version M-2017.03L-SP1-1 -#-- Project file /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/run_options.txt -#-- Written on Fri May 10 14:33:10 2019 - - -#project files -add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd" -add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc" - - - -#implementation: "syn_results" -impl -add syn_results -type fpga - -# -#implementation attributes - -set_option -vlog_std v2001 - -#device options -set_option -technology ecp5um -set_option -part LFE5UM_25F -set_option -package MG285C -set_option -speed_grade -6 -set_option -part_companion "" - -#compilation/mapping options -set_option -top_module "pll_200_125_100" - -# hdl_compiler_options -set_option -distributed_compile 0 - -# mapper_without_write_options -set_option -frequency 100 -set_option -srs_instrumentation 1 - -# mapper_options -set_option -write_verilog 1 -set_option -write_vhdl 1 - -# Lattice XP -set_option -maxfan 50 -set_option -disable_io_insertion 1 -set_option -retiming 0 -set_option -pipe 0 -set_option -forcegsr false -set_option -fix_gated_and_generated_clocks 1 -set_option -rw_check_on_ram 1 -set_option -update_models_cp 0 -set_option -syn_edif_array_rename 1 -set_option -Write_declared_clocks_only 1 - -# NFilter -set_option -no_sequential_opt 0 - -# sequential_optimization_options -set_option -symbolic_fsm_compiler 1 - -# Compiler Options -set_option -compiler_compatible 0 -set_option -resource_sharing 1 - -# Compiler Options -set_option -auto_infer_blackbox 0 - -#automatic place and route (vendor) options -set_option -write_apr_constraint 1 - -#set result format/file last -project -result_file "./pll_200_125_100.edn" - -#set log file -set_option log_file "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srf" -impl -active "syn_results" diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/scratchproject.prs b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/scratchproject.prs deleted file mode 100644 index 6e19e6b..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/scratchproject.prs +++ /dev/null @@ -1,73 +0,0 @@ -#-- Synopsys, Inc. -#-- Version M-2017.03L-SP1-1 -#-- Project file /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/scratchproject.prs - -#project files -add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd" -add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc" - - - -#implementation: "syn_results" -impl -add /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results -type fpga - -# -#implementation attributes - -set_option -vlog_std v2001 - -#device options -set_option -technology ecp5um -set_option -part LFE5UM_25F -set_option -package MG285C -set_option -speed_grade -6 -set_option -part_companion "" - -#compilation/mapping options -set_option -top_module "pll_200_125_100" - -# hdl_compiler_options -set_option -distributed_compile 0 - -# mapper_without_write_options -set_option -frequency 100 -set_option -srs_instrumentation 1 - -# mapper_options -set_option -write_verilog 1 -set_option -write_vhdl 1 - -# Lattice XP -set_option -maxfan 50 -set_option -disable_io_insertion 1 -set_option -retiming 0 -set_option -pipe 0 -set_option -forcegsr false -set_option -fix_gated_and_generated_clocks 1 -set_option -rw_check_on_ram 1 -set_option -update_models_cp 0 -set_option -syn_edif_array_rename 1 -set_option -Write_declared_clocks_only 1 - -# NFilter -set_option -no_sequential_opt 0 - -# sequential_optimization_options -set_option -symbolic_fsm_compiler 1 - -# Compiler Options -set_option -compiler_compatible 0 -set_option -resource_sharing 1 - -# Compiler Options -set_option -auto_infer_blackbox 0 - -#automatic place and route (vendor) options -set_option -write_apr_constraint 1 - -#set result format/file last -project -result_file "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.edn" - -#set log file -set_option log_file "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srf" -impl -active "syn_results" diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/layer0.tlg.rptmap b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/layer0.tlg.rptmap deleted file mode 100644 index 3910cac..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/layer0.tlg.rptmap +++ /dev/null @@ -1 +0,0 @@ -./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages. diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr deleted file mode 100644 index 4501cf1..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr +++ /dev/null @@ -1,51 +0,0 @@ -Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. - -Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. - -Running on host :lxhadeb07 -@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps -@N:"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Top entity is set to pll_200_125_100. -VHDL syntax check successful! -@N: CD630 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Synthesizing work.pll_200_125_100.structure. -@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box. -Post processing for ecp5um.ehxplll.syn_black_box -@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box. -Post processing for ecp5um.vlo.syn_black_box -@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box. -Post processing for ecp5um.vhi.syn_black_box -Post processing for work.pll_200_125_100.structure -@W: CL168 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":50:4:50:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. - -At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Fri May 10 14:33:11 2019 - -###########################################################] -Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Fri May 10 14:33:11 2019 - -###########################################################] -@END - -At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Fri May 10 14:33:11 2019 - -###########################################################] diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr.db b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr.db deleted file mode 100644 index b43ab41e45c47969ad26458f91fdda0c85ae5af4..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8192 zcmeH~%}x|S5XWa11QT757{kGkbnu`?oSqN%BkMsCi5D&c7f+j>nSyC|rhDw}S-@~v zPR1wjHGCGI#+x8Rmie(IpD{NIf^=lPG%4a}-7e{t|*hb3SMSOS)SC143y0+xU!UpvM^#&>LRUr~V%t{S}8x7k@v29&R2htNPx$J698+Fvg;j*T`S;T(OZ6mpE;9nMd zELGo~w#K9lTy0btn^M8#4?V+s|M2nKN^Lv%gX+RIqS_?my7B`=*Fi1eNDN?kVo4dE T1HpEXS!uWw#9(*maXI}2tvZET diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr.rptmap b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr.rptmap deleted file mode 100644 index 4edadfd..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr.rptmap +++ /dev/null @@ -1 +0,0 @@ -./synlog/pll_200_125_100_compiler.srr,pll_200_125_100_compiler.srr,Compile Log diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.srr b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.srr deleted file mode 100644 index fbbc4b8..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.srr +++ /dev/null @@ -1,265 +0,0 @@ -# Fri May 10 14:33:13 2019 - -Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. -Product Version M-2017.03L-SP1-1 - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) - -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) - - - -Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - -Available hyper_sources - for debug and ip models - None Found - - -Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - -Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - -Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - -Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - -Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - -Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - -Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------- - -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. - -Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - - -@S |Clock Optimization Summary - - -#### START OF CLOCK OPTIMIZATION REPORT #####[ - -0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) -0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) -0 instances converted, 0 sequential instances remain driven by gated/generated clocks - - - -##### END OF CLOCK OPTIMIZATION REPORT ######] - - -Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB) - -Writing Analyst data base /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_m.srm - -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - -Writing EDIF Netlist and constraint files -@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.edn -M-2017.03L-SP1-1 -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF - -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) - -Writing Verilog Simulation files - -Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) - -Writing VHDL Simulation files - -Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) - - -Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB) - -@W: MT246 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":56:4:56:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) - - -##### START OF TIMING REPORT #####[ -# Timing Report written on Fri May 10 14:33:15 2019 -# - - -Top view: pll_200_125_100 -Requested Frequency: 100.0 MHz -Wire load mode: top -Paths requested: 5 -Constraint File(s): /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc - -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. - -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. - - - -Performance Summary -******************* - - -Worst slack in design: 10.000 - -@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. - Requested Estimated Requested Estimated Clock Clock -Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------- -System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup -================================================================================================================ -Estimated period and frequency reported as NA means no slack depends directly on the clock waveform - - - - - -Clock Relationships -******************* - -Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------- -Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------- -System System | 10.000 10.000 | No paths - | No paths - | No paths - -========================================================================================================= - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - - -Interface Information -********************* - -No IO constraint found - - - -==================================== -Detailed Report for Clock: System -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------ -PLLInst_0 System EHXPLLL CLKINTFB CLKFB_t 0.000 10.000 -=================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------- -PLLInst_0 System EHXPLLL CLKFB CLKFB_t 10.000 10.000 -================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.000 - + Clock delay at ending point: 0.000 (ideal) - + Estimated clock delay at ending point: 0.000 - = Required time: 10.000 - - - Propagation time: 0.000 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (critical) : 10.000 - - Number of logic level(s): 0 - Starting point: PLLInst_0 / CLKINTFB - Ending point: PLLInst_0 / CLKFB - The start point is clocked by System [rising] - The end point is clocked by System [rising] - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------- -PLLInst_0 EHXPLLL CLKINTFB Out 0.000 0.000 - -CLKFB_t Net - - - - 1 -PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 - -==================================================================================== - - - -##### END OF TIMING REPORT #####] - -Timing exceptions that could not be applied -None - -Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB) - - -Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB) - 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2017 -@N|Running in 64-bit mode - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Fri May 10 14:33:12 2019 - -###########################################################] diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_multi_srs_gen.srr.db b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_multi_srs_gen.srr.db deleted file mode 100644 index 029fa7a6cf9014af50ee9d4aa843536a1f7b5c42..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8192 zcmeI#JqyA>3DEQgKL*xDXO@ z%d=&(imfwzIG4G0Jf%J073BwWN1`{~f``Krs^Nta{J wY>_tId!-qqw)j}S$WL3iQGJ`s(T{)t1Rwwb2tWV=5P$##AOHafK;VZ3UKAiP82|tP diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_premap.srr b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_premap.srr deleted file mode 100644 index 889cbd5..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_premap.srr +++ /dev/null @@ -1,63 +0,0 @@ -# Fri May 10 14:33:12 2019 - -Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. -Product Version M-2017.03L-SP1-1 - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) - -Reading constraint file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc -@L: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt -Printing clock summary report in "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt" file -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB) - -ICG Latch Removal Summary: -Number of ICG latches removed: 0 -Number of ICG latches not removed: 0 -syn_allowed_resources : blockrams=56 set on top level netlist pll_200_125_100 - -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - - -Clock Summary -****************** - - Start Requested Requested Clock Clock Clock -Level Clock Frequency Period Type Group Load -------------------------------------------------------------------------------------- -0 - System 100.0 MHz 10.000 system system_clkgroup 0 -===================================================================================== - -Finished Pre Mapping Phase. - -Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - -None -None - -Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - -Pre-mapping successful! - -At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Fri May 10 14:33:13 2019 - -###########################################################] diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_premap.srr.db b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_premap.srr.db deleted file mode 100644 index d3d49fbbcb447f8a3dbecf9cf1e7bbb3fb033d75..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8192 zcmeI#F;Buk6bJBYV`L(@7$%YzCP;)tC5;J-NN~bIWMgPb`zR;v9cfRaBb)I9`d!?- zLkMoh+5by>ukY@)O@7;ZxF1Wyw9rK!8M+iF!t=y6kr2Y)-8OB*v+L3B*(F#17QX0w zzEy3PS9=%sLO=il5P$##AOHafKmY;|fB*#kxq$I1^+v4>I-oAHSDyDgc}b5z93s5qlcs@0*|wH!89QvGON+c%{$Z8w|ywV9}W*aZOr2tWV= z5P$##AOHafKmY;|fWTh`Uj0hFx|yB&ceg3fc7^iwFP!0000016+-<4#F@DM0dWzOE-kmN?n+`urjenX=B=;w25qk1mfdK zk;;H{me1DHT~$?(IVlagZSwXSBJH~F{Ju;af;YQ)FA=bU?}lPpsrO>~)_H=tsftk9)3L#a8Rr6uF8 z1R1?8Ir#IWpmf}KQck-N#=p9o&gwFRyRo}I>vEHNU^3&($td)517&O!sFJmkmzJh? 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To preserve this instance, use the syn_noprune synthesis directive. - diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_area_report.xml b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_area_report.xml deleted file mode 100644 index 243c347..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_area_report.xml +++ /dev/null @@ -1,26 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_resourceusage.rpt -Resource Usage - - -0 - - -0 - - -0 - - -0 - - -0 - - diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_errors.txt b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_errors.txt deleted file mode 100644 index e69de29..0000000 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_notes.txt b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_notes.txt deleted file mode 100644 index 5e801a0..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_notes.txt +++ /dev/null @@ -1,8 +0,0 @@ -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. -@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.edn -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. -@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_opt_report.xml b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_opt_report.xml deleted file mode 100644 index 7832235..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_opt_report.xml +++ /dev/null @@ -1,14 +0,0 @@ - - - - -0 / 0 - -/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_combined_clk.rpt -START OF CLOCK OPTIMIZATION REPORT - - - diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_runstatus.xml b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_runstatus.xml deleted file mode 100644 index b0bf07a..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_runstatus.xml +++ /dev/null @@ -1,46 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.srr -Synopsys Lattice Technology Mapper - - -Completed - - - -8 - -/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_notes.txt - - - -1 - -/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_warnings.txt - - - -0 - -/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_errors.txt - - - -0h:00m:02s - - -0h:00m:02s - - -146MB - - -1557491595 - - - diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_timing_report.xml b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_timing_report.xml deleted file mode 100644 index 60b8b51..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_timing_report.xml +++ /dev/null @@ -1,23 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.srr -START OF TIMING REPORT - - -Clock Name -Req Freq -Est Freq -Slack - - -System -100.0 MHz -NA -10.000 - - diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_warnings.txt b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_warnings.txt deleted file mode 100644 index ebff314..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_warnings.txt +++ /dev/null @@ -1 +0,0 @@ -@W: MT246 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":56:4:56:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_errors.txt b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_errors.txt deleted file mode 100644 index e69de29..0000000 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_notes.txt b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_notes.txt deleted file mode 100644 index eed8756..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_notes.txt +++ /dev/null @@ -1,2 +0,0 @@ -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_runstatus.xml b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_runstatus.xml deleted file mode 100644 index 00fedf8..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_runstatus.xml +++ /dev/null @@ -1,46 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_premap.srr -Synopsys Lattice Technology Pre-mapping - - -Completed - - - -2 - -/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_notes.txt - - - -0 - -/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_warnings.txt - - - -0 - -/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_errors.txt - - - -0h:00m:00s - - -0h:00m:00s - - -143MB - - -1557491593 - - - diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_warnings.txt b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_warnings.txt deleted file mode 100644 index e69de29..0000000 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/syntax_constraint_check.rpt.rptmap b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/syntax_constraint_check.rpt.rptmap deleted file mode 100644 index 0213fed..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/syntax_constraint_check.rpt.rptmap +++ /dev/null @@ -1 +0,0 @@ -./pll_200_125_100_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100.plg b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100.plg deleted file mode 100644 index bba9612..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100.plg +++ /dev/null @@ -1,8 +0,0 @@ -@P: Worst Slack : 10.000 -@P: System - Estimated Frequency : NA -@P: System - Requested Frequency : 100.0 MHz -@P: System - Estimated Period : 0.000 -@P: System - Requested Period : 10.000 -@P: System - Slack : 10.000 -@P: Total Area : 0.0 -@P: CPU Time : 0h:00m:02s diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm deleted file mode 100644 index 2d8be4d..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm +++ /dev/null @@ -1,428 +0,0 @@ -

    -
-#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
-#install: /home/soft/lattice/diamond/3.10_x64/synpbase
-#OS: Linux 
-#Hostname: lxhadeb07
-
-# Fri May 10 14:33:10 2019
-
-#Implementation: syn_results
-
-Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
-@N: :  | Running in 64-bit mode 
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
-@N: :  | Running in 64-bit mode 
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Running on host :lxhadeb07
-@N:CD720 : std.vhd(123) | Setting time resolution to ps
-@N: : pll_200_125_100.vhd(12) | Top entity is set to pll_200_125_100.
-VHDL syntax check successful!
-@N:CD630 : pll_200_125_100.vhd(12) | Synthesizing work.pll_200_125_100.structure.
-@N:CD630 : ecp5um.vhd(2083) | Synthesizing ecp5um.ehxplll.syn_black_box.
-Post processing for ecp5um.ehxplll.syn_black_box
-@N:CD630 : ecp5um.vhd(832) | Synthesizing ecp5um.vlo.syn_black_box.
-Post processing for ecp5um.vlo.syn_black_box
-@N:CD630 : ecp5um.vhd(825) | Synthesizing ecp5um.vhi.syn_black_box.
-Post processing for ecp5um.vhi.syn_black_box
-Post processing for work.pll_200_125_100.structure
-@W:CL168 : pll_200_125_100.vhd(50) | Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 14:33:11 2019
-
-###########################################################]
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
-@N: :  | Running in 64-bit mode 
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 14:33:11 2019
-
-###########################################################]
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 14:33:11 2019
-
-###########################################################]
-
-
    -
    -
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
-@N: :  | Running in 64-bit mode 
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 14:33:12 2019
-
-###########################################################]
-
-
     -
    -
-Pre-mapping Report
-
-
-
     -
    -
-# Fri May 10 14:33:12 2019
-
-Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-Reading constraint file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc
-Linked File: pll_200_125_100_scck.rpt
-Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt" file 
-@N:MF248 :  | Running in 64-bit mode. 
-@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
-
-ICG Latch Removal Summary:
-Number of ICG latches removed:	0
-Number of ICG latches not removed:	0
-syn_allowed_resources : blockrams=56  set on top level netlist pll_200_125_100
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-
-Clock Summary
-******************
-
-          Start      Requested     Requested     Clock      Clock               Clock
-Level     Clock      Frequency     Period        Type       Group               Load 
--------------------------------------------------------------------------------------
-0 -       System     100.0 MHz     10.000        system     system_clkgroup     0    
-=====================================================================================
-
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-None
-None
-
-Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Fri May 10 14:33:13 2019
-
-###########################################################]
-
-
     -
    -
-Map & Optimize Report
-
-
-
     -
    -
-# Fri May 10 14:33:13 2019
-
-Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-@N:MF248 :  | Running in 64-bit mode. 
-@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Available hyper_sources - for debug and ip models
-	None Found
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-Pass		 CPU time		Worst Slack		Luts / Registers
-------------------------------------------------------------
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-
-@S |Clock Optimization Summary
-
-
-#### START OF CLOCK OPTIMIZATION REPORT #####[
-
-0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######]
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB)
-
-Writing Analyst data base /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-Writing EDIF Netlist and constraint files
-@N:FX1056 :  | Writing EDF file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.edn 
-M-2017.03L-SP1-1
-@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
-
-Writing Verilog Simulation files
-
-Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
-
-Writing VHDL Simulation files
-
-Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
-
-@W:MT246 : pll_200_125_100.vhd(56) | Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
-
-
-##### START OF TIMING REPORT #####[
-# Timing Report written on Fri May 10 14:33:15 2019
-#
-
-
-Top view:               pll_200_125_100
-Requested Frequency:    100.0 MHz
-Wire load mode:         top
-Paths requested:        5
-Constraint File(s):    /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc
-                       
-@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
-
-@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: 10.000
-
-@N:MT286 :  | System clock period 0.000 stretches to negative invalid value -- ignoring stretching. 
-                   Requested     Estimated     Requested     Estimated                Clock      Clock          
-Starting Clock     Frequency     Frequency     Period        Period        Slack      Type       Group          
-----------------------------------------------------------------------------------------------------------------
-System             100.0 MHz     NA            10.000        0.000         10.000     system     system_clkgroup
-================================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-
-
-
-Clock Relationships
-*******************
-
-Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------
-Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------
-System    System  |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
-=========================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
-       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information 
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: System
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-              Starting                                           Arrival           
-Instance      Reference     Type        Pin          Net         Time        Slack 
-              Clock                                                                
------------------------------------------------------------------------------------
-PLLInst_0     System        EHXPLLL     CLKINTFB     CLKFB_t     0.000       10.000
-===================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-              Starting                                        Required           
-Instance      Reference     Type        Pin       Net         Time         Slack 
-              Clock                                                              
----------------------------------------------------------------------------------
-PLLInst_0     System        EHXPLLL     CLKFB     CLKFB_t     10.000       10.000
-=================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      10.000
-    - Setup time:                            0.000
-    + Clock delay at ending point:           0.000 (ideal)
-    + Estimated clock delay at ending point: 0.000
-    = Required time:                         10.000
-
-    - Propagation time:                      0.000
-    - Clock delay at starting point:         0.000 (ideal)
-    - Estimated clock delay at start point:  -0.000
-    = Slack (critical) :                     10.000
-
-    Number of logic level(s):                0
-    Starting point:                          PLLInst_0 / CLKINTFB
-    Ending point:                            PLLInst_0 / CLKFB
-    The start point is clocked by            System [rising]
-    The end   point is clocked by            System [rising]
-
-Instance / Net                 Pin          Pin               Arrival     No. of    
-Name               Type        Name         Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------
-PLLInst_0          EHXPLLL     CLKINTFB     Out     0.000     0.000       -         
-CLKFB_t            Net         -            -       -         -           1         
-PLLInst_0          EHXPLLL     CLKFB        In      0.000     0.000       -         
-====================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-None
-
-Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
-
----------------------------------------
-Resource Usage Report
-Part: lfe5um_25f-6
-
-Register bits: 0 of 24288 (0%)
-PIC Latch:       0
-I/O cells:       0
-
-
-Details:
-EHXPLLL:        1
-GSR:            1
-PUR:            1
-VHI:            1
-VLO:            1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB)
-
-Process took 0h:00m:02s realtime, 0h:00m:02s cputime
-# Fri May 10 14:33:15 2019
-
-###########################################################]
-
-
     diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_toc.htm b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_toc.htm deleted file mode 100644 index 75d317d..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_toc.htm +++ /dev/null @@ -1,45 +0,0 @@ - - - - - - - - - - - - - - \ No newline at end of file diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/run_option.xml b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/run_option.xml deleted file mode 100644 index 35a3688..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/run_option.xml +++ /dev/null @@ -1,24 +0,0 @@ - - - - - - - - - - - - - - - - - diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/statusReport.html b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/statusReport.html deleted file mode 100644 index c4d093f..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/statusReport.html +++ /dev/null @@ -1,112 +0,0 @@ - - - Project Status Summary Page - - - - - - -
    - - - - - - - - - - -
    Project Settings
    Project Name pll_200_125_100 Device Name syn_results: Lattice ECP5UM : LFE5UM_25F
    Implementation Name syn_results Top Module pll_200_125_100
    Pipelining 0 Retiming 0
    Resource Sharing 1 Fanout Guide 50
    Disable I/O Insertion 1 Disable Sequential Optimizations 0
    Clock Conversion 1 FSM Compiler 1

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    Run Status
    Job NameStatusCPU TimeReal TimeMemoryDate/Time
    (compiler)Complete910-00m:01s-5/10/19
    2:33 PM
    (premap)Complete2000m:00s0m:00s143MB5/10/19
    2:33 PM
    (fpga_mapper)Complete8100m:02s0m:02s146MB5/10/19
    2:33 PM
    Multi-srs GeneratorComplete5/10/19
    2:33 PM
    -
    - - - - - - - - - - - - - - - - -
    Area Summary
    Register bits 0I/O cells 0
    Block RAMs -(v_ram) 0DSPs -(dsp_used) 0
    ORCA LUTs -(total_luts) 0

    - - - - - - - - -
    Timing Summary
    Clock NameReq FreqEst FreqSlack
    System100.0 MHzNA10.000
    -
    - - - - - - -
    Optimizations Summary
    Combined Clock Conversion 0 / 0

    -
    -
    - \ No newline at end of file diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/.cckTransfer b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/.cckTransfer deleted file mode 100644 index 8d68b51ffc123b9e9915c50b3dcd0e75f3d66b87..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 456 zcmV;(0XP01iwFP!0000015#C0RVXORFG)=a{vaLcI6*^mGAZ z9&d$5|4m>w&WRYZ^EqN=LB_ZWh}q~zk2Uk~$$!>h^&qn$=dq*jHKwE;j_u+XZtHC~ zDNT4e?*X*S(*o6H9cA=h&$Pzfmm}Kaa{u{+cCnIZV+gS}JPc0_dT99AVHbpaleyTW z4!H}+L1lQ)Hzb*CX3|WO4L&m5Wz@{%6d@nk5$cD=2BdNn=ZsD)GPd9;qzR+vFc}e~ z2Qh;jbI7n%R4Y?LN*0BzTz?sj^@BY}(sz)5lWgP>C2WvXKbnlYvQysXt zlt$8U)tl>rHmTB(wH5=!6KU{Cw^SU!7Z277ipzuK2 z4HO-tYY2GTmY0HmXs%6>Hv#?gpA>+}_^lTNUo9bKj7XSeN{{sNLV`sjt0ssK%qu^!$ diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/_mh_info b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/_mh_info deleted file mode 100644 index 37bc105..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/_mh_info +++ /dev/null @@ -1 +0,0 @@ -|1| diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.fdep b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.fdep deleted file mode 100644 index 0d906a3..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.fdep +++ /dev/null @@ -1,28 +0,0 @@ -#defaultlanguage:vhdl -#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_comp.srs|-top|pll_200_125_100|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work" -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610 -#CUR:"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":1557491589 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599 -0 "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd" vhdl - -# Dependency Lists (Uses list) -0 -1 - -# Dependency Lists (Users Of) -0 -1 - -# Design Unit to File Association -arch work pll_200_125_100 structure 0 -module work pll_200_125_100 0 - - -# Configuration files used diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.fdeporig b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.fdeporig deleted file mode 100644 index 7b38ff3..0000000 --- a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.fdeporig +++ /dev/null @@ -1,24 +0,0 @@ -#defaultlanguage:vhdl -#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_comp.srs|-top|pll_200_125_100|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work" -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610 -#CUR:"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":1557491589 -0 "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd" vhdl - -# Dependency Lists (Uses list) -0 -1 - -# Dependency Lists (Users Of) -0 -1 - -# Design Unit to File Association -arch work pll_200_125_100 structure 0 -module work pll_200_125_100 0 diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.srs b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.srs deleted file mode 100644 index b9cb7b8176f7c01c4120f5032e22ba2349cb106b..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 6188 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:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box. -Post processing for ecp5um.vlo.syn_black_box -@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box. -Post processing for ecp5um.vhi.syn_black_box -Post processing for work.pll_200_125_100.structure -@W: CL168 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":50:4:50:17|Removing instance scuba_vhi_inst because it does not drive other instances. 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a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr deleted file mode 100644 index cd2e67c..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr +++ /dev/null @@ -1,201 +0,0 @@ -Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. - -Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. - -Running on host :lxhadeb07 -@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps -@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Top entity is set to PCSD. -VHDL syntax check successful! -File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling - -At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 72MB) - - -Process completed successfully. -# Tue Apr 30 12:09:44 2019 - -###########################################################] -Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. - -Running on host :lxhadeb07 -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) -@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work) -Verilog syntax check successful! - -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) - - -Process completed successfully. -# Tue Apr 30 12:09:45 2019 - -###########################################################] -Running on host :lxhadeb07 -@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps -@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Top entity is set to PCSD. -File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling -File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling -VHDL syntax check successful! -File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling -@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Synthesizing work.pcsd.v1. -Post processing for work.pcsd.v1 - -At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) - - -Process completed successfully. -# Tue Apr 30 12:09:45 2019 - -###########################################################] -Running on host :lxhadeb07 -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) -@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work) -Verilog syntax check successful! -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":92:7:92:18|Synthesizing module PCSDrsl_core in library work. - - pnum_channels=32'b00000000000000000000000000000001 - pprotocol=24'b010001110100001001000101 - pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 - pport_tx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100 - pwait_tx_rdy=32'b00000000000000000000101110111000 - pport_rx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100 - pwait_rx_rdy=32'b00000000000000000000101110111000 - wa_num_cycles=32'b00000000000000000000010000000000 - dac_num_cycles=32'b00000000000000000000000000000011 - lreset_pwidth=32'b00000000000000000000000000000011 - lwait_b4_trst=32'b00000000000010111110101111000010 - lwait_b4_trst_s=32'b00000000000000000000001100001101 - lplol_cnt_width=32'b00000000000000000000000000010100 - lwait_after_plol0=32'b00000000000000000000000000000100 - lwait_b4_rrst=32'b00000000000000101100000000000000 - lrrst_wait_width=32'b00000000000000000000000000010100 - lwait_after_rrst=32'b00000000000011000011010100000000 - lwait_b4_rrst_s=32'b00000000000000000000000111001100 - lrlol_cnt_width=32'b00000000000000000000000000010011 - lwait_after_lols=32'b00000000000000001100010000000000 - lwait_after_lols_s=32'b00000000000000000000000010010110 - llols_cnt_width=32'b00000000000000000000000000010010 - lrdb_max=32'b00000000000000000000000000001111 - ltxr_wait_width=32'b00000000000000000000000000001100 - lrxr_wait_width=32'b00000000000000000000000000001100 - Generated name = PCSDrsl_core_Z1_layer1 -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":274:33:274:48|Removing wire dual_or_serd_rst, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":275:33:275:46|Removing wire tx_any_pcs_rst, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":276:33:276:42|Removing wire tx_any_rst, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":277:33:277:41|Object txsr_appd is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":278:33:278:42|Object txdpr_appd is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":279:33:279:41|Object txpr_appd is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":280:33:280:41|Object txr_wt_en is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":281:33:281:42|Object txr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":282:33:282:41|Removing wire txr_wt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":283:33:283:43|Object ruo_tx_rdyr is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":356:33:356:41|Object rxsr_appd is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":357:33:357:41|Object rxpr_appd is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":358:33:358:42|Object rxsdr_appd is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":359:33:359:42|Object rxdpr_appd is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":360:33:360:48|Removing wire rxsdr_or_sr_appd, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":361:33:361:49|Removing wire dual_or_rserd_rst, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":362:33:362:46|Removing wire rx_any_pcs_rst, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":363:33:363:42|Removing wire rx_any_rst, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":364:33:364:41|Object rxr_wt_en is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":365:33:365:42|Object rxr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":366:33:366:41|Removing wire rxr_wt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":367:33:367:43|Object ruo_rx_rdyr is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":507:10:507:10|Object m is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":880:10:880:10|Object l is declared but not assigned. Either assign a value or remove the declaration. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. - -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 75MB) - - -Process completed successfully. -# Tue Apr 30 12:09:45 2019 - -###########################################################] -Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer0.srs changed - recompiling -File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer1.srs changed - recompiling - -======================================================================================= -For a summary of linker messages for components that did not bind, please see log file: -@L: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.linkerlog -======================================================================================= - - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Tue Apr 30 12:09:46 2019 - -###########################################################] -@END - -At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Tue Apr 30 12:09:46 2019 - -###########################################################] diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr.db b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr.db deleted file mode 100644 index 64aab840978977f4a582ac1d60aca86e02f0c33d..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 20480 zcmeHP&2JmW6(=Rqlq|_i(%5dBx*aQ(W5)`~{osd~2B_pXjwBj(EC)Uq!D7iBQClr{ z7qdf3G6WP93N$eK7xdQl-b;~N3-sJ;kv||n?*)n?K-x>+%q&gHN+eO4u@Q6$d!Mx; zx$pO8=FPnKd(RsmHC&3(WA~VMx``g+zL9lXgkEU{bJjtMM|3Gs8yu66M8nq#gGKQ zz%5#g+8x&|-oLf+KEGH|ut~k3?Y0WN`MP0N>xRLFS>AtuJ3-I&+i1rn7!fb{0Q_I0E&nDPG%`OEUX{;o63h1`Wl#g#98^+t~ViXWW7-r0%#UHn+8~7t= z7GCFQ(y|Q?R%eDc7@Fq{zZ;&x>K}fO>v>1E)pemKh^1#%2L(w)m6`m**VI7K1QZa5 zpuh}Q24(G44rN{PsOU8g1%#4>t z7!CH7O`x^&O2AZ?I2aJ4U_xTqVF+hHMTd*^X(jWl%C`p{#OOS8RHIp&QZqDsf6%M2 zKRny)=x(HVXclrDjO25lUgdiT6GzT{;CgL;kDaW>Ic?uK$Mu|+>`|*_u^!5GvvS0v zay`RVG_I~Uvs~9X*}9rSSF>)`p3~Lo+MX2Jp z_bbNP1HnRX%bBn1Ca41!t#nu&{yZ3Ar_j^Hb2IxB@Z7iVu;*6w!E;$OS%i3#x-DFE zT)PwaPSGf6C2O~07Nb2sY}yen0*oR&uNYDILiSuuH^2m3=-U1UhA#jkP`3kdCyoNI z%c3wAS%wiuo!N)D|3yC?BKXYPaGAWsxcN&E(&rEInG3&}`*#xmC-MKcOuQuV|2L*w zlKB6mv|SSaADe+p;{THpze)Um>;zg*;{Ox5gCzcE49K@57n1n@WR8jj{w&Xw#Q$H* zwk7euUQOcv@rmFh{y%m0Vfn8t{(n97k5vBAghuCr@x|32xm8UfVx zyAjaz1h?IY0xjRhe$(653#{b83XKA~Yj0x|bs+~vx1ixd6dnMz&nge%4?|f7CLIhp zCuqzVd{Z<++&{R%;aGCv)Jl-Rt+VSX;0PjLf2`L_pU45Va-C;T-(?w8d9@Wa;Bd53 zU5Ei2=qY18R^CzpqFkyn5JC(nWKpGb*A^3d9k?2xPxOx!7Bie|P%1)g3zt7=3l6&?y%3?PF zVO9sn<`Foo{8AaDYnM4B*%hT_v15QZT2UIuWaCXG7XQy?K2PPf3%BMzo^8*x&Rf%u zr)ci!xj$t848KTTi3Ji1Bo_ECS)lJ!xc6nn*bUvRNJ{wWkcVM>4G1`|ulgZ0OsH zTDttU=-zRM4}y|9Jdy}>%4%SWN>0cGo(85DL;!O~B}`KdOi>70g51clquJ%783(ym zOWA0)4F>ZdD|^xk4yk0;%i3|1R={M@G3Mp33XwXxngQj9BfZ4K>0_2BAccx#gflt^*ZKGD;N7RN8uv9<~1GJ5C$Y-(3 zZ?`aH+``b?6YnE7tP=!P-&P1!+?e$6d$83*9XFJE4n8oP_5JO4l%O4%^(Uj{t+tQ# g7lC$B1=>+RcRX64S6|@RHf}PsFPTh^WRc1L0}i|FPXGV_ diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr.rptmap b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr.rptmap deleted file mode 100644 index 0168f12..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr.rptmap +++ /dev/null @@ -1 +0,0 @@ -./synlog/PCSD_compiler.srr,PCSD_compiler.srr,Compile Log diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.srr b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.srr deleted file mode 100644 index da6761e..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.srr +++ /dev/null @@ -1,537 +0,0 @@ -# Tue Apr 30 12:09:48 2019 - -Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. -Product Version M-2017.03L-SP1-1 - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) - -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) - - - -Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Available hyper_sources - for debug and ip models - None Found - - -Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - -@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk1\.plol_cnt[19:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":778:3:778:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":680:3:680:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] - -Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) - - -Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) - - -Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) - - -Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) - - -Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) - - -Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) - - -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) - - -Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) - - -Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) - -Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------- - 1 0h:00m:00s 5.36ns 63 / 92 - -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) - -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. - -Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB) - - - -@S |Clock Optimization Summary - - -#### START OF CLOCK OPTIMIZATION REPORT #####[ - -2 non-gated/non-generated clock tree(s) driving 92 clock pin(s) of sequential element(s) -0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) -0 instances converted, 0 sequential instances remain driven by gated/generated clocks - -=================================== Non-Gated/Non-Generated Clocks ==================================== -Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance -------------------------------------------------------------------------------------------------------- -@K:CKID0001 rxrefclk port 59 rsl_inst.genblk2\.rlol1_cnt[18] -@K:CKID0002 pll_refclki port 33 rsl_inst.genblk1\.pll_lol_p1 -======================================================================================================= - - -##### END OF CLOCK OPTIMIZATION REPORT ######] - - -Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 107MB peak: 144MB) - -Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_m.srm - -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB) - -Writing EDIF Netlist and constraint files -@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.edn -M-2017.03L-SP1-1 -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF - -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB) - -Writing Verilog Simulation files - -Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB) - -Writing VHDL Simulation files - -Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB) - - -Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB) - -@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":118:4:118:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) -@W: MT420 |Found inferred clock PCSD|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" -@W: MT420 |Found inferred clock PCSD|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" - - -##### START OF TIMING REPORT #####[ -# Timing Report written on Tue Apr 30 12:09:50 2019 -# - - -Top view: PCSD -Requested Frequency: 100.0 MHz -Wire load mode: top -Paths requested: 5 -Constraint File(s): /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc - -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. - -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. - - - -Performance Summary -******************* - - -Worst slack in design: 4.079 - -@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. - Requested Estimated Requested Estimated Clock Clock -Starting Clock Frequency Frequency Period Period Slack Type Group -------------------------------------------------------------------------------------------------------------------------- -PCSD|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0 -PCSD|rxrefclk 100.0 MHz 170.5 MHz 10.000 5.864 4.136 inferred Inferred_clkgroup_1 -System 100.0 MHz 18518.5 MHz 10.000 0.054 9.946 system system_clkgroup -========================================================================================================================= - - - - - -Clock Relationships -******************* - -Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------------- -Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------------- -System System | 10.000 10.000 | No paths - | No paths - | No paths - -System PCSD|rxrefclk | 10.000 9.946 | No paths - | No paths - | No paths - -PCSD|pll_refclki System | 10.000 8.385 | No paths - | No paths - | No paths - -PCSD|pll_refclki PCSD|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths - -PCSD|rxrefclk System | 10.000 8.283 | No paths - | No paths - | No paths - -PCSD|rxrefclk PCSD|rxrefclk | 10.000 4.136 | No paths - | No paths - | No paths - -=========================================================================================================================== - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - - -Interface Information -********************* - -No IO constraint found - - - -==================================== -Detailed Report for Clock: PCSD|pll_refclki -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock --------------------------------------------------------------------------------------------------------------- -rsl_inst.genblk1\.plol_cnt[1] PCSD|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.079 -rsl_inst.genblk1\.plol_cnt[6] PCSD|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.079 -rsl_inst.genblk1\.plol_cnt[7] PCSD|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.079 -rsl_inst.genblk1\.plol_cnt[12] PCSD|pll_refclki FD1S3DX Q plol_cnt[12] 0.907 4.079 -rsl_inst.genblk1\.plol_cnt[2] PCSD|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.684 -rsl_inst.genblk1\.plol_cnt[3] PCSD|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.684 -rsl_inst.genblk1\.plol_cnt[4] PCSD|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684 -rsl_inst.genblk1\.plol_cnt[5] PCSD|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684 -rsl_inst.genblk1\.plol_cnt[8] PCSD|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684 -rsl_inst.genblk1\.plol_cnt[9] PCSD|pll_refclki FD1S3DX Q plol_cnt[9] 0.907 4.684 -============================================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------ -rsl_inst.genblk1\.plol_cnt[19] PCSD|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079 -rsl_inst.genblk1\.plol_cnt[17] PCSD|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139 -rsl_inst.genblk1\.plol_cnt[18] PCSD|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139 -rsl_inst.genblk1\.plol_cnt[15] PCSD|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200 -rsl_inst.genblk1\.plol_cnt[16] PCSD|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200 -rsl_inst.genblk1\.plol_cnt[13] PCSD|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261 -rsl_inst.genblk1\.plol_cnt[14] PCSD|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261 -rsl_inst.genblk1\.plol_cnt[11] PCSD|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322 -rsl_inst.genblk1\.plol_cnt[12] PCSD|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322 -rsl_inst.genblk1\.plol_cnt[9] PCSD|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383 -================================================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.054 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 9.946 - - - Propagation time: 5.867 - - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : 4.079 - - Number of logic level(s): 15 - Starting point: rsl_inst.genblk1\.plol_cnt[1] / Q - Ending point: rsl_inst.genblk1\.plol_cnt[19] / D - The start point is clocked by PCSD|pll_refclki [rising] on pin CK - The end point is clocked by PCSD|pll_refclki [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------- -rsl_inst.genblk1\.plol_cnt[1] FD1S3DX Q Out 0.907 0.907 - -plol_cnt[1] Net - - - - 2 -rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 - -rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 - -un1_plol_cnt_tc_10 Net - - - - 1 -rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 - -rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 - -un1_plol_cnt_tc_14 Net - - - - 1 -rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 - -rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 - -un1_plol_cnt_tc Net - - - - 5 -rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 - -rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 - -plol_cnt Net - - - - 21 -rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 - -rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 - -plol_cnt_cry[0] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 - -rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 - -plol_cnt_cry[2] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 - -rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 - -plol_cnt_cry[4] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 - -rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 - -plol_cnt_cry[6] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 - -rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 - -plol_cnt_cry[8] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 - -rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 - -plol_cnt_cry[10] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 - -rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 - -plol_cnt_cry[12] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 - -rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 - -plol_cnt_cry[14] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 - -rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 - -plol_cnt_cry[16] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 - -rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 - -plol_cnt_cry[18] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 - -rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 - -plol_cnt_s[19] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 - -======================================================================================================= - - - - -==================================== -Detailed Report for Clock: PCSD|rxrefclk -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------------------- -rsl_inst.genblk2\.rlol1_cnt[14] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[14] 0.907 4.136 -rsl_inst.genblk2\.rlol1_cnt[15] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[15] 0.907 4.136 -rsl_inst.genblk2\.rlol1_cnt[16] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[16] 0.907 4.136 -rsl_inst.genblk2\.rlol1_cnt[17] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[17] 0.907 4.136 -rsl_inst.genblk2\.rlols0_cnt[10] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[10] 0.907 4.170 -rsl_inst.genblk2\.rlols0_cnt[14] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[14] 0.907 4.170 -rsl_inst.genblk2\.rlols0_cnt[16] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[16] 0.907 4.170 -rsl_inst.genblk2\.rlols0_cnt[17] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[17] 0.907 4.170 -rsl_inst.genblk2\.rlol1_cnt[0] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742 -rsl_inst.genblk2\.rlol1_cnt[1] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[1] 0.907 4.742 -=============================================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------- -rsl_inst.genblk2\.rlol1_cnt[17] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136 -rsl_inst.genblk2\.rlol1_cnt[18] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136 -rsl_inst.genblk2\.rlols0_cnt[17] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170 -rsl_inst.genblk2\.rlol1_cnt[15] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197 -rsl_inst.genblk2\.rlol1_cnt[16] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197 -rsl_inst.genblk2\.rlols0_cnt[15] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[15] 9.946 4.231 -rsl_inst.genblk2\.rlols0_cnt[16] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[16] 9.946 4.231 -rsl_inst.genblk2\.rlol1_cnt[13] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[13] 9.946 4.258 -rsl_inst.genblk2\.rlol1_cnt[14] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[14] 9.946 4.258 -rsl_inst.genblk2\.rlols0_cnt[13] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[13] 9.946 4.292 -================================================================================================================== - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.054 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 9.946 - - - Propagation time: 5.809 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.136 - - Number of logic level(s): 14 - Starting point: rsl_inst.genblk2\.rlol1_cnt[14] / Q - Ending point: rsl_inst.genblk2\.rlol1_cnt[18] / D - The start point is clocked by PCSD|rxrefclk [rising] on pin CK - The end point is clocked by PCSD|rxrefclk [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------- -rsl_inst.genblk2\.rlol1_cnt[14] FD1P3DX Q Out 0.907 0.907 - -rlol1_cnt[14] Net - - - - 2 -rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 A In 0.000 0.907 - -rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 Z Out 0.606 1.513 - -rlol1_cnt_tc_1_10 Net - - - - 1 -rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 D In 0.000 1.513 - -rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 Z Out 0.606 2.119 - -rlol1_cnt_tc_1_14 Net - - - - 1 -rsl_inst.rlol1_cnt_tc_1 ORCALUT4 D In 0.000 2.119 - -rsl_inst.rlol1_cnt_tc_1 ORCALUT4 Z Out 0.768 2.887 - -rlol1_cnt_tc_1 Net - - - - 6 -rsl_inst.genblk2\.rxs_rst_RNIS0OP ORCALUT4 A In 0.000 2.887 - -rsl_inst.genblk2\.rxs_rst_RNIS0OP ORCALUT4 Z Out 0.837 3.724 - -rlol1_cnt Net - - - - 20 -rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C A1 In 0.000 3.724 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C COUT Out 0.900 4.624 - -rlol1_cnt_cry[0] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C CIN In 0.000 4.624 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C COUT Out 0.061 4.685 - -rlol1_cnt_cry[2] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C CIN In 0.000 4.685 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C COUT Out 0.061 4.746 - -rlol1_cnt_cry[4] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C CIN In 0.000 4.746 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C COUT Out 0.061 4.807 - -rlol1_cnt_cry[6] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C CIN In 0.000 4.807 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C COUT Out 0.061 4.868 - -rlol1_cnt_cry[8] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C CIN In 0.000 4.868 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C COUT Out 0.061 4.929 - -rlol1_cnt_cry[10] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C CIN In 0.000 4.929 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C COUT Out 0.061 4.990 - -rlol1_cnt_cry[12] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C CIN In 0.000 4.990 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C COUT Out 0.061 5.051 - -rlol1_cnt_cry[14] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C CIN In 0.000 5.051 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C COUT Out 0.061 5.112 - -rlol1_cnt_cry[16] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C CIN In 0.000 5.112 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C S1 Out 0.698 5.809 - -rlol1_cnt_s[18] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt[18] FD1P3DX D In 0.000 5.809 - -======================================================================================================== - - - - -==================================== -Detailed Report for Clock: System -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock -------------------------------------------------------------------------------------------- -DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 9.946 -DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 9.946 -DCU0_inst System DCUA CH0_FF_TX_PCLK tx_pclk 0.000 10.000 -=========================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ----------------------------------------------------------------------------------------------------------------- -rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946 -rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946 -DCU0_inst System DCUA CH0_FF_EBRD_CLK tx_pclk 10.000 10.000 -DCU0_inst System DCUA CH0_FF_RXI_CLK tx_pclk 10.000 10.000 -================================================================================================================ - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.054 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 9.946 - - - Propagation time: 0.000 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (non-critical) : 9.946 - - Number of logic level(s): 0 - Starting point: DCU0_inst / CH0_FFS_RLOL - Ending point: rsl_inst.genblk2\.rlol_p1 / D - The start point is clocked by System [rising] - The end point is clocked by PCSD|rxrefclk [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------- -DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 - -rx_cdr_lol_s Net - - - - 2 -rsl_inst.genblk2\.rlol_p1 FD1S3DX D In 0.000 0.000 - -=================================================================================================== - - - -##### END OF TIMING REPORT #####] - -Timing exceptions that could not be applied -None - -Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB) - - -Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB) - ---------------------------------------- -Resource Usage Report -Part: lfe5um_25f-6 - -Register bits: 92 of 24288 (0%) -PIC Latch: 0 -I/O cells: 0 - - -Details: -CCU2C: 37 -DCUA: 1 -FD1P3BX: 4 -FD1P3DX: 42 -FD1S3BX: 10 -FD1S3DX: 36 -GSR: 1 -ORCALUT4: 63 -PFUMX: 2 -PUR: 1 -VHI: 2 -VLO: 2 -Mapper successful! - -At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 32MB peak: 148MB) - -Process took 0h:00m:02s realtime, 0h:00m:02s cputime -# Tue Apr 30 12:09:51 2019 - -###########################################################] diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.srr.db b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.srr.db deleted file mode 100644 index b2fe294f4efe46b9adcc1481761fbc4514e1da1b..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8192 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zeJ;0-a~><0CtBsyc6%=K{UZ7w^D|)A$2hke$4t1s3M(=WH0W)(f-= zc6mX=H*^2tSidtidslJuCe2vp5Ax67S#KNX$=vC-N1y#N*Gt(N`lHWz*|iRDeXr$o@EN$B!!rPHr;VmSW4(_vANmom zmiQj!$@oC}y;7rV>}a3>zjd0;cv!DEXoa1j5!OB1Yi7Mu?^Hv}o{pEA+V|+h@sNxG j%@=nqVp;zW00960;&M>n0ssI2|NjF3<}rCzsGtA<5JZb0 diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.xck b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.xck deleted file mode 100644 index 090e73d..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.xck +++ /dev/null @@ -1,2 +0,0 @@ -CKID0001:@|S:rxrefclk@|E:rsl_inst.genblk2\.rlol1_cnt[18]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001 -CKID0002:@|S:pll_refclki@|E:rsl_inst.genblk1\.pll_lol_p1@|F:@syn_sample_clock_path==CKID0002@|M:ClockId0002 diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_multi_srs_gen.srr b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_multi_srs_gen.srr deleted file mode 100644 index fc78ac1..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_multi_srs_gen.srr +++ /dev/null @@ -1,12 +0,0 @@ -Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs changed - recompiling - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Tue Apr 30 12:09:47 2019 - -###########################################################] diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_multi_srs_gen.srr.db b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_multi_srs_gen.srr.db deleted file mode 100644 index 029fa7a6cf9014af50ee9d4aa843536a1f7b5c42..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8192 zcmeI#JqyA>3DEQgKL*xDXO@ z%d=&(imfwzIG4G0Jf%J073BwWN1`{~f``Krs^Nta{J wY>_tId!-qqw)j}S$WL3iQGJ`s(T{)t1Rwwb2tWV=5P$##AOHafK;VZ3UKAiP82|tP diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_premap.srr b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_premap.srr deleted file mode 100644 index fe3b5ab..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_premap.srr +++ /dev/null @@ -1,70 +0,0 @@ -# Tue Apr 30 12:09:47 2019 - -Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. -Product Version M-2017.03L-SP1-1 - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) - -Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc -@L: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt -Printing clock summary report in "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt" file -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB) - -ICG Latch Removal Summary: -Number of ICG latches removed: 0 -Number of ICG latches not removed: 0 -syn_allowed_resources : blockrams=56 set on top level netlist PCSD - -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - - -Clock Summary -****************** - - Start Requested Requested Clock Clock Clock -Level Clock Frequency Period Type Group Load ------------------------------------------------------------------------------------------------------ -0 - System 100.0 MHz 10.000 system system_clkgroup 0 - -0 - PCSD|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 59 - -0 - PCSD|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 33 -===================================================================================================== - -@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found inferred clock PCSD|pll_refclki which controls 33 sequential elements including rsl_inst.genblk1\.plol_cnt[19:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Found inferred clock PCSD|rxrefclk which controls 59 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. - -Finished Pre Mapping Phase. - -Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - -None -None - -Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - -Pre-mapping successful! - -At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Tue Apr 30 12:09:48 2019 - -###########################################################] diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_premap.srr.db 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zvhIp1=Ou%YIJ71{oTeaPgz-)rsYz6vkZIYQit%Ylo#)T9qe?}|mc8gJU+>QY?qf>c zV>A>nn9e(V*b_iYHespfpivx{$_s`gm%}mjB+lW z8>G4T^Lz)_x;TSheGXfHHixb6=dd&fQIOhHGY`2y_0`V6Q5s;3;3>vbENNd~U_UCm zHrGJ^41D5FU&}W!+kq{DH(pPPdnZ50Zv3yeG`m{7pP_$u#((X3b>85!f3cT+90={y zFuUW3HF3mr^rx%}@{2MP4O|N5j?oEPMY;uk8Kr zPYJ_L;PilWUy|-7wb9{fb3`=&iW!mp9{>OV|Nr80P~ZXp009600|2*BC#QED006c$ B@wxy2 diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/layer0.tlg.rptmap b/gbe/cores/sgmii/PCSD/syn_results/synlog/layer0.tlg.rptmap deleted file mode 100644 index 3910cac..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/synlog/layer0.tlg.rptmap +++ /dev/null @@ -1 +0,0 @@ -./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages. diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/layer1.tlg.rptmap b/gbe/cores/sgmii/PCSD/syn_results/synlog/layer1.tlg.rptmap deleted file mode 100644 index af92e0b..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/synlog/layer1.tlg.rptmap +++ /dev/null @@ -1 +0,0 @@ -./synwork/layer1.tlg,layer1.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages. diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/linker.rpt.rptmap b/gbe/cores/sgmii/PCSD/syn_results/synlog/linker.rpt.rptmap deleted file mode 100644 index e21637c..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/synlog/linker.rpt.rptmap +++ /dev/null @@ -1 +0,0 @@ -./synwork/PCSD_comp.linkerlog,linker.rpt,Summary of linker messages for components that did not bind diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_notes.txt b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_notes.txt deleted file mode 100644 index 64eb40e..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_notes.txt +++ /dev/null @@ -1,11 +0,0 @@ -@N|Running in 64-bit mode -@N|Running in 64-bit mode -@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps -@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Top entity is set to PCSD. -@N|Running in 64-bit mode -@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps -@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Top entity is set to PCSD. -@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Synthesizing work.pcsd.v1. -@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":92:7:92:18|Synthesizing module PCSDrsl_core in library work. -@N|Running in 64-bit mode - diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_runstatus.xml b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_runstatus.xml deleted file mode 100644 index 5ab9b80..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_runstatus.xml +++ /dev/null @@ -1,41 +0,0 @@ - - - - - - /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr - Synopsys HDL Compiler - - - Completed - - - - 10 - /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_notes.txt - - - 50 - /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_warnings.txt - - - 0 - /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_errors.txt - - - - - - - 00h:00m:02s - - - - - - - 1556618986 - - - \ No newline at end of file diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_warnings.txt b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_warnings.txt deleted file mode 100644 index 664f602..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_warnings.txt +++ /dev/null @@ -1,51 +0,0 @@ -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":274:33:274:48|Removing wire dual_or_serd_rst, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":275:33:275:46|Removing wire tx_any_pcs_rst, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":276:33:276:42|Removing wire tx_any_rst, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":277:33:277:41|Object txsr_appd is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":278:33:278:42|Object txdpr_appd is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":279:33:279:41|Object txpr_appd is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":280:33:280:41|Object txr_wt_en is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":281:33:281:42|Object txr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":282:33:282:41|Removing wire txr_wt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":283:33:283:43|Object ruo_tx_rdyr is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":356:33:356:41|Object rxsr_appd is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":357:33:357:41|Object rxpr_appd is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":358:33:358:42|Object rxsdr_appd is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":359:33:359:42|Object rxdpr_appd is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":360:33:360:48|Removing wire rxsdr_or_sr_appd, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":361:33:361:49|Removing wire dual_or_rserd_rst, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":362:33:362:46|Removing wire rx_any_pcs_rst, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":363:33:363:42|Removing wire rx_any_rst, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":364:33:364:41|Object rxr_wt_en is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":365:33:365:42|Object rxr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":366:33:366:41|Removing wire rxr_wt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":367:33:367:43|Object ruo_rx_rdyr is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":507:10:507:10|Object m is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":880:10:880:10|Object l is declared but not assigned. Either assign a value or remove the declaration. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. - diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_area_report.xml b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_area_report.xml deleted file mode 100644 index 194415f..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_area_report.xml +++ /dev/null @@ -1,26 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_resourceusage.rpt -Resource Usage - - -92 - - -0 - - -0 - - -0 - - -63 - - diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_errors.txt b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_errors.txt deleted file mode 100644 index e69de29..0000000 diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_notes.txt b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_notes.txt deleted file mode 100644 index b4c4fcb..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_notes.txt +++ /dev/null @@ -1,11 +0,0 @@ -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) -@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk1\.plol_cnt[19:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":778:3:778:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":680:3:680:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. -@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.edn -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. -@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_opt_report.xml b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_opt_report.xml deleted file mode 100644 index 2e79d15..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_opt_report.xml +++ /dev/null @@ -1,14 +0,0 @@ - - - - -2 / 0 - -/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_combined_clk.rpt -START OF CLOCK OPTIMIZATION REPORT - - - diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_runstatus.xml b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_runstatus.xml deleted file mode 100644 index f5531ea..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_runstatus.xml +++ /dev/null @@ -1,46 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.srr -Synopsys Lattice Technology Mapper - - -Completed - - - -11 - -/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_notes.txt - - - -3 - -/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_warnings.txt - - - -0 - -/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_errors.txt - - - -0h:00m:02s - - -0h:00m:02s - - -148MB - - -1556618991 - - - diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_timing_report.xml b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_timing_report.xml deleted file mode 100644 index 04932ce..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_timing_report.xml +++ /dev/null @@ -1,35 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.srr -START OF TIMING REPORT - - -Clock Name -Req Freq -Est Freq -Slack - - -PCSD|pll_refclki -100.0 MHz -168.9 MHz -4.079 - - -PCSD|rxrefclk -100.0 MHz -170.5 MHz -4.136 - - -System -100.0 MHz -18518.5 MHz -9.946 - - diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_warnings.txt b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_warnings.txt deleted file mode 100644 index 5df4948..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_warnings.txt +++ /dev/null @@ -1,3 +0,0 @@ -@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":118:4:118:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) -@W: MT420 |Found inferred clock PCSD|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" -@W: MT420 |Found inferred clock PCSD|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_errors.txt b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_errors.txt deleted file mode 100644 index e69de29..0000000 diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_notes.txt b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_notes.txt deleted file mode 100644 index eed8756..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_notes.txt +++ /dev/null @@ -1,2 +0,0 @@ -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_runstatus.xml b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_runstatus.xml deleted file mode 100644 index 3302c41..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_runstatus.xml +++ /dev/null @@ -1,46 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/PCSD_premap.srr -Synopsys Lattice Technology Pre-mapping - - -Completed - - - -2 - -/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_notes.txt - - - -2 - -/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_warnings.txt - - - -0 - -/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_errors.txt - - - -0h:00m:00s - - -0h:00m:00s - - -143MB - - -1556618988 - - - diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_warnings.txt b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_warnings.txt deleted file mode 100644 index 22d5ea5..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_warnings.txt +++ /dev/null @@ -1,2 +0,0 @@ -@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found inferred clock PCSD|pll_refclki which controls 33 sequential elements including rsl_inst.genblk1\.plol_cnt[19:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Found inferred clock PCSD|rxrefclk which controls 59 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/metrics.db b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/metrics.db deleted file mode 100644 index 3d974e4e3831441084f7ad4e1dd75d9e6311c32e..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 20480 zcmeI3O>Y}T7{_TOUB3l4lnYU+XOxZS<$3<|-(NO|nH@j=cE?wo zbt4(NirqG@8m4L7Wy~;)CR~@`8kGg8B-f~zqsl3tO{4PH3jzTPWT=}6ddg<>=_a1F;?QOHYtuJ=A zSvl=2-;CPNxTo0AmEOK9KV>0T()T9qp&JbNq&X12iYLuyQG3$xqA=uQN~6-YN1tC@EL1AyaaDWtg2+2)d65`$8T*kq*cqXJXSa7Yn75d0f^u_d5Y#4*PzYlb?M{uHg=M`q&%HG1&ori+ zxtHhgUl1)L0VIF~kN^@u0!RP}AOR$R1dsp{_!k13Z(F34C&jOA6)87pbz!LMGj5+3;luCbHC=k&lSmUK;C+kSf(f3?=u3TTh(~#~C zOdf>$_nItlmAB7h29FJc&4XyjI}O;7C_#2J%hsKzCTEGs`ro9#8}Ne#2_OL^fCP{L y5 -
    -
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
-@N: :  | Running in 64-bit mode 
-File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Apr 30 12:09:47 2019
-
-###########################################################]
-
-
     -
    -
-# Tue Apr 30 12:09:47 2019
-
-Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
-
-Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc
-Linked File: PCSD_scck.rpt
-Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt" file 
-@N:MF248 :  | Running in 64-bit mode. 
-@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
-
-ICG Latch Removal Summary:
-Number of ICG latches removed:	0
-Number of ICG latches not removed:	0
-syn_allowed_resources : blockrams=56  set on top level netlist PCSD
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-
-Clock Summary
-******************
-
-          Start                Requested     Requested     Clock        Clock                   Clock
-Level     Clock                Frequency     Period        Type         Group                   Load 
------------------------------------------------------------------------------------------------------
-0 -       System               100.0 MHz     10.000        system       system_clkgroup         0    
-                                                                                                     
-0 -       PCSD|rxrefclk        100.0 MHz     10.000        inferred     Inferred_clkgroup_1     59   
-                                                                                                     
-0 -       PCSD|pll_refclki     100.0 MHz     10.000        inferred     Inferred_clkgroup_0     33   
-=====================================================================================================
-
-@W:MT529 : PCSD_softlogic.v(412) | Found inferred clock PCSD|pll_refclki which controls 33 sequential elements including rsl_inst.genblk1\.plol_cnt[19:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
-@W:MT529 : PCSD_softlogic.v(567) | Found inferred clock PCSD|rxrefclk which controls 59 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
-
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-None
-None
-
-Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Apr 30 12:09:48 2019
-
-###########################################################]
-
-
     -
    -
-# Tue Apr 30 12:09:48 2019
-
-Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
-
-@N:MF248 :  | Running in 64-bit mode. 
-@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Available hyper_sources - for debug and ip models
-	None Found
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-@N:MO231 : PCSD_softlogic.v(412) | Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
-@N:MO231 : PCSD_softlogic.v(778) | Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
-@N:MO231 : PCSD_softlogic.v(680) | Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
-
-
-Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
-
-
-Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
-
-Pass		 CPU time		Worst Slack		Luts / Registers
-------------------------------------------------------------
-   1		0h:00m:00s		     5.36ns		  63 /        92
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
-
-@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
-
-
-
-@S |Clock Optimization Summary
-
-
-#### START OF CLOCK OPTIMIZATION REPORT #####[
-
-2 non-gated/non-generated clock tree(s) driving 92 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-=================================== Non-Gated/Non-Generated Clocks ====================================
-Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                
--------------------------------------------------------------------------------------------------------
-ClockId0001        rxrefclk            port                   59         rsl_inst.genblk2\.rlol1_cnt[18]
-ClockId0002        pll_refclki         port                   33         rsl_inst.genblk1\.pll_lol_p1   
-=======================================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######]
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 107MB peak: 144MB)
-
-Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)
-
-Writing EDIF Netlist and constraint files
-@N:FX1056 :  | Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.edn 
-M-2017.03L-SP1-1
-@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB)
-
-Writing Verilog Simulation files
-
-Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB)
-
-Writing VHDL Simulation files
-
-Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
-
-@W:MT246 : PCSD.vhd(118) | Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
-@W:MT420 :  | Found inferred clock PCSD|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" 
-@W:MT420 :  | Found inferred clock PCSD|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" 
-
-
-##### START OF TIMING REPORT #####[
-# Timing Report written on Tue Apr 30 12:09:50 2019
-#
-
-
-Top view:               PCSD
-Requested Frequency:    100.0 MHz
-Wire load mode:         top
-Paths requested:        5
-Constraint File(s):    /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc
-                       
-@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
-
-@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: 4.079
-
-@N:MT286 :  | System clock period 0.000 stretches to negative invalid value -- ignoring stretching. 
-                     Requested     Estimated       Requested     Estimated               Clock        Clock              
-Starting Clock       Frequency     Frequency       Period        Period        Slack     Type         Group              
--------------------------------------------------------------------------------------------------------------------------
-PCSD|pll_refclki     100.0 MHz     168.9 MHz       10.000        5.921         4.079     inferred     Inferred_clkgroup_0
-PCSD|rxrefclk        100.0 MHz     170.5 MHz       10.000        5.864         4.136     inferred     Inferred_clkgroup_1
-System               100.0 MHz     18518.5 MHz     10.000        0.054         9.946     system       system_clkgroup    
-=========================================================================================================================
-
-
-
-
-
-Clock Relationships
-*******************
-
-Clocks                              |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------------------------
-Starting          Ending            |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------------------------
-System            System            |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
-System            PCSD|rxrefclk     |  10.000      9.946   |  No paths    -      |  No paths    -      |  No paths    -    
-PCSD|pll_refclki  System            |  10.000      8.385   |  No paths    -      |  No paths    -      |  No paths    -    
-PCSD|pll_refclki  PCSD|pll_refclki  |  10.000      4.079   |  No paths    -      |  No paths    -      |  No paths    -    
-PCSD|rxrefclk     System            |  10.000      8.283   |  No paths    -      |  No paths    -      |  No paths    -    
-PCSD|rxrefclk     PCSD|rxrefclk     |  10.000      4.136   |  No paths    -      |  No paths    -      |  No paths    -    
-===========================================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
-       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information 
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: PCSD|pll_refclki
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                                   Starting                                                  Arrival          
-Instance                           Reference            Type        Pin     Net              Time        Slack
-                                   Clock                                                                      
---------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk1\.plol_cnt[1]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.079
-rsl_inst.genblk1\.plol_cnt[6]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.079
-rsl_inst.genblk1\.plol_cnt[7]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.079
-rsl_inst.genblk1\.plol_cnt[12]     PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[12]     0.907       4.079
-rsl_inst.genblk1\.plol_cnt[2]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.684
-rsl_inst.genblk1\.plol_cnt[3]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.684
-rsl_inst.genblk1\.plol_cnt[4]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
-rsl_inst.genblk1\.plol_cnt[5]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
-rsl_inst.genblk1\.plol_cnt[8]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
-rsl_inst.genblk1\.plol_cnt[9]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[9]      0.907       4.684
-==============================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                                   Starting                                                    Required          
-Instance                           Reference            Type        Pin     Net                Time         Slack
-                                   Clock                                                                         
------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk1\.plol_cnt[19]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
-rsl_inst.genblk1\.plol_cnt[17]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
-rsl_inst.genblk1\.plol_cnt[18]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
-rsl_inst.genblk1\.plol_cnt[15]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
-rsl_inst.genblk1\.plol_cnt[16]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
-rsl_inst.genblk1\.plol_cnt[13]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
-rsl_inst.genblk1\.plol_cnt[14]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
-rsl_inst.genblk1\.plol_cnt[11]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
-rsl_inst.genblk1\.plol_cnt[12]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
-rsl_inst.genblk1\.plol_cnt[9]      PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
-=================================================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      10.000
-    - Setup time:                            0.054
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         9.946
-
-    - Propagation time:                      5.867
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     4.079
-
-    Number of logic level(s):                15
-    Starting point:                          rsl_inst.genblk1\.plol_cnt[1] / Q
-    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
-    The start point is clocked by            PCSD|pll_refclki [rising] on pin CK
-    The end   point is clocked by            PCSD|pll_refclki [rising] on pin CK
-
-Instance / Net                                        Pin      Pin               Arrival     No. of    
-Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------
-rsl_inst.genblk1\.plol_cnt[1]            FD1S3DX      Q        Out     0.907     0.907       -         
-plol_cnt[1]                              Net          -        -       -         -           2         
-rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
-rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
-un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
-rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
-rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
-un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
-rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
-rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
-un1_plol_cnt_tc                          Net          -        -       -         -           5         
-rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
-rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
-plol_cnt                                 Net          -        -       -         -           21        
-rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
-rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
-plol_cnt_cry[0]                          Net          -        -       -         -           1         
-rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
-rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
-plol_cnt_cry[2]                          Net          -        -       -         -           1         
-rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
-rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
-plol_cnt_cry[4]                          Net          -        -       -         -           1         
-rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
-rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
-plol_cnt_cry[6]                          Net          -        -       -         -           1         
-rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
-rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
-plol_cnt_cry[8]                          Net          -        -       -         -           1         
-rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
-rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
-plol_cnt_cry[10]                         Net          -        -       -         -           1         
-rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
-rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
-plol_cnt_cry[12]                         Net          -        -       -         -           1         
-rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
-rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
-plol_cnt_cry[14]                         Net          -        -       -         -           1         
-rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
-rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
-plol_cnt_cry[16]                         Net          -        -       -         -           1         
-rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
-rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
-plol_cnt_cry[18]                         Net          -        -       -         -           1         
-rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
-rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
-plol_cnt_s[19]                           Net          -        -       -         -           1         
-rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
-=======================================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: PCSD|rxrefclk
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                                     Starting                                                 Arrival          
-Instance                             Reference         Type        Pin     Net                Time        Slack
-                                     Clock                                                                     
----------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.rlol1_cnt[14]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[14]      0.907       4.136
-rsl_inst.genblk2\.rlol1_cnt[15]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[15]      0.907       4.136
-rsl_inst.genblk2\.rlol1_cnt[16]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[16]      0.907       4.136
-rsl_inst.genblk2\.rlol1_cnt[17]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[17]      0.907       4.136
-rsl_inst.genblk2\.rlols0_cnt[10]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[10]     0.907       4.170
-rsl_inst.genblk2\.rlols0_cnt[14]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[14]     0.907       4.170
-rsl_inst.genblk2\.rlols0_cnt[16]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[16]     0.907       4.170
-rsl_inst.genblk2\.rlols0_cnt[17]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[17]     0.907       4.170
-rsl_inst.genblk2\.rlol1_cnt[0]       PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]       0.907       4.742
-rsl_inst.genblk2\.rlol1_cnt[1]       PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[1]       0.907       4.742
-===============================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                                     Starting                                                   Required          
-Instance                             Reference         Type        Pin     Net                  Time         Slack
-                                     Clock                                                                        
-------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.rlol1_cnt[17]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
-rsl_inst.genblk2\.rlol1_cnt[18]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
-rsl_inst.genblk2\.rlols0_cnt[17]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
-rsl_inst.genblk2\.rlol1_cnt[15]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
-rsl_inst.genblk2\.rlol1_cnt[16]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
-rsl_inst.genblk2\.rlols0_cnt[15]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[15]     9.946        4.231
-rsl_inst.genblk2\.rlols0_cnt[16]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[16]     9.946        4.231
-rsl_inst.genblk2\.rlol1_cnt[13]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[13]      9.946        4.258
-rsl_inst.genblk2\.rlol1_cnt[14]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[14]      9.946        4.258
-rsl_inst.genblk2\.rlols0_cnt[13]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[13]     9.946        4.292
-==================================================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      10.000
-    - Setup time:                            0.054
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         9.946
-
-    - Propagation time:                      5.809
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 4.136
-
-    Number of logic level(s):                14
-    Starting point:                          rsl_inst.genblk2\.rlol1_cnt[14] / Q
-    Ending point:                            rsl_inst.genblk2\.rlol1_cnt[18] / D
-    The start point is clocked by            PCSD|rxrefclk [rising] on pin CK
-    The end   point is clocked by            PCSD|rxrefclk [rising] on pin CK
-
-Instance / Net                                         Pin      Pin               Arrival     No. of    
-Name                                      Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.rlol1_cnt[14]           FD1P3DX      Q        Out     0.907     0.907       -         
-rlol1_cnt[14]                             Net          -        -       -         -           2         
-rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     A        In      0.000     0.907       -         
-rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     Z        Out     0.606     1.513       -         
-rlol1_cnt_tc_1_10                         Net          -        -       -         -           1         
-rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     D        In      0.000     1.513       -         
-rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     Z        Out     0.606     2.119       -         
-rlol1_cnt_tc_1_14                         Net          -        -       -         -           1         
-rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     D        In      0.000     2.119       -         
-rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     Z        Out     0.768     2.887       -         
-rlol1_cnt_tc_1                            Net          -        -       -         -           6         
-rsl_inst.genblk2\.rxs_rst_RNIS0OP         ORCALUT4     A        In      0.000     2.887       -         
-rsl_inst.genblk2\.rxs_rst_RNIS0OP         ORCALUT4     Z        Out     0.837     3.724       -         
-rlol1_cnt                                 Net          -        -       -         -           20        
-rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.724       -         
-rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.624       -         
-rlol1_cnt_cry[0]                          Net          -        -       -         -           1         
-rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.624       -         
-rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.685       -         
-rlol1_cnt_cry[2]                          Net          -        -       -         -           1         
-rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.685       -         
-rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.746       -         
-rlol1_cnt_cry[4]                          Net          -        -       -         -           1         
-rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.746       -         
-rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.807       -         
-rlol1_cnt_cry[6]                          Net          -        -       -         -           1         
-rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.807       -         
-rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.868       -         
-rlol1_cnt_cry[8]                          Net          -        -       -         -           1         
-rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.868       -         
-rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.929       -         
-rlol1_cnt_cry[10]                         Net          -        -       -         -           1         
-rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.929       -         
-rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.990       -         
-rlol1_cnt_cry[12]                         Net          -        -       -         -           1         
-rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.990       -         
-rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.051       -         
-rlol1_cnt_cry[14]                         Net          -        -       -         -           1         
-rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.051       -         
-rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.112       -         
-rlol1_cnt_cry[16]                         Net          -        -       -         -           1         
-rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.112       -         
-rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        S1       Out     0.698     5.809       -         
-rlol1_cnt_s[18]                           Net          -        -       -         -           1         
-rsl_inst.genblk2\.rlol1_cnt[18]           FD1P3DX      D        In      0.000     5.809       -         
-========================================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: System
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-              Starting                                                   Arrival           
-Instance      Reference     Type     Pin                Net              Time        Slack 
-              Clock                                                                        
--------------------------------------------------------------------------------------------
-DCU0_inst     System        DCUA     CH0_FFS_RLOL       rx_cdr_lol_s     0.000       9.946 
-DCU0_inst     System        DCUA     CH0_FFS_RLOS       rx_los_low_s     0.000       9.946 
-DCU0_inst     System        DCUA     CH0_FF_TX_PCLK     tx_pclk          0.000       10.000
-===========================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                              Starting                                                       Required           
-Instance                      Reference     Type        Pin                 Net              Time         Slack 
-                              Clock                                                                             
-----------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.rlol_p1     System        FD1S3DX     D                   rx_cdr_lol_s     9.946        9.946 
-rsl_inst.genblk2\.rlos_p1     System        FD1S3DX     D                   rx_los_low_s     9.946        9.946 
-DCU0_inst                     System        DCUA        CH0_FF_EBRD_CLK     tx_pclk          10.000       10.000
-DCU0_inst                     System        DCUA        CH0_FF_RXI_CLK      tx_pclk          10.000       10.000
-================================================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      10.000
-    - Setup time:                            0.054
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         9.946
-
-    - Propagation time:                      0.000
-    - Clock delay at starting point:         0.000 (ideal)
-    - Estimated clock delay at start point:  -0.000
-    = Slack (non-critical) :                 9.946
-
-    Number of logic level(s):                0
-    Starting point:                          DCU0_inst / CH0_FFS_RLOL
-    Ending point:                            rsl_inst.genblk2\.rlol_p1 / D
-    The start point is clocked by            System [rising]
-    The end   point is clocked by            PCSD|rxrefclk [rising] on pin CK
-
-Instance / Net                            Pin              Pin               Arrival     No. of    
-Name                          Type        Name             Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------
-DCU0_inst                     DCUA        CH0_FFS_RLOL     Out     0.000     0.000       -         
-rx_cdr_lol_s                  Net         -                -       -         -           2         
-rsl_inst.genblk2\.rlol_p1     FD1S3DX     D                In      0.000     0.000       -         
-===================================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-None
-
-Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
-
----------------------------------------
-Resource Usage Report
-Part: lfe5um_25f-6
-
-Register bits: 92 of 24288 (0%)
-PIC Latch:       0
-I/O cells:       0
-
-
-Details:
-CCU2C:          37
-DCUA:           1
-FD1P3BX:        4
-FD1P3DX:        42
-FD1S3BX:        10
-FD1S3DX:        36
-GSR:            1
-ORCALUT4:       63
-PFUMX:          2
-PUR:            1
-VHI:            2
-VLO:            2
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 32MB peak: 148MB)
-
-Process took 0h:00m:02s realtime, 0h:00m:02s cputime
-# Tue Apr 30 12:09:51 2019
-
-###########################################################]
-
-
     diff --git a/gbe/cores/sgmii/PCSD/syn_results/syntmp/PCSD_toc.htm b/gbe/cores/sgmii/PCSD/syn_results/syntmp/PCSD_toc.htm deleted file mode 100644 index 9a28325..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/syntmp/PCSD_toc.htm +++ /dev/null @@ -1,55 +0,0 @@ - - - - - - - - - - - - - - \ No newline at end of file diff --git a/gbe/cores/sgmii/PCSD/syn_results/syntmp/run_option.xml b/gbe/cores/sgmii/PCSD/syn_results/syntmp/run_option.xml deleted file mode 100644 index b616b1f..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/syntmp/run_option.xml +++ /dev/null @@ -1,24 +0,0 @@ - - - - - - - - - - - - - - - - - diff --git a/gbe/cores/sgmii/PCSD/syn_results/syntmp/statusReport.html b/gbe/cores/sgmii/PCSD/syn_results/syntmp/statusReport.html deleted file mode 100644 index b48fd55..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/syntmp/statusReport.html +++ /dev/null @@ -1,114 +0,0 @@ - - - Project Status Summary Page - - - - - - -
    - - - - - - - - - - -
    Project Settings
    Project Name PCSD Device Name syn_results: Lattice ECP5UM : LFE5UM_25F
    Implementation Name syn_results Top Module PCSD
    Pipelining 0 Retiming 0
    Resource Sharing 1 Fanout Guide 50
    Disable I/O Insertion 1 Disable Sequential Optimizations 0
    Clock Conversion 1 FSM Compiler 1

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    Run Status
    Job NameStatusCPU TimeReal TimeMemoryDate/Time
    (compiler)Complete10500-00m:02s-4/30/19
    12:09 PM
    (premap)Complete2200m:00s0m:00s143MB4/30/19
    12:09 PM
    (fpga_mapper)Complete11300m:02s0m:02s148MB4/30/19
    12:09 PM
    Multi-srs GeneratorComplete4/30/19
    12:09 PM
    -
    - - - - - - - - - - - - - - - - -
    Area Summary
    Register bits 92I/O cells 0
    Block RAMs -(v_ram) 0DSPs -(dsp_used) 0
    ORCA LUTs -(total_luts) 63

    - - - - - - - - - - -
    Timing Summary
    Clock NameReq FreqEst FreqSlack
    PCSD|pll_refclki100.0 MHz168.9 MHz4.079
    PCSD|rxrefclk100.0 MHz170.5 MHz4.136
    System100.0 MHz18518.5 MHz9.946
    -
    - - - - - - -
    Optimizations Summary
    Combined Clock Conversion 2 / 0

    -
    -
    - \ No newline at end of file diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/.cckTransfer b/gbe/cores/sgmii/PCSD/syn_results/synwork/.cckTransfer deleted file mode 100644 index 1106516a728bba57445e931c86cd822e9e0a3dda..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 457 zcmV;)0XF_0iwFP!0000015#C0RVXORFG)=2L*O z9v+2<{FA`hI0jmdB4H+Qmw|4bJ)6uuF#qJ=DF=uy;av6S>5M z4zY8HP9@#@r67~dOd3g|ArFk4Wzfi!$wS_|!_~XS5<*$>b3`ZR8C&q=!h|75HyIJ6 z2Qh;(W*1?h;7x_p#98L6uU}S`3gJNL`+EOC_fxf3m~LG{m?X`_7H?b!MRufJ zBA+qHwpT5lnrl@-Uou&72C)MszLY|*?TF>+d3?rku{@1!b*--d?G%)qf4Kwup&A>- z=Ra=`&F@Md+VV$Ps%4qco3K{RYs5=7)3a3^9;z?ZUjP6A|NjF3L@?kstpWf5oafvx diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_comp.fdep b/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_comp.fdep deleted file mode 100644 index 48777ad..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_comp.fdep +++ /dev/null @@ -1,35 +0,0 @@ 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b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer0.fdep deleted file mode 100644 index b533443..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/synwork/layer0.fdep +++ /dev/null @@ -1,32 +0,0 @@ -#defaultlanguage:vhdl -#OPTIONS:"|-mixedhdl|-top|PCSD|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work" -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610 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a/gbe/cores/sgmii/PCSD/syn_results/synwork/layer0.fdeporig b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer0.fdeporig deleted file mode 100644 index 41b0e30..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/synwork/layer0.fdeporig +++ /dev/null @@ -1,28 +0,0 @@ -#defaultlanguage:vhdl -#OPTIONS:"|-mixedhdl|-top|PCSD|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work" -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610 -#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610 -#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":1556618983 -0 "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd" vhdl - -# Dependency Lists (Uses list) -0 -1 - -# Dependency Lists (Users Of) -0 -1 - -# Design Unit to File Association -arch work pcsd v1 0 -module work pcsd 0 - -# Unbound Instances to File Association -inst work pcsd pcsdrsl_core 0 -inst work pcsd dcua 0 diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/layer0.srs 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zk=|W_ka@IqXTh{|yMx4L0pxRyxczp3TF!T%lf1hEX;1xWe_KZ3F75gKr#g|=-isz~ zU3bhNdi1L(=p0VFlaif(aNmpG}?9Et<&A zHvp@==C{yHzI|@XVO&6uExhM$J!URT@@ECJ(;N$bq~)l8V$s_yztg|_`k4}-ryla0 z8lT~qf7R%9xIj_h+=oUel7BhxoxidM7<$iV5XL{!BAMv-ecHk8a{Cu2Ose--+WFvD znQxH)Wot#eZX)UW3AG+JCO>6*nu=>b+i7_3`x**T@kVLC5O<8&XbnFYFmS z>SjHA&0sUeZD_%2dVhB4JV|BzaF)mV`LL!>%rnDtI#)nMjCob+Xr=}B0WnEE7QlW} zrdU&b3q}b9OS+OIIonM>{RX>830~e8c$K&3j6v9aPkCe>A+qO%)2ZksI24W!OwX7B zEmJi*sg6%%k-?_z;98maK<4EZ3EyGQKRH-kgYPwD?#6rXsj+KL{C{>AKDD)N-fjWz z0nEk)Ft36W2vMIC1E%%G)yL^~rq`czotpxA4ekU&+)6`Y4w)c~Eb2sx|Bundg80^1nc$;P~*%$sP&mzW`bz0>uCT diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/layer1.tlg b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer1.tlg deleted file mode 100644 index 52e3197..0000000 --- a/gbe/cores/sgmii/PCSD/syn_results/synwork/layer1.tlg +++ /dev/null @@ -1,96 +0,0 @@ -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":92:7:92:18|Synthesizing module PCSDrsl_core in library work. - - pnum_channels=32'b00000000000000000000000000000001 - pprotocol=24'b010001110100001001000101 - pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 - pport_tx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100 - pwait_tx_rdy=32'b00000000000000000000101110111000 - pport_rx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100 - pwait_rx_rdy=32'b00000000000000000000101110111000 - wa_num_cycles=32'b00000000000000000000010000000000 - dac_num_cycles=32'b00000000000000000000000000000011 - lreset_pwidth=32'b00000000000000000000000000000011 - lwait_b4_trst=32'b00000000000010111110101111000010 - lwait_b4_trst_s=32'b00000000000000000000001100001101 - lplol_cnt_width=32'b00000000000000000000000000010100 - lwait_after_plol0=32'b00000000000000000000000000000100 - lwait_b4_rrst=32'b00000000000000101100000000000000 - lrrst_wait_width=32'b00000000000000000000000000010100 - lwait_after_rrst=32'b00000000000011000011010100000000 - lwait_b4_rrst_s=32'b00000000000000000000000111001100 - lrlol_cnt_width=32'b00000000000000000000000000010011 - lwait_after_lols=32'b00000000000000001100010000000000 - lwait_after_lols_s=32'b00000000000000000000000010010110 - llols_cnt_width=32'b00000000000000000000000000010010 - lrdb_max=32'b00000000000000000000000000001111 - ltxr_wait_width=32'b00000000000000000000000000001100 - lrxr_wait_width=32'b00000000000000000000000000001100 - Generated name = PCSDrsl_core_Z1_layer1 -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":274:33:274:48|Removing wire dual_or_serd_rst, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":275:33:275:46|Removing wire tx_any_pcs_rst, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":276:33:276:42|Removing wire tx_any_rst, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":277:33:277:41|Object txsr_appd is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":278:33:278:42|Object txdpr_appd is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":279:33:279:41|Object txpr_appd is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":280:33:280:41|Object txr_wt_en is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":281:33:281:42|Object txr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":282:33:282:41|Removing wire txr_wt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":283:33:283:43|Object ruo_tx_rdyr is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":356:33:356:41|Object rxsr_appd is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":357:33:357:41|Object rxpr_appd is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":358:33:358:42|Object rxsdr_appd is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":359:33:359:42|Object rxdpr_appd is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":360:33:360:48|Removing wire rxsdr_or_sr_appd, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":361:33:361:49|Removing wire dual_or_rserd_rst, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":362:33:362:46|Removing wire rx_any_pcs_rst, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":363:33:363:42|Removing wire rx_any_rst, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":364:33:364:41|Object rxr_wt_en is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":365:33:365:42|Object rxr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":366:33:366:41|Removing wire rxr_wt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":367:33:367:43|Object ruo_rx_rdyr is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":507:10:507:10|Object m is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":880:10:880:10|Object l is declared but not assigned. Either assign a value or remove the declaration. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. 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b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_fpga_mapper.srr deleted file mode 100644 index 2b5185d..0000000 --- a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_fpga_mapper.srr +++ /dev/null @@ -1,265 +0,0 @@ -# Fri May 10 15:07:28 2019 - -Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. -Product Version M-2017.03L-SP1-1 - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) - -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) - - - -Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - -Available hyper_sources - for debug and ip models - None Found - - -Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - -Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - -Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - -Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - -Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - -Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - -Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------- - -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. - -Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - - - -@S |Clock Optimization Summary - - -#### START OF CLOCK OPTIMIZATION REPORT #####[ - -0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) -0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) -0 instances converted, 0 sequential instances remain driven by gated/generated clocks - - - -##### END OF CLOCK OPTIMIZATION REPORT ######] - - -Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB) - -Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_m.srm - -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) - -Writing EDIF Netlist and constraint files -@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.edn -M-2017.03L-SP1-1 -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF - -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) - -Writing Verilog Simulation files - -Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) - -Writing VHDL Simulation files - -Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) - - -Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB) - -@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":52:4:52:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) - - -##### START OF TIMING REPORT #####[ -# Timing Report written on Fri May 10 15:07:30 2019 -# - - -Top view: pll_in125_out125_out33 -Requested Frequency: 100.0 MHz -Wire load mode: top -Paths requested: 5 -Constraint File(s): /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc - -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. - -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. - - - -Performance Summary -******************* - - -Worst slack in design: 10.000 - -@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. - Requested Estimated Requested Estimated Clock Clock -Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------- -System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup -================================================================================================================ -Estimated period and frequency reported as NA means no slack depends directly on the clock waveform - - - - - -Clock Relationships -******************* - -Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------- -Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------- -System System | 10.000 10.000 | No paths - | No paths - | No paths - -========================================================================================================= - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - - -Interface Information -********************* - -No IO constraint found - - - -==================================== -Detailed Report for Clock: System -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------ -PLLInst_0 System EHXPLLL CLKINTFB CLKFB_t 0.000 10.000 -=================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------- -PLLInst_0 System EHXPLLL CLKFB CLKFB_t 10.000 10.000 -================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.000 - + Clock delay at ending point: 0.000 (ideal) - + Estimated clock delay at ending point: 0.000 - = Required time: 10.000 - - - Propagation time: 0.000 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (critical) : 10.000 - - Number of logic level(s): 0 - Starting point: PLLInst_0 / CLKINTFB - Ending point: PLLInst_0 / CLKFB - The start point is clocked by System [rising] - The end point is clocked by System [rising] - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------- -PLLInst_0 EHXPLLL CLKINTFB Out 0.000 0.000 - -CLKFB_t Net - - - - 1 -PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 - -==================================================================================== - - - -##### END OF TIMING REPORT #####] - -Timing exceptions that could not be applied -None - -Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB) - - -Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB) - 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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. -Product Version M-2017.03L-SP1-1 - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) - -Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc -@L: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt -Printing clock summary report in "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt" file -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB) - -ICG Latch Removal Summary: -Number of ICG latches removed: 0 -Number of ICG latches not removed: 0 -syn_allowed_resources : blockrams=56 set on top level netlist pll_in125_out125_out33 - -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - - -Clock Summary -****************** - - Start Requested Requested Clock Clock Clock -Level Clock Frequency Period Type Group Load -------------------------------------------------------------------------------------- -0 - System 100.0 MHz 10.000 system system_clkgroup 0 -===================================================================================== - -Finished Pre Mapping Phase. - -Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - - -Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - -None -None - -Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - -Pre-mapping successful! - -At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Fri May 10 15:07:28 2019 - -###########################################################] diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_premap.srr.db b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_premap.srr.db deleted file mode 100644 index e1a8837f299ed545acca0f4cd473ad0ec3834f52..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8192 zcmeI#F;Buk6bJBYV`L(@7$%YzCP;)tC5;J*5eZH>h-?f^X&>c;-jVh+I5*e z*5_;4c6pUIVJ`#(AOHafKmY;|fB*y_009U<;GYW^uT-toymi+^(F8lq_ zpf?`SxOY7q&~CRO6MBmBcpl{^w3KSGueL4wjfGS{npgHssZ7(&=6+=&Dj#-1KmY;| zfB*y_009U<00Izz00bcLSAiG5R4uP3$Nue25Cr|Dju#Yb^~8B0wIWt-&QIFZ=<6(t z>~LN$*o1mz+-YkjpTjgVoP_o$Oj&Whsbcq?f==spd?zz!TIKqIV?#5!?;BGmM~ra|UN1SJGZ>2U0AUiFKv19>LPC~HvJe$D?eZDEYA?B&JH zaQ*-Q0RR8QSZ#0IHWL24`W3xUK;nb7q$6dkQ<@^)p}2IgB<(4xeh3P|w2BxKZ{>pV zx(WK@ZzLzVyVeGJSEnIho1!Vsa9*ByMkh(4%DB)xzNkS39&M?)H6zzTtm2jl$3X^f zxd8t$C!DQmclc@ zR2r|_CZ$D{IWSSAxBrir4ce5kMv@)C>N48VOgH0^ZC4Js2-ZvCfk#lU9TR-ifi&>4 zEwq{Mv=qf^XqDhy$J*4y0hmO=vgob2!K<(KtM~2Aa)mbYZd_P+i~HsJ`xVI_EtZgF zI}DB8*puvH_r-c7?Xp2AWb&@BSd7ruEWAX~C84B#)U^$s$EO%@oL}l^;=R*_u_c zY=s(TA9jQ2LVh~!sj-y4l~OOw?cG1@>rT78&H}P91lz<^qXZsm1tqu9XbO>0^R0+0 z&K%j4d~XF;KE9@F@W4jx$+UOLO*u1k7bXVDruirp_v8^C#hrTiu8kIg5BWw4%oJ%0 z@|12J)Id7j`A*iM(oi-J9SdBrJLN%_mzhE5l&Sq<($_Q2@S$_;PW{@hbGchY^df^M zzUr~)`@HYTR*uVu(cvz+dDk^qy3Z05@kA}|(WRAP5HV-0q5ML1;wg44GM2f~wcw*? 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To preserve this instance, use the syn_noprune synthesis directive. - diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_area_report.xml b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_area_report.xml deleted file mode 100644 index c6fedcf..0000000 --- a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_area_report.xml +++ /dev/null @@ -1,26 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_resourceusage.rpt -Resource Usage - - -0 - - -0 - - -0 - - -0 - - -0 - - diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_errors.txt b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_errors.txt deleted file mode 100644 index e69de29..0000000 diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_notes.txt b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_notes.txt deleted file mode 100644 index ad96549..0000000 --- a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_notes.txt +++ /dev/null @@ -1,8 +0,0 @@ -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. -@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.edn -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. -@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_opt_report.xml b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_opt_report.xml deleted file mode 100644 index a39ddc1..0000000 --- a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_opt_report.xml +++ /dev/null @@ -1,14 +0,0 @@ - - - - -0 / 0 - -/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_combined_clk.rpt -START OF CLOCK OPTIMIZATION REPORT - - - diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_runstatus.xml b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_runstatus.xml deleted file mode 100644 index f7bd0c8..0000000 --- a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_runstatus.xml +++ /dev/null @@ -1,46 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_fpga_mapper.srr -Synopsys Lattice Technology Mapper - - -Completed - - - -8 - -/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_notes.txt - - - -1 - -/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_warnings.txt - - - -0 - -/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_errors.txt - - - -0h:00m:02s - - -0h:00m:02s - - -146MB - - -1557493650 - - - diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_timing_report.xml b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_timing_report.xml deleted file mode 100644 index b33a877..0000000 --- a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_timing_report.xml +++ /dev/null @@ -1,23 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_fpga_mapper.srr -START OF TIMING REPORT - - -Clock Name -Req Freq -Est Freq -Slack - - -System -100.0 MHz -NA -10.000 - - diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_warnings.txt b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_warnings.txt deleted file mode 100644 index 61d4bc9..0000000 --- a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_warnings.txt +++ /dev/null @@ -1 +0,0 @@ -@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":52:4:52:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_errors.txt b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_errors.txt deleted file mode 100644 index e69de29..0000000 diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_notes.txt b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_notes.txt deleted file mode 100644 index eed8756..0000000 --- a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_notes.txt +++ /dev/null @@ -1,2 +0,0 @@ -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_runstatus.xml b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_runstatus.xml deleted file mode 100644 index 503e067..0000000 --- a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_runstatus.xml +++ /dev/null @@ -1,46 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_premap.srr -Synopsys Lattice Technology Pre-mapping - - -Completed - - - -2 - -/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_notes.txt - - - -0 - -/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_warnings.txt - - - -0 - -/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_errors.txt - - - -0h:00m:00s - - -0h:00m:00s - - -143MB - - -1557493648 - - - diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_warnings.txt b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_warnings.txt deleted file mode 100644 index e69de29..0000000 diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/syntax_constraint_check.rpt.rptmap b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/syntax_constraint_check.rpt.rptmap deleted file mode 100644 index dd09adb..0000000 --- a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/syntax_constraint_check.rpt.rptmap +++ /dev/null @@ -1 +0,0 @@ -./pll_in125_out125_out33_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/.cckTransfer b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/.cckTransfer deleted file mode 100644 index 85a95944780910aa4adec3aeadb26065b2389336..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 457 zcmV;)0XF_0iwFP!0000015#C0RVXORFG)= zQit3HY2%P!ke96a_Ha+54HtQHL?5*kW)LoG5a~-&( zl#8U{mABMIZBnHnYb^$dC(_`v?x-Y|_kqy!e-0c1rXC>&$-`@xlx7(gV#}}G0EGwA zZlLHGW!I|~PtCcipm$DIoI&gbuFuG^Z6|zL-Ap%Fuhz$@tpB2^$jLMIYH zdgvsSP-R)!S!%U{2foO^$FX70>4`PidKE?s;G^$ZLQ1O$+x;Cmt=Bc+1) zC+YH~W|S2_empzFc<9U%Ts)N<+;g20BX2n}qF%Qp#7sajR}jv9V&&~t7EixdON?cFA|Gvu}>02;NGTb!wRfw5c@7wLOf3 z-KjP=UQ(0c$xtv+z`|?fH^YZnN;SwQ=$e?&2<^zR<%(sG+QFz}DGTA$C^(j+ zEZJADl&VuMpDhN;WKC&bf={f92#29qvgLA1Bzb)~W>gfUHolwfE59E<#2G8W>?YSyGZqhSFm;W^W!zgM zpL&Fds7r&VD0Ihd7gVp+x}`-(%QhdA6x`(-9{2iHkgH3$d|F#+fH!=6K7Qr5;nes* zfR=F!_^q~<(dFu2d6J{oAleooT(pTdnbcyUUPgP0G32i5fUJi`nm3WW%ZH)@di=?k z?RfH}C`~RivCC$Lq^0l|knG}UI2HKCc1}4`UaOdn2hyevHwCw*n~v23q9Z%~@j2VU zAV1##!2j-T?Hk|$MAeFi+xhqBxw&({FS1jNT2VIFYL$gR1_BldOP5pmMnjZ=y)`k4 z`B)ou#x8Sj^1aK|#CT{9bk*_beWpmD&ua0y)J^I(hXDrvS>Ewkb#mfP7xF;q%cWJd z^MZLn`1E8_UhbWh+qr;Yb*1f7eLx}-D#ubf8mL1%3EsWc<1-j9Bzr=V44M|bj~@jx zIkMwS>NWavbKcyp?Tj|c%VvHZ_W?tGt@P8@%!)2vL1h z;nrc(Z49KZ!rAG!OPexV5k_K`q2@6(fU)8wESjas+?C4y^ncidAC7; zaN+eiqaLWT+d})J*xLB-15w%Ot3eCamxVaTSa;Vl4tpPcsa*^b%`bSV>1?go{e{WX zVYmRu4)G^$?W~o<@N?gE$a_vN60Li8--==$zQn|S39#p9n%ZZ*XoR-!E!94 zL}f^MCoA@A&4zzF==Tkh{GQU@FfuhhGrpaPa2P*@2a5$;oYh!d_A_```rIvv#9nZ) zt^dXP9&2G#m1vIoLw?;$w2*O8lydQi(p6oqQRVWi!NWn)Q9J>L-v=)j!C^dIG#_gd zV5W3XkFQn1?demy8EzPq-I9l?Dt{6GxKnS?9(51=Tz(|2Oo#^-$IEMFE(ldPWdW<-wmpb<@lVIMVLlOP z`<4RVB~)su5BYPOuhT1^Opx2gXxuXzTQ0ZDlO3HP4{$0k=e%{hBNF(m+i0dyVlS4r z9{xea%X^I@hlqBLcsxrQS84l9EnHTrtyr3{h%Ti!id)e1_6;Ys znVQN*KZMi1GBP!-#^P_Q8{TCtNsY-(M@FY$}TziGDD_ADVm1+ zKyz(?*xV~FHD~-#im?3zzUL8gEIpT9&P6;+@z5nbeZUJ(v$yGYrJ2aqMY8Dt;czX{RyN$#R@T#w z4(H9M5#vlBmB_7_!gHzb#$;(r&3hhAs{1?0tomSQvt^8biaZNrswwk0DYASliH-Z4 zzf#yrfIYK!IDNZnnd8Imo=a`ABi@q z4OG0V;xKuPofX)t4T?0krfJVCVn0G1rD}CiN604a(RDwgXWt0;p4?$B7x6r9T{vT? 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zf4k#X>{imf`P*oj*{b)llTCdB=cwmL z5k0^9+w|lr3tpuCr9OUV$N%7Q-}CGkoU>K%WM@I|EMGo5M`-(2v}t*E!CB*Fy(EU;BbZ9GIf~|e22h;EE zFF()SL(m+hYrDPOId*Iaj+r|SYWrHNO|9pFJle(kddN=2YJ8NxZ{G9h|1*S~5oUVy zb(Ss`>%~6WF04Ou*urqTM0#Z};5jhAd1SRSQUNZX2*giuJ5#NH00030|Kf5`-~s>u Q0RR630OCx$t_Cdt00QcmaR2}S diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/layer0.tlg.rptmap b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/layer0.tlg.rptmap deleted file mode 100644 index 3910cac..0000000 --- a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/layer0.tlg.rptmap +++ /dev/null @@ -1 +0,0 @@ -./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages. diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/layer1.tlg.rptmap b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/layer1.tlg.rptmap deleted file mode 100644 index af92e0b..0000000 --- a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/layer1.tlg.rptmap +++ /dev/null @@ -1 +0,0 @@ -./synwork/layer1.tlg,layer1.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages. diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/linker.rpt.rptmap b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/linker.rpt.rptmap deleted file mode 100644 index 3793ead..0000000 --- a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/linker.rpt.rptmap +++ /dev/null @@ -1 +0,0 @@ -./synwork/sgmii_ecp5_comp.linkerlog,linker.rpt,Summary of linker messages for components that did not bind diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/metrics.db b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/metrics.db deleted file mode 100644 index f26fd6af62093a2882e7d380ad36bb0ae93eb77f..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 20480 zcmeI3&uL&#F;;$SB{+9Kcc<#*ngrI)aU)-AF27(OBDJ>UhmB8d*6BcdG_IX$4?$@3B_64 z3tUUFiuSdp>)I{GG);RA#~C=%HU*vjkv2W;eBk_AEB*b7fWZ{GrP1x|FXS)iU_$~( z00|%gB!C2v01`j~NB{|(KmrGsr>1kWv-)9PSxtv4;R@M_-_P86ys^Hs!FJYfZ*8z* zJXyTvHD7RBv7Qy!yH;?6xm*Rp9*%pK)8)fqR|*vlhcCS5aA13`%jJlc9|+e9UT(*d zP0w?`%b5CX-Lq*fb z?DQv@?7B@JFt5$--Q8kB`d!5$!&=TDMN0BNB;Kyq>VkjueeTKi^=}MP0=Ml9Oo+DN zt;Q#MvP8M1ZC)_Q0%$xRYD6KG-?#RW&<9HW`u{6>R-=E=H}n;4(iIqBLjp(u2_OL^ zfCP{L5u)mipWW{FnV_B&R?wS1ok z*9!*8N2UR{oY=NnU#YB?|7|;eC6b*T$SyCMQA%k&T zCT{#k$9^!Z6^I^}tof2jPnJ5C;;p5q$0ZN?qhu8oa2~EMz|(C?W;Zj!?lhpx^m@Ey z#`WglM%YhxHko57dzXhSv3X`1V_u69f2_OL^fCP{L55z1j%Dvv7tLy= KW}0$zC&NFq`p7*1 diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt deleted file mode 100644 index cf05fac..0000000 --- a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt +++ /dev/null @@ -1,16 +0,0 @@ -@N|Running in 64-bit mode -@N|Running in 64-bit mode -@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps -@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. -@N|Running in 64-bit mode -@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps -@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. -@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1. -@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. -@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work. -@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment. -@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment. -@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work. -@N: CL201 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state. -@N|Running in 64-bit mode - diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml deleted file mode 100644 index 797309b..0000000 --- a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml +++ /dev/null @@ -1,41 +0,0 @@ - - - - - - /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr - Synopsys HDL Compiler - - - Completed - - - - 15 - /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt - - - 76 - /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt - - - 0 - /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_errors.txt - - - - - - - 00h:00m:02s - - - - - - - 1557471731 - - - \ No newline at end of file diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt deleted file mode 100644 index d386b26..0000000 --- a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt +++ /dev/null @@ -1,77 +0,0 @@ -@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers. - diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml deleted file mode 100644 index 8733c9b..0000000 --- a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml +++ /dev/null @@ -1,26 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_resourceusage.rpt -Resource Usage - - -221 - - -0 - - -0 - - -0 - - -154 - - diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt deleted file mode 100644 index e69de29..0000000 diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt deleted file mode 100644 index d8e3e2c..0000000 --- a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt +++ /dev/null @@ -1,22 +0,0 @@ -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) -@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. -@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. -@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.edn -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml deleted file mode 100644 index c6da126..0000000 --- a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml +++ /dev/null @@ -1,14 +0,0 @@ - - - - -3 / 0 - -/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_combined_clk.rpt -START OF CLOCK OPTIMIZATION REPORT - - - diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml deleted file mode 100644 index 05527dc..0000000 --- a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml +++ /dev/null @@ -1,46 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr -Synopsys Lattice Technology Mapper - - -Completed - - - -22 - -/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt - - - -4 - -/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt - - - -0 - -/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt - - - -0h:00m:03s - - -0h:00m:03s - - -153MB - - -1557471736 - - - diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml deleted file mode 100644 index 8f866cb..0000000 --- a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml +++ /dev/null @@ -1,41 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr -START OF TIMING REPORT - - -Clock Name -Req Freq -Est Freq -Slack - - -sgmii_ecp5|pll_refclki -100.0 MHz -168.9 MHz -4.079 - - -sgmii_ecp5|rxrefclk -100.0 MHz -167.9 MHz -4.043 - - -sgmii_ecp5|tx_pclk_inferred_clock -100.0 MHz -237.5 MHz -5.789 - - -System -100.0 MHz -840.7 MHz -8.810 - - diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt deleted file mode 100644 index 6170ebf..0000000 --- a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt +++ /dev/null @@ -1,4 +0,0 @@ -@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) -@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" -@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" -@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt deleted file mode 100644 index e69de29..0000000 diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt deleted file mode 100644 index bd89dbb..0000000 --- a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt +++ /dev/null @@ -1,9 +0,0 @@ -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) -@N: BN362 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. -@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml deleted file mode 100644 index 3878c1e..0000000 --- a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml +++ /dev/null @@ -1,46 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr -Synopsys Lattice Technology Pre-mapping - - -Completed - - - -9 - -/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt - - - -3 - -/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt - - - -0 - -/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt - - - -0h:00m:00s - - -0h:00m:00s - - -144MB - - -1557471733 - - - diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt deleted file mode 100644 index 3044eef..0000000 --- a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt +++ /dev/null @@ -1,3 +0,0 @@ -@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr deleted file mode 100644 index 5d31417..0000000 --- a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr +++ /dev/null @@ -1,357 +0,0 @@ -Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. - -Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. - -Running on host :lxhadeb07 -@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps -@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. -VHDL syntax check successful! -File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling - -At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) - - -Process completed successfully. -# Fri May 10 09:02:09 2019 - -###########################################################] -Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. - -Running on host :lxhadeb07 -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) -@I::"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work) -Verilog syntax check successful! - -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) - - -Process completed successfully. -# Fri May 10 09:02:10 2019 - -###########################################################] -Running on host :lxhadeb07 -@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps -@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. -File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling -File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling -VHDL syntax check successful! -File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling -@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1. -Post processing for work.sgmii_ecp5.v1 - -At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) - - -Process completed successfully. -# Fri May 10 09:02:10 2019 - -###########################################################] -Running on host :lxhadeb07 -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) -@I::"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work) -Verilog syntax check successful! -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. - - PDATA_RST_VAL=32'b00000000000000000000000000000000 - Generated name = sync_0s -@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work. - - PPROTOCOL=24'b010001110100001001000101 - PLOL_SETTING=32'b00000000000000000000000000000000 - PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100 - PPCIE_MAX_RATE=24'b001100100010111000110101 - PDIFF_VAL_LOCK=32'b00000000000000000000000000100111 - PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110 - PPCLK_TC=32'b00000000000000100000000000000000 - PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000 - PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000 - PPCLK_DIV11_TC=32'b00000000000000000000000000000000 - LPLL_LOSS_ST=2'b00 - LPLL_PRELOSS_ST=2'b01 - LPLL_PRELOCK_ST=2'b10 - LPLL_LOCK_ST=2'b11 - LRCLK_TC=16'b1111111111111111 - LRCLK_TC_PUL_WIDTH=16'b0000000000110010 - LHB_WAIT_CNT=8'b11111111 - LPCLK_TC_0=32'b00000000000000001000000000000000 - LPCLK_TC_1=32'b00000000000000010000000000000000 - LPCLK_TC_2=32'b00000000000000100000000000000000 - LPCLK_TC_3=32'b00000000000000101000000000000000 - LPCLK_TC_4=32'b00000000000000010000000000000000 - LPDIFF_LOCK_00=32'b00000000000000000000000000001001 - LPDIFF_LOCK_10=32'b00000000000000000000000000010011 - LPDIFF_LOCK_20=32'b00000000000000000000000000100111 - LPDIFF_LOCK_30=32'b00000000000000000000000000110001 - LPDIFF_LOCK_40=32'b00000000000000000000000000010011 - LPDIFF_LOCK_01=32'b00000000000000000000000000001001 - LPDIFF_LOCK_11=32'b00000000000000000000000000010011 - LPDIFF_LOCK_21=32'b00000000000000000000000000100111 - LPDIFF_LOCK_31=32'b00000000000000000000000000110001 - LPDIFF_LOCK_41=32'b00000000000000000000000000010011 - LPDIFF_LOCK_02=32'b00000000000000000000000000110001 - LPDIFF_LOCK_12=32'b00000000000000000000000001100010 - LPDIFF_LOCK_22=32'b00000000000000000000000011000100 - LPDIFF_LOCK_32=32'b00000000000000000000000011110101 - LPDIFF_LOCK_42=32'b00000000000000000000000001100010 - LPDIFF_LOCK_03=32'b00000000000000000000000010000011 - LPDIFF_LOCK_13=32'b00000000000000000000000100000110 - LPDIFF_LOCK_23=32'b00000000000000000000001000001100 - LPDIFF_LOCK_33=32'b00000000000000000000001010001111 - LPDIFF_LOCK_43=32'b00000000000000000000000100000110 - LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011 - LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111 - LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110 - LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010 - LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111 - LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001 - LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011 - LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110 - LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111 - LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011 - LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000 - LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000 - LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000 - LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000 - LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000 - LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100 - LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001 - LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010 - LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111 - LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001 - Generated name = sgmii_ecp5sll_core_Z1_layer1 -@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment. -@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work. - - pnum_channels=32'b00000000000000000000000000000001 - pprotocol=24'b010001110100001001000101 - pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 - pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100 - pwait_tx_rdy=32'b00000000000000000000101110111000 - pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100 - pwait_rx_rdy=32'b00000000000000000000101110111000 - wa_num_cycles=32'b00000000000000000000010000000000 - dac_num_cycles=32'b00000000000000000000000000000011 - lreset_pwidth=32'b00000000000000000000000000000011 - lwait_b4_trst=32'b00000000000010111110101111000010 - lwait_b4_trst_s=32'b00000000000000000000001100001101 - lplol_cnt_width=32'b00000000000000000000000000010100 - lwait_after_plol0=32'b00000000000000000000000000000100 - lwait_b4_rrst=32'b00000000000000101100000000000000 - lrrst_wait_width=32'b00000000000000000000000000010100 - lwait_after_rrst=32'b00000000000011000011010100000000 - lwait_b4_rrst_s=32'b00000000000000000000000111001100 - lrlol_cnt_width=32'b00000000000000000000000000010011 - lwait_after_lols=32'b00000000000000001100010000000000 - lwait_after_lols_s=32'b00000000000000000000000010010110 - llols_cnt_width=32'b00000000000000000000000000010010 - lrdb_max=32'b00000000000000000000000000001111 - ltxr_wait_width=32'b00000000000000000000000000001100 - lrxr_wait_width=32'b00000000000000000000000000001100 - Generated name = sgmii_ecp5rsl_core_Z2_layer1 -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers. -@N: CL201 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state. -Extracted state machine for register sll_state -State machine has 4 reachable states with original encodings of: - 00 - 01 - 10 - 11 - -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB) - - -Process completed successfully. -# Fri May 10 09:02:10 2019 - -###########################################################] -Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer0.srs changed - recompiling -File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer1.srs changed - recompiling - -======================================================================================= -For a summary of linker messages for components that did not bind, please see log file: -@L: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog -======================================================================================= - - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Fri May 10 09:02:11 2019 - -###########################################################] -@END - -At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Fri May 10 09:02:11 2019 - -###########################################################] diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.db b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.db deleted file mode 100644 index a986936281551f5f31b97a5f3f9dab68cedc9ff9..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 28672 zcmeI5U2G#)6@cy7j`Qy>n`NQxwwI-}yEL`u*RkF1w!7Pqrb$S5leDa&Wi+-Y&LrcR z*_m;EmK1O#1VWXNc;SHuo{)IxGvXD2kPzab4-=oy zZmwXgWUk}i^PO|&-gEAqbFz4IPWLplYB_b)Lt^ZSSUetk4WU>pmV)0j{I+j#xRY%E z0WJRfuv;qj(#PK!g;&Kh-;Kdfbc-|)X&}--q=85Skp?0SL>h=R5NRONK%{|41OMk5 z@Z#z77cRt`FMDd)(CV7&sx{4Rw|zHmOLQB`K&rPBBqnGq5+Eks&n(9m-LpL`% zf3;rHd0;~~yIyR=J9X2$jD!4S<^k4yI`i+$KQbR>9t{6;_{pK{;PrvG)9d|TPklf6 z;bLyhs%ts5>gcMOtLa|ObIP(?$$47c zHdIf`*^afYRlJ;AtLwUdRJ4jMcimN7Yt=KXnqJ9nUM%sGVzI>ejl6r!Fp#6EU?VUq zQe9WCnRU(dT;y4(tb2%;khO|xnprkB&u#4zg@duj}_zPq)nMmg<kwnC6#WT(kTF(@GRFSnRAI7)BGeAIH4$(WTC{9 zR^GjZy;aQTXw`;URZXwU8P1xPr(uV6yq~&Qg~^gEfmpaL9#O1`6o_^6Ygk)iUZT+z zIGHa^mU!F<((dAp31)Tmdsty$`UZp!B>o_ghie!RA%MYk6QaJdqdGfi%W^jMwfIaD zi>pu+x0o+radE?Q4;OdGtn?IcFaZJ<=Rv^N^CB0DKC_!^)r%#O1F_)1=Yv8K^>j3t z-Q-)!+IzPTM0sHvi!v#+MZxi04x&F#uV^_qi|UqH&52o_Q?~O`&fPKXvg&F%P<{@+ zHs^X(|Lb`{Eb*WcXas(DQG*Wv143+u&qCKS8aP11fuHUAJ$~<92>Tz?*F*H){{|dV zG8~f6!69)L@6Dfuz&_K=^o?zf{%-X7k?%$Ee-!^yTkMG9|BzO8qWJ$b*X$_zol*RM ziiVBi|4`PQ^(g*7y$yvZ{tu-ONAds3cEO_f|2TVwQT%_xJ=iGzhn?r+Ez2 zHB3+ODk}p2=v(pX=NV%RZcc~8c#$#2;GT3ijGtqSF&K)5!nlSAW1X4vk?*yCcj7B# z)}CbzwU_&Ta@1#7Lk$kIohzSCj(UML)Zl0vChF6yp#}%tFj1dk4K+CShKO2wlAvxd zGXnRz2~cjQfkh_ z`ZytF=nC;(-tWn;5clK%4`P|8#|ooMBlhrnLq8e(#lZda$LaC@Tp7kQAH&^@{|O zoh>2?zJPj}F-8imfO?5B#^54ID5H-00%MF6ydCv<#uzC$JL(r0V+`Nd@vr~C8p|w? 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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. -Product Version M-2017.03L-SP1-1 - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) - -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) - - - -Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB) - - -Available hyper_sources - for debug and ip models - None Found - - -Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) - -Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) -original code -> new code - 00 -> 00 - 01 -> 01 - 10 -> 10 - 11 -> 11 -@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. -@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] - -Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) - - -Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB) - - -Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) - - -Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) - - -Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - -Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) - - -Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) - - -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - -Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 145MB) - -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). - -Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB) - -Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------- - 1 0h:00m:01s 4.90ns 155 / 221 -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). - -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB) - -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. - -Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB) - - - -@S |Clock Optimization Summary - - -#### START OF CLOCK OPTIMIZATION REPORT #####[ - -3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s) -0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) -0 instances converted, 0 sequential instances remain driven by gated/generated clocks - -============================================= Non-Gated/Non-Generated Clocks ============================================= -Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------------------------------------------- -@K:CKID0001 pll_refclki port 91 rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0] -@K:CKID0002 rxrefclk port 77 rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] -@K:CKID0003 DCU0_inst DCUA 53 sll_inst.pcount[21] -========================================================================================================================== - - -##### END OF CLOCK OPTIMIZATION REPORT ######] - - -Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 149MB) - -Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm - -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 149MB) - -Writing EDIF Netlist and constraint files -@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.edn -M-2017.03L-SP1-1 -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF - -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB) - -Writing Verilog Simulation files - -Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 152MB) - -Writing VHDL Simulation files - -Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) - - -Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) - -@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) -@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" -@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" -@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" - - -##### START OF TIMING REPORT #####[ -# Timing Report written on Fri May 10 09:02:16 2019 -# - - -Top view: sgmii_ecp5 -Requested Frequency: 100.0 MHz -Wire load mode: top -Paths requested: 5 -Constraint File(s): /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc - -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. - -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. - - - -Performance Summary -******************* - - -Worst slack in design: 4.043 - - Requested Estimated Requested Estimated Clock Clock -Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------------- -sgmii_ecp5|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0 -sgmii_ecp5|rxrefclk 100.0 MHz 167.9 MHz 10.000 5.957 4.043 inferred Inferred_clkgroup_1 -sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 237.5 MHz 10.000 4.211 5.789 inferred Inferred_clkgroup_2 -System 100.0 MHz 840.7 MHz 10.000 1.190 8.810 system system_clkgroup -======================================================================================================================================== - - - - - -Clock Relationships -******************* - -Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------- -Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------- -System sgmii_ecp5|rxrefclk | 10.000 8.811 | No paths - | No paths - | No paths - -sgmii_ecp5|pll_refclki System | 10.000 8.253 | No paths - | No paths - | No paths - -sgmii_ecp5|pll_refclki sgmii_ecp5|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths - -sgmii_ecp5|pll_refclki sgmii_ecp5|tx_pclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - -sgmii_ecp5|rxrefclk System | 10.000 8.277 | No paths - | No paths - | No paths - -sgmii_ecp5|rxrefclk sgmii_ecp5|rxrefclk | 10.000 4.043 | No paths - | No paths - | No paths - -sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|pll_refclki | Diff grp - | No paths - | No paths - | No paths - -sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|tx_pclk_inferred_clock | 10.000 5.789 | No paths - | No paths - | No paths - -============================================================================================================================================================ - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - - -Interface Information -********************* - -No IO constraint found - - - -==================================== -Detailed Report for Clock: sgmii_ecp5|pll_refclki -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock --------------------------------------------------------------------------------------------------------------------- -rsl_inst.genblk1\.plol_cnt[2] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.079 -rsl_inst.genblk1\.plol_cnt[3] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.079 -rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[17] 0.907 4.079 -rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[19] 0.907 4.079 -rsl_inst.genblk1\.plol_cnt[1] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.684 -rsl_inst.genblk1\.plol_cnt[4] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684 -rsl_inst.genblk1\.plol_cnt[5] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684 -rsl_inst.genblk1\.plol_cnt[6] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.684 -rsl_inst.genblk1\.plol_cnt[7] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.684 -rsl_inst.genblk1\.plol_cnt[8] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684 -==================================================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------------ -rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079 -rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139 -rsl_inst.genblk1\.plol_cnt[18] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139 -rsl_inst.genblk1\.plol_cnt[15] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200 -rsl_inst.genblk1\.plol_cnt[16] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200 -rsl_inst.genblk1\.plol_cnt[13] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261 -rsl_inst.genblk1\.plol_cnt[14] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261 -rsl_inst.genblk1\.plol_cnt[11] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322 -rsl_inst.genblk1\.plol_cnt[12] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322 -rsl_inst.genblk1\.plol_cnt[9] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383 -======================================================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.054 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 9.946 - - - Propagation time: 5.867 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.079 - - Number of logic level(s): 15 - Starting point: rsl_inst.genblk1\.plol_cnt[2] / Q - Ending point: rsl_inst.genblk1\.plol_cnt[19] / D - The start point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK - The end point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------- -rsl_inst.genblk1\.plol_cnt[2] FD1S3DX Q Out 0.907 0.907 - -plol_cnt[2] Net - - - - 2 -rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 - -rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 - -un1_plol_cnt_tc_10 Net - - - - 1 -rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 - -rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 - -un1_plol_cnt_tc_14 Net - - - - 1 -rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 - -rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 - -un1_plol_cnt_tc Net - - - - 5 -rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 - -rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 - -plol_cnt Net - - - - 21 -rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 - -rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 - -plol_cnt_cry[0] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 - -rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 - -plol_cnt_cry[2] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 - -rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 - -plol_cnt_cry[4] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 - -rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 - -plol_cnt_cry[6] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 - -rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 - -plol_cnt_cry[8] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 - -rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 - -plol_cnt_cry[10] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 - -rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 - -plol_cnt_cry[12] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 - -rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 - -plol_cnt_cry[14] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 - -rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 - -plol_cnt_cry[16] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 - -rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 - -plol_cnt_cry[18] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 - -rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 - -plol_cnt_s[19] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 - -======================================================================================================= - - - - -==================================== -Detailed Report for Clock: sgmii_ecp5|rxrefclk -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock -------------------------------------------------------------------------------------------------------------------- -rsl_inst.genblk2\.rxs_rst sgmii_ecp5|rxrefclk FD1P3DX Q rxs_rst 1.015 4.043 -rsl_inst.genblk2\.rlol1_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[7] 0.907 4.136 -rsl_inst.genblk2\.rlol1_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[8] 0.907 4.136 -rsl_inst.genblk2\.rlol1_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[9] 0.907 4.136 -rsl_inst.genblk2\.rlol1_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[10] 0.907 4.136 -rsl_inst.genblk2\.rlols0_cnt[1] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[1] 0.907 4.170 -rsl_inst.genblk2\.rlols0_cnt[2] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[2] 0.907 4.170 -rsl_inst.genblk2\.rlols0_cnt[3] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[3] 0.907 4.170 -rsl_inst.genblk2\.rlols0_cnt[4] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[4] 0.907 4.170 -rsl_inst.genblk2\.rlol1_cnt[0] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742 -=================================================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------------------------------------- -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[11] 9.946 4.043 -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[9] 9.946 4.104 -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[10] 9.946 4.104 -rsl_inst.genblk2\.rlol1_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136 -rsl_inst.genblk2\.rlol1_cnt[18] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136 -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[7] 9.946 4.165 -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[8] 9.946 4.165 -rsl_inst.genblk2\.rlols0_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170 -rsl_inst.genblk2\.rlol1_cnt[15] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197 -rsl_inst.genblk2\.rlol1_cnt[16] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197 -================================================================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.054 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 9.946 - - - Propagation time: 5.902 - - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : 4.043 - - Number of logic level(s): 11 - Starting point: rsl_inst.genblk2\.rxs_rst / Q - Ending point: rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] / D - The start point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK - The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------ -rsl_inst.genblk2\.rxs_rst FD1P3DX Q Out 1.015 1.015 - -rxs_rst Net - - - - 6 -rsl_inst.rdo_rx_serdes_rst_c_1[0] ORCALUT4 B In 0.000 1.015 - -rsl_inst.rdo_rx_serdes_rst_c_1[0] ORCALUT4 Z Out 0.708 1.723 - -rsl_rx_serdes_rst_c Net - - - - 3 -rsl_inst.dual_or_rserd_rst ORCALUT4 A In 0.000 1.723 - -rsl_inst.dual_or_rserd_rst ORCALUT4 Z Out 0.798 2.521 - -dual_or_rserd_rst Net - - - - 9 -rsl_inst.rx_any_rst ORCALUT4 A In 0.000 2.521 - -rsl_inst.rx_any_rst ORCALUT4 Z Out 0.660 3.181 - -rx_any_rst Net - - - - 2 -rsl_inst.rx_any_rst_RNIFD021 ORCALUT4 A In 0.000 3.181 - -rsl_inst.rx_any_rst_RNIFD021 ORCALUT4 Z Out 0.819 4.000 - -rxr_wt_cnt9 Net - - - - 14 -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0] CCU2C A1 In 0.000 4.000 - -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0] CCU2C COUT Out 0.900 4.900 - -rxr_wt_cnt_cry[0] Net - - - - 1 -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1] CCU2C CIN In 0.000 4.900 - -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1] CCU2C COUT Out 0.061 4.961 - -rxr_wt_cnt_cry[2] Net - - - - 1 -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3] CCU2C CIN In 0.000 4.961 - -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3] CCU2C COUT Out 0.061 5.022 - -rxr_wt_cnt_cry[4] Net - - - - 1 -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5] CCU2C CIN In 0.000 5.022 - -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5] CCU2C COUT Out 0.061 5.083 - -rxr_wt_cnt_cry[6] Net - - - - 1 -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7] CCU2C CIN In 0.000 5.083 - -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7] CCU2C COUT Out 0.061 5.144 - -rxr_wt_cnt_cry[8] Net - - - - 1 -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9] CCU2C CIN In 0.000 5.144 - -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9] CCU2C COUT Out 0.061 5.205 - -rxr_wt_cnt_cry[10] Net - - - - 1 -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11] CCU2C CIN In 0.000 5.205 - -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11] CCU2C S0 Out 0.698 5.902 - -rxr_wt_cnt_s[11] Net - - - - 1 -rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] FD1P3DX D In 0.000 5.902 - -================================================================================================================= - - - - -==================================== -Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------------- -sll_inst.ppul_sync_p1 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p1 1.098 5.789 -sll_inst.ppul_sync_p2 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p2 1.098 5.789 -sll_inst.pcount_diff[0] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_0 0.985 6.147 -sll_inst.pcount[0] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[0] 0.955 6.178 -sll_inst.pcount_diff[1] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_1 0.955 6.239 -sll_inst.pcount_diff[2] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_2 0.955 6.239 -sll_inst.pcount[1] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[1] 0.907 6.287 -sll_inst.pcount[2] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[2] 0.907 6.287 -sll_inst.pcount_diff[3] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_3 0.955 6.300 -sll_inst.pcount_diff[4] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_4 0.955 6.300 -======================================================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------------------------------ -sll_inst.pcount[21] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[21] 9.946 5.789 -sll_inst.pcount[19] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[19] 9.946 5.850 -sll_inst.pcount[20] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[20] 9.946 5.850 -sll_inst.pcount[17] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[17] 9.946 5.911 -sll_inst.pcount[18] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[18] 9.946 5.911 -sll_inst.pcount[15] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[15] 9.946 5.972 -sll_inst.pcount[16] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[16] 9.946 5.972 -sll_inst.pcount[13] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[13] 9.946 6.033 -sll_inst.pcount[14] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[14] 9.946 6.033 -sll_inst.pcount_diff[21] sgmii_ecp5|tx_pclk_inferred_clock FD1P3DX D un1_pcount_diff_1_s_21_0_S0 9.946 6.034 -========================================================================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.054 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 9.946 - - - Propagation time: 4.157 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 5.789 - - Number of logic level(s): 13 - Starting point: sll_inst.ppul_sync_p1 / Q - Ending point: sll_inst.pcount[21] / D - The start point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK - The end point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- -sll_inst.ppul_sync_p1 FD1S3DX Q Out 1.098 1.098 - -ppul_sync_p1 Net - - - - 25 -sll_inst.pcount10_0_o3 ORCALUT4 A In 0.000 1.098 - -sll_inst.pcount10_0_o3 ORCALUT4 Z Out 0.851 1.950 - -N_8 Net - - - - 25 -sll_inst.pcount_cry_0[0] CCU2C A1 In 0.000 1.950 - -sll_inst.pcount_cry_0[0] CCU2C COUT Out 0.900 2.850 - -pcount_cry[0] Net - - - - 1 -sll_inst.pcount_cry_0[1] CCU2C CIN In 0.000 2.850 - -sll_inst.pcount_cry_0[1] CCU2C COUT Out 0.061 2.911 - -pcount_cry[2] Net - - - - 1 -sll_inst.pcount_cry_0[3] CCU2C CIN In 0.000 2.911 - -sll_inst.pcount_cry_0[3] CCU2C COUT Out 0.061 2.972 - -pcount_cry[4] Net - - - - 1 -sll_inst.pcount_cry_0[5] CCU2C CIN In 0.000 2.972 - -sll_inst.pcount_cry_0[5] CCU2C COUT Out 0.061 3.033 - -pcount_cry[6] Net - - - - 1 -sll_inst.pcount_cry_0[7] CCU2C CIN In 0.000 3.033 - -sll_inst.pcount_cry_0[7] CCU2C COUT Out 0.061 3.094 - -pcount_cry[8] Net - - - - 1 -sll_inst.pcount_cry_0[9] CCU2C CIN In 0.000 3.094 - -sll_inst.pcount_cry_0[9] CCU2C COUT Out 0.061 3.155 - -pcount_cry[10] Net - - - - 1 -sll_inst.pcount_cry_0[11] CCU2C CIN In 0.000 3.155 - -sll_inst.pcount_cry_0[11] CCU2C COUT Out 0.061 3.216 - -pcount_cry[12] Net - - - - 1 -sll_inst.pcount_cry_0[13] CCU2C CIN In 0.000 3.216 - -sll_inst.pcount_cry_0[13] CCU2C COUT Out 0.061 3.277 - -pcount_cry[14] Net - - - - 1 -sll_inst.pcount_cry_0[15] CCU2C CIN In 0.000 3.277 - -sll_inst.pcount_cry_0[15] CCU2C COUT Out 0.061 3.338 - -pcount_cry[16] Net - - - - 1 -sll_inst.pcount_cry_0[17] CCU2C CIN In 0.000 3.338 - -sll_inst.pcount_cry_0[17] CCU2C COUT Out 0.061 3.399 - -pcount_cry[18] Net - - - - 1 -sll_inst.pcount_cry_0[19] CCU2C CIN In 0.000 3.399 - -sll_inst.pcount_cry_0[19] CCU2C COUT Out 0.061 3.460 - -pcount_cry[20] Net - - - - 1 -sll_inst.pcount_s_0[21] CCU2C CIN In 0.000 3.460 - -sll_inst.pcount_s_0[21] CCU2C S0 Out 0.698 4.157 - -pcount_s[21] Net - - - - 1 -sll_inst.pcount[21] FD1S3DX D In 0.000 4.157 - -============================================================================================ - - - - -==================================== -Detailed Report for Clock: System -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ----------------------------------------------------------------------------------------- -DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 8.810 -DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 8.810 -======================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------------------------------------------------- -rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX SP un2_rdo_serdes_rst_dual_c_2_i 9.806 8.810 -rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX D rxpr_appd_RNO[0] 9.946 9.556 -rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946 -rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946 -============================================================================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.194 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 9.806 - - - Propagation time: 0.996 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (non-critical) : 8.810 - - Number of logic level(s): 2 - Starting point: DCU0_inst / CH0_FFS_RLOL - Ending point: rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP - The start point is clocked by System [rising] - The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------ -DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 - -rx_cdr_lol_s Net - - - - 4 -rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 A In 0.000 0.000 - -rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 Z Out 0.606 0.606 - -un2_rdo_serdes_rst_dual_c_1_1 Net - - - - 1 -rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 B In 0.000 0.606 - -rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 Z Out 0.390 0.996 - -un2_rdo_serdes_rst_dual_c_2_i Net - - - - 1 -rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] FD1P3DX SP In 0.000 0.996 - -=================================================================================================================================== - - - -##### END OF TIMING REPORT #####] - -Timing exceptions that could not be applied -None - -Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) - - -Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) - ---------------------------------------- -Resource Usage Report -Part: lfe5um_25f-6 - -Register bits: 221 of 24288 (1%) -PIC Latch: 0 -I/O cells: 0 - - -Details: -CCU2C: 113 -DCUA: 1 -FD1P3BX: 20 -FD1P3DX: 92 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-CKID0001:@|S:pll_refclki@|E:rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001 -CKID0002:@|S:rxrefclk@|E:rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]@|F:@syn_sample_clock_path==CKID0002@|M:ClockId0002 -CKID0003:@|S:DCU0_inst@|E:sll_inst.pcount[21]@|F:@syn_sample_clock_path==CKID0003@|M:ClockId0003 diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr deleted file mode 100644 index 8337c2b..0000000 --- a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr +++ /dev/null @@ -1,12 +0,0 @@ -Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs changed - recompiling - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Fri May 10 09:02:12 2019 - -###########################################################] diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr.db b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr.db deleted file mode 100644 index 029fa7a6cf9014af50ee9d4aa843536a1f7b5c42..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8192 zcmeI#JqyA>3DEQgKL*xDXO@ z%d=&(imfwzIG4G0Jf%J073BwWN1`{~f``Krs^Nta{J wY>_tId!-qqw)j}S$WL3iQGJ`s(T{)t1Rwwb2tWV=5P$##AOHafK;VZ3UKAiP82|tP diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr deleted file mode 100644 index 0a65ebd..0000000 --- a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr +++ /dev/null @@ -1,86 +0,0 @@ -# Fri May 10 09:02:12 2019 - -Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. -Product Version M-2017.03L-SP1-1 - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) - -Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc -@L: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt -Printing clock summary report in "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB) - -@N: BN362 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. -ICG Latch Removal Summary: -Number of ICG latches removed: 0 -Number of ICG latches not removed: 0 -syn_allowed_resources : blockrams=56 set on top level netlist sgmii_ecp5 - -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) - - - -Clock Summary -****************** - - Start Requested Requested Clock Clock Clock -Level Clock Frequency Period Type Group Load ----------------------------------------------------------------------------------------------------------------------- -0 - System 100.0 MHz 10.000 system system_clkgroup 0 - -0 - sgmii_ecp5|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 93 - -0 - sgmii_ecp5|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 77 - -0 - sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 53 -====================================================================================================================== - -@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. - -Finished Pre Mapping Phase. - -Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) - -Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) -original code -> new code - 00 -> 00 - 01 -> 01 - 10 -> 10 - 11 -> 11 -@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. - -Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) - -None -None - -Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) - -Pre-mapping successful! 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z4FZy*xQX0$ZMRabUkHrre~Udg>^Jr=_ICca{LlFU`<*7xKmY_l00ck)1V8`;KmY_l z00jOYfuAgk?b@t(n)76&9qEdwDMLLxj;}?#GF4{&Fn;qKiRXPf>F?3&=y4kNMMv|# z9H&0aT5OA?pH4}S7vDj5oYP#+#c!&MXJ)SJkhkXWw*Wn|FkdcN=kYpkD{mkqZ@u72 z>g}$OLd7C{7^IaD(RWlw-=-TpnbA*{=HK8FEiXf6KOwU#IXC{76T-aOlns929}cW3UD*xs6Zqqor9qssoK&DI{~Jh$6aLOY(Mr(w7|FnJKZy?3Ac zj&@H(#Obl&w0RH?M0%^&-Yds^SD>@>D36*+y9;a_l5q5}W` diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt deleted file mode 100644 index ae389c2..0000000 --- a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt +++ /dev/null @@ -1,16 +0,0 @@ -@N|Running in 64-bit mode -@N|Running in 64-bit mode -@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps -@N:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. -@N|Running in 64-bit mode -@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps -@N:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. -@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1. -@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. -@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work. -@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment. -@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment. -@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work. -@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state. -@N|Running in 64-bit mode - diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml deleted file mode 100644 index ca7d50b..0000000 --- a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml +++ /dev/null @@ -1,41 +0,0 @@ - - - - - - /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr - Synopsys HDL Compiler - - - Completed - - - - 15 - /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt - - - 77 - /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt - - - 0 - /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_errors.txt - - - - - - - 00h:00m:02s - - - - - - - 1557482336 - - - \ No newline at end of file diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt deleted file mode 100644 index 0eac89c..0000000 --- a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt +++ /dev/null @@ -1,78 +0,0 @@ -@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 17 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_unlock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 4 to 3 of genblk5.rdiff_comp_lock[4:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[2]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[16]. Make sure that there are no unused intermediate registers. - diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml deleted file mode 100644 index 58aa421..0000000 --- a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml +++ /dev/null @@ -1,26 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_resourceusage.rpt -Resource Usage - - -221 - - -0 - - -0 - - -0 - - -153 - - diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt deleted file mode 100644 index e69de29..0000000 diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt deleted file mode 100644 index 89ed59a..0000000 --- a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt +++ /dev/null @@ -1,22 +0,0 @@ -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) -@N: MO225 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. -@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.edn -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml deleted file mode 100644 index 37c27e7..0000000 --- a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml +++ /dev/null @@ -1,14 +0,0 @@ - - - - -3 / 0 - -/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_combined_clk.rpt -START OF CLOCK OPTIMIZATION REPORT - - - diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml deleted file mode 100644 index aa1f7f0..0000000 --- a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml +++ /dev/null @@ -1,46 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr -Synopsys Lattice Technology Mapper - - -Completed - - - -22 - -/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt - - - -4 - -/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt - - - -0 - -/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt - - - -0h:00m:03s - - -0h:00m:03s - - -153MB - - -1557482342 - - - diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml deleted file mode 100644 index 354cbb6..0000000 --- a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml +++ /dev/null @@ -1,41 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr -START OF TIMING REPORT - - -Clock Name -Req Freq -Est Freq -Slack - - -sgmii_ecp5|pll_refclki -100.0 MHz -168.9 MHz -4.079 - - -sgmii_ecp5|rxrefclk -100.0 MHz -170.5 MHz -4.136 - - -sgmii_ecp5|tx_pclk_inferred_clock -100.0 MHz -237.5 MHz -5.789 - - -System -100.0 MHz -840.7 MHz -8.810 - - diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt deleted file mode 100644 index d44b509..0000000 --- a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt +++ /dev/null @@ -1,4 +0,0 @@ -@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) -@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" -@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" -@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt deleted file mode 100644 index e69de29..0000000 diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt deleted file mode 100644 index a540d08..0000000 --- a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt +++ /dev/null @@ -1,9 +0,0 @@ -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) -@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. -@N: MO225 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml deleted file mode 100644 index 127251d..0000000 --- a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml +++ /dev/null @@ -1,46 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr -Synopsys Lattice Technology Pre-mapping - - -Completed - - - -9 - -/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt - - - -3 - -/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt - - - -0 - -/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt - - - -0h:00m:00s - - -0h:00m:00s - - -144MB - - -1557482338 - - - diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt deleted file mode 100644 index 47b05ba..0000000 --- a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt +++ /dev/null @@ -1,3 +0,0 @@ -@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr deleted file mode 100644 index 77a0cae..0000000 --- a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr +++ /dev/null @@ -1,352 +0,0 @@ -Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. - -Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. - -Running on host :lxhadeb07 -@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps -@N:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. -VHDL syntax check successful! - -At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) - - -Process completed successfully. -# Fri May 10 11:58:55 2019 - -###########################################################] -Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. - -Running on host :lxhadeb07 -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) -@I::"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work) -Verilog syntax check successful! - -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) - - -Process completed successfully. -# Fri May 10 11:58:55 2019 - -###########################################################] -Running on host :lxhadeb07 -@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps -@N:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5. -VHDL syntax check successful! -@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1. -Post processing for work.sgmii_ecp5.v1 - -At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) - - -Process completed successfully. -# Fri May 10 11:58:55 2019 - -###########################################################] -Running on host :lxhadeb07 -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) -@I::"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work) -Verilog syntax check successful! -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. - - PDATA_RST_VAL=32'b00000000000000000000000000000000 - Generated name = sync_0s -@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work. - - PPROTOCOL=24'b010001110100001001000101 - PLOL_SETTING=32'b00000000000000000000000000000000 - PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100 - PPCIE_MAX_RATE=24'b001100100010111000110101 - PDIFF_VAL_LOCK=32'b00000000000000000000000000010011 - PDIFF_VAL_UNLOCK=32'b00000000000000000000000000100111 - PPCLK_TC=32'b00000000000000010000000000000000 - PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000 - PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000 - PPCLK_DIV11_TC=32'b00000000000000000000000000000000 - LPLL_LOSS_ST=2'b00 - LPLL_PRELOSS_ST=2'b01 - LPLL_PRELOCK_ST=2'b10 - LPLL_LOCK_ST=2'b11 - LRCLK_TC=16'b1111111111111111 - LRCLK_TC_PUL_WIDTH=16'b0000000000110010 - LHB_WAIT_CNT=8'b11111111 - LPCLK_TC_0=32'b00000000000000001000000000000000 - LPCLK_TC_1=32'b00000000000000010000000000000000 - LPCLK_TC_2=32'b00000000000000100000000000000000 - LPCLK_TC_3=32'b00000000000000101000000000000000 - LPCLK_TC_4=32'b00000000000000010000000000000000 - LPDIFF_LOCK_00=32'b00000000000000000000000000001001 - LPDIFF_LOCK_10=32'b00000000000000000000000000010011 - LPDIFF_LOCK_20=32'b00000000000000000000000000100111 - LPDIFF_LOCK_30=32'b00000000000000000000000000110001 - LPDIFF_LOCK_40=32'b00000000000000000000000000010011 - LPDIFF_LOCK_01=32'b00000000000000000000000000001001 - LPDIFF_LOCK_11=32'b00000000000000000000000000010011 - LPDIFF_LOCK_21=32'b00000000000000000000000000100111 - LPDIFF_LOCK_31=32'b00000000000000000000000000110001 - LPDIFF_LOCK_41=32'b00000000000000000000000000010011 - LPDIFF_LOCK_02=32'b00000000000000000000000000110001 - LPDIFF_LOCK_12=32'b00000000000000000000000001100010 - LPDIFF_LOCK_22=32'b00000000000000000000000011000100 - LPDIFF_LOCK_32=32'b00000000000000000000000011110101 - LPDIFF_LOCK_42=32'b00000000000000000000000001100010 - LPDIFF_LOCK_03=32'b00000000000000000000000010000011 - LPDIFF_LOCK_13=32'b00000000000000000000000100000110 - LPDIFF_LOCK_23=32'b00000000000000000000001000001100 - LPDIFF_LOCK_33=32'b00000000000000000000001010001111 - LPDIFF_LOCK_43=32'b00000000000000000000000100000110 - LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011 - LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111 - LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110 - LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010 - LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111 - LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001 - LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011 - LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110 - LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111 - LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011 - LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000 - LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000 - LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000 - LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000 - LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000 - LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100 - LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001 - LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010 - LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111 - LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001 - Generated name = sgmii_ecp5sll_core_Z1_layer1 -@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment. -@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 17 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work. - - pnum_channels=32'b00000000000000000000000000000001 - pprotocol=24'b010001110100001001000101 - pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 - pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100 - pwait_tx_rdy=32'b00000000000000000000101110111000 - pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100 - pwait_rx_rdy=32'b00000000000000000000101110111000 - wa_num_cycles=32'b00000000000000000000010000000000 - dac_num_cycles=32'b00000000000000000000000000000011 - lreset_pwidth=32'b00000000000000000000000000000011 - lwait_b4_trst=32'b00000000000010111110101111000010 - lwait_b4_trst_s=32'b00000000000000000000001100001101 - lplol_cnt_width=32'b00000000000000000000000000010100 - lwait_after_plol0=32'b00000000000000000000000000000100 - lwait_b4_rrst=32'b00000000000000101100000000000000 - lrrst_wait_width=32'b00000000000000000000000000010100 - lwait_after_rrst=32'b00000000000011000011010100000000 - lwait_b4_rrst_s=32'b00000000000000000000000111001100 - lrlol_cnt_width=32'b00000000000000000000000000010011 - lwait_after_lols=32'b00000000000000001100010000000000 - lwait_after_lols_s=32'b00000000000000000000000010010110 - llols_cnt_width=32'b00000000000000000000000000010010 - lrdb_max=32'b00000000000000000000000000001111 - ltxr_wait_width=32'b00000000000000000000000000001100 - lrxr_wait_width=32'b00000000000000000000000000001100 - Generated name = sgmii_ecp5rsl_core_Z2_layer1 -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_unlock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 4 to 3 of genblk5.rdiff_comp_lock[4:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[2]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[16]. Make sure that there are no unused intermediate registers. -@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state. -Extracted state machine for register sll_state -State machine has 4 reachable states with original encodings of: - 00 - 01 - 10 - 11 - -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB) - - -Process completed successfully. -# Fri May 10 11:58:56 2019 - -###########################################################] -Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode - -======================================================================================= -For a summary of linker messages for components that did not bind, please see log file: -@L: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog -======================================================================================= - - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Fri May 10 11:58:56 2019 - -###########################################################] -@END - -At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Fri May 10 11:58:56 2019 - -###########################################################] diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.db b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.db deleted file mode 100644 index d028ab57b460c029f040b39c37ad880998e9090a..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 32768 zcmeHQON<*y8MepcdCxe{4Vw@sl3n(}#O`i)du%6xon$9rc4x?L9%Q8}IQ!gNtN~N;!HwJ(0BMnc6+y6jG z{(sPsO`Un~8`E%AI`_>KJdz_}AYmY3AYmY3AYmY3AYmY3AYmY3AYmY3;QyR~AU%5Q z70)z*|*(y%1o_HMIa2T+jIu z*5P&R2Wov4ySiWS>y}}tSa+4Kr>gI)1*TIs^!( z_=GI5gY3*u$PQ=SSA`+sX)Y0$86uwI67d{E#FJbiE-^$r!6jmbR){msC1Qp~h&DzM zUn70BSgNoyHH(TsOifZKyRUc+V)&tk-SELK>==r=>lv!$)Kq<4^@BWG);2Km8y-f% zI!wz2>lmJD@Mk;i4}0CvBe(g@_1dXwQ2^oKB$lG0QK~v@<~PNV zxS#&(jUf=|naf0=IjJoW@fQo=V+Mwf3(&?a$F3EMc~MZeOLD>AvE5b8#|2PC0e-gN z2et6$MX6X7ffy(xarYXAF92nN??>9G@0bnZ020U2^=V6hp9i;}{m+BrK6(RABbVTm zmEkme8cvzRWN!X2IQF?_ZfM4x{_XUUsjbPk6aPQ)|Cxn6691ojcW7@>9&|DTU(h{XSou~sMke|)oPiU0qo^N@-EpZNcS@&9{;AAUsq{{!hvDmOiI za{A2F`N`#pTjSQ)8>8PI`EK^D;h$uFGxW#w-{FD}@6oKEromv9vx&Q?ccwcHJ5U3C zMG_xlrPN)j9K3AmTp+CSir^9i`utX2PjKgK8E zUJGaX2YixGz|oGmvmUH}z#rukaI}Ap5wLZF0^Z=Pm+rM>rf&sX$GODYD`3_?-Y2=l z+iST@|9C&bCEi|(W%|c^j7z-Cj4bO3F7YxmIjo~x;$>!WxJM{n?pC1ps?hzfKqvnH z!IYKCJux#oePQagNqgd}<8O}raP(IrZ)g9J9Ugu%lOMX6ehn_^|7fnulwXar@m`D$ z_^~*k>qS1HM#uViph|o~jSlniKo$9f8towBfhzC`H5yQe2Wo*&sL^pf9;kUfp+<-F zc%Yu)6KXVk5D(N@KA}bf2eCk{e~LooEm+UMf~Y^wB~k_kMEyA~kutC!>d$hCG#Vg? zr=32-B~k{4QvH)$B4uDF)t}}PDFZX9{uGx;d;UMhEV=K1NJsW&J8Jn{Yn z8ox01_0jK-{B>kDduh0q`QFga(|>}CK1@eby#y-0*<`*2Oew*Jlqxxwdu{*=lM6_B z&vbm%EylC~OkLm-p&1`S{31n2jX{>%_{u^FbV$zo(BZbL>UJQlNU%;LCQY8ZNV}tP zh?~KVwDu;Y_%mY^m14CB4=ChPXS3Xv0sGEsTA-<>iH1+MC3X^L zknK%I(7h8;y+FmkLc|w~#TXZTMH71zVH+Y9U#iN*-7BjkIY_tM2t=)6-GrT#kd>nm zfZXlPiMWXSI%47bJN^FDez4^;^25gnT#WvJ?Ht9s3Y_=&0dD@D442VyE=BB(r? zr&&i4%}`42#ey_QO4|7PqTDCE>+k{}?qALJyeX*yd> zkzW}Ua)lW3lAt^Qd4uX4GSU+FOx4-x{PyQ)uaIS5+vO0sTvf#T)%Fm%kG&dZ4t{HS zP->?UDM^5c)P0*efDg7+_G-U-WC@VpynCLionc70Q~|YD$+;8y?jA5v*PIkgU~K!u z)oaDRA8Cl}F+yr~I7p)VkC8`S9tpygwv<)s19B0+EpB5Tq< zX?eW0rFmzO(sGbABC*15UWE|SrsYbQ3Ovk^*vb@6(u{`=1*t17Qf?6gLPNS^`vJ+K zDCE&~2W?>Nw(LprvW{UU#&yk|@H$Te8x%o)I@N`IbJ*L&=fMPljC0fg4L{IrFx>g< zfC%VnE)OPvPN1zw10mq@Ug&Ml?jksJvF2?GfO2?GfO2?GfO z2?GfO2?GfO2?GfO2?P6JpecSHmUOI;B^_}8I+5ADlUNoY2OQjI019RIy0=5`G2kG) j9e5h7c!e+z+!MrtTiO{mrqfA#0b6nx3Ho;Xwh{jWXc+k{ diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.rptmap b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.rptmap deleted file mode 100644 index 14937c8..0000000 --- a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.rptmap +++ /dev/null @@ -1 +0,0 @@ -./synlog/sgmii_ecp5_compiler.srr,sgmii_ecp5_compiler.srr,Compile Log diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr deleted file mode 100644 index bc02d12..0000000 --- a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr +++ /dev/null @@ -1,682 +0,0 @@ -# Fri May 10 11:58:58 2019 - -Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35 -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. -Product Version M-2017.03L-SP1-1 - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) - -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) - - - -Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB) - - -Available hyper_sources - for debug and ip models - None Found - - -Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) - -Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) -original code -> new code - 00 -> 00 - 01 -> 01 - 10 -> 10 - 11 -> 11 -@N: MO225 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] - -Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) - - -Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB) - - -Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) - - -Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) - - -Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - -Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) - - -Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) - - -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - -Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 145MB) - -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). - -Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB) - -Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------- - 1 0h:00m:01s 5.36ns 154 / 221 -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)). - -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB) - -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. - -Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB) - - - -@S |Clock Optimization Summary - - -#### START OF CLOCK OPTIMIZATION REPORT #####[ - -3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s) -0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) -0 instances converted, 0 sequential instances remain driven by gated/generated clocks - -============================================= Non-Gated/Non-Generated Clocks ============================================= -Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------------------------------------------- -@K:CKID0001 pll_refclki port 91 rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0] -@K:CKID0002 rxrefclk port 77 rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] -@K:CKID0003 DCU0_inst DCUA 53 sll_inst.pcount[21] -========================================================================================================================== - - -##### END OF CLOCK OPTIMIZATION REPORT ######] - - -Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 148MB) - -Writing Analyst data base /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm - -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB) - -Writing EDIF Netlist and constraint files -@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.edn -M-2017.03L-SP1-1 -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF - -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB) - -Writing Verilog Simulation files - -Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB) - -Writing VHDL Simulation files - -Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) - - -Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) - -@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) -@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" -@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" -@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" - - -##### START OF TIMING REPORT #####[ -# Timing Report written on Fri May 10 11:59:02 2019 -# - - -Top view: sgmii_ecp5 -Requested Frequency: 100.0 MHz -Wire load mode: top -Paths requested: 5 -Constraint File(s): /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc - -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. - -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. - - - -Performance Summary -******************* - - -Worst slack in design: 4.079 - - Requested Estimated Requested Estimated Clock Clock -Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------------- -sgmii_ecp5|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0 -sgmii_ecp5|rxrefclk 100.0 MHz 170.5 MHz 10.000 5.864 4.136 inferred Inferred_clkgroup_1 -sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 237.5 MHz 10.000 4.211 5.789 inferred Inferred_clkgroup_2 -System 100.0 MHz 840.7 MHz 10.000 1.190 8.810 system system_clkgroup -======================================================================================================================================== - - - - - -Clock Relationships -******************* - -Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------- -Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------- -System sgmii_ecp5|rxrefclk | 10.000 8.811 | No paths - | No paths - | No paths - -sgmii_ecp5|pll_refclki System | 10.000 8.253 | No paths - | No paths - | No paths - -sgmii_ecp5|pll_refclki sgmii_ecp5|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths - -sgmii_ecp5|pll_refclki sgmii_ecp5|tx_pclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - -sgmii_ecp5|rxrefclk System | 10.000 8.184 | No paths - | No paths - | No paths - -sgmii_ecp5|rxrefclk sgmii_ecp5|rxrefclk | 10.000 4.136 | No paths - | No paths - | No paths - -sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|pll_refclki | Diff grp - | No paths - | No paths - | No paths - -sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|tx_pclk_inferred_clock | 10.000 5.789 | No paths - | No paths - | No paths - -============================================================================================================================================================ - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - - -Interface Information -********************* - -No IO constraint found - - - -==================================== -Detailed Report for Clock: sgmii_ecp5|pll_refclki -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock --------------------------------------------------------------------------------------------------------------------- -rsl_inst.genblk1\.plol_cnt[2] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.079 -rsl_inst.genblk1\.plol_cnt[3] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.079 -rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[17] 0.907 4.079 -rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[19] 0.907 4.079 -rsl_inst.genblk1\.plol_cnt[1] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.684 -rsl_inst.genblk1\.plol_cnt[4] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684 -rsl_inst.genblk1\.plol_cnt[5] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684 -rsl_inst.genblk1\.plol_cnt[6] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.684 -rsl_inst.genblk1\.plol_cnt[7] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.684 -rsl_inst.genblk1\.plol_cnt[8] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684 -==================================================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------------ -rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079 -rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139 -rsl_inst.genblk1\.plol_cnt[18] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139 -rsl_inst.genblk1\.plol_cnt[15] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200 -rsl_inst.genblk1\.plol_cnt[16] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200 -rsl_inst.genblk1\.plol_cnt[13] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261 -rsl_inst.genblk1\.plol_cnt[14] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261 -rsl_inst.genblk1\.plol_cnt[11] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322 -rsl_inst.genblk1\.plol_cnt[12] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322 -rsl_inst.genblk1\.plol_cnt[9] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383 -======================================================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.054 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 9.946 - - - Propagation time: 5.867 - - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : 4.079 - - Number of logic level(s): 15 - Starting point: rsl_inst.genblk1\.plol_cnt[2] / Q - Ending point: rsl_inst.genblk1\.plol_cnt[19] / D - The start point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK - The end point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------- -rsl_inst.genblk1\.plol_cnt[2] FD1S3DX Q Out 0.907 0.907 - -plol_cnt[2] Net - - - - 2 -rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 - -rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 - -un1_plol_cnt_tc_10 Net - - - - 1 -rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 - -rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 - -un1_plol_cnt_tc_14 Net - - - - 1 -rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 - -rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 - -un1_plol_cnt_tc Net - - - - 5 -rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 - -rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 - -plol_cnt Net - - - - 21 -rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 - -rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 - -plol_cnt_cry[0] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 - -rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 - -plol_cnt_cry[2] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 - -rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 - -plol_cnt_cry[4] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 - -rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 - -plol_cnt_cry[6] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 - -rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 - -plol_cnt_cry[8] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 - -rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 - -plol_cnt_cry[10] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 - -rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 - -plol_cnt_cry[12] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 - -rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 - -plol_cnt_cry[14] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 - -rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 - -plol_cnt_cry[16] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 - -rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 - -plol_cnt_cry[18] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 - -rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 - -plol_cnt_s[19] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 - -======================================================================================================= - - - - -==================================== -Detailed Report for Clock: sgmii_ecp5|rxrefclk -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock -------------------------------------------------------------------------------------------------------------------- -rsl_inst.genblk2\.rlol1_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[7] 0.907 4.136 -rsl_inst.genblk2\.rlol1_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[8] 0.907 4.136 -rsl_inst.genblk2\.rlol1_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[9] 0.907 4.136 -rsl_inst.genblk2\.rlol1_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[10] 0.907 4.136 -rsl_inst.genblk2\.rlols0_cnt[1] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[1] 0.907 4.170 -rsl_inst.genblk2\.rlols0_cnt[2] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[2] 0.907 4.170 -rsl_inst.genblk2\.rlols0_cnt[3] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[3] 0.907 4.170 -rsl_inst.genblk2\.rlols0_cnt[4] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[4] 0.907 4.170 -rsl_inst.genblk2\.rxs_rst sgmii_ecp5|rxrefclk FD1P3DX Q rxs_rst 1.015 4.700 -rsl_inst.genblk2\.rlol1_cnt[0] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742 -=================================================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------------- -rsl_inst.genblk2\.rlol1_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136 -rsl_inst.genblk2\.rlol1_cnt[18] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136 -rsl_inst.genblk2\.rlols0_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170 -rsl_inst.genblk2\.rlol1_cnt[15] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197 -rsl_inst.genblk2\.rlol1_cnt[16] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197 -rsl_inst.genblk2\.rlols0_cnt[15] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[15] 9.946 4.231 -rsl_inst.genblk2\.rlols0_cnt[16] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[16] 9.946 4.231 -rsl_inst.genblk2\.rlol1_cnt[13] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[13] 9.946 4.258 -rsl_inst.genblk2\.rlol1_cnt[14] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[14] 9.946 4.258 -rsl_inst.genblk2\.rlols0_cnt[13] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[13] 9.946 4.292 -======================================================================================================================== - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.054 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 9.946 - - - Propagation time: 5.809 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.136 - - Number of logic level(s): 14 - Starting point: rsl_inst.genblk2\.rlol1_cnt[7] / Q - Ending point: rsl_inst.genblk2\.rlol1_cnt[18] / D - The start point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK - The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------- -rsl_inst.genblk2\.rlol1_cnt[7] FD1P3DX Q Out 0.907 0.907 - -rlol1_cnt[7] Net - - - - 2 -rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 A In 0.000 0.907 - -rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 Z Out 0.606 1.513 - -rlol1_cnt_tc_1_10 Net - - - - 1 -rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 D In 0.000 1.513 - -rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 Z Out 0.606 2.119 - -rlol1_cnt_tc_1_14 Net - - - - 1 -rsl_inst.rlol1_cnt_tc_1 ORCALUT4 D In 0.000 2.119 - -rsl_inst.rlol1_cnt_tc_1 ORCALUT4 Z Out 0.768 2.887 - -rlol1_cnt_tc_1 Net - - - - 6 -rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 A In 0.000 2.887 - -rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 Z Out 0.837 3.724 - -rlol1_cnt Net - - - - 20 -rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C A1 In 0.000 3.724 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C COUT Out 0.900 4.624 - -rlol1_cnt_cry[0] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C CIN In 0.000 4.624 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C COUT Out 0.061 4.685 - -rlol1_cnt_cry[2] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C CIN In 0.000 4.685 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C COUT Out 0.061 4.746 - -rlol1_cnt_cry[4] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C CIN In 0.000 4.746 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C COUT Out 0.061 4.807 - -rlol1_cnt_cry[6] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C CIN In 0.000 4.807 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C COUT Out 0.061 4.868 - -rlol1_cnt_cry[8] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C CIN In 0.000 4.868 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C COUT Out 0.061 4.929 - -rlol1_cnt_cry[10] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C CIN In 0.000 4.929 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C COUT Out 0.061 4.990 - -rlol1_cnt_cry[12] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C CIN In 0.000 4.990 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C COUT Out 0.061 5.051 - -rlol1_cnt_cry[14] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C CIN In 0.000 5.051 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C COUT Out 0.061 5.112 - -rlol1_cnt_cry[16] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C CIN In 0.000 5.112 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C S1 Out 0.698 5.809 - -rlol1_cnt_s[18] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt[18] FD1P3DX D In 0.000 5.809 - -======================================================================================================== - - - - -==================================== -Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------------- -sll_inst.ppul_sync_p1 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p1 1.098 5.789 -sll_inst.ppul_sync_p2 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p2 1.098 5.789 -sll_inst.pcount_diff[0] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_0 0.985 6.147 -sll_inst.pcount[0] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[0] 0.955 6.178 -sll_inst.pcount_diff[1] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_1 0.955 6.239 -sll_inst.pcount_diff[2] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_2 0.955 6.239 -sll_inst.pcount[1] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[1] 0.907 6.287 -sll_inst.pcount[2] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[2] 0.907 6.287 -sll_inst.pcount_diff[3] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_3 0.955 6.300 -sll_inst.pcount_diff[4] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_4 0.955 6.300 -======================================================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------------------------------ -sll_inst.pcount[21] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[21] 9.946 5.789 -sll_inst.pcount[19] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[19] 9.946 5.850 -sll_inst.pcount[20] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[20] 9.946 5.850 -sll_inst.pcount[17] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[17] 9.946 5.911 -sll_inst.pcount[18] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[18] 9.946 5.911 -sll_inst.pcount[15] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[15] 9.946 5.972 -sll_inst.pcount[16] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[16] 9.946 5.972 -sll_inst.pcount[13] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[13] 9.946 6.033 -sll_inst.pcount[14] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[14] 9.946 6.033 -sll_inst.pcount_diff[21] sgmii_ecp5|tx_pclk_inferred_clock FD1P3DX D un1_pcount_diff_1_s_21_0_S0 9.946 6.034 -========================================================================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.054 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 9.946 - - - Propagation time: 4.157 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 5.789 - - Number of logic level(s): 13 - Starting point: sll_inst.ppul_sync_p1 / Q - Ending point: sll_inst.pcount[21] / D - The start point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK - The end point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- -sll_inst.ppul_sync_p1 FD1S3DX Q Out 1.098 1.098 - -ppul_sync_p1 Net - - - - 25 -sll_inst.pcount10_0_o3 ORCALUT4 A In 0.000 1.098 - -sll_inst.pcount10_0_o3 ORCALUT4 Z Out 0.851 1.950 - -N_8 Net - - - - 25 -sll_inst.pcount_cry_0[0] CCU2C A1 In 0.000 1.950 - -sll_inst.pcount_cry_0[0] CCU2C COUT Out 0.900 2.850 - -pcount_cry[0] Net - - - - 1 -sll_inst.pcount_cry_0[1] CCU2C CIN In 0.000 2.850 - -sll_inst.pcount_cry_0[1] CCU2C COUT Out 0.061 2.911 - -pcount_cry[2] Net - - - - 1 -sll_inst.pcount_cry_0[3] CCU2C CIN In 0.000 2.911 - -sll_inst.pcount_cry_0[3] CCU2C COUT Out 0.061 2.972 - -pcount_cry[4] Net - - - - 1 -sll_inst.pcount_cry_0[5] CCU2C CIN In 0.000 2.972 - -sll_inst.pcount_cry_0[5] CCU2C COUT Out 0.061 3.033 - -pcount_cry[6] Net - - - - 1 -sll_inst.pcount_cry_0[7] CCU2C CIN In 0.000 3.033 - -sll_inst.pcount_cry_0[7] CCU2C COUT Out 0.061 3.094 - -pcount_cry[8] Net - - - - 1 -sll_inst.pcount_cry_0[9] CCU2C CIN In 0.000 3.094 - -sll_inst.pcount_cry_0[9] CCU2C COUT Out 0.061 3.155 - -pcount_cry[10] Net - - - - 1 -sll_inst.pcount_cry_0[11] CCU2C CIN In 0.000 3.155 - -sll_inst.pcount_cry_0[11] CCU2C COUT Out 0.061 3.216 - -pcount_cry[12] Net - - - - 1 -sll_inst.pcount_cry_0[13] CCU2C CIN In 0.000 3.216 - -sll_inst.pcount_cry_0[13] CCU2C COUT Out 0.061 3.277 - -pcount_cry[14] Net - - - - 1 -sll_inst.pcount_cry_0[15] CCU2C CIN In 0.000 3.277 - -sll_inst.pcount_cry_0[15] CCU2C COUT Out 0.061 3.338 - -pcount_cry[16] Net - - - - 1 -sll_inst.pcount_cry_0[17] CCU2C CIN In 0.000 3.338 - -sll_inst.pcount_cry_0[17] CCU2C COUT Out 0.061 3.399 - -pcount_cry[18] Net - - - - 1 -sll_inst.pcount_cry_0[19] CCU2C CIN In 0.000 3.399 - -sll_inst.pcount_cry_0[19] CCU2C COUT Out 0.061 3.460 - -pcount_cry[20] Net - - - - 1 -sll_inst.pcount_s_0[21] CCU2C CIN In 0.000 3.460 - -sll_inst.pcount_s_0[21] CCU2C S0 Out 0.698 4.157 - -pcount_s[21] Net - - - - 1 -sll_inst.pcount[21] FD1S3DX D In 0.000 4.157 - -============================================================================================ - - - - -==================================== -Detailed Report for Clock: System -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ----------------------------------------------------------------------------------------- -DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 8.810 -DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 8.810 -======================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------------------------------------------------- -rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX SP un2_rdo_serdes_rst_dual_c_2_i 9.806 8.810 -rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX D rxpr_appd_RNO[0] 9.946 9.556 -rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946 -rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946 -============================================================================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.194 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 9.806 - - - Propagation time: 0.996 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (non-critical) : 8.810 - - Number of logic level(s): 2 - Starting point: DCU0_inst / CH0_FFS_RLOL - Ending point: rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP - The start point is clocked by System [rising] - The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------ -DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 - -rx_cdr_lol_s Net - - - - 4 -rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 A In 0.000 0.000 - -rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 Z Out 0.606 0.606 - -un2_rdo_serdes_rst_dual_c_1_1 Net - - - - 1 -rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 B In 0.000 0.606 - -rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 Z Out 0.390 0.996 - -un2_rdo_serdes_rst_dual_c_2_i Net - - - - 1 -rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] FD1P3DX SP In 0.000 0.996 - -=================================================================================================================================== - - - -##### END OF TIMING REPORT #####] - -Timing exceptions that could not be applied -None - -Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) - - -Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB) - ---------------------------------------- -Resource Usage Report -Part: lfe5um_25f-6 - -Register bits: 221 of 24288 (1%) -PIC Latch: 0 -I/O cells: 0 - - -Details: -CCU2C: 113 -DCUA: 1 -FD1P3BX: 20 -FD1P3DX: 92 -FD1S3BX: 12 -FD1S3DX: 97 -GSR: 1 -INV: 3 -ORCALUT4: 153 -PFUMX: 2 -PUR: 1 -VHI: 6 -VLO: 6 -Mapper successful! - -At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB) - -Process took 0h:00m:03s realtime, 0h:00m:03s cputime -# Fri May 10 11:59:02 2019 - -###########################################################] diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr.db b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr.db deleted file mode 100644 index 1e1a850b20308c7deb626fa6593c682b7dc66616..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 16384 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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. -Product Version M-2017.03L-SP1-1 - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) - -Reading constraint file: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc -@L: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt -Printing clock summary report in "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB) - -@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. -ICG Latch Removal Summary: -Number of ICG latches removed: 0 -Number of ICG latches not removed: 0 -syn_allowed_resources : blockrams=56 set on top level netlist sgmii_ecp5 - -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) - - - -Clock Summary -****************** - - Start Requested Requested Clock Clock Clock -Level Clock Frequency Period Type Group Load ----------------------------------------------------------------------------------------------------------------------- -0 - System 100.0 MHz 10.000 system system_clkgroup 0 - -0 - sgmii_ecp5|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 93 - -0 - sgmii_ecp5|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 77 - -0 - sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 53 -====================================================================================================================== - -@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. - -Finished Pre Mapping Phase. - -Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) - -Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) -original code -> new code - 00 -> 00 - 01 -> 01 - 10 -> 10 - 11 -> 11 -@N: MO225 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required. - -Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) - -None -None - -Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) - -Pre-mapping successful! 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Make sure that there are no unused intermediate registers. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 8 to 7 of genblk5.rdiff_comp_unlock[8:6]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[6]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers. - diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_area_report.xml b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_area_report.xml deleted file mode 100644 index 8fa1b06..0000000 --- a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_area_report.xml +++ /dev/null @@ -1,26 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_resourceusage.rpt -Resource Usage - - -220 - - -0 - - -0 - - -0 - - -150 - - diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_errors.txt b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_errors.txt deleted file mode 100644 index e69de29..0000000 diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_notes.txt b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_notes.txt deleted file mode 100644 index 2d9eda0..0000000 --- a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_notes.txt +++ /dev/null @@ -1,23 +0,0 @@ -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1304:0:1304:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rcount[15:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1759:0:1759:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance pcount[21:0] -@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Removing sequential instance sll_state[0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":412:3:412:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":909:3:909:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":527:3:527:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":778:3:778:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":680:3:680:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. -@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.edn -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. -@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_opt_report.xml b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_opt_report.xml deleted file mode 100644 index 2137e39..0000000 --- a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_opt_report.xml +++ /dev/null @@ -1,14 +0,0 @@ - - - - -3 / 0 - -/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_combined_clk.rpt -START OF CLOCK OPTIMIZATION REPORT - - - diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_runstatus.xml b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_runstatus.xml deleted file mode 100644 index dc0003e..0000000 --- a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_runstatus.xml +++ /dev/null @@ -1,46 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_fpga_mapper.srr -Synopsys Lattice Technology Mapper - - -Completed - - - -23 - -/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_notes.txt - - - -4 - -/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_warnings.txt - - - -0 - -/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_errors.txt - - - -0h:00m:03s - - -0h:00m:03s - - -152MB - - -1557476618 - - - diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_timing_report.xml b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_timing_report.xml deleted file mode 100644 index ae318a5..0000000 --- a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_timing_report.xml +++ /dev/null @@ -1,41 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_fpga_mapper.srr -START OF TIMING REPORT - - -Clock Name -Req Freq -Est Freq -Slack - - -serdes_sync_1|pll_refclki -100.0 MHz -168.9 MHz -4.079 - - -serdes_sync_1|rxrefclk -100.0 MHz -170.5 MHz -4.136 - - -serdes_sync_1|tx_pclk_inferred_clock -100.0 MHz -237.5 MHz -5.789 - - -System -100.0 MHz -840.7 MHz -8.810 - - diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_warnings.txt b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_warnings.txt deleted file mode 100644 index 08dea66..0000000 --- a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_warnings.txt +++ /dev/null @@ -1,4 +0,0 @@ -@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":160:4:160:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) -@W: MT420 |Found inferred clock serdes_sync_1|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" -@W: MT420 |Found inferred clock serdes_sync_1|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" -@W: MT420 |Found inferred clock serdes_sync_1|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_errors.txt b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_errors.txt deleted file mode 100644 index e69de29..0000000 diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_notes.txt b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_notes.txt deleted file mode 100644 index ff38fdb..0000000 --- a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_notes.txt +++ /dev/null @@ -1,8 +0,0 @@ -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) -@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_runstatus.xml b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_runstatus.xml deleted file mode 100644 index e63e0c3..0000000 --- a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_runstatus.xml +++ /dev/null @@ -1,46 +0,0 @@ - - - - -/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_premap.srr -Synopsys Lattice Technology Pre-mapping - - -Completed - - - -8 - -/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_notes.txt - - - -3 - -/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_warnings.txt - - - -0 - -/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_errors.txt - - - -0h:00m:00s - - -0h:00m:00s - - -145MB - - -1557476614 - - - diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_warnings.txt b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_warnings.txt deleted file mode 100644 index b332633..0000000 --- a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_warnings.txt +++ /dev/null @@ -1,3 +0,0 @@ -@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|pll_refclki which controls 92 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Found inferred clock serdes_sync_1|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_compiler.srr b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_compiler.srr deleted file mode 100644 index 471f88d..0000000 --- a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_compiler.srr +++ /dev/null @@ -1,357 +0,0 @@ -Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. - -Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. - -Running on host :lxhadeb07 -@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps -@N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1. -VHDL syntax check successful! -File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling - -At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) - - -Process completed successfully. -# Fri May 10 10:23:30 2019 - -###########################################################] -Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. - -Running on host :lxhadeb07 -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) -@I::"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" (library work) -Verilog syntax check successful! - -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) - - -Process completed successfully. -# Fri May 10 10:23:31 2019 - -###########################################################] -Running on host :lxhadeb07 -@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps -@N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1. -File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling -File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling -VHDL syntax check successful! -File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling -@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Synthesizing work.serdes_sync_1.v1. -Post processing for work.serdes_sync_1.v1 - -At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) - - -Process completed successfully. -# Fri May 10 10:23:31 2019 - -###########################################################] -Running on host :lxhadeb07 -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps) -@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps) -@I::"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" (library work) -Verilog syntax check successful! -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work. - - PDATA_RST_VAL=32'b00000000000000000000000000000000 - Generated name = sync_0s -@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1051:7:1051:27|Synthesizing module serdes_sync_1sll_core in library work. - - PPROTOCOL=48'b010001110011100001000010001100010011000001000010 - PLOL_SETTING=32'b00000000000000000000000000000001 - PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100 - PPCIE_MAX_RATE=24'b001100100010111000110101 - PDIFF_VAL_LOCK=32'b00000000000000000000000000100111 - PDIFF_VAL_UNLOCK=32'b00000000000000000000000100000110 - PPCLK_TC=32'b00000000000000100000000000000000 - PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000 - PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000 - PPCLK_DIV11_TC=32'b00000000000000000000000000000000 - LPLL_LOSS_ST=2'b00 - LPLL_PRELOSS_ST=2'b01 - LPLL_PRELOCK_ST=2'b10 - LPLL_LOCK_ST=2'b11 - LRCLK_TC=16'b1111111111111111 - LRCLK_TC_PUL_WIDTH=16'b0000000000110010 - LHB_WAIT_CNT=8'b11111111 - LPCLK_TC_0=32'b00000000000000001000000000000000 - LPCLK_TC_1=32'b00000000000000010000000000000000 - LPCLK_TC_2=32'b00000000000000100000000000000000 - LPCLK_TC_3=32'b00000000000000101000000000000000 - LPCLK_TC_4=32'b00000000000000010000000000000000 - LPDIFF_LOCK_00=32'b00000000000000000000000000001001 - LPDIFF_LOCK_10=32'b00000000000000000000000000010011 - LPDIFF_LOCK_20=32'b00000000000000000000000000100111 - LPDIFF_LOCK_30=32'b00000000000000000000000000110001 - LPDIFF_LOCK_40=32'b00000000000000000000000000010011 - LPDIFF_LOCK_01=32'b00000000000000000000000000001001 - LPDIFF_LOCK_11=32'b00000000000000000000000000010011 - LPDIFF_LOCK_21=32'b00000000000000000000000000100111 - LPDIFF_LOCK_31=32'b00000000000000000000000000110001 - LPDIFF_LOCK_41=32'b00000000000000000000000000010011 - LPDIFF_LOCK_02=32'b00000000000000000000000000110001 - LPDIFF_LOCK_12=32'b00000000000000000000000001100010 - LPDIFF_LOCK_22=32'b00000000000000000000000011000100 - LPDIFF_LOCK_32=32'b00000000000000000000000011110101 - LPDIFF_LOCK_42=32'b00000000000000000000000001100010 - LPDIFF_LOCK_03=32'b00000000000000000000000010000011 - LPDIFF_LOCK_13=32'b00000000000000000000000100000110 - LPDIFF_LOCK_23=32'b00000000000000000000001000001100 - LPDIFF_LOCK_33=32'b00000000000000000000001010001111 - LPDIFF_LOCK_43=32'b00000000000000000000000100000110 - LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011 - LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111 - LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110 - LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010 - LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111 - LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001 - LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011 - LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110 - LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111 - LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011 - LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000 - LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000 - LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000 - LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000 - LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000 - LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100 - LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001 - LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010 - LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111 - LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001 - Generated name = serdes_sync_1sll_core_Z1_layer1 -@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1287:54:1287:59|Removing redundant assignment. -@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1293:52:1293:55|Removing redundant assignment. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization. -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -Could not match passed parameter, trying a case insensitive search ... -@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":92:7:92:27|Synthesizing module serdes_sync_1rsl_core in library work. - - pnum_channels=32'b00000000000000000000000000000001 - pprotocol=48'b010001110011100001000010001100010011000001000010 - pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000 - pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100 - pwait_tx_rdy=32'b00000000000000000000101110111000 - pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100 - pwait_rx_rdy=32'b00000000000000000000101110111000 - wa_num_cycles=32'b00000000000000000000010000000000 - dac_num_cycles=32'b00000000000000000000000000000011 - lreset_pwidth=32'b00000000000000000000000000000011 - lwait_b4_trst=32'b00000000000010111110101111000010 - lwait_b4_trst_s=32'b00000000000000000000001100001101 - lplol_cnt_width=32'b00000000000000000000000000010100 - lwait_after_plol0=32'b00000000000000000000000000000100 - lwait_b4_rrst=32'b00000000000000101100000000000000 - lrrst_wait_width=32'b00000000000000000000000000010100 - lwait_after_rrst=32'b00000000000011000011010100000000 - lwait_b4_rrst_s=32'b00000000000000000000000111001100 - lrlol_cnt_width=32'b00000000000000000000000000010011 - lwait_after_lols=32'b00000000000000001100010000000000 - lwait_after_lols_s=32'b00000000000000000000000010010110 - llols_cnt_width=32'b00000000000000000000000000010010 - lrdb_max=32'b00000000000000000000000000001111 - ltxr_wait_width=32'b00000000000000000000000000001100 - lrxr_wait_width=32'b00000000000000000000000000001100 - Generated name = serdes_sync_1rsl_core_Z2_layer1 -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size. -@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 8 to 7 of genblk5.rdiff_comp_unlock[8:6]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[6]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers. -@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state. -Extracted state machine for register sll_state -State machine has 3 reachable states with original encodings of: - 00 - 01 - 11 - -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB) - - -Process completed successfully. -# Fri May 10 10:23:32 2019 - -###########################################################] -Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 -@N|Running in 64-bit mode -File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.srs changed - recompiling -File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.srs changed - recompiling - -======================================================================================= -For a summary of linker messages for components that did not bind, please see log file: -@L: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.linkerlog -======================================================================================= - - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Fri May 10 10:23:32 2019 - -###########################################################] -@END - -At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Fri May 10 10:23:32 2019 - -###########################################################] diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_compiler.srr.db b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_compiler.srr.db deleted file mode 100644 index b41afd23ba561957247397e61c5ae2f6545ea0dd..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 32768 zcmeHQOLN=S6$U9$)SI@O)JapPH>%qtu0rBLP$Uw!k!4v?E!Pjp?MyWp3`9Z_DiA;b zP^4VSF4@WSJ(+aTPP6T%UGx|94|LO2yYDiaZqi3IZKg9l_ku4trfiu2D73(cxFiLV z_`dtV`OdxPVEy)*V#{b-H_MWZIO+@)i&1YPL{U@%9^>$6Z!vf>+I|5ge*L&DLA~~` zAI`v0vDA+#_=~oPfrx>Kfrx>Kfrx>Kfrx>Kfrx>Kfrx>Kf&X&`>{#;rg$uF9>$bF| z%4ONIq#fC6m+_@L%ZnS!Xk+op+A?at`-)OR`;uAQmCSjhD%xK6RqK%M8+(e@bFcxQ zR5bflEb9-SsZUZLr#?#kHTB`-`xEbt|19~Fu^%OVF#7Ju_v7D-9a8tat)M1# zZv1@Xu<_0d@ufAE&d+6b^|G9iN~R)dnH|N>*ya{*6*IP6HdM)$Glr>uM=rwqvSo|b zwvn-9vm{%hb)XeR+VzTYzY;Bd+g9}*rI_BI6PN|AAka?1*B4b4nX&{N0_{k$EM-S4 z%bIN=TSr@pjTjc`+h|ADw$wd7ZI+bnZLz4A4Y8uBdU0=);RX8b)&~(i4_~&UShj4! zld`@qm(bP$(hXZFEB7Q@(Y16{GBripu|8;0XG1~(;~xcQLP7!U7X^(6DMEpM+B-tQ zKL%#Q!N7ul49tXsft-H~OoxL3-aiJW!ofh+KL#el!2stU0~6t3z`v{EJL80bb$m5s za)kiRLXM}gS%?e1e#@+2BMnuwiUl@Y*QhHRrXrU0l33goEjx{FNP9A}DyEF=U6?|% zcV&1g!9&yA9|l8PHp_BJ0V}riO;*Fq+g|So>R0T8}MFS7XgFEeF$MRj5-MGUr}r6$ zTcaL_b9{LPpW_1CK1Zw=Gax%{r6^~h=azM?l;P40E!J|`3`kC6OS0q)R8Kvp+5gP^d-`bVX!2;{X#6O7 zG8 z(@X;s@M1^^=(qA_U;-|Lgn)j2w}A=xd`JlB=XD#DfWsFE0eh$YD$sAu&A|9S7Y_XS zJ~QnD<9|LJ`1`Fm8W{g`;lST-z0tt<&xZrQUpCO;XTyQtCljbiJxlPP{>8`rRDcJI zkDmz%1^xPf2NZlJBoy@P1_M)o_5T^_+f-_7c6#RA^m9`$PF|e2G)^aTV{arDN3V@s zkKc;jg#%8!HEIkYS32z`)fjan&z|1G)D`Ty-uS z$UV2=u>L1U>%pWK*`$A6Xl?bz=Ve@w(j&yFm`tFZa)2&NP5Zk}Zj-z0J1~4} zif>&efMY|bKBzlfeH;e-$fkJ0y4!n$Kv@|=-8rLY7K%cr?w~uFmVaZ&-s?j{>x`UP zC|qd$95KrRL3=&;x@GgEnL?3eI&}*bD^?{)kK@}FqCoHt;R?Yzqbd}izCvKwCm&PQ zJi)R$gt~LaR2Ifm+EsUcHq|Q&0Jl1Xpz8t)(Z8^Jl7MT|IzHgKmLqj`>Zh+*@6}L^ z4+(V7xb^YvBD04;Cmrj2v`S%|~x zj*O^~=ub3jVzFd`2S63AO^z%F0Ga5dgh``Ck}D9Ayn^@+3P^%fg59rzHz28?wu2MH z;Itl{AA&3(a#ub!ledP(1ThX+8jOP{U_#X`V4~_L6E}y(1dmNzmgXPBM1`~oqiA7a zBNlyY6O-S-Of(Zi=p9*yiLAgg$Mp_}iB?7xf5}MR7+SL+z9N7oIq)iq^%rsivh5-;%BJrb< z1X(!qtgMx=BURp&_7xqn*FxIY{oawX3Jz85MI{+-!Ix^yV{fXYwFc5{Q!kTo)z%H9 z%KNg~GooI+J|vp5Iq(Pwc>j2sn6&M<8;3{J*M~(D3vMFtd9hDO({NkU>?)z@Ebeqn zAwX9(Ca6u*O(%h{lbfxTUl{j0CoM5|4Vkq^Em5o)F^8-(-Uz zWMxQ%^bX6%6Vfv%`%g$izlI5E1fRo^&w+6-;C*)hemH}p(`A4VY|t8`{Sux=Tf{)bK*T`AK*T`AK*T`AK*T_p7-%eh6EbQa zei!n2!+oWg;AWPXJPjeEko_A9zP@1|kj&pYl54gp!D>=)q(J`vGTdrP(a0^gJNE)W zIQu*KcRSsC^)68v!K*9x&9VC31)*~{tWJ;xvjDDMFZ9*@4T7BH=L%F;o)Gz`?gN(d zhJYrwjtOYu1;J}3-Q>!=#IJQ5 new code - 00 -> 00 - 01 -> 01 - 11 -> 10 -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1304:0:1304:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rcount[15:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1759:0:1759:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance pcount[21:0] -@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Removing sequential instance sll_state[0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":412:3:412:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":909:3:909:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":527:3:527:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":778:3:778:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] -@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":680:3:680:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] - -Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) - - -Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB) - - -Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) - - -Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) - - -Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) - - -Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) - - -Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) - - -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) - - -Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) - -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). - -Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB) - -Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------- - 1 0h:00m:01s 5.35ns 151 / 220 -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). -@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)). - -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB) - -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. - -Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB) - - - -@S |Clock Optimization Summary - - -#### START OF CLOCK OPTIMIZATION REPORT #####[ - -3 non-gated/non-generated clock tree(s) driving 220 clock pin(s) of sequential element(s) -0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) -0 instances converted, 0 sequential instances remain driven by gated/generated clocks - -============================================= Non-Gated/Non-Generated Clocks ============================================= -Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------------------------------------------- -@K:CKID0001 pll_refclki port 90 rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0] -@K:CKID0002 rxrefclk port 77 rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] -@K:CKID0003 DCU0_inst DCUA 53 sll_inst.pcount_diff[21] -========================================================================================================================== - - -##### END OF CLOCK OPTIMIZATION REPORT ######] - - -Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 148MB) - -Writing Analyst data base /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_m.srm - -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB) - -Writing EDIF Netlist and constraint files -@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.edn -M-2017.03L-SP1-1 -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF - -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB) - -Writing Verilog Simulation files - -Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB) - -Writing VHDL Simulation files - -Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB) - - -Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB) - -@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":160:4:160:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) -@W: MT420 |Found inferred clock serdes_sync_1|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk" -@W: MT420 |Found inferred clock serdes_sync_1|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki" -@W: MT420 |Found inferred clock serdes_sync_1|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk" - - -##### START OF TIMING REPORT #####[ -# Timing Report written on Fri May 10 10:23:38 2019 -# - - -Top view: serdes_sync_1 -Requested Frequency: 100.0 MHz -Wire load mode: top -Paths requested: 5 -Constraint File(s): /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc - -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. - -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. - - - -Performance Summary -******************* - - -Worst slack in design: 4.079 - -@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching. - Requested Estimated Requested Estimated Clock Clock -Starting Clock Frequency Frequency Period Period Slack Type Group -------------------------------------------------------------------------------------------------------------------------------------------- -serdes_sync_1|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0 -serdes_sync_1|rxrefclk 100.0 MHz 170.5 MHz 10.000 5.864 4.136 inferred Inferred_clkgroup_1 -serdes_sync_1|tx_pclk_inferred_clock 100.0 MHz 237.5 MHz 10.000 4.211 5.789 inferred Inferred_clkgroup_2 -System 100.0 MHz 840.7 MHz 10.000 1.190 8.810 system system_clkgroup -=========================================================================================================================================== - - - - - -Clock Relationships -******************* - -Clocks | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------------------------------------------------------------------- -Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack -------------------------------------------------------------------------------------------------------------------------------------------------------------------- -System System | 10.000 10.000 | No paths - | No paths - | No paths - -System serdes_sync_1|rxrefclk | 10.000 8.811 | No paths - | No paths - | No paths - -serdes_sync_1|pll_refclki System | 10.000 8.307 | No paths - | No paths - | No paths - -serdes_sync_1|pll_refclki serdes_sync_1|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths - -serdes_sync_1|pll_refclki serdes_sync_1|tx_pclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths - -serdes_sync_1|rxrefclk System | 10.000 8.193 | No paths - | No paths - | No paths - -serdes_sync_1|rxrefclk serdes_sync_1|rxrefclk | 10.000 4.136 | No paths - | No paths - | No paths - -serdes_sync_1|tx_pclk_inferred_clock serdes_sync_1|pll_refclki | Diff grp - | No paths - | No paths - | No paths - -serdes_sync_1|tx_pclk_inferred_clock serdes_sync_1|tx_pclk_inferred_clock | 10.000 5.789 | No paths - | No paths - | No paths - -=================================================================================================================================================================== - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - - -Interface Information -********************* - -No IO constraint found - - - -==================================== -Detailed Report for Clock: serdes_sync_1|pll_refclki -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------------ -rsl_inst.genblk1\.plol_cnt[1] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.079 -rsl_inst.genblk1\.plol_cnt[6] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.079 -rsl_inst.genblk1\.plol_cnt[7] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.079 -rsl_inst.genblk1\.plol_cnt[12] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[12] 0.907 4.079 -rsl_inst.genblk1\.plol_cnt[2] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.684 -rsl_inst.genblk1\.plol_cnt[3] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.684 -rsl_inst.genblk1\.plol_cnt[4] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684 -rsl_inst.genblk1\.plol_cnt[5] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684 -rsl_inst.genblk1\.plol_cnt[8] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684 -rsl_inst.genblk1\.plol_cnt[9] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[9] 0.907 4.684 -======================================================================================================================= - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock --------------------------------------------------------------------------------------------------------------------------- -rsl_inst.genblk1\.plol_cnt[19] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079 -rsl_inst.genblk1\.plol_cnt[17] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139 -rsl_inst.genblk1\.plol_cnt[18] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139 -rsl_inst.genblk1\.plol_cnt[15] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200 -rsl_inst.genblk1\.plol_cnt[16] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200 -rsl_inst.genblk1\.plol_cnt[13] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261 -rsl_inst.genblk1\.plol_cnt[14] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261 -rsl_inst.genblk1\.plol_cnt[11] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322 -rsl_inst.genblk1\.plol_cnt[12] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322 -rsl_inst.genblk1\.plol_cnt[9] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383 -========================================================================================================================== - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.054 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 9.946 - - - Propagation time: 5.867 - - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : 4.079 - - Number of logic level(s): 15 - Starting point: rsl_inst.genblk1\.plol_cnt[1] / Q - Ending point: rsl_inst.genblk1\.plol_cnt[19] / D - The start point is clocked by serdes_sync_1|pll_refclki [rising] on pin CK - The end point is clocked by serdes_sync_1|pll_refclki [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------- -rsl_inst.genblk1\.plol_cnt[1] FD1S3DX Q Out 0.907 0.907 - -plol_cnt[1] Net - - - - 2 -rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 - -rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 - -un1_plol_cnt_tc_10 Net - - - - 1 -rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 - -rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 - -un1_plol_cnt_tc_14 Net - - - - 1 -rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 - -rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 - -un1_plol_cnt_tc Net - - - - 5 -rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 - -rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 - -plol_cnt Net - - - - 21 -rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 - -rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 - -plol_cnt_cry[0] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 - -rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 - -plol_cnt_cry[2] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 - -rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 - -plol_cnt_cry[4] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 - -rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 - -plol_cnt_cry[6] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 - -rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 - -plol_cnt_cry[8] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 - -rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 - -plol_cnt_cry[10] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 - -rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 - -plol_cnt_cry[12] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 - -rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 - -plol_cnt_cry[14] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 - -rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 - -plol_cnt_cry[16] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 - -rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 - -plol_cnt_cry[18] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 - -rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 - -plol_cnt_s[19] Net - - - - 1 -rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 - -======================================================================================================= - - - - -==================================== -Detailed Report for Clock: serdes_sync_1|rxrefclk -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------------- -rsl_inst.genblk2\.rlol1_cnt[14] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[14] 0.907 4.136 -rsl_inst.genblk2\.rlol1_cnt[15] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[15] 0.907 4.136 -rsl_inst.genblk2\.rlol1_cnt[16] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[16] 0.907 4.136 -rsl_inst.genblk2\.rlol1_cnt[17] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[17] 0.907 4.136 -rsl_inst.genblk2\.rlols0_cnt[9] serdes_sync_1|rxrefclk FD1P3DX Q rlols0_cnt[9] 0.907 4.170 -rsl_inst.genblk2\.rlols0_cnt[11] serdes_sync_1|rxrefclk FD1P3DX Q rlols0_cnt[11] 0.907 4.170 -rsl_inst.genblk2\.rlols0_cnt[12] serdes_sync_1|rxrefclk FD1P3DX Q rlols0_cnt[12] 0.907 4.170 -rsl_inst.genblk2\.rlols0_cnt[13] serdes_sync_1|rxrefclk FD1P3DX Q rlols0_cnt[13] 0.907 4.170 -rsl_inst.genblk2\.rlol1_cnt[0] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742 -rsl_inst.genblk2\.rlol1_cnt[1] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[1] 0.907 4.742 -======================================================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------------------------------- -rsl_inst.genblk2\.rlol1_cnt[17] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136 -rsl_inst.genblk2\.rlol1_cnt[18] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136 -rsl_inst.genblk2\.rlols0_cnt[17] serdes_sync_1|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170 -rsl_inst.genblk2\.rlol1_cnt[15] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197 -rsl_inst.genblk2\.rlol1_cnt[16] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197 -rsl_inst.genblk2\.rlols0_cnt[15] serdes_sync_1|rxrefclk FD1P3DX D rlols0_cnt_s[15] 9.946 4.231 -rsl_inst.genblk2\.rlols0_cnt[16] serdes_sync_1|rxrefclk FD1P3DX D rlols0_cnt_s[16] 9.946 4.231 -rsl_inst.genblk2\.rlol1_cnt[13] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[13] 9.946 4.258 -rsl_inst.genblk2\.rlol1_cnt[14] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[14] 9.946 4.258 -rsl_inst.genblk2\.rlols0_cnt[13] serdes_sync_1|rxrefclk FD1P3DX D rlols0_cnt_s[13] 9.946 4.292 -=========================================================================================================================== - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.054 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 9.946 - - - Propagation time: 5.809 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.136 - - Number of logic level(s): 14 - Starting point: rsl_inst.genblk2\.rlol1_cnt[14] / Q - Ending point: rsl_inst.genblk2\.rlol1_cnt[18] / D - The start point is clocked by serdes_sync_1|rxrefclk [rising] on pin CK - The end point is clocked by serdes_sync_1|rxrefclk [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------- -rsl_inst.genblk2\.rlol1_cnt[14] FD1P3DX Q Out 0.907 0.907 - -rlol1_cnt[14] Net - - - - 2 -rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 A In 0.000 0.907 - -rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 Z Out 0.606 1.513 - -rlol1_cnt_tc_1_10 Net - - - - 1 -rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 D In 0.000 1.513 - -rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 Z Out 0.606 2.119 - -rlol1_cnt_tc_1_14 Net - - - - 1 -rsl_inst.rlol1_cnt_tc_1 ORCALUT4 D In 0.000 2.119 - -rsl_inst.rlol1_cnt_tc_1 ORCALUT4 Z Out 0.768 2.887 - -rlol1_cnt_tc_1 Net - - - - 6 -rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 A In 0.000 2.887 - -rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 Z Out 0.837 3.724 - -rlol1_cnt Net - - - - 20 -rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C A1 In 0.000 3.724 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C COUT Out 0.900 4.624 - -rlol1_cnt_cry[0] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C CIN In 0.000 4.624 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C COUT Out 0.061 4.685 - -rlol1_cnt_cry[2] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C CIN In 0.000 4.685 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C COUT Out 0.061 4.746 - -rlol1_cnt_cry[4] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C CIN In 0.000 4.746 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C COUT Out 0.061 4.807 - -rlol1_cnt_cry[6] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C CIN In 0.000 4.807 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C COUT Out 0.061 4.868 - -rlol1_cnt_cry[8] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C CIN In 0.000 4.868 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C COUT Out 0.061 4.929 - -rlol1_cnt_cry[10] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C CIN In 0.000 4.929 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C COUT Out 0.061 4.990 - -rlol1_cnt_cry[12] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C CIN In 0.000 4.990 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C COUT Out 0.061 5.051 - -rlol1_cnt_cry[14] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C CIN In 0.000 5.051 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C COUT Out 0.061 5.112 - -rlol1_cnt_cry[16] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C CIN In 0.000 5.112 - -rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C S1 Out 0.698 5.809 - -rlol1_cnt_s[18] Net - - - - 1 -rsl_inst.genblk2\.rlol1_cnt[18] FD1P3DX D In 0.000 5.809 - -======================================================================================================== - - - - -==================================== -Detailed Report for Clock: serdes_sync_1|tx_pclk_inferred_clock -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------------------------------- -sll_inst.ppul_sync_p1 serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p1 1.098 5.789 -sll_inst.ppul_sync_p2 serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p2 1.098 5.789 -sll_inst.pcount_diff[0] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_0 0.985 6.147 -sll_inst.pcount[0] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q pcount[0] 0.955 6.178 -sll_inst.pcount_diff[1] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_1 0.955 6.239 -sll_inst.pcount_diff[2] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_2 0.955 6.239 -sll_inst.pcount[1] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q pcount[1] 0.907 6.287 -sll_inst.pcount[2] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q pcount[2] 0.907 6.287 -sll_inst.pcount_diff[3] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_3 0.955 6.300 -sll_inst.pcount_diff[4] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_4 0.955 6.300 -=========================================================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock --------------------------------------------------------------------------------------------------------------------------------------------- -sll_inst.pcount[21] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[21] 9.946 5.789 -sll_inst.pcount[19] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[19] 9.946 5.850 -sll_inst.pcount[20] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[20] 9.946 5.850 -sll_inst.pcount[17] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[17] 9.946 5.911 -sll_inst.pcount[18] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[18] 9.946 5.911 -sll_inst.pcount[15] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[15] 9.946 5.972 -sll_inst.pcount[16] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[16] 9.946 5.972 -sll_inst.pcount[13] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[13] 9.946 6.033 -sll_inst.pcount[14] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[14] 9.946 6.033 -sll_inst.pcount_diff[21] serdes_sync_1|tx_pclk_inferred_clock FD1P3DX D un1_pcount_diff_1_s_21_0_S0 9.946 6.034 -============================================================================================================================================ - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.054 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 9.946 - - - Propagation time: 4.157 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 5.789 - - Number of logic level(s): 13 - Starting point: sll_inst.ppul_sync_p1 / Q - Ending point: sll_inst.pcount[21] / D - The start point is clocked by serdes_sync_1|tx_pclk_inferred_clock [rising] on pin CK - The end point is clocked by serdes_sync_1|tx_pclk_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- -sll_inst.ppul_sync_p1 FD1S3DX Q Out 1.098 1.098 - -ppul_sync_p1 Net - - - - 25 -sll_inst.pcount10_0_o3 ORCALUT4 A In 0.000 1.098 - -sll_inst.pcount10_0_o3 ORCALUT4 Z Out 0.851 1.950 - -N_8 Net - - - - 25 -sll_inst.pcount_cry_0[0] CCU2C A1 In 0.000 1.950 - -sll_inst.pcount_cry_0[0] CCU2C COUT Out 0.900 2.850 - -pcount_cry[0] Net - - - - 1 -sll_inst.pcount_cry_0[1] CCU2C CIN In 0.000 2.850 - -sll_inst.pcount_cry_0[1] CCU2C COUT Out 0.061 2.911 - -pcount_cry[2] Net - - - - 1 -sll_inst.pcount_cry_0[3] CCU2C CIN In 0.000 2.911 - -sll_inst.pcount_cry_0[3] CCU2C COUT Out 0.061 2.972 - -pcount_cry[4] Net - - - - 1 -sll_inst.pcount_cry_0[5] CCU2C CIN In 0.000 2.972 - -sll_inst.pcount_cry_0[5] CCU2C COUT Out 0.061 3.033 - -pcount_cry[6] Net - - - - 1 -sll_inst.pcount_cry_0[7] CCU2C CIN In 0.000 3.033 - -sll_inst.pcount_cry_0[7] CCU2C COUT Out 0.061 3.094 - -pcount_cry[8] Net - - - - 1 -sll_inst.pcount_cry_0[9] CCU2C CIN In 0.000 3.094 - -sll_inst.pcount_cry_0[9] CCU2C COUT Out 0.061 3.155 - -pcount_cry[10] Net - - - - 1 -sll_inst.pcount_cry_0[11] CCU2C CIN In 0.000 3.155 - -sll_inst.pcount_cry_0[11] CCU2C COUT Out 0.061 3.216 - -pcount_cry[12] Net - - - - 1 -sll_inst.pcount_cry_0[13] CCU2C CIN In 0.000 3.216 - -sll_inst.pcount_cry_0[13] CCU2C COUT Out 0.061 3.277 - -pcount_cry[14] Net - - - - 1 -sll_inst.pcount_cry_0[15] CCU2C CIN In 0.000 3.277 - -sll_inst.pcount_cry_0[15] CCU2C COUT Out 0.061 3.338 - -pcount_cry[16] Net - - - - 1 -sll_inst.pcount_cry_0[17] CCU2C CIN In 0.000 3.338 - -sll_inst.pcount_cry_0[17] CCU2C COUT Out 0.061 3.399 - -pcount_cry[18] Net - - - - 1 -sll_inst.pcount_cry_0[19] CCU2C CIN In 0.000 3.399 - -sll_inst.pcount_cry_0[19] CCU2C COUT Out 0.061 3.460 - -pcount_cry[20] Net - - - - 1 -sll_inst.pcount_s_0[21] CCU2C CIN In 0.000 3.460 - -sll_inst.pcount_s_0[21] CCU2C S0 Out 0.698 4.157 - -pcount_s[21] Net - - - - 1 -sll_inst.pcount[21] FD1S3DX D In 0.000 4.157 - -============================================================================================ - - - - -==================================== -Detailed Report for Clock: System -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock -------------------------------------------------------------------------------------------- -DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 8.810 -DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 8.810 -DCU0_inst System DCUA CH0_FF_RX_PCLK rx_pclk 0.000 10.000 -=========================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------- -rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX SP un2_rdo_serdes_rst_dual_c_2_i 9.806 8.810 -rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX D un2_rdo_serdes_rst_dual_c_1 9.946 9.556 -rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946 -rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946 -DCU0_inst System DCUA CH0_FF_RXI_CLK rx_pclk 10.000 10.000 -========================================================================================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 10.000 - - Setup time: 0.194 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 9.806 - - - Propagation time: 0.996 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (non-critical) : 8.810 - - Number of logic level(s): 2 - Starting point: DCU0_inst / CH0_FFS_RLOL - Ending point: rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP - The start point is clocked by System [rising] - The end point is clocked by serdes_sync_1|rxrefclk [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------- -DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 - -rx_cdr_lol_s Net - - - - 4 -rsl_inst.un2_rdo_serdes_rst_dual_c_2_0 ORCALUT4 B In 0.000 0.000 - -rsl_inst.un2_rdo_serdes_rst_dual_c_2_0 ORCALUT4 Z Out 0.606 0.606 - -un2_rdo_serdes_rst_dual_c_2_0 Net - - - - 1 -rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO[0] ORCALUT4 B In 0.000 0.606 - -rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO[0] ORCALUT4 Z Out 0.390 0.996 - -un2_rdo_serdes_rst_dual_c_2_i Net - - - - 1 -rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] FD1P3DX SP In 0.000 0.996 - -================================================================================================================================= - - - -##### END OF TIMING REPORT #####] - -Timing exceptions that could not be applied -None - -Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB) - - -Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB) - ---------------------------------------- -Resource Usage Report -Part: lfe5um_25f-6 - -Register bits: 220 of 24288 (1%) -PIC Latch: 0 -I/O cells: 0 - - -Details: -CCU2C: 113 -DCUA: 1 -FD1P3BX: 20 -FD1P3DX: 92 -FD1S3BX: 12 -FD1S3DX: 96 -GSR: 1 -INV: 3 -ORCALUT4: 150 -PFUMX: 2 -PUR: 1 -VHI: 6 -VLO: 6 -Mapper successful! - -At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 152MB) - -Process took 0h:00m:03s realtime, 0h:00m:03s cputime -# Fri May 10 10:23:38 2019 - -###########################################################] diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_fpga_mapper.srr.db b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_fpga_mapper.srr.db deleted file mode 100644 index f91149b0137889f30b1864304ece9560b909c129..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 16384 zcmeHNPjA~c6t|tUNt32&yQNuI1mJQ?fJTv=*m2y;(ljZC^>31`YtuoXCCcV3lNw3e zaodZ1>IMuOu*GHFkl!k4E)a-Q0bw`si}1Pn!=@!)QFV0Ol0qzS>0G$*;+$e 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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. -Product Version M-2017.03L-SP1-1 - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) - -Reading constraint file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc -@L: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt -Printing clock summary report in "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt" file -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 115MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 117MB) - -@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances. -@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances. -ICG Latch Removal Summary: -Number of ICG latches removed: 0 -Number of ICG latches not removed: 0 -syn_allowed_resources : blockrams=56 set on top level netlist serdes_sync_1 - -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB) - - - -Clock Summary -****************** - - Start Requested Requested Clock Clock Clock -Level Clock Frequency Period Type Group Load -------------------------------------------------------------------------------------------------------------------------- -0 - System 100.0 MHz 10.000 system system_clkgroup 0 - -0 - serdes_sync_1|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 92 - -0 - serdes_sync_1|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 77 - -0 - serdes_sync_1|tx_pclk_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 53 -========================================================================================================================= - -@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|pll_refclki which controls 92 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Found inferred clock serdes_sync_1|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. - -Finished Pre Mapping Phase. - -Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 145MB) - -Encoding state machine sll_state[2:0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) -original code -> new code - 00 -> 00 - 01 -> 01 - 11 -> 10 - -Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB) - -None -None - -Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB) - -Pre-mapping successful! - -At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 59MB peak: 145MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Fri May 10 10:23:34 2019 - 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    -
-#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
-#install: /home/soft/lattice/diamond/3.10_x64/synpbase
-#OS: Linux 
-#Hostname: lxhadeb07
-
-# Tue Apr 30 12:09:44 2019
-
-#Implementation: syn_results
-
-Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
-@N: :  | Running in 64-bit mode 
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
-@N: :  | Running in 64-bit mode 
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Running on host :lxhadeb07
-@N:CD720 : std.vhd(123) | Setting time resolution to ps
-@N: : PCSD.vhd(24) | Top entity is set to PCSD.
-VHDL syntax check successful!
-File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 72MB)
-
-
-Process completed successfully.
-# Tue Apr 30 12:09:44 2019
-
-###########################################################]
-Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
-@N: :  | Running in 64-bit mode 
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Running on host :lxhadeb07
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
-@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work)
-Verilog syntax check successful!
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
-
-
-Process completed successfully.
-# Tue Apr 30 12:09:45 2019
-
-###########################################################]
-Running on host :lxhadeb07
-@N:CD720 : std.vhd(123) | Setting time resolution to ps
-@N: : PCSD.vhd(24) | Top entity is set to PCSD.
-File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling
-File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
-VHDL syntax check successful!
-File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling
-@N:CD630 : PCSD.vhd(24) | Synthesizing work.pcsd.v1.
-Post processing for work.pcsd.v1
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
-
-
-Process completed successfully.
-# Tue Apr 30 12:09:45 2019
-
-###########################################################]
-Running on host :lxhadeb07
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
-@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work)
-Verilog syntax check successful!
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-@N:CG364 : PCSD_softlogic.v(92) | Synthesizing module PCSDrsl_core in library work.
-
-	pnum_channels=32'b00000000000000000000000000000001
-	pprotocol=24'b010001110100001001000101
-	pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
-	pport_tx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100
-	pwait_tx_rdy=32'b00000000000000000000101110111000
-	pport_rx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100
-	pwait_rx_rdy=32'b00000000000000000000101110111000
-	wa_num_cycles=32'b00000000000000000000010000000000
-	dac_num_cycles=32'b00000000000000000000000000000011
-	lreset_pwidth=32'b00000000000000000000000000000011
-	lwait_b4_trst=32'b00000000000010111110101111000010
-	lwait_b4_trst_s=32'b00000000000000000000001100001101
-	lplol_cnt_width=32'b00000000000000000000000000010100
-	lwait_after_plol0=32'b00000000000000000000000000000100
-	lwait_b4_rrst=32'b00000000000000101100000000000000
-	lrrst_wait_width=32'b00000000000000000000000000010100
-	lwait_after_rrst=32'b00000000000011000011010100000000
-	lwait_b4_rrst_s=32'b00000000000000000000000111001100
-	lrlol_cnt_width=32'b00000000000000000000000000010011
-	lwait_after_lols=32'b00000000000000001100010000000000
-	lwait_after_lols_s=32'b00000000000000000000000010010110
-	llols_cnt_width=32'b00000000000000000000000000010010
-	lrdb_max=32'b00000000000000000000000000001111
-	ltxr_wait_width=32'b00000000000000000000000000001100
-	lrxr_wait_width=32'b00000000000000000000000000001100
-   Generated name = PCSDrsl_core_Z1_layer1
-@W:CG360 : PCSD_softlogic.v(274) | Removing wire dual_or_serd_rst, as there is no assignment to it.
-@W:CG360 : PCSD_softlogic.v(275) | Removing wire tx_any_pcs_rst, as there is no assignment to it.
-@W:CG360 : PCSD_softlogic.v(276) | Removing wire tx_any_rst, as there is no assignment to it.
-@W:CG133 : PCSD_softlogic.v(277) | Object txsr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W:CG133 : PCSD_softlogic.v(278) | Object txdpr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W:CG133 : PCSD_softlogic.v(279) | Object txpr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W:CG133 : PCSD_softlogic.v(280) | Object txr_wt_en is declared but not assigned. Either assign a value or remove the declaration.
-@W:CG133 : PCSD_softlogic.v(281) | Object txr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W:CG360 : PCSD_softlogic.v(282) | Removing wire txr_wt_tc, as there is no assignment to it.
-@W:CG133 : PCSD_softlogic.v(283) | Object ruo_tx_rdyr is declared but not assigned. Either assign a value or remove the declaration.
-@W:CG133 : PCSD_softlogic.v(326) | Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W:CG360 : PCSD_softlogic.v(327) | Removing wire rrst_cnt_tc, as there is no assignment to it.
-@W:CG133 : PCSD_softlogic.v(328) | Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
-@W:CG133 : PCSD_softlogic.v(341) | Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W:CG133 : PCSD_softlogic.v(342) | Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
-@W:CG360 : PCSD_softlogic.v(343) | Removing wire rxp_cnt_tc, as there is no assignment to it.
-@W:CG133 : PCSD_softlogic.v(346) | Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W:CG360 : PCSD_softlogic.v(347) | Removing wire rlolsz_cnt_tc, as there is no assignment to it.
-@W:CG360 : PCSD_softlogic.v(350) | Removing wire rxp_cnt2_tc, as there is no assignment to it.
-@W:CG133 : PCSD_softlogic.v(351) | Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W:CG133 : PCSD_softlogic.v(352) | Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
-@W:CG360 : PCSD_softlogic.v(353) | Removing wire data_loop_b_tc, as there is no assignment to it.
-@W:CG133 : PCSD_softlogic.v(356) | Object rxsr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W:CG133 : PCSD_softlogic.v(357) | Object rxpr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W:CG133 : PCSD_softlogic.v(358) | Object rxsdr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W:CG133 : PCSD_softlogic.v(359) | Object rxdpr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W:CG360 : PCSD_softlogic.v(360) | Removing wire rxsdr_or_sr_appd, as there is no assignment to it.
-@W:CG360 : PCSD_softlogic.v(361) | Removing wire dual_or_rserd_rst, as there is no assignment to it.
-@W:CG360 : PCSD_softlogic.v(362) | Removing wire rx_any_pcs_rst, as there is no assignment to it.
-@W:CG360 : PCSD_softlogic.v(363) | Removing wire rx_any_rst, as there is no assignment to it.
-@W:CG133 : PCSD_softlogic.v(364) | Object rxr_wt_en is declared but not assigned. Either assign a value or remove the declaration.
-@W:CG133 : PCSD_softlogic.v(365) | Object rxr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W:CG360 : PCSD_softlogic.v(366) | Removing wire rxr_wt_tc, as there is no assignment to it.
-@W:CG133 : PCSD_softlogic.v(367) | Object ruo_rx_rdyr is declared but not assigned. Either assign a value or remove the declaration.
-@W:CG133 : PCSD_softlogic.v(507) | Object m is declared but not assigned. Either assign a value or remove the declaration.
-@W:CG133 : PCSD_softlogic.v(880) | Object l is declared but not assigned. Either assign a value or remove the declaration.
-@W:CL169 : PCSD_softlogic.v(806) | Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
-@W:CL169 : PCSD_softlogic.v(567) | Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
-@W:CL169 : PCSD_softlogic.v(567) | Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
-@W:CL190 : PCSD_softlogic.v(694) | Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W:CL190 : PCSD_softlogic.v(461) | Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W:CL190 : PCSD_softlogic.v(422) | Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W:CL260 : PCSD_softlogic.v(422) | Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W:CL260 : PCSD_softlogic.v(461) | Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W:CL260 : PCSD_softlogic.v(694) | Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W:CL246 : PCSD_softlogic.v(200) | Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W:CL246 : PCSD_softlogic.v(204) | Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W:CL246 : PCSD_softlogic.v(205) | Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W:CL246 : PCSD_softlogic.v(206) | Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W:CL246 : PCSD_softlogic.v(207) | Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 75MB)
-
-
-Process completed successfully.
-# Tue Apr 30 12:09:45 2019
-
-###########################################################]
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
-@N: :  | Running in 64-bit mode 
-File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer0.srs changed - recompiling
-File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer1.srs changed - recompiling
-
-=======================================================================================
-For a summary of linker messages for components that did not bind, please see log file:
-Linked File: PCSD_comp.linkerlog
-=======================================================================================
-
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Apr 30 12:09:46 2019
-
-###########################################################]
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Apr 30 12:09:46 2019
-
-###########################################################]
-
-