From 40d3c2fb2e53ae3788a70e50c101d89ba4fb524f Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 15 May 2014 19:06:02 +0200 Subject: [PATCH] added few more registers to represent configuration of the data handler in endpoints. --- trb_net16_endpoint_hades_full_handler.vhd | 275 ++++++++++++---------- 1 file changed, 146 insertions(+), 129 deletions(-) diff --git a/trb_net16_endpoint_hades_full_handler.vhd b/trb_net16_endpoint_hades_full_handler.vhd index a1e4fd4..7f3844c 100644 --- a/trb_net16_endpoint_hades_full_handler.vhd +++ b/trb_net16_endpoint_hades_full_handler.vhd @@ -25,7 +25,7 @@ entity trb_net16_endpoint_hades_full_handler is REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - REGIO_COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); + REGIO_INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0'); REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; @@ -199,19 +199,33 @@ architecture trb_net16_endpoint_hades_full_handler_arch of trb_net16_endpoint_ha signal stat_header_buffer_level: std_logic_vector (31 downto 0); signal dbuf_read_enable : std_logic; - signal dbuf_addr : std_logic_vector (3 downto 0); - signal dbuf_data_in : std_logic_vector (31 downto 0); + signal dbuf_addr : std_logic_vector (15 downto 0); + signal dbuf_data_out : std_logic_vector (31 downto 0); signal dbuf_dataready : std_logic; signal dbuf_unknown_addr : std_logic; - signal tbuf_dataready : std_logic; - signal tbuf_read_enable : std_logic; - - signal dummy : std_logic_vector(324 downto 0); - signal write_enable : std_logic_vector(7 downto 0); - signal read_enable : std_logic_vector(7 downto 0); - signal last_write_enable : std_logic_vector(7 downto 0); - signal last_read_enable : std_logic_vector(7 downto 0); + signal info_addr : std_logic_vector(15 downto 0); + signal info_data_in : std_logic_vector(31 downto 0); + signal info_data_out : std_logic_vector(31 downto 0); + signal info_read : std_logic; + signal info_write : std_logic; + signal info_rd_nack : std_logic; + signal info_wr_nack : std_logic; + signal info_wr_ack : std_logic; + signal info_valid : std_logic; + signal info_invalid : std_logic; + signal info_registers : std_logic_vector_array_32(0 to 3); + + signal stat_handler_addr : std_logic_vector(15 downto 0); + signal stat_handler_data_in : std_logic_vector(31 downto 0); + signal stat_handler_data_out : std_logic_vector(31 downto 0); + signal stat_handler_read : std_logic; + signal stat_handler_write : std_logic; + signal stat_handler_valid : std_logic; + signal stat_handler_invalid : std_logic; + signal stat_handler_registers : std_logic_vector_array_32(0 to 2); + + signal dummy : std_logic_vector(100 downto 0); signal debug_data_handler_i : std_logic_vector(31 downto 0); signal debug_ipu_handler_i : std_logic_vector(31 downto 0); @@ -224,11 +238,14 @@ architecture trb_net16_endpoint_hades_full_handler_arch of trb_net16_endpoint_ha signal int_lvl1_long_trg : std_logic; signal tmg_trg_error_i : std_logic; - signal stat_buffer_i : std_logic_vector(31 downto 0); + signal stat_buffer_out : std_logic_vector(31 downto 0); signal stat_buffer_read : std_logic; + signal stat_buffer_write : std_logic; signal stat_buffer_ready : std_logic; signal stat_buffer_unknown : std_logic; - signal stat_buffer_address : std_logic_vector(4 downto 0); + signal stat_buffer_wr_nack : std_logic; + signal stat_buffer_rd_nack : std_logic; + signal stat_buffer_address : std_logic_vector(15 downto 0); signal max_event_size : std_logic_vector(15 downto 0); signal new_max_size : std_logic_vector(15 downto 0); @@ -253,7 +270,7 @@ begin REGIO_INIT_BOARD_INFO => REGIO_INIT_BOARD_INFO, REGIO_INIT_ENDPOINT_ID => REGIO_INIT_ENDPOINT_ID, REGIO_COMPILE_TIME => REGIO_COMPILE_TIME, - REGIO_COMPILE_VERSION => REGIO_COMPILE_VERSION, + REGIO_INCLUDED_FEATURES => REGIO_INCLUDED_FEATURES, REGIO_HARDWARE_VERSION => REGIO_HARDWARE_VERSION, REGIO_USE_1WIRE_INTERFACE => REGIO_USE_1WIRE_INTERFACE, REGIO_USE_VAR_ENDPOINT_ID => REGIO_USE_VAR_ENDPOINT_ID, @@ -358,9 +375,9 @@ begin THE_INTERNAL_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 8, - PORT_ADDRESSES => (0 => x"8000", 1 => x"7100", 2 => x"7110", 3 => x"7200", 4 => x"7201", 5 => x"7202", 6 => x"7300", 7 => x"7111", others => x"0000"), - PORT_ADDR_MASK => (0 => 15, 1 => 4, 2 => 0, 3 => 0, 4 => 0, 5 => 0, 6 => 5, 7 => 0, others => 0) + PORT_NUMBER => 5, + PORT_ADDRESSES => (0 => x"8000", 1 => x"7100", 2 => x"7110", 3 => x"7200", 4 => x"7300", others => x"0000"), + PORT_ADDR_MASK => (0 => 15, 1 => 4, 2 => 3, 3 => 2, 4 => 5, others => 0) ) port map( CLK => CLK, @@ -377,138 +394,139 @@ begin DAT_NO_MORE_DATA_OUT => regio_nomoredata_i, DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_i, --- BUS_READ_ENABLE_OUT(0) => BUS_READ_ENABLE_OUT, --- BUS_WRITE_ENABLE_OUT(0) => BUS_WRITE_ENABLE_OUT, --- BUS_DATA_OUT(31 downto 0) => BUS_DATA_OUT, --- BUS_ADDR_OUT(15 downto 0) => BUS_ADDR_OUT, --- BUS_TIMEOUT_OUT(0) => BUS_TIMEOUT_OUT, --- BUS_DATA_IN(31 downto 0) => BUS_DATA_IN, --- BUS_DATAREADY_IN(0) => BUS_DATAREADY_IN, --- BUS_WRITE_ACK_IN(0) => BUS_WRITE_ACK_IN, --- BUS_NO_MORE_DATA_IN(0) => BUS_NO_MORE_DATA_IN, --- BUS_UNKNOWN_ADDR_IN(0) => BUS_UNKNOWN_ADDR_IN, --- --- BUS_READ_ENABLE_OUT(1) => dbuf_read_enable, --- BUS_WRITE_ENABLE_OUT(1) => open, --- BUS_DATA_OUT(63 downto 32) => open, --- BUS_ADDR_OUT(19 downto 16) => dbuf_addr, --- BUS_ADDR_OUT(31 downto 20) => open, --- BUS_TIMEOUT_OUT(1) => open, --- BUS_DATA_IN(63 downto 32) => dbuf_data_in, --- BUS_DATAREADY_IN(1) => dbuf_dataready, --- BUS_WRITE_ACK_IN(1) => '0', --- BUS_NO_MORE_DATA_IN(1) => '0', --- BUS_UNKNOWN_ADDR_IN(1) => dbuf_unknown_addr, --- --- BUS_READ_ENABLE_OUT(2) => tbuf_read_enable, --- BUS_WRITE_ENABLE_OUT(2) => open, --- BUS_DATA_OUT(95 downto 64) => open, --- BUS_ADDR_OUT(47 downto 32) => open, --- BUS_TIMEOUT_OUT(1) => open, --- BUS_DATA_IN(95 downto 64) => stat_header_buffer_level, --- BUS_DATAREADY_IN(2) => tbuf_dataready, --- BUS_WRITE_ACK_IN(2) => '0', --- BUS_NO_MORE_DATA_IN(2) => '0', --- BUS_UNKNOWN_ADDR_IN(2) => '0' - --Fucking Modelsim wants it like this... BUS_READ_ENABLE_OUT(0) => BUS_READ_ENABLE_OUT, BUS_READ_ENABLE_OUT(1) => dbuf_read_enable, - BUS_READ_ENABLE_OUT(2) => tbuf_read_enable, - BUS_READ_ENABLE_OUT(3) => read_enable(3), - BUS_READ_ENABLE_OUT(4) => read_enable(4), - BUS_READ_ENABLE_OUT(5) => read_enable(5), - BUS_READ_ENABLE_OUT(6) => stat_buffer_read, - BUS_READ_ENABLE_OUT(7) => read_enable(6), + BUS_READ_ENABLE_OUT(2) => info_read, + BUS_READ_ENABLE_OUT(3) => stat_handler_read, + BUS_READ_ENABLE_OUT(4) => stat_buffer_read, + BUS_WRITE_ENABLE_OUT(0) => BUS_WRITE_ENABLE_OUT, - BUS_WRITE_ENABLE_OUT(1) => dummy(0), - BUS_WRITE_ENABLE_OUT(2) => write_enable(2), - BUS_WRITE_ENABLE_OUT(3) => write_enable(3), - BUS_WRITE_ENABLE_OUT(4) => write_enable(4), - BUS_WRITE_ENABLE_OUT(5) => write_enable(5), - BUS_WRITE_ENABLE_OUT(6) => write_enable(6), - BUS_WRITE_ENABLE_OUT(7) => write_enable(7), - BUS_DATA_OUT(31 downto 0) => BUS_DATA_OUT, - BUS_DATA_OUT(63 downto 32) => dummy(33 downto 2), - BUS_DATA_OUT(95 downto 64) => dummy(65 downto 34), - BUS_DATA_OUT(191 downto 96) => dummy(191 downto 96), - BUS_DATA_OUT(223 downto 192)=> dummy(291 downto 260), - BUS_DATA_OUT(239 downto 224)=> new_max_size, - BUS_DATA_OUT(255 downto 240)=> dummy(307 downto 292), - BUS_ADDR_OUT(15 downto 0) => BUS_ADDR_OUT, - BUS_ADDR_OUT(19 downto 16) => dbuf_addr, - BUS_ADDR_OUT(31 downto 20) => dummy(77 downto 66), - BUS_ADDR_OUT(47 downto 32) => dummy(93 downto 78), - BUS_ADDR_OUT(95 downto 48) => dummy(242 downto 195), - BUS_ADDR_OUT(100 downto 96)=> stat_buffer_address, - BUS_ADDR_OUT(111 downto 101)=> dummy(259 downto 249), - BUS_ADDR_OUT(127 downto 112)=> dummy(323 downto 308), + BUS_WRITE_ENABLE_OUT(1) => dummy(100), + BUS_WRITE_ENABLE_OUT(2) => info_write, + BUS_WRITE_ENABLE_OUT(3) => stat_handler_write, + BUS_WRITE_ENABLE_OUT(4) => stat_buffer_write, + + BUS_DATA_OUT(31 downto 0) => BUS_DATA_OUT, + BUS_DATA_OUT(63 downto 32) => dummy(31 downto 0), + BUS_DATA_OUT(95 downto 64) => info_data_in, + BUS_DATA_OUT(127 downto 96) => dummy(63 downto 32), + BUS_DATA_OUT(159 downto 128)=> dummy(95 downto 64), + + BUS_ADDR_OUT(15 downto 0) => BUS_ADDR_OUT, + BUS_ADDR_OUT(31 downto 16) => dbuf_addr, + BUS_ADDR_OUT(47 downto 32) => info_addr, + BUS_ADDR_OUT(63 downto 48) => stat_handler_addr, + BUS_ADDR_OUT(79 downto 64) => stat_buffer_address, + BUS_TIMEOUT_OUT(0) => BUS_TIMEOUT_OUT, - BUS_TIMEOUT_OUT(1) => dummy(94), - BUS_TIMEOUT_OUT(2) => dummy(95), - BUS_TIMEOUT_OUT(3) => dummy(192), - BUS_TIMEOUT_OUT(4) => dummy(193), - BUS_TIMEOUT_OUT(5) => dummy(194), - BUS_TIMEOUT_OUT(6) => dummy(243), - BUS_TIMEOUT_OUT(7) => dummy(324), + BUS_TIMEOUT_OUT(1) => dummy(96), + BUS_TIMEOUT_OUT(2) => dummy(97), + BUS_TIMEOUT_OUT(3) => dummy(98), + BUS_TIMEOUT_OUT(4) => dummy(99), + BUS_DATA_IN(31 downto 0) => BUS_DATA_IN, - BUS_DATA_IN(63 downto 32) => dbuf_data_in, - BUS_DATA_IN(95 downto 64) => stat_header_buffer_level, - BUS_DATA_IN(191 downto 96) => stat_handler_i(95 downto 0), - BUS_DATA_IN(223 downto 192)=> stat_buffer_i, - BUS_DATA_IN(239 downto 224)=> max_event_size, - BUS_DATA_IN(255 downto 240)=> x"0000", + BUS_DATA_IN(63 downto 32) => dbuf_data_out, + BUS_DATA_IN(95 downto 64) => info_data_out, + BUS_DATA_IN(127 downto 96) => stat_handler_data_out, + BUS_DATA_IN(159 downto 128)=> stat_buffer_out, + BUS_DATAREADY_IN(0) => BUS_DATAREADY_IN, BUS_DATAREADY_IN(1) => dbuf_dataready, - BUS_DATAREADY_IN(2) => tbuf_dataready, - BUS_DATAREADY_IN(3) => last_read_enable(3), - BUS_DATAREADY_IN(4) => last_read_enable(4), - BUS_DATAREADY_IN(5) => last_read_enable(5), - BUS_DATAREADY_IN(6) => stat_buffer_ready, - BUS_DATAREADY_IN(7) => last_read_enable(7), + BUS_DATAREADY_IN(2) => info_valid, + BUS_DATAREADY_IN(3) => stat_handler_valid, + BUS_DATAREADY_IN(4) => stat_buffer_ready, + BUS_WRITE_ACK_IN(0) => BUS_WRITE_ACK_IN, BUS_WRITE_ACK_IN(1) => '0', - BUS_WRITE_ACK_IN(2) => '0', + BUS_WRITE_ACK_IN(2) => info_wr_ack, BUS_WRITE_ACK_IN(3) => '0', BUS_WRITE_ACK_IN(4) => '0', - BUS_WRITE_ACK_IN(5) => '0', - BUS_WRITE_ACK_IN(6) => '0', - BUS_WRITE_ACK_IN(7) => write_enable(7), + BUS_NO_MORE_DATA_IN(0) => BUS_NO_MORE_DATA_IN, BUS_NO_MORE_DATA_IN(1) => '0', BUS_NO_MORE_DATA_IN(2) => '0', BUS_NO_MORE_DATA_IN(3) => '0', BUS_NO_MORE_DATA_IN(4) => '0', - BUS_NO_MORE_DATA_IN(5) => '0', - BUS_NO_MORE_DATA_IN(6) => '0', - BUS_NO_MORE_DATA_IN(7) => '0', + BUS_UNKNOWN_ADDR_IN(0) => BUS_UNKNOWN_ADDR_IN, BUS_UNKNOWN_ADDR_IN(1) => dbuf_unknown_addr, - BUS_UNKNOWN_ADDR_IN(2) => last_write_enable(2), - BUS_UNKNOWN_ADDR_IN(3) => last_write_enable(3), - BUS_UNKNOWN_ADDR_IN(4) => last_write_enable(4), - BUS_UNKNOWN_ADDR_IN(5) => last_write_enable(5), - BUS_UNKNOWN_ADDR_IN(6) => stat_buffer_unknown, - BUS_UNKNOWN_ADDR_IN(7) => '0' + BUS_UNKNOWN_ADDR_IN(2) => info_invalid, + BUS_UNKNOWN_ADDR_IN(3) => stat_handler_invalid, + BUS_UNKNOWN_ADDR_IN(4) => stat_buffer_unknown ); - proc_ack_strobes : process(CLK) - begin - if rising_edge(CLK) then - last_write_enable <= write_enable; - last_read_enable <= read_enable; - end if; - end process; +stat_buffer_wr_nack <= stat_buffer_write; +stat_buffer_unknown <= stat_buffer_wr_nack or stat_buffer_rd_nack when rising_edge(CLK); + +--------------------------------------------------------------------------- +-- registers 0x7110 ff. +--------------------------------------------------------------------------- + +THE_HANDLER_INFO_REGS : bus_register_handler + generic map( + BUS_LENGTH => 4 + ) + port map( + RESET => RESET, + CLK => CLK, + DATA_IN => info_registers, + READ_EN_IN => info_read, + WRITE_EN_IN => '0', + ADDR_IN(2 downto 0) => info_addr(2 downto 0), + ADDR_IN(6 downto 3) => "0000", + DATA_OUT => info_data_out, + DATAREADY_OUT => info_valid, + UNKNOWN_ADDR_OUT => info_rd_nack + ); + +info_invalid <= info_rd_nack or info_wr_nack; +info_registers(0) <= stat_header_buffer_level; +info_registers(1) <= std_logic_vector(to_unsigned((2**DATA_BUFFER_DEPTH-DATA_BUFFER_FULL_THRESH-1),16)) & max_event_size; +info_registers(2) <= std_logic_vector(to_unsigned(DATA_BUFFER_FULL_THRESH,16)) + & std_logic_vector(to_unsigned(DATA_BUFFER_DEPTH,8)) + & std_logic_vector(to_unsigned(DATA_INTERFACE_NUMBER,8)); +info_registers(3) <= std_logic_vector(to_unsigned(TRG_RELEASE_AFTER_DATA,1)) + & "0000000" + & std_logic_vector(to_unsigned(HEADER_BUFFER_FULL_THRESH,16)) + & std_logic_vector(to_unsigned(HEADER_BUFFER_DEPTH,8)); proc_maxeventsize : process begin wait until rising_edge(CLK); if RESET = '1' then max_event_size <= std_logic_vector(to_unsigned((2**DATA_BUFFER_DEPTH-DATA_BUFFER_FULL_THRESH-1),16)); - elsif write_enable(7) = '1' then - max_event_size <= new_max_size; + elsif info_write = '1' and info_addr(2 downto 0) = "001" then + max_event_size <= info_data_in(15 downto 0); + info_wr_ack <= '1'; + info_wr_nack <= '0'; + else + info_wr_nack <= info_write; end if; - end process; - + end process; + +--------------------------------------------------------------------------- +-- registers 0x7200 ff. +--------------------------------------------------------------------------- +THE_HANDLER_STATUS_REGS : bus_register_handler + generic map( + BUS_LENGTH => 3 + ) + port map( + RESET => RESET, + CLK => CLK, + DATA_IN => stat_handler_registers, + READ_EN_IN => stat_handler_read, + WRITE_EN_IN => '0', + ADDR_IN(2 downto 0) => stat_handler_addr(2 downto 0), + ADDR_IN(6 downto 3) => "0000", + DATA_OUT => stat_handler_data_out, + DATAREADY_OUT => stat_handler_valid, + UNKNOWN_ADDR_OUT => stat_handler_invalid + ); +stat_handler_registers(0) <= stat_handler_i(31 downto 0); +stat_handler_registers(1) <= stat_handler_i(63 downto 32); +stat_handler_registers(2) <= stat_handler_i(95 downto 64); + --------------------------------------------------------------------------- -- Data and IPU Handler --------------------------------------------------------------------------- @@ -565,11 +583,11 @@ begin STAT_HEADER_BUFFER_LEVEL => stat_header_buffer_level, STATUS_OUT => stat_handler_i, TIMER_TICKS_IN => time_ticks_i, - STATISTICS_DATA_OUT => stat_buffer_i, - STATISTICS_UNKNOWN_OUT => stat_buffer_unknown, + STATISTICS_DATA_OUT => stat_buffer_out, + STATISTICS_UNKNOWN_OUT => stat_buffer_rd_nack, STATISTICS_READY_OUT => stat_buffer_ready, STATISTICS_READ_IN => stat_buffer_read, - STATISTICS_ADDR_IN => stat_buffer_address, + STATISTICS_ADDR_IN => stat_buffer_address(4 downto 0), --Debug @@ -594,14 +612,13 @@ begin if rising_edge(CLK) then dbuf_unknown_addr <= '0'; dbuf_dataready <= '0'; - tbuf_dataready <= tbuf_read_enable; if dbuf_read_enable = '1' then - tmp := to_integer(unsigned(dbuf_addr)); + tmp := to_integer(unsigned(dbuf_addr(3 downto 0))); if tmp < DATA_INTERFACE_NUMBER then - dbuf_data_in <= stat_data_buffer_level(tmp*32+31 downto tmp*32); + dbuf_data_out <= stat_data_buffer_level(tmp*32+31 downto tmp*32); dbuf_dataready <= '1'; else - dbuf_data_in <= (others => '0'); + dbuf_data_out <= (others => '0'); dbuf_unknown_addr <= '1'; end if; end if; -- 2.43.0