From 413e405c448a0e2b327afde54f59d61df45bf9eb Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Tue, 14 Dec 2021 15:02:52 +0100 Subject: [PATCH] fixed bugs in RX_LSM --- media_interfaces/med_ecp3_sfp_sync_all_RS.vhd | 11 ++--- media_interfaces/sync/med_sync_control_RS.vhd | 12 +++--- media_interfaces/sync/rx_control_RS.vhd | 4 +- media_interfaces/sync/rx_lsm_RS.vhd | 40 +++++++++---------- media_interfaces/sync/rx_rsl.vhd | 6 +-- media_interfaces/sync/tx_control_RS.vhd | 21 ++++++---- 6 files changed, 47 insertions(+), 47 deletions(-) diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd index 53621cd..30ebef4 100644 --- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd @@ -496,7 +496,7 @@ end generate; -- WAP WA_POS_OUT => wa_position_i, WA_READ_OUT => wa_read_i, --open, - LINK_RX_READY_IN => '0', -- BUG + LINK_RX_READY_IN => '0', -- NOT REALLY NEEDED --Slowcontrol BUS_RX => BUS_RX, BUS_TX => BUS_TX, @@ -517,14 +517,9 @@ end generate; STAT_DEBUG(3 downto 0) <= clk_rx_full(3 downto 0); STAT_DEBUG(7 downto 4) <= clk_tx_full(3 downto 0); STAT_DEBUG(63 downto 8) <= (others => '0'); - + + -- SerDes #3 is used for debugging DEBUG_OUT <= debug_i(3*32+31 downto 3*32); --- DEBUG_OUT(11 downto 0) <= debug_i(3*32+11 downto 3*32); --- DEBUG_OUT(12) <= debug_i(3*32+12); --debug_tx_control_i(3*32+4); --- DEBUG_OUT(13) <= debug_i(3*32+13); --debug_tx_control_i(3*32+5); --- DEBUG_OUT(14) <= debug_i(3*32+14); --debug_tx_control_i(3*32+30); --- DEBUG_OUT(15) <= debug_i(3*32+15); --debug_tx_control_i(3*32+31); --- DEBUG_OUT(31 downto 16) <= debug_i(3*32+31 downto 3*32+16); end architecture; diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd index fc1dd56..e2a31da 100644 --- a/media_interfaces/sync/med_sync_control_RS.vhd +++ b/media_interfaces/sync/med_sync_control_RS.vhd @@ -155,9 +155,9 @@ begin SD_LOS_IN => SFP_LOS_IN, WAP_ZERO_IN => is_wap_zero_i, -- outputs - RX_SERDES_RST_OUT => rx_serdes_rst_i, - RX_PCS_RST_OUT => rx_pcs_rst_i, - LINK_RX_READY_OUT => link_rx_ready_i, + RX_SERDES_RST_OUT => rx_serdes_rst_i, -- CLK_REF based + RX_PCS_RST_OUT => rx_pcs_rst_i, -- CLK_REF based + LINK_RX_READY_OUT => link_rx_ready_i, -- CLK_REF based STATE_OUT => rx_fsm_state ); @@ -220,8 +220,8 @@ begin CLK_RXI => CLK_RXI, RX_K_IN => RX_K_IN, RX_DATA_IN => RX_DATA_IN, - LINK_HALF_DONE_OUT => link_half_done_i, - LINK_FULL_DONE_OUT => link_full_done_i, + LINK_HALF_DONE_OUT => link_half_done_i, -- CLK_RXI based + LINK_FULL_DONE_OUT => link_full_done_i, -- CLK_RXI based STATE_OUT => rx_lsm_state --open ); @@ -317,7 +317,7 @@ begin link_status <= x"0" when ((link_half_done_i = '1') and (link_full_done_i = '1')) else x"7"; - + SYNC_MEDIA_SIGS : entity work.signal_sync generic map( WIDTH => 6, diff --git a/media_interfaces/sync/rx_control_RS.vhd b/media_interfaces/sync/rx_control_RS.vhd index 9bcfcbb..82aa343 100644 --- a/media_interfaces/sync/rx_control_RS.vhd +++ b/media_interfaces/sync/rx_control_RS.vhd @@ -30,8 +30,8 @@ entity rx_control_RS is RX_RST_WORD_OUT : out std_logic_vector(7 downto 0); -- link status signals LINK_RX_READY_IN : in std_logic; - LINK_TX_READY_IN : in std_logic; - LINK_HALF_DONE_IN : in std_logic; + LINK_TX_READY_IN : in std_logic; -- unused + LINK_HALF_DONE_IN : in std_logic; -- unused LINK_FULL_DONE_IN : in std_logic; -- debug DEBUG_OUT : out std_logic_vector(31 downto 0); diff --git a/media_interfaces/sync/rx_lsm_RS.vhd b/media_interfaces/sync/rx_lsm_RS.vhd index 7e9bbe7..85c4757 100644 --- a/media_interfaces/sync/rx_lsm_RS.vhd +++ b/media_interfaces/sync/rx_lsm_RS.vhd @@ -26,10 +26,12 @@ architecture rx_lsm_arch of rx_lsm_RS is signal reset_ctr_t : std_logic; signal ce_ctr_t : std_logic; + signal ce_ctr_t_q : std_logic; signal ctr_t : unsigned(4 downto 0); signal ctr_t_done : std_logic; signal reset_ctr_s : std_logic; signal ce_ctr_s : std_logic; + signal ce_ctr_s_q : std_logic; signal ctr_s : unsigned(4 downto 0); signal ctr_s_done : std_logic; signal link_toggling_int : std_logic; @@ -39,15 +41,13 @@ begin THE_CTR_T_PROC: process( CLK_RXI, LINK_RX_READY_IN ) begin - if ( LINK_RX_READY_IN <= '0' ) then + if( LINK_RX_READY_IN = '0' ) then ctr_t <= (others => '0'); elsif( rising_edge(CLK_RXI) ) then if( reset_ctr_t = '1' ) then ctr_t <= (others => '0'); - else - if( (ctr_t(4) = '0') and (ce_ctr_t = '1') ) then - ctr_t <= ctr_t + 1 ; - end if; + elsif( (ctr_t_done = '0') and (ce_ctr_t_q = '1') ) then + ctr_t <= ctr_t + 1 ; end if; end if; end process THE_CTR_T_PROC; @@ -56,15 +56,13 @@ begin THE_CTR_S_PROC: process( CLK_RXI, LINK_RX_READY_IN ) begin - if ( LINK_RX_READY_IN = '0' ) then + if( LINK_RX_READY_IN = '0' ) then ctr_s <= (others => '0'); elsif( rising_edge(CLK_RXI) ) then if( reset_ctr_s = '1' ) then ctr_s <= (others => '0'); - else - if( (ctr_s(4) = '0') and (ce_ctr_s = '1') and (ctr_t_done = '1') ) then -- added to make sure correct sequence is done - ctr_s <= ctr_s + 1 ; - end if; + elsif( (ctr_s_done = '0') and (ce_ctr_s_q = '1') and (ctr_t_done = '1') ) then -- added to make sure correct sequence is done + ctr_s <= ctr_s + 1 ; end if; end if; end process THE_CTR_S_PROC; @@ -74,10 +72,10 @@ begin -- toggling idles sequence detected THE_TOGGLE_DETECTED_PROC: process( CLK_RXI, LINK_RX_READY_IN ) begin - if ( LINK_RX_READY_IN = '0' ) then + if( LINK_RX_READY_IN = '0' ) then link_toggling_int <= '0'; elsif( rising_edge(CLK_RXI) ) then - if( ctr_t_done = '1' ) then + if( (ce_ctr_t_q = '1') and (ctr_t_done = '1') ) then link_toggling_int <= '1'; end if; end if; @@ -88,10 +86,10 @@ begin -- steady idles sequence detected THE_STEADY_DETECTED_PROC: process( CLK_RXI, LINK_RX_READY_IN ) begin - if ( LINK_RX_READY_IN = '0' ) then + if( LINK_RX_READY_IN = '0' ) then link_steady_int <= '0'; elsif( rising_edge(CLK_RXI) ) then - if( ctr_s_done = '1' ) then + if( (ce_ctr_s_q = '1') and (ctr_s_done = '1') ) then link_steady_int <= '1'; end if; end if; @@ -104,10 +102,12 @@ begin begin if( LINK_RX_READY_IN = '0' ) then CURRENT_STATE <= IDLE; - else - if( rising_edge(CLK_RXI) ) then - CURRENT_STATE <= NEXT_STATE; - end if; + ce_ctr_t_q <= '0'; + ce_ctr_s_q <= '0'; + elsif( rising_edge(CLK_RXI) ) then + CURRENT_STATE <= NEXT_STATE; + ce_ctr_t_q <= ce_ctr_t; + ce_ctr_s_q <= ce_ctr_s; end if; end process THE_FSM_PROC; @@ -152,8 +152,10 @@ begin STATE_OUT <= x"3"; if ( (RX_K_IN = '0') and (RX_DATA_IN = D_IDLE1) ) then NEXT_STATE <= D2FS; + ce_ctr_s <= '1'; elsif( (RX_K_IN = '0') and (RX_DATA_IN = D_IDLE0) ) then NEXT_STATE <= D2FT; + ce_ctr_t <= '1'; else NEXT_STATE <= IDLE; end if; @@ -162,7 +164,6 @@ begin STATE_OUT <= x"4"; if( (RX_K_IN = '1') and (RX_DATA_IN = K_IDLE) ) then NEXT_STATE <= K1F; - ce_ctr_t <= '1'; else NEXT_STATE <= IDLE; end if; @@ -171,7 +172,6 @@ begin STATE_OUT <= x"5"; if( (RX_K_IN = '1') and (RX_DATA_IN = K_IDLE) ) then NEXT_STATE <= K1F; - ce_ctr_s <= '1'; else NEXT_STATE <= IDLE; end if; diff --git a/media_interfaces/sync/rx_rsl.vhd b/media_interfaces/sync/rx_rsl.vhd index 06bc1be..dfce0cc 100644 --- a/media_interfaces/sync/rx_rsl.vhd +++ b/media_interfaces/sync/rx_rsl.vhd @@ -30,9 +30,9 @@ architecture rx_rsl_arc of rx_rsl is constant Tshort : unsigned(31 downto 0) := x"0000000a"; -- @200MHz 100ms - constant Tplol : unsigned(31 downto 0) := x"01312d00"; --x"003fffff"; - constant Tcdr : unsigned(31 downto 0) := x"01312d00"; --x"003fffff"; - constant Tviol : unsigned(31 downto 0) := x"01312d00"; --x"003fffff"; + constant Tplol : unsigned(31 downto 0) := x"003fffff"; --x"01312d00"; + constant Tcdr : unsigned(31 downto 0) := x"003fffff"; --x"01312d00"; + constant Tviol : unsigned(31 downto 0) := x"003fffff"; --x"01312d00"; signal pll_lol_s : std_logic; signal cdr_lol_s : std_logic; diff --git a/media_interfaces/sync/tx_control_RS.vhd b/media_interfaces/sync/tx_control_RS.vhd index f6799d4..607d809 100644 --- a/media_interfaces/sync/tx_control_RS.vhd +++ b/media_interfaces/sync/tx_control_RS.vhd @@ -260,9 +260,9 @@ begin -- TX control state machine ---------------------------------------------------------------------- - THE_DATA_CONTROL_FSM : process(CLK_TXI, LINK_TX_READY_IN, RESET) + THE_DATA_CONTROL_FSM : process(CLK_TXI, link_tx_ready_qtx, RESET) begin - if( (LINK_TX_READY_IN = '0') or (RESET = '1') ) then + if( RESET = '1' ) then current_state <= IDLE; TX_K_OUT <= '1'; TX_DATA_OUT <= K_NULL; @@ -275,6 +275,17 @@ begin debug_sending_dlm <= '0'; debug_sending_rst <= '0'; case current_state is + when IDLE => + TX_K_OUT <= '1'; + TX_DATA_OUT <= K_NULL; + word_sync_i <= '0'; + toggle_idle <= '1'; + if( link_tx_ready_qtx = '1' ) then + current_state <= SEND_IDLE_L; + else + current_state <= IDLE; + end if; + when SEND_IDLE_L => TX_DATA_OUT <= K_IDLE; TX_K_OUT <= '1'; @@ -320,12 +331,6 @@ begin current_state <= SEND_RST_H; debug_sending_rst <= '1'; - when IDLE => - TX_DATA_OUT <= K_NULL; - TX_K_OUT <= '1'; - current_state <= SEND_IDLE_L; - -- used to get out of async reset - when SEND_RST_H => word_sync_i <= '1'; TX_DATA_OUT <= send_rst_word_i; -- 2.43.0