From 41b44e8f10f81f90736f40ad742f652ff0c2d8d4 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Thu, 20 Jan 2022 14:35:33 +0100 Subject: [PATCH] DLM fixed --- media_interfaces/sync/tx_control_RS.vhd | 50 ++++++++++++++----------- 1 file changed, 28 insertions(+), 22 deletions(-) diff --git a/media_interfaces/sync/tx_control_RS.vhd b/media_interfaces/sync/tx_control_RS.vhd index 632600b..99d6032 100644 --- a/media_interfaces/sync/tx_control_RS.vhd +++ b/media_interfaces/sync/tx_control_RS.vhd @@ -89,7 +89,7 @@ architecture arch of tx_control_RS is signal load_eop : std_logic; signal send_steady_idle_int : std_logic; signal word_sync_i : std_logic; - + signal link_tx_ready_qtx : std_logic; signal link_rx_ready_qtx : std_logic; signal link_half_done_qtx : std_logic; @@ -97,7 +97,10 @@ architecture arch of tx_control_RS is signal link_active_int : std_logic; signal link_active_qtx : std_logic; signal link_active_qsys : std_logic; - + + signal tx_k_i : std_logic; + signal tx_data_i : std_logic_vector(7 downto 0); + -- attribute syn_keep : boolean; -- attribute syn_preserve : boolean; -- attribute syn_keep of word_sync_i : signal is true; @@ -262,21 +265,21 @@ begin begin if( RESET = '1' ) then current_state <= IDLE; - TX_K_OUT <= '1'; - TX_DATA_OUT <= K_NULL; - word_sync_i <= '0'; + tx_k_i <= '1'; + tx_data_i <= K_NULL; + word_sync_i <= '0'; else if( rising_edge(CLK_TXI) ) then - TX_K_OUT <= '0'; + tx_k_i <= '0'; word_sync_i <= '0'; debug_sending_dlm <= '0'; debug_sending_rst <= '0'; case current_state is when IDLE => - TX_K_OUT <= '1'; - TX_DATA_OUT <= K_NULL; - word_sync_i <= '0'; + tx_k_i <= '1'; + tx_data_i <= K_NULL; +-- word_sync_i <= '0'; if( link_tx_ready_qtx = '1' ) then current_state <= SEND_IDLE_L; else @@ -284,8 +287,8 @@ begin end if; when SEND_IDLE_L => - TX_DATA_OUT <= K_IDLE; - TX_K_OUT <= '1'; + tx_data_i <= K_IDLE; + tx_k_i <= '1'; if( WORD_SYNC_IN = '1' )then current_state <= SEND_IDLE_H; else @@ -295,40 +298,40 @@ begin when SEND_IDLE_H => word_sync_i <= '1'; if( send_steady_idle_int = '1' ) then - TX_DATA_OUT <= D_IDLE1; + tx_data_i <= D_IDLE1; else - TX_DATA_OUT <= D_IDLE0; + tx_data_i <= D_IDLE0; end if; when SEND_DATA_L => - TX_DATA_OUT <= ram_dout(7 downto 0); + tx_data_i <= ram_dout(7 downto 0); load_sop <= ram_dout(16); load_eop <= ram_dout(17); current_state <= SEND_DATA_H; when SEND_DATA_H => word_sync_i <= '1'; - TX_DATA_OUT <= ram_dout(15 downto 8); + tx_data_i <= ram_dout(15 downto 8); when SEND_DLM_L => - TX_DATA_OUT <= K_DLM; - TX_K_OUT <= '1'; + tx_data_i <= K_DLM; + tx_k_i <= '1'; current_state <= SEND_DLM_H; debug_sending_dlm <= '1'; when SEND_DLM_H => word_sync_i <= '1'; - TX_DATA_OUT <= send_dlm_word_i; + tx_data_i <= send_dlm_word_i; when SEND_RST_L => - TX_DATA_OUT <= K_RST; - TX_K_OUT <= '1'; + tx_data_i <= K_RST; + tx_k_i <= '1'; current_state <= SEND_RST_H; debug_sending_rst <= '1'; when SEND_RST_H => word_sync_i <= '1'; - TX_DATA_OUT <= send_rst_word_i; + tx_data_i <= send_rst_word_i; when others => current_state <= SEND_IDLE_L; @@ -461,5 +464,8 @@ send_dlm_word_i <= SEND_DLM_WORD_IN when rising_edge(CLK_TXI); x"F"; WORD_SYNC_OUT <= word_sync_i; - + + TX_K_OUT <= tx_k_i when rising_edge(CLK_TXI); + TX_DATA_OUT <= tx_data_i when rising_edge(CLK_TXI); + end architecture; -- 2.43.0