From 4247495fb8be014159bc4b9e9f20410cb1fda9d4 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 10 Jan 2014 14:42:24 +0100 Subject: [PATCH] added new fifo used in Pexor --- lattice/scm/fifo/fifo_19x16.ipx | 9 + lattice/scm/fifo/fifo_19x16.lpc | 45 + lattice/scm/fifo/fifo_19x16.vhd | 813 +++++++++++++++++++ lattice/scm/lattice_ecp2m_fifo.vhd | 14 +- special/trb_net_bridge_pcie_endpoint_hub.vhd | 5 +- 5 files changed, 883 insertions(+), 3 deletions(-) create mode 100644 lattice/scm/fifo/fifo_19x16.ipx create mode 100644 lattice/scm/fifo/fifo_19x16.lpc create mode 100644 lattice/scm/fifo/fifo_19x16.vhd diff --git a/lattice/scm/fifo/fifo_19x16.ipx b/lattice/scm/fifo/fifo_19x16.ipx new file mode 100644 index 0000000..6aa3f94 --- /dev/null +++ b/lattice/scm/fifo/fifo_19x16.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/lattice/scm/fifo/fifo_19x16.lpc b/lattice/scm/fifo/fifo_19x16.lpc new file mode 100644 index 0000000..acaff0b --- /dev/null +++ b/lattice/scm/fifo/fifo_19x16.lpc @@ -0,0 +1,45 @@ +[Device] +Family=latticescm +PartType=LFSCM3GA40EP1 +PartName=LFSCM3GA40EP1-6FC1152C +SpeedGrade=6 +Package=FCBGA1152 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=4.8 +ModuleName=fifo_19x16 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=11/29/2013 +Time=19:09:01 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=LUT Based +Depth=16 +Width=19 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Static - Single Threshold +PfAssert=8 +PfDeassert=506 +RDataCount=1 +EnECC=0 +EnFWFT=0 diff --git a/lattice/scm/fifo/fifo_19x16.vhd b/lattice/scm/fifo/fifo_19x16.vhd new file mode 100644 index 0000000..0410dd4 --- /dev/null +++ b/lattice/scm/fifo/fifo_19x16.vhd @@ -0,0 +1,813 @@ +-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) +-- Module Version: 4.8 +--/d/jspc29/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -n fifo_19x16 -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -sync_mode -depth 16 -width 19 -pfu_fifo -no_enable -pe -1 -pf 8 -fill -e + +-- Fri Nov 29 19:09:01 2013 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library SCM; +use SCM.COMPONENTS.all; +-- synopsys translate_on + +entity fifo_19x16 is + port ( + Data: in std_logic_vector(18 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(18 downto 0); + WCNT: out std_logic_vector(4 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end fifo_19x16; + +architecture Structure of fifo_19x16 is + + -- internal signal declarations + signal invout_2: std_logic; + signal invout_1: std_logic; + signal rden_i_inv: std_logic; + signal invout_0: std_logic; + signal r_nw_inv: std_logic; + signal r_nw: std_logic; + signal fcnt_en_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal co2: std_logic; + signal co1: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal cmp_le_1: std_logic; + signal co1_1: std_logic; + signal co0_2: std_logic; + signal cmp_ge_d1: std_logic; + signal co1_2: std_logic; + signal wren_i_inv: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal iwcount_4: std_logic; + signal co2_1: std_logic; + signal wcount_4: std_logic; + signal co1_3: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal ircount_4: std_logic; + signal co2_2: std_logic; + signal rcount_4: std_logic; + signal co1_4: std_logic; + signal fcnt_en_inv_inv: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_5: std_logic; + signal cnt_con: std_logic; + signal cnt_con_inv: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal af_d: std_logic; + signal co1_5: std_logic; + signal fcount_4: std_logic; + signal rdataout18: std_logic; + signal scuba_vlo: std_logic; + signal rdataout17: std_logic; + signal rdataout16: std_logic; + signal rdataout15: std_logic; + signal rdataout14: std_logic; + signal rdataout13: std_logic; + signal rdataout12: std_logic; + signal rdataout11: std_logic; + signal rdataout10: std_logic; + signal rdataout9: std_logic; + signal rdataout8: std_logic; + signal rdataout7: std_logic; + signal rdataout6: std_logic; + signal rdataout5: std_logic; + signal rdataout4: std_logic; + signal rdataout3: std_logic; + signal rdataout2: std_logic; + signal rdataout1: std_logic; + signal rdataout0: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal wren_i: std_logic; + signal scuba_vhi: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + + -- local component declarations + component DPR16X2 + -- synopsys translate_off + generic (INITVAL : in String; GSR : in String); + -- synopsys translate_on + port (DI0: in std_logic; DI1: in std_logic; + WAD3: in std_logic; WAD2: in std_logic; + WAD1: in std_logic; WAD0: in std_logic; WRE: in std_logic; + WPE: in std_logic; WCK: in std_logic; RAD3: in std_logic; + RAD2: in std_logic; RAD1: in std_logic; + RAD0: in std_logic; WDO0: out std_logic; + WDO1: out std_logic; RDO0: out std_logic; + RDO1: out std_logic); + end component; + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic; + CO: out std_logic; NC1: out std_logic; NC0: out std_logic); + end component; + component CB2 + port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic; + CON: in std_logic; CO: out std_logic; NC1: out std_logic; + NC0: out std_logic); + end component; + component AGEB2 + port (A1: in std_logic; A0: in std_logic; B1: in std_logic; + B0: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component ALEB2 + port (A1: in std_logic; A0: in std_logic; B1: in std_logic; + B0: in std_logic; CI: in std_logic; LE: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + attribute GSR : string; + attribute MEM_INIT_FILE : string; + attribute MEM_LPC_FILE : string; + attribute COMP : string; + attribute initval : string; + attribute initval of LUT4_1 : label is "0x3232"; + attribute initval of LUT4_0 : label is "0x3232"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute GSR of fifo_pfu_0_0 : label is "ENABLED"; + attribute MEM_INIT_FILE of fifo_pfu_0_0 : label is "(0-15)(0-1)"; + attribute MEM_LPC_FILE of fifo_pfu_0_0 : label is "fifo_19x16.lpc"; + attribute COMP of fifo_pfu_0_0 : label is "fifo_pfu_0_0"; + attribute initval of fifo_pfu_0_0 : label is "0x0000000000000000"; + attribute GSR of fifo_pfu_0_1 : label is "ENABLED"; + attribute MEM_INIT_FILE of fifo_pfu_0_1 : label is "(0-15)(2-3)"; + attribute MEM_LPC_FILE of fifo_pfu_0_1 : label is "fifo_19x16.lpc"; + attribute COMP of fifo_pfu_0_1 : label is "fifo_pfu_0_1"; + attribute initval of fifo_pfu_0_1 : label is "0x0000000000000000"; + attribute GSR of fifo_pfu_0_2 : label is "ENABLED"; + attribute MEM_INIT_FILE of fifo_pfu_0_2 : label is "(0-15)(4-5)"; + attribute MEM_LPC_FILE of fifo_pfu_0_2 : label is "fifo_19x16.lpc"; + attribute COMP of fifo_pfu_0_2 : label is "fifo_pfu_0_2"; + attribute initval of fifo_pfu_0_2 : label is "0x0000000000000000"; + attribute GSR of fifo_pfu_0_3 : label is "ENABLED"; + attribute MEM_INIT_FILE of fifo_pfu_0_3 : label is "(0-15)(6-7)"; + attribute MEM_LPC_FILE of fifo_pfu_0_3 : label is "fifo_19x16.lpc"; + attribute COMP of fifo_pfu_0_3 : label is "fifo_pfu_0_3"; + attribute initval of fifo_pfu_0_3 : label is "0x0000000000000000"; + attribute GSR of fifo_pfu_0_4 : label is "ENABLED"; + attribute MEM_INIT_FILE of fifo_pfu_0_4 : label is "(0-15)(8-9)"; + attribute MEM_LPC_FILE of fifo_pfu_0_4 : label is "fifo_19x16.lpc"; + attribute COMP of fifo_pfu_0_4 : label is "fifo_pfu_0_4"; + attribute initval of fifo_pfu_0_4 : label is "0x0000000000000000"; + attribute GSR of fifo_pfu_0_5 : label is "ENABLED"; + attribute MEM_INIT_FILE of fifo_pfu_0_5 : label is "(0-15)(10-11)"; + attribute MEM_LPC_FILE of fifo_pfu_0_5 : label is "fifo_19x16.lpc"; + attribute COMP of fifo_pfu_0_5 : label is "fifo_pfu_0_5"; + attribute initval of fifo_pfu_0_5 : label is "0x0000000000000000"; + attribute GSR of fifo_pfu_0_6 : label is "ENABLED"; + attribute MEM_INIT_FILE of fifo_pfu_0_6 : label is "(0-15)(12-13)"; + attribute MEM_LPC_FILE of fifo_pfu_0_6 : label is "fifo_19x16.lpc"; + attribute COMP of fifo_pfu_0_6 : label is "fifo_pfu_0_6"; + attribute initval of fifo_pfu_0_6 : label is "0x0000000000000000"; + attribute GSR of fifo_pfu_0_7 : label is "ENABLED"; + attribute MEM_INIT_FILE of fifo_pfu_0_7 : label is "(0-15)(14-15)"; + attribute MEM_LPC_FILE of fifo_pfu_0_7 : label is "fifo_19x16.lpc"; + attribute COMP of fifo_pfu_0_7 : label is "fifo_pfu_0_7"; + attribute initval of fifo_pfu_0_7 : label is "0x0000000000000000"; + attribute GSR of fifo_pfu_0_8 : label is "ENABLED"; + attribute MEM_INIT_FILE of fifo_pfu_0_8 : label is "(0-15)(16-17)"; + attribute MEM_LPC_FILE of fifo_pfu_0_8 : label is "fifo_19x16.lpc"; + attribute COMP of fifo_pfu_0_8 : label is "fifo_pfu_0_8"; + attribute initval of fifo_pfu_0_8 : label is "0x0000000000000000"; + attribute GSR of fifo_pfu_0_9 : label is "ENABLED"; + attribute MEM_INIT_FILE of fifo_pfu_0_9 : label is "(0-15)(18-19)"; + attribute MEM_LPC_FILE of fifo_pfu_0_9 : label is "fifo_19x16.lpc"; + attribute COMP of fifo_pfu_0_9 : label is "fifo_pfu_0_9"; + attribute initval of fifo_pfu_0_9 : label is "0x0000000000000000"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t4: AND2 + port map (A=>WrEn, B=>invout_2, Z=>wren_i); + + INV_8: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t3: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_7: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t2: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t1: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_6: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_5: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x3232") + -- synopsys translate_on + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x3232") + -- synopsys translate_on + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + AND2_t0: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_4: INV + port map (A=>wren_i, Z=>invout_0); + + INV_3: INV + port map (A=>fcnt_en, Z=>fcnt_en_inv); + + INV_2: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + INV_1: INV + port map (A=>r_nw, Z=>r_nw_inv); + + INV_0: INV + port map (A=>fcnt_en_inv, Z=>fcnt_en_inv_inv); + + FF_36: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_35: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_34: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_33: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_32: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_31: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_30: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_29: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_0); + + FF_28: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_27: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_26: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_25: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_24: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_0); + + FF_23: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_22: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_21: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_20: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_19: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(0)); + + FF_18: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(1)); + + FF_17: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(2)); + + FF_16: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(3)); + + FF_15: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(4)); + + FF_14: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(5)); + + FF_13: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(6)); + + FF_12: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(7)); + + FF_11: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(8)); + + FF_10: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(9)); + + FF_9: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(10)); + + FF_8: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout11, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(11)); + + FF_7: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout12, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(12)); + + FF_6: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout13, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(13)); + + FF_5: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout14, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(14)); + + FF_4: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout15, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(15)); + + FF_3: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout16, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(16)); + + FF_2: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout17, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(17)); + + FF_1: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rdataout18, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(18)); + + FF_0: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>af_d, CK=>Clock, CD=>Reset, Q=>AlmostFull); + + bdcnt_bctr_0: CB2 + port map (CI=>cnt_con, PC1=>fcount_1, PC0=>fcount_0, + CON=>cnt_con, CO=>co0, NC1=>ifcount_1, NC0=>ifcount_0); + + bdcnt_bctr_1: CB2 + port map (CI=>co0, PC1=>fcount_3, PC0=>fcount_2, CON=>cnt_con, + CO=>co1, NC1=>ifcount_3, NC0=>ifcount_2); + + bdcnt_bctr_2: CB2 + port map (CI=>co1, PC1=>scuba_vlo, PC0=>fcount_4, CON=>cnt_con, + CO=>co2, NC1=>open, NC0=>ifcount_4); + + e_cmp_0: ALEB2 + port map (A1=>fcount_1, A0=>fcount_0, B1=>scuba_vlo, B0=>rden_i, + CI=>scuba_vhi, LE=>co0_1); + + e_cmp_1: ALEB2 + port map (A1=>fcount_3, A0=>fcount_2, B1=>scuba_vlo, + B0=>scuba_vlo, CI=>co0_1, LE=>co1_1); + + e_cmp_2: ALEB2 + port map (A1=>scuba_vlo, A0=>fcount_4, B1=>scuba_vlo, + B0=>scuba_vlo, CI=>co1_1, LE=>cmp_le_1); + + g_cmp_0: AGEB2 + port map (A1=>fcount_1, A0=>fcount_0, B1=>wren_i, B0=>wren_i, + CI=>scuba_vhi, GE=>co0_2); + + g_cmp_1: AGEB2 + port map (A1=>fcount_3, A0=>fcount_2, B1=>wren_i, B0=>wren_i, + CI=>co0_2, GE=>co1_2); + + g_cmp_2: AGEB2 + port map (A1=>scuba_vlo, A0=>fcount_4, B1=>scuba_vlo, + B0=>wren_i_inv, CI=>co1_2, GE=>cmp_ge_d1); + + w_ctr_0: CU2 + port map (CI=>scuba_vhi, PC1=>wcount_1, PC0=>wcount_0, CO=>co0_3, + NC1=>iwcount_1, NC0=>iwcount_0); + + w_ctr_1: CU2 + port map (CI=>co0_3, PC1=>wcount_3, PC0=>wcount_2, CO=>co1_3, + NC1=>iwcount_3, NC0=>iwcount_2); + + w_ctr_2: CU2 + port map (CI=>co1_3, PC1=>scuba_vlo, PC0=>wcount_4, CO=>co2_1, + NC1=>open, NC0=>iwcount_4); + + r_ctr_0: CU2 + port map (CI=>scuba_vhi, PC1=>rcount_1, PC0=>rcount_0, CO=>co0_4, + NC1=>ircount_1, NC0=>ircount_0); + + r_ctr_1: CU2 + port map (CI=>co0_4, PC1=>rcount_3, PC0=>rcount_2, CO=>co1_4, + NC1=>ircount_3, NC0=>ircount_2); + + r_ctr_2: CU2 + port map (CI=>co1_4, PC1=>scuba_vlo, PC0=>rcount_4, CO=>co2_2, + NC1=>open, NC0=>ircount_4); + + af_cmp_0: AGEB2 + port map (A1=>fcount_1, A0=>fcount_0, B1=>cnt_con, + B0=>fcnt_en_inv_inv, CI=>scuba_vhi, GE=>co0_5); + + af_cmp_1: AGEB2 + port map (A1=>fcount_3, A0=>fcount_2, B1=>cnt_con_inv, + B0=>cnt_con, CI=>co0_5, GE=>co1_5); + + af_cmp_2: AGEB2 + port map (A1=>scuba_vlo, A0=>fcount_4, B1=>scuba_vlo, + B0=>scuba_vlo, CI=>co1_5, GE=>af_d); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + fifo_pfu_0_0: DPR16X2 + -- synopsys translate_off + generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") + -- synopsys translate_on + port map (DI0=>Data(18), DI1=>scuba_vlo, WAD3=>wcount_3, + WAD2=>wcount_2, WAD1=>wcount_1, WAD0=>wcount_0, + WRE=>scuba_vhi, WPE=>wren_i, WCK=>Clock, RAD3=>rcount_3, + RAD2=>rcount_2, RAD1=>rcount_1, RAD0=>rcount_0, WDO0=>open, + WDO1=>open, RDO0=>rdataout18, RDO1=>open); + + fifo_pfu_0_1: DPR16X2 + -- synopsys translate_off + generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") + -- synopsys translate_on + port map (DI0=>Data(16), DI1=>Data(17), WAD3=>wcount_3, + WAD2=>wcount_2, WAD1=>wcount_1, WAD0=>wcount_0, + WRE=>scuba_vhi, WPE=>wren_i, WCK=>Clock, RAD3=>rcount_3, + RAD2=>rcount_2, RAD1=>rcount_1, RAD0=>rcount_0, WDO0=>open, + WDO1=>open, RDO0=>rdataout16, RDO1=>rdataout17); + + fifo_pfu_0_2: DPR16X2 + -- synopsys translate_off + generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") + -- synopsys translate_on + port map (DI0=>Data(14), DI1=>Data(15), WAD3=>wcount_3, + WAD2=>wcount_2, WAD1=>wcount_1, WAD0=>wcount_0, + WRE=>scuba_vhi, WPE=>wren_i, WCK=>Clock, RAD3=>rcount_3, + RAD2=>rcount_2, RAD1=>rcount_1, RAD0=>rcount_0, WDO0=>open, + WDO1=>open, RDO0=>rdataout14, RDO1=>rdataout15); + + fifo_pfu_0_3: DPR16X2 + -- synopsys translate_off + generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") + -- synopsys translate_on + port map (DI0=>Data(12), DI1=>Data(13), WAD3=>wcount_3, + WAD2=>wcount_2, WAD1=>wcount_1, WAD0=>wcount_0, + WRE=>scuba_vhi, WPE=>wren_i, WCK=>Clock, RAD3=>rcount_3, + RAD2=>rcount_2, RAD1=>rcount_1, RAD0=>rcount_0, WDO0=>open, + WDO1=>open, RDO0=>rdataout12, RDO1=>rdataout13); + + fifo_pfu_0_4: DPR16X2 + -- synopsys translate_off + generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") + -- synopsys translate_on + port map (DI0=>Data(10), DI1=>Data(11), WAD3=>wcount_3, + WAD2=>wcount_2, WAD1=>wcount_1, WAD0=>wcount_0, + WRE=>scuba_vhi, WPE=>wren_i, WCK=>Clock, RAD3=>rcount_3, + RAD2=>rcount_2, RAD1=>rcount_1, RAD0=>rcount_0, WDO0=>open, + WDO1=>open, RDO0=>rdataout10, RDO1=>rdataout11); + + fifo_pfu_0_5: DPR16X2 + -- synopsys translate_off + generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") + -- synopsys translate_on + port map (DI0=>Data(8), DI1=>Data(9), WAD3=>wcount_3, + WAD2=>wcount_2, WAD1=>wcount_1, WAD0=>wcount_0, + WRE=>scuba_vhi, WPE=>wren_i, WCK=>Clock, RAD3=>rcount_3, + RAD2=>rcount_2, RAD1=>rcount_1, RAD0=>rcount_0, WDO0=>open, + WDO1=>open, RDO0=>rdataout8, RDO1=>rdataout9); + + fifo_pfu_0_6: DPR16X2 + -- synopsys translate_off + generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") + -- synopsys translate_on + port map (DI0=>Data(6), DI1=>Data(7), WAD3=>wcount_3, + WAD2=>wcount_2, WAD1=>wcount_1, WAD0=>wcount_0, + WRE=>scuba_vhi, WPE=>wren_i, WCK=>Clock, RAD3=>rcount_3, + RAD2=>rcount_2, RAD1=>rcount_1, RAD0=>rcount_0, WDO0=>open, + WDO1=>open, RDO0=>rdataout6, RDO1=>rdataout7); + + fifo_pfu_0_7: DPR16X2 + -- synopsys translate_off + generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") + -- synopsys translate_on + port map (DI0=>Data(4), DI1=>Data(5), WAD3=>wcount_3, + WAD2=>wcount_2, WAD1=>wcount_1, WAD0=>wcount_0, + WRE=>scuba_vhi, WPE=>wren_i, WCK=>Clock, RAD3=>rcount_3, + RAD2=>rcount_2, RAD1=>rcount_1, RAD0=>rcount_0, WDO0=>open, + WDO1=>open, RDO0=>rdataout4, RDO1=>rdataout5); + + fifo_pfu_0_8: DPR16X2 + -- synopsys translate_off + generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") + -- synopsys translate_on + port map (DI0=>Data(2), DI1=>Data(3), WAD3=>wcount_3, + WAD2=>wcount_2, WAD1=>wcount_1, WAD0=>wcount_0, + WRE=>scuba_vhi, WPE=>wren_i, WCK=>Clock, RAD3=>rcount_3, + RAD2=>rcount_2, RAD1=>rcount_1, RAD0=>rcount_0, WDO0=>open, + WDO1=>open, RDO0=>rdataout2, RDO1=>rdataout3); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + fifo_pfu_0_9: DPR16X2 + -- synopsys translate_off + generic map (GSR=> "ENABLED", initval=> "0x0000000000000000") + -- synopsys translate_on + port map (DI0=>Data(0), DI1=>Data(1), WAD3=>wcount_3, + WAD2=>wcount_2, WAD1=>wcount_1, WAD0=>wcount_0, + WRE=>scuba_vhi, WPE=>wren_i, WCK=>Clock, RAD3=>rcount_3, + RAD2=>rcount_2, RAD1=>rcount_1, RAD0=>rcount_0, WDO0=>open, + WDO1=>open, RDO0=>rdataout0, RDO1=>rdataout1); + + WCNT(0) <= fcount_0; + WCNT(1) <= fcount_1; + WCNT(2) <= fcount_2; + WCNT(3) <= fcount_3; + WCNT(4) <= fcount_4; + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library SCM; +configuration Structure_CON of fifo_19x16 is + for Structure + for all:DPR16X2 use entity SCM.DPR16X2(V); end for; + for all:ROM16X1 use entity SCM.ROM16X1(V); end for; + for all:AND2 use entity SCM.AND2(V); end for; + for all:XOR2 use entity SCM.XOR2(V); end for; + for all:INV use entity SCM.INV(V); end for; + for all:VHI use entity SCM.VHI(V); end for; + for all:VLO use entity SCM.VLO(V); end for; + for all:CU2 use entity SCM.CU2(V); end for; + for all:CB2 use entity SCM.CB2(V); end for; + for all:AGEB2 use entity SCM.AGEB2(V); end for; + for all:ALEB2 use entity SCM.ALEB2(V); end for; + for all:FD1P3DX use entity SCM.FD1P3DX(V); end for; + for all:FD1S3BX use entity SCM.FD1S3BX(V); end for; + for all:FD1S3DX use entity SCM.FD1S3DX(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/lattice/scm/lattice_ecp2m_fifo.vhd b/lattice/scm/lattice_ecp2m_fifo.vhd index a580566..f3a2c64 100644 --- a/lattice/scm/lattice_ecp2m_fifo.vhd +++ b/lattice/scm/lattice_ecp2m_fifo.vhd @@ -272,6 +272,18 @@ package lattice_ecp2m_fifo is AlmostFull: out std_logic); end component; - +component fifo_19x16 is + port ( + Data: in std_logic_vector(18 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(18 downto 0); + WCNT: out std_logic_vector(4 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end component; end package; \ No newline at end of file diff --git a/special/trb_net_bridge_pcie_endpoint_hub.vhd b/special/trb_net_bridge_pcie_endpoint_hub.vhd index 6f63ade..723df57 100644 --- a/special/trb_net_bridge_pcie_endpoint_hub.vhd +++ b/special/trb_net_bridge_pcie_endpoint_hub.vhd @@ -551,8 +551,9 @@ df_read(1) <= '1' when BUS_ADDR_IN(15 downto 0) = x"0e01" and bus_read_i = '1' e -------------------------------- debugfifo_read <= '1' when (bus_read_i='1' and BUS_ADDR_IN(15 downto 0) = x"0e0e") or debugfifo_full = '1' else '0'; -debugfifo_write <= '1' when (bus_read_i or bus_write_i) = '1' and BUS_ADDR_IN(11 downto 0) /= x"702" and BUS_ADDR_IN(11 downto 0) /= x"273" and BUS_ADDR_IN(11 downto 8) /= x"e" else '0'; -debugfifo_in <= bus_write_i & BUS_ADDR_IN(10 downto 0) & BUS_WDAT_IN(19 downto 0); +debugfifo_write <= '1' when (bus_read_last or bus_write_i) = '1' and BUS_ADDR_IN(11 downto 0) /= x"702" and BUS_ADDR_IN(11 downto 0) /= x"273" and BUS_ADDR_IN(11 downto 8) /= x"e" else '0'; +debugfifo_in <= bus_write_i & BUS_ADDR_IN(10 downto 8) & BUS_ADDR_IN(3 downto 0) & BUS_WDAT_IN(31 downto 28) & BUS_WDAT_IN(19 downto 0) when bus_write_i = '1' + else bus_write_i & BUS_ADDR_IN(10 downto 8) & BUS_ADDR_IN(3 downto 0) & bus_data_i(31 downto 28) & bus_data_i(19 downto 0); DEBUG_FIFO : fifo_32x512 port map( -- 2.43.0