From 426a663947a197856c15c80575ed8bb7c45278d4 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Mon, 21 Mar 2022 14:20:25 +0100 Subject: [PATCH] first 125MHz designs working --- backplanemaster/trb3sc_master.prj | 7 ++++-- backplanemaster/trb3sc_master.vhd | 10 ++++---- cts/trb3sc_cts.lpf | 39 +------------------------------ cts/trb3sc_cts.prj | 7 ++++-- cts/trb3sc_cts.vhd | 8 +++---- 5 files changed, 20 insertions(+), 51 deletions(-) diff --git a/backplanemaster/trb3sc_master.prj b/backplanemaster/trb3sc_master.prj index 3169f83..f10f3cb 100644 --- a/backplanemaster/trb3sc_master.prj +++ b/backplanemaster/trb3sc_master.prj @@ -133,8 +133,11 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vh add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_RS.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd" +#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_RS.vhd" +#add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd" + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_125M_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_125M_RS.vhd" #TrbNet Endpoint add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" diff --git a/backplanemaster/trb3sc_master.vhd b/backplanemaster/trb3sc_master.vhd index f0e25b9..4829506 100644 --- a/backplanemaster/trb3sc_master.vhd +++ b/backplanemaster/trb3sc_master.vhd @@ -228,14 +228,14 @@ THE_CLOCK_RESET : entity work.clock_reset_handler --------------------------------------------------------------------------- -- PCBSB: TrbNet Uplink --------------------------------------------------------------------------- -THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_all_RS +THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_all_125M_RS generic map( IS_MODE => (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_SLAVE), IS_WAP_ZERO => 1 ) port map( -- Clocks and reset - CLK_REF_FULL => clk_full_osc, + CLK_REF_FULL => CLK_SUPPL_PCLK, --clk_full_osc, SYSCLK => clk_sys, RESET => reset_i, -- Media Interface TX/RX @@ -319,7 +319,7 @@ THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_all_RS THE_MAIN_TX_RST: main_tx_reset_RS port map ( CLEAR => '0', - CLK_REF => clk_full_osc, + CLK_REF => CLK_SUPPL_PCLK, --clk_full_osc, TX_PLL_LOL_QD_A_IN => tx_pll_lol_qd_a_i, TX_PLL_LOL_QD_B_IN => tx_pll_lol_qd_b_i, TX_PLL_LOL_QD_C_IN => '0', @@ -334,14 +334,14 @@ THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_all_RS --------------------------------------------------------------------------- -- PCSA: TrbNet Downlink --------------------------------------------------------------------------- -THE_MEDIA_4_DOWN : entity work.med_ecp3_sfp_sync_all_RS +THE_MEDIA_4_DOWN : entity work.med_ecp3_sfp_sync_all_125M_RS generic map( IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_MASTER), IS_WAP_ZERO => 1 ) port map( -- Clocks and reset - CLK_REF_FULL => clk_full_osc, + CLK_REF_FULL => CLK_SUPPL_PCLK, --clk_full_osc, SYSCLK => clk_sys, RESET => reset_i, -- Media Interface TX/RX diff --git a/cts/trb3sc_cts.lpf b/cts/trb3sc_cts.lpf index 32d9c54..5deaf52 100644 --- a/cts/trb3sc_cts.lpf +++ b/cts/trb3sc_cts.lpf @@ -8,14 +8,10 @@ REGION "MEDIA_RIGHT" "R102C92D" 13 75; # RIGHT is for PCSA/PCSC LOCATE UGROUP "gen_PCSB.THE_MEDIA_PCSB/media_interface_group" REGION "MEDIA_LEFT"; # read from SCI can be delayed due to long read strobe -# write strobe can be delayed due to A/D being stable after access MULTICYCLE FROM ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; +# write strobe can be delayed due to A/D being stable after access MULTICYCLE TO ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns; -# SCI write signal problem... -#BLOCK NET gen_PCSB.THE_MEDIA_PCSB/sci_write_i; -#BLOCK INTERCLOCKDOMAIN PATHS; - ################################################################################################################### ################################################################################################################### #### OLD constraints @@ -28,37 +24,4 @@ FREQUENCY NET "GBE/clk_125_rx_from_pcs[3]" 125 MHz; PROHIBIT SECONDARY NET "THE_TOOLS/gen_STATISTICS.THE_STAT_LOGIC/reset_cnt" ; -### DUMPING AREA - -#MULTICYCLE TO CELL "gen_PCSB.THE_MEDIA_PCSB/sci*" 20 ns; -#MULTICYCLE FROM CELL "gen_PCSB.THE_MEDIA_PCSB/sci*" 20 ns; -#MULTICYCLE TO CELL "gen_PCSB.THE_MEDIA_PCSB/PROC_SCI_CTRL.wa*" 20 ns; -#BLOCK PATH TO CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_write_i"; -#BLOCK PATH FROM CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_write_i"; -#BLOCK PATH TO CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_read_i"; -#BLOCK PATH FROM CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_read_i"; - -#MULTICYCLE TO CELL "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci*" 20 ns; -#MULTICYCLE FROM CELL "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci*" 20 ns; -#MULTICYCLE TO CELL "gen_PCSB_ADDON.THE_MEDIA_PCSB/PROC_SCI_CTRL.wa*" 20 ns; -#BLOCK PATH TO CLKNET "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci_write_i"; -#BLOCK PATH FROM CLKNET "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci_write_i"; -#BLOCK PATH TO CLKNET "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci_read_i"; -#BLOCK PATH FROM CLKNET "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci_read_i"; - -#MULTICYCLE TO CELL "gen_PCSC.THE_MEDIA_PCSC/sci*" 20 ns; -#MULTICYCLE FROM CELL "gen_PCSC.THE_MEDIA_PCSC/sci*" 20 ns; -#MULTICYCLE TO CELL "gen_PCSC.THE_MEDIA_PCSC/PROC_SCI_CTRL.wa*" 20 ns; -#BLOCK PATH TO CLKNET "gen_PCSC.THE_MEDIA_PCSC/sci_write_i"; -#BLOCK PATH FROM CLKNET "gen_PCSC.THE_MEDIA_PCSC/sci_write_i"; -#BLOCK PATH TO CLKNET "gen_PCSC.THE_MEDIA_PCSC/sci_read_i"; -#BLOCK PATH FROM CLKNET "gen_PCSC.THE_MEDIA_PCSC/sci_read_i"; - -#MULTICYCLE TO ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; -#MAXDELAY TO ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; - -#MULTICYCLE TO ASIC gen_PCSB_ADDON.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; -#MAXDELAY TO ASIC gen_PCSB_ADDON.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; -#MULTICYCLE TO ASIC gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; -#MAXDELAY TO ASIC gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; diff --git a/cts/trb3sc_cts.prj b/cts/trb3sc_cts.prj index e271d83..a7a805f 100644 --- a/cts/trb3sc_cts.prj +++ b/cts/trb3sc_cts.prj @@ -136,8 +136,11 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vh add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_RS.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd" +#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_RS.vhd" +#add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd" + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_125M_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_125M_RS.vhd" #TrbNet Endpoint add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd index 60c8e0c..2d5924f 100644 --- a/cts/trb3sc_cts.vhd +++ b/cts/trb3sc_cts.vhd @@ -354,14 +354,14 @@ THE_CLOCK_RESET : entity work.clock_reset_handler -- PCSB: Downlink without backplane is SFP --------------------------------------------------------------------------- gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate - THE_MEDIA_PCSB : entity med_ecp3_sfp_sync_all_RS + THE_MEDIA_PCSB : entity med_ecp3_sfp_sync_all_125M_RS generic map( IS_MODE => (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_MASTER), IS_WAP_ZERO => 1 ) port map( -- Clocks and reset - CLK_REF_FULL => clk_full_osc, + CLK_REF_FULL => CLK_SUPPL_PCLK, --clk_full_osc, SYSCLK => clk_sys, RESET => reset_i, -- check -- Media Interface TX/RX @@ -425,12 +425,12 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate DEBUG_OUT => debug_i ); - master_clk_i <= clk_full_osc; + master_clk_i <= CLK_SUPPL_PCLK; --clk_full_osc; THE_MAIN_TX_RST: main_tx_reset_RS port map ( CLEAR => '0', - CLK_REF => clk_full_osc, + CLK_REF => CLK_SUPPL_PCLK, --clk_full_osc, TX_PLL_LOL_QD_A_IN => '0', TX_PLL_LOL_QD_B_IN => tx_pll_lol_qd_b_i, TX_PLL_LOL_QD_C_IN => '0', -- 2.43.0