From 429d74c80c756c5c085de4a5e17fee47319a249f Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 6 Jan 2016 16:55:55 +0100 Subject: [PATCH] More DiRich files --- code/clock_reset_handler.vhd | 123 +++++++++ cores/pll_240_100/pll_240_100.fdc | 2 + cores/pll_240_100/pll_240_100.lpc | 93 +++++++ cores/pll_240_100/pll_240_100.sbx | 430 ++++++++++++++++++++++++++++++ cores/pll_240_100/pll_240_100.vhd | 86 ++++++ dirich/dirich.ldf | 107 +++++++- dirich/dirich.prj | 91 +++---- dirich/dirich.vhd | 128 ++++----- pinout/combiner.lpf | 0 pinout/dirich.lpf | 0 10 files changed, 930 insertions(+), 130 deletions(-) create mode 100644 code/clock_reset_handler.vhd create mode 100644 cores/pll_240_100/pll_240_100.fdc create mode 100644 cores/pll_240_100/pll_240_100.lpc create mode 100644 cores/pll_240_100/pll_240_100.sbx create mode 100644 cores/pll_240_100/pll_240_100.vhd create mode 100644 pinout/combiner.lpf create mode 100644 pinout/dirich.lpf diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd new file mode 100644 index 0000000..f2e50e9 --- /dev/null +++ b/code/clock_reset_handler.vhd @@ -0,0 +1,123 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.trb_net_components.all; + use work.trb_net_std.all; + use work.trb3_components.all; + use work.config.all; + +entity clock_reset_handler is + port ( + CLOCK_IN : in std_logic; -- oscillator + RESET_FROM_NET : in std_logic; + + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX; + + RESET_OUT : out std_logic; + CLEAR_OUT : out std_logic; + GSR_OUT : out std_logic; + + RAW_CLK_OUT : out std_logic; -- 200/240 MHz for FPGA fabric + SYS_CLK_OUT : out std_logic; -- 100/120 MHz for FPGA fabric + REF_CLK_OUT : out std_logic; -- 200/240 internal reference clock + + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end entity; + +architecture clock_reset_handler_arch of clock_reset_handler is + +attribute syn_keep : boolean; +attribute syn_preserve : boolean; +signal clock_100, clock_120, clock_200, clock_240: std_logic; +signal sys_clk_i : std_logic; +signal timer : unsigned(16 downto 0) := (others => '0'); +signal clear_n_i : std_logic := '0'; +signal reset_i : std_logic; + +signal pll_lock : std_logic; + +attribute syn_keep of clear_n_i : signal is true; +attribute syn_preserve of clear_n_i : signal is true; + +begin + + +SYS_CLK_OUT <= sys_clk_i; +GSR_OUT <= not pll_lock or clear_n_i; + +THE_PLL : entity work.pll_240_100 + port map( + CLKI => CLOCK_IN, + CLKOP => clock_200, + CLKOS => clock_100, + CLKOS2 => clock_240, + CLKOS3 => clock_120, + LOCK => pll_lock + ); + +gen_slow_clock : if USE_120_MHZ = 0 generate + RAW_CLK_OUT <= clock_240; + sys_clk_i <= clock_100; + REF_CLK_OUT <= clock_200; +end generate; +gen_fast_clock : if USE_120_MHZ = 1 generate + RAW_CLK_OUT <= clock_240; + sys_clk_i <= clock_120; + REF_CLK_OUT <= clock_240; +end generate; + + +clear_n_i <= timer(16) when rising_edge(CLOCK_IN); + +process begin + wait until rising_edge(sys_clk_i); + if timer(16) = '1' then + timer <= timer; + else + timer <= timer + 1; + end if; +end process; + + +--------------------------------------------------------------------------- +-- Reset generation +--------------------------------------------------------------------------- +THE_RESET_HANDLER : trb_net_reset_handler + generic map( + RESET_DELAY => x"FEEE" + ) + port map( + CLEAR_IN => '0', -- reset input (high active, async) + CLEAR_N_IN => clear_n_i, -- reset input (low active, async) + CLK_IN => clock_240, -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN => sys_clk_i, -- PLL/DLL remastered clock + PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) + RESET_IN => '0', -- general reset signal (SYSCLK) + TRB_RESET_IN => RESET_FROM_NET, -- TRBnet reset signal (SYSCLK) + CLEAR_OUT => CLEAR_OUT, -- async reset out, USE WITH CARE! + RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) + DEBUG_OUT => open + ); + +RESET_OUT <= reset_i; + + +--------------------------------------------------------------------------- +-- Slow clock for DCDC converters +--------------------------------------------------------------------------- +DEBUG_OUT(0) <= pll_lock; +DEBUG_OUT(1) <= clear_n_i; +DEBUG_OUT(31 downto 2) <= (others => '0'); + +BUS_TX.data <= (others => '0'); +BUS_TX.unknown <= '1'; +BUS_TX.ack <= '0'; +BUS_TX.nack <= '0'; + + + +end architecture; \ No newline at end of file diff --git a/cores/pll_240_100/pll_240_100.fdc b/cores/pll_240_100/pll_240_100.fdc new file mode 100644 index 0000000..6fbcac9 --- /dev/null +++ b/cores/pll_240_100/pll_240_100.fdc @@ -0,0 +1,2 @@ +###==== Start Configuration + diff --git a/cores/pll_240_100/pll_240_100.lpc b/cores/pll_240_100/pll_240_100.lpc new file mode 100644 index 0000000..dafb638 --- /dev/null +++ b/cores/pll_240_100/pll_240_100.lpc @@ -0,0 +1,93 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG381C +SpeedGrade=8 +Package=CABGA381 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.8 +ModuleName=pll_240_100 +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=01/06/2016 +Time=14:19:48 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +CLKI_FREQ=240 +CLKI_DIV=6 +ENABLE_HBW=DISABLED +REFERENCE=0 +IOBUF=LVDS +CLKOP_FREQ=200 +CLKOP_TOL=0.0 +CLKOP_DIV=3 +CLKOP_ACTUAL_FREQ=200.000000 +CLKOP_MUXA=DISABLED +CLKOS_Enable=ENABLED +CLKOS_FREQ=100.00 +CLKOS_TOL=0.0 +CLKOS_DIV=6 +CLKOS_ACTUAL_FREQ=100.000000 +CLKOS_MUXB=DISABLED +CLKOS2_Enable=ENABLED +CLKOS2_FREQ=100.00 +CLKOS2_TOL=0.0 +CLKOS2_DIV=1 +CLKOS2_ACTUAL_FREQ=240.000000 +CLKOS2_MUXC=ENABLED +CLKOS3_Enable=ENABLED +CLKOS3_FREQ=120.00 +CLKOS3_TOL=0.0 +CLKOS3_DIV=5 +CLKOS3_ACTUAL_FREQ=120.000000 +CLKOS3_MUXD=DISABLED +FEEDBK_PATH=CLKOP +CLKFB_DIV=5 +FRACN_ENABLE=DISABLED +FRACN_DIV= +VCO_RATE=600.000 +PLL_BW=4.966 +CLKOP_DPHASE=0 +CLKOP_APHASE=0.00 +CLKOP_TRIM_POL=Rising +CLKOP_TRIM_DELAY=0 +CLKOS_DPHASE=0 +CLKOS_APHASE=0.00 +CLKOS_TRIM_POL=Rising +CLKOS_TRIM_DELAY=0 +CLKOS2_DPHASE=0 +CLKOS2_APHASE=0.00 +CLKOS2_TRIM_POL=Rising +CLKOS2_TRIM_DELAY=0 +CLKOS3_DPHASE=0 +CLKOS3_APHASE=0.00 +CLKOS3_TRIM_POL=Rising +CLKOS3_TRIM_DELAY=0 +CLKSEL_ENA=DISABLED +DPHASE_SOURCE=STATIC +ENABLE_CLKOP=DISABLED +ENABLE_CLKOS=DISABLED +ENABLE_CLKOS2=DISABLED +ENABLE_CLKOS3=DISABLED +STDBY_ENABLE=DISABLED +PLLRST_ENA=DISABLED +PLL_LOCK_MODE=ENABLED +PLL_LOCK_STK=DISABLED +PLL_USE_SMI=DISABLED + +[Command] +cmd_line= -w -n pll_240_100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 240 -fclkop 200 -fclkop_tol 0.0 -fclkos 100.00 -fclkos_tol 0.0 -phases 0 -bypass_divs2 -fclkos3 120.00 -fclkos3_tol 0.0 -phases3 0 -phase_cntl STATIC -lock -fb_mode 1 diff --git a/cores/pll_240_100/pll_240_100.sbx b/cores/pll_240_100/pll_240_100.sbx new file mode 100644 index 0000000..7161108 --- /dev/null +++ b/cores/pll_240_100/pll_240_100.sbx @@ -0,0 +1,430 @@ + + + + Lattice Semiconductor Corporation + LEGACY + PLL + 5.8 + + + Diamond_Simulation + simulation + + ./pll_240_100.vhd + vhdlSource + + + + Diamond_Synthesis + synthesis + + ./pll_240_100.vhd + vhdlSource + + + + + + Configuration + none + ${sbp_path}/generate_core.tcl + CONFIG + + + Generation + none + ${sbp_path}/${instance}/generate_core.tcl + GENERATE + + + + + + + + LFE5UM-85F-8BG381C + synplify + 2016-01-06.11:38:14 AM + 2016-01-06.02:19:54 PM + 3.6.0.83.4 + VHDL + + false + false + false + false + false + false + false + false + false + false + LPM + PRIMARY + PRIMARY + false + false + + + + + + Family + ecp5um + + + OperatingCondition + COM + + + Package + CABGA381 + + + PartName + LFE5UM-85F-8BG381C + + + PartType + LFE5UM-85F + + + SpeedGrade + 8 + + + Status + P + + + + CoreName + PLL + + + CoreRevision + 5.8 + + + CoreStatus + Demo + + + CoreType + LPM + + + Date + 01/06/2016 + + + ModuleName + pll_240_100 + + + ParameterFileVersion + 1.0 + + + SourceFormat + vhdl + + + Time + 14:19:48 + + + VendorName + Lattice Semiconductor Corporation + + + + CLKFB_DIV + 5 + + + CLKI_DIV + 6 + + + CLKI_FREQ + 240 + + + CLKOP_ACTUAL_FREQ + 200.000000 + + + CLKOP_APHASE + 0.00 + + + CLKOP_DIV + 3 + + + CLKOP_DPHASE + 0 + + + CLKOP_FREQ + 200 + + + CLKOP_MUXA + DISABLED + + + CLKOP_TOL + 0.0 + + + CLKOP_TRIM_DELAY + 0 + + + CLKOP_TRIM_POL + Rising + + + CLKOS2_ACTUAL_FREQ + 240.000000 + + + CLKOS2_APHASE + 0.00 + + + CLKOS2_DIV + 1 + + + CLKOS2_DPHASE + 0 + + + CLKOS2_Enable + ENABLED + + + CLKOS2_FREQ + 100.00 + + + CLKOS2_MUXC + ENABLED + + + CLKOS2_TOL + 0.0 + + + CLKOS2_TRIM_DELAY + 0 + + + CLKOS2_TRIM_POL + Rising + + + CLKOS3_ACTUAL_FREQ + 120.000000 + + + CLKOS3_APHASE + 0.00 + + + CLKOS3_DIV + 5 + + + CLKOS3_DPHASE + 0 + + + CLKOS3_Enable + ENABLED + + + CLKOS3_FREQ + 120.00 + + + CLKOS3_MUXD + DISABLED + + + CLKOS3_TOL + 0.0 + + + CLKOS3_TRIM_DELAY + 0 + + + CLKOS3_TRIM_POL + Rising + + + CLKOS_ACTUAL_FREQ + 100.000000 + + + CLKOS_APHASE + 0.00 + + + CLKOS_DIV + 6 + + + CLKOS_DPHASE + 0 + + + CLKOS_Enable + ENABLED + + + CLKOS_FREQ + 100.00 + + + CLKOS_MUXB + DISABLED + + + CLKOS_TOL + 0.0 + + + CLKOS_TRIM_DELAY + 0 + + + CLKOS_TRIM_POL + Rising + + + CLKSEL_ENA + DISABLED + + + DPHASE_SOURCE + STATIC + + + Destination + Synplicity + + + EDIF + 1 + + + ENABLE_CLKOP + DISABLED + + + ENABLE_CLKOS + DISABLED + + + ENABLE_CLKOS2 + DISABLED + + + ENABLE_CLKOS3 + DISABLED + + + ENABLE_HBW + DISABLED + + + Expression + BusA(0 to 7) + + + FEEDBK_PATH + CLKOP + + + FRACN_DIV + + + + FRACN_ENABLE + DISABLED + + + IO + 0 + + + IOBUF + LVDS + + + Order + Big Endian [MSB:LSB] + + + PLLRST_ENA + DISABLED + + + PLL_BW + 4.966 + + + PLL_LOCK_MODE + ENABLED + + + PLL_LOCK_STK + DISABLED + + + PLL_USE_SMI + DISABLED + + + REFERENCE + 0 + + + STDBY_ENABLE + DISABLED + + + VCO_RATE + 600.000 + + + VHDL + 1 + + + Verilog + 0 + + + + cmd_line + -w -n pll_240_100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 240 -fclkop 200 -fclkop_tol 0.0 -fclkos 100.00 -fclkos_tol 0.0 -phases 0 -bypass_divs2 -fclkos3 120.00 -fclkos3_tol 0.0 -phases3 0 -phase_cntl STATIC -lock -fb_mode 1 + + + + + + + LATTICE + LOCAL + pll_240_100 + 1.0 + + + + diff --git a/cores/pll_240_100/pll_240_100.vhd b/cores/pll_240_100/pll_240_100.vhd new file mode 100644 index 0000000..dfc5aa1 --- /dev/null +++ b/cores/pll_240_100/pll_240_100.vhd @@ -0,0 +1,86 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.6.0.83.4 +-- Module Version: 5.7 +--/d/jspc29/lattice/diamond/3.6_x64/ispfpga/bin/lin64/scuba -w -n pll_240_100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 240 -fclkop 200 -fclkop_tol 0.0 -fclkos 100.00 -fclkos_tol 0.0 -phases 0 -bypass_divs2 -fclkos3 120.00 -fclkos3_tol 0.0 -phases3 0 -phase_cntl STATIC -lock -fb_mode 1 -fdc /d/jspc22/trb/git/dirich/cores/pll_240_100/pll_240_100.fdc + +-- Wed Jan 6 14:19:54 2016 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity pll_240_100 is + port ( + CLKI: in std_logic; + CLKOP: out std_logic; + CLKOS: out std_logic; + CLKOS2: out std_logic; + CLKOS3: out std_logic; + LOCK: out std_logic); +end pll_240_100; + +architecture Structure of pll_240_100 is + + -- internal signal declarations + signal REFCLK: std_logic; + signal CLKOS3_t: std_logic; + signal CLKOS2_t: std_logic; + signal CLKOS_t: std_logic; + signal CLKOP_t: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + attribute FREQUENCY_PIN_CLKOS3 : string; + attribute FREQUENCY_PIN_CLKOS2 : string; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute ICP_CURRENT : string; + attribute LPF_RESISTOR : string; + attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "120.000000"; + attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "240.000000"; + attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "100.000000"; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "200.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "240.000000"; + attribute ICP_CURRENT of PLLInst_0 : label is "12"; + attribute LPF_RESISTOR of PLLInst_0 : label is "8"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLL + generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", + STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", + CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 4, CLKOS2_FPHASE=> 0, + CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 5, + CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 2, PLL_LOCK_MODE=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", + OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "ENABLED", + OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "ENABLED", + OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "ENABLED", + OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 5, + CLKOS2_DIV=> 1, CLKOS_DIV=> 6, CLKOP_DIV=> 3, CLKFB_DIV=> 5, + CLKI_DIV=> 6, FEEDBK_PATH=> "CLKOP") + port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, + PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, + PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, + STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, + ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, + ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, + CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>LOCK, + INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open); + + CLKOS3 <= CLKOS3_t; + CLKOS2 <= CLKOS2_t; + CLKOS <= CLKOS_t; + CLKOP <= CLKOP_t; +end Structure; diff --git a/dirich/dirich.ldf b/dirich/dirich.ldf index 8f55851..b78c545 100644 --- a/dirich/dirich.ldf +++ b/dirich/dirich.ldf @@ -2,10 +2,105 @@ - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/dirich/dirich.prj b/dirich/dirich.prj index 1ae35c2..08ab870 100644 --- a/dirich/dirich.prj +++ b/dirich/dirich.prj @@ -3,16 +3,16 @@ impl -add workdir -type fpga # device options -set_option -technology LATTICE-ECP3 -set_option -part LFE3_150EA -set_option -package FN1156C +set_option -technology ECP5UM +set_option -part LFE5UM_85F +set_option -package BG381C set_option -speed_grade -8 set_option -part_companion "" # compilation/mapping options set_option -default_enum_encoding sequential set_option -symbolic_fsm_compiler 1 -set_option -top_module "trb3sc_basic" +set_option -top_module "dirich" set_option -resource_sharing false # map options @@ -21,10 +21,11 @@ set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -retiming 1 set_option -pipe 1 -set_option -force_gsr false +set_option -forcegsr false set_option -fixgatedclocks 3 set_option -fixgeneratedclocks 3 set_option -compiler_compatible true +set_option -multi_file_compilation_unit 1 set_option -max_parallel_jobs 3 #set_option -automatic_compile_point 1 @@ -40,8 +41,8 @@ set_option -write_apr_constraint 0 # set result format/file last project -result_format "edif" -project -result_file "workdir/trb3sc_basic.edf" - +project -result_file "workdir/dirich.edf" +set_option log_file "workdir/dirich_project.srf" #implementation attributes set_option -vlog_std v2001 @@ -57,47 +58,41 @@ add_file -vhdl -lib work "workdir/version.vhd" add_file -vhdl -lib work "config.vhd" add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" -add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_protocols.vhd" -add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_components.vhd" #Basic Infrastructure -add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd" -add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd" -add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd" -add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd" -add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../cores/pll_240_100/pll_240_100.vhd" +add_file -vhdl -lib work "../code/clock_reset_handler.vhd" add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd" #Fifos -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.vhd" #Flash & Reload, Tools @@ -115,7 +110,7 @@ add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" -add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" #SlowControl files @@ -127,15 +122,15 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" #Media interface add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0/serdes_sync_0.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd" +# add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd" #TrbNet Endpoint add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" @@ -182,7 +177,7 @@ add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" -add_file -vhdl -lib work "./trb3sc_basic.vhd" +add_file -vhdl -lib work "./dirich.vhd" #add_file -fpga_constraint "./synplify.fdc" diff --git a/dirich/dirich.vhd b/dirich/dirich.vhd index 5c3881c..cd7f5f5 100644 --- a/dirich/dirich.vhd +++ b/dirich/dirich.vhd @@ -11,7 +11,7 @@ use work.trb3_components.all; use work.version.all; use work.med_sync_define.all; -entity trb3sc_basic is +entity dirich is port( CLOCK_IN : in std_logic; --Main Oscillator TRIG_IN : in std_logic; --Reference Time @@ -41,7 +41,7 @@ entity trb3sc_basic is TEMPSENS : inout std_logic; --Test Connectors - TEST_LINE : out std_logic_vector(15 downto 0) + TEST_LINE : out std_logic_vector(13 downto 0) ); @@ -60,7 +60,7 @@ entity trb3sc_basic is end entity; -architecture trb3sc_arch of trb3sc_basic is +architecture dirich_arch of dirich is attribute syn_keep : boolean; attribute syn_preserve : boolean; @@ -70,7 +70,6 @@ architecture trb3sc_arch of trb3sc_basic is signal clear_i : std_logic; signal time_counter : unsigned(31 downto 0) := (others => '0'); - signal led : std_logic_vector(1 downto 0); signal debug_clock_reset : std_logic_vector(31 downto 0); signal debug_tools : std_logic_vector(31 downto 0); @@ -78,7 +77,7 @@ architecture trb3sc_arch of trb3sc_basic is signal med2int : med2int_array_t(0 to 0); signal int2med : int2med_array_t(0 to 0); signal med_stat_debug : std_logic_vector (1*64-1 downto 0); - + signal link_stat_in, link_stat_out : std_logic; --READOUT signal readout_rx : READOUT_RX; signal readout_tx : readout_tx_array_t(0 to 0); @@ -97,18 +96,11 @@ architecture trb3sc_arch of trb3sc_basic is signal timer : TIMERS; signal lcd_data : std_logic_vector(511 downto 0); + signal hdr_io : std_logic_vector(9 downto 0); - signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; - attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; - attribute syn_keep of bussci_rx : signal is true; - attribute syn_preserve of bussci_rx : signal is true; - attribute syn_keep of bustools_rx : signal is true; - attribute syn_preserve of bustools_rx : signal is true; - attribute syn_keep of bustc_rx : signal is true; - attribute syn_preserve of bustc_rx : signal is true; - + begin --------------------------------------------------------------------------- @@ -116,10 +108,7 @@ begin --------------------------------------------------------------------------- THE_CLOCK_RESET : entity work.clock_reset_handler port map( - INT_CLK_IN => CLK_CORE_PCLK, - EXT_CLK_IN => CLK_EXT_PLL_LEFT, - NET_CLK_FULL_IN => med2int(0).clk_full, - NET_CLK_HALF_IN => med2int(0).clk_half, + CLOCK_IN => CLOCK_IN, RESET_FROM_NET => med2int(0).stat_op(13), BUS_RX => bustc_rx, @@ -129,13 +118,10 @@ THE_CLOCK_RESET : entity work.clock_reset_handler CLEAR_OUT => clear_i, GSR_OUT => GSR_N, - FULL_CLK_OUT => clk_full, + REF_CLK_OUT => clk_full, SYS_CLK_OUT => clk_sys, - REF_CLK_OUT => clk_full_osc, + RAW_CLK_OUT => clk_full_osc, - ENPIRION_CLOCK => open, - LED_RED_OUT => open, - LED_GREEN_OUT => open, DEBUG_OUT => debug_clock_reset ); @@ -144,53 +130,42 @@ THE_CLOCK_RESET : entity work.clock_reset_handler -- TrbNet Uplink --------------------------------------------------------------------------- - THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync - generic map( - SERDES_NUM => 0, - IS_SYNC_SLAVE => c_YES - ) - port map( - CLK_REF_FULL => med2int(0).clk_full, - CLK_INTERNAL_FULL => clk_full_osc, - SYSCLK => clk_sys, - RESET => reset_i, - CLEAR => clear_i, - --Internal Connection - MEDIA_MED2INT => med2int(0), - MEDIA_INT2MED => int2med(0), - - --Sync operation - RX_DLM => open, - RX_DLM_WORD => open, - TX_DLM => open, - TX_DLM_WORD => open, - - --SFP Connection - SD_REFCLK_P_IN => '0', - SD_REFCLK_N_IN => '0', - SD_PRSNT_N_IN => sfp_prsnt_i, - SD_LOS_IN => sfp_los_i, - SD_TXDIS_OUT => sfp_txdis_i, - --Control Interface - BUS_RX => bussci_rx, - BUS_TX => bussci_tx, - -- Status and control port - STAT_DEBUG => med_stat_debug(63 downto 0), - CTRL_DEBUG => open - ); - - SFP_TX_DIS(0) <= '1'; - gen_sfp_con : if SERDES_NUM = 3 generate - sfp_los_i <= SFP_LOS(1); - sfp_prsnt_i <= SFP_MOD0(1); - SFP_TX_DIS(1) <= sfp_txdis_i; - end generate; - gen_bpl_con : if SERDES_NUM = 0 generate - sfp_los_i <= BACK_GPIO(1); - sfp_prsnt_i <= BACK_GPIO(1); - BACK_GPIO(0) <= sfp_txdis_i; - end generate; - +-- THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync +-- generic map( +-- SERDES_NUM => 0, +-- IS_SYNC_SLAVE => c_YES +-- ) +-- port map( +-- CLK_REF_FULL => med2int(0).clk_full, +-- CLK_INTERNAL_FULL => clk_full_osc, +-- SYSCLK => clk_sys, +-- RESET => reset_i, +-- CLEAR => clear_i, +-- --Internal Connection +-- MEDIA_MED2INT => med2int(0), +-- MEDIA_INT2MED => int2med(0), +-- +-- --Sync operation +-- RX_DLM => open, +-- RX_DLM_WORD => open, +-- TX_DLM => open, +-- TX_DLM_WORD => open, +-- +-- --SFP Connection +-- SD_PRSNT_N_IN => link_stat_in, +-- SD_LOS_IN => link_stat_in, +-- SD_TXDIS_OUT => link_stat_out, +-- --Control Interface +-- BUS_RX => bussci_rx, +-- BUS_TX => bussci_tx, +-- -- Status and control port +-- STAT_DEBUG => med_stat_debug(63 downto 0), +-- CTRL_DEBUG => open +-- ); + +CTRL(2) <= '0' when link_stat_out = '1' else 'Z'; +link_stat_in <= CTRL(2); + --------------------------------------------------------------------------- -- Endpoint --------------------------------------------------------------------------- @@ -221,7 +196,7 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record MEDIA_INT2MED => int2med(0), --Timing trigger in - TRG_TIMING_TRG_RECEIVED_IN => TRIG_LEFT, + TRG_TIMING_TRG_RECEIVED_IN => TRIG_IN, READOUT_RX => readout_rx, READOUT_TX => readout_tx, @@ -285,12 +260,12 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record PROGRAMN => PROGRAMN, REBOOT_IN => common_ctrl_reg(15), --SPI - SPI_CS_OUT => spi_cs, - SPI_MOSI_OUT=> spi_mosi, - SPI_MISO_IN => spi_miso, - SPI_CLK_OUT => spi_clk, + SPI_CS_OUT => open, + SPI_MOSI_OUT=> open, + SPI_MISO_IN => open, + SPI_CLK_OUT => open, --Header - HEADER_IO => HDR_IO, + HEADER_IO => hdr_io, --LCD LCD_DATA_IN => lcd_data, --ADC @@ -320,6 +295,7 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record -- I/O --------------------------------------------------------------------------- + TEST_LINE(9 downto 0) <= hdr_io; --------------------------------------------------------------------------- -- LCD Data to display diff --git a/pinout/combiner.lpf b/pinout/combiner.lpf new file mode 100644 index 0000000..e69de29 diff --git a/pinout/dirich.lpf b/pinout/dirich.lpf new file mode 100644 index 0000000..e69de29 -- 2.43.0