From 42bd89377fd62b8f6de0e5b94834e16a72f78e3c Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Fri, 17 Aug 2012 09:50:17 +0000 Subject: [PATCH] *** empty log message *** --- base/code/adc_ad9222.vhd | 183 ++++++++ base/cores/dqsinput.ipx | 8 + base/cores/dqsinput.lpc | 60 +++ base/cores/dqsinput.vhd | 453 +++++++++++++++++++ base/cores/fifo_32x512.ipx | 9 + base/cores/fifo_32x512.lpc | 45 ++ base/cores/fifo_32x512.vhd | 651 +++++++++++++++++++++++++++ base/cores/fifo_cdt_20.ipx | 9 + base/cores/fifo_cdt_20.lpc | 47 ++ base/cores/fifo_cdt_20.vhd | 746 +++++++++++++++++++++++++++++++ base/cores/fifo_cdt_200.ipx | 9 + base/cores/fifo_cdt_200.lpc | 47 ++ base/cores/fifo_cdt_200.vhd | 783 +++++++++++++++++++++++++++++++++ base/cores/pll_adc12bit.ipx | 8 + base/cores/pll_adc12bit.lpc | 66 +++ base/cores/pll_adc12bit.vhd | 104 +++++ base/trb3_components.vhd | 71 +++ base/trb3_periph_ada.lpf | 4 +- base/trb3_periph_multitest.lpf | 24 +- 19 files changed, 3316 insertions(+), 11 deletions(-) create mode 100644 base/code/adc_ad9222.vhd create mode 100644 base/cores/dqsinput.ipx create mode 100644 base/cores/dqsinput.lpc create mode 100644 base/cores/dqsinput.vhd create mode 100644 base/cores/fifo_32x512.ipx create mode 100644 base/cores/fifo_32x512.lpc create mode 100644 base/cores/fifo_32x512.vhd create mode 100644 base/cores/fifo_cdt_20.ipx create mode 100644 base/cores/fifo_cdt_20.lpc create mode 100644 base/cores/fifo_cdt_20.vhd create mode 100644 base/cores/fifo_cdt_200.ipx create mode 100644 base/cores/fifo_cdt_200.lpc create mode 100644 base/cores/fifo_cdt_200.vhd create mode 100644 base/cores/pll_adc12bit.ipx create mode 100644 base/cores/pll_adc12bit.lpc create mode 100644 base/cores/pll_adc12bit.vhd diff --git a/base/code/adc_ad9222.vhd b/base/code/adc_ad9222.vhd new file mode 100644 index 0000000..5972cae --- /dev/null +++ b/base/code/adc_ad9222.vhd @@ -0,0 +1,183 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb3_components.all; + + +entity adc_ad9222 is + generic( + CHANNELS : integer range 4 to 4 := 4; + DEVICES : integer range 2 to 2 := 2; + RESOLUTION : integer range 12 to 12 := 12 + ); + port( + CLK : in std_logic; + CLK_ADCREF : in std_logic; + CLK_ADCDAT : in std_logic; + RESTART_IN : in std_logic; + ADCCLK_OUT : out std_logic; + ADC_DATA : in std_logic_vector(DEVICES*CHANNELS-1 downto 0); + ADC_DCO : in std_logic_vector(DEVICES-1 downto 0); + ADC_FCO : in std_logic_vector(DEVICES-1 downto 0); + + DATA_OUT : out std_logic_vector(DEVICES*CHANNELS*RESOLUTION-1 downto 0); + FCO_OUT : out std_logic_vector(DEVICES*RESOLUTION-1 downto 0); + DATA_VALID_OUT : out std_logic_vector(DEVICES-1 downto 0); + DEBUG : out std_logic_vector(31 downto 0) + ); +end entity; + + + +architecture adc_ad9222_arch of adc_ad9222 is + + +signal clk_data : std_logic; + +signal data_in : std_logic_vector(39 downto 0); +signal data_int : std_logic_vector(39 downto 0); +signal fifo_empty : std_logic_vector(1 downto 0); +signal fifo_full : std_logic_vector(1 downto 0); +signal valid_read : std_logic_vector(1 downto 0); + +type cdt_t is array(0 to DEVICES-1) of std_logic_vector(59 downto 0); +signal cdt_data_in : cdt_t; +signal cdt_data_out: cdt_t; +signal cdt_write : std_logic_vector(DEVICES-1 downto 0); + +type datarr_sub_t is array(0 to CHANNELS) of std_logic_vector(3 downto 0); +type datarr_t is array(0 to DEVICES-1) of datarr_sub_t; +signal data_block : datarr_t; + +type dat_final_subt is array(0 to CHANNELS) of std_logic_vector(RESOLUTION-1 downto 0); +type dat_final_t is array(0 to DEVICES-1) of dat_final_subt; +signal last_data : dat_final_t; +signal curr_data : dat_final_t; + +type arr_4DEV_t is array(0 to DEVICES-1) of std_logic_vector(3 downto 0); +signal mask : arr_4DEV_t; + + +type state_t is array(0 to DEVICES-1) of integer range 0 to 3; +signal state : state_t := (others => 0); + +signal data_buffer : std_logic_vector(DEVICES*CHANNELS*RESOLUTION-1 downto 0); +signal fco_buffer : std_logic_vector(DEVICES*RESOLUTION-1 downto 0); +signal data_ready : std_logic_vector(DEVICES-1 downto 0); +signal restart_i : std_logic; + +begin + + ADCCLK_OUT <= CLK_ADCREF; + restart_i <= RESTART_IN when rising_edge(clk_data); + + THE_INPUT : dqsinput + port map( + clk_0 => ADC_DCO(0), + clk_1 => ADC_DCO(1), + clkdiv_reset => '0', + eclk => CLK_ADCDAT, + reset_0 => '0', + reset_1 => '0', + sclk => clk_data, + datain_0(3 downto 0) => ADC_DATA(3 downto 0), + datain_1(3 downto 0) => ADC_DATA(7 downto 4), + datain_0(4) => ADC_FCO(0), + datain_1(4) => ADC_FCO(1), + q_0 => data_in(19 downto 0), + q_1 => data_in(39 downto 20) + ); + + gen_chips : for i in 0 to 1 generate + THE_FIFO : fifo_cdt_200 + port map( + Data => cdt_data_in(i), + WrClock => clk_data, + RdClock => CLK, + WrEn => cdt_write(i), + RdEn => '1', + Reset => '0', + RPReset => restart_i, + Q => cdt_data_out(i), + Empty => fifo_empty(i), + Full => fifo_full(i) + ); + + valid_read(i) <= not fifo_empty(i) when rising_edge(CLK); + + gen_data_mapping : for j in 0 to CHANNELS generate + gen_data_mapping_bits : for k in 0 to 3 generate + data_block(i)(j)(3-k) <= data_in(i*(CHANNELS+1)*4+k*(CHANNELS+1)+j); + end generate; + end generate; + + + process begin + wait until rising_edge(clk_data); + cdt_write(i) <= '0'; + case state(i) is + when 0 => + if data_block(i)(CHANNELS) = x"F" then + state(i) <= 2; + end if; + when 1 => + loop_chan_0 : for j in 0 to CHANNELS loop + cdt_data_in(i)(j*12+11 downto j*12+8) <= data_block(i)(j); + end loop; + state(i) <= 2; + when 2 => + loop_chan_1 : for j in 0 to CHANNELS loop + cdt_data_in(i)(j*12+7 downto j*12+4) <= data_block(i)(j); + end loop; + state(i) <= 3; + when 3 => + loop_chan_2 : for j in 0 to CHANNELS loop + cdt_data_in(i)(j*12+3 downto j*12+0) <= data_block(i)(j); + end loop; + cdt_write(i) <= '1'; + state(i) <= 1; + end case; + if restart_i = '1' then + state(i) <= 0; + end if; + end process; + + + end generate; + + gen_shift_bits : for i in 0 to DEVICES-1 generate + mask(i) <= cdt_data_out(i)(CHANNELS*12+3 downto CHANNELS*12); + gen_shift_bits_2 : for j in 0 to CHANNELS-1 generate + + curr_data(i)(j) <= cdt_data_out(i)(j*12+11 downto j*12); + + process begin + wait until rising_edge(CLK); + if valid_read(i) = '1' then + if mask(i) = x"3" then + data_buffer(i*RESOLUTION*CHANNELS+(j+1)*RESOLUTION-1 downto i*RESOLUTION*CHANNELS+j*RESOLUTION) <= last_data(i)(j)(1 downto 0) & curr_data(i)(j)(RESOLUTION-1 downto 2); + else --if mask = x"0" then + data_buffer(i*RESOLUTION*CHANNELS+(j+1)*RESOLUTION-1 downto i*RESOLUTION*CHANNELS+j*RESOLUTION) <= curr_data(i)(j); + end if; + last_data(i)(j) <= curr_data(i)(j); + end if; + end process; + end generate; + end generate; + + FCO_OUT <= cdt_data_out(1)(CHANNELS*12+11 downto CHANNELS*12) & cdt_data_out(0)(CHANNELS*12+11 downto CHANNELS*12); + DATA_OUT <= data_buffer; + DATA_VALID_OUT <= valid_read when rising_edge(CLK); + + DEBUG(3 downto 0) <= std_logic_vector(to_unsigned(state(1),4)); + DEBUG(7 downto 4) <= data_block(1)(1); + DEBUG(11 downto 8) <= data_block(1)(4); + DEBUG(12) <= fifo_empty(1); + DEBUG(13) <= fifo_full(1); + DEBUG(14) <= clk_data; + DEBUG(15) <= DATA_VALID_OUT(1); + +end architecture; \ No newline at end of file diff --git a/base/cores/dqsinput.ipx b/base/cores/dqsinput.ipx new file mode 100644 index 0000000..21cc5c6 --- /dev/null +++ b/base/cores/dqsinput.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/base/cores/dqsinput.lpc b/base/cores/dqsinput.lpc new file mode 100644 index 0000000..5d74e90 --- /dev/null +++ b/base/cores/dqsinput.lpc @@ -0,0 +1,60 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-6FN1156C +SpeedGrade=6 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=DDR_GENERIC +CoreRevision=5.2 +ModuleName=dqsinput +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/14/2012 +Time=16:40:21 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +mode=Receive +io_type=LVDS25 +num_int=2 +width=5 +freq_in=120 +bandwidth=1200 +aligned=Centered +pre-configuration=DISABLED +mode2=Receive +io_type2=LVDS25 +freq_in2=120 +gear=2x +aligned2=Centered +num_int2=2 +width2=5 +Interface=GDDRX2_RX.DQS.Centered +Delay=Bypass +Number=2 +dqs1=5 +dqs2=5 +dqs3= +dqs4= +dqs5= +dqs6= +dqs7= +dqs8= +val= +Phase=TRDLLB/DLLDELB +Divider=CLKDIVB +Multiplier=2 +PllFreq=60 diff --git a/base/cores/dqsinput.vhd b/base/cores/dqsinput.vhd new file mode 100644 index 0000000..9dee3f3 --- /dev/null +++ b/base/cores/dqsinput.vhd @@ -0,0 +1,453 @@ +-- VHDL netlist generated by SCUBA Diamond_1.4_Production (87) +-- Module Version: 5.2 +--/d/jspc29/lattice/diamond/1.4.2.105/ispfpga/bin/lin/scuba -w -n dqsinput -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 120 -gear 2 -clk dqs -dqs 1 5 -dqs 2 5 -e + +-- Tue Aug 14 16:40:21 2012 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity dqsinput is + port ( + clk_0: in std_logic; + clk_1: in std_logic; + clkdiv_reset: in std_logic; + eclk: in std_logic; + reset_0: in std_logic; + reset_1: in std_logic; + sclk: out std_logic; + datain_0: in std_logic_vector(4 downto 0); + datain_1: in std_logic_vector(4 downto 0); + q_0: out std_logic_vector(19 downto 0); + q_1: out std_logic_vector(19 downto 0)); + attribute dont_touch : boolean; + attribute dont_touch of dqsinput : entity is true; +end dqsinput; + +architecture Structure of dqsinput is + + -- internal signal declarations + signal datain_1i_t4: std_logic; + signal datain_1i_t3: std_logic; + signal datain_1i_t2: std_logic; + signal datain_1i_t1: std_logic; + signal datain_1i_t0: std_logic; + signal buf_datain_1i4: std_logic; + signal buf_datain_1i3: std_logic; + signal buf_datain_1i2: std_logic; + signal buf_datain_1i1: std_logic; + signal buf_datain_1i0: std_logic; + signal datain_0i_t4: std_logic; + signal datain_0i_t3: std_logic; + signal datain_0i_t2: std_logic; + signal datain_0i_t1: std_logic; + signal datain_0i_t0: std_logic; + signal buf_datain_0i4: std_logic; + signal buf_datain_0i3: std_logic; + signal buf_datain_0i2: std_logic; + signal buf_datain_0i1: std_logic; + signal buf_datain_0i0: std_logic; + signal qb19: std_logic; + signal qa19: std_logic; + signal qb09: std_logic; + signal qa09: std_logic; + signal datain_t9: std_logic; + signal qb18: std_logic; + signal qa18: std_logic; + signal qb08: std_logic; + signal qa08: std_logic; + signal datain_t8: std_logic; + signal qb17: std_logic; + signal qa17: std_logic; + signal qb07: std_logic; + signal qa07: std_logic; + signal datain_t7: std_logic; + signal qb16: std_logic; + signal qa16: std_logic; + signal qb06: std_logic; + signal qa06: std_logic; + signal datain_t6: std_logic; + signal qb15: std_logic; + signal qa15: std_logic; + signal qb05: std_logic; + signal qa05: std_logic; + signal datain_t5: std_logic; + signal qb14: std_logic; + signal qa14: std_logic; + signal qb04: std_logic; + signal qa04: std_logic; + signal datain_t4: std_logic; + signal qb13: std_logic; + signal qa13: std_logic; + signal qb03: std_logic; + signal qa03: std_logic; + signal datain_t3: std_logic; + signal qb12: std_logic; + signal qa12: std_logic; + signal qb02: std_logic; + signal qa02: std_logic; + signal datain_t2: std_logic; + signal qb11: std_logic; + signal qa11: std_logic; + signal qb01: std_logic; + signal qa01: std_logic; + signal datain_t1: std_logic; + signal qb10: std_logic; + signal qa10: std_logic; + signal qb00: std_logic; + signal qa00: std_logic; + signal datain_t0: std_logic; + signal dqclk11: std_logic; + signal dqclk01: std_logic; + signal eclkdqsr1: std_logic; + signal ddrlat1: std_logic; + signal datavalid1: std_logic; + signal prmbdet1: std_logic; + signal ddrclkpol1: std_logic; + signal dqsw1: std_logic; + signal dqclk10: std_logic; + signal dqclk00: std_logic; + signal eclkdqsr0: std_logic; + signal ddrlat0: std_logic; + signal datavalid0: std_logic; + signal prmbdet0: std_logic; + signal ddrclkpol0: std_logic; + signal dqsw0: std_logic; + signal scuba_vlo: std_logic; + signal dqsdel: std_logic; + signal dqsdll_lock: std_logic; + signal dqsdll_uddcntln: std_logic; + signal dqsdll_reset: std_logic; + signal clkos: std_logic; + signal cdiv8: std_logic; + signal cdiv4: std_logic; + signal cdiv1: std_logic; + signal scuba_vhi: std_logic; + signal clkok: std_logic; + signal buf_clk_1: std_logic; + signal buf_clk_0: std_logic; + signal sclk_t: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component IB + port (I: in std_logic; O: out std_logic); + end component; + component CLKDIVB + port (CLKI: in std_logic; RST: in std_logic; + RELEASE: in std_logic; CDIV1: out std_logic; + CDIV2: out std_logic; CDIV4: out std_logic; + CDIV8: out std_logic); + end component; + component IDDRX2D + generic (DELAYMODE : in String; SCLKLATENCY : in Integer); + port (D: in std_logic; SCLK: in std_logic; ECLK: in std_logic; + ECLKDQSR: in std_logic; DDRLAT: in std_logic; + DDRCLKPOL: in std_logic; QA0: out std_logic; + QB0: out std_logic; QA1: out std_logic; + QB1: out std_logic); + end component; + component DQSBUFD + generic (NRZMODE : in String; DYNDEL_CNTL : in String; + DYNDEL_VAL : in Integer; DYNDEL_TYPE : in String); + port (DQSI: in std_logic; SCLK: in std_logic; + READ: in std_logic; DQSDEL: in std_logic; + ECLK: in std_logic; ECLKW: in std_logic; + RST: in std_logic; DYNDELPOL: in std_logic; + DYNDELAY6: in std_logic; DYNDELAY5: in std_logic; + DYNDELAY4: in std_logic; DYNDELAY3: in std_logic; + DYNDELAY2: in std_logic; DYNDELAY1: in std_logic; + DYNDELAY0: in std_logic; DQSW: out std_logic; + DDRCLKPOL: out std_logic; PRMBDET: out std_logic; + DATAVALID: out std_logic; DDRLAT: out std_logic; + ECLKDQSR: out std_logic; DQCLK0: out std_logic; + DQCLK1: out std_logic); + end component; + component DQSDLLB + generic (LOCK_SENSITIVITY : in String); + port (CLK: in std_logic; RST: in std_logic; + UDDCNTLN: in std_logic; LOCK: out std_logic; + DQSDEL: out std_logic); + end component; + component DELAYC + port (A: in std_logic; Z: out std_logic); + end component; + attribute IDDRAPPS : string; + attribute IO_TYPE : string; + attribute IO_TYPE of Inst6_IB4 : label is "LVDS25"; + attribute IO_TYPE of Inst6_IB3 : label is "LVDS25"; + attribute IO_TYPE of Inst6_IB2 : label is "LVDS25"; + attribute IO_TYPE of Inst6_IB1 : label is "LVDS25"; + attribute IO_TYPE of Inst6_IB0 : label is "LVDS25"; + attribute IO_TYPE of Inst5_IB4 : label is "LVDS25"; + attribute IO_TYPE of Inst5_IB3 : label is "LVDS25"; + attribute IO_TYPE of Inst5_IB2 : label is "LVDS25"; + attribute IO_TYPE of Inst5_IB1 : label is "LVDS25"; + attribute IO_TYPE of Inst5_IB0 : label is "LVDS25"; + attribute IDDRAPPS of Inst_IDDRX2D_1_4 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_1_3 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_1_2 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_1_1 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_1_0 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_0_4 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_0_3 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_0_2 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_0_1 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_0_0 : label is "DQS_CENTERED"; + attribute IO_TYPE of Inst1_IB1 : label is "LVDS25"; + attribute IO_TYPE of Inst1_IB0 : label is "LVDS25"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + +begin + -- component instantiation statements + udel_datain_1i4: DELAYC + port map (A=>buf_datain_1i4, Z=>datain_1i_t4); + + udel_datain_1i3: DELAYC + port map (A=>buf_datain_1i3, Z=>datain_1i_t3); + + udel_datain_1i2: DELAYC + port map (A=>buf_datain_1i2, Z=>datain_1i_t2); + + udel_datain_1i1: DELAYC + port map (A=>buf_datain_1i1, Z=>datain_1i_t1); + + udel_datain_1i0: DELAYC + port map (A=>buf_datain_1i0, Z=>datain_1i_t0); + + Inst6_IB4: IB + port map (I=>datain_1(4), O=>buf_datain_1i4); + + Inst6_IB3: IB + port map (I=>datain_1(3), O=>buf_datain_1i3); + + Inst6_IB2: IB + port map (I=>datain_1(2), O=>buf_datain_1i2); + + Inst6_IB1: IB + port map (I=>datain_1(1), O=>buf_datain_1i1); + + Inst6_IB0: IB + port map (I=>datain_1(0), O=>buf_datain_1i0); + + udel_datain_0i4: DELAYC + port map (A=>buf_datain_0i4, Z=>datain_0i_t4); + + udel_datain_0i3: DELAYC + port map (A=>buf_datain_0i3, Z=>datain_0i_t3); + + udel_datain_0i2: DELAYC + port map (A=>buf_datain_0i2, Z=>datain_0i_t2); + + udel_datain_0i1: DELAYC + port map (A=>buf_datain_0i1, Z=>datain_0i_t1); + + udel_datain_0i0: DELAYC + port map (A=>buf_datain_0i0, Z=>datain_0i_t0); + + Inst5_IB4: IB + port map (I=>datain_0(4), O=>buf_datain_0i4); + + Inst5_IB3: IB + port map (I=>datain_0(3), O=>buf_datain_0i3); + + Inst5_IB2: IB + port map (I=>datain_0(2), O=>buf_datain_0i2); + + Inst5_IB1: IB + port map (I=>datain_0(1), O=>buf_datain_0i1); + + Inst5_IB0: IB + port map (I=>datain_0(0), O=>buf_datain_0i0); + + Inst_IDDRX2D_1_4: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t9, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, + QA0=>qa09, QB0=>qb09, QA1=>qa19, QB1=>qb19); + + Inst_IDDRX2D_1_3: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t8, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, + QA0=>qa08, QB0=>qb08, QA1=>qa18, QB1=>qb18); + + Inst_IDDRX2D_1_2: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t7, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, + QA0=>qa07, QB0=>qb07, QA1=>qa17, QB1=>qb17); + + Inst_IDDRX2D_1_1: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t6, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, + QA0=>qa06, QB0=>qb06, QA1=>qa16, QB1=>qb16); + + Inst_IDDRX2D_1_0: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t5, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, + QA0=>qa05, QB0=>qb05, QA1=>qa15, QB1=>qb15); + + Inst_IDDRX2D_0_4: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t4, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, + QA0=>qa04, QB0=>qb04, QA1=>qa14, QB1=>qb14); + + Inst_IDDRX2D_0_3: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t3, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, + QA0=>qa03, QB0=>qb03, QA1=>qa13, QB1=>qb13); + + Inst_IDDRX2D_0_2: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t2, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, + QA0=>qa02, QB0=>qb02, QA1=>qa12, QB1=>qb12); + + Inst_IDDRX2D_0_1: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t1, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, + QA0=>qa01, QB0=>qb01, QA1=>qa11, QB1=>qb11); + + Inst_IDDRX2D_0_0: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t0, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, + QA0=>qa00, QB0=>qb00, QA1=>qa10, QB1=>qb10); + + Inst4_DQSBUFD1: DQSBUFD + generic map (NRZMODE=> "DISABLED", DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC", + DYNDEL_TYPE=> "NORMAL") + port map (DQSI=>buf_clk_1, SCLK=>clkok, READ=>reset_1, + DQSDEL=>dqsdel, ECLK=>clkos, ECLKW=>clkos, RST=>reset_1, + DYNDELPOL=>scuba_vlo, DYNDELAY6=>scuba_vlo, + DYNDELAY5=>scuba_vlo, DYNDELAY4=>scuba_vlo, + DYNDELAY3=>scuba_vlo, DYNDELAY2=>scuba_vlo, + DYNDELAY1=>scuba_vlo, DYNDELAY0=>scuba_vlo, DQSW=>dqsw1, + DDRCLKPOL=>ddrclkpol1, PRMBDET=>prmbdet1, + DATAVALID=>datavalid1, DDRLAT=>ddrlat1, ECLKDQSR=>eclkdqsr1, + DQCLK0=>dqclk01, DQCLK1=>dqclk11); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + Inst4_DQSBUFD0: DQSBUFD + generic map (NRZMODE=> "DISABLED", DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC", + DYNDEL_TYPE=> "NORMAL") + port map (DQSI=>buf_clk_0, SCLK=>clkok, READ=>reset_0, + DQSDEL=>dqsdel, ECLK=>clkos, ECLKW=>clkos, RST=>reset_0, + DYNDELPOL=>scuba_vlo, DYNDELAY6=>scuba_vlo, + DYNDELAY5=>scuba_vlo, DYNDELAY4=>scuba_vlo, + DYNDELAY3=>scuba_vlo, DYNDELAY2=>scuba_vlo, + DYNDELAY1=>scuba_vlo, DYNDELAY0=>scuba_vlo, DQSW=>dqsw0, + DDRCLKPOL=>ddrclkpol0, PRMBDET=>prmbdet0, + DATAVALID=>datavalid0, DDRLAT=>ddrlat0, ECLKDQSR=>eclkdqsr0, + DQCLK0=>dqclk00, DQCLK1=>dqclk10); + + Inst3_DQSDLLB: DQSDLLB + generic map (LOCK_SENSITIVITY=> "LOW") + port map (CLK=>clkos, RST=>dqsdll_reset, + UDDCNTLN=>dqsdll_uddcntln, LOCK=>dqsdll_lock, DQSDEL=>dqsdel); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + Inst2_CLKDIVB: CLKDIVB + port map (CLKI=>eclk, RST=>clkdiv_reset, RELEASE=>scuba_vhi, + CDIV1=>cdiv1, CDIV2=>clkok, CDIV4=>cdiv4, CDIV8=>cdiv8); + + Inst1_IB1: IB + port map (I=>clk_1, O=>buf_clk_1); + + Inst1_IB0: IB + port map (I=>clk_0, O=>buf_clk_0); + + q_1(19) <= qb19; + q_1(18) <= qb18; + q_1(17) <= qb17; + q_1(16) <= qb16; + q_1(15) <= qb15; + q_1(14) <= qa19; + q_1(13) <= qa18; + q_1(12) <= qa17; + q_1(11) <= qa16; + q_1(10) <= qa15; + q_1(9) <= qb09; + q_1(8) <= qb08; + q_1(7) <= qb07; + q_1(6) <= qb06; + q_1(5) <= qb05; + q_1(4) <= qa09; + q_1(3) <= qa08; + q_1(2) <= qa07; + q_1(1) <= qa06; + q_1(0) <= qa05; + datain_t9 <= datain_1i_t4; + datain_t8 <= datain_1i_t3; + datain_t7 <= datain_1i_t2; + datain_t6 <= datain_1i_t1; + datain_t5 <= datain_1i_t0; + q_0(19) <= qb14; + q_0(18) <= qb13; + q_0(17) <= qb12; + q_0(16) <= qb11; + q_0(15) <= qb10; + q_0(14) <= qa14; + q_0(13) <= qa13; + q_0(12) <= qa12; + q_0(11) <= qa11; + q_0(10) <= qa10; + q_0(9) <= qb04; + q_0(8) <= qb03; + q_0(7) <= qb02; + q_0(6) <= qb01; + q_0(5) <= qb00; + q_0(4) <= qa04; + q_0(3) <= qa03; + q_0(2) <= qa02; + q_0(1) <= qa01; + q_0(0) <= qa00; + datain_t4 <= datain_0i_t4; + datain_t3 <= datain_0i_t3; + datain_t2 <= datain_0i_t2; + datain_t1 <= datain_0i_t1; + datain_t0 <= datain_0i_t0; + dqsdll_uddcntln <= scuba_vhi; + dqsdll_reset <= scuba_vhi; + clkos <= eclk; + sclk_t <= clkok; + sclk <= sclk_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of dqsinput is + for Structure + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:IB use entity ecp3.IB(V); end for; + for all:CLKDIVB use entity ecp3.CLKDIVB(V); end for; + for all:IDDRX2D use entity ecp3.IDDRX2D(V); end for; + for all:DQSBUFD use entity ecp3.DQSBUFD(V); end for; + for all:DQSDLLB use entity ecp3.DQSDLLB(V); end for; + for all:DELAYC use entity ecp3.DELAYC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/base/cores/fifo_32x512.ipx b/base/cores/fifo_32x512.ipx new file mode 100644 index 0000000..06d0fb0 --- /dev/null +++ b/base/cores/fifo_32x512.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/base/cores/fifo_32x512.lpc b/base/cores/fifo_32x512.lpc new file mode 100644 index 0000000..1c5cc4c --- /dev/null +++ b/base/cores/fifo_32x512.lpc @@ -0,0 +1,45 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-6FN1156C +SpeedGrade=6 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=4.8 +ModuleName=fifo_32x512 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/14/2012 +Time=18:18:36 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=512 +Width=32 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +EnECC=0 +EnFWFT=0 diff --git a/base/cores/fifo_32x512.vhd b/base/cores/fifo_32x512.vhd new file mode 100644 index 0000000..04f9f18 --- /dev/null +++ b/base/cores/fifo_32x512.vhd @@ -0,0 +1,651 @@ +-- VHDL netlist generated by SCUBA Diamond_1.4_Production (87) +-- Module Version: 4.8 +--/d/jspc29/lattice/diamond/1.4.2.105/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 32 -depth 512 -no_enable -pe -1 -pf -1 -e + +-- Tue Aug 14 18:18:36 2012 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_32x512 is + port ( + Data: in std_logic_vector(31 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(31 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_32x512; + +architecture Structure of fifo_32x512 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal rden_i_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal ifcount_5: std_logic; + signal co1: std_logic; + signal ifcount_6: std_logic; + signal ifcount_7: std_logic; + signal co2: std_logic; + signal ifcount_8: std_logic; + signal ifcount_9: std_logic; + signal co4: std_logic; + signal cnt_con: std_logic; + signal co3: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal co2_1: std_logic; + signal co3_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_2: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_2: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; + signal co2_2: std_logic; + signal fcount_6: std_logic; + signal fcount_7: std_logic; + signal co3_2: std_logic; + signal wren_i: std_logic; + signal wren_i_inv: std_logic; + signal fcount_8: std_logic; + signal fcount_9: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co0_3: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co1_3: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co2_3: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co4_1: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co3_3: std_logic; + signal scuba_vlo: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal r_ctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co0_4: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co1_4: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co2_4: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co4_2: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co3_4: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component ALEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; LE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component CB2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CON: in std_logic; CO: out std_logic; NC0: out std_logic; + NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component PDPW16KC + generic (GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_32x512.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t3: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_3: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t2: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_2: INV + port map (A=>empty_i, Z=>invout_0); + + AND2_t1: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t0: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_1: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_0: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + pdp_ram_0_0_0: PDPW16KC + generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), + DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), + DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), + DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), + DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo, + DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, + ADW0=>wcount_0, ADW1=>wcount_1, ADW2=>wcount_2, + ADW3=>wcount_3, ADW4=>wcount_4, ADW5=>wcount_5, + ADW6=>wcount_6, ADW7=>wcount_7, ADW8=>wcount_8, + BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, + BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW0=>scuba_vhi, + CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, + ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, + ADR4=>scuba_vlo, ADR5=>rcount_0, ADR6=>rcount_1, + ADR7=>rcount_2, ADR8=>rcount_3, ADR9=>rcount_4, + ADR10=>rcount_5, ADR11=>rcount_6, ADR12=>rcount_7, + ADR13=>rcount_8, CER=>rden_i, CLKR=>Clock, CSR0=>scuba_vlo, + CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), + DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), + DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), + DO11=>Q(29), DO12=>Q(30), DO13=>Q(31), DO14=>open, + DO15=>open, DO16=>open, DO17=>open, DO18=>Q(0), DO19=>Q(1), + DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), + DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), + DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), + DO34=>Q(16), DO35=>Q(17)); + + FF_31: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_30: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_29: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_28: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_27: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_26: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_25: FD1P3DX + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_24: FD1P3DX + port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_7); + + FF_23: FD1P3DX + port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_8); + + FF_22: FD1P3DX + port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_9); + + FF_21: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_20: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_19: FD1P3DX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_0); + + FF_18: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_17: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_16: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_15: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_14: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_13: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_12: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_7); + + FF_11: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_8); + + FF_10: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_9); + + FF_9: FD1P3DX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_0); + + FF_8: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_7: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_6: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_5: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_4: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_3: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_2: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_7); + + FF_1: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_8); + + FF_0: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_9); + + bdcnt_bctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open); + + bdcnt_bctr_0: CB2 + port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1, + CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1); + + bdcnt_bctr_1: CB2 + port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con, + CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3); + + bdcnt_bctr_2: CB2 + port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con, + CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5); + + bdcnt_bctr_3: CB2 + port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con, + CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7); + + bdcnt_bctr_4: CB2 + port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con, + CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9); + + e_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, + S1=>open); + + e_cmp_0: ALEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo, + CI=>cmp_ci, LE=>co0_1); + + e_cmp_1: ALEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co0_1, LE=>co1_1); + + e_cmp_2: ALEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co1_1, LE=>co2_1); + + e_cmp_3: ALEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co2_1, LE=>co3_1); + + e_cmp_4: ALEB2 + port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co3_1, LE=>cmp_le_1_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1, + S1=>open); + + g_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, + S1=>open); + + g_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + CI=>cmp_ci_1, GE=>co0_2); + + g_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + CI=>co0_2, GE=>co1_2); + + g_cmp_2: AGEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + CI=>co1_2, GE=>co2_2); + + g_cmp_3: AGEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, + CI=>co2_2, GE=>co3_2); + + g_cmp_4: AGEB2 + port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i_inv, + CI=>co3_2, GE=>cmp_ge_d1_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1, + S1=>open); + + w_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open, + S1=>open); + + w_ctr_0: CU2 + port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_ctr_1: CU2 + port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_ctr_2: CU2 + port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_ctr_3: CU2 + port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_ctr_4: CU2 + port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_1, + NC0=>iwcount_8, NC1=>iwcount_9); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open, + S1=>open); + + r_ctr_0: CU2 + port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4, + NC0=>ircount_0, NC1=>ircount_1); + + r_ctr_1: CU2 + port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4, + NC0=>ircount_2, NC1=>ircount_3); + + r_ctr_2: CU2 + port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4, + NC0=>ircount_4, NC1=>ircount_5); + + r_ctr_3: CU2 + port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4, + NC0=>ircount_6, NC1=>ircount_7); + + r_ctr_4: CU2 + port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_2, + NC0=>ircount_8, NC1=>ircount_9); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_32x512 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:ALEB2 use entity ecp3.ALEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:CB2 use entity ecp3.CB2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/base/cores/fifo_cdt_20.ipx b/base/cores/fifo_cdt_20.ipx new file mode 100644 index 0000000..2425337 --- /dev/null +++ b/base/cores/fifo_cdt_20.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/base/cores/fifo_cdt_20.lpc b/base/cores/fifo_cdt_20.lpc new file mode 100644 index 0000000..e5fe65f --- /dev/null +++ b/base/cores/fifo_cdt_20.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-6FN1156C +SpeedGrade=6 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_cdt_20 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/14/2012 +Time=17:09:06 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=16 +Width=20 +RDepth=16 +RWidth=20 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/base/cores/fifo_cdt_20.vhd b/base/cores/fifo_cdt_20.vhd new file mode 100644 index 0000000..e1ae201 --- /dev/null +++ b/base/cores/fifo_cdt_20.vhd @@ -0,0 +1,746 @@ +-- VHDL netlist generated by SCUBA Diamond_1.4_Production (87) +-- Module Version: 5.4 +--/d/jspc29/lattice/diamond/1.4.2.105/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 16 -width 20 -depth 16 -rdata_width 20 -regout -no_enable -pe -1 -pf -1 -e + +-- Tue Aug 14 17:09:06 2012 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_cdt_20 is + port ( + Data: in std_logic_vector(19 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(19 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_cdt_20; + +architecture Structure of fifo_cdt_20 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal co2: std_logic; + signal wcount_4: std_logic; + signal co1: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal co2_1: std_logic; + signal rcount_4: std_logic; + signal co1_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component PDPW16KC + generic (GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_cdt_20.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t10: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t9: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t8: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t7: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t6: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t5: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t4: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t3: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t2: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t1: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t0: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, + DO0=>w_g2b_xor_cluster_0); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r3); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>wcount_r3, DO0=>wcount_r0); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_0); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w3); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>rcount_w3, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_0: PDPW16KC + generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>scuba_vlo, + DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo, + DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo, + DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo, + DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo, + DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, + ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, + ADW4=>scuba_vlo, ADW5=>scuba_vlo, ADW6=>scuba_vlo, + ADW7=>scuba_vlo, ADW8=>scuba_vlo, BE0=>scuba_vhi, + BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, + CLKW=>WrClock, CSW0=>scuba_vhi, CSW1=>scuba_vlo, + CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo, + ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo, + ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, ADR8=>rptr_3, + ADR9=>scuba_vlo, ADR10=>scuba_vlo, ADR11=>scuba_vlo, + ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>scuba_vhi, + CLKR=>RdClock, CSR0=>rden_i, CSR1=>scuba_vlo, + CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19), + DO2=>open, DO3=>open, DO4=>open, DO5=>open, DO6=>open, + DO7=>open, DO8=>open, DO9=>open, DO10=>open, DO11=>open, + DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open, + DO17=>open, DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), + DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), + DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), + DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), + DO35=>Q(17)); + + FF_51: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_50: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_49: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_48: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_47: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_46: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_45: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_44: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_43: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_42: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_41: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_40: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_39: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_38: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_37: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_36: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_35: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_34: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_33: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_32: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_31: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_30: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_29: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_28: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_27: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_26: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_25: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_24: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_23: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_22: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_21: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_20: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_19: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_18: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_17: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_16: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_15: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_14: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_13: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_12: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_11: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_10: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_9: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_8: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_7: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_6: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_5: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_4: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_3: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_2: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>scuba_vlo, CO=>co2, + NC0=>iwcount_4, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>scuba_vlo, CO=>co2_1, + NC0=>ircount_4, NC1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>w_g2b_xor_cluster_0, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co1_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>r_g2b_xor_cluster_0, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co1_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_cdt_20 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/base/cores/fifo_cdt_200.ipx b/base/cores/fifo_cdt_200.ipx new file mode 100644 index 0000000..34866a3 --- /dev/null +++ b/base/cores/fifo_cdt_200.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/base/cores/fifo_cdt_200.lpc b/base/cores/fifo_cdt_200.lpc new file mode 100644 index 0000000..05b1dd9 --- /dev/null +++ b/base/cores/fifo_cdt_200.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-6FN1156C +SpeedGrade=6 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_cdt_200 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/16/2012 +Time=10:56:11 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=16 +Width=60 +RDepth=16 +RWidth=60 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/base/cores/fifo_cdt_200.vhd b/base/cores/fifo_cdt_200.vhd new file mode 100644 index 0000000..850d4f8 --- /dev/null +++ b/base/cores/fifo_cdt_200.vhd @@ -0,0 +1,783 @@ +-- VHDL netlist generated by SCUBA Diamond_1.4_Production (87) +-- Module Version: 5.4 +--/d/jspc29/lattice/diamond/1.4.2.105/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 16 -width 60 -depth 16 -rdata_width 60 -regout -no_enable -pe -1 -pf -1 -e + +-- Thu Aug 16 10:56:11 2012 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_cdt_200 is + port ( + Data: in std_logic_vector(59 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(59 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_cdt_200; + +architecture Structure of fifo_cdt_200 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal co2: std_logic; + signal wcount_4: std_logic; + signal co1: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal co2_1: std_logic; + signal rcount_4: std_logic; + signal co1_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component PDPW16KC + generic (GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_cdt_200.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; + attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_cdt_200.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is ""; + attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t10: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t9: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t8: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t7: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t6: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t5: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t4: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t3: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t2: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t1: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t0: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, + DO0=>w_g2b_xor_cluster_0); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r3); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>wcount_r3, DO0=>wcount_r0); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_0); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w3); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>rcount_w3, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_1: PDPW16KC + generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), + DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), + DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), + DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), + DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), + DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0, + ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>scuba_vlo, + ADW5=>scuba_vlo, ADW6=>scuba_vlo, ADW7=>scuba_vlo, + ADW8=>scuba_vlo, BE0=>scuba_vhi, BE1=>scuba_vhi, + BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, + CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo, + ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo, + ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, + ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>scuba_vlo, + ADR10=>scuba_vlo, ADR11=>scuba_vlo, ADR12=>scuba_vlo, + ADR13=>scuba_vlo, CER=>scuba_vhi, CLKR=>RdClock, + CSR0=>rden_i, CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, + DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), + DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), + DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), DO13=>Q(31), + DO14=>Q(32), DO15=>Q(33), DO16=>Q(34), DO17=>Q(35), + DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), + DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), + DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), + DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), DO35=>Q(17)); + + pdp_ram_0_1_0: PDPW16KC + generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), + DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42), + DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46), + DI11=>Data(47), DI12=>Data(48), DI13=>Data(49), + DI14=>Data(50), DI15=>Data(51), DI16=>Data(52), + DI17=>Data(53), DI18=>Data(54), DI19=>Data(55), + DI20=>Data(56), DI21=>Data(57), DI22=>Data(58), + DI23=>Data(59), DI24=>scuba_vlo, DI25=>scuba_vlo, + DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo, + DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo, + DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo, + DI35=>scuba_vlo, ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, + ADW3=>wptr_3, ADW4=>scuba_vlo, ADW5=>scuba_vlo, + ADW6=>scuba_vlo, ADW7=>scuba_vlo, ADW8=>scuba_vlo, + BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, + BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, + CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, + ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, + ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, + ADR8=>rptr_3, ADR9=>scuba_vlo, ADR10=>scuba_vlo, + ADR11=>scuba_vlo, ADR12=>scuba_vlo, ADR13=>scuba_vlo, + CER=>scuba_vhi, CLKR=>RdClock, CSR0=>rden_i, CSR1=>scuba_vlo, + CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(54), DO1=>Q(55), + DO2=>Q(56), DO3=>Q(57), DO4=>Q(58), DO5=>Q(59), DO6=>open, + DO7=>open, DO8=>open, DO9=>open, DO10=>open, DO11=>open, + DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open, + DO17=>open, DO18=>Q(36), DO19=>Q(37), DO20=>Q(38), + DO21=>Q(39), DO22=>Q(40), DO23=>Q(41), DO24=>Q(42), + DO25=>Q(43), DO26=>Q(44), DO27=>Q(45), DO28=>Q(46), + DO29=>Q(47), DO30=>Q(48), DO31=>Q(49), DO32=>Q(50), + DO33=>Q(51), DO34=>Q(52), DO35=>Q(53)); + + FF_51: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_50: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_49: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_48: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_47: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_46: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_45: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_44: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_43: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_42: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_41: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_40: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_39: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_38: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_37: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_36: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_35: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_34: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_33: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_32: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_31: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_30: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_29: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_28: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_27: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_26: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_25: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_24: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_23: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_22: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_21: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_20: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_19: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_18: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_17: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_16: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_15: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_14: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_13: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_12: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_11: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_10: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_9: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_8: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_7: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_6: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_5: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_4: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_3: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_2: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>scuba_vlo, CO=>co2, + NC0=>iwcount_4, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>scuba_vlo, CO=>co2_1, + NC0=>ircount_4, NC1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>w_g2b_xor_cluster_0, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co1_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>r_g2b_xor_cluster_0, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co1_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_cdt_200 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/base/cores/pll_adc12bit.ipx b/base/cores/pll_adc12bit.ipx new file mode 100644 index 0000000..3264e7c --- /dev/null +++ b/base/cores/pll_adc12bit.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/base/cores/pll_adc12bit.lpc b/base/cores/pll_adc12bit.lpc new file mode 100644 index 0000000..62a2e34 --- /dev/null +++ b/base/cores/pll_adc12bit.lpc @@ -0,0 +1,66 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-6FN1156C +SpeedGrade=6 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.2 +ModuleName=pll_adc12bit +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/16/2012 +Time=14:37:37 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=200 +Div=5 +ClkOPBp=0 +Post=2 +U_OFrq=360 +OP_Tol=0.0 +OFrq=360.000000 +DutyTrimP=Rising +DelayMultP=0 +fb_mode=CLKOP +Mult=9 +Phase=0.0 +Duty=8 +DelayMultS=0 +DPD=50% Duty +DutyTrimS=Rising +DelayMultD=0 +ClkOSDelay=0 +PhaseDuty=Static +CLKOK_INPUT=CLKOP +SecD=6 +U_KFrq=60 +OK_Tol=0.0 +KFrq=60.000000 +ClkRst=0 +PCDR=0 +FINDELA=0 +VcoRate= +Bandwidth=1.948057 +;DelayControl=No +EnCLKOS=1 +ClkOSBp=1 +EnCLKOK=1 +ClkOKBp=0 +enClkOK2=0 diff --git a/base/cores/pll_adc12bit.vhd b/base/cores/pll_adc12bit.vhd new file mode 100644 index 0000000..3556fad --- /dev/null +++ b/base/cores/pll_adc12bit.vhd @@ -0,0 +1,104 @@ +-- VHDL netlist generated by SCUBA Diamond_1.4_Production (87) +-- Module Version: 5.2 +--/d/jspc29/lattice/diamond/1.4.2.105/ispfpga/bin/lin/scuba -w -n pll_adc12bit -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypasss -fclkop 360 -fclkop_tol 0.0 -fb_mode CLOCKTREE -phaseadj 0.0 -duty 8 -fclkok 60 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw -e + +-- Thu Aug 16 14:37:37 2012 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity pll_adc12bit is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + CLKOS: out std_logic; + CLKOK: out std_logic; + LOCK: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of pll_adc12bit : entity is true; +end pll_adc12bit; + +architecture Structure of pll_adc12bit is + + -- internal signal declarations + signal CLKOS_t: std_logic; + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; + FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOK : string; + attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "200.000000"; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "360.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; + attribute FREQUENCY_PIN_CLKOK of PLLInst_0 : label is "60.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLF + generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", + CLKOS_BYPASS=> "ENABLED", CLKOP_BYPASS=> "DISABLED", CLKOK_INPUT=> "CLKOP", + DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, CLKOS_TRIM_DELAY=> 0, + CLKOS_TRIM_POL=> "RISING", CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 6, CLKOP_DIV=> 2, CLKFB_DIV=> 9, CLKI_DIV=> 5, + FIN=> "200.000000") + port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, + RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, + DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, + DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, + DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, + FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, + CLKOS=>CLKOS_t, CLKOK=>CLKOK, CLKOK2=>open, LOCK=>LOCK, + CLKINTFB=>open); + + CLKOS <= CLKOS_t; + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of pll_adc12bit is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/base/trb3_components.vhd b/base/trb3_components.vhd index ffc702d..f0c88a3 100644 --- a/base/trb3_components.vhd +++ b/base/trb3_components.vhd @@ -190,4 +190,75 @@ component edge_to_pulse pulse : out std_logic); end component; +component adc_ad9222 + generic( + CHANNELS : integer range 4 to 4 := 4; + DEVICES : integer range 2 to 2 := 2; + RESOLUTION : integer range 12 to 12 := 12 + ); + port( + CLK : in std_logic; + CLK_ADCREF : in std_logic; + CLK_ADCDAT : in std_logic; + RESTART_IN : in std_logic; + ADCCLK_OUT : out std_logic; + ADC_DATA : in std_logic_vector(DEVICES*CHANNELS-1 downto 0); + ADC_DCO : in std_logic_vector(DEVICES-1 downto 0); + ADC_FCO : in std_logic_vector(DEVICES-1 downto 0); + + DATA_OUT : out std_logic_vector(DEVICES*CHANNELS*RESOLUTION-1 downto 0); + FCO_OUT : out std_logic_vector(DEVICES*RESOLUTION-1 downto 0); + DATA_VALID_OUT : out std_logic_vector(DEVICES-1 downto 0); + DEBUG : out std_logic_vector(31 downto 0) + + ); +end component; + +component fifo_32x512 + port ( + Data: in std_logic_vector(31 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(31 downto 0); + Empty: out std_logic; + Full: out std_logic); +end component; + + + +component dqsinput + port ( + clk_0: in std_logic; + clk_1: in std_logic; + clkdiv_reset: in std_logic; + eclk: in std_logic; + reset_0: in std_logic; + reset_1: in std_logic; + sclk: out std_logic; + datain_0: in std_logic_vector(4 downto 0); + datain_1: in std_logic_vector(4 downto 0); + q_0: out std_logic_vector(19 downto 0); + q_1: out std_logic_vector(19 downto 0) + ); +end component; + +component fifo_cdt_200 + port ( + Data: in std_logic_vector(59 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(59 downto 0); + Empty: out std_logic; + Full: out std_logic); +end component; + + + end package; + diff --git a/base/trb3_periph_ada.lpf b/base/trb3_periph_ada.lpf index 200f7dd..14b11e7 100644 --- a/base/trb3_periph_ada.lpf +++ b/base/trb3_periph_ada.lpf @@ -316,9 +316,9 @@ LOCATE COMP "INP_32" SITE "J23"; #"DQUR_0" "DQUR_0" DQUR0_0 #105 LOCATE COMP "INP_33" SITE "G26"; #"DQUR_2" "DQUR_2" DQUR0_2 #109 # LOCATE COMP "INN_33" SITE "F26"; #"DQUR_3" "DQUR_3" DQUR0_3 #111 LOCATE COMP "INP_34" SITE "F24"; #"DQUR_4" "DQUR_4" DQSUR0_T #113 -# LOCATE COMP "INN_34" SITE "H25"; #"DQUR_5" "DQUR_5" DQUR0_5 #115 +# LOCATE COMP "INN_34" SITE "G24"; #"DQUR_7" "DQUR_7" DQSUR0_C #115 LOCATE COMP "INP_35" SITE "H26"; #"DQUR_6" "DQUR_6" DQUR0_4 #117 -# LOCATE COMP "INN_35" SITE "G24"; #"DQUR_7" "DQUR_7" DQSUR0_C #119 +# LOCATE COMP "INN_35" SITE "H25"; #"DQUR_5" "DQUR_5" DQUR0_5 #119 LOCATE COMP "INP_36" SITE "K23"; #"DQUR_8" "DQUR_8" DQUR0_6 #121 # LOCATE COMP "INN_36" SITE "K22"; #"DQUR_9" "DQUR_9" DQUR0_7 #123 LOCATE COMP "INP_37" SITE "F25"; #"DQUR_10" DQUR0_8 #125 #input only diff --git a/base/trb3_periph_multitest.lpf b/base/trb3_periph_multitest.lpf index 8f7771f..7eeb2ed 100644 --- a/base/trb3_periph_multitest.lpf +++ b/base/trb3_periph_multitest.lpf @@ -10,8 +10,8 @@ BLOCK RD_DURING_WR_PATHS ; # FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; # FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; -# FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; -# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; +# FREQUENCY PORT CLK_GPLL_LEFT 200 MHz; +# FREQUENCY PORT CLK_GPLL_RIGHT 125 MHz; ################################################################# @@ -21,8 +21,8 @@ LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20"; LOCATE COMP "CLK_PCLK_LEFT" SITE "M4"; LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18"; LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10"; -LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1"; -LOCATE COMP "CLK_GPLL_LEFT" SITE "U25"; +LOCATE COMP "CLK_GPLL_LEFT" SITE "W1"; +LOCATE COMP "CLK_GPLL_RIGHT" SITE "U25"; DEFINE PORT GROUP "CLK_group" "CLK*" ; IOBUF GROUP "CLK_group" IO_TYPE=LVDS25; @@ -266,10 +266,10 @@ IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12; # LOCATE COMP "LVDS_IO_N_16" SITE "H23"; #DQUR0_1 #107 LOCATE COMP "LVDS_IO_17" SITE "G26"; #DQUR0_2 #109 # LOCATE COMP "LVDS_IO_N_17" SITE "F26"; #DQUR0_3 #111 - LOCATE COMP "MADC2_SCLK" SITE "H26"; #DQUR0_4 #113 - LOCATE COMP "MADC2_SDIO" SITE "H25"; #DQUR0_5 #115 - LOCATE COMP "MADC2_CSB" SITE "F24"; #DQSUR0_T #117 - LOCATE COMP "MADC2_PDWN" SITE "G24"; #DQSUR0_C #119 + LOCATE COMP "MADC2_SCLK" SITE "F24"; #DQSUR0_T #113 + LOCATE COMP "MADC2_SDIO" SITE "G24"; #DQSUR0_C #115 + LOCATE COMP "MADC2_CSB" SITE "H26"; #DQUR0_4 #117 + LOCATE COMP "MADC2_PDWN" SITE "H25"; #DQUR0_5 #119 LOCATE COMP "MADC1_SCLK" SITE "K23"; #DQUR0_6 #121 LOCATE COMP "MADC1_SDIO" SITE "K22"; #DQUR0_7 #123 # LOCATE COMP "MADC1_CSB" SITE "F25"; #DQUR0_8 #125 #input only @@ -300,8 +300,14 @@ IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12; LOCATE COMP "RJ45_LVDS_1" SITE "P21"; #DQUR2_8 #150 # LOCATE COMP "RJ45_LVDS_N_1" SITE "P22"; #DQUR2_9 #152 -DEFINE PORT GROUP "LVDS_group" "LVDS*" ; +DEFINE PORT GROUP "LVDS_group" "LVDS_INP*" ; IOBUF GROUP "LVDS_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + +DEFINE PORT GROUP "LVDS2_group" "LVDS_IO*" ; +IOBUF GROUP "LVDS2_group" IO_TYPE=LVCMOS25; + + + DEFINE PORT GROUP "RJ_group" "RJ*" ; IOBUF GROUP "RJ_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; -- 2.43.0