From 42d77f08d2eace1dc538c8315de06b6a9e3762a8 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Fri, 3 Jul 2009 07:38:04 +0000 Subject: [PATCH] attilio --- design/mdc_addon_daq_bus_0.vhd | 16 +- design/mdc_oepb_pack.vhd | 4 +- design/tdc_readout.vhd | 1002 ++++++++++++++++++---- design/tdc_readout_and_trb_interface.vhd | 417 +++++---- 4 files changed, 1074 insertions(+), 365 deletions(-) diff --git a/design/mdc_addon_daq_bus_0.vhd b/design/mdc_addon_daq_bus_0.vhd index 10eeeea..baf5645 100644 --- a/design/mdc_addon_daq_bus_0.vhd +++ b/design/mdc_addon_daq_bus_0.vhd @@ -72,9 +72,9 @@ entity mdc_addon_daq_bus_0 is A_RDO_OUT : out std_logic; --ready FROM first motherboard ROC1_WRITTEN_OUT : out std_logic; - --BUS_NUMBER_IN : in std_logic_vector(3 downto 0); - DIRECTION_DATA_LINE_IN : out std_logic_vector(3 downto 0); - MOTHERBOARD_TYPE_IN : in std_logic_vector(3 downto 0); + DATA_TYPE_SELECT_IN : in std_logic_vector(3 downto 0); + DIRECTION_DATA_LINE_OUT : out std_logic_vector(3 downto 0); + MOTHERBOARD_TYPE_IN : in std_logic_vector(3 downto 0); ------------------------------------------------------------------------------- -- TRB INTERFACE ------------------------------------------------------------------------------- @@ -223,7 +223,7 @@ architecture behavioral of mdc_addon_daq_bus_0 is ------------------------------------------------------------------------------- -- tdc_readout_and_trb_interface ------------------------------------------------------------------------------- - BUS_NUMBER_IN : in std_logic_vector(3 downto 0); + DATA_TYPE_SELECT_IN : in std_logic_vector(3 downto 0); TOKEN_TO_TRB_OUT : out std_logic; REINIT_ROC1_IN : in std_logic; REINIT_ROC1_OUT : out std_logic; @@ -319,7 +319,7 @@ begin --behavioral RAM_WRITE_ENABLE_IN => RAM_WRITE_ENABLE_IN, DEBUG_REGISTER => open, - ENABLE_MODE_LINE => enable_mode_line_i, + ENABLE_MODE_LINE => enable_mode_line_i, --in ROC1_WRITTEN => roc1_written_i, CAL1_WRITTEN => cal1_written_i, TOKEN_BACK_OUT => token_back_out_i, @@ -336,7 +336,7 @@ begin --behavioral a_aod_data_i <= A_AOD_DATA_IN; --data adress line direction - DIRECTION_DATA_LINE_IN <= enable_mode_line_i; + DIRECTION_DATA_LINE_OUT <= enable_mode_line_i; u2 : common_stop_generator generic map(width => 5) @@ -366,11 +366,11 @@ begin --behavioral A_ACK => a_ack_i, A_DST => a_dst_data_i, A_DRE => open, --enable_a_add_data_i, - -- + TOKEN_IN => token_back_out_i, INIT_TDC_READOUT_IN => init_tdc_readout_i, - BUS_NUMBER_IN => x"1", --BUS_NUMBER_IN, + DATA_TYPE_SELECT_IN => DATA_TYPE_SELECT_IN, -- INIT_TRB_INTERFACE_IN => init_trb_interface_i, TOKEN_TO_TRB_OUT => token_to_trb_i, REINIT_ROC1_IN => reinit_roc1_i, diff --git a/design/mdc_oepb_pack.vhd b/design/mdc_oepb_pack.vhd index a1f1888..01cd0b6 100644 --- a/design/mdc_oepb_pack.vhd +++ b/design/mdc_oepb_pack.vhd @@ -44,8 +44,8 @@ component mdc_addon_daq_bus_0 D : out std_logic_vector(6 downto 0); A_RDO_OUT : out std_logic; ROC1_WRITTEN_OUT : out std_logic; - --BUS_NUMBER_IN : in std_logic_vector(3 downto 0); - DIRECTION_DATA_LINE_IN : out std_logic_vector(3 downto 0); + DATA_TYPE_SELECT_IN : in std_logic_vector(3 downto 0); + DIRECTION_DATA_LINE_OUT : out std_logic_vector(3 downto 0); MOTHERBOARD_TYPE_IN : in std_logic_vector(3 downto 0); ACKNOWLEDGE_TRB_INTERFACE_IN : in std_logic_vector(3 downto 0); INIT_TRB_INTERFACE_OUT : out std_logic; diff --git a/design/tdc_readout.vhd b/design/tdc_readout.vhd index 53f8509..9f019cc 100644 --- a/design/tdc_readout.vhd +++ b/design/tdc_readout.vhd @@ -36,60 +36,98 @@ entity tdc_readout is TOKEN_TDC_READOUT_OUT : out std_logic_vector(3 downto 0); FLAG_EVENT_COUNTER_IN : in std_logic_vector(3 downto 0); - DATA_BUS_OUT : out std_logic_vector(35 downto 0); --(25 downto 0); --(18 downto 0); + DATA_BUS_OUT : out std_logic_vector(35 downto 0); DATA_VALID_OUT : out std_logic; FULL_FIFO_IN : in std_logic; - INIT_TDC_READOUT_IN : in std_logic; --from common stop generator + INIT_TDC_READOUT_IN : in std_logic_vector(3 downto 0); --from common stop generator + DATA_TYPE_SELECT_IN : in std_logic_vector(3 downto 0); --x"0"debug, + --x"1" 2 hit in one word DEBUG_REGISTER_OUT : out std_logic_vector(3 downto 0)); end tdc_readout; architecture behavioral of tdc_readout is - +------------------------------------------------------------------------------- +-- debug mode signals +------------------------------------------------------------------------------- type state_type is (idle_state, save_H_word_state, save_H_word_state_next, save_L_word_state,save_L_word_state_next, wait_1_state,wait_2_state,wait_3_state, wait_4_state, send_data,send_data_next, send_data_with_valid, - send_data_with_valid_next, send_data_no_valid, fifo_full_state, - send_token_state_1, send_token_state_2, send_token_state_3, send_token_state_4); signal current_state, next_state : state_type; signal reg_debug_register, next_debug_register : std_logic_vector(3 downto 0); -signal reg_data_bus_out, next_data_bus_out : std_logic_vector(35 downto 0);--(18 downto 0); +signal reg_data_bus_out, next_data_bus_out : std_logic_vector(35 downto 0); signal reg_data_valid_out, next_data_valid_out : std_logic; -signal saved_data : std_logic_vector(35 downto 0);--(25 downto 0);--(23 downto 0);--(18 downto 0); +signal saved_data : std_logic_vector(35 downto 0); signal reg_token_tdc_readout_i, next_token_tdc_readout_i : std_logic_vector(3 downto 0); -signal pulse_init_tdc_readout : std_logic; +signal reg_flag_event_counter_in : std_logic_vector(3 downto 0); +--signal pulse_init_tdc_readout : std_logic; - component edge_to_pulse - port ( - CLOCK : in std_logic; - ENABLE_CLK_IN : in std_logic; - SIGNAL_IN : in std_logic; - PULSE_OUT : out std_logic); - end component; +------------------------------------------------------------------------------- +-- new format signals (2 hits in one dataword) +------------------------------------------------------------------------------- +type state_type_new_format is (idle_state_new_format, + save_H_word_state_new_format, save_H_word_state_next_new_format, + save_L_word_state_new_format, save_L_word_state_next_new_format, + send_data_new_format, send_data_next_new_format, send_data_with_valid_new_format, + send_data_with_valid_next_new_format, send_data_no_valid_new_format, + fifo_full_state_new_format, + send_token_state_1_new_format, send_token_state_2_new_format, + send_token_state_3_new_format, + send_token_state_4_new_format, check_hit_number_state_new_format, + wait_state_0_new_format, send_one_hit_new_format, send_one_hit_with_valid_format, + wait_state_1_new_format, send_third_hit_new_format, send_third_hit_with_valid_new_format, + wait_state_2_new_format, + send_error_word, send_error_word_with_valid_next_new_format, + wait_state_3_new_format, +--calibration + save_L_word_state_new_format_calibration, + save_L_word_state_next_new_format_calibration, + save_H_word_state_new_format_calibration, + save_H_word_state_next_new_format_calibration, + dummy_wait_0_calibration, + check_hit_number_state_new_format_calibration, + send_calibration_data, send_calibration_data_next, + wait_state_0_calibration, wait_state_2_calibration, + send_error_calibration_word, + send_error_calibration_word_next, wait_state_1_calibration); -begin -- behavioral +signal current_state_new_format, next_state_new_format : state_type_new_format; +signal reg_debug_register_new_format, next_debug_register_new_format : std_logic_vector(3 downto 0); +signal reg_data_bus_out_new_format, next_data_bus_out_new_format : std_logic_vector(35 downto 0); +signal reg_data_valid_out_new_format, next_data_valid_out_new_format : std_logic; +signal saved_data_new_format_hit_0 : std_logic_vector(35 downto 0); +signal saved_data_new_format_hit_1 : std_logic_vector(35 downto 0); +signal saved_data_new_format_hit_0_cal : std_logic_vector(35 downto 0); +signal saved_data_new_format_hit_1_cal : std_logic_vector(35 downto 0); - u1: edge_to_pulse - port map ( - CLOCK => CLK, - ENABLE_CLK_IN =>'1', - SIGNAL_IN => INIT_TDC_READOUT_IN, - PULSE_OUT => pulse_init_tdc_readout); - - REGISTER_OUTPUT : process (CLK) +signal saved_data_new_format : std_logic_vector(35 downto 0); +signal reg_token_tdc_readout_i_new_format, next_token_tdc_readout_i_new_format : std_logic_vector(3 downto 0); +signal pulse_init_tdc_readout_new_format : std_logic; +signal clear_counter_check_hit,up_counter_check_hit : STD_LOGIC; +signal counter_check_hit : std_logic_vector(3 downto 0); +signal reg_data_type_select_in : std_logic_vector(3 downto 0); +signal clear_counter_check_hit_calibration,up_counter_check_hit_calibration : STD_LOGIC; +signal counter_check_hit_calibration : std_logic_vector(3 downto 0); +signal clear_saved_data_new_format_hit_0_1_cal : std_logic; + +begin -- behavioral + +------------------------------------------------------------------------------- +-- DEBUG DATAWORD STRUCTURE : BEGIN +------------------------------------------------------------------------------- + REGISTER_OUTPUT : process (CLK, reg_data_type_select_in) begin if rising_edge(CLK) then - if RESET = '1' then + if (RESET = '1' or reg_data_type_select_in = x"1") then current_state <= idle_state; reg_data_bus_out <= (others => '0'); reg_data_valid_out <= '0'; - --reg_token_out_to_trb <= '0'; reg_token_tdc_readout_i <= (others => '0'); reg_debug_register <= (others => '0'); else @@ -97,20 +135,12 @@ begin -- behavioral reg_debug_register <= next_debug_register; reg_data_bus_out <= next_data_bus_out; reg_data_valid_out <= next_data_valid_out; - -- reg_token_out_to_trb <= next_token_out_to_trb; reg_token_tdc_readout_i <= next_token_tdc_readout_i; end if; end if; end process REGISTER_OUTPUT; ---DATA_BUS_OUT(9) <= '0'; ---saved_data(9) <= '0'; - DATA_VALID_OUT <= reg_data_valid_out; - DATA_BUS_OUT <= saved_data; --- A_DRE <= reg_a_dre; ---TOKEN_OUT_TO_TRB <= reg_token_out_to_trb; - TOKEN_TDC_READOUT_OUT <= reg_token_tdc_readout_i; - DEBUG_REGISTER_OUT <= reg_debug_register; + ------------------------------------------------------------------------------ -- purpose: state machine. get TDC data and build a std_logic_vector ------------------------------------------------------------------------------- @@ -121,19 +151,18 @@ begin -- behavioral next_data_valid_out <= '0'; next_data_bus_out <= (others => '0'); - --next_token_out_to_trb <= '0'; next_debug_register <= (others => '0'); - --next_a_dre <= '0'; - --up_counter_12bit_i <= '0'; next_token_tdc_readout_i <= (others => '0'); case current_state is when idle_state => next_debug_register <= "0000"; - if INIT_TDC_READOUT_IN = '1' then + -- x"1" normal trigger + -- x"9" calibration trigger + if (INIT_TDC_READOUT_IN = x"1" or + INIT_TDC_READOUT_IN = x"9") then next_state <= save_L_word_state; - --next_a_dre <= '1'; else next_state <= idle_state; end if; @@ -151,59 +180,48 @@ begin -- behavioral ------------------------------------------------------------------------------- when save_L_word_state => next_debug_register <= "0001"; - --next_a_dre <= '1'; if A_DST_IN = '1' and A_AOD_IN = '1' then - --next_state <= wait_1_state; - next_state <= save_L_word_state_next; - elsif TOKEN_IN = x"1" then --token and NO data - next_state <= send_token_state_2; - elsif TOKEN_IN = x"2" then --NO token and NO data - next_state <= send_token_state_3; +-- next_state <= save_L_word_state_next; + next_state <= wait_1_state; +-- elsif TOKEN_IN = x"1" then --token and NO data +-- next_state <= send_token_state_2; +-- elsif TOKEN_IN = x"2" then --NO token and NO data +-- next_state <= send_token_state_3; else next_state <= save_L_word_state; end if; -------------------------------------------------------------------------------- --- -------------------------------------------------------------------------------- --- when wait_1_state => --- next_state <= wait_2_state; --- when wait_2_state => --- next_state <= save_L_word_state_next; - + when wait_1_state => + next_state <= wait_2_state; + + when wait_2_state => + next_state <= save_L_word_state_next; + when save_L_word_state_next => --here I save data next_state <= save_H_word_state; when save_H_word_state => next_debug_register <= "0011"; if A_DST_IN = '1' and A_AOD_IN = '0' then - --next_state <= wait_3_state; - next_state <= save_H_word_state_next; + -- next_state <= save_H_word_state_next; + next_state <= wait_3_state; else next_state <= save_H_word_state; end if; --- when wait_3_state => --- next_state <= wait_4_state; - --- when wait_4_state => --- next_state <= save_H_word_state_next; + when wait_3_state => + next_state <= wait_4_state; + when wait_4_state => + next_state <= save_H_word_state_next; + when save_H_word_state_next => --here I save data - next_data_valid_out <= '1'; - next_state <= send_data_with_valid; + --next_data_valid_out <= '1'; + next_state <= send_data_with_valid; -------------------------------------------------------------------------------- --- here I send the data to the FIFO --- DATA_VALID_OUT is the write enable signal to fifo --- DATA_VALID_OUT <= '1' data is written into FIFO --- DATA_VALID_OUT <= '0' data is NOT written into FIFO --- I assert DATA_VALID_OUT <= '1', after 1 clk cycle the data on the bus is --- written into the FIFO -------------------------------------------------------------------------------- + when send_data_with_valid => next_debug_register <= "0101"; - -- next_a_dre <= '1'; next_data_valid_out <= '0'; --connected to WRITE_FIFO next_state <= send_data_with_valid_next; -- if FULL_FIFO_IN = '1' then --not full @@ -213,23 +231,20 @@ begin -- behavioral -- end if; when send_data_with_valid_next => - next_debug_register <= "0111"; - --next_a_dre <= '1'; - next_data_valid_out <= '0'; --'0'; --only here I write the fifo! - next_state <= send_data_no_valid; + next_debug_register <= "0111"; + next_data_valid_out <= '1'; + next_state <= send_data_no_valid; when send_data_no_valid => next_debug_register <= "1000"; - --next_a_dre <= '1'; next_data_valid_out <= '0'; --connected to WRITE_FIFO if (A_AOD_IN = '1' and TOKEN_IN = x"0") then next_state <= save_L_word_state; - elsif (A_AOD_IN = '0' and TOKEN_IN = x"1") then next_state <= send_token_state_1; --token and data - elsif (A_AOD_IN = '0' and TOKEN_IN = x"2") then --NO token back and data in fifo - next_state <= send_token_state_4; -- NO token and data +-- elsif (A_AOD_IN = '0' and TOKEN_IN = x"2") then --NO token back and data in fifo +-- next_state <= send_token_state_4; -- NO token and data else next_state <= send_data_no_valid; end if; @@ -239,33 +254,29 @@ begin -- behavioral ------------------------------------------------------------------------------- when send_token_state_1 => next_debug_register <= "1001"; - -- next_a_dre <= '1'; next_token_tdc_readout_i <= x"1"; next_state <= idle_state; ------------------------------------------------------------------------------- -- token + NO data => => => => OK ------------------------------------------------------------------------------- - when send_token_state_2 => - next_debug_register <= "1011"; - -- next_a_dre <= '1'; - next_token_tdc_readout_i <= x"3"; - next_state <= idle_state; -------------------------------------------------------------------------------- --- NO token + NO data -------------------------------------------------------------------------------- - when send_token_state_3 => - next_debug_register <= "1100"; - -- next_a_dre <= '1'; - next_token_tdc_readout_i <= x"4"; - next_state <= idle_state; -------------------------------------------------------------------------------- --- NO token + data -------------------------------------------------------------------------------- - when send_token_state_4 => - next_debug_register <= "1100"; - -- next_a_dre <= '1'; - next_token_tdc_readout_i <= x"5"; - next_state <= idle_state; +-- when send_token_state_2 => +-- next_debug_register <= "1011"; +-- next_token_tdc_readout_i <= x"3"; +-- next_state <= idle_state; +-- ------------------------------------------------------------------------------- +-- -- NO token + NO data +-- ------------------------------------------------------------------------------- +-- when send_token_state_3 => +-- next_debug_register <= "1100"; +-- next_token_tdc_readout_i <= x"4"; +-- next_state <= idle_state; +-- ------------------------------------------------------------------------------- +-- -- NO token + data +-- ------------------------------------------------------------------------------- +-- when send_token_state_4 => +-- next_debug_register <= "1100"; +-- next_token_tdc_readout_i <= x"5"; +-- next_state <= idle_state; -- when send_data_no_valid => @@ -282,17 +293,15 @@ begin -- behavioral -- next_state <= send_data_no_valid; -- end if; - when fifo_full_state => - next_debug_register <= "1100"; - -- next_a_dre <= '1'; - next_data_valid_out <= '0'; - -- next_token_out_to_trb <= '0'; ---I stay here if there is no space in the fifo - if FULL_FIFO_IN = '1' then --cannot write anymore in fifo - next_state <= fifo_full_state; - else - next_state <= idle_state; - end if; +-- when fifo_full_state => +-- next_debug_register <= "1100"; +-- next_data_valid_out <= '0'; +-- --I stay here if there is no space in the fifo +-- if FULL_FIFO_IN = '1' then --cannot write anymore in fifo +-- next_state <= fifo_full_state; +-- else +-- next_state <= idle_state; +-- end if; when others => next_state <= idle_state; @@ -304,22 +313,21 @@ begin -- behavioral -- process: it gets the token from entity "send_token", -- it is back I send to TRB ------------------------------------------------------------------------------ - save_data: process (CLK) + save_data: process (CLK,next_state) begin if rising_edge(CLK) then if RESET = '1' then saved_data <= (others => '0'); - -- reg_flag_event_counter <= (others => '0'); - elsif next_state = save_H_word_state_next then - saved_data(35 downto 32) <= FLAG_EVENT_COUNTER_IN; - saved_data(31 downto 26) <= FLAG_EVENT_COUNTER_IN & "00";--x"0"; + elsif (next_state = save_H_word_state_next) then + saved_data(35 downto 32) <= reg_flag_event_counter_in; + saved_data(31 downto 26) <= reg_flag_event_counter_in & "00";--x"0"; saved_data(25 downto 23) <= '0' & "00";--mb_number; saved_data(22 downto 19) <= x"0";--reg_bus_number;--x"1"; saved_data(18 downto 12) <= A_ADD_IN(8 downto 2); saved_data(11) <= A_RESERV_IN; --11th bit is reserv! saved_data(10 downto 9) <= A_ADD_IN(1 downto 0); saved_data(8 downto 0) <= saved_data(8 downto 0); - elsif next_state = save_L_word_state_next then + elsif (next_state = save_L_word_state_next) then saved_data(18 downto 9) <= saved_data(18 downto 9); saved_data(8 downto 0) <= A_ADD_IN(8 downto 0); else @@ -328,71 +336,731 @@ begin -- behavioral end if; end process save_data; +--register flag event counter + process (CLK, RESET) + begin + if (rising_edge(CLK)) then + if RESET = '1' then + reg_flag_event_counter_in <= (others => '0'); + else + reg_flag_event_counter_in <= FLAG_EVENT_COUNTER_IN; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +-- DEBUG DATAWORD STRUCTURE : END +------------------------------------------------------------------------------- + ------------------------------------------------------------------------------- --- I mark the event using dataword 4-bit saved_data(35 downto 32) +-- 2 HITS IN ONE DATAWORD STRUCTURE : BEGIN +-- here I repeat a new FSM to build the data in a compact way: 2 hits in one word +------------------------------------------------------------------------------- + +--register data select + process (CLK, RESET) + begin + if (rising_edge(CLK)) then + if (RESET = '1') then + reg_data_type_select_in <= (others => '0'); + else + reg_data_type_select_in <= DATA_TYPE_SELECT_IN; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +-- DATA SELECT MULTIPLEXER ------------------------------------------------------------------------------- --- process (CLK) +-- process (CLK, reg_data_type_select_in) +-- begin +-- if (rising_edge(CLK)) then +-- if (reg_data_type_select_in = x"0") then --debug mode + DATA_VALID_OUT <= reg_data_valid_out; + DATA_BUS_OUT <= saved_data; + TOKEN_TDC_READOUT_OUT <= reg_token_tdc_readout_i; + DEBUG_REGISTER_OUT <= reg_debug_register; + +-- elsif (reg_data_type_select_in = x"1") then --2hit in one dw +-- DATA_VALID_OUT <= reg_data_valid_out_new_format; +-- DATA_BUS_OUT <= saved_data_new_format; +-- TOKEN_TDC_READOUT_OUT <= reg_token_tdc_readout_i_new_format; +-- DEBUG_REGISTER_OUT <= reg_debug_register_new_format; + +-- else --debug mode +-- DATA_VALID_OUT <= reg_data_valid_out; +-- DATA_BUS_OUT <= saved_data; +-- TOKEN_TDC_READOUT_OUT <= reg_token_tdc_readout_i; +-- DEBUG_REGISTER_OUT <= reg_debug_register; +-- end if; +-- end if; +-- end process; + +------------------------------------------------------------------------------- +-- +------------------------------------------------------------------------------- +-- REGISTER_OUTPUT_NEW_FORMAT : process (CLK, reg_data_type_select_in) -- begin -- if rising_edge(CLK) then --- if RESET = '1' then --- reg_flag_event_counter <= (others => '0'); +-- if (RESET = '1' or reg_data_type_select_in = x"0") then +-- current_state_new_format <= idle_state_new_format; +-- reg_data_bus_out_new_format <= (others => '0'); +-- reg_data_valid_out_new_format <= '0'; +-- reg_token_tdc_readout_i_new_format <= (others => '0'); +-- reg_debug_register_new_format <= (others => '0'); -- else --- reg_flag_event_counter <= FLAG_EVENT_COUNTER_IN; +-- current_state_new_format <= next_state_new_format; +-- reg_debug_register_new_format <= next_debug_register_new_format; +-- reg_data_bus_out_new_format <= next_data_bus_out_new_format; +-- reg_data_valid_out_new_format <= next_data_valid_out_new_format; +-- reg_token_tdc_readout_i_new_format <= next_token_tdc_readout_i_new_format; -- end if; -- end if; --- end process; -------------------------------------------------------------------------------- --- I count the ACK signals to see when the transfer for each MB is finished. -------------------------------------------------------------------------------- --- process (CLK) +-- end process REGISTER_OUTPUT_NEW_FORMAT; + +-- ------------------------------------------------------------------------------ +-- -- purpose: state machine. +-- ------------------------------------------------------------------------------- +-- process(current_state_new_format, TOKEN_IN, INIT_TDC_READOUT_IN, +-- A_DST_IN, A_AOD_IN, FULL_FIFO_IN, +-- counter_check_hit, +-- saved_data_new_format_hit_0, saved_data_new_format_hit_1, +-- counter_check_hit_calibration, +-- saved_data_new_format_hit_0_cal, saved_data_new_format_hit_1_cal) + +-- begin + +-- next_data_valid_out_new_format <= '0'; +-- next_data_bus_out_new_format <= (others => '0'); +-- next_debug_register_new_format <= (others => '0'); +-- next_token_tdc_readout_i_new_format <= (others => '0'); +-- clear_counter_check_hit <= '0'; +-- clear_counter_check_hit_calibration <= '0'; +-- up_counter_check_hit <= '0'; +-- up_counter_check_hit_calibration <= '0'; +-- saved_data_new_format <= (others => '0'); +-- clear_saved_data_new_format_hit_0_1_cal <= '0'; + +-- case current_state_new_format is + +-- when idle_state_new_format => +-- next_debug_register_new_format <= x"0"; +-- up_counter_check_hit <= '0'; +-- clear_counter_check_hit <= '0'; +-- --normal trigger +-- if (INIT_TDC_READOUT_IN = x"1") then +-- next_state_new_format <= save_L_word_state_new_format; +-- --calibration trigger +-- elsif (INIT_TDC_READOUT_IN = x"9") then +-- next_state_new_format <= save_L_word_state_new_format_calibration; +-- else +-- next_state_new_format <= idle_state_new_format; +-- end if; + +-- when save_L_word_state_new_format => +-- next_debug_register_new_format <= x"1"; +-- if (A_DST_IN = '1' and A_AOD_IN = '1') then +-- next_state_new_format <= save_L_word_state_next_new_format; +-- elsif (TOKEN_IN = x"1") then --token and NO data +-- next_state_new_format <= send_token_state_2_new_format; +-- elsif (TOKEN_IN = x"2") then --NO token and NO data +-- next_state_new_format <= send_token_state_3_new_format; +-- else +-- next_state_new_format <= save_L_word_state_new_format; +-- end if; + +-- when save_L_word_state_next_new_format => --here I save data +-- next_debug_register_new_format <= x"2"; +-- next_state_new_format <= save_H_word_state_new_format; + +-- when save_H_word_state_new_format => +-- next_debug_register_new_format <= x"3"; +-- if (A_DST_IN = '1' and A_AOD_IN = '0') then +-- next_state_new_format <= save_H_word_state_next_new_format; +-- else +-- next_state_new_format <= save_H_word_state_new_format; +-- end if; +-- ------------------------------------------------------------------------------- +-- -- I must check the hit number. If it is '0' +-- ------------------------------------------------------------------------------- +-- when save_H_word_state_next_new_format => --here I save data +-- next_debug_register_new_format <= x"4"; +-- up_counter_check_hit <= '1'; --increase hit number +-- next_state_new_format <= check_hit_number_state_new_format; + +-- when check_hit_number_state_new_format => +-- next_debug_register_new_format <= x"5"; +-- up_counter_check_hit <= '0'; + +-- case counter_check_hit is +-- --first hit already saved + +-- when x"1" => +-- --go and save the second hit +-- if (saved_data_new_format_hit_0(11) = '1') then +-- --new dataword coming +-- if (A_AOD_IN = '1' and TOKEN_IN = x"0") then +-- next_state_new_format <= save_L_word_state_new_format; +-- else +-- next_state_new_format <= check_hit_number_state_new_format; +-- end if; +-- --single hit word or the 3rd hit +-- elsif (saved_data_new_format_hit_0(11) = '0') then +-- if (saved_data_new_format_hit_0(28 downto 22) = saved_data_new_format_hit_1(28 downto 22) ) then +-- --3rd hit +-- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0(35 downto 32); +-- saved_data_new_format(31 downto 29) <= "010"; +-- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0(28 downto 22); +-- saved_data_new_format(21 downto 11) <= (others => '0'); +-- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0(10 downto 0); +-- next_state_new_format <= send_third_hit_new_format; +-- --single hit +-- else +-- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0(35 downto 32); +-- saved_data_new_format(31 downto 29) <= "101"; +-- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0(28 downto 22); +-- saved_data_new_format(21 downto 11) <= (others => '0'); +-- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0(10 downto 0); +-- next_state_new_format <= send_one_hit_new_format; +-- end if; +-- end if; +-- --I check if tdc number and channel are the same +-- when x"2" => +-- if (saved_data_new_format_hit_0(28 downto 22) = saved_data_new_format_hit_1(28 downto 22) ) then +-- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0(35 downto 32); +-- saved_data_new_format(31 downto 29) <= "001"; --normal word, two hit in one +-- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0(28 downto 22); +-- saved_data_new_format(21 downto 11) <= saved_data_new_format_hit_1(10 downto 0); +-- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0(10 downto 0); +-- next_state_new_format <= send_data_with_valid_new_format; +-- else +-- --I send 2 hit in one but with error flag +-- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0(35 downto 32); +-- saved_data_new_format(31 downto 29) <= "100"; +-- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0(28 downto 22); +-- saved_data_new_format(21 downto 11) <= saved_data_new_format_hit_1(10 downto 0); +-- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0(10 downto 0); +-- next_state_new_format <= send_error_word; +-- end if; + +-- when x"0"|x"3"|x"4"|x"5"|x"6"|x"7"|x"8"|x"9"|x"a"|x"b"|x"c"| x"d"|x"e"|x"f" => +-- next_state_new_format <= send_data_with_valid_new_format; +-- when others => null; +-- end case; + +-- ------------------------------------------------------------------------------- +-- -- send two hits in one dataword +-- ------------------------------------------------------------------------------- +-- when send_data_with_valid_new_format => +-- next_debug_register_new_format <= x"6"; +-- next_data_valid_out_new_format <= '1'; +-- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0(35 downto 32); +-- saved_data_new_format(31 downto 29) <= "001"; --normal word, two hit in one +-- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0(28 downto 22); +-- saved_data_new_format(21 downto 11) <= saved_data_new_format_hit_1(10 downto 0); +-- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0(10 downto 0); +-- next_state_new_format <= send_data_with_valid_next_new_format; + +-- --send data +-- when send_data_with_valid_next_new_format => +-- next_debug_register_new_format <= x"7"; +-- next_data_valid_out_new_format <= '0'; +-- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0(35 downto 32); +-- saved_data_new_format(31 downto 29) <= "001"; --normal word, two hit in one +-- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0(28 downto 22); +-- saved_data_new_format(21 downto 11) <= saved_data_new_format_hit_1(10 downto 0); +-- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0(10 downto 0); +-- next_state_new_format <= wait_state_0_new_format; + +-- when wait_state_0_new_format => +-- next_debug_register_new_format <= x"8"; +-- next_data_valid_out_new_format <= '0'; +-- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0(35 downto 32); +-- saved_data_new_format(31 downto 29) <= "001"; --normal word, two hit in one +-- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0(28 downto 22); +-- saved_data_new_format(21 downto 11) <= saved_data_new_format_hit_1(10 downto 0); +-- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0(10 downto 0); +-- clear_counter_check_hit <= '1'; +-- if (A_AOD_IN = '1' and TOKEN_IN = x"0") then +-- next_state_new_format <= save_L_word_state_new_format; +-- elsif (A_AOD_IN = '0' and TOKEN_IN = x"1") then +-- next_state_new_format <= send_token_state_1_new_format; +-- else +-- next_state_new_format <= wait_state_0_new_format; +-- end if; + +-- ------------------------------------------------------------------------------- +-- -- send single hit in one dataword +-- ------------------------------------------------------------------------------- +-- when send_one_hit_new_format => +-- next_debug_register_new_format <= x"8"; +-- next_data_valid_out_new_format <= '1'; +-- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0(35 downto 32); +-- saved_data_new_format(31 downto 29) <= "101"; +-- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0(28 downto 22); +-- saved_data_new_format(21 downto 11) <= (others => '0'); +-- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0(10 downto 0); +-- next_state_new_format <= send_one_hit_with_valid_format; + +-- when send_one_hit_with_valid_format => +-- next_data_valid_out_new_format <= '0'; +-- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0(35 downto 32); +-- saved_data_new_format(31 downto 29) <= "101"; +-- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0(28 downto 22); +-- saved_data_new_format(21 downto 11) <= (others => '0'); +-- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0(10 downto 0); +-- next_state_new_format <= wait_state_1_new_format; + +-- when wait_state_1_new_format => +-- next_debug_register_new_format <= x"7"; +-- next_data_valid_out_new_format <= '0'; +-- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0(35 downto 32); +-- saved_data_new_format(31 downto 29) <= "101"; +-- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0(28 downto 22); +-- saved_data_new_format(21 downto 11) <= (others => '0'); +-- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0(10 downto 0); +-- clear_counter_check_hit <= '1'; +-- if (A_AOD_IN = '1' and TOKEN_IN = x"0") then +-- next_state_new_format <= save_L_word_state_new_format; +-- elsif (A_AOD_IN = '0' and TOKEN_IN = x"1") then +-- next_state_new_format <= send_token_state_1_new_format; +-- else +-- next_state_new_format <= wait_state_1_new_format; +-- end if; +-- ------------------------------------------------------------------------------- +-- -- send third hit +-- ------------------------------------------------------------------------------- +-- when send_third_hit_new_format => +-- next_data_valid_out_new_format <= '1'; +-- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0(35 downto 32); +-- saved_data_new_format(31 downto 29) <= "010"; +-- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0(28 downto 22); +-- saved_data_new_format(21 downto 11) <= (others => '0'); +-- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0(10 downto 0); +-- next_state_new_format <= send_third_hit_with_valid_new_format; + +-- when send_third_hit_with_valid_new_format => +-- next_data_valid_out_new_format <= '0'; +-- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0(35 downto 32); +-- saved_data_new_format(31 downto 29) <= "010"; +-- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0(28 downto 22); +-- saved_data_new_format(21 downto 11) <= (others => '0'); +-- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0(10 downto 0); +-- next_state_new_format <= wait_state_2_new_format; + +-- when wait_state_2_new_format => +-- next_data_valid_out_new_format <= '0'; +-- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0(35 downto 32); +-- saved_data_new_format(31 downto 29) <= "010"; +-- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0(28 downto 22); +-- saved_data_new_format(21 downto 11) <= (others => '0'); +-- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0(10 downto 0); +-- clear_counter_check_hit <= '1'; +-- if (A_AOD_IN = '1' and TOKEN_IN = x"0") then +-- next_state_new_format <= save_L_word_state_new_format; +-- elsif (A_AOD_IN = '0' and TOKEN_IN = x"1") then +-- next_state_new_format <= send_token_state_1_new_format; +-- else +-- next_state_new_format <= wait_state_2_new_format; +-- end if; +-- ------------------------------------------------------------------------------- +-- -- send error word +-- ------------------------------------------------------------------------------- +-- when send_error_word => +-- next_debug_register_new_format <= x"6"; +-- next_data_valid_out_new_format <= '1'; +-- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0(35 downto 32); +-- saved_data_new_format(31 downto 29) <= "100"; +-- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0(28 downto 22); +-- saved_data_new_format(21 downto 11) <= saved_data_new_format_hit_1(10 downto 0); +-- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0(10 downto 0); +-- next_state_new_format <= send_error_word_with_valid_next_new_format; + +-- --send data +-- when send_error_word_with_valid_next_new_format => +-- next_debug_register_new_format <= x"7"; +-- next_data_valid_out_new_format <= '0'; +-- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0(35 downto 32); +-- saved_data_new_format(31 downto 29) <= "100"; +-- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0(28 downto 22); +-- saved_data_new_format(21 downto 11) <= saved_data_new_format_hit_1(10 downto 0); +-- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0(10 downto 0); +-- next_state_new_format <= wait_state_3_new_format; + +-- when wait_state_3_new_format => +-- next_debug_register_new_format <= x"8"; +-- next_data_valid_out_new_format <= '0'; +-- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0(35 downto 32); +-- saved_data_new_format(31 downto 29) <= "100"; +-- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0(28 downto 22); +-- saved_data_new_format(21 downto 11) <= saved_data_new_format_hit_1(10 downto 0); +-- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0(10 downto 0); +-- clear_counter_check_hit <= '1'; +-- if (A_AOD_IN = '1' and TOKEN_IN = x"0") then +-- next_state_new_format <= save_L_word_state_new_format; +-- elsif (A_AOD_IN = '0' and TOKEN_IN = x"1") then +-- next_state_new_format <= send_token_state_1_new_format; +-- else +-- next_state_new_format <= wait_state_3_new_format; +-- end if; + +-- ------------------------------------------------------------------------------ +-- --READOUT CALIBRATION DATA +-- ------------------------------------------------------------------------------ +-- when save_L_word_state_new_format_calibration => +-- next_debug_register_new_format <= x"1"; +-- if (A_DST_IN = '1' and A_AOD_IN = '1') then +-- next_state_new_format <= save_L_word_state_next_new_format_calibration; +-- elsif (TOKEN_IN = x"1") then --token and NO data +-- next_state_new_format <= send_token_state_2_new_format; +-- elsif (TOKEN_IN = x"2") then --NO token and NO data +-- next_state_new_format <= send_token_state_3_new_format; +-- else +-- next_state_new_format <= save_L_word_state_new_format_calibration; +-- end if; + +-- when save_L_word_state_next_new_format_calibration => --here I save data +-- next_debug_register_new_format <= x"2"; +-- next_state_new_format <= save_H_word_state_new_format_calibration; + +-- when save_H_word_state_new_format_calibration => +-- next_debug_register_new_format <= x"3"; +-- if (A_DST_IN = '1' and A_AOD_IN = '0') then +-- next_state_new_format <= save_H_word_state_next_new_format_calibration; +-- else +-- next_state_new_format <= save_H_word_state_new_format_calibration; +-- end if; + +-- when save_H_word_state_next_new_format_calibration => --here I save data +-- next_debug_register_new_format <= x"4"; +-- up_counter_check_hit_calibration <= '0'; +-- next_state_new_format <= dummy_wait_0_calibration; + +-- when dummy_wait_0_calibration => +-- next_debug_register_new_format <= x"4"; +-- up_counter_check_hit_calibration <= '1'; --increase hit number +-- next_state_new_format <= check_hit_number_state_new_format_calibration; + +-- when check_hit_number_state_new_format_calibration => +-- next_debug_register_new_format <= x"5"; +-- up_counter_check_hit_calibration <= '0'; + +-- case counter_check_hit_calibration is +-- --clear counter_check_hit_calibration after one channel has been calibrated +-- when x"1" => +-- --go and save the second hit +-- if (saved_data_new_format_hit_0_cal(11) = '1') then +-- --new dataword coming +-- if (A_AOD_IN = '1' and TOKEN_IN = x"0") then +-- next_state_new_format <= save_L_word_state_new_format_calibration; +-- else +-- next_state_new_format <= check_hit_number_state_new_format_calibration; +-- end if; +-- --error +-- elsif (saved_data_new_format_hit_0_cal(11) = '0') then +-- -- next_state_new_format <= check_hit_number_state_new_format_calibration; +-- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0_cal(35 downto 32); +-- saved_data_new_format(31 downto 29) <= "111"; --error calibrationflag +-- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0_cal(28 downto 22); +-- saved_data_new_format(21 downto 11) <= (others => '0'); +-- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0_cal(10 downto 0); +-- next_state_new_format <= send_error_calibration_word; +-- end if; + +-- --combine word nr0 and nr1 and send +-- when x"2" => +-- --you should add a safe condition, in case the FEE has problem, like +-- --if (saved_data_new_format_hit_1_cal(11) = '1' ) then +-- -- if (saved_data_new_format_hit_0_cal(28 downto 22) = saved_data_new_format_hit_1_cal(28 downto 22) ) then +-- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0_cal(35 downto 32); +-- saved_data_new_format(31 downto 29) <= "110"; --normal cal word, two hit in one +-- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0_cal(28 downto 22); +-- saved_data_new_format(21 downto 11) <= saved_data_new_format_hit_1_cal(10 downto 0); +-- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0_cal(10 downto 0); +-- next_state_new_format <= wait_state_2_calibration;--send_calibration_data; + +-- when x"0"|x"3"|x"4"|x"5"|x"6"|x"7"|x"8"|x"9"|x"a"|x"b"|x"c"| x"d"|x"e"|x"f" => +-- next_state_new_format <= send_error_calibration_word; +-- when others => null; +-- end case; + +-- ------------------------------------------------------------------------------- +-- --send calibration data, when no error found in dataword building +-- ------------------------------------------------------------------------------- + +-- when wait_state_2_calibration => +-- next_debug_register_new_format <= x"7"; +-- next_data_valid_out_new_format <= '0'; +-- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0_cal(35 downto 32); +-- saved_data_new_format(31 downto 29) <= "110"; --normal cal word, two hit in one +-- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0_cal(28 downto 22); +-- saved_data_new_format(21 downto 11) <= saved_data_new_format_hit_1_cal(10 downto 0); +-- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0_cal(10 downto 0); +-- next_state_new_format <= send_calibration_data; + +-- when send_calibration_data => +-- next_debug_register_new_format <= x"6"; +-- next_data_valid_out_new_format <= '0'; +-- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0_cal(35 downto 32); +-- saved_data_new_format(31 downto 29) <= "110"; --normal cal word, two hit in one +-- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0_cal(28 downto 22); +-- saved_data_new_format(21 downto 11) <= saved_data_new_format_hit_1_cal(10 downto 0); +-- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0_cal(10 downto 0); +-- next_state_new_format <= send_calibration_data_next; + +-- when send_calibration_data_next => +-- next_debug_register_new_format <= x"7"; +-- next_data_valid_out_new_format <= '1'; +-- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0_cal(35 downto 32); +-- saved_data_new_format(31 downto 29) <= "110"; --normal cal word, two hit in one +-- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0_cal(28 downto 22); +-- saved_data_new_format(21 downto 11) <= saved_data_new_format_hit_1_cal(10 downto 0); +-- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0_cal(10 downto 0); +-- next_state_new_format <= wait_state_0_calibration; + +-- when wait_state_0_calibration => +-- next_debug_register_new_format <= x"8"; +-- next_data_valid_out_new_format <= '0'; +-- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0_cal(35 downto 32); +-- saved_data_new_format(31 downto 29) <= "110"; --normal cal word, two hit in one +-- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0_cal(28 downto 22); +-- saved_data_new_format(21 downto 11) <= saved_data_new_format_hit_1_cal(10 downto 0); +-- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0_cal(10 downto 0); +-- if (A_AOD_IN = '1' and TOKEN_IN = x"0") then +-- clear_counter_check_hit_calibration <= '1'; --clear cal dataword number +-- clear_saved_data_new_format_hit_0_1_cal <= '1'; --clear save data vector +-- next_state_new_format <= save_L_word_state_new_format_calibration; +-- elsif (A_AOD_IN = '0' and TOKEN_IN = x"1") then +-- next_state_new_format <= send_token_state_1_new_format; +-- else +-- next_state_new_format <= wait_state_0_calibration; +-- end if; +-- ------------------------------------------------------------------------------- +-- -- send error in case of error calibration +-- ------------------------------------------------------------------------------- +-- when send_error_calibration_word => +-- next_debug_register_new_format <= x"6"; +-- next_data_valid_out_new_format <= '0'; +-- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0_cal(35 downto 32); +-- saved_data_new_format(31 downto 29) <= "111"; --normal cal word, two hit in one +-- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0_cal(28 downto 22); +-- saved_data_new_format(21 downto 11) <= saved_data_new_format_hit_1_cal(10 downto 0); +-- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0_cal(10 downto 0); +-- next_state_new_format <= send_error_calibration_word_next; + +-- when send_error_calibration_word_next => +-- next_debug_register_new_format <= x"7"; +-- next_data_valid_out_new_format <= '1'; +-- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0_cal(35 downto 32); +-- saved_data_new_format(31 downto 29) <= "111"; --normal cal word, two hit in one +-- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0_cal(28 downto 22); +-- saved_data_new_format(21 downto 11) <= saved_data_new_format_hit_1_cal(10 downto 0); +-- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0_cal(10 downto 0); +-- next_state_new_format <= wait_state_1_calibration; + +-- when wait_state_1_calibration => +-- next_debug_register_new_format <= x"8"; +-- next_data_valid_out_new_format <= '0'; +-- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0_cal(35 downto 32); +-- saved_data_new_format(31 downto 29) <= "111"; --normal cal word, two hit in one +-- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0_cal(28 downto 22); +-- saved_data_new_format(21 downto 11) <= saved_data_new_format_hit_1_cal(10 downto 0); +-- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0_cal(10 downto 0); +-- if (A_AOD_IN = '1' and TOKEN_IN = x"0") then +-- clear_counter_check_hit_calibration <= '1'; --clear cal dataword number +-- clear_saved_data_new_format_hit_0_1_cal <= '1'; --clear save data vector +-- next_state_new_format <= save_L_word_state_new_format_calibration; +-- elsif (A_AOD_IN = '0' and TOKEN_IN = x"1") then +-- next_state_new_format <= send_token_state_1_new_format; +-- else +-- next_state_new_format <= wait_state_1_calibration; +-- end if; +-- ------------------------------------------------------------------------------- +-- -- token after data have been retrieved +-- ------------------------------------------------------------------------------- +-- when send_token_state_1_new_format => +-- next_debug_register_new_format <= "1001"; +-- clear_counter_check_hit_calibration <= '1'; --clear cal dataword number +-- clear_saved_data_new_format_hit_0_1_cal <= '1'; --clear save data vector +-- next_token_tdc_readout_i_new_format <= x"1"; +-- next_state_new_format <= idle_state_new_format; +-- ------------------------------------------------------------------------------- +-- -- token + NO data => => => => OK +-- ------------------------------------------------------------------------------- +-- when send_token_state_2_new_format => +-- next_debug_register_new_format <= "1011"; +-- next_token_tdc_readout_i_new_format <= x"3"; +-- next_state_new_format <= idle_state_new_format; +-- ------------------------------------------------------------------------------- +-- -- NO token + NO data +-- ------------------------------------------------------------------------------- +-- when send_token_state_3_new_format => +-- next_debug_register_new_format <= "1100"; +-- next_token_tdc_readout_i_new_format <= x"4"; +-- next_state_new_format <= idle_state_new_format; +-- ------------------------------------------------------------------------------- +-- -- NO token + data +-- ------------------------------------------------------------------------------- +-- when send_token_state_4_new_format => +-- next_debug_register_new_format <= "1100"; +-- next_token_tdc_readout_i_new_format <= x"5"; +-- next_state_new_format <= idle_state_new_format; + +-- when fifo_full_state_new_format => +-- next_debug_register_new_format <= "1100"; +-- next_data_valid_out_new_format <= '0'; +-- --I stay here if there is no space in the fifo +-- if FULL_FIFO_IN = '1' then --cannot write anymore in fifo +-- next_state_new_format <= fifo_full_state_new_format; +-- else +-- next_state_new_format <= idle_state_new_format; +-- end if; + +-- when others => +-- next_state_new_format <= idle_state_new_format; +-- end case; +-- end process; + +-- ------------------------------------------------------------------------------ +-- -- process: it gets the token from entity "send_token", +-- -- it is back I send to TRB. +-- -- Save data +-- ------------------------------------------------------------------------------ +-- SAVE_DATA_NEW_FORMAT : process (CLK, RESET, next_state_new_format, counter_check_hit) -- begin --- if rising_edge(CLK) then --- if (RESET = '1' or TOKEN_IN = x"1" or --- current_state = idle_state or --- counter_12bit_i = x"000" or --- counter_12bit_i = x"001" or --- counter_12bit_i = x"002") then --- mb_counter <= (others => '0'); --- elsif pulse_a_ack = '1' then --- mb_counter <= mb_counter + 1; +-- if (rising_edge(CLK)) then +-- if (RESET = '1') then +-- saved_data_new_format_hit_0 <= (others => '0'); +-- saved_data_new_format_hit_1 <= (others => '0'); + +-- --I increase the counter after one full word is collected + +-- -- FIRST HIT +-- elsif (counter_check_hit = x"0") then --save the first hit and TDC number/channel + +-- if (next_state_new_format = save_H_word_state_next_new_format) then +-- saved_data_new_format_hit_0(35 downto 32) <= FLAG_EVENT_COUNTER_IN; --INTERNAL USE +-- saved_data_new_format_hit_0(31 downto 29) <= saved_data_new_format_hit_0(31 downto 29);--"001"; --DATA TYPE +-- saved_data_new_format_hit_0(28 downto 22) <= A_ADD_IN(8 downto 2); --TDCnr/CHANNEL +-- saved_data_new_format_hit_0(11) <= A_RESERV_IN; --hit number +-- saved_data_new_format_hit_0(10 downto 9) <= A_ADD_IN(1 downto 0); --DATA +-- saved_data_new_format_hit_0(8 downto 0) <= saved_data_new_format_hit_0(8 downto 0); + +-- elsif (next_state_new_format = save_L_word_state_next_new_format) then +-- saved_data_new_format_hit_0(18 downto 9) <= saved_data_new_format_hit_0(18 downto 9); +-- saved_data_new_format_hit_0(8 downto 0) <= A_ADD_IN(8 downto 0); --DATA +-- else +-- saved_data_new_format_hit_0 <= saved_data_new_format_hit_0; +-- end if; + +-- -- SECOND HIT +-- elsif (counter_check_hit = x"1") then --save the second hit and TDC number/channel + +-- if (next_state_new_format = save_H_word_state_next_new_format) then +-- saved_data_new_format_hit_1(35 downto 32) <= FLAG_EVENT_COUNTER_IN; --INTERNAL USE +-- saved_data_new_format_hit_1(31 downto 29) <= saved_data_new_format_hit_1(31 downto 29); --"001"; --DATA TYPE +-- saved_data_new_format_hit_1(28 downto 22) <= A_ADD_IN(8 downto 2); --TDCnr/CHANNEL +-- saved_data_new_format_hit_1(11) <= A_RESERV_IN; --hit number +-- saved_data_new_format_hit_1(10 downto 9) <= A_ADD_IN(1 downto 0); --DATA +-- saved_data_new_format_hit_1(8 downto 0) <= saved_data_new_format_hit_1(8 downto 0); + +-- elsif (next_state_new_format = save_L_word_state_next_new_format) then +-- saved_data_new_format_hit_1(18 downto 9) <= saved_data_new_format_hit_1(18 downto 9); +-- saved_data_new_format_hit_1(8 downto 0) <= A_ADD_IN(8 downto 0); --DATA + +-- else +-- saved_data_new_format_hit_1 <= saved_data_new_format_hit_1; +-- end if; + +-- end if; +-- end if; +-- end process SAVE_DATA_NEW_FORMAT; + +-- ------------------------------------------------------------------------------- +-- -- Save calibration data process +-- ------------------------------------------------------------------------------- +-- save_data_cal: process (CLK, RESET, current_state_new_format, counter_check_hit_calibration, +-- clear_saved_data_new_format_hit_0_1_cal) +-- begin +-- if (rising_edge(CLK)) then +-- if (RESET = '1' or clear_saved_data_new_format_hit_0_1_cal = '1') then +-- saved_data_new_format_hit_0_cal <= (others => '0'); +-- saved_data_new_format_hit_1_cal <= (others => '0'); + +-- --I increase the counter after one full word is collected + +-- elsif (counter_check_hit_calibration = x"0") then --save the first hit and TDC number/channel + +-- if (current_state_new_format = save_H_word_state_next_new_format_calibration) then +-- saved_data_new_format_hit_0_cal(35 downto 32) <= FLAG_EVENT_COUNTER_IN; --INTERNAL USE +-- saved_data_new_format_hit_0_cal(31 downto 29) <= saved_data_new_format_hit_0_cal(31 downto 29); --DATA TYPE +-- saved_data_new_format_hit_0_cal(28 downto 22) <= A_ADD_IN(8 downto 2); --TDCnr/CHANNEL +-- saved_data_new_format_hit_0_cal(11) <= A_RESERV_IN; --hit number +-- saved_data_new_format_hit_0_cal(10 downto 9) <= A_ADD_IN(1 downto 0); --DATA +-- saved_data_new_format_hit_0_cal(8 downto 0) <= saved_data_new_format_hit_0_cal(8 downto 0); + +-- elsif (current_state_new_format = save_L_word_state_next_new_format_calibration) then +-- saved_data_new_format_hit_0_cal(18 downto 9) <= saved_data_new_format_hit_0_cal(18 downto 9); +-- saved_data_new_format_hit_0_cal(8 downto 0) <= A_ADD_IN(8 downto 0); --DATA +-- else +-- saved_data_new_format_hit_0_cal <= saved_data_new_format_hit_0_cal; +-- end if; + +-- elsif (counter_check_hit_calibration = x"1") then --save the second hit and TDC number/channel + +-- if (current_state_new_format = save_H_word_state_next_new_format_calibration) then +-- saved_data_new_format_hit_1_cal(35 downto 32) <= FLAG_EVENT_COUNTER_IN; --INTERNAL USE +-- saved_data_new_format_hit_1_cal(31 downto 29) <= saved_data_new_format_hit_1_cal(31 downto 29); +-- saved_data_new_format_hit_1_cal(28 downto 22) <= A_ADD_IN(8 downto 2); --TDCnr/CHANNEL +-- saved_data_new_format_hit_1_cal(11) <= A_RESERV_IN; --hit number +-- saved_data_new_format_hit_1_cal(10 downto 9) <= A_ADD_IN(1 downto 0); --DATA +-- saved_data_new_format_hit_1_cal(8 downto 0) <= saved_data_new_format_hit_1_cal(8 downto 0); + +-- elsif (current_state_new_format = save_L_word_state_next_new_format_calibration) then +-- saved_data_new_format_hit_1_cal(18 downto 9) <= saved_data_new_format_hit_1_cal(18 downto 9); +-- saved_data_new_format_hit_1_cal(8 downto 0) <= A_ADD_IN(8 downto 0); --DATA + +-- else +-- saved_data_new_format_hit_1_cal <= saved_data_new_format_hit_1_cal; +-- end if; + +-- end if; +-- end if; +-- end process save_data_cal; + +-- --counter used to chech the correct hit number in normal triggering +-- process (CLK, RESET, clear_counter_check_hit) +-- begin +-- if (rising_edge(CLK)) then +-- if (RESET = '1' or clear_counter_check_hit = '1') then +-- counter_check_hit <= (others => '0'); +-- elsif (up_counter_check_hit = '1') then +-- counter_check_hit <= counter_check_hit + 1; -- else --- mb_counter <= mb_counter; +-- counter_check_hit <= counter_check_hit; -- end if; -- end if; -- end process; --- clear_counter_12bit_i <= '1' when (current_state = idle_state) else '0'; --- process (CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- mb_number_temp <= (others => '0'); --- elsif mb_counter = "00" then --- mb_number_temp <= "00"; --- elsif mb_counter = "01" then --- mb_number_temp <= "01"; --- else --- mb_number_temp <= mb_number_temp; --- end if; --- end if; --- end process; --- mb_number <= mb_number_temp; -------------------------------------------------------------------------------- --- I register the bus number which I put in the dataword ------------------------------------------------------------------------------ --- process (CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- reg_bus_number <= (others => '0'); +-- --counter used to check the correct hit number in calibration trigger +-- process (CLK, RESET, clear_counter_check_hit_calibration) +-- begin +-- if (rising_edge(CLK)) then +-- if (RESET = '1' or clear_counter_check_hit_calibration = '1') then +-- counter_check_hit_calibration <= (others => '0'); +-- elsif (up_counter_check_hit_calibration = '1') then +-- counter_check_hit_calibration <= counter_check_hit_calibration + 1; -- else --- reg_bus_number <= BUS_NUMBER_IN; +-- counter_check_hit_calibration <= counter_check_hit_calibration; -- end if; -- end if; -- end process; - - +------------------------------------------------------------------------------- +-- 2 HITS IN ONE DATAWORD STRUCTURE : END +------------------------------------------------------------------------------- + + end behavioral; diff --git a/design/tdc_readout_and_trb_interface.vhd b/design/tdc_readout_and_trb_interface.vhd index aeef419..9f4a04e 100644 --- a/design/tdc_readout_and_trb_interface.vhd +++ b/design/tdc_readout_and_trb_interface.vhd @@ -31,11 +31,8 @@ use ecp2m.components.all; entity tdc_readout_and_trb_interface is -- generic (width : integer := 16; - -- bus_number: std_logic_vector(3 downto 0));-- if 5 and clk 100MHz the state remain active 320 ns - port ( -- if width 15 => 330 usec: - -- I send the token if I do not see it after - -- 330 us => BEEF - -- if width 16 => 855 usec between token + -- bus_number: std_logic_vector(3 downto 0)); + port ( CLK : in std_logic; RESET : in std_logic; @@ -54,8 +51,8 @@ entity tdc_readout_and_trb_interface is ------------------------------------------------------------------------------- -- tdc_readout_and_trb_interface -------------------------------------------------------------------------------- - BUS_NUMBER_IN : in std_logic_vector(3 downto 0); +------------------------------------------------------------------------------- + DATA_TYPE_SELECT_IN : in std_logic_vector(3 downto 0); -- INIT_TRB_INTERFACE_IN : in std_logic; TOKEN_TO_TRB_OUT : out std_logic; REINIT_ROC1_IN : in std_logic; @@ -110,9 +107,9 @@ architecture behavioral of tdc_readout_and_trb_interface is -- FSM_HEADER ---------------------------------------------------------------------- - type state_type is (idle_state, wait_for_token, send_first_header_state, + type state_type is (idle_state, wait_for_token, send_second_header_state, send_data_state, - send_data_1_state, dummy_wait_1_header_state,busy_header_state); + send_data_1_state,busy_header_state); signal current_state, next_state : state_type; @@ -127,7 +124,6 @@ architecture behavioral of tdc_readout_and_trb_interface is end_of_event_transfer_fsm_multiplexer, dummy_wait_1_fsm_multiplexer, dummy_wait_2_fsm_multiplexer, - dummy_wait_3_fsm_multiplexer, dummy_wait_4_fsm_multiplexer ); signal current_state_fsm_multiplexer, next_state_fsm_multiplexer : state_type_fsm_multiplexer; @@ -213,10 +209,21 @@ architecture behavioral of tdc_readout_and_trb_interface is -- signal reg_ipu_number : std_logic_vector (15 downto 0); -- signal reg_ipu_information : std_logic_vector (7 downto 0); signal reg_ipu_start_readout_in : std_logic; - signal push_read_fee_data_1_i : std_logic; ------------------------------------------------------------------------------- --- COUNTERs -------------------------------------------------------------------------------- + signal push_read_fee_data_1_i : std_logic; + + signal last_not_empty_flag_fee_data_fifo_i : std_logic; + signal not_empty_flag_fee_data_fifo_i : std_logic; + signal pulse_not_empty_flag_fee_data_fifo_i : std_logic; + signal counter_pulse_not_empty : std_logic_vector(15 downto 0); + + signal last_not_empty_flag_header_data_fifo_i : std_logic; + signal not_empty_flag_header_data_fifo_i : std_logic; + signal pulse_not_empty_flag_header_data_fifo_i : std_logic; + signal counter_pulse_not_empty_header : std_logic_vector(15 downto 0); + signal fee_data_fifo_data_valid : std_logic; + signal last_read_fee_data_fifo : std_logic; + signal reg_pseudo_token,next_pseudo_token: std_logic; + component counter_4bit port ( QOUT : out std_logic_vector(3 downto 0); @@ -244,64 +251,59 @@ architecture behavioral of tdc_readout_and_trb_interface is port ( CLK : in std_logic; RESET : in std_logic; - A_ADD_IN : in std_logic_vector(8 downto 0); A_RESERV_IN : in std_logic; --this is 11 bit of dataword A_AOD_IN : in std_logic; --address or data - -- A_ACK_IN : in std_logic; --acknowledgment A_DST_IN : in std_logic; - TOKEN_IN : in std_logic_vector(3 downto 0); TOKEN_TDC_READOUT_OUT : out std_logic_vector(3 downto 0); FLAG_EVENT_COUNTER_IN : in std_logic_vector(3 downto 0); DATA_BUS_OUT : out std_logic_vector(35 downto 0); --(25 downto 0); --(23 downto 0); DATA_VALID_OUT : out std_logic; FULL_FIFO_IN : in std_logic; - INIT_TDC_READOUT_IN : in std_logic; + INIT_TDC_READOUT_IN : in std_logic_vector(3 downto 0); + DATA_TYPE_SELECT_IN : in std_logic_vector(3 downto 0); --x"0"debug, + --x"1" 2 hit in one word DEBUG_REGISTER_OUT : out std_logic_vector(3 downto 0)); end component; - component fifo_8192depth_36width_dual_thresh + component fifo_8192depth_36width_dual_thresh_reg_out port ( - Data : in std_logic_vector(35 downto 0); - Clock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - AmEmptyThresh : in std_logic_vector(12 downto 0); - AmFullThresh : in std_logic_vector(12 downto 0); - Q : out std_logic_vector(35 downto 0); - WCNT : out std_logic_vector(13 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostEmpty : out std_logic; - AlmostFull : out std_logic); + Data : in std_logic_vector(35 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + AmEmptySetThresh : in std_logic_vector(12 downto 0); + AmEmptyClrThresh : in std_logic_vector(12 downto 0); + Q : out std_logic_vector(35 downto 0); + WCNT : out std_logic_vector(13 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostEmpty : out std_logic; + AlmostFull : out std_logic); end component; - component fifo_fall_through_512depth_52width + component fifo_fall_through_512depth_52width_reg_out port ( - Data : in std_logic_vector(51 downto 0); - Clock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(51 downto 0); - WCNT : out std_logic_vector(9 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostEmpty : out std_logic; - AlmostFull : out std_logic); + Data : in std_logic_vector(51 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + AmEmptySetThresh : in std_logic_vector(8 downto 0); + AmEmptyClrThresh : in std_logic_vector(8 downto 0); + Q : out std_logic_vector(51 downto 0); + WCNT : out std_logic_vector(9 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostEmpty : out std_logic; + AlmostFull : out std_logic); end component; + begin -- behavioral --- u0: counter_4bit --- port map ( --- QOUT => counter_4bit_i, --- UP => up_counter_4bit_i, --- CLK => CLK, --- RESET => RESET, --- CLR => clear_counter_4bit_i); - + A_ADO_PULSE: edge_to_pulse port map ( CLOCK => CLK, @@ -343,15 +345,9 @@ begin -- behavioral ENABLE_CLK_IN => '1', SIGNAL_IN => write_fee_data_fifo_i, PULSE_OUT => pulse_write_fee_data_fifo_i); - --- READ_HEADER_FI0 : edge_to_pulse --- port map ( --- CLOCK => CLK, --- ENABLE_CLK_IN => '1', --- SIGNAL_IN => read_header_fifo, --- PULSE_OUT => pulse_read_header_fifo); + - TDC_READOUT_INTERFACE : tdc_readout +TDC_READOUT_INTERFACE : tdc_readout port map ( CLK => CLK, RESET => RESET, @@ -368,50 +364,82 @@ begin -- behavioral DATA_VALID_OUT => write_fee_data_fifo_i, DATA_BUS_OUT => data_tdc_readout_i, - INIT_TDC_READOUT_IN => INIT_TDC_READOUT_IN(0), --init from common_stop_ + INIT_TDC_READOUT_IN => INIT_TDC_READOUT_IN, --init from common_stop_ --generator after send --token FULL_FIFO_IN => '0', + DATA_TYPE_SELECT_IN => DATA_TYPE_SELECT_IN, DEBUG_REGISTER_OUT => debug_register_tdc_readout_i); ------------------------------------------------------------------------------- -- OENP point test token back ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- => => . DEVI DECIDERE COME FARE LA CONNESSIONE DEL TOKEN TRA ENETITY <= <= +-- => => . DEVI DIDERE COME FARE LA CONNESSIONE DEL TOKEN TRA ENETITY <= <= ------------------------------------------------------------------------------- - TOKEN_TO_TRB_OUT <= reg_token_in(0); + --TOKEN_TO_TRB_OUT <= reg_token_in(0); + TOKEN_TO_TRB_OUT <= reg_pseudo_token; + -- TOKEN_TO_TRB_OUT <= '1' when (token_tdc_readout_i = x"1" or -- token_tdc_readout_i = x"2" or -- token_tdc_readout_i = x"3" or -- token_tdc_readout_i = x"4" or -- token_tdc_readout_i = x"5") else '0'; +------------------------------------------------------------------------------- + FEE_DATA_FIFO : fifo_8192depth_36width_dual_thresh_reg_out + port map ( + Data => data_tdc_readout_i, + Clock => CLK, + WrEn => write_fee_data_fifo_i, + RdEn => read_fee_data_fifo, + Reset => RESET, + AmEmptySetThresh => "0000000000000", + AmEmptyClrThresh => "0000000000000", + Q => fee_data_fifo_out_i, + WCNT => word_count_fee_data_fifo, + Empty => empty_flag_fee_data_fifo_i, + Full => full_flag_fee_data_fifo_i, + AlmostEmpty => almost_empty_flag_fee_data_fifo_i, + AlmostFull => almost_full_flag_fee_data_fifo_i); + + + not_empty_flag_fee_data_fifo_i <= not empty_flag_fee_data_fifo_i; + + process(CLK, counter_pulse_not_empty) + begin + if rising_edge(CLK) then + if (counter_pulse_not_empty = x"0001") then + pulse_not_empty_flag_fee_data_fifo_i <= '0'; + else + last_not_empty_flag_fee_data_fifo_i <= not_empty_flag_fee_data_fifo_i; + pulse_not_empty_flag_fee_data_fifo_i <= not_empty_flag_fee_data_fifo_i and not (last_not_empty_flag_fee_data_fifo_i); + end if; + end if; + end process; + process(CLK, pulse_not_empty_flag_fee_data_fifo_i, RESET, reg_token_in(0) ) + begin + if rising_edge(CLK) then + if (RESET = '1' or reg_token_in(0) = '1') then + counter_pulse_not_empty <= (others => '0'); + elsif (pulse_not_empty_flag_fee_data_fifo_i = '1') then + counter_pulse_not_empty <= counter_pulse_not_empty + '1'; + end if; + end if; +end process; - FEE_DATA_FIFO: fifo_8192depth_36width_dual_thresh - port map ( - Data => data_tdc_readout_i, - Clock => CLK, - WrEn => write_fee_data_fifo_i, - RdEn => read_fee_data_fifo, - Reset => RESET, - AmEmptyThresh => "0000000000000", - AmFullThresh => "1011101110000", - Q => fee_data_fifo_out_i, - WCNT => word_count_fee_data_fifo, - Empty => empty_flag_fee_data_fifo_i, - Full => full_flag_fee_data_fifo_i, - AlmostEmpty => almost_empty_flag_fee_data_fifo_i, - AlmostFull => almost_full_flag_fee_data_fifo_i); - - read_fee_data_fifo <= (reg_ipu_read and reg_read_fee_data_fifo_i) or push_read_fee_data_i or push_read_fee_data_1_i; - - HEADER_FIFO: fifo_fall_through_512depth_52width + read_fee_data_fifo <= (IPU_READ_IN and reg_read_fee_data_fifo_i) or + pulse_not_empty_flag_fee_data_fifo_i; +-- push_read_fee_data_i or push_read_fee_data_1_i; +------------------------------------------------------------------------------- +HEADER_FIFO: fifo_fall_through_512depth_52width_reg_out port map ( - Data => reg_first_header,--data_header_fifo_in_i, + Data => reg_first_header, Clock => CLK, WrEn => write_header_fifo_i, - RdEn => read_header_fifo, --reg_read_header_fifo_i, - Reset => RESET, + RdEn => read_header_fifo, + Reset => RESET, + AmEmptySetThresh => '0'& x"00", + AmEmptyClrThresh => '0' & x"00", Q => header_data_fifo_out_i, WCNT => word_count_header_fifo, Empty => empty_flag_header_data_fifo_i, @@ -422,7 +450,35 @@ begin -- behavioral -- reg_ipu_read is setted by TRBNET, -- reg_read_header_fifo_i is defined by the state machine ------------------------------------------------------------------------------- -read_header_fifo <= (reg_ipu_read and reg_read_header_fifo_i) or push_read_header_data_i; +read_header_fifo <= (IPU_READ_IN and reg_read_header_fifo_i) or + push_read_header_data_i or + pulse_not_empty_flag_header_data_fifo_i; + +------------------------------------------------------------------------------- + not_empty_flag_header_data_fifo_i <= not empty_flag_header_data_fifo_i; + + process(CLK, counter_pulse_not_empty_header) + begin + if rising_edge(CLK) then + if (counter_pulse_not_empty_header = x"0001") then + pulse_not_empty_flag_header_data_fifo_i <= '0'; + else + last_not_empty_flag_header_data_fifo_i <= not_empty_flag_header_data_fifo_i; + pulse_not_empty_flag_header_data_fifo_i <= not_empty_flag_header_data_fifo_i and not (last_not_empty_flag_header_data_fifo_i); + end if; + end if; + end process; + + process(CLK, pulse_not_empty_flag_header_data_fifo_i, RESET, next_ipu_finished ) + begin + if rising_edge(CLK) then + if (RESET = '1' or next_ipu_finished = '1') then + counter_pulse_not_empty_header <= (others => '0'); + elsif (pulse_not_empty_flag_header_data_fifo_i = '1') then + counter_pulse_not_empty_header <= counter_pulse_not_empty_header + '1'; + end if; + end if; +end process; ------------------------------------------------------------------------------- -- I WANT THE FIRST DATAWORD TO APPEAR AT FIFO HEADER @@ -441,22 +497,16 @@ read_header_fifo <= (reg_ipu_read and reg_read_header_fifo_i) or push_read_heade end if; end process; -------------------------------------------------------------------------------- +----------------------------------------------------------------------------- -- register empty flag for fee data -------------------------------------------------------------------------------- - process (CLK, RESET) - begin - if rising_edge(CLK) then --- if (RESET = '1') then --- reg_empty_flag_fee_data_fifo_i <= '0'; --- last_empty_flag_fee_data_fifo_i <= '0'; --- else - last_empty_flag_fee_data_fifo_i <= empty_flag_fee_data_fifo_i; - reg_empty_flag_fee_data_fifo_i <= last_empty_flag_fee_data_fifo_i; - --- end if; - end if; - end process; +----------------------------------------------------------------------------- + process (CLK, RESET) + begin + if rising_edge(CLK) then + last_empty_flag_fee_data_fifo_i <= empty_flag_fee_data_fifo_i; + reg_empty_flag_fee_data_fifo_i <= last_empty_flag_fee_data_fifo_i; + end if; + end process; process (CLK, pulse_write_header_fifo_i) @@ -482,13 +532,15 @@ read_header_fifo <= (reg_ipu_read and reg_read_header_fifo_i) or push_read_heade if rising_edge(CLK) then if (RESET = '1') then push_read_fee_data_i <= '0'; - elsif (pulse_write_fee_data_fifo_i = '1' and counter_pulse_write_fee_data_fifo_i = X"0000") then - push_read_fee_data_i <= '1'; - else + elsif (counter_pulse_write_fee_data_fifo_i >= x"0001") then push_read_fee_data_i <= '0'; - end if; + elsif (pulse_write_fee_data_fifo_i = '1' and counter_pulse_write_fee_data_fifo_i = X"0000") then + push_read_fee_data_i <= '1'; + else + push_read_fee_data_i <= push_read_fee_data_i; end if; - end process; + end if; + end process; process (CLK, pulse_write_fee_data_fifo_i) begin @@ -511,10 +563,13 @@ read_header_fifo <= (reg_ipu_read and reg_read_header_fifo_i) or push_read_heade -- OUTPUT CONNECTIONS ------------------------------------------------------------------------------- LVL1_ERROR_PATTERN_OUT <= x"00000000"; - LVL1_TRG_RELEASE_OUT <= reg_lvl1_busy_i; + LVL1_TRG_RELEASE_OUT <= reg_empty_flag_fee_data_fifo_i and (not next_lvl1_busy_i); IPU_DATA_OUT <= next_data_to_trb_net(31 downto 0); - IPU_DATAREADY_OUT <= next_ipu_data_ready;--reg_ipu_data_ready; + IPU_DATAREADY_OUT <= (fee_data_fifo_data_valid and next_ipu_data_ready) when + (current_state_fsm_multiplexer=send_data_state_fsm_multiplexer) else + reg_ipu_data_ready; + IPU_READOUT_FINISHED_OUT <= reg_ipu_finished; IPU_LENGTH_OUT <= reg_first_header(51 downto 36); @@ -567,9 +622,9 @@ read_header_fifo <= (reg_ipu_read and reg_read_header_fifo_i) or push_read_heade end if; end process; - + -- process init_signals process (CLK) - begin -- process init_signals + begin if rising_edge(CLK) then if RESET = '1' then current_state <= idle_state; @@ -612,25 +667,6 @@ read_header_fifo <= (reg_ipu_read and reg_read_header_fifo_i) or push_read_heade next_state <= idle_state; end if; ------------------------------------------------------------------------ ---SEND FIRST HEADER ---I can send the first header as soon as I receive the ---trigger info. It is important that this header has the same tag of the ---corrisponing event which is being collected. ------------------------------------------------------------------------ --- when send_first_header_state => --- next_debug_register_fsm_header <= x"01"; --- next_write_header_fifo_i <= '0'; --- data_header_fifo_in_i <= first_header; --- next_lvl1_busy_i <= '0'; --- next_state <= dummy_wait_1_header_state; - --- when dummy_wait_1_header_state => --- next_debug_register_fsm_header <= x"01"; --- next_write_header_fifo_i <= '0'; --- data_header_fifo_in_i <= first_header; --- next_lvl1_busy_i <= '0'; --- next_state <= wait_for_token; ----------------------------------------------------------------------- --WAIT FOR TOKEN: --I have to wait the event which is being collected is complete. @@ -652,7 +688,7 @@ read_header_fifo <= (reg_ipu_read and reg_read_header_fifo_i) or push_read_heade end if; ------------------------------------------------------------------------------- --- FOR THE MOMENT WE DECIDED TO SEND ONE HEADER +-- SEND HEADER ------------------------------------------------------------------------------- when send_second_header_state => next_debug_register_fsm_header <= x"03"; @@ -669,6 +705,7 @@ read_header_fifo <= (reg_ipu_read and reg_read_header_fifo_i) or push_read_heade data_header_fifo_in_i <= reg_first_header; next_lvl1_busy_i <= '1'; if (almost_empty_flag_fee_data_fifo_i = '0') then + -- clear_counter_pulse_not_empty <= '1'; next_state <= send_second_header_state; else next_state <= busy_header_state; @@ -699,9 +736,10 @@ read_header_fifo <= (reg_ipu_read and reg_read_header_fifo_i) or push_read_heade reg_lvl1_error_pattern <= (others => '0'); reg_lvl1_trg_release <= '0'; reg_ipu_data <= (others => '0'); - -- reg_ipu_data_ready <= '0'; + reg_ipu_data_ready <= '0'; reg_ipu_finished <= '0'; - -- reg_ipu_length <= (others => '0'); + reg_pseudo_token <= '0'; + -- reg_ipu_length <= (others => '0'); else current_state_fsm_multiplexer <= next_state_fsm_multiplexer; reg_debug_register_fsm_multiplexer <= next_debug_register_fsm_multiplexer; @@ -711,8 +749,9 @@ read_header_fifo <= (reg_ipu_read and reg_read_header_fifo_i) or push_read_heade reg_lvl1_error_pattern <= next_lvl1_error_pattern; reg_lvl1_trg_release <= next_lvl1_trg_release; reg_ipu_data <= next_ipu_data; - --reg_ipu_data_ready <= next_ipu_data_ready; - reg_ipu_finished <= next_ipu_finished; + reg_ipu_data_ready <= next_ipu_data_ready; + reg_ipu_finished <= next_ipu_finished; + reg_pseudo_token <= next_pseudo_token; -- reg_ipu_length <= next_ipu_length; end if; end if; @@ -745,6 +784,7 @@ read_header_fifo <= (reg_ipu_read and reg_read_header_fifo_i) or push_read_heade -- next_ipu_length <= (others => '0'); clear_counter_word_read_from_trbnet <= '0'; push_read_fee_data_1_i <= '0'; + next_pseudo_token <= '0'; -- push_read_fee_data_i <= '0'; -- push_read_header_data_i <= '0'; @@ -757,7 +797,6 @@ read_header_fifo <= (reg_ipu_read and reg_read_header_fifo_i) or push_read_heade next_ipu_data_ready <= '0'; next_data_to_trb_net <= header_data_fifo_out_i(31 downto 0); --start readout if IPU requests comes - --if (INIT_TDC_READOUT_IN(0) = '1') then --TRIGGER FROM TRB NET if (pulse_ipu_start_readout = '1') then next_state_fsm_multiplexer <= wait_for_complete_event_fsm_multiplexer; else @@ -800,12 +839,13 @@ read_header_fifo <= (reg_ipu_read and reg_read_header_fifo_i) or push_read_heade next_debug_register_fsm_multiplexer <= x"03"; next_read_fee_data_fifo_i <= '0'; next_read_header_fifo_i <= '1'; - next_ipu_data_ready <= '1'; --trbnet can read + next_ipu_data_ready <= not IPU_READ_IN or not reg_ipu_data_ready; --trbnet can read next_data_to_trb_net <= header_data_fifo_out_i(31 downto 0); --header_fifo if (read_header_fifo = '1') then --this read correspond to the header --read from trbnet - -- next_ipu_data_ready <= '0'; - push_read_fee_data_1_i <= '1'; + --next_read_header_fifo_i <= '0'; + --next_ipu_data_ready <= '0'; + -- push_read_fee_data_1_i <= '1'; next_state_fsm_multiplexer <= dummy_wait_1_fsm_multiplexer; else next_state_fsm_multiplexer <= send_first_and_second_header_state_fsm_multiplexer; @@ -819,45 +859,29 @@ read_header_fifo <= (reg_ipu_read and reg_read_header_fifo_i) or push_read_heade next_ipu_data_ready <= '0'; --trbnet cannot read next_data_to_trb_net <= fee_data_fifo_out_i(31 downto 0); next_state_fsm_multiplexer <= send_data_state_fsm_multiplexer; - -- next_state_fsm_multiplexer <= dummy_wait_3_fsm_multiplexer; - --- when dummy_wait_3_fsm_multiplexer => --- next_debug_register_fsm_multiplexer <= x"01"; --- next_read_fee_data_fifo_i <= '0'; --- next_read_header_fifo_i <= '0'; --- next_ipu_data_ready <= '0'; --- next_data_to_trb_net <= fee_data_fifo_out_i; --- next_state_fsm_multiplexer <= send_data_state_fsm_multiplexer; + ------------------------------------------------------------------------------- -- Connect fee_data_fifo to trbnet. -- I leave connected till the flag change to next event ------------------------------------------------------------------------------- when send_data_state_fsm_multiplexer => next_debug_register_fsm_multiplexer <= x"05"; - next_read_fee_data_fifo_i <= '1'; - next_read_header_fifo_i <= '0'; - next_ipu_data_ready <= '1'; --trbnet can read - next_data_to_trb_net <= fee_data_fifo_out_i(31 downto 0); --data_fifo + next_read_fee_data_fifo_i <= '1'; + next_read_header_fifo_i <= '0'; + next_ipu_data_ready <= '1'; --trbnet can read + next_data_to_trb_net <= fee_data_fifo_out_i(31 downto 0); --data_fifo --chenge state if event you read from the fifo is different from the --event you are sending or if the fifo does not contain anymore data. - if ( (fee_data_fifo_out_i(35 downto 32) /= reg_flag_in_header ) or - (reg_empty_flag_fee_data_fifo_i = '1') ) then - next_ipu_data_ready <= '0'; - next_read_fee_data_fifo_i <= '0'; - next_state_fsm_multiplexer <= dummy_wait_2_fsm_multiplexer; - else - next_state_fsm_multiplexer <= send_data_state_fsm_multiplexer; - end if; - - when dummy_wait_2_fsm_multiplexer => - next_debug_register_fsm_multiplexer <= x"06"; - next_read_fee_data_fifo_i <= '0'; - next_read_header_fifo_i <= '0'; - next_ipu_data_ready <= '0'; - next_data_to_trb_net <= fee_data_fifo_out_i(31 downto 0); --data_fifo - next_ipu_finished <= '1'; --transmission terminated - next_state_fsm_multiplexer <= end_of_event_transfer_fsm_multiplexer; - +-- if ( (fee_data_fifo_out_i(35 downto 32) /= reg_flag_in_header ) or +-- (reg_empty_flag_fee_data_fifo_i = '1') ) then + if ( reg_empty_flag_fee_data_fifo_i = '1' ) then + next_ipu_data_ready <= '0'; + next_read_fee_data_fifo_i <= '0'; + next_state_fsm_multiplexer <= end_of_event_transfer_fsm_multiplexer; + else + next_state_fsm_multiplexer <= send_data_state_fsm_multiplexer; + end if; + --stay if no tok back and fifo empty for when end_of_event_transfer_fsm_multiplexer => next_debug_register_fsm_multiplexer <= x"07"; next_read_fee_data_fifo_i <= '0'; @@ -866,9 +890,11 @@ read_header_fifo <= (reg_ipu_read and reg_read_header_fifo_i) or push_read_heade next_data_to_trb_net <= fee_data_fifo_out_i(31 downto 0); next_ipu_finished <= '1'; --transmission terminated clear_counter_word_read_from_trbnet <= '1'; - --push_read_fee_data_1_i <= '1'; + push_read_fee_data_1_i <= '1'; + if (reg_ipu_start_readout_in = '0') then - next_state_fsm_multiplexer <= idle_state_fsm_multiplexer; + next_pseudo_token <= '1'; + next_state_fsm_multiplexer <= idle_state_fsm_multiplexer; else next_state_fsm_multiplexer <= end_of_event_transfer_fsm_multiplexer; end if; @@ -880,26 +906,38 @@ read_header_fifo <= (reg_ipu_read and reg_read_header_fifo_i) or push_read_heade end case; end process; +process (CLK) +begin + if rising_edge(CLK) then + last_read_fee_data_fifo <= read_fee_data_fifo; + if last_read_fee_data_fifo = '1' and last_empty_flag_fee_data_fifo_i = '0' then + fee_data_fifo_data_valid <= '1'; + elsif IPU_READ_IN = '1' and current_state_fsm_multiplexer = send_data_state_fsm_multiplexer then + fee_data_fifo_data_valid <= '0'; + end if; + end if; + + +end process; + ------------------------------------------------------------------------------- -- EVENT FLAG GENERATOR: -- For each event I generate a flag (4 bits), which will be used to distinguish -- the events. The flag marks the dataword and the header. ------------------------------------------------------------------------------- - process (CLK, RESET, pulse_init_tdc_readout) - begin - if (rising_edge(CLK)) then - if RESET = '1' then - flag_event_counter <= (others => '0'); - --WRONG!!!!!!!!!!!!! - --elsif (pulse_reg_lvl1_trg_received = '1') then - elsif (pulse_init_tdc_readout = '1') then - flag_event_counter <= flag_event_counter + 1; - else - flag_event_counter <= flag_event_counter; - end if; - end if; - end process; - + process (CLK, RESET, pulse_init_tdc_readout) + begin + if (rising_edge(CLK)) then + if RESET = '1' then + flag_event_counter <= (others => '0'); + elsif (pulse_init_tdc_readout = '1') then + flag_event_counter <= flag_event_counter + 1; + else + flag_event_counter <= flag_event_counter; + end if; + end if; + end process; + ------------------------------------------------------------------------------- -- I see which trigger has been processed and I store it. I use this -- information in the first dataword @@ -969,8 +1007,7 @@ DEBUG_REGISTER_0 <= x"0" & reg_debug_register_fsm_multiplexer(3 downto 0); -- EVENT COMPLETE in FIFO: -- the counter is used to check how many event complete are stored in the fifo. ----------------------------------------------------------------------------- -process(CLK, RESET, pulse_init_tdc_readout, - pulse_init_tdc_readout, reg_token_in) +process(CLK, RESET, pulse_init_tdc_readout, reg_token_in) begin if (rising_edge(CLK)) then if (RESET = '1') then @@ -1054,6 +1091,10 @@ begin end if; end process; +------------------------------------------------------------------------------- +-- read data fifo +------------------------------------------------------------------------------- + ------------------------------------------------------------------------------- -- AVERAGE NUMBER OF DATAWORDS PER EVENT ON THIS BUS. -- 2.43.0