From 43094fa375f9b9e3300e3c41c92cca79d9aa4e8a Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 15 Dec 2022 12:07:41 +0100 Subject: [PATCH] add CTS busy signal as option in output multiplexer --- cts/source/cts.vhd | 16 ++++++++++------ cts/source/cts_trigger.vhd | 12 ++++++++---- 2 files changed, 18 insertions(+), 10 deletions(-) diff --git a/cts/source/cts.vhd b/cts/source/cts.vhd index 2794fcf..580b87b 100755 --- a/cts/source/cts.vhd +++ b/cts/source/cts.vhd @@ -345,8 +345,10 @@ architecture RTL of CTS is signal trg_information_reg : std_logic_vector(23 downto 0); - signal busy_out_counter : unsigned(3 downto 0); - signal busy_out_i, busy_end_i : std_logic; + signal busy_out_i : std_logic; + --japanese synchronous read-out option + --signal busy_out_counter : unsigned(3 downto 0); + --signal busy_out_i : std_logic; begin assert(EFFECTIVE_INPUT_COUNT > 0) report "The CTS requires atleast 1 input or input multiplexer"; @@ -393,7 +395,7 @@ begin debug_lvl1_limit_i <= (others => '1'); else - case(td_fsm_i) is + case (td_fsm_i) is when TD_FSM_IDLE => if to_integer(debug_lvl1_limit_i) = 0 then td_fsm_i <= TD_FSM_DEBUG_LIMIT_REACHED; @@ -580,11 +582,12 @@ begin proc_busyout : process begin wait until rising_edge(CLK); if td_fsm_i = TD_FSM_IDLE then - TRIGGER_BUSY_OUT <= '0'; + busy_out_i <= '0'; else - TRIGGER_BUSY_OUT <= '1'; + busy_out_i <= '1'; end if; end process; +TRIGGER_BUSY_OUT <= busy_out_i; ---------------------------------------------------- -- Busy out option for synchronous japanese setup @@ -784,7 +787,7 @@ begin -- Trigger ----------------------------------------- - my_trigger : CTS_TRIGGER + my_trigger : entity work.CTS_TRIGGER generic map ( TRIGGER_INPUT_COUNT => TRIGGER_INPUT_COUNT, TRIGGER_COIN_COUNT => TRIGGER_COIN_COUNT, @@ -823,6 +826,7 @@ begin TRIGGER_OUT => trigger_i, TRIGGER_TYPE_OUT => trigger_type_i, TRIGGER_BITMASK_OUT => trigger_bitmask_i, + TRIGGER_BUSY_IN => busy_out_i, INPUT_COUNTERS_OUT => input_counters_i, INPUT_EDGE_COUNTERS_OUT => input_edge_counters_i, diff --git a/cts/source/cts_trigger.vhd b/cts/source/cts_trigger.vhd index 5ba02b6..7bba9b6 100755 --- a/cts/source/cts_trigger.vhd +++ b/cts/source/cts_trigger.vhd @@ -50,6 +50,7 @@ entity CTS_TRIGGER is TRIGGER_OUT : out std_logic; -- asserted when trigger detected TRIGGER_TYPE_OUT : out std_logic_vector(3 downto 0); TRIGGER_BITMASK_OUT : out std_logic_vector(15 downto 0); + TRIGGER_BUSY_IN : in std_logic; -- Counters INPUT_COUNTERS_OUT : out std_logic_vector(32 * (TRIGGER_INPUT_COUNT+TRIGGER_ADDON_COUNT) - 1 downto 0) := (others => '0'); @@ -146,7 +147,7 @@ architecture RTL of CTS_TRIGGER is type output_multiplexer_configs_t is array(MAX(0,OUTPUT_MULTIPLEXERS - 1) downto 0) of std_logic_vector(7 downto 0); signal output_multiplexer_configs_i : output_multiplexer_configs_t; - signal output_multiplexer_ins_i : std_logic_vector(16 + 2*TRIGGER_INPUT_COUNT + ADDON_LINE_COUNT + TRIGGER_ADDON_COUNT downto 0); + signal output_multiplexer_ins_i : std_logic_vector(16 + 2*TRIGGER_INPUT_COUNT + ADDON_LINE_COUNT + TRIGGER_ADDON_COUNT + 1 downto 0); -- Trigger Type Assoc type trigger_type_assoc_t is array(0 to 15) of std_logic_vector(3 downto 0); @@ -214,12 +215,15 @@ begin output_multiplexer_ins_i(i) <= CLK_IN; i := i + 1; + output_multiplexer_ins_i(i) <= TRIGGER_BUSY_IN; + i := i + 1; + end process; proc_out_mux: process (output_multiplexer_ins_i, output_multiplexer_configs_i) is - variable tmp : integer range 0 to 255 := 0; - variable idx : integer range 0 to output_multiplexer_ins_i'high := 0; - variable test : std_logic_vector(31 downto 0); + --variable tmp : integer range 0 to 255 := 0; + --variable idx : integer range 0 to output_multiplexer_ins_i'high := 0; + --variable test : std_logic_vector(31 downto 0); begin for j in 0 to output_multiplexers - 1 loop output_multiplexers_out(j) <= output_multiplexer_ins_i(to_integer( unsigned( output_multiplexer_configs_i(j)))); -- 2.43.0