From 43d40d26391b76dd534dd8896eb38f6957d0a69f Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 9 Aug 2021 14:01:24 +0200 Subject: [PATCH] add new ECP5 fifos --- lattice/ecp5/FIFO/fifo_36x32/fifo_36x32.lpc | 50 + lattice/ecp5/FIFO/fifo_36x32/fifo_36x32.vhd | 671 ++++++++ .../FIFO/fifo_36x32_oreg/fifo_36x32_oreg.lpc | 50 + .../FIFO/fifo_36x32_oreg/fifo_36x32_oreg.vhd | 671 ++++++++ .../fifo_36x512_dualport_oreg.lpc | 53 + .../fifo_36x512_dualport_oreg.vhd | 1351 +++++++++++++++++ .../lattice_ecp5_fifo_36x16_dualport_oreg.lpc | 8 +- .../lattice_ecp5_fifo_36x16_dualport_oreg.vhd | 30 +- 8 files changed, 2865 insertions(+), 19 deletions(-) create mode 100644 lattice/ecp5/FIFO/fifo_36x32/fifo_36x32.lpc create mode 100644 lattice/ecp5/FIFO/fifo_36x32/fifo_36x32.vhd create mode 100644 lattice/ecp5/FIFO/fifo_36x32_oreg/fifo_36x32_oreg.lpc create mode 100644 lattice/ecp5/FIFO/fifo_36x32_oreg/fifo_36x32_oreg.vhd create mode 100644 lattice/ecp5/FIFO/fifo_36x512_dualport_oreg/fifo_36x512_dualport_oreg.lpc create mode 100644 lattice/ecp5/FIFO/fifo_36x512_dualport_oreg/fifo_36x512_dualport_oreg.vhd diff --git a/lattice/ecp5/FIFO/fifo_36x32/fifo_36x32.lpc b/lattice/ecp5/FIFO/fifo_36x32/fifo_36x32.lpc new file mode 100644 index 0000000..88550d3 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x32/fifo_36x32.lpc @@ -0,0 +1,50 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-45F +PartName=LFE5UM-45F-8BG381C +SpeedGrade=8 +Package=CABGA381 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=5.1 +ModuleName=fifo_36x32 +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=07/21/2021 +Time=17:37:39 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=32 +Width=36 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Dynamic - Single Threshold +PfAssert=10 +PfDeassert=506 +Reset=Async +Reset1=Sync +RDataCount=1 +EnECC=0 +EnFWFT=0 + +[Command] +cmd_line= -w -n fifo_36x32 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 32 -width 36 -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill diff --git a/lattice/ecp5/FIFO/fifo_36x32/fifo_36x32.vhd b/lattice/ecp5/FIFO/fifo_36x32/fifo_36x32.vhd new file mode 100644 index 0000000..c8ab84a --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x32/fifo_36x32.vhd @@ -0,0 +1,671 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.11.2.446 +-- Module Version: 5.1 +--/d/jspc29/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x32 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 32 -width 36 -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /local/trb/git/trbnet/lattice/ecp5/FIFO/fifo_36x32/fifo_36x32.fdc + +-- Wed Jul 21 17:37:42 2021 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity fifo_36x32 is + port ( + Data: in std_logic_vector(35 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + AmFullThresh: in std_logic_vector(4 downto 0); + Q: out std_logic_vector(35 downto 0); + WCNT: out std_logic_vector(5 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end fifo_36x32; + +architecture Structure of fifo_36x32 is + + -- internal signal declarations + signal invout_2: std_logic; + signal invout_1: std_logic; + signal rden_i_inv: std_logic; + signal invout_0: std_logic; + signal r_nw: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal rptr_5: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal ifcount_5: std_logic; + signal co2: std_logic; + signal co1: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_2: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_2: std_logic; + signal wren_i_inv: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co2_1: std_logic; + signal co1_3: std_logic; + signal wcount_5: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co2_2: std_logic; + signal co1_4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal wcnt_sub_0: std_logic; + signal rptr_0: std_logic; + signal cnt_con_inv: std_logic; + signal wcount_0: std_logic; + signal cnt_con: std_logic; + signal precin: std_logic; + signal wcnt_sub_1: std_logic; + signal wcnt_sub_2: std_logic; + signal rptr_2: std_logic; + signal rptr_1: std_logic; + signal wcount_2: std_logic; + signal wcount_1: std_logic; + signal co0_5: std_logic; + signal wcnt_sub_3: std_logic; + signal wcnt_sub_4: std_logic; + signal rptr_4: std_logic; + signal rptr_3: std_logic; + signal wcount_4: std_logic; + signal wcount_3: std_logic; + signal co1_5: std_logic; + signal wcnt_sub_5: std_logic; + signal wcnt_sub_msb: std_logic; + signal co2_3: std_logic; + signal wren_i: std_logic; + signal cmp_ci_2: std_logic; + signal wcnt_reg_0: std_logic; + signal wcnt_reg_1: std_logic; + signal co0_6: std_logic; + signal wcnt_reg_2: std_logic; + signal wcnt_reg_3: std_logic; + signal co1_6: std_logic; + signal wcnt_reg_4: std_logic; + signal wcnt_reg_5: std_logic; + signal af_set: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + signal af_set_c: std_logic; + + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_36x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t5: AND2 + port map (A=>WrEn, B=>invout_2, Z=>wren_i); + + INV_5: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t4: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_4: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t3: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t2: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_3: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_2: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + AND2_t1: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_1: INV + port map (A=>wren_i, Z=>invout_0); + + XOR2_t0: XOR2 + port map (A=>wcount_5, B=>rptr_5, Z=>wcnt_sub_msb); + + INV_0: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + pdp_ram_0_0_0: PDPW16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "ENABLED", + RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36, + DATA_WIDTH_W=> 36) + port map (DI35=>Data(35), DI34=>Data(34), DI33=>Data(33), + DI32=>Data(32), DI31=>Data(31), DI30=>Data(30), + DI29=>Data(29), DI28=>Data(28), DI27=>Data(27), + DI26=>Data(26), DI25=>Data(25), DI24=>Data(24), + DI23=>Data(23), DI22=>Data(22), DI21=>Data(21), + DI20=>Data(20), DI19=>Data(19), DI18=>Data(18), + DI17=>Data(17), DI16=>Data(16), DI15=>Data(15), + DI14=>Data(14), DI13=>Data(13), DI12=>Data(12), + DI11=>Data(11), DI10=>Data(10), DI9=>Data(9), DI8=>Data(8), + DI7=>Data(7), DI6=>Data(6), DI5=>Data(5), DI4=>Data(4), + DI3=>Data(3), DI2=>Data(2), DI1=>Data(1), DI0=>Data(0), + ADW8=>scuba_vlo, ADW7=>scuba_vlo, ADW6=>scuba_vlo, + ADW5=>scuba_vlo, ADW4=>wptr_4, ADW3=>wptr_3, ADW2=>wptr_2, + ADW1=>wptr_1, ADW0=>wptr_0, BE3=>scuba_vhi, BE2=>scuba_vhi, + BE1=>scuba_vhi, BE0=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, + CSW2=>scuba_vlo, CSW1=>scuba_vlo, CSW0=>scuba_vhi, + ADR13=>scuba_vlo, ADR12=>scuba_vlo, ADR11=>scuba_vlo, + ADR10=>scuba_vlo, ADR9=>rptr_4, ADR8=>rptr_3, ADR7=>rptr_2, + ADR6=>rptr_1, ADR5=>rptr_0, ADR4=>scuba_vlo, ADR3=>scuba_vlo, + ADR2=>scuba_vlo, ADR1=>scuba_vlo, ADR0=>scuba_vlo, + CER=>rden_i, OCER=>rden_i, CLKR=>Clock, CSR2=>scuba_vlo, + CSR1=>scuba_vlo, CSR0=>scuba_vlo, RST=>Reset, DO35=>Q(17), + DO34=>Q(16), DO33=>Q(15), DO32=>Q(14), DO31=>Q(13), + DO30=>Q(12), DO29=>Q(11), DO28=>Q(10), DO27=>Q(9), + DO26=>Q(8), DO25=>Q(7), DO24=>Q(6), DO23=>Q(5), DO22=>Q(4), + DO21=>Q(3), DO20=>Q(2), DO19=>Q(1), DO18=>Q(0), DO17=>Q(35), + DO16=>Q(34), DO15=>Q(33), DO14=>Q(32), DO13=>Q(31), + DO12=>Q(30), DO11=>Q(29), DO10=>Q(28), DO9=>Q(27), + DO8=>Q(26), DO7=>Q(25), DO6=>Q(24), DO5=>Q(23), DO4=>Q(22), + DO3=>Q(21), DO2=>Q(20), DO1=>Q(19), DO0=>Q(18)); + + FF_38: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_37: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_36: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_35: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_34: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_33: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_32: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_31: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_30: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, + Q=>wcount_0); + + FF_29: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_28: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_27: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_26: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_25: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_24: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, + Q=>rcount_0); + + FF_23: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_22: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_21: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_20: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_19: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_18: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_0); + + FF_17: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_1); + + FF_16: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_2); + + FF_15: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_3); + + FF_14: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_4); + + FF_13: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_5); + + FF_12: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_0); + + FF_11: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_1); + + FF_10: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_2); + + FF_9: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_3); + + FF_8: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_4); + + FF_7: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_5); + + FF_6: FD1S3DX + port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0); + + FF_5: FD1S3DX + port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1); + + FF_4: FD1S3DX + port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2); + + FF_3: FD1S3DX + port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3); + + FF_2: FD1S3DX + port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4); + + FF_1: FD1S3DX + port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5); + + FF_0: FD1S3DX + port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull); + + bdcnt_bctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci); + + bdcnt_bctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0); + + bdcnt_bctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1); + + bdcnt_bctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2); + + e_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci); + + e_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1); + + e_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, + B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1); + + e_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, + B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, + COUT=>cmp_le_1_c); + + a0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, + COUT=>open); + + g_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1); + + g_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2); + + g_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2); + + g_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i_inv, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_2, S0=>open, S1=>open, COUT=>cmp_ge_d1_c); + + a1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, + COUT=>open); + + w_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci); + + w_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, + COUT=>co0_3); + + w_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, + COUT=>co1_3); + + w_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, + COUT=>co2_1); + + r_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci); + + r_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, + COUT=>co0_4); + + r_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, + COUT=>co1_4); + + r_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, + COUT=>co2_2); + + precin_inst182: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", + INIT0=> X"0000") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin); + + wcnt_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5); + + wcnt_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5); + + wcnt_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, COUT=>co2_3); + + wcnt_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_3, S0=>wcnt_sub_5, S1=>open, + COUT=>open); + + af_set_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2); + + af_set_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), + B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, + S1=>open, COUT=>co0_6); + + af_set_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), + B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, + COUT=>co1_6); + + af_set_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, + COUT=>af_set_c); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open, + COUT=>open); + + WCNT(0) <= fcount_0; + WCNT(1) <= fcount_1; + WCNT(2) <= fcount_2; + WCNT(3) <= fcount_3; + WCNT(4) <= fcount_4; + WCNT(5) <= fcount_5; + Empty <= empty_i; + Full <= full_i; +end Structure; diff --git a/lattice/ecp5/FIFO/fifo_36x32_oreg/fifo_36x32_oreg.lpc b/lattice/ecp5/FIFO/fifo_36x32_oreg/fifo_36x32_oreg.lpc new file mode 100644 index 0000000..e415886 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x32_oreg/fifo_36x32_oreg.lpc @@ -0,0 +1,50 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-45F +PartName=LFE5UM-45F-8BG381C +SpeedGrade=8 +Package=CABGA381 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=5.1 +ModuleName=fifo_36x32_oreg +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=07/20/2021 +Time=10:53:25 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=32 +Width=36 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Single Threshold +PeAssert=1 +PeDeassert=12 +FullFlg=1 +PfMode=Dynamic - Single Threshold +PfAssert=10 +PfDeassert=506 +Reset=Async +Reset1=Sync +RDataCount=1 +EnECC=0 +EnFWFT=0 + +[Command] +cmd_line= -w -n fifo_36x32_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 32 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill diff --git a/lattice/ecp5/FIFO/fifo_36x32_oreg/fifo_36x32_oreg.vhd b/lattice/ecp5/FIFO/fifo_36x32_oreg/fifo_36x32_oreg.vhd new file mode 100644 index 0000000..b1378c4 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x32_oreg/fifo_36x32_oreg.vhd @@ -0,0 +1,671 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.11.2.446 +-- Module Version: 5.1 +--/d/jspc29/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x32_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 32 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /local/trb/git/trbnet/lattice/ecp5/FIFO/fifo_36x32_oreg/fifo_36x32_oreg.fdc + +-- Tue Jul 20 10:53:41 2021 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity fifo_36x32_oreg is + port ( + Data: in std_logic_vector(35 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + AmFullThresh: in std_logic_vector(4 downto 0); + Q: out std_logic_vector(35 downto 0); + WCNT: out std_logic_vector(5 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end fifo_36x32_oreg; + +architecture Structure of fifo_36x32_oreg is + + -- internal signal declarations + signal invout_2: std_logic; + signal invout_1: std_logic; + signal rden_i_inv: std_logic; + signal invout_0: std_logic; + signal r_nw: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal rptr_5: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal ifcount_5: std_logic; + signal co2: std_logic; + signal co1: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_2: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_2: std_logic; + signal wren_i_inv: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co2_1: std_logic; + signal co1_3: std_logic; + signal wcount_5: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co2_2: std_logic; + signal co1_4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal wcnt_sub_0: std_logic; + signal rptr_0: std_logic; + signal cnt_con_inv: std_logic; + signal wcount_0: std_logic; + signal cnt_con: std_logic; + signal precin: std_logic; + signal wcnt_sub_1: std_logic; + signal wcnt_sub_2: std_logic; + signal rptr_2: std_logic; + signal rptr_1: std_logic; + signal wcount_2: std_logic; + signal wcount_1: std_logic; + signal co0_5: std_logic; + signal wcnt_sub_3: std_logic; + signal wcnt_sub_4: std_logic; + signal rptr_4: std_logic; + signal rptr_3: std_logic; + signal wcount_4: std_logic; + signal wcount_3: std_logic; + signal co1_5: std_logic; + signal wcnt_sub_5: std_logic; + signal wcnt_sub_msb: std_logic; + signal co2_3: std_logic; + signal wren_i: std_logic; + signal cmp_ci_2: std_logic; + signal wcnt_reg_0: std_logic; + signal wcnt_reg_1: std_logic; + signal co0_6: std_logic; + signal wcnt_reg_2: std_logic; + signal wcnt_reg_3: std_logic; + signal co1_6: std_logic; + signal wcnt_reg_4: std_logic; + signal wcnt_reg_5: std_logic; + signal af_set: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + signal af_set_c: std_logic; + + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_36x32_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t5: AND2 + port map (A=>WrEn, B=>invout_2, Z=>wren_i); + + INV_5: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t4: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_4: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t3: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t2: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_3: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_2: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + AND2_t1: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_1: INV + port map (A=>wren_i, Z=>invout_0); + + XOR2_t0: XOR2 + port map (A=>wcount_5, B=>rptr_5, Z=>wcnt_sub_msb); + + INV_0: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + pdp_ram_0_0_0: PDPW16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "ENABLED", + RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, + DATA_WIDTH_W=> 36) + port map (DI35=>Data(35), DI34=>Data(34), DI33=>Data(33), + DI32=>Data(32), DI31=>Data(31), DI30=>Data(30), + DI29=>Data(29), DI28=>Data(28), DI27=>Data(27), + DI26=>Data(26), DI25=>Data(25), DI24=>Data(24), + DI23=>Data(23), DI22=>Data(22), DI21=>Data(21), + DI20=>Data(20), DI19=>Data(19), DI18=>Data(18), + DI17=>Data(17), DI16=>Data(16), DI15=>Data(15), + DI14=>Data(14), DI13=>Data(13), DI12=>Data(12), + DI11=>Data(11), DI10=>Data(10), DI9=>Data(9), DI8=>Data(8), + DI7=>Data(7), DI6=>Data(6), DI5=>Data(5), DI4=>Data(4), + DI3=>Data(3), DI2=>Data(2), DI1=>Data(1), DI0=>Data(0), + ADW8=>scuba_vlo, ADW7=>scuba_vlo, ADW6=>scuba_vlo, + ADW5=>scuba_vlo, ADW4=>wptr_4, ADW3=>wptr_3, ADW2=>wptr_2, + ADW1=>wptr_1, ADW0=>wptr_0, BE3=>scuba_vhi, BE2=>scuba_vhi, + BE1=>scuba_vhi, BE0=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, + CSW2=>scuba_vlo, CSW1=>scuba_vlo, CSW0=>scuba_vhi, + ADR13=>scuba_vlo, ADR12=>scuba_vlo, ADR11=>scuba_vlo, + ADR10=>scuba_vlo, ADR9=>rptr_4, ADR8=>rptr_3, ADR7=>rptr_2, + ADR6=>rptr_1, ADR5=>rptr_0, ADR4=>scuba_vlo, ADR3=>scuba_vlo, + ADR2=>scuba_vlo, ADR1=>scuba_vlo, ADR0=>scuba_vlo, + CER=>scuba_vhi, OCER=>scuba_vhi, CLKR=>Clock, + CSR2=>scuba_vlo, CSR1=>scuba_vlo, CSR0=>rden_i, RST=>Reset, + DO35=>Q(17), DO34=>Q(16), DO33=>Q(15), DO32=>Q(14), + DO31=>Q(13), DO30=>Q(12), DO29=>Q(11), DO28=>Q(10), + DO27=>Q(9), DO26=>Q(8), DO25=>Q(7), DO24=>Q(6), DO23=>Q(5), + DO22=>Q(4), DO21=>Q(3), DO20=>Q(2), DO19=>Q(1), DO18=>Q(0), + DO17=>Q(35), DO16=>Q(34), DO15=>Q(33), DO14=>Q(32), + DO13=>Q(31), DO12=>Q(30), DO11=>Q(29), DO10=>Q(28), + DO9=>Q(27), DO8=>Q(26), DO7=>Q(25), DO6=>Q(24), DO5=>Q(23), + DO4=>Q(22), DO3=>Q(21), DO2=>Q(20), DO1=>Q(19), DO0=>Q(18)); + + FF_38: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_37: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_36: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_35: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_34: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_33: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_32: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_31: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_30: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, + Q=>wcount_0); + + FF_29: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_28: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_27: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_26: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_25: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_24: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, + Q=>rcount_0); + + FF_23: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_22: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_21: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_20: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_19: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_18: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_0); + + FF_17: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_1); + + FF_16: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_2); + + FF_15: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_3); + + FF_14: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_4); + + FF_13: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_5); + + FF_12: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_0); + + FF_11: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_1); + + FF_10: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_2); + + FF_9: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_3); + + FF_8: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_4); + + FF_7: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_5); + + FF_6: FD1S3DX + port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0); + + FF_5: FD1S3DX + port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1); + + FF_4: FD1S3DX + port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2); + + FF_3: FD1S3DX + port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3); + + FF_2: FD1S3DX + port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4); + + FF_1: FD1S3DX + port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5); + + FF_0: FD1S3DX + port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull); + + bdcnt_bctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci); + + bdcnt_bctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0); + + bdcnt_bctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1); + + bdcnt_bctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2); + + e_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci); + + e_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1); + + e_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, + B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1); + + e_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, + B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, + COUT=>cmp_le_1_c); + + a0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, + COUT=>open); + + g_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1); + + g_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2); + + g_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2); + + g_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i_inv, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_2, S0=>open, S1=>open, COUT=>cmp_ge_d1_c); + + a1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, + COUT=>open); + + w_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci); + + w_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, + COUT=>co0_3); + + w_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, + COUT=>co1_3); + + w_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, + COUT=>co2_1); + + r_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci); + + r_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, + COUT=>co0_4); + + r_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, + COUT=>co1_4); + + r_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, + COUT=>co2_2); + + precin_inst218: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", + INIT0=> X"0000") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin); + + wcnt_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5); + + wcnt_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5); + + wcnt_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, COUT=>co2_3); + + wcnt_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_3, S0=>wcnt_sub_5, S1=>open, + COUT=>open); + + af_set_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2); + + af_set_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), + B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, + S1=>open, COUT=>co0_6); + + af_set_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), + B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, + COUT=>co1_6); + + af_set_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, + COUT=>af_set_c); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open, + COUT=>open); + + WCNT(0) <= fcount_0; + WCNT(1) <= fcount_1; + WCNT(2) <= fcount_2; + WCNT(3) <= fcount_3; + WCNT(4) <= fcount_4; + WCNT(5) <= fcount_5; + Empty <= empty_i; + Full <= full_i; +end Structure; diff --git a/lattice/ecp5/FIFO/fifo_36x512_dualport_oreg/fifo_36x512_dualport_oreg.lpc b/lattice/ecp5/FIFO/fifo_36x512_dualport_oreg/fifo_36x512_dualport_oreg.lpc new file mode 100644 index 0000000..c829f03 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x512_dualport_oreg/fifo_36x512_dualport_oreg.lpc @@ -0,0 +1,53 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-45F +PartName=LFE5UM-45F-8BG381C +SpeedGrade=8 +Package=CABGA381 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.8 +ModuleName=fifo_36x512_dualport_oreg +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=08/04/2021 +Time=11:43:07 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=512 +Width=36 +RDepth=512 +RWidth=36 +regout=1 +ClockEn=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Static - Single Threshold +PfAssert=500 +PfDeassert=506 +Reset=Async +Reset1=Sync +RDataCount=0 +WDataCount=0 +EnECC=0 + +[Command] +cmd_line= -w -n fifo_36x512_dualport_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 512 -width 36 -rwidth 36 -regout -no_enable -reset_rel SYNC -pe -1 -pf 500 diff --git a/lattice/ecp5/FIFO/fifo_36x512_dualport_oreg/fifo_36x512_dualport_oreg.vhd b/lattice/ecp5/FIFO/fifo_36x512_dualport_oreg/fifo_36x512_dualport_oreg.vhd new file mode 100644 index 0000000..d523ce1 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_36x512_dualport_oreg/fifo_36x512_dualport_oreg.vhd @@ -0,0 +1,1351 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.11.2.446 +-- Module Version: 5.8 +--/d/jspc29/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x512_dualport_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 512 -width 36 -rwidth 36 -regout -no_enable -reset_rel SYNC -pe -1 -pf 500 -fdc /local/trb/git/trbnet/lattice/ecp5/FIFO/fifo_36x512_dualport_oreg/fifo_36x512_dualport_oreg.fdc + +-- Wed Aug 4 11:43:11 2021 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity fifo_36x512_dualport_oreg is + port ( + Data: in std_logic_vector(35 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(35 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end fifo_36x512_dualport_oreg; + +architecture Structure of fifo_36x512_dualport_oreg is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co4: std_logic; + signal co3: std_logic; + signal wcount_9: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co4_1: std_logic; + signal co3_1: std_logic; + signal rcount_9: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal wcount_r8: std_logic; + signal empty_cmp_clr: std_logic; + signal rcount_8: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal cmp_ci_1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_8: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal iaf_setcount_0: std_logic; + signal iaf_setcount_1: std_logic; + signal af_set_ctr_ci: std_logic; + signal iaf_setcount_2: std_logic; + signal iaf_setcount_3: std_logic; + signal co0_4: std_logic; + signal iaf_setcount_4: std_logic; + signal iaf_setcount_5: std_logic; + signal co1_4: std_logic; + signal iaf_setcount_6: std_logic; + signal iaf_setcount_7: std_logic; + signal co2_4: std_logic; + signal iaf_setcount_8: std_logic; + signal iaf_setcount_9: std_logic; + signal co4_2: std_logic; + signal co3_4: std_logic; + signal af_setcount_9: std_logic; + signal wren_i: std_logic; + signal cmp_ci_2: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal af_setcount_0: std_logic; + signal af_setcount_1: std_logic; + signal co0_5: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal af_setcount_2: std_logic; + signal af_setcount_3: std_logic; + signal co1_5: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal af_setcount_4: std_logic; + signal af_setcount_5: std_logic; + signal co2_5: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w7: std_logic; + signal af_setcount_6: std_logic; + signal af_setcount_7: std_logic; + signal co3_5: std_logic; + signal rcount_w8: std_logic; + signal af_set_cmp_clr: std_logic; + signal af_setcount_8: std_logic; + signal af_set_cmp_set: std_logic; + signal af_set: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + signal af_set_c: std_logic; + + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_36x512_dualport_oreg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t20: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t19: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t18: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t17: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t16: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t15: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t14: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t13: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t12: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t11: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t10: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t9: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t8: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t7: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t6: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t5: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t4: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t3: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t2: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t1: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t0: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>w_gcount_r29, + DO0=>w_g2b_xor_cluster_0); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>w_gcount_r25, + DO0=>w_g2b_xor_cluster_1); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r8); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, + AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>r_gcount_w29, + DO0=>r_g2b_xor_cluster_0); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>r_gcount_w25, + DO0=>r_g2b_xor_cluster_1); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w8); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, + AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0); + + LUT4_5: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_4: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_3: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"4c32") + port map (AD3=>af_setcount_9, AD2=>wcount_9, AD1=>r_gcount_w29, + AD0=>wptr_9, DO0=>af_set_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"8001") + port map (AD3=>af_setcount_9, AD2=>wcount_9, AD1=>r_gcount_w29, + AD0=>wptr_9, DO0=>af_set_cmp_clr); + + pdp_ram_0_0_0: PDPW16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "ENABLED", + RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, + DATA_WIDTH_W=> 36) + port map (DI35=>Data(35), DI34=>Data(34), DI33=>Data(33), + DI32=>Data(32), DI31=>Data(31), DI30=>Data(30), + DI29=>Data(29), DI28=>Data(28), DI27=>Data(27), + DI26=>Data(26), DI25=>Data(25), DI24=>Data(24), + DI23=>Data(23), DI22=>Data(22), DI21=>Data(21), + DI20=>Data(20), DI19=>Data(19), DI18=>Data(18), + DI17=>Data(17), DI16=>Data(16), DI15=>Data(15), + DI14=>Data(14), DI13=>Data(13), DI12=>Data(12), + DI11=>Data(11), DI10=>Data(10), DI9=>Data(9), DI8=>Data(8), + DI7=>Data(7), DI6=>Data(6), DI5=>Data(5), DI4=>Data(4), + DI3=>Data(3), DI2=>Data(2), DI1=>Data(1), DI0=>Data(0), + ADW8=>wptr_8, ADW7=>wptr_7, ADW6=>wptr_6, ADW5=>wptr_5, + ADW4=>wptr_4, ADW3=>wptr_3, ADW2=>wptr_2, ADW1=>wptr_1, + ADW0=>wptr_0, BE3=>scuba_vhi, BE2=>scuba_vhi, BE1=>scuba_vhi, + BE0=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW2=>scuba_vlo, + CSW1=>scuba_vlo, CSW0=>scuba_vhi, ADR13=>rptr_8, + ADR12=>rptr_7, ADR11=>rptr_6, ADR10=>rptr_5, ADR9=>rptr_4, + ADR8=>rptr_3, ADR7=>rptr_2, ADR6=>rptr_1, ADR5=>rptr_0, + ADR4=>scuba_vlo, ADR3=>scuba_vlo, ADR2=>scuba_vlo, + ADR1=>scuba_vlo, ADR0=>scuba_vlo, CER=>scuba_vhi, + OCER=>scuba_vhi, CLKR=>RdClock, CSR2=>scuba_vlo, + CSR1=>scuba_vlo, CSR0=>rden_i, RST=>Reset, DO35=>Q(17), + DO34=>Q(16), DO33=>Q(15), DO32=>Q(14), DO31=>Q(13), + DO30=>Q(12), DO29=>Q(11), DO28=>Q(10), DO27=>Q(9), + DO26=>Q(8), DO25=>Q(7), DO24=>Q(6), DO23=>Q(5), DO22=>Q(4), + DO21=>Q(3), DO20=>Q(2), DO19=>Q(1), DO18=>Q(0), DO17=>Q(35), + DO16=>Q(34), DO15=>Q(33), DO14=>Q(32), DO13=>Q(31), + DO12=>Q(30), DO11=>Q(29), DO10=>Q(28), DO9=>Q(27), + DO8=>Q(26), DO7=>Q(25), DO6=>Q(24), DO5=>Q(23), DO4=>Q(22), + DO3=>Q(21), DO2=>Q(20), DO1=>Q(19), DO0=>Q(18)); + + FF_112: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_111: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_110: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_109: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_108: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_107: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_106: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_105: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_104: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_103: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_102: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_101: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_100: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_99: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_98: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_97: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_96: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_95: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_94: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_93: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_92: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_91: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_90: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_89: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_88: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_87: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_86: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_85: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_84: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_83: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_82: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_81: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_80: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_79: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_78: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_77: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_76: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_75: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_74: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_73: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_72: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_71: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_70: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_69: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_68: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_67: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_66: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_65: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_64: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_63: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_62: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_61: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_60: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_59: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_58: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_57: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_56: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_55: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_54: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_53: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_52: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_51: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_50: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_49: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_48: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_47: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_46: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_45: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_44: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_43: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_42: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_41: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_40: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_39: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_38: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_37: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_36: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_35: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_34: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_33: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_32: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_31: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_30: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_29: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_28: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_27: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_26: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_25: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_24: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_23: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_22: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_21: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_20: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_19: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_18: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_17: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_16: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_15: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_14: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_13: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_12: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_11: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + FF_10: FD1P3BX + port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_0); + + FF_9: FD1P3DX + port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_1); + + FF_8: FD1P3BX + port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_2); + + FF_7: FD1P3BX + port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_3); + + FF_6: FD1P3DX + port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_4); + + FF_5: FD1P3DX + port map (D=>iaf_setcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_5); + + FF_4: FD1P3DX + port map (D=>iaf_setcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_6); + + FF_3: FD1P3DX + port map (D=>iaf_setcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_7); + + FF_2: FD1P3DX + port map (D=>iaf_setcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_8); + + FF_1: FD1P3DX + port map (D=>iaf_setcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_9); + + FF_0: FD1S3DX + port map (D=>af_set, CK=>WrClock, CD=>Reset, Q=>AlmostFull); + + w_gctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_gctr_ci); + + w_gctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>w_gctr_ci, S0=>iwcount_0, S1=>iwcount_1, + COUT=>co0); + + w_gctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0, S0=>iwcount_2, S1=>iwcount_3, + COUT=>co1); + + w_gctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1, S0=>iwcount_4, S1=>iwcount_5, + COUT=>co2); + + w_gctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2, S0=>iwcount_6, S1=>iwcount_7, + COUT=>co3); + + w_gctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3, S0=>iwcount_8, S1=>iwcount_9, + COUT=>co4); + + r_gctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_gctr_ci); + + r_gctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>r_gctr_ci, S0=>ircount_0, S1=>ircount_1, + COUT=>co0_1); + + r_gctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_1, S0=>ircount_2, S1=>ircount_3, + COUT=>co1_1); + + r_gctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_1, S0=>ircount_4, S1=>ircount_5, + COUT=>co2_1); + + r_gctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_1, S0=>ircount_6, S1=>ircount_7, + COUT=>co3_1); + + r_gctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_1, S0=>ircount_8, S1=>ircount_9, + COUT=>co4_1); + + empty_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci); + + empty_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_2); + + empty_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2); + + empty_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2); + + empty_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0, + B1=>wcount_r7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2); + + empty_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8, + B1=>empty_cmp_clr, C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co3_2, S0=>open, S1=>open, + COUT=>empty_d_c); + + a0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>empty_d_c, S0=>empty_d, S1=>open, + COUT=>open); + + full_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1); + + full_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ci_1, S0=>open, S1=>open, + COUT=>co0_3); + + full_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_3, S0=>open, S1=>open, COUT=>co1_3); + + full_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_3, S0=>open, S1=>open, COUT=>co2_3); + + full_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_3, S0=>open, S1=>open, COUT=>co3_3); + + full_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8, + B1=>full_cmp_clr, C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co3_3, S0=>open, S1=>open, + COUT=>full_d_c); + + a1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>full_d_c, S0=>full_d, S1=>open, + COUT=>open); + + af_set_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, + COUT=>af_set_ctr_ci); + + af_set_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>af_set_ctr_ci, S0=>iaf_setcount_0, + S1=>iaf_setcount_1, COUT=>co0_4); + + af_set_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_4, S0=>iaf_setcount_2, + S1=>iaf_setcount_3, COUT=>co1_4); + + af_set_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>af_setcount_4, A1=>af_setcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_4, S0=>iaf_setcount_4, + S1=>iaf_setcount_5, COUT=>co2_4); + + af_set_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>af_setcount_6, A1=>af_setcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_4, S0=>iaf_setcount_6, + S1=>iaf_setcount_7, COUT=>co3_4); + + af_set_ctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>af_setcount_8, A1=>af_setcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_4, S0=>iaf_setcount_8, + S1=>iaf_setcount_9, COUT=>co4_2); + + af_set_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2); + + af_set_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0, + B1=>rcount_w1, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, S1=>open, + COUT=>co0_5); + + af_set_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>rcount_w2, + B1=>rcount_w3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_5, S0=>open, S1=>open, COUT=>co1_5); + + af_set_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>af_setcount_4, A1=>af_setcount_5, B0=>rcount_w4, + B1=>rcount_w5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_5, S0=>open, S1=>open, COUT=>co2_5); + + af_set_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>af_setcount_6, A1=>af_setcount_7, + B0=>r_g2b_xor_cluster_0, B1=>rcount_w7, C0=>scuba_vhi, + C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_5, + S0=>open, S1=>open, COUT=>co3_5); + + af_set_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>af_setcount_8, A1=>af_set_cmp_set, B0=>rcount_w8, + B1=>af_set_cmp_clr, C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co3_5, S0=>open, S1=>open, + COUT=>af_set_c); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open, + COUT=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; diff --git a/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.lpc b/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.lpc index 7366630..38d6e88 100644 --- a/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.lpc +++ b/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.lpc @@ -16,8 +16,8 @@ CoreRevision=5.8 ModuleName=lattice_ecp5_fifo_36x16_dualport_oreg SourceFormat=vhdl ParameterFileVersion=1.0 -Date=06/14/2021 -Time=12:45:48 +Date=07/09/2021 +Time=17:09:39 [Parameters] Verilog=0 @@ -32,7 +32,7 @@ Depth=16 Width=36 RDepth=16 RWidth=36 -regout=0 +regout=1 ClockEn=0 CtrlByRdEn=0 EmpFlg=1 @@ -50,4 +50,4 @@ WDataCount=0 EnECC=0 [Command] -cmd_line= -w -n lattice_ecp5_fifo_36x16_dualport_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 36 -rwidth 36 -reset_rel SYNC -pe 10 -pf 10 +cmd_line= -w -n lattice_ecp5_fifo_36x16_dualport_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 36 -rwidth 36 -regout -no_enable -reset_rel SYNC -pe 10 -pf 10 diff --git a/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.vhd b/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.vhd index dfba1b7..02829a3 100644 --- a/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.vhd +++ b/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.11.2.446 -- Module Version: 5.8 ---/d/jspc29/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n lattice_ecp5_fifo_36x16_dualport_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 36 -rwidth 36 -reset_rel SYNC -pe 10 -pf 10 -fdc /d/jspc22/trb/git/trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.fdc +--/d/jspc29/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n lattice_ecp5_fifo_36x16_dualport_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 36 -rwidth 36 -regout -no_enable -reset_rel SYNC -pe 10 -pf 10 -fdc /local/trb/git/trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.fdc --- Mon Jun 14 12:46:02 2021 +-- Fri Jul 9 17:09:43 2021 library IEEE; use IEEE.std_logic_1164.all; @@ -376,8 +376,8 @@ begin pdp_ram_0_0_0: PDPW16KD generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", - CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "ENABLED", - RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36, + CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "ENABLED", + RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) port map (DI35=>Data(35), DI34=>Data(34), DI33=>Data(33), DI32=>Data(32), DI31=>Data(31), DI30=>Data(30), @@ -399,17 +399,17 @@ begin ADR10=>scuba_vlo, ADR9=>scuba_vlo, ADR8=>rptr_3, ADR7=>rptr_2, ADR6=>rptr_1, ADR5=>rptr_0, ADR4=>scuba_vlo, ADR3=>scuba_vlo, ADR2=>scuba_vlo, ADR1=>scuba_vlo, - ADR0=>scuba_vlo, CER=>rden_i, OCER=>rden_i, CLKR=>RdClock, - CSR2=>scuba_vlo, CSR1=>scuba_vlo, CSR0=>scuba_vlo, - RST=>Reset, DO35=>Q(17), DO34=>Q(16), DO33=>Q(15), - DO32=>Q(14), DO31=>Q(13), DO30=>Q(12), DO29=>Q(11), - DO28=>Q(10), DO27=>Q(9), DO26=>Q(8), DO25=>Q(7), DO24=>Q(6), - DO23=>Q(5), DO22=>Q(4), DO21=>Q(3), DO20=>Q(2), DO19=>Q(1), - DO18=>Q(0), DO17=>Q(35), DO16=>Q(34), DO15=>Q(33), - DO14=>Q(32), DO13=>Q(31), DO12=>Q(30), DO11=>Q(29), - DO10=>Q(28), DO9=>Q(27), DO8=>Q(26), DO7=>Q(25), DO6=>Q(24), - DO5=>Q(23), DO4=>Q(22), DO3=>Q(21), DO2=>Q(20), DO1=>Q(19), - DO0=>Q(18)); + ADR0=>scuba_vlo, CER=>scuba_vhi, OCER=>scuba_vhi, + CLKR=>RdClock, CSR2=>scuba_vlo, CSR1=>scuba_vlo, + CSR0=>rden_i, RST=>Reset, DO35=>Q(17), DO34=>Q(16), + DO33=>Q(15), DO32=>Q(14), DO31=>Q(13), DO30=>Q(12), + DO29=>Q(11), DO28=>Q(10), DO27=>Q(9), DO26=>Q(8), DO25=>Q(7), + DO24=>Q(6), DO23=>Q(5), DO22=>Q(4), DO21=>Q(3), DO20=>Q(2), + DO19=>Q(1), DO18=>Q(0), DO17=>Q(35), DO16=>Q(34), + DO15=>Q(33), DO14=>Q(32), DO13=>Q(31), DO12=>Q(30), + DO11=>Q(29), DO10=>Q(28), DO9=>Q(27), DO8=>Q(26), DO7=>Q(25), + DO6=>Q(24), DO5=>Q(23), DO4=>Q(22), DO3=>Q(21), DO2=>Q(20), + DO1=>Q(19), DO0=>Q(18)); FF_63: FD1P3BX port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, -- 2.43.0