From 440b1f8534f7d50bc66b9075cbaff27efe9bbe2d Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 13 Apr 2011 10:02:11 +0000 Subject: [PATCH] *** empty log message *** --- compile_frankfurt.pl | 1 + design2/trigger_handler.vhd | 21 +++++++++++++++++++-- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/compile_frankfurt.pl b/compile_frankfurt.pl index 75be7a7..47d0638 100755 --- a/compile_frankfurt.pl +++ b/compile_frankfurt.pl @@ -16,6 +16,7 @@ use strict; my $lattice_path = '/d/sugar/lattice/diamond/1.1'; #my $synplify_path = '/d/sugar/lattice/synplify/syn96L3/synplify_linux/'; my $synplify_path = '/d/sugar/lattice/synplify/D-2010.03/'; +#my $synplify_path = '/d/sugar/lattice/synplify/fpga_e201009sp2/'; use FileHandle; diff --git a/design2/trigger_handler.vhd b/design2/trigger_handler.vhd index 8f15ebc..55a49cb 100644 --- a/design2/trigger_handler.vhd +++ b/design2/trigger_handler.vhd @@ -96,6 +96,7 @@ architecture trigger_handle_trg_arch of trigger_handler is signal time_waiting : unsigned(31 downto 0); signal force_reinit : std_logic; + signal doing_calib : std_logic; begin @@ -212,8 +213,14 @@ begin when WAIT_FOR_FINISHED_STORING => if storing_data_is_finished = '1' then - current_state <= RELEASE_LVL1; - lvl1_release_i <= '1'; + if doing_calib = '0' then + current_state <= RELEASE_LVL1; + lvl1_release_i <= '1'; + else + current_state <= TIMING_TRIGGER; + timer_clear <= '1'; + start_trigger_i <= '1'; + end if; end if; when RELEASE_LVL1 => @@ -268,6 +275,16 @@ begin end if; end process; + proc_doing_calib : process(CLK) + begin + if rising_edge(CLK) then + if start_calib_i = '1' then + doing_calib <= '1'; + elsif storing_data_is_finished = '1' then + doing_calib <= '0'; + end if; + end if; + end process; ------------------------------------------------------------------------------- -- I/O -- 2.43.0