From 4496ac236f09a3d81de3145bceb6982dec7d39ec Mon Sep 17 00:00:00 2001 From: Manuel Penschuck Date: Mon, 3 Mar 2014 17:41:17 +0100 Subject: [PATCH] THIS RELEASE MAY BREAK HARD-CODED REGISTER MAPPINGS. PLEASE CHECK YOUR CONFIGS especially related to addon input. - unified input multiplexer (inputs from trb3 rj45 jacks + cts-addon are now treaded the same way) - added "any" line for several input jacks - included trigger input from peripheral fpga - included output mux that can select any itc/input and map them to the addon-outputs --- cts/compile_central_frankfurt.pl | 16 ++++--- cts/source/cts.vhd | 6 +-- cts/source/cts_pkg.vhd | 21 ++++----- cts/source/cts_trigger.vhd | 74 ++++++++++++++++---------------- cts/trb3_central.vhd | 15 +++---- 5 files changed, 61 insertions(+), 71 deletions(-) mode change 100755 => 100644 cts/trb3_central.vhd diff --git a/cts/compile_central_frankfurt.pl b/cts/compile_central_frankfurt.pl index 7d32701..81eecdb 100755 --- a/cts/compile_central_frankfurt.pl +++ b/cts/compile_central_frankfurt.pl @@ -2,7 +2,7 @@ use Data::Dumper; use warnings; use strict; - +use Term::ANSIColor; @@ -60,7 +60,7 @@ if(defined $ENV{'LPF_ONLY'} and $ENV{'LPF_ONLY'} == 1) {exit;} #set -o errexit #generate timestamp -my $t=time; +my $t=sprintf "%08x", time; my $fh = new FileHandle(">version.vhd"); die "could not open file" if (! defined $fh); print $fh < '0'); ADDON_GROUP_SELECTED_OUT : out std_logic_vector(ADDON_GROUPS-1 downto 0) := (others => '0'); - PERIPH_TRIGGER_IN : in std_logic_vector(3 downto 0) := (others => '0'); + PERIPH_TRIGGER_IN : in std_logic_vector(19 downto 0) := (others => '0'); OUTPUT_MULTIPLEXERS_OUT : out std_logic_vector(OUTPUT_MULTIPLEXERS-1 downto 0); - OUTPUT_EXTRA_INPUTS_IN : in std_logic_vector(max(0, OUTPUT_EXTRA_INPUTS-1) downto 0) := (others => '0'); -- External trigger logic EXT_TRIGGER_IN : in std_logic; @@ -742,7 +740,6 @@ begin PERIPH_TRIGGER_COUNT => PERIPH_TRIGGER_COUNT, OUTPUT_MULTIPLEXERS => OUTPUT_MULTIPLEXERS, - OUTPUT_EXTRA_INPUTS => OUTPUT_EXTRA_INPUTS, TRIGGER_ADDON_COUNT => TRIGGER_ADDON_COUNT, EXTERNAL_TRIGGER_ID => EXTERNAL_TRIGGER_ID @@ -760,7 +757,6 @@ begin PERIPH_TRIGGER_IN => PERIPH_TRIGGER_IN, OUTPUT_MULTIPLEXERS_OUT => OUTPUT_MULTIPLEXERS_OUT, - OUTPUT_EXTRA_INPUTS_IN => OUTPUT_EXTRA_INPUTS_IN, EXT_TRIGGER_IN => EXT_TRIGGER_IN, EXT_STATUS_IN => EXT_STATUS_IN, diff --git a/cts/source/cts_pkg.vhd b/cts/source/cts_pkg.vhd index b69569c..355b2fe 100755 --- a/cts/source/cts_pkg.vhd +++ b/cts/source/cts_pkg.vhd @@ -11,22 +11,20 @@ package cts_pkg is component CTS is generic ( -- The total number of trigger units below has to be below 16 - TRIGGER_INPUT_COUNT : integer range 0 to 8 := 4; - TRIGGER_COIN_COUNT : integer range 0 to 15 := 3; + TRIGGER_INPUT_COUNT : integer range 0 to 8 := 4; + TRIGGER_COIN_COUNT : integer range 0 to 15 := 2; TRIGGER_PULSER_COUNT: integer range 0 to 15 := 4; TRIGGER_RAND_PULSER : integer range 0 to 15 := 1; + TRIGGER_ADDON_COUNT : integer range 0 to 15 := 2; -- number of module instances used to patch through those lines + PERIPH_TRIGGER_COUNT: integer range 0 to 15 := 2; + ADDON_GROUPS : integer range 1 to 8 := 5; ADDON_LINE_COUNT : integer range 0 to 255 := 22; -- number of lines available from add-on board - TRIGGER_ADDON_COUNT : integer range 0 to 15 := 2; -- number of module instances used to patch through those lines - ADDON_GROUPS : integer range 1 to 8 := 5; ADDON_GROUP_UPPER : CTS_GROUP_CONFIG_T := (3,7,11,12,13, others=>'0'); - PERIPH_TRIGGER_COUNT: integer range 0 to 1 := 1; OUTPUT_MULTIPLEXERS : integer range 0 to 255 := 0; - OUTPUT_EXTRA_INPUTS : integer range 0 to 255 := 0; - EXTERNAL_TRIGGER_ID : std_logic_vector(7 downto 0) := X"00"; TIME_REFERENCE_COUNT: positive := 10; -- Number of clock cycles the time reference needs to stay asserted (100ns) @@ -46,10 +44,9 @@ package cts_pkg is ADDON_GROUP_ACTIVITY_OUT : out std_logic_vector(ADDON_GROUPS-1 downto 0) := (others => '0'); ADDON_GROUP_SELECTED_OUT : out std_logic_vector(ADDON_GROUPS-1 downto 0) := (others => '0'); - PERIPH_TRIGGER_IN : in std_logic_vector(3 downto 0) := (others => '0'); + PERIPH_TRIGGER_IN : in std_logic_vector(19 downto 0) := (others => '0'); OUTPUT_MULTIPLEXERS_OUT : out std_logic_vector(OUTPUT_MULTIPLEXERS-1 downto 0); - OUTPUT_EXTRA_INPUTS_IN : in std_logic_vector(max(0, OUTPUT_EXTRA_INPUTS-1) downto 0) := (others => '0'); -- External trigger logic EXT_TRIGGER_IN : in std_logic; @@ -187,10 +184,9 @@ package cts_pkg is ADDON_GROUPS : integer range 1 to 8 := 5; ADDON_GROUP_UPPER : CTS_GROUP_CONFIG_T := (3,7,11,12,13, others=>'0'); - PERIPH_TRIGGER_COUNT: integer range 0 to 1 := 1; + PERIPH_TRIGGER_COUNT: integer range 0 to 15 := 2; OUTPUT_MULTIPLEXERS : integer range 0 to 255 := 0; - OUTPUT_EXTRA_INPUTS : integer range 0 to 255 := 0; EXTERNAL_TRIGGER_ID : std_logic_vector(7 downto 0) := X"00" ); @@ -206,10 +202,9 @@ package cts_pkg is ADDON_GROUP_ACTIVITY_OUT : out std_logic_vector(ADDON_GROUPS-1 downto 0) := (others => '0'); ADDON_GROUP_SELECTED_OUT : out std_logic_vector(ADDON_GROUPS-1 downto 0) := (others => '0'); - PERIPH_TRIGGER_IN : in std_logic_vector(3 downto 0) := (others => '0'); + PERIPH_TRIGGER_IN : in std_logic_vector(19 downto 0) := (others => '0'); OUTPUT_MULTIPLEXERS_OUT : out std_logic_vector(OUTPUT_MULTIPLEXERS-1 downto 0); - OUTPUT_EXTRA_INPUTS_IN : in std_logic_vector(max(0, OUTPUT_EXTRA_INPUTS-1) downto 0) := (others => '0'); -- External EXT_TRIGGER_IN : in std_logic; diff --git a/cts/source/cts_trigger.vhd b/cts/source/cts_trigger.vhd index 4f5ac6e..a8aa9f5 100755 --- a/cts/source/cts_trigger.vhd +++ b/cts/source/cts_trigger.vhd @@ -18,10 +18,9 @@ entity CTS_TRIGGER is ADDON_GROUPS : integer range 1 to 8 := 5; ADDON_GROUP_UPPER : CTS_GROUP_CONFIG_T := (3,7,11,12,13, others=>'0'); - PERIPH_TRIGGER_COUNT: integer range 0 to 1 := 1; + PERIPH_TRIGGER_COUNT: integer range 0 to 15 := 1; OUTPUT_MULTIPLEXERS : integer range 0 to 255 := 0; - OUTPUT_EXTRA_INPUTS : integer range 0 to 255 := 0; EXTERNAL_TRIGGER_ID : std_logic_vector(7 downto 0) := X"00" ); @@ -38,10 +37,9 @@ entity CTS_TRIGGER is ADDON_GROUP_ACTIVITY_OUT : out std_logic_vector(ADDON_GROUPS-1 downto 0) := (others => '0'); ADDON_GROUP_SELECTED_OUT : out std_logic_vector(ADDON_GROUPS-1 downto 0) := (others => '0'); - PERIPH_TRIGGER_IN : in std_logic_vector(3 downto 0) := (others => '0'); + PERIPH_TRIGGER_IN : in std_logic_vector(19 downto 0) := (others => '0'); OUTPUT_MULTIPLEXERS_OUT : out std_logic_vector(OUTPUT_MULTIPLEXERS-1 downto 0); - OUTPUT_EXTRA_INPUTS_IN : in std_logic_vector(max(0, OUTPUT_EXTRA_INPUTS-1) downto 0) := (others => '0'); -- External EXT_TRIGGER_IN : in std_logic; @@ -123,22 +121,23 @@ architecture RTL of CTS_TRIGGER is signal trigger_input_edge_counters_i : trigger_input_counters_t; -- Coincidence Detection - type coin_config_t is array(TRIGGER_COIN_COUNT - 1 downto 0) of std_logic_vector(31 downto 0); + type coin_config_t is array(MAX(0, TRIGGER_COIN_COUNT - 1) downto 0) of std_logic_vector(31 downto 0); signal coin_config_i : coin_config_t; -- TRIGGER_PULSER_COUNT - type pulser_interval_t is array(TRIGGER_PULSER_COUNT - 1 downto 0) of std_logic_vector(31 downto 0); + type pulser_interval_t is array(MAX(0, TRIGGER_PULSER_COUNT - 1) downto 0) of std_logic_vector(31 downto 0); signal pulser_interval_i : pulser_interval_t; signal pulser_counter_i : pulser_interval_t := (others => (others => '0')); signal pulser_1us_i : std_logic; -- Random Pulser - type rand_pulser_threshold_t is array(TRIGGER_RAND_PULSER - 1 downto 0) of std_logic_vector(31 downto 0); + type rand_pulser_threshold_t is array(MAX(0, TRIGGER_RAND_PULSER - 1) downto 0) of std_logic_vector(31 downto 0); signal rand_pulser_threshold_i : rand_pulser_threshold_t := (others => (others => '0')); -- Peripheral Trigger Inputs - signal periph_trigger_mask_i : std_logic_vector(3 downto 0) := (others => '0'); + type periph_trigger_mask_t is array(MAX(0, PERIPH_TRIGGER_COUNT - 1) downto 0) of std_logic_vector(19 downto 0); + signal periph_trigger_mask_i : periph_trigger_mask_t; -- Add On type trigger_addon_configs_t is array(TRIGGER_ADDON_COUNT - 1 downto 0) of std_logic_vector(7 downto 0); @@ -146,9 +145,9 @@ architecture RTL of CTS_TRIGGER is signal addon_group_activity_i : std_logic_vector(ADDON_GROUPS-1 downto 0) := (others => '0'); signal addon_group_selected_i : std_logic_vector(ADDON_GROUPS-1 downto 0) := (others => '0'); - type output_multiplexer_configs_t is array(OUTPUT_MULTIPLEXERS - 1 downto 0) of std_logic_vector(7 downto 0); + type output_multiplexer_configs_t is array(MAX(0,OUTPUT_MULTIPLEXERS - 1) downto 0) of std_logic_vector(7 downto 0); signal output_multiplexer_configs_i : output_multiplexer_configs_t; - signal output_multiplexer_ins_i : std_logic_vector(16 + 2*TRIGGER_INPUT_COUNT + ADDON_LINE_COUNT + TRIGGER_ADDON_COUNT + OUTPUT_EXTRA_INPUTS - 1 downto 0); + signal output_multiplexer_ins_i : std_logic_vector(16 + 2*TRIGGER_INPUT_COUNT + ADDON_LINE_COUNT + TRIGGER_ADDON_COUNT - 1 downto 0); -- Trigger Type Assoc type trigger_type_assoc_t is array(0 to 15) of std_logic_vector(3 downto 0); @@ -172,7 +171,7 @@ begin end if; end process; - proc_addon_multi: process(CLK_IN) is + proc_addon_mux: process(CLK_IN) is begin if rising_edge(CLK_IN) then for i in 0 to TRIGGER_ADDON_COUNT - 1 loop @@ -186,8 +185,8 @@ begin channels_i(ITC_BASE_EXT) <= EXT_TRIGGER_IN; end generate; - proc_output_multi_ins: process(channels_i, TRIGGERS_IN, ADDON_TRIGGERS_IN, trigger_inputs_i, - OUTPUT_EXTRA_INPUTS_IN, output_multiplexer_configs_i) is + proc_output_mux_ins: process(channels_i, TRIGGERS_IN, ADDON_TRIGGERS_IN, trigger_inputs_i, + output_multiplexer_configs_i) is variable i : integer := 0; begin i := 0; @@ -207,14 +206,9 @@ begin output_multiplexer_ins_i(trigger_inputs_i'high + i downto i) <= trigger_inputs_i; i := i + EFFECTIVE_INPUT_COUNT; - - if OUTPUT_EXTRA_INPUTS > 0 then - output_multiplexer_ins_i(OUTPUT_EXTRA_INPUTS + i - 1 downto i) <= OUTPUT_EXTRA_INPUTS_IN; - i := i + OUTPUT_EXTRA_INPUTS; - end if; end process; - proc_out_multi: process(output_multiplexer_ins_i, output_multiplexer_configs_i) is + proc_out_mux: process(output_multiplexer_ins_i, output_multiplexer_configs_i) is variable tmp : integer range 0 to 255 := 0; variable idx : integer range 0 to output_multiplexer_ins_i'high := 0; variable test : std_logic_vector(31 downto 0); @@ -262,7 +256,9 @@ begin proc_periph: process(CLK_IN) is begin if rising_edge(clk_in) and PERIPH_TRIGGER_COUNT > 0 then - channels_i(ITC_BASE_PERIPH) <= OR_ALL( periph_trigger_mask_i and PERIPH_TRIGGER_IN ); + for i in 0 to PERIPH_TRIGGER_COUNT - 1 loop + channels_i(ITC_BASE_PERIPH + i) <= OR_ALL( periph_trigger_mask_i(i) and PERIPH_TRIGGER_IN ); + end loop; end if; end process; @@ -578,7 +574,7 @@ begin REGIO_UNKNOWN_ADDR_OUT <= REGIO_WRITE_ENABLE_IN; REGIO_DATAREADY_OUT <= REGIO_READ_ENABLE_IN; REGIO_DATA_OUT <= CTS_BLOCK_HEADER( - id => 16#12#, + id => 16#15#, len => TRIGGER_ADDON_COUNT, itc_base => ITC_BASE_INPUTS + TRIGGER_INPUT_COUNT, itc_num => TRIGGER_ADDON_COUNT @@ -604,7 +600,7 @@ begin end loop; end if; --- OUTPUT MULTIPLEXER MODULE +-- OUTPUT MULTIPLEXER MODULE (important: has to appear AFTER type 0x10 and 0x12/0x15 in order to compute the length of the bitmasks correctly) if OUTPUT_MULTIPLEXERS > 0 then if addr = ref_addr then REGIO_UNKNOWN_ADDR_OUT <= REGIO_WRITE_ENABLE_IN; @@ -636,33 +632,35 @@ begin end loop; end if; --- PERIPH TRIGGER +-- PERIPH TRIGGER if PERIPH_TRIGGER_COUNT > 0 then if addr = ref_addr then REGIO_UNKNOWN_ADDR_OUT <= REGIO_WRITE_ENABLE_IN; REGIO_DATAREADY_OUT <= REGIO_READ_ENABLE_IN; REGIO_DATA_OUT <= CTS_BLOCK_HEADER( - id => 16#13#, - len => 1, + id => 16#14#, + len => PERIPH_TRIGGER_COUNT, itc_base => ITC_BASE_PERIPH, - itc_num => 1 + itc_num => PERIPH_TRIGGER_COUNT ); end if; ref_addr := ref_addr + 1; - if addr=ref_addr then - REGIO_UNKNOWN_ADDR_OUT <= '0'; - REGIO_DATAREADY_OUT <= REGIO_READ_ENABLE_IN; - REGIO_WRITE_ACK_OUT <= REGIO_WRITE_ENABLE_IN; - - REGIO_DATA_OUT <= (others => '0'); - REGIO_DATA_OUT(periph_trigger_mask_i'range) <= periph_trigger_mask_i; - - if REGIO_WRITE_ENABLE_IN = '1' then - periph_trigger_mask_i <= REGIO_DATA_IN(periph_trigger_mask_i'range); + for i in 0 to PERIPH_TRIGGER_COUNT-1 loop + if addr=ref_addr then + REGIO_UNKNOWN_ADDR_OUT <= '0'; + REGIO_DATAREADY_OUT <= REGIO_READ_ENABLE_IN; + REGIO_WRITE_ACK_OUT <= REGIO_WRITE_ENABLE_IN; + + REGIO_DATA_OUT <= (others => '0'); + REGIO_DATA_OUT(periph_trigger_mask_i(i)'range) <= periph_trigger_mask_i(i); + + if REGIO_WRITE_ENABLE_IN = '1' then + periph_trigger_mask_i(i) <= REGIO_DATA_IN(periph_trigger_mask_i(i)'range); + end if; end if; - end if; - ref_addr := ref_addr + 1; + ref_addr := ref_addr + 1; + end loop; end if; -- TRIGGER_PULSER_COUNT CONFIGURATION diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd old mode 100755 new mode 100644 index 52d6959..daf1578 --- a/cts/trb3_central.vhd +++ b/cts/trb3_central.vhd @@ -334,10 +334,10 @@ architecture trb3_central_arch of trb3_central is signal cts_addon_activity_i, cts_addon_selected_i : std_logic_vector(6 downto 0); - signal cts_periph_trigger_i : std_logic_vector(3 downto 0); + signal cts_periph_trigger_i : std_logic_vector(19 downto 0); signal cts_output_multiplexers_i : std_logic_vector(CTS_OUTPUT_MULTIPLEXERS - 1 downto 0); - signal cts_output_extra_inputs_i : std_logic_vector(CTS_OUTPUT_INPUTS - 1 downto 0); + signal cts_periph_lines_i : std_logic_vector(CTS_OUTPUT_INPUTS - 1 downto 0); signal cts_trg_send : std_logic; signal cts_trg_type : std_logic_vector(3 downto 0); @@ -493,10 +493,9 @@ begin TRIGGER_INPUT_COUNT => 0, -- now all inputs are routed via an input multiplexer! TRIGGER_ADDON_COUNT => 6, - PERIPH_TRIGGER_COUNT => 1, + PERIPH_TRIGGER_COUNT => 2, OUTPUT_MULTIPLEXERS => CTS_OUTPUT_MULTIPLEXERS, - OUTPUT_EXTRA_INPUTS => CTS_OUTPUT_INPUTS, ADDON_LINE_COUNT => CTS_ADDON_LINE_COUNT, ADDON_GROUPS => 7, @@ -522,7 +521,6 @@ begin PERIPH_TRIGGER_IN => cts_periph_trigger_i, OUTPUT_MULTIPLEXERS_OUT => cts_output_multiplexers_i, - OUTPUT_EXTRA_INPUTS_IN => cts_output_extra_inputs_i, CTS_TRG_SEND_OUT => cts_trg_send, CTS_TRG_TYPE_OUT => cts_trg_type, @@ -593,9 +591,10 @@ begin others => '0' ); - cts_periph_trigger_i <= FPGA4_COMM(10) & FPGA3_COMM(10) & FPGA2_COMM(10) & FPGA1_COMM(10); - - cts_output_extra_inputs_i <= FPGA4_COMM(7 downto 4) & FPGA3_COMM(7 downto 4) & FPGA2_COMM(7 downto 4) & FPGA1_COMM(7 downto 4); + cts_periph_trigger_i <= FPGA4_COMM(10) & FPGA4_COMM(7 downto 4) + & FPGA3_COMM(10) & FPGA3_COMM(7 downto 4) + & FPGA2_COMM(10) & FPGA2_COMM(7 downto 4) + & FPGA1_COMM(10) & FPGA1_COMM(7 downto 4); JOUT1 <= cts_output_multiplexers_i(3 downto 0); JOUT2 <= cts_output_multiplexers_i(7 downto 4); -- 2.43.0